[PATCH 39/40] staging: comedi: me4000: remove me4000.h

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Move the remaining defines in this header to the c file. Nothing
in the header is needed by any other file.

While moving the defines, reorder them so that the bit defines
are associated with the register they go with. Also, convert the
bit defines to bit shifts to make them a bit clearer.

Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx>
Cc: Ian Abbott <abbotti@xxxxxxxxx>
Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
 drivers/staging/comedi/drivers/me4000.c | 140 ++++++++++++++++++-
 drivers/staging/comedi/drivers/me4000.h | 231 --------------------------------
 2 files changed, 139 insertions(+), 232 deletions(-)
 delete mode 100644 drivers/staging/comedi/drivers/me4000.h

diff --git a/drivers/staging/comedi/drivers/me4000.c b/drivers/staging/comedi/drivers/me4000.c
index 6247ee3..bb724b1 100644
--- a/drivers/staging/comedi/drivers/me4000.c
+++ b/drivers/staging/comedi/drivers/me4000.c
@@ -53,7 +53,7 @@ broken.
 #include <linux/spinlock.h>
 
 #include "8253.h"
-#include "me4000.h"
+
 #if 0
 /* file removed due to GPL incompatibility */
 #include "me4000_fw.h"
@@ -75,6 +75,144 @@ broken.
 #define PCI_DEVICE_ID_MEILHAUS_ME4680S	0x4682
 #define PCI_DEVICE_ID_MEILHAUS_ME4680IS	0x4683
 
+/*
+ * ME4000 Register map and bit defines
+ */
+#define ME4000_AO_CHAN(x)			((x) * 0x18)
+
+#define ME4000_AO_CTRL_REG(x)			(0x00 + ME4000_AO_CHAN(x))
+#define ME4000_AO_CTRL_BIT_MODE_0		(1 << 0)
+#define ME4000_AO_CTRL_BIT_MODE_1		(1 << 1)
+#define ME4000_AO_CTRL_MASK_MODE		(3 << 0)
+#define ME4000_AO_CTRL_BIT_STOP			(1 << 2)
+#define ME4000_AO_CTRL_BIT_ENABLE_FIFO		(1 << 3)
+#define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG	(1 << 4)
+#define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE		(1 << 5)
+#define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP	(1 << 7)
+#define ME4000_AO_CTRL_BIT_ENABLE_DO		(1 << 8)
+#define ME4000_AO_CTRL_BIT_ENABLE_IRQ		(1 << 9)
+#define ME4000_AO_CTRL_BIT_RESET_IRQ		(1 << 10)
+#define ME4000_AO_STATUS_REG(x)			(0x04 + ME4000_AO_CHAN(x))
+#define ME4000_AO_STATUS_BIT_FSM		(1 << 0)
+#define ME4000_AO_STATUS_BIT_FF			(1 << 1)
+#define ME4000_AO_STATUS_BIT_HF			(1 << 2)
+#define ME4000_AO_STATUS_BIT_EF			(1 << 3)
+#define ME4000_AO_FIFO_REG(x)			(0x08 + ME4000_AO_CHAN(x))
+#define ME4000_AO_SINGLE_REG(x)			(0x0c + ME4000_AO_CHAN(x))
+#define ME4000_AO_TIMER_REG(x)			(0x10 + ME4000_AO_CHAN(x))
+#define ME4000_AI_CTRL_REG			0x74
+#define ME4000_AI_STATUS_REG			0x74
+#define ME4000_AI_CTRL_BIT_MODE_0		(1 << 0)
+#define ME4000_AI_CTRL_BIT_MODE_1		(1 << 1)
+#define ME4000_AI_CTRL_BIT_MODE_2		(1 << 2)
+#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD		(1 << 3)
+#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP	(1 << 4)
+#define ME4000_AI_CTRL_BIT_STOP			(1 << 5)
+#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO		(1 << 6)
+#define ME4000_AI_CTRL_BIT_DATA_FIFO		(1 << 7)
+#define ME4000_AI_CTRL_BIT_FULLSCALE		(1 << 8)
+#define ME4000_AI_CTRL_BIT_OFFSET		(1 << 9)
+#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG	(1 << 10)
+#define ME4000_AI_CTRL_BIT_EX_TRIG		(1 << 11)
+#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING	(1 << 12)
+#define ME4000_AI_CTRL_BIT_EX_IRQ		(1 << 13)
+#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET		(1 << 14)
+#define ME4000_AI_CTRL_BIT_LE_IRQ		(1 << 15)
+#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET		(1 << 16)
+#define ME4000_AI_CTRL_BIT_HF_IRQ		(1 << 17)
+#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET		(1 << 18)
+#define ME4000_AI_CTRL_BIT_SC_IRQ		(1 << 19)
+#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET		(1 << 20)
+#define ME4000_AI_CTRL_BIT_SC_RELOAD		(1 << 21)
+#define ME4000_AI_STATUS_BIT_EF_CHANNEL		(1 << 22)
+#define ME4000_AI_STATUS_BIT_HF_CHANNEL		(1 << 23)
+#define ME4000_AI_STATUS_BIT_FF_CHANNEL		(1 << 24)
+#define ME4000_AI_STATUS_BIT_EF_DATA		(1 << 25)
+#define ME4000_AI_STATUS_BIT_HF_DATA		(1 << 26)
+#define ME4000_AI_STATUS_BIT_FF_DATA		(1 << 27)
+#define ME4000_AI_STATUS_BIT_LE			(1 << 28)
+#define ME4000_AI_STATUS_BIT_FSM		(1 << 29)
+#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH		(1 << 31)
+#define ME4000_AI_CHANNEL_LIST_REG		0x78
+#define ME4000_AI_LIST_INPUT_SINGLE_ENDED	(0 << 5)
+#define ME4000_AI_LIST_INPUT_DIFFERENTIAL	(1 << 5)
+#define ME4000_AI_LIST_RANGE_BIPOLAR_10		(0 << 6)
+#define ME4000_AI_LIST_RANGE_BIPOLAR_2_5	(1 << 6)
+#define ME4000_AI_LIST_RANGE_UNIPOLAR_10	(2 << 6)
+#define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5	(3 << 6)
+#define ME4000_AI_LIST_LAST_ENTRY		(1 << 8)
+#define ME4000_AI_DATA_REG			0x7c
+#define ME4000_AI_CHAN_TIMER_REG		0x80
+#define ME4000_AI_CHAN_PRE_TIMER_REG		0x84
+#define ME4000_AI_SCAN_TIMER_LOW_REG		0x88
+#define ME4000_AI_SCAN_TIMER_HIGH_REG		0x8c
+#define ME4000_AI_SCAN_PRE_TIMER_LOW_REG	0x90
+#define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG	0x94
+#define ME4000_AI_START_REG			0x98
+#define ME4000_IRQ_STATUS_REG			0x9c
+#define ME4000_IRQ_STATUS_BIT_EX		(1 << 0)
+#define ME4000_IRQ_STATUS_BIT_LE		(1 << 1)
+#define ME4000_IRQ_STATUS_BIT_AI_HF		(1 << 2)
+#define ME4000_IRQ_STATUS_BIT_AO_0_HF		(1 << 3)
+#define ME4000_IRQ_STATUS_BIT_AO_1_HF		(1 << 4)
+#define ME4000_IRQ_STATUS_BIT_AO_2_HF		(1 << 5)
+#define ME4000_IRQ_STATUS_BIT_AO_3_HF		(1 << 6)
+#define ME4000_IRQ_STATUS_BIT_SC		(1 << 7)
+#define ME4000_DIO_PORT_0_REG			0xa0
+#define ME4000_DIO_PORT_1_REG			0xa4
+#define ME4000_DIO_PORT_2_REG			0xa8
+#define ME4000_DIO_PORT_3_REG			0xac
+#define ME4000_DIO_DIR_REG			0xb0
+#define ME4000_AO_LOADSETREG_XX			0xb4
+#define ME4000_DIO_CTRL_REG			0xb8
+#define ME4000_DIO_CTRL_BIT_MODE_0		(1 << 0)
+#define ME4000_DIO_CTRL_BIT_MODE_1		(1 << 1)
+#define ME4000_DIO_CTRL_BIT_MODE_2		(1 << 2)
+#define ME4000_DIO_CTRL_BIT_MODE_3		(1 << 3)
+#define ME4000_DIO_CTRL_BIT_MODE_4		(1 << 4)
+#define ME4000_DIO_CTRL_BIT_MODE_5		(1 << 5)
+#define ME4000_DIO_CTRL_BIT_MODE_6		(1 << 6)
+#define ME4000_DIO_CTRL_BIT_MODE_7		(1 << 7)
+#define ME4000_DIO_CTRL_BIT_FUNCTION_0		(1 << 8)
+#define ME4000_DIO_CTRL_BIT_FUNCTION_1		(1 << 9)
+#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0		(1 << 10)
+#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1		(1 << 11)
+#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2		(1 << 12)
+#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3		(1 << 13)
+#define ME4000_AO_DEMUX_ADJUST_REG		0xbc
+#define ME4000_AO_DEMUX_ADJUST_VALUE		0x4c
+#define ME4000_AI_SAMPLE_COUNTER_REG		0xc0
+
+/*
+ * PLX Register map and bit defines
+ */
+#define PLX_INTCSR				0x4c
+#define PLX_INTCSR_LOCAL_INT1_EN		(1 << 0)
+#define PLX_INTCSR_LOCAL_INT1_POL		(1 << 1)
+#define PLX_INTCSR_LOCAL_INT1_STATE		(1 << 2)
+#define PLX_INTCSR_LOCAL_INT2_EN		(1 << 3)
+#define PLX_INTCSR_LOCAL_INT2_POL		(1 << 4)
+#define PLX_INTCSR_LOCAL_INT2_STATE		(1 << 5)
+#define PLX_INTCSR_PCI_INT_EN			(1 << 6)
+#define PLX_INTCSR_SOFT_INT			(1 << 7)
+#define PLX_ICR					0x50
+#define PLX_ICR_BIT_EEPROM_CLOCK_SET		(1 << 24)
+#define PLX_ICR_BIT_EEPROM_CHIP_SELECT		(1 << 25)
+#define PLX_ICR_BIT_EEPROM_WRITE		(1 << 26)
+#define PLX_ICR_BIT_EEPROM_READ			(1 << 27)
+#define PLX_ICR_BIT_EEPROM_VALID		(1 << 28)
+#define PLX_ICR_MASK_EEPROM			(0x1f << 24)
+
+#define EEPROM_DELAY				1
+
+#define ME4000_AI_FIFO_COUNT			2048
+
+#define ME4000_AI_MIN_TICKS			66
+#define ME4000_AI_MIN_SAMPLE_TIME		2000
+#define ME4000_AI_BASE_FREQUENCY		(unsigned int) 33E6
+
+#define ME4000_AI_CHANNEL_LIST_COUNT		1024
+
 struct me4000_info {
 	unsigned long plx_regbase;
 	unsigned long timer_regbase;
diff --git a/drivers/staging/comedi/drivers/me4000.h b/drivers/staging/comedi/drivers/me4000.h
deleted file mode 100644
index 2478933..0000000
--- a/drivers/staging/comedi/drivers/me4000.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
-    me4000.h
-    Register descriptions and defines for the ME-4000 board family
-
-    COMEDI - Linux Control and Measurement Device Interface
-    Copyright (C) 1998-9 David A. Schleef <ds@xxxxxxxxxxx>
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-*/
-
-#ifndef _ME4000_H_
-#define _ME4000_H_
-
-/*=============================================================================
-  ME-4000 base register offsets
-  ===========================================================================*/
-
-#define ME4000_AO_CHAN(x)			((x) * 0x18)
-
-#define ME4000_AO_CTRL_REG(x)			(0x00 + ME4000_AO_CHAN(x))
-#define ME4000_AO_STATUS_REG(x)			(0x04 + ME4000_AO_CHAN(x))
-#define ME4000_AO_FIFO_REG(x)			(0x08 + ME4000_AO_CHAN(x))
-#define ME4000_AO_SINGLE_REG(x)			(0x0c + ME4000_AO_CHAN(x))
-#define ME4000_AO_TIMER_REG(x)			(0x10 + ME4000_AO_CHAN(x))
-
-#define ME4000_AI_CTRL_REG			0x74	/*  _/W */
-#define ME4000_AI_STATUS_REG			0x74	/*  R/_ */
-#define ME4000_AI_CHANNEL_LIST_REG		0x78	/*  _/W */
-#define ME4000_AI_DATA_REG			0x7C	/*  R/_ */
-#define ME4000_AI_CHAN_TIMER_REG		0x80	/*  _/W */
-#define ME4000_AI_CHAN_PRE_TIMER_REG		0x84	/*  _/W */
-#define ME4000_AI_SCAN_TIMER_LOW_REG		0x88	/*  _/W */
-#define ME4000_AI_SCAN_TIMER_HIGH_REG		0x8C	/*  _/W */
-#define ME4000_AI_SCAN_PRE_TIMER_LOW_REG	0x90	/*  _/W */
-#define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG	0x94	/*  _/W */
-#define ME4000_AI_START_REG			0x98	/*  R/_ */
-
-#define ME4000_IRQ_STATUS_REG			0x9C	/*  R/_ */
-
-#define ME4000_DIO_PORT_0_REG			0xA0	/*  R/W */
-#define ME4000_DIO_PORT_1_REG			0xA4	/*  R/W */
-#define ME4000_DIO_PORT_2_REG			0xA8	/*  R/W */
-#define ME4000_DIO_PORT_3_REG			0xAC	/*  R/W */
-#define ME4000_DIO_DIR_REG			0xB0	/*  R/W */
-
-#define ME4000_AO_LOADSETREG_XX			0xB4	/*  R/W */
-
-#define ME4000_DIO_CTRL_REG			0xB8	/*  R/W */
-
-#define ME4000_AO_DEMUX_ADJUST_REG		0xBC	/*  -/W */
-
-#define ME4000_AI_SAMPLE_COUNTER_REG		0xC0	/*  _/W */
-
-/*=============================================================================
-  Value to adjust Demux
-  ===========================================================================*/
-
-#define ME4000_AO_DEMUX_ADJUST_VALUE            0x4C
-
-/*=============================================================================
-  PLX base register offsets
-  ===========================================================================*/
-
-#define PLX_INTCSR	0x4C	/*  Interrupt control and status register */
-#define PLX_ICR		0x50	/*  Initialization control register */
-
-/*=============================================================================
-  Bits for the PLX_ICSR register
-  ===========================================================================*/
-
-#define PLX_INTCSR_LOCAL_INT1_EN             0x01	/*  If set, local interrupt 1 is enabled (r/w) */
-#define PLX_INTCSR_LOCAL_INT1_POL            0x02	/*  If set, local interrupt 1 polarity is active high (r/w) */
-#define PLX_INTCSR_LOCAL_INT1_STATE          0x04	/*  If set, local interrupt 1 is active (r/_) */
-#define PLX_INTCSR_LOCAL_INT2_EN             0x08	/*  If set, local interrupt 2 is enabled (r/w) */
-#define PLX_INTCSR_LOCAL_INT2_POL            0x10	/*  If set, local interrupt 2 polarity is active high (r/w) */
-#define PLX_INTCSR_LOCAL_INT2_STATE          0x20	/*  If set, local interrupt 2 is active  (r/_) */
-#define PLX_INTCSR_PCI_INT_EN                0x40	/*  If set, PCI interrupt is enabled (r/w) */
-#define PLX_INTCSR_SOFT_INT                  0x80	/*  If set, a software interrupt is generated (r/w) */
-
-/*=============================================================================
-  Bits for the PLX_ICR register
-  ===========================================================================*/
-
-#define PLX_ICR_BIT_EEPROM_CLOCK_SET		0x01000000
-#define PLX_ICR_BIT_EEPROM_CHIP_SELECT		0x02000000
-#define PLX_ICR_BIT_EEPROM_WRITE		0x04000000
-#define PLX_ICR_BIT_EEPROM_READ			0x08000000
-#define PLX_ICR_BIT_EEPROM_VALID		0x10000000
-
-#define PLX_ICR_MASK_EEPROM			0x1F000000
-
-#define EEPROM_DELAY				1
-
-/*=============================================================================
-  Bits for the ME4000_AO_CTRL_REG register
-  ===========================================================================*/
-
-#define ME4000_AO_CTRL_BIT_MODE_0		0x001
-#define ME4000_AO_CTRL_BIT_MODE_1		0x002
-#define ME4000_AO_CTRL_MASK_MODE		0x003
-#define ME4000_AO_CTRL_BIT_STOP			0x004
-#define ME4000_AO_CTRL_BIT_ENABLE_FIFO		0x008
-#define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG	0x010
-#define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE		0x020
-#define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP	0x080
-#define ME4000_AO_CTRL_BIT_ENABLE_DO		0x100
-#define ME4000_AO_CTRL_BIT_ENABLE_IRQ		0x200
-#define ME4000_AO_CTRL_BIT_RESET_IRQ		0x400
-
-/*=============================================================================
-  Bits for the ME4000_AO_STATUS_REG register
-  ===========================================================================*/
-
-#define ME4000_AO_STATUS_BIT_FSM		0x01
-#define ME4000_AO_STATUS_BIT_FF			0x02
-#define ME4000_AO_STATUS_BIT_HF			0x04
-#define ME4000_AO_STATUS_BIT_EF			0x08
-
-/*=============================================================================
-  Bits for the ME4000_AI_CTRL_REG register
-  ===========================================================================*/
-
-#define ME4000_AI_CTRL_BIT_MODE_0		0x00000001
-#define ME4000_AI_CTRL_BIT_MODE_1		0x00000002
-#define ME4000_AI_CTRL_BIT_MODE_2		0x00000004
-#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD		0x00000008
-#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP	0x00000010
-#define ME4000_AI_CTRL_BIT_STOP			0x00000020
-#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO		0x00000040
-#define ME4000_AI_CTRL_BIT_DATA_FIFO		0x00000080
-#define ME4000_AI_CTRL_BIT_FULLSCALE		0x00000100
-#define ME4000_AI_CTRL_BIT_OFFSET		0x00000200
-#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG	0x00000400
-#define ME4000_AI_CTRL_BIT_EX_TRIG		0x00000800
-#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING	0x00001000
-#define ME4000_AI_CTRL_BIT_EX_IRQ		0x00002000
-#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET		0x00004000
-#define ME4000_AI_CTRL_BIT_LE_IRQ		0x00008000
-#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET		0x00010000
-#define ME4000_AI_CTRL_BIT_HF_IRQ		0x00020000
-#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET		0x00040000
-#define ME4000_AI_CTRL_BIT_SC_IRQ		0x00080000
-#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET		0x00100000
-#define ME4000_AI_CTRL_BIT_SC_RELOAD		0x00200000
-#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH		0x80000000
-
-/*=============================================================================
-  Bits for the ME4000_AI_STATUS_REG register
-  ===========================================================================*/
-
-#define ME4000_AI_STATUS_BIT_EF_CHANNEL		0x00400000
-#define ME4000_AI_STATUS_BIT_HF_CHANNEL		0x00800000
-#define ME4000_AI_STATUS_BIT_FF_CHANNEL		0x01000000
-#define ME4000_AI_STATUS_BIT_EF_DATA		0x02000000
-#define ME4000_AI_STATUS_BIT_HF_DATA		0x04000000
-#define ME4000_AI_STATUS_BIT_FF_DATA		0x08000000
-#define ME4000_AI_STATUS_BIT_LE			0x10000000
-#define ME4000_AI_STATUS_BIT_FSM		0x20000000
-
-/*=============================================================================
-  Bits for the ME4000_IRQ_STATUS_REG register
-  ===========================================================================*/
-
-#define ME4000_IRQ_STATUS_BIT_EX		0x01
-#define ME4000_IRQ_STATUS_BIT_LE		0x02
-#define ME4000_IRQ_STATUS_BIT_AI_HF		0x04
-#define ME4000_IRQ_STATUS_BIT_AO_0_HF		0x08
-#define ME4000_IRQ_STATUS_BIT_AO_1_HF		0x10
-#define ME4000_IRQ_STATUS_BIT_AO_2_HF		0x20
-#define ME4000_IRQ_STATUS_BIT_AO_3_HF		0x40
-#define ME4000_IRQ_STATUS_BIT_SC		0x80
-
-/*=============================================================================
-  Bits for the ME4000_DIO_CTRL_REG register
-  ===========================================================================*/
-
-#define ME4000_DIO_CTRL_BIT_MODE_0		0x0001
-#define ME4000_DIO_CTRL_BIT_MODE_1		0x0002
-#define ME4000_DIO_CTRL_BIT_MODE_2		0x0004
-#define ME4000_DIO_CTRL_BIT_MODE_3		0x0008
-#define ME4000_DIO_CTRL_BIT_MODE_4		0x0010
-#define ME4000_DIO_CTRL_BIT_MODE_5		0x0020
-#define ME4000_DIO_CTRL_BIT_MODE_6		0x0040
-#define ME4000_DIO_CTRL_BIT_MODE_7		0x0080
-
-#define ME4000_DIO_CTRL_BIT_FUNCTION_0		0x0100
-#define ME4000_DIO_CTRL_BIT_FUNCTION_1		0x0200
-
-#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0		0x0400
-#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1		0x0800
-#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2		0x1000
-#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3		0x2000
-
-/*-----------------------------------------------------------------------------
-  Defines for analog input
- ----------------------------------------------------------------------------*/
-
-/* General stuff */
-#define ME4000_AI_FIFO_COUNT			2048
-
-#define ME4000_AI_MIN_TICKS			66
-#define ME4000_AI_MIN_SAMPLE_TIME		2000	/*  Minimum sample time [ns] */
-#define ME4000_AI_BASE_FREQUENCY		(unsigned int) 33E6
-
-/* Channel list defines and masks */
-#define ME4000_AI_CHANNEL_LIST_COUNT		1024
-
-#define ME4000_AI_LIST_INPUT_SINGLE_ENDED	0x000
-#define ME4000_AI_LIST_INPUT_DIFFERENTIAL	0x020
-
-#define ME4000_AI_LIST_RANGE_BIPOLAR_10		0x000
-#define ME4000_AI_LIST_RANGE_BIPOLAR_2_5	0x040
-#define ME4000_AI_LIST_RANGE_UNIPOLAR_10	0x080
-#define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5	0x0C0
-
-#define ME4000_AI_LIST_LAST_ENTRY		0x100
-
-#endif
-- 
1.7.11

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