The mite_io_addr and daq_io_addr variables in struct mite_struct
are both ioremap'ed pci resources and should be void __iomem *
not void *.
This quiets a lot of sparse warings for the write[lwb],read[lwb]
calls in the comedi mite drives like:
warning: incorrect type in argument 1 (different address spaces)
expected void const volatile [noderef] <asn:2>*addr
got void *<noident>
warning: incorrect type in argument 2 (different address spaces)
expected void volatile [noderef] <asn:2>*addr
got void *
It also exposed some warnings in the mite ni_660x driver where
the daq_io_address was getting cast as a void *const.
Signed-off-by: H Hartley Sweeten <hsweeten@xxxxxxxxxxxxxxxxxxx>
Cc: Ian Abbott <abbotti@xxxxxxxxx>
Cc: Mori Hess <fmhess@xxxxxxxxxxxxxxxxxxxxx>
Cc: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
diff --git a/drivers/staging/comedi/drivers/mite.h b/drivers/staging/comedi/drivers/mite.h
index 999551f..83f1b27 100644
--- a/drivers/staging/comedi/drivers/mite.h
+++ b/drivers/staging/comedi/drivers/mite.h
@@ -66,9 +66,9 @@ struct mite_struct {
struct pci_dev *pcidev;
resource_size_t mite_phys_addr;
- void *mite_io_addr;
+ void __iomem *mite_io_addr;
resource_size_t daq_phys_addr;
- void *daq_io_addr;
+ void __iomem *daq_io_addr;
struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
short channel_allocated[MAX_MITE_DMA_CHANNELS];
diff --git a/drivers/staging/comedi/drivers/ni_660x.c b/drivers/staging/comedi/drivers/ni_660x.c
index eea7047..21eb7fb 100644
--- a/drivers/staging/comedi/drivers/ni_660x.c
+++ b/drivers/staging/comedi/drivers/ni_660x.c
@@ -761,7 +761,7 @@ static inline void ni_660x_write_register(struct comedi_device *dev,
unsigned chip_index, unsigned bits,
enum NI_660x_Register reg)
{
- void *const write_address =
+ void __iomem *write_address =
private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
registerData[reg].offset;
@@ -784,7 +784,7 @@ static inline unsigned ni_660x_read_register(struct comedi_device *dev,
unsigned chip_index,
enum NI_660x_Register reg)
{
- void *const read_address =
+ void __iomem *read_address =
private(dev)->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
registerData[reg].offset;
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