On Thursday 19 April 2012 11:22 PM, Grant Grundler wrote:
On Thu, Apr 19, 2012 at 4:15 AM, Laxman Dewangan<ldewangan@xxxxxxxxxx> wrote:
Using regmap for accessing register through i2c bus. This will
remove the code for caching registers, read-modify-write logics.
Also it will provide the debugfs feature to dump register
through regmap debugfs.
Signed-off-by: Laxman Dewangan<ldewangan@xxxxxxxxxx>
Reviewed-by: Grant Grundler<grundler@xxxxxxxxxxxx>
Laxman,
Thanks for reposting this patch. I was talking with Bryan Freed and it
looks like the caching of registers will change the usage of
ADD_COMMAND1. More details below.
Thanks for review. ADD_COMMAND1 have the intrrupt flag bit. More
details below.
+static bool is_volatile_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case ISL29018_REG_ADD_DATA_LSB:
+ case ISL29018_REG_ADD_DATA_MSB:
+ case ISL29018_REG_ADD_COMMAND1:
+ case ISL29018_REG_TEST:
Of these four, I think only ADD_COMMAND1 wasn't treated as volatile in
the old code. Am I overlooking something?
My concern is only about the additional I2C read traffic this patch
might generate. It's possible *some* bits in that register are
volatile and we could previously ignore them.
Register ADD_COMMAND1, bit 2 is interrupt flag bit which shows the
interrupt status and hence we can not cache it.
The ISL29018 datasheet says:
Interrupt flag; Bit 2. This is the status bit of the interrupt.
The bit is set to logic high when the interrupt thresholds
have been triggered, and logic low when not yet triggered.
Once triggered, INT pin stays low and the status bit stays
high. Both interrupt pin and the status bit are automatically
cleared at the end of Command Register I transfer.
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