On Mon, Mar 15, 2021 at 12:37 PM Zhengxun Li <zhengxunli.mxic@xxxxxxxxx> wrote:
>
> Hi Shubhrajyoti,
>
> My name is Zhengxun and I am the engineer from Macronix. We are
> using the platform PicoZed 7015/7030 SOM (System On Module),
> which is based on Xilinx Zynq®-7000 All Programmable (AP) SoC to
> verify our Flash driver. Of course, we are also using your clock
> wizard, our version seems to be v5.2, but something went wrong.
>
> +static int clk_wzrd_dynamic_reconfig(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + int err;
> + u32 value;
> + unsigned long flags = 0;
> + struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
> + void __iomem *div_addr = divider->base + divider->offset;
> +
> + if (divider->lock)
> + spin_lock_irqsave(divider->lock, flags);
> + else
> + __acquire(divider->lock);
> +
> + value = DIV_ROUND_CLOSEST(parent_rate, rate);
> +
> + /* Cap the value to max */
> + min_t(u32, value, WZRD_DR_MAX_INT_DIV_VALUE);
> +
> + /* Set divisor and clear phase offset */
> + writel(value, div_addr);
> + writel(0x00, div_addr + WZRD_DR_DIV_TO_PHASE_OFFSET);
>
> Why phase always set to zero? We want to support DTR operation in
> Flash driver. Can you add a set_phase function to adjust the phase?
>
The phase setting is a separate feature will address in a separate series.
>
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