On Thu, Feb 18, 2021 at 08:07:05AM +0100, Sergio Paracuellos wrote: > Adds device tree binding documentation for clocks in the > MT7621 SOC. > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx> > --- > .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++++++++++++++++++ > 1 file changed, 66 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > new file mode 100644 > index 000000000000..842a0f2c9d40 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MT7621 Clock Device Tree Bindings > + > +maintainers: > + - Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx> > + > +description: | > + The MT7621 has a PLL controller from where the cpu clock is provided > + as well as derived clocks for the bus and the peripherals. It also > + can gate SoC device clocks. > + > + Each clock is assigned an identifier and client nodes use this identifier > + to specify the clock which they consume. > + > + All these identifiers could be found in: > + [1]: <include/dt-bindings/clock/mt7621-clk.h>. > + > +properties: > + compatible: > + const: mediatek,mt7621-clk > + > + "#clock-cells": > + description: > + The first cell indicates the clock number, see [1] for available > + clocks. > + const: 1 > + > + ralink,sysctl: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandle of syscon used to control system registers > + > + ralink,memctl: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: > + phandle of syscon used to control memory registers I assume one of these phandles are the main registers for the clocks? Make this a child node and drop that phandle. > + > + clock-output-names: > + maxItems: 8 > + > +required: > + - compatible > + - '#clock-cells' > + - ralink,sysctl > + - ralink,memctl > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt7621-clk.h> > + > + pll { > + compatible = "mediatek,mt7621-clk"; > + #clock-cells = <1>; > + ralink,sysctl = <&sysc>; > + ralink,memctl = <&memc>; > + clock-output-names = "xtal", "cpu", "bus", > + "50m", "125m", "150m", > + "250m", "270m"; > + }; > -- > 2.25.1 > _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
