Decoders hardware blocks could exist in multiple versions: add
a field to distinguish them at runtime.
Keep the default behavoir to be G1 hardware.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxxxxx>
Signed-off-by: Ezequiel Garcia <ezequiel@xxxxxxxxxxxxx>
Signed-off-by: Adrian Ratiu <adrian.ratiu@xxxxxxxxxxxxx>
---
drivers/staging/media/hantro/hantro.h | 5 +++++
drivers/staging/media/hantro/hantro_drv.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h
index bde65231f22f..2a566dfc2fe3 100644
--- a/drivers/staging/media/hantro/hantro.h
+++ b/drivers/staging/media/hantro/hantro.h
@@ -36,6 +36,9 @@ struct hantro_codec_ops;
#define HANTRO_H264_DECODER BIT(18)
#define HANTRO_DECODERS 0xffff0000
+#define HANTRO_G1_REV 0x6731
+#define HANTRO_G2_REV 0x6732
+
/**
* struct hantro_irq - irq handler and name
*
@@ -170,6 +173,7 @@ hantro_vdev_to_func(struct video_device *vdev)
* @enc_base: Mapped address of VPU encoder register for convenience.
* @dec_base: Mapped address of VPU decoder register for convenience.
* @ctrl_base: Mapped address of VPU control block.
+ * @core_hw_dec_rev Runtime detected HW decoder core revision
* @vpu_mutex: Mutex to synchronize V4L2 calls.
* @irqlock: Spinlock to synchronize access to data structures
* shared with interrupt handlers.
@@ -189,6 +193,7 @@ struct hantro_dev {
void __iomem *enc_base;
void __iomem *dec_base;
void __iomem *ctrl_base;
+ u32 core_hw_dec_rev;
struct mutex vpu_mutex; /* video_device lock */
spinlock_t irqlock;
diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c
index 0570047c7fa0..e1443c394f62 100644
--- a/drivers/staging/media/hantro/hantro_drv.c
+++ b/drivers/staging/media/hantro/hantro_drv.c
@@ -840,6 +840,8 @@ static int hantro_probe(struct platform_device *pdev)
}
vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
+ /* by default decoder is G1 */
+ vpu->core_hw_dec_rev = HANTRO_G1_REV;
ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
if (ret) {
--
2.25.1
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