On Fri, Dec 25, 2020 at 07:02:15PM +0800, Xin Ji wrote:
> +static int anx7625_aux_dpcd_read(struct anx7625_data *ctx,
> + u8 addrh, u8 addrm, u8 addrl,
> + u8 len, u8 *buf)
> +{
> + struct device *dev = &ctx->client->dev;
> + int ret;
> + u8 cmd;
> +
> + if (len > MAX_DPCD_BUFFER_SIZE) {
> + DRM_DEV_ERROR(dev, "exceed aux buffer len.\n");
> + return -E2BIG;
s/E2BIG/EINVAL/. -E2BIG means something else.
> + }
> +
> + cmd = ((len - 1) << 4) | 0x09;
> +
> + /* Set command and length */
> + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> + AP_AUX_COMMAND, cmd);
> +
> + /* Set aux access address */
> + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> + AP_AUX_ADDR_7_0, addrl);
> + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> + AP_AUX_ADDR_15_8, addrm);
> + ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
> + AP_AUX_ADDR_19_16, addrh);
> +
> + /* Enable aux access */
> + ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
> + AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
> +
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "cannot access aux related register.\n");
> + return -EIO;
> + }
> +
> + usleep_range(2000, 2100);
> +
> + ret = wait_aux_op_finish(ctx);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "aux IO error: wait aux op finish.\n");
> + return ret;
> + }
> +
> + ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
> + AP_AUX_BUFF_START, len, buf);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "read dpcd register failed\n");
> + return -EIO;
> }
>
> - return val;
> + return 0;
> }
>
> static int anx7625_video_mute_control(struct anx7625_data *ctx,
> @@ -595,6 +663,101 @@ static int anx7625_dsi_config(struct anx7625_data *ctx)
> return ret;
> }
>
> +static int anx7625_api_dpi_config(struct anx7625_data *ctx)
> +{
> + struct device *dev = &ctx->client->dev;
> + u16 freq = ctx->dt.pixelclock.min / 1000;
> + int ret;
> +
> + /* configure pixel clock */
> + ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> + PIXEL_CLOCK_L, freq & 0xFF);
> + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
> + PIXEL_CLOCK_H, (freq >> 8));
> +
> + /* set DPI mode */
> + /* set to DPI PLL module sel */
> + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
> + MIPI_DIGITAL_PLL_9, 0x20);
> + /* power down MIPI */
> + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
> + MIPI_LANE_CTRL_10, 0x08);
> + /* enable DPI mode */
> + ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
> + MIPI_DIGITAL_PLL_18, 0x1C);
> + /* set first edge */
> + ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
> + VIDEO_CONTROL_0, 0x06);
> + if (ret < 0)
> + DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n");
> +
> + return ret;
> +}
> +
> +static int anx7625_dpi_config(struct anx7625_data *ctx)
> +{
> + struct device *dev = &ctx->client->dev;
> + int ret;
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n");
> +
> + /* DSC disable */
> + ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
> + R_DSC_CTRL_0, ~DSC_EN);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n");
> + return ret;
> + }
> +
> + ret = anx7625_config_bit_matrix(ctx);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "config bit matrix failed.\n");
> + return ret;
> + }
> +
> + ret = anx7625_api_dpi_config(ctx);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n");
> + return ret;
> + }
> +
> + /* set MIPI RX EN */
> + ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
> + AP_AV_STATUS, AP_MIPI_RX_EN);
> + /* clear mute flag */
> + ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
> + AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
> + if (ret < 0)
> + DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
> +
> + return ret;
> +}
> +
> +static int anx7625_hdcp_setting(struct anx7625_data *ctx)
> +{
> + u8 bcap;
> + struct device *dev = &ctx->client->dev;
> +
> + if (!(ctx->hdcp_support && ctx->hdcp_en)) {
Push the ! in and remove the parentheses.
if (!ctx->hdcp_support || !ctx->hdcp_en) {
> + DRM_DEV_DEBUG_DRIVER(dev, "hdcp_support(%d), hdcp_en(%d)\n",
> + ctx->hdcp_support, ctx->hdcp_en);
> + DRM_DEV_DEBUG_DRIVER(dev, "disable HDCP by config\n");
> + return anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
> + 0xee, 0x9f);
> + }
> +
> + anx7625_aux_dpcd_read(ctx, 0x06, 0x80, 0x28, 1, &bcap);
> + if (!(bcap & 0x01)) {
> + DRM_WARN("downstream not support HDCP 1.4, cap(%x).\n", bcap);
> + return anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
> + 0xee, 0x9f);
> + }
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "enable HDCP 1.4\n");
> +
> + return anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
> +}
> +
> static void anx7625_dp_start(struct anx7625_data *ctx)
> {
> int ret;
> @@ -605,9 +768,15 @@ static void anx7625_dp_start(struct anx7625_data *ctx)
> return;
> }
>
> + /* HDCP config */
> + anx7625_hdcp_setting(ctx);
> +
> anx7625_config_audio_input(ctx);
>
> - ret = anx7625_dsi_config(ctx);
> + if (ctx->pdata.is_dpi)
> + ret = anx7625_dpi_config(ctx);
> + else
> + ret = anx7625_dsi_config(ctx);
>
> if (ret < 0)
> DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
> @@ -688,8 +857,53 @@ static int sp_tx_get_edid_block(struct anx7625_data *ctx)
> return c;
> }
>
> -static int edid_read(struct anx7625_data *ctx,
> - u8 offset, u8 *pblock_buf)
> +static int check_hdcp_support(struct anx7625_data *ctx)
> +{
> + int ret;
> + struct device *dev = &ctx->client->dev;
> +
> + /* Select HDCP1.4 Key load */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, FLASH_SRAM_SEL, 0x12);
> + /* Select flash addr low byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, FLASH_ADDR_LOW, 0x91);
> + /* Select flash addr high byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, FLASH_ADDR_HIGH, 0xa0);
> + /* Select sram length high byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, SRAM_LEN_HIGH, 0x00);
> + /* Select sram length low byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, SRAM_LEN_LOW, 0x27);
> + /* Select flash length high byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, FLASH_LEN_HIGH, 0x02);
> + /* Select flash length low byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, FLASH_LEN_LOW, 0x70);
> + /* Select sram addr high byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, SRAM_ADDR_HIGH, 0x00);
> + /* Select sram addr low byte */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, SRAM_ADDR_LOW, 0x00);
> + /* Enable load with decrypt_en */
> + anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, FLASH_LOAD_STA, 0x03);
> +
> + usleep_range(10000, 11000);
> +
> + /* Check load status */
> + ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, FLASH_LOAD_STA);
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "IO error : access flash load.\n");
> + return ret;
> + }
> +
> + if ((ret & 0xF2) != 0xF2) {
> + ctx->hdcp_support = 0;
> + DRM_DEV_DEBUG_DRIVER(dev, "not support HDCP\n");
> + } else {
> + ctx->hdcp_support = 1;
> + DRM_DEV_DEBUG_DRIVER(dev, "support HDCP\n");
> + }
> +
> + return 0;
> +}
> +
> +static int edid_read(struct anx7625_data *ctx, u8 offset, u8 *pblock_buf)
> {
> int ret, cnt;
> struct device *dev = &ctx->client->dev;
> @@ -718,6 +932,15 @@ static int edid_read(struct anx7625_data *ctx,
> return 0;
> }
>
> +void hdcp_enable(struct anx7625_data *ctx, int en)
> +{
> + struct device *dev = &ctx->client->dev;
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "en(%d)\n", en);
> +
> + ctx->hdcp_en = !!en;
> +}
> +
> static int segments_edid_read(struct anx7625_data *ctx,
> u8 segment, u8 *buf, u8 offset)
> {
> @@ -992,8 +1215,10 @@ static void anx7625_chip_control(struct anx7625_data *ctx, int state)
>
> if (state) {
> atomic_inc(&ctx->power_status);
> - if (atomic_read(&ctx->power_status) == 1)
> + if (atomic_read(&ctx->power_status) == 1) {
> anx7625_power_on_init(ctx);
> + check_hdcp_support(ctx);
> + }
> } else {
> if (atomic_read(&ctx->power_status)) {
> atomic_dec(&ctx->power_status);
> @@ -1051,6 +1276,7 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx)
> return;
> }
>
> + ctx->hpd_status = 1;
> ctx->hpd_high_cnt++;
>
> /* Not support HDCP */
> @@ -1060,8 +1286,10 @@ static void anx7625_start_dp_work(struct anx7625_data *ctx)
> ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
> /* Interrupt for DRM */
> ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
> - if (ret < 0)
> + if (ret < 0) {
> + DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n");
> return;
> + }
>
> ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
> if (ret < 0)
> @@ -1080,6 +1308,10 @@ static void anx7625_hpd_polling(struct anx7625_data *ctx)
> int ret, val;
> struct device *dev = &ctx->client->dev;
>
> + /* Interrupt mode, no need poll HPD status, just return */
> + if (ctx->pdata.intp_irq)
> + return;
> +
> if (atomic_read(&ctx->power_status) != 1) {
> DRM_DEV_DEBUG_DRIVER(dev, "No need to poling HPD status.\n");
> return;
> @@ -1130,6 +1362,22 @@ static void anx7625_remove_edid(struct anx7625_data *ctx)
> ctx->slimport_edid_p.edid_block_num = -1;
> }
>
> +static void anx7625_dp_adjust_swing(struct anx7625_data *ctx)
> +{
> + struct device *dev = &ctx->client->dev;
> + int i;
> +
> + if (!ctx->pdata.reg_table_size)
> + return;
No need for this check. Just remove it and the for loop becomes a no-op.
> +
> + DRM_DEV_DEBUG_DRIVER(dev, "adjust DP tx swing\n");
Delete this debug statement and use ftrace for this information.
> +
> + for (i = 0; i < ctx->pdata.reg_table_size; i++)
> + anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
> + ctx->pdata.art[i].offset & 0xFF,
> + ctx->pdata.art[i].data & 0xFF);
> +}
> +
> static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
> {
> struct device *dev = &ctx->client->dev;
> @@ -1145,9 +1393,8 @@ static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
> } else {
> DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n");
> anx7625_start_dp_work(ctx);
> + anx7625_dp_adjust_swing(ctx);
> }
> -
> - ctx->hpd_status = 1;
> }
>
> static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
> @@ -1224,12 +1471,63 @@ static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data)
> return IRQ_HANDLED;
> }
>
> +static int anx7625_get_u32_value(struct device_node *np,
> + const char *name,
> + int start_pos,
> + int *reg_data)
> +{
> + int i, ret;
> +
> + /* each slot has 2 cells */
> + for (i = 0; i < 2; i++) {
> + ret = of_property_read_u32_index(np, name,
> + start_pos + i,
> + ®_data[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> static int anx7625_parse_dt(struct device *dev,
> struct anx7625_platform_data *pdata)
> {
> struct device_node *np = dev->of_node;
> struct drm_panel *panel;
> - int ret;
> + int ret, i;
> + int reg_data[2];
> + int total_size, num_regs, start_pos;
> +
> + if (of_get_property(dev->of_node, "anx,swing-setting", &total_size)) {
> + /* each slot has 2 cells */
> + num_regs = total_size / (sizeof(u32) * 2);
> + if (num_regs > MAX_REG_SIZE)
> + num_regs = MAX_REG_SIZE;
> +
> + pdata->reg_table_size = num_regs;
> +
> + for (i = 0; i < num_regs; i++) {
> + start_pos = i * 2;
> + ret = anx7625_get_u32_value(np, "anx,swing-setting",
> + start_pos, reg_data);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "get swing-setting at %d\n",
> + start_pos);
> + return -ENODEV;
return ret;?
regards,
dan carpenter
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