[PATCH 1/5] brcm80211: use native PCI register offsets

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Signed-off-by: Stanislav Fomichev <kernel@xxxxxxxxxxx>
---
 drivers/staging/brcm80211/include/pcicfg.h |   34 +--------------------------
 drivers/staging/brcm80211/util/nicpci.c    |    6 ++--
 drivers/staging/brcm80211/util/siutils.c   |    5 ++-
 3 files changed, 8 insertions(+), 37 deletions(-)

diff --git a/drivers/staging/brcm80211/include/pcicfg.h b/drivers/staging/brcm80211/include/pcicfg.h
index a3569e4..860121f 100644
--- a/drivers/staging/brcm80211/include/pcicfg.h
+++ b/drivers/staging/brcm80211/include/pcicfg.h
@@ -17,6 +17,8 @@
 #ifndef	_h_pcicfg_
 #define	_h_pcicfg_
 
+#include <linux/pci_regs.h>
+
 /* The actual config space */
 
 #define	PCI_BAR_MAX		6
@@ -56,38 +58,6 @@ typedef struct _pci_config_regs {
 #define	SZPCR		(sizeof (pci_config_regs))
 #define	MINSZPCR	64	/* offsetof (dev_dep[0] */
 
-/* A structure for the config registers is nice, but in most
- * systems the config space is not memory mapped, so we need
- * field offsetts. :-(
- */
-#define	PCI_CFG_VID		0
-#define	PCI_CFG_DID		2
-#define	PCI_CFG_CMD		4
-#define	PCI_CFG_STAT		6
-#define	PCI_CFG_REV		8
-#define	PCI_CFG_PROGIF		9
-#define	PCI_CFG_SUBCL		0xa
-#define	PCI_CFG_BASECL		0xb
-#define	PCI_CFG_CLSZ		0xc
-#define	PCI_CFG_LATTIM		0xd
-#define	PCI_CFG_HDR		0xe
-#define	PCI_CFG_BIST		0xf
-#define	PCI_CFG_BAR0		0x10
-#define	PCI_CFG_BAR1		0x14
-#define	PCI_CFG_BAR2		0x18
-#define	PCI_CFG_BAR3		0x1c
-#define	PCI_CFG_BAR4		0x20
-#define	PCI_CFG_BAR5		0x24
-#define	PCI_CFG_CIS		0x28
-#define	PCI_CFG_SVID		0x2c
-#define	PCI_CFG_SSID		0x2e
-#define	PCI_CFG_ROMBAR		0x30
-#define PCI_CFG_CAPPTR		0x34
-#define	PCI_CFG_INT		0x3c
-#define	PCI_CFG_PIN		0x3d
-#define	PCI_CFG_MINGNT		0x3e
-#define	PCI_CFG_MAXLAT		0x3f
-
 /* Classes and subclasses */
 
 /* Header types */
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
index a1fb2f0..d603452 100644
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ b/drivers/staging/brcm80211/util/nicpci.c
@@ -130,16 +130,16 @@ pcicore_find_pci_capability(void *dev, u8 req_cap_id,
 	u8 byte_val;
 
 	/* check for Header type 0 */
-	pci_read_config_byte(dev, PCI_CFG_HDR, &byte_val);
+	pci_read_config_byte(dev, PCI_HEADER_TYPE, &byte_val);
 	if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
 		goto end;
 
 	/* check if the capability pointer field exists */
-	pci_read_config_byte(dev, PCI_CFG_STAT, &byte_val);
+	pci_read_config_byte(dev, PCI_STATUS, &byte_val);
 	if (!(byte_val & PCI_CAPPTR_PRESENT))
 		goto end;
 
-	pci_read_config_byte(dev, PCI_CFG_CAPPTR, &cap_ptr);
+	pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
 	/* check if the capability pointer is 0x00 */
 	if (cap_ptr == 0x00)
 		goto end;
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
index e88a7bb..29b6fa7 100644
--- a/drivers/staging/brcm80211/util/siutils.c
+++ b/drivers/staging/brcm80211/util/siutils.c
@@ -312,7 +312,8 @@ static __used void si_nvram_process(si_info_t *sii, char *pvars)
 	switch (sii->pub.bustype) {
 	case PCI_BUS:
 		/* do a pci config read to get subsystem id and subvendor id */
-		pci_read_config_dword(sii->pbus, PCI_CFG_SVID, &w);
+		pci_read_config_dword(sii->pbus, PCI_SUBSYSTEM_VENDOR_ID,
+				      &w);
 		/* Let nvram variables override subsystem Vend/ID */
 		sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
 			"boardvendor");
@@ -1864,7 +1865,7 @@ bool si_deviceremoved(si_t *sih)
 	switch (sih->bustype) {
 	case PCI_BUS:
 		ASSERT(sii->pbus != NULL);
-		pci_read_config_dword(sii->pbus, PCI_CFG_VID, &w);
+		pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
 		if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
 			return true;
 		break;
-- 
1.7.1

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