Hi Rob,
On Mon, Nov 16, 2020 at 8:16 PM Rob Herring <robh@xxxxxxxxxx> wrote:
>
> On Wed, 11 Nov 2020 17:30:08 +0100, Sergio Paracuellos wrote:
> > Adds device tree binding documentation for PLL controller in
> > the MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
> > ---
> > .../bindings/clock/mediatek,mt7621-pll.yaml | 51 +++++++++++++++++++
> > 1 file changed, 51 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.yaml
> >
>
> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Thanks for the review. In that series there were two clock bindings
relating the pll and gates, There were finally joined in only one
binding and driver. This is done in the v3 of this series sent on
friday. Thanks for your time in looking also into this new version,
Best regards,
Sergio Paracuellos
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