Function 'mt7621_pci_parse_request_of_pci_ranges' is using
'of_pci_range_to_resource' to get both mem and io resources.
Internally this function calls to 'pci_address_to_pio' which
returns -1 if io space address is an address > IO_SPACE_LIMIT
which is 0xFFFF for mips. This mt7621 soc has io space in physical
address 0x1e160000. In order to fix this, overwrite invalid io
0xffffffff with properly values from the device tree and set
mapped address of this resource as io port base memory address
calling 'set_io_port_base' function. There is also need to properly
setup resource limits and io and memory windows with properly
parsed values instead of set them as 'no limit' which it is wrong.
For any reason I don't really know legacy driver sets up mem window
as 0xFFFFFFFF and any other value seems to does not work as expected,
so set up also here with same values.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
---
Io resources seems to be ok with this changes (tested on gnubee PC1):
[ 16.629599] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
[ 16.640715] mt7621-pci-phy 1e149000.pcie-phy: Xtal is 40MHz
[ 16.651828] mt7621-pci-phy 1e14a000.pcie-phy: Xtal is 40MHz
[ 16.762828] mt7621-pci 1e140000.pcie: PCIE0 enabled
[ 16.772546] mt7621-pci 1e140000.pcie: PCIE1 enabled
[ 16.782263] mt7621-pci 1e140000.pcie: PCIE2 enabled
[ 16.791990] mt7621-pci 1e140000.pcie: PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
[ 16.810725] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
[ 16.823414] pci_bus 0000:00: root bus resource [io 0x1e160000-0x1e16ffff]
[ 16.837111] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
[ 16.850809] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 16.861797] pci 0000:00:00.0: [0e8d:0801] type 01 class 0x060400
[ 16.873807] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[ 16.886296] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 16.898867] pci 0000:00:00.0: supports D1
[ 16.906860] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[ 16.918729] pci 0000:00:01.0: [0e8d:0801] type 01 class 0x060400
[ 16.930741] pci 0000:00:01.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[ 16.943239] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 16.955795] pci 0000:00:01.0: supports D1
[ 16.963790] pci 0000:00:01.0: PME# supported from D0 D1 D3hot
[ 16.975590] pci 0000:00:02.0: [0e8d:0801] type 01 class 0x060400
[ 16.987596] pci 0000:00:02.0: reg 0x10: [mem 0x00000000-0x7fffffff]
[ 17.000088] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x0000ffff]
[ 17.012642] pci 0000:00:02.0: supports D1
[ 17.020634] pci 0000:00:02.0: PME# supported from D0 D1 D3hot
[ 17.033310] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 17.049284] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 17.065236] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 17.081408] pci 0000:01:00.0: [1b21:0611] type 00 class 0x010185
[ 17.093429] pci 0000:01:00.0: reg 0x10: [io 0x0000-0x0007]
[ 17.104544] pci 0000:01:00.0: reg 0x14: [io 0x0000-0x0003]
[ 17.115655] pci 0000:01:00.0: reg 0x18: [io 0x0000-0x0007]
[ 17.126767] pci 0000:01:00.0: reg 0x1c: [io 0x0000-0x0003]
[ 17.137877] pci 0000:01:00.0: reg 0x20: [io 0x0000-0x000f]
[ 17.148991] pci 0000:01:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[ 17.161627] pci 0000:01:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:00.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[ 17.190393] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[ 17.200842] pci 0000:00:00.0: bridge window [io 0x0000-0x0fff]
[ 17.212985] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff]
[ 17.226512] pci 0000:00:00.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 17.240905] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 17.254335] pci 0000:02:00.0: [1b21:0611] type 00 class 0x010185
[ 17.266360] pci 0000:02:00.0: reg 0x10: [io 0x0000-0x0007]
[ 17.277472] pci 0000:02:00.0: reg 0x14: [io 0x0000-0x0003]
[ 17.288584] pci 0000:02:00.0: reg 0x18: [io 0x0000-0x0007]
[ 17.299695] pci 0000:02:00.0: reg 0x1c: [io 0x0000-0x0003]
[ 17.310806] pci 0000:02:00.0: reg 0x20: [io 0x0000-0x000f]
[ 17.321917] pci 0000:02:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[ 17.334555] pci 0000:02:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:01.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[ 17.363326] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
[ 17.373781] pci 0000:00:01.0: bridge window [io 0x0000-0x0fff]
[ 17.385922] pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff]
[ 17.399445] pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 17.413838] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
[ 17.427246] pci 0000:03:00.0: [1b21:0611] type 00 class 0x010185
[ 17.439270] pci 0000:03:00.0: reg 0x10: [io 0x0000-0x0007]
[ 17.450382] pci 0000:03:00.0: reg 0x14: [io 0x0000-0x0003]
[ 17.461496] pci 0000:03:00.0: reg 0x18: [io 0x0000-0x0007]
[ 17.472613] pci 0000:03:00.0: reg 0x1c: [io 0x0000-0x0003]
[ 17.483723] pci 0000:03:00.0: reg 0x20: [io 0x0000-0x000f]
[ 17.494837] pci 0000:03:00.0: reg 0x24: [mem 0x00000000-0x000001ff]
[ 17.507471] pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:02.0 (capable of 4.000 Gb/s with 5 GT/s x1 link)
[ 17.536234] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
[ 17.546669] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
[ 17.558810] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
[ 17.572333] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff pref]
[ 17.586724] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
[ 17.599971] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
[ 17.613150] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
[ 17.627021] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
[ 17.640197] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
[ 17.654067] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
[ 17.667243] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
[ 17.681116] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
[ 17.694643] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
[ 17.709034] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
[ 17.722565] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
[ 17.736962] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
[ 17.750491] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
[ 17.764882] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
[ 17.778415] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
[ 17.791944] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
[ 17.805473] pci 0000:00:00.0: BAR 7: assigned [io 0x1e160000-0x1e160fff]
[ 17.818999] pci 0000:00:01.0: BAR 7: assigned [io 0x1e161000-0x1e161fff]
[ 17.832525] pci 0000:00:02.0: BAR 7: assigned [io 0x1e162000-0x1e162fff]
[ 17.846064] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
[ 17.859596] pci 0000:01:00.0: BAR 4: assigned [io 0x1e160000-0x1e16000f]
[ 17.873131] pci 0000:01:00.0: BAR 0: assigned [io 0x1e160010-0x1e160017]
[ 17.886662] pci 0000:01:00.0: BAR 2: assigned [io 0x1e160018-0x1e16001f]
[ 17.900192] pci 0000:01:00.0: BAR 1: assigned [io 0x1e160020-0x1e160023]
[ 17.913722] pci 0000:01:00.0: BAR 3: assigned [io 0x1e160024-0x1e160027]
[ 17.927254] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 17.937150] pci 0000:00:00.0: bridge window [io 0x1e160000-0x1e160fff]
[ 17.950675] pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff]
[ 17.964199] pci 0000:00:00.0: bridge window [mem 0x60100000-0x601fffff pref]
[ 17.978600] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
[ 17.992133] pci 0000:02:00.0: BAR 4: assigned [io 0x1e161000-0x1e16100f]
[ 18.005668] pci 0000:02:00.0: BAR 0: assigned [io 0x1e161010-0x1e161017]
[ 18.019199] pci 0000:02:00.0: BAR 2: assigned [io 0x1e161018-0x1e16101f]
[ 18.032729] pci 0000:02:00.0: BAR 1: assigned [io 0x1e161020-0x1e161023]
[ 18.046259] pci 0000:02:00.0: BAR 3: assigned [io 0x1e161024-0x1e161027]
[ 18.059788] pci 0000:00:01.0: PCI bridge to [bus 02]
[ 18.069682] pci 0000:00:01.0: bridge window [io 0x1e161000-0x1e161fff]
[ 18.083207] pci 0000:00:01.0: bridge window [mem 0x60200000-0x602fffff]
[ 18.096730] pci 0000:00:01.0: bridge window [mem 0x60300000-0x603fffff pref]
[ 18.111128] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
[ 18.124659] pci 0000:03:00.0: BAR 4: assigned [io 0x1e162000-0x1e16200f]
[ 18.138196] pci 0000:03:00.0: BAR 0: assigned [io 0x1e162010-0x1e162017]
[ 18.151729] pci 0000:03:00.0: BAR 2: assigned [io 0x1e162018-0x1e16201f]
[ 18.165261] pci 0000:03:00.0: BAR 1: assigned [io 0x1e162020-0x1e162023]
[ 18.178792] pci 0000:03:00.0: BAR 3: assigned [io 0x1e162024-0x1e162027]
[ 18.192321] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 18.202216] pci 0000:00:02.0: bridge window [io 0x1e162000-0x1e162fff]
[ 18.215739] pci 0000:00:02.0: bridge window [mem 0x60400000-0x604fffff]
[ 18.229270] pci 0000:00:02.0: bridge window [mem 0x60500000-0x605fffff pref]
drivers/staging/mt7621-pci/pci-mt7621.c | 43 ++++++++++++++-----------
1 file changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 973be9aa7bb2..7ef2099b01c5 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -118,6 +118,7 @@ struct mt7621_pcie_port {
* @busn: bus range
* @offset: IO / Memory offset
* @dev: Pointer to PCIe device
+ * @io_map_base: virtual memory base address for io
* @ports: pointer to PCIe port information
* @resets_inverted: depends on chip revision
* reset lines are inverted.
@@ -132,6 +133,7 @@ struct mt7621_pcie {
resource_size_t mem;
resource_size_t io;
} offset;
+ unsigned long io_map_base;
struct list_head ports;
bool resets_inverted;
};
@@ -291,22 +293,21 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
}
for_each_of_pci_range(&parser, &range) {
- struct resource *res = NULL;
-
switch (range.flags & IORESOURCE_TYPE_BITS) {
case IORESOURCE_IO:
- ioremap(range.cpu_addr, range.size);
- res = &pcie->io;
+ pcie->io_map_base =
+ (unsigned long)ioremap(range.cpu_addr,
+ range.size);
+ of_pci_range_to_resource(&range, node, &pcie->io);
+ pcie->io.start = range.cpu_addr;
+ pcie->io.end = range.cpu_addr + range.size - 1;
pcie->offset.io = 0x00000000UL;
break;
case IORESOURCE_MEM:
- res = &pcie->mem;
+ of_pci_range_to_resource(&range, node, &pcie->mem);
pcie->offset.mem = 0x00000000UL;
break;
}
-
- if (res)
- of_pci_range_to_resource(&range, node, res);
}
err = of_pci_parse_bus_range(node, &pcie->busn);
@@ -318,6 +319,8 @@ static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
pcie->busn.flags = IORESOURCE_BUS;
}
+ set_io_port_base(pcie->io_map_base);
+
return 0;
}
@@ -548,6 +551,10 @@ static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
u32 slot;
u32 val;
+ /* Setup MEMWIN and IOWIN */
+ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
+ pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE);
+
list_for_each_entry(port, &pcie->ports, list) {
if (port->enabled) {
mt7621_pcie_port_clk_enable(port);
@@ -668,11 +675,17 @@ static int mt7621_pci_probe(struct platform_device *pdev)
return err;
}
+ err = mt7621_pci_parse_request_of_pci_ranges(pcie);
+ if (err) {
+ dev_err(dev, "Error requesting pci resources from ranges");
+ goto out_release_gpios;
+ }
+
/* set resources limits */
- iomem_resource.start = 0;
- iomem_resource.end = ~0UL; /* no limit */
- ioport_resource.start = 0;
- ioport_resource.end = ~0UL; /* no limit */
+ iomem_resource.start = pcie->mem.start;
+ iomem_resource.end = pcie->mem.end;
+ ioport_resource.start = pcie->io.start;
+ ioport_resource.end = pcie->io.end;
mt7621_pcie_init_ports(pcie);
@@ -685,12 +698,6 @@ static int mt7621_pci_probe(struct platform_device *pdev)
mt7621_pcie_enable_ports(pcie);
- err = mt7621_pci_parse_request_of_pci_ranges(pcie);
- if (err) {
- dev_err(dev, "Error requesting pci resources from ranges");
- goto out_release_gpios;
- }
-
setup_cm_memory_region(pcie);
err = mt7621_pcie_request_resources(pcie, &res);
--
2.25.1
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