On Mon, Nov 04, 2019 at 01:20:09PM +0100, Greg KH wrote:
On Mon, Nov 04, 2019 at 07:22:20PM +0800, Jack Ping CHNG wrote:
This driver enables the Intel's LGM SoC GSWIP block.
GSWIP is a core module tailored for L2/L3/L4+ data plane and QoS functions.
It allows CPUs and other accelerators connected to the SoC datapath
to enqueue and dequeue packets through DMAs.
Most configuration values are stored in tables such as Parsing and
Classification Engine tables, Buffer Manager tables and Pseudo MAC
tables.
Why is this being submitted to staging? What is wrong with the "real"
part of the kernel for this?
Or even, what is wrong with the current driver?
drivers/net/dsa/lantiq_gswip.c?
GSWIP (a new HW IP) is part of Intel Datapath Architecture drivers
design for new Intel network/GW SoC (LGM).
Currently there are few other drivers (for different HW blocks in the
datapath) which are still under internal code review.
Once it is done we are planning to submit staging folder.
Since the development is ongoing, we thought it is best to submit GSWIP
first in drivers/staging/intel-dpa folder.
In the meantime, we will prepare a more detail TODO list for intel-dpa
folder and a README to introduce the dpa.
Jack, your patch does not seem to of made it to any of the lists. So i cannot comment on it contents. If this is a switch driver, please ensure you Cc: the usual suspects for switch drivers.
Andrew
Sure, I will resubmit my patch.
Best regards,
Chng Jack Ping
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