This commit adds device tree binding documentation for MT7621 PLL controller. Signed-off-by: Chuanhong Guo <gch981213@xxxxxxxxx> --- .../bindings/clock/mediatek,mt7621-pll.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt new file mode 100644 index 000000000000..05c15062cd20 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-pll.txt @@ -0,0 +1,19 @@ +Binding for Mediatek MT7621 PLL controller + +The PLL controller provides the 2 main clocks of the SoC: CPU and BUS. + +Required Properties: +- compatible: has to be "mediatek,mt7621-pll" +- #clock-cells: has to be one + +Optional properties: +- clock-output-names: should be "cpu", "bus" + +Example: + pll { + compatible = "mediatek,mt7621-pll", "syscon"; + + #clock-cells = <1>; + clock-output-names = "cpu", "bus"; + }; + -- 2.21.0 _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel