The rtl8821ce can be found on many HP and Lenovo laptops. Users have been using out-of-tree module for a while, The new Realtek WiFi driver, rtw88, will support rtl8821ce in 2020 or later. But before that happens let's include rtl8821ce in staging at the interim. The original tarball can be found at [1]. The driver was trimmed from 600K LOC down to 200K LOC. [1] https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1829220/+attachment/5263936/+files/rtl8821CE_WiFi_linux_v5.2.5.2.1_30816.20190425_COEX20170310-1212.tar.xz Cc: Larry Finger <Larry.Finger@xxxxxxxxxxxx> Signed-off-by: Kai-Heng Feng <kai.heng.feng@xxxxxxxxxxxxx> --- drivers/staging/Kconfig | 2 + drivers/staging/Makefile | 1 + drivers/staging/rtl8821ce/Kconfig | 10 + drivers/staging/rtl8821ce/Makefile | 103 + drivers/staging/rtl8821ce/TODO | 15 + .../staging/rtl8821ce/core/efuse/rtw_efuse.c | 1461 ++ drivers/staging/rtl8821ce/core/rtw_ap.c | 3263 ++++ drivers/staging/rtl8821ce/core/rtw_br_ext.c | 1286 ++ drivers/staging/rtl8821ce/core/rtw_btcoex.c | 363 + .../rtl8821ce/core/rtw_btcoex_wifionly.c | 43 + drivers/staging/rtl8821ce/core/rtw_cmd.c | 3016 ++++ drivers/staging/rtl8821ce/core/rtw_debug.c | 264 + .../staging/rtl8821ce/core/rtw_ieee80211.c | 2271 +++ drivers/staging/rtl8821ce/core/rtw_io.c | 155 + .../staging/rtl8821ce/core/rtw_ioctl_query.c | 24 + .../staging/rtl8821ce/core/rtw_ioctl_set.c | 602 + drivers/staging/rtl8821ce/core/rtw_mi.c | 834 + drivers/staging/rtl8821ce/core/rtw_mlme.c | 3606 ++++ drivers/staging/rtl8821ce/core/rtw_mlme_ext.c | 11868 +++++++++++++ drivers/staging/rtl8821ce/core/rtw_mp.c | 1616 ++ drivers/staging/rtl8821ce/core/rtw_odm.c | 380 + drivers/staging/rtl8821ce/core/rtw_p2p.c | 3661 ++++ drivers/staging/rtl8821ce/core/rtw_pwrctrl.c | 1034 ++ drivers/staging/rtl8821ce/core/rtw_recv.c | 3210 ++++ drivers/staging/rtl8821ce/core/rtw_rf.c | 937 + drivers/staging/rtl8821ce/core/rtw_security.c | 2038 +++ drivers/staging/rtl8821ce/core/rtw_sreset.c | 213 + drivers/staging/rtl8821ce/core/rtw_sta_mgt.c | 872 + drivers/staging/rtl8821ce/core/rtw_vht.c | 670 + .../staging/rtl8821ce/core/rtw_wlan_util.c | 2935 ++++ drivers/staging/rtl8821ce/core/rtw_xmit.c | 3570 ++++ .../rtl8821ce/hal/btc/halbtc8821c1ant.c | 5148 ++++++ .../rtl8821ce/hal/btc/halbtc8821c1ant.h | 461 + .../rtl8821ce/hal/btc/halbtc8821c2ant.c | 5773 +++++++ .../rtl8821ce/hal/btc/halbtc8821c2ant.h | 470 + .../rtl8821ce/hal/btc/halbtc8821cwifionly.c | 182 + .../rtl8821ce/hal/btc/halbtc8821cwifionly.h | 68 + .../staging/rtl8821ce/hal/btc/halbtcoutsrc.h | 987 ++ .../staging/rtl8821ce/hal/btc/mp_precomp.h | 64 + .../staging/rtl8821ce/hal/efuse/efuse_mask.h | 15 + .../efuse/rtl8821c/HalEfuseMask8821C_PCIE.c | 99 + .../efuse/rtl8821c/HalEfuseMask8821C_PCIE.h | 37 + drivers/staging/rtl8821ce/hal/hal_btcoex.c | 2741 +++ .../rtl8821ce/hal/hal_btcoex_wifionly.c | 69 + drivers/staging/rtl8821ce/hal/hal_com.c | 3490 ++++ drivers/staging/rtl8821ce/hal/hal_com_c2h.h | 109 + .../staging/rtl8821ce/hal/hal_com_phycfg.c | 4226 +++++ drivers/staging/rtl8821ce/hal/hal_dm.c | 331 + drivers/staging/rtl8821ce/hal/hal_dm.h | 27 + drivers/staging/rtl8821ce/hal/hal_halmac.c | 1832 ++ drivers/staging/rtl8821ce/hal/hal_halmac.h | 104 + drivers/staging/rtl8821ce/hal/hal_intf.c | 1080 ++ drivers/staging/rtl8821ce/hal/hal_mp.c | 1414 ++ .../rtl8821ce/hal/halmac/halmac_2_platform.h | 80 + .../halmac_8821c/halmac_8821c_cfg.h | 75 + .../halmac_8821c/halmac_8821c_phy.c | 37 + .../halmac_8821c/halmac_8821c_pwr_seq.c | 240 + .../halmac_8821c/halmac_8821c_pwr_seq.h | 17 + .../halmac_8821c/halmac_api_8821c.c | 269 + .../halmac_8821c/halmac_api_8821c.h | 29 + .../halmac_8821c/halmac_api_8821c_pcie.c | 251 + .../halmac_8821c/halmac_api_8821c_pcie.h | 40 + .../halmac_8821c/halmac_func_8821c.c | 311 + .../halmac_8821c/halmac_func_8821c.h | 19 + .../hal/halmac/halmac_88xx/halmac_88xx_cfg.h | 154 + .../hal/halmac/halmac_88xx/halmac_api_88xx.c | 5404 ++++++ .../hal/halmac/halmac_88xx/halmac_api_88xx.h | 601 + .../halmac/halmac_88xx/halmac_api_88xx_pcie.c | 322 + .../halmac/halmac_88xx/halmac_api_88xx_pcie.h | 76 + .../hal/halmac/halmac_88xx/halmac_func_88xx.c | 3735 ++++ .../hal/halmac/halmac_88xx/halmac_func_88xx.h | 523 + .../staging/rtl8821ce/hal/halmac/halmac_api.c | 359 + .../staging/rtl8821ce/hal/halmac/halmac_api.h | 84 + .../rtl8821ce/hal/halmac/halmac_bit2.h | 226 + .../rtl8821ce/hal/halmac/halmac_bit_8821c.h | 9782 +++++++++++ .../rtl8821ce/hal/halmac/halmac_fw_info.h | 98 + .../hal/halmac/halmac_fw_offload_c2h_ap.h | 158 + .../hal/halmac/halmac_fw_offload_c2h_nic.h | 124 + .../hal/halmac/halmac_fw_offload_h2c_ap.h | 421 + .../hal/halmac/halmac_fw_offload_h2c_nic.h | 300 + .../hal/halmac/halmac_h2c_extra_info_ap.h | 70 + .../hal/halmac/halmac_h2c_extra_info_nic.h | 48 + .../hal/halmac/halmac_intf_phy_cmd.h | 31 + .../rtl8821ce/hal/halmac/halmac_module.h | 116 + .../hal/halmac/halmac_original_c2h_ap.h | 337 + .../hal/halmac/halmac_original_c2h_nic.h | 230 + .../hal/halmac/halmac_original_h2c_ap.h | 879 + .../hal/halmac/halmac_original_h2c_nic.h | 610 + .../rtl8821ce/hal/halmac/halmac_pcie_reg.h | 5 + .../rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h | 107 + .../rtl8821ce/hal/halmac/halmac_reg2.h | 1116 ++ .../rtl8821ce/hal/halmac/halmac_reg_8821c.h | 737 + .../rtl8821ce/hal/halmac/halmac_rx_bd_ap.h | 22 + .../rtl8821ce/hal/halmac/halmac_rx_bd_chip.h | 22 + .../rtl8821ce/hal/halmac/halmac_rx_bd_nic.h | 22 + .../rtl8821ce/hal/halmac/halmac_rx_desc_ap.h | 89 + .../hal/halmac/halmac_rx_desc_chip.h | 79 + .../rtl8821ce/hal/halmac/halmac_rx_desc_nic.h | 89 + .../rtl8821ce/hal/halmac/halmac_tx_bd_ap.h | 92 + .../rtl8821ce/hal/halmac/halmac_tx_bd_chip.h | 75 + .../rtl8821ce/hal/halmac/halmac_tx_bd_nic.h | 75 + .../rtl8821ce/hal/halmac/halmac_tx_desc_ap.h | 408 + .../hal/halmac/halmac_tx_desc_chip.h | 266 + .../rtl8821ce/hal/halmac/halmac_tx_desc_nic.h | 294 + .../rtl8821ce/hal/halmac/halmac_type.h | 1905 ++ .../staging/rtl8821ce/hal/led/hal_pci_led.c | 1214 ++ .../staging/rtl8821ce/hal/phydm/halphyrf_ap.h | 92 + .../staging/rtl8821ce/hal/phydm/halphyrf_ce.c | 705 + .../staging/rtl8821ce/hal/phydm/halphyrf_ce.h | 101 + .../staging/rtl8821ce/hal/phydm/mp_precomp.h | 20 + drivers/staging/rtl8821ce/hal/phydm/phydm.c | 2147 +++ drivers/staging/rtl8821ce/hal/phydm/phydm.h | 1036 ++ .../staging/rtl8821ce/hal/phydm/phydm_acs.c | 183 + .../staging/rtl8821ce/hal/phydm/phydm_acs.h | 66 + .../rtl8821ce/hal/phydm/phydm_adaptivity.c | 863 + .../rtl8821ce/hal/phydm/phydm_adaptivity.h | 187 + .../rtl8821ce/hal/phydm/phydm_adc_sampling.c | 591 + .../rtl8821ce/hal/phydm/phydm_adc_sampling.h | 118 + .../rtl8821ce/hal/phydm/phydm_antdiv.c | 55 + .../rtl8821ce/hal/phydm/phydm_antdiv.h | 288 + .../rtl8821ce/hal/phydm/phydm_beamforming.h | 22 + .../staging/rtl8821ce/hal/phydm/phydm_ccx.c | 389 + .../staging/rtl8821ce/hal/phydm/phydm_ccx.h | 100 + .../rtl8821ce/hal/phydm/phydm_cfotracking.c | 317 + .../rtl8821ce/hal/phydm/phydm_cfotracking.h | 70 + .../staging/rtl8821ce/hal/phydm/phydm_debug.c | 319 + .../staging/rtl8821ce/hal/phydm/phydm_debug.h | 313 + .../staging/rtl8821ce/hal/phydm/phydm_dfs.c | 38 + .../staging/rtl8821ce/hal/phydm/phydm_dfs.h | 97 + .../staging/rtl8821ce/hal/phydm/phydm_dig.c | 1129 ++ .../staging/rtl8821ce/hal/phydm/phydm_dig.h | 311 + .../hal/phydm/phydm_dynamic_rx_path.h | 33 + .../hal/phydm/phydm_dynamicbbpowersaving.c | 39 + .../hal/phydm/phydm_dynamicbbpowersaving.h | 49 + .../hal/phydm/phydm_edcaturbocheck.h | 26 + .../rtl8821ce/hal/phydm/phydm_hwconfig.c | 1652 ++ .../rtl8821ce/hal/phydm/phydm_hwconfig.h | 558 + .../rtl8821ce/hal/phydm/phydm_interface.c | 509 + .../rtl8821ce/hal/phydm/phydm_interface.h | 376 + .../staging/rtl8821ce/hal/phydm/phydm_iqk.h | 66 + .../staging/rtl8821ce/hal/phydm/phydm_kfree.c | 331 + .../staging/rtl8821ce/hal/phydm/phydm_kfree.h | 73 + .../rtl8821ce/hal/phydm/phydm_noisemonitor.h | 47 + .../rtl8821ce/hal/phydm/phydm_pathdiv.c | 50 + .../rtl8821ce/hal/phydm/phydm_pathdiv.h | 53 + .../hal/phydm/phydm_powertracking_ap.h | 302 + .../hal/phydm/phydm_powertracking_ce.c | 726 + .../hal/phydm/phydm_powertracking_ce.h | 297 + .../rtl8821ce/hal/phydm/phydm_pre_define.h | 587 + .../rtl8821ce/hal/phydm/phydm_precomp.h | 68 + .../staging/rtl8821ce/hal/phydm/phydm_psd.c | 447 + .../staging/rtl8821ce/hal/phydm/phydm_psd.h | 100 + .../rtl8821ce/hal/phydm/phydm_rainfo.c | 1641 ++ .../rtl8821ce/hal/phydm/phydm_rainfo.h | 395 + .../staging/rtl8821ce/hal/phydm/phydm_reg.h | 132 + .../rtl8821ce/hal/phydm/phydm_regdefine11ac.h | 90 + .../rtl8821ce/hal/phydm/phydm_regdefine11n.h | 209 + .../staging/rtl8821ce/hal/phydm/phydm_types.h | 153 + .../staging/rtl8821ce/hal/phydm/rtchnlplan.h | 613 + .../hal/phydm/rtl8821c/halhwimg8821c_bb.c | 3421 ++++ .../hal/phydm/rtl8821c/halhwimg8821c_bb.h | 81 + .../hal/phydm/rtl8821c/halhwimg8821c_fw.h | 59 + .../hal/phydm/rtl8821c/halhwimg8821c_mac.c | 318 + .../hal/phydm/rtl8821c/halhwimg8821c_mac.h | 37 + .../hal/phydm/rtl8821c/halhwimg8821c_rf.c | 1793 ++ .../hal/phydm/rtl8821c/halhwimg8821c_rf.h | 57 + .../hal/phydm/rtl8821c/halphyrf_8821c.c | 372 + .../hal/phydm/rtl8821c/halphyrf_8821c.h | 63 + .../hal/phydm/rtl8821c/phydm_hal_api8821c.c | 888 + .../hal/phydm/rtl8821c/phydm_hal_api8821c.h | 213 + .../hal/phydm/rtl8821c/phydm_iqk_8821c.c | 1991 +++ .../hal/phydm/rtl8821c/phydm_iqk_8821c.h | 44 + .../hal/phydm/rtl8821c/phydm_regconfig8821c.c | 169 + .../hal/phydm/rtl8821c/phydm_regconfig8821c.h | 101 + .../hal/phydm/rtl8821c/version_rtl8821c.h | 10 + .../rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h | 13 + .../rtl8821ce/hal/rtl8821c/hal8821c_fw.c | 14412 ++++++++++++++++ .../rtl8821ce/hal/rtl8821c/hal8821c_fw.h | 31 + .../rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h | 109 + .../hal/rtl8821c/pci/rtl8821ce_halinit.c | 319 + .../hal/rtl8821c/pci/rtl8821ce_halmac.c | 289 + .../rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c | 120 + .../hal/rtl8821c/pci/rtl8821ce_ops.c | 694 + .../hal/rtl8821c/pci/rtl8821ce_recv.c | 435 + .../hal/rtl8821c/pci/rtl8821ce_xmit.c | 984 ++ .../staging/rtl8821ce/hal/rtl8821c/rtl8821c.h | 115 + .../rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c | 816 + .../rtl8821ce/hal/rtl8821c/rtl8821c_dm.c | 168 + .../rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c | 289 + .../rtl8821ce/hal/rtl8821c/rtl8821c_mac.c | 183 + .../rtl8821ce/hal/rtl8821c/rtl8821c_ops.c | 2777 +++ .../rtl8821ce/hal/rtl8821c/rtl8821c_phy.c | 968 ++ .../staging/rtl8821ce/include/HalPwrSeqCmd.h | 133 + drivers/staging/rtl8821ce/include/HalVerDef.h | 174 + drivers/staging/rtl8821ce/include/autoconf.h | 38 + .../staging/rtl8821ce/include/basic_types.h | 293 + .../rtl8821ce/include/byteorder/big_endian.h | 88 + .../rtl8821ce/include/byteorder/generic.h | 184 + .../rtl8821ce/include/byteorder/swab.h | 130 + .../rtl8821ce/include/byteorder/swabb.h | 152 + drivers/staging/rtl8821ce/include/circ_buf.h | 29 + drivers/staging/rtl8821ce/include/cmd_osdep.h | 31 + .../staging/rtl8821ce/include/custom_gpio.h | 24 + drivers/staging/rtl8821ce/include/drv_conf.h | 165 + drivers/staging/rtl8821ce/include/drv_types.h | 1005 ++ .../rtl8821ce/include/drv_types_linux.h | 24 + .../staging/rtl8821ce/include/drv_types_pci.h | 199 + drivers/staging/rtl8821ce/include/ethernet.h | 41 + drivers/staging/rtl8821ce/include/h2clbk.h | 30 + .../staging/rtl8821ce/include/hal_btcoex.h | 94 + .../rtl8821ce/include/hal_btcoex_wifionly.h | 48 + drivers/staging/rtl8821ce/include/hal_com.h | 557 + .../staging/rtl8821ce/include/hal_com_h2c.h | 294 + .../staging/rtl8821ce/include/hal_com_led.h | 258 + .../rtl8821ce/include/hal_com_phycfg.h | 324 + .../staging/rtl8821ce/include/hal_com_reg.h | 1110 ++ drivers/staging/rtl8821ce/include/hal_data.h | 819 + .../staging/rtl8821ce/include/hal_ic_cfg.h | 28 + drivers/staging/rtl8821ce/include/hal_intf.h | 655 + drivers/staging/rtl8821ce/include/hal_pg.h | 776 + drivers/staging/rtl8821ce/include/hal_phy.h | 235 + .../staging/rtl8821ce/include/hal_phy_reg.h | 31 + drivers/staging/rtl8821ce/include/ieee80211.h | 1618 ++ .../staging/rtl8821ce/include/ieee80211_ext.h | 289 + drivers/staging/rtl8821ce/include/if_ether.h | 109 + drivers/staging/rtl8821ce/include/ip.h | 138 + .../rtl8821ce/include/linux/wireless.h | 79 + .../staging/rtl8821ce/include/mlme_osdep.h | 35 + .../staging/rtl8821ce/include/mp_custom_oid.h | 350 + drivers/staging/rtl8821ce/include/nic_spec.h | 44 + .../staging/rtl8821ce/include/osdep_intf.h | 101 + .../staging/rtl8821ce/include/osdep_service.h | 570 + .../rtl8821ce/include/osdep_service_linux.h | 278 + drivers/staging/rtl8821ce/include/pci_hal.h | 26 + drivers/staging/rtl8821ce/include/pci_ops.h | 26 + .../staging/rtl8821ce/include/pci_osintf.h | 38 + .../staging/rtl8821ce/include/recv_osdep.h | 58 + .../staging/rtl8821ce/include/rtl8821c_dm.h | 31 + .../staging/rtl8821ce/include/rtl8821c_hal.h | 42 + .../staging/rtl8821ce/include/rtl8821c_spec.h | 197 + .../staging/rtl8821ce/include/rtl8821ce_hal.h | 29 + .../staging/rtl8821ce/include/rtw_android.h | 76 + drivers/staging/rtl8821ce/include/rtw_ap.h | 74 + .../rtl8821ce/include/rtw_beamforming.h | 25 + .../staging/rtl8821ce/include/rtw_br_ext.h | 68 + drivers/staging/rtl8821ce/include/rtw_bt_mp.h | 278 + .../staging/rtl8821ce/include/rtw_btcoex.h | 130 + .../rtl8821ce/include/rtw_btcoex_wifionly.h | 28 + .../staging/rtl8821ce/include/rtw_byteorder.h | 36 + drivers/staging/rtl8821ce/include/rtw_cmd.h | 993 ++ drivers/staging/rtl8821ce/include/rtw_debug.h | 337 + .../staging/rtl8821ce/include/rtw_eeprom.h | 114 + drivers/staging/rtl8821ce/include/rtw_efuse.h | 238 + drivers/staging/rtl8821ce/include/rtw_event.h | 114 + drivers/staging/rtl8821ce/include/rtw_ht.h | 218 + drivers/staging/rtl8821ce/include/rtw_io.h | 404 + drivers/staging/rtl8821ce/include/rtw_ioctl.h | 175 + .../rtl8821ce/include/rtw_ioctl_query.h | 24 + .../staging/rtl8821ce/include/rtw_ioctl_rtl.h | 77 + .../staging/rtl8821ce/include/rtw_ioctl_set.h | 52 + drivers/staging/rtl8821ce/include/rtw_iol.h | 123 + drivers/staging/rtl8821ce/include/rtw_mcc.h | 19 + drivers/staging/rtl8821ce/include/rtw_mem.h | 41 + drivers/staging/rtl8821ce/include/rtw_mi.h | 199 + drivers/staging/rtl8821ce/include/rtw_mlme.h | 885 + .../staging/rtl8821ce/include/rtw_mlme_ext.h | 1085 ++ drivers/staging/rtl8821ce/include/rtw_mp.h | 829 + .../staging/rtl8821ce/include/rtw_mp_ioctl.h | 301 + .../rtl8821ce/include/rtw_mp_phy_regdef.h | 1071 ++ drivers/staging/rtl8821ce/include/rtw_odm.h | 49 + drivers/staging/rtl8821ce/include/rtw_p2p.h | 143 + .../staging/rtl8821ce/include/rtw_pwrctrl.h | 358 + drivers/staging/rtl8821ce/include/rtw_qos.h | 31 + drivers/staging/rtl8821ce/include/rtw_recv.h | 634 + drivers/staging/rtl8821ce/include/rtw_rf.h | 237 + .../staging/rtl8821ce/include/rtw_security.h | 416 + .../staging/rtl8821ce/include/rtw_sreset.h | 59 + drivers/staging/rtl8821ce/include/rtw_tdls.h | 24 + .../staging/rtl8821ce/include/rtw_version.h | 3 + drivers/staging/rtl8821ce/include/rtw_vht.h | 142 + drivers/staging/rtl8821ce/include/rtw_wapi.h | 212 + .../staging/rtl8821ce/include/rtw_wifi_regd.h | 26 + drivers/staging/rtl8821ce/include/rtw_xmit.h | 547 + drivers/staging/rtl8821ce/include/sta_info.h | 542 + drivers/staging/rtl8821ce/include/wifi.h | 1193 ++ .../staging/rtl8821ce/include/wlan_bssdef.h | 360 + .../staging/rtl8821ce/include/xmit_osdep.h | 63 + .../rtl8821ce/os_dep/linux/ioctl_linux.c | 8796 ++++++++++ .../staging/rtl8821ce/os_dep/linux/ioctl_mp.c | 2071 +++ .../rtl8821ce/os_dep/linux/mlme_linux.c | 211 + .../staging/rtl8821ce/os_dep/linux/os_intfs.c | 2389 +++ .../staging/rtl8821ce/os_dep/linux/pci_intf.c | 1574 ++ .../rtl8821ce/os_dep/linux/recv_linux.c | 577 + .../rtl8821ce/os_dep/linux/rtw_android.c | 549 + .../rtl8821ce/os_dep/linux/xmit_linux.c | 353 + .../staging/rtl8821ce/os_dep/osdep_service.c | 1325 ++ 296 files changed, 206166 insertions(+) create mode 100644 drivers/staging/rtl8821ce/Kconfig create mode 100644 drivers/staging/rtl8821ce/Makefile create mode 100644 drivers/staging/rtl8821ce/TODO create mode 100644 drivers/staging/rtl8821ce/core/efuse/rtw_efuse.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_ap.c create mode 100644 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100644 drivers/staging/rtl8821ce/core/rtw_recv.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_rf.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_security.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_sreset.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_sta_mgt.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_vht.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_wlan_util.c create mode 100644 drivers/staging/rtl8821ce/core/rtw_xmit.c create mode 100644 drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.c create mode 100644 drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.h create mode 100644 drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.c create mode 100644 drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.h create mode 100644 drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.c create mode 100644 drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.h create mode 100644 drivers/staging/rtl8821ce/hal/btc/halbtcoutsrc.h create mode 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drivers/staging/rtl8821ce/include/rtw_mp_ioctl.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_mp_phy_regdef.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_odm.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_p2p.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_pwrctrl.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_qos.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_recv.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_rf.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_security.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_sreset.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_tdls.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_version.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_vht.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_wapi.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_wifi_regd.h create mode 100644 drivers/staging/rtl8821ce/include/rtw_xmit.h create mode 100644 drivers/staging/rtl8821ce/include/sta_info.h create mode 100644 drivers/staging/rtl8821ce/include/wifi.h create mode 100644 drivers/staging/rtl8821ce/include/wlan_bssdef.h create mode 100644 drivers/staging/rtl8821ce/include/xmit_osdep.h create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/ioctl_linux.c create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/ioctl_mp.c create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/mlme_linux.c create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/os_intfs.c create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/pci_intf.c create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/recv_linux.c create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/rtw_android.c create mode 100644 drivers/staging/rtl8821ce/os_dep/linux/xmit_linux.c create mode 100644 drivers/staging/rtl8821ce/os_dep/osdep_service.c diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index d5f771fafc21..ef4ad6cab441 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -40,6 +40,8 @@ source "drivers/staging/rtl8712/Kconfig" source "drivers/staging/rtl8188eu/Kconfig" +source "drivers/staging/rtl8821ce/Kconfig" + source "drivers/staging/rts5208/Kconfig" source "drivers/staging/octeon/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 0da0d3f0b5e4..732e89655739 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_RTL8192E) += rtl8192e/ obj-$(CONFIG_RTL8723BS) += rtl8723bs/ obj-$(CONFIG_R8712U) += rtl8712/ obj-$(CONFIG_R8188EU) += rtl8188eu/ +obj-$(CONFIG_R8821CE) += rtl8821ce/ obj-$(CONFIG_RTS5208) += rts5208/ obj-$(CONFIG_NETLOGIC_XLR_NET) += netlogic/ obj-$(CONFIG_OCTEON_ETHERNET) += octeon/ diff --git a/drivers/staging/rtl8821ce/Kconfig b/drivers/staging/rtl8821ce/Kconfig new file mode 100644 index 000000000000..6a878cf086fe --- /dev/null +++ b/drivers/staging/rtl8821ce/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0 +config RTL8821CE + tristate "Realtek 8821CE PCIE Wireless LAN NIC driver" + depends on WLAN && MMC && CFG80211 + depends on m + select WIRELESS_EXT + select WEXT_PRIV + ---help--- + This option enables support for RTL8821CE PCI driver. It can be found + on many HP and Lenovo Laptops. diff --git a/drivers/staging/rtl8821ce/Makefile b/drivers/staging/rtl8821ce/Makefile new file mode 100644 index 000000000000..240bd9ec2cc8 --- /dev/null +++ b/drivers/staging/rtl8821ce/Makefile @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_RTL8821CE) := r8821ce.o + +r8821ce-objs += core/rtw_cmd.o \ + core/rtw_security.o \ + core/rtw_debug.o \ + core/rtw_io.o \ + core/rtw_ioctl_set.o \ + core/rtw_ieee80211.o \ + core/rtw_mlme.o \ + core/rtw_mlme_ext.o \ + core/rtw_mi.o \ + core/rtw_wlan_util.o \ + core/rtw_vht.o \ + core/rtw_pwrctrl.o \ + core/rtw_rf.o \ + core/rtw_recv.o \ + core/rtw_sta_mgt.o \ + core/rtw_ap.o \ + core/rtw_xmit.o \ + core/rtw_p2p.o \ + core/rtw_br_ext.o \ + core/rtw_sreset.o \ + core/rtw_btcoex_wifionly.o \ + core/rtw_btcoex.o \ + core/rtw_odm.o \ + core/rtw_mp.o \ + core/efuse/rtw_efuse.o \ + os_dep/osdep_service.o \ + os_dep/linux/os_intfs.o \ + os_dep/linux/pci_intf.o \ + os_dep/linux/ioctl_linux.o \ + os_dep/linux/xmit_linux.o \ + os_dep/linux/mlme_linux.o \ + os_dep/linux/recv_linux.o \ + os_dep/linux/rtw_android.o \ + os_dep/linux/ioctl_mp.o \ + hal/hal_intf.o \ + hal/hal_com.o \ + hal/hal_com_phycfg.o \ + hal/hal_dm.o \ + hal/hal_btcoex_wifionly.o \ + hal/hal_btcoex.o \ + hal/hal_mp.o \ + hal/led/hal_pci_led.o \ + hal/halmac/halmac_api.o \ + hal/halmac/halmac_88xx/halmac_api_88xx.o \ + hal/halmac/halmac_88xx/halmac_func_88xx.o \ + hal/halmac/halmac_88xx/halmac_api_88xx_pcie.o \ + hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.o \ + hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.o \ + hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.o \ + hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.o \ + hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.o \ + hal/hal_halmac.o \ + hal/rtl8821c/rtl8821c_halinit.o \ + hal/rtl8821c/rtl8821c_mac.o \ + hal/rtl8821c/rtl8821c_cmd.o \ + hal/rtl8821c/rtl8821c_phy.o \ + hal/rtl8821c/rtl8821c_dm.o \ + hal/rtl8821c/rtl8821c_ops.o \ + hal/rtl8821c/hal8821c_fw.o \ + hal/rtl8821c/pci/rtl8821ce_halinit.o \ + hal/rtl8821c/pci/rtl8821ce_halmac.o \ + hal/rtl8821c/pci/rtl8821ce_io.o \ + hal/rtl8821c/pci/rtl8821ce_xmit.o \ + hal/rtl8821c/pci/rtl8821ce_recv.o \ + hal/rtl8821c/pci/rtl8821ce_ops.o \ + hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.o \ + hal/phydm/phydm_debug.o \ + hal/phydm/phydm_antdiv.o \ + hal/phydm/phydm_interface.o \ + hal/phydm/phydm_hwconfig.o \ + hal/phydm/phydm.o \ + hal/phydm/halphyrf_ce.o \ + hal/phydm/phydm_dig.o \ + hal/phydm/phydm_pathdiv.o \ + hal/phydm/phydm_rainfo.o \ + hal/phydm/phydm_dynamicbbpowersaving.o \ + hal/phydm/phydm_powertracking_ce.o \ + hal/phydm/phydm_adaptivity.o \ + hal/phydm/phydm_cfotracking.o \ + hal/phydm/phydm_acs.o \ + hal/phydm/phydm_dfs.o \ + hal/phydm/phydm_adc_sampling.o \ + hal/phydm/phydm_kfree.o \ + hal/phydm/phydm_ccx.o \ + hal/phydm/phydm_psd.o \ + hal/btc/halbtc8821cwifionly.o \ + hal/btc/halbtc8821c1ant.o \ + hal/btc/halbtc8821c2ant.o \ + hal/phydm/rtl8821c/halhwimg8821c_bb.o \ + hal/phydm/rtl8821c/halhwimg8821c_mac.o \ + hal/phydm/rtl8821c/halhwimg8821c_rf.o \ + hal/phydm/rtl8821c/phydm_hal_api8821c.o \ + hal/phydm/rtl8821c/phydm_regconfig8821c.o \ + hal/phydm/rtl8821c/halphyrf_8821c.o \ + hal/phydm/rtl8821c/phydm_iqk_8821c.o + +ccflags-y += -I$(srctree)/$(src)/include \ + -I$(srctree)/$(src)/hal/btc \ + -I$(srctree)/$(src)/hal/phydm \ + -I$(srctree)/$(src)/platform diff --git a/drivers/staging/rtl8821ce/TODO b/drivers/staging/rtl8821ce/TODO new file mode 100644 index 000000000000..be30f79551e1 --- /dev/null +++ b/drivers/staging/rtl8821ce/TODO @@ -0,0 +1,15 @@ +TODO: +- remove unused functions, macros and variables. +- find and remove any code for other chips that is left over +- find and remove any code for non-PCIe that is left over +- convert any remaining unusual variable types +- find codes that can use %pM and %Nph formatting +- checkpatch.pl fixes - most of the remaining ones are lines too long. Many + of them will require refactoring +- merge Realtek's bugfixes and new features into the driver +- switch to use LIB80211 +- switch to use MAC80211 + +Please send any patches to Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, +Kai-Heng Feng <kai.heng.feng@xxxxxxxxxxxxx> +and Larry Finger <Larry.Finger@xxxxxxxxxxxx>. diff --git a/drivers/staging/rtl8821ce/core/efuse/rtw_efuse.c b/drivers/staging/rtl8821ce/core/efuse/rtw_efuse.c new file mode 100644 index 000000000000..69188988251b --- /dev/null +++ b/drivers/staging/rtl8821ce/core/efuse/rtw_efuse.c @@ -0,0 +1,1461 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_EFUSE_C_ + +#include <drv_types.h> +#include <hal_data.h> + +#include "../hal/efuse/efuse_mask.h" + +/*------------------------Define local variable------------------------------*/ +u8 fakeEfuseBank = {0}; +u32 fakeEfuseUsedBytes = {0}; +u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE] = {0}; +u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN] = {0}; +u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN] = {0}; + +u32 BTEfuseUsedBytes = {0}; +u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0}; +u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0}; + +u32 fakeBTEfuseUsedBytes = {0}; +u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN] = {0}; +u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN] = {0}; + +u8 maskfileBuffer[64]; +/*------------------------Define local variable------------------------------*/ +BOOLEAN rtw_file_efuse_IsMasked(PADAPTER pAdapter, u16 Offset) +{ + int r = Offset / 16; + int c = (Offset % 16) / 2; + int result = 0; + + if (pAdapter->registrypriv.boffefusemask) + return FALSE; + + if (c < 4) /* Upper double word */ + result = (maskfileBuffer[r] & (0x10 << c)); + else + result = (maskfileBuffer[r] & (0x01 << (c - 4))); + + return (result > 0) ? 0 : 1; +} + +BOOLEAN efuse_IsMasked(PADAPTER pAdapter, u16 Offset) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + if (pAdapter->registrypriv.boffefusemask) + return FALSE; + + if (IS_HARDWARE_TYPE_8821CE(pAdapter)) + return (IS_MASKED(8821C, _MPCIE, Offset)) ? TRUE : FALSE; + + return FALSE; +} + +void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (IS_HARDWARE_TYPE_8821CU(pAdapter)) + GET_MASK_ARRAY(8821C, _MUSB, pArray); + +#elif DEV_BUS_TYPE == RT_PCI_INTERFACE + if (IS_HARDWARE_TYPE_8821CE(pAdapter)) + GET_MASK_ARRAY(8821C, _MPCIE, pArray); + +#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (IS_HARDWARE_TYPE_8821CS(pAdapter)) + GET_MASK_ARRAY(8821C , _MSDIO, pArray); +#endif /*#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE*/ +} + +u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (IS_HARDWARE_TYPE_8821CU(pAdapter)) + return GET_MASK_ARRAY_LEN(8821C, _MUSB); + +#elif DEV_BUS_TYPE == RT_PCI_INTERFACE + if (IS_HARDWARE_TYPE_8821CE(pAdapter)) + return GET_MASK_ARRAY_LEN(8821C, _MPCIE); + +#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE + if (IS_HARDWARE_TYPE_8821CS(pAdapter)) + return GET_MASK_ARRAY_LEN(8821C, _MSDIO); +#endif + return 0; +} + +u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u8 ret = _SUCCESS; + u16 mapLen = 0, i = 0; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + + ret = rtw_efuse_map_read(padapter, addr, cnts , data); + + if (padapter->registrypriv.boffefusemask == 0) { + + for (i = 0; i < cnts; i++) { + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { + if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask.*/ + data[i] = 0xff; + } else { + /*RTW_INFO(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ + if (efuse_IsMasked(padapter, addr + i)) { + data[i] = 0xff; + /*RTW_INFO(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ + } + } + } + + } + return ret; + +} + +#include "../../hal/hal_halmac.h" + +void BTEfuse_PowerSwitch(PADAPTER adapter, u8 write, u8 pwrstate) +{ +} + +u16 efuse_GetavailableSize(PADAPTER adapter) +{ + struct dvobj_priv *d; + u32 size = 0; + int err; + + d = adapter_to_dvobj(adapter); + err = rtw_halmac_get_available_efuse_size(d, &size); + if (err) + return 0; + + return size; +} + +u8 efuse_bt_GetCurrentSize(PADAPTER adapter, u16 *usesize) +{ + u8 *efuse_map; + + *usesize = 0; + efuse_map = rtw_malloc(EFUSE_BT_MAP_LEN); + if (efuse_map == NULL) { + RTW_DBG("%s: malloc FAIL\n", __FUNCTION__); + return _FAIL; + } + + /* for get bt phy efuse last use byte */ + hal_ReadEFuse_BT_logic_map(adapter, 0x00, EFUSE_BT_MAP_LEN, efuse_map); + *usesize = fakeBTEfuseUsedBytes; + + if (efuse_map) + rtw_mfree(efuse_map, EFUSE_BT_MAP_LEN); + + return _SUCCESS; +} + +u16 efuse_bt_GetMaxSize(PADAPTER adapter) +{ + return EFUSE_BT_REAL_CONTENT_LEN; +} + +void EFUSE_GetEfuseDefinition(PADAPTER adapter, u8 efusetype, u8 type, void *out, BOOLEAN test) +{ + struct dvobj_priv *d; + u32 v32 = 0; + + d = adapter_to_dvobj(adapter); + + if (adapter->hal_func.EFUSEGetEfuseDefinition) { + adapter->hal_func.EFUSEGetEfuseDefinition(adapter, efusetype, type, out, test); + return; + } + + if (EFUSE_WIFI == efusetype) { + switch (type) { + case TYPE_EFUSE_MAP_LEN: + rtw_halmac_get_logical_efuse_size(d, &v32); + *(u16 *)out = (u16)v32; + return; + + case TYPE_EFUSE_REAL_CONTENT_LEN: + rtw_halmac_get_physical_efuse_size(d, &v32); + *(u16 *)out = (u16)v32; + return; + } + } else if (EFUSE_BT == efusetype) { + switch (type) { + case TYPE_EFUSE_MAP_LEN: + *(u16 *)out = EFUSE_BT_MAP_LEN; + return; + + case TYPE_EFUSE_REAL_CONTENT_LEN: + *(u16 *)out = EFUSE_BT_REAL_CONTENT_LEN; + return; + } + } +} + +/* + * read/write raw efuse data + */ +u8 rtw_efuse_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data) +{ + struct dvobj_priv *d; + u8 *efuse = NULL; + u32 size, i; + int err; + + d = adapter_to_dvobj(adapter); + err = rtw_halmac_get_physical_efuse_size(d, &size); + if (err) + size = EFUSE_MAX_SIZE; + + if ((addr + cnts) > size) + return _FAIL; + + if (_TRUE == write) { + err = rtw_halmac_write_physical_efuse(d, addr, cnts, data); + if (err) + return _FAIL; + } else { + if (cnts > 16) + efuse = rtw_zmalloc(size); + + if (efuse) { + err = rtw_halmac_read_physical_efuse_map(d, efuse, size); + if (err) { + rtw_mfree(efuse, size); + return _FAIL; + } + + _rtw_memcpy(data, efuse + addr, cnts); + rtw_mfree(efuse, size); + } else { + err = rtw_halmac_read_physical_efuse(d, addr, cnts, data); + if (err) + return _FAIL; + } + } + + return _SUCCESS; +} + +static inline void dump_buf(u8 *buf, u32 len) +{ + u32 i; + + RTW_INFO("-----------------Len %d----------------\n", len); + for (i = 0; i < len; i++) + printk("%2.2x-", *(buf + i)); + printk("\n"); +} + +/* + * read/write raw efuse data + */ +u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data) +{ + struct dvobj_priv *d; + u8 *efuse = NULL; + u32 size, i; + int err = _FAIL; + + d = adapter_to_dvobj(adapter); + + size = EFUSE_BT_REAL_CONTENT_LEN; + + if ((addr + cnts) > size) + return _FAIL; + + if (_TRUE == write) { + err = rtw_halmac_write_bt_physical_efuse(d, addr, cnts, data); + if (err == -1) { + RTW_ERR("%s: rtw_halmac_write_bt_physical_efuse fail!\n", __FUNCTION__); + return _FAIL; + } + RTW_INFO("%s: rtw_halmac_write_bt_physical_efuse OK! data 0x%x\n", __FUNCTION__, *data); + } else { + efuse = rtw_zmalloc(size); + + if (efuse) { + err = rtw_halmac_read_bt_physical_efuse_map(d, efuse, size); + + if (err == -1) { + RTW_ERR("%s: rtw_halmac_read_bt_physical_efuse_map fail!\n", __FUNCTION__); + rtw_mfree(efuse, size); + return _FAIL; + } + dump_buf(efuse + addr, cnts); + + _rtw_memcpy(data, efuse + addr, cnts); + + RTW_INFO("%s: rtw_halmac_read_bt_physical_efuse_map ok! data 0x%x\n", __FUNCTION__, *data); + rtw_mfree(efuse, size); + } + } + + return _SUCCESS; +} + +u8 rtw_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) +{ + struct dvobj_priv *d; + u8 *efuse = NULL; + u32 size, i; + int err; + + d = adapter_to_dvobj(adapter); + err = rtw_halmac_get_logical_efuse_size(d, &size); + if (err) + return _FAIL; + + /* size error handle */ + if ((addr + cnts) > size) { + if (addr < size) + cnts = size - addr; + else + return _FAIL; + } + + if (cnts > 16) + efuse = rtw_zmalloc(size); + + if (efuse) { + err = rtw_halmac_read_logical_efuse_map(d, efuse, size); + if (err) { + rtw_mfree(efuse, size); + return _FAIL; + } + + _rtw_memcpy(data, efuse + addr, cnts); + rtw_mfree(efuse, size); + } else { + err = rtw_halmac_read_logical_efuse(d, addr, cnts, data); + if (err) + return _FAIL; + } + + return _SUCCESS; +} + +u8 rtw_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) +{ + struct dvobj_priv *d; + u8 *efuse = NULL; + u32 size, i; + int err; + u8 mask_buf[64] = ""; + u16 mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(adapter); + + d = adapter_to_dvobj(adapter); + err = rtw_halmac_get_logical_efuse_size(d, &size); + if (err) + return _FAIL; + + if ((addr + cnts) > size) + return _FAIL; + + efuse = rtw_zmalloc(size); + if (!efuse) + return _FAIL; + + err = rtw_halmac_read_logical_efuse_map(d, efuse, size); + if (err) { + rtw_mfree(efuse, size); + return _FAIL; + } + + _rtw_memcpy(efuse + addr, data, cnts); + + if (adapter->registrypriv.boffefusemask == 0) { + RTW_INFO("Use mask Array Len: %d\n", mask_len); + + if (mask_len != 0) { + if (adapter->registrypriv.bFileMaskEfuse == _TRUE) + _rtw_memcpy(mask_buf, maskfileBuffer, mask_len); + else + rtw_efuse_mask_array(adapter, mask_buf); + + err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, mask_len); + } else + err = rtw_halmac_write_logical_efuse_map(d, efuse, size, NULL, 0); + } else { + _rtw_memset(mask_buf, 0xFF, sizeof(mask_buf)); + RTW_INFO("Efuse mask off\n"); + err = rtw_halmac_write_logical_efuse_map(d, efuse, size, mask_buf, size/16); + } + + if (err) { + rtw_mfree(efuse, size); + return _FAIL; + } + + rtw_mfree(efuse, size); + + return _SUCCESS; +} + +u8 rtw_BT_efuse_map_read(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) +{ + hal_ReadEFuse_BT_logic_map(adapter,addr, cnts, data); + + return _SUCCESS; +} + +u8 rtw_BT_efuse_map_write(PADAPTER adapter, u16 addr, u16 cnts, u8 *data) +{ +#define RT_ASSERT_RET(expr) \ + if (!(expr)) { \ + printk("Assertion failed! %s at ......\n", #expr); \ + printk(" ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__); \ + return _FAIL; \ + } + + u8 offset, word_en; + u8 *map; + u8 newdata[PGPKT_DATA_SIZE]; + s32 i = 0, j = 0, idx; + u8 ret = _SUCCESS; + u16 mapLen = 1024; + + if ((addr + cnts) > mapLen) + return _FAIL; + + RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */ + RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */ + + map = rtw_zmalloc(mapLen); + if (map == NULL) + return _FAIL; + + ret = rtw_BT_efuse_map_read(adapter, 0, mapLen, map); + if (ret == _FAIL) + goto exit; + RTW_INFO("OFFSET\tVALUE(hex)\n"); + for (i = 0; i < mapLen; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */ + RTW_INFO("0x%03x\t", i); + for (j = 0; j < 8; j++) + RTW_INFO("%02X ", map[i + j]); + RTW_INFO("\t"); + for (; j < 16; j++) + RTW_INFO("%02X ", map[i + j]); + RTW_INFO("\n"); + } + RTW_INFO("\n"); + + idx = 0; + offset = (addr >> 3); + while (idx < cnts) { + word_en = 0xF; + j = (addr + idx) & 0x7; + _rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE); + for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { + if (data[idx] != map[addr + idx]) { + word_en &= ~BIT(i >> 1); + newdata[i] = data[idx]; + } + } + + if (word_en != 0xF) { + ret = EfusePgPacketWrite_BT(adapter, offset, word_en, newdata, _FALSE); + RTW_INFO("offset=%x\n", offset); + RTW_INFO("word_en=%x\n", word_en); + RTW_INFO("%s: data=", __FUNCTION__); + for (i = 0; i < PGPKT_DATA_SIZE; i++) + RTW_INFO("0x%02X ", newdata[i]); + RTW_INFO("\n"); + if (ret == _FAIL) + break; + } + offset++; + } +exit: + rtw_mfree(map, mapLen); + return _SUCCESS; +} + +VOID hal_ReadEFuse_BT_logic_map( + PADAPTER padapter, + u16 _offset, + u16 _size_byte, + u8 *pbuf +) +{ + + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; + + u8 *efuseTbl, *phyefuse; + u8 bank; + u16 eFuse_Addr = 0; + u8 efuseHeader, efuseExtHdr, efuseData; + u8 offset, wden; + u16 i, total, used; + u8 efuse_usage; + + /* */ + /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ + /* */ + if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) { + RTW_INFO("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __FUNCTION__, _offset, _size_byte); + return; + } + + efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN); + phyefuse = rtw_malloc(EFUSE_BT_REAL_CONTENT_LEN); + if (efuseTbl == NULL || phyefuse == NULL) { + RTW_INFO("%s: efuseTbl or phyefuse malloc fail!\n", __FUNCTION__); + goto exit; + } + + /* 0xff will be efuse default value instead of 0x00. */ + _rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN); + _rtw_memset(phyefuse, 0xFF, EFUSE_BT_REAL_CONTENT_LEN); + + if (rtw_efuse_bt_access(padapter, _FALSE, 0, EFUSE_BT_REAL_CONTENT_LEN, phyefuse)) + dump_buf(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN); + + total = BANK_NUM; + for (bank = 1; bank <= total; bank++) { /* 8723d Max bake 0~2 */ + eFuse_Addr = 0; + + while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) { + /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */ + efuseHeader = phyefuse[eFuse_Addr++]; + + if (efuseHeader == 0xFF) + break; + RTW_INFO("%s: efuse[%#X]=0x%02x (header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseHeader); + + /* Check PG header for section num. */ + if (EXT_HEADER(efuseHeader)) { /* extended header */ + offset = GET_HDR_OFFSET_2_0(efuseHeader); + RTW_INFO("%s: extended header offset_2_0=0x%X\n", __FUNCTION__, offset); + + /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */ + efuseExtHdr = phyefuse[eFuse_Addr++]; + + RTW_INFO("%s: efuse[%#X]=0x%02x (ext header)\n", __FUNCTION__, (((bank - 1) * EFUSE_BT_REAL_CONTENT_LEN) + eFuse_Addr - 1), efuseExtHdr); + if (ALL_WORDS_DISABLED(efuseExtHdr)) + continue; + + offset |= ((efuseExtHdr & 0xF0) >> 1); + wden = (efuseExtHdr & 0x0F); + } else { + offset = ((efuseHeader >> 4) & 0x0f); + wden = (efuseHeader & 0x0f); + } + + if (offset < EFUSE_BT_MAX_SECTION) { + u16 addr; + + /* Get word enable value from PG header */ + RTW_INFO("%s: Offset=%d Worden=%#X\n", __FUNCTION__, offset, wden); + + addr = offset * PGPKT_DATA_SIZE; + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(wden & (0x01 << i))) { + efuseData = 0; + /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */ + efuseData = phyefuse[eFuse_Addr++]; + + RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData); + efuseTbl[addr] = efuseData; + + efuseData = 0; + /* ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */ + efuseData = phyefuse[eFuse_Addr++]; + + RTW_INFO("%s: efuse[%#X]=0x%02X\n", __FUNCTION__, eFuse_Addr - 1, efuseData); + efuseTbl[addr + 1] = efuseData; + } + addr += 2; + } + } else { + RTW_INFO("%s: offset(%d) is illegal!!\n", __FUNCTION__, offset); + eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2; + } + } + + if ((eFuse_Addr - 1) < total) { + RTW_INFO("%s: bank(%d) data end at %#x\n", __FUNCTION__, bank, eFuse_Addr - 1); + break; + } + } + + /* switch bank back to bank 0 for later BT and wifi use. */ + //hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); + + /* Copy from Efuse map to output pointer memory!!! */ + for (i = 0; i < _size_byte; i++) + pbuf[i] = efuseTbl[_offset + i]; + /* Calculate Efuse utilization */ + total = EFUSE_BT_REAL_BANK_CONTENT_LEN; + + used = eFuse_Addr - 1; + + if (total) + efuse_usage = (u8)((used * 100) / total); + else + efuse_usage = 100; + + fakeBTEfuseUsedBytes = used; + RTW_INFO("%s: BTEfuseUsed last Bytes = %#x\n", __FUNCTION__, fakeBTEfuseUsedBytes); + +exit: + if (efuseTbl) + rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN); + if (phyefuse) + rtw_mfree(phyefuse, EFUSE_BT_REAL_BANK_CONTENT_LEN); +} + +static u8 hal_EfusePartialWriteCheck( + PADAPTER padapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; + u8 bRet = _FALSE; + u16 startAddr = 0, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN, efuse_max = EFUSE_BT_REAL_BANK_CONTENT_LEN; + u8 efuse_data = 0; + + startAddr = (u16)fakeBTEfuseUsedBytes; + + startAddr %= efuse_max; + RTW_INFO("%s: startAddr=%#X\n", __FUNCTION__, startAddr); + + while (1) { + if (startAddr >= efuse_max_available_len) { + bRet = _FALSE; + RTW_INFO("%s: startAddr(%d) >= efuse_max_available_len(%d)\n", + __FUNCTION__, startAddr, efuse_max_available_len); + break; + } + if (rtw_efuse_bt_access(padapter, _FALSE, startAddr, 1, &efuse_data)&& (efuse_data != 0xFF)) { + bRet = _FALSE; + RTW_INFO("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n", + __FUNCTION__, startAddr, efuse_data); + break; + } else { + /* not used header, 0xff */ + *pAddr = startAddr; + /* RTW_INFO("%s: Started from unused header offset=%d\n", __FUNCTION__, startAddr)); */ + bRet = _TRUE; + break; + } + } + + return bRet; +} + +static u8 hal_EfusePgPacketWrite2ByteHeader( + PADAPTER padapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u16 efuse_addr, efuse_max_available_len = EFUSE_BT_REAL_BANK_CONTENT_LEN; + u8 pg_header = 0, tmp_header = 0; + u8 repeatcnt = 0; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + efuse_addr = *pAddr; + if (efuse_addr >= efuse_max_available_len) { + RTW_INFO("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len); + return _FALSE; + } + + pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F; + /* RTW_INFO("%s: pg_header=0x%x\n", __FUNCTION__, pg_header); */ + + do { + + rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header); + rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header); + + if (tmp_header != 0xFF) + break; + if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { + RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__); + return _FALSE; + } + } while (1); + + if (tmp_header != pg_header) { + RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header); + return _FALSE; + } + + /* to write ext_header */ + efuse_addr++; + pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en; + + do { + rtw_efuse_bt_access(padapter, _TRUE, efuse_addr, 1, &pg_header); + rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &tmp_header); + + if (tmp_header != 0xFF) + break; + if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { + RTW_INFO("%s: Repeat over limit for ext_header!!\n", __FUNCTION__); + return _FALSE; + } + } while (1); + + if (tmp_header != pg_header) { /* offset PG fail */ + RTW_ERR("%s: PG EXT Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header); + return _FALSE; + } + + *pAddr = efuse_addr; + + return _TRUE; +} + +static u8 hal_EfusePgPacketWrite1ByteHeader( + PADAPTER pAdapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + u8 pg_header = 0, tmp_header = 0; + u16 efuse_addr = *pAddr; + u8 repeatcnt = 0; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en; + + do { + rtw_efuse_bt_access(pAdapter, _TRUE, efuse_addr, 1, &pg_header); + rtw_efuse_bt_access(pAdapter, _FALSE, efuse_addr, 1, &tmp_header); + + if (tmp_header != 0xFF) + break; + if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { + RTW_INFO("%s: Repeat over limit for pg_header!!\n", __FUNCTION__); + return _FALSE; + } + } while (1); + + if (tmp_header != pg_header) { + RTW_ERR("%s: PG Header Fail!!(pg=0x%02X read=0x%02X)\n", __FUNCTION__, pg_header, tmp_header); + return _FALSE; + } + + *pAddr = efuse_addr; + + return _TRUE; +} + +static u8 hal_EfusePgPacketWriteHeader( + PADAPTER padapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + + if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE) + bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); + else + bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); + + return bRet; +} + +static u8 +Hal_EfuseWordEnableDataWrite( + PADAPTER padapter, + u16 efuse_addr, + u8 word_en, + u8 *data, + u8 bPseudoTest) +{ + u16 tmpaddr = 0; + u16 start_addr = efuse_addr; + u8 badworden = 0x0F; + u8 tmpdata[PGPKT_DATA_SIZE]; + + /* RTW_INFO("%s: efuse_addr=%#x word_en=%#x\n", __FUNCTION__, efuse_addr, word_en); */ + _rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE); + + if (!(word_en & BIT(0))) { + tmpaddr = start_addr; + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[0]); + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[1]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[0]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[1]); + if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1])) + badworden &= (~BIT(0)); + } + if (!(word_en & BIT(1))) { + tmpaddr = start_addr; + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[2]); + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[3]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[2]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[3]); + if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3])) + badworden &= (~BIT(1)); + } + if (!(word_en & BIT(2))) { + tmpaddr = start_addr; + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[4]); + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[5]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[4]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[5]); + if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5])) + badworden &= (~BIT(2)); + } + if (!(word_en & BIT(3))) { + tmpaddr = start_addr; + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[6]); + rtw_efuse_bt_access(padapter, _TRUE, start_addr++, 1, &data[7]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr, 1, &tmpdata[6]); + rtw_efuse_bt_access(padapter, _FALSE, tmpaddr + 1, 1, &tmpdata[7]); + + if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7])) + badworden &= (~BIT(3)); + } + + return badworden; +} + +static void +hal_EfuseConstructPGPkt( + u8 offset, + u8 word_en, + u8 *pData, + PPGPKT_STRUCT pTargetPkt) +{ + _rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE); + pTargetPkt->offset = offset; + pTargetPkt->word_en = word_en; + efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data); + pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); +} + +static u8 +hal_EfusePgPacketWriteData( + PADAPTER pAdapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u16 efuse_addr; + u8 badworden; + + efuse_addr = *pAddr; + badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest); + if (badworden != 0x0F) { + RTW_INFO("%s: Fail!!\n", __FUNCTION__); + return _FALSE; + } else + RTW_INFO("%s: OK!!\n", __FUNCTION__); + + return _TRUE; +} + +/* *********************************************************** + * Efuse related code + * *********************************************************** */ +static u8 +hal_EfuseSwitchToBank( + PADAPTER padapter, + u8 bank, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + u32 value32 = 0; + + RTW_INFO("%s: Efuse switch bank to %d\n", __FUNCTION__, bank); + if (bPseudoTest) { + fakeEfuseBank = bank; + bRet = _TRUE; + } else { + value32 = rtw_read32(padapter, 0x34); + bRet = _TRUE; + switch (bank) { + case 0: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + break; + case 1: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); + break; + case 2: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); + break; + case 3: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); + break; + default: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + bRet = _FALSE; + break; + } + rtw_write32(padapter, 0x34, value32); + } + + return bRet; +} + +#define EFUSE_CTRL 0x30 /* E-Fuse Control. */ + +/* 11/16/2008 MH Read one byte from real Efuse. */ +u8 +efuse_OneByteRead( + IN PADAPTER pAdapter, + IN u16 addr, + IN u8 *data, + IN BOOLEAN bPseudoTest) +{ + u32 tmpidx = 0; + u8 bResult; + u8 readbyte; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + if (IS_HARDWARE_TYPE_8723B(pAdapter) || + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->version_id))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->version_id)) + ) { + /* <20130121, Kordan> For SMIC EFUSE specificatoin. */ + /* 0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) */ + /* phy_set_mac_reg(pAdapter, 0x34, BIT11, 0); */ + rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter, 0x34) & (~BIT11)); + } + + /* -----------------e-fuse reg ctrl --------------------------------- */ + /* address */ + rtw_write8(pAdapter, EFUSE_CTRL + 1, (u8)(addr & 0xff)); + rtw_write8(pAdapter, EFUSE_CTRL + 2, ((u8)((addr >> 8) & 0x03)) | + (rtw_read8(pAdapter, EFUSE_CTRL + 2) & 0xFC)); + + /* rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72); */ /* read cmd */ + /* Write bit 32 0 */ + readbyte = rtw_read8(pAdapter, EFUSE_CTRL + 3); + rtw_write8(pAdapter, EFUSE_CTRL + 3, (readbyte & 0x7f)); + + while (!(0x80 & rtw_read8(pAdapter, EFUSE_CTRL + 3)) && (tmpidx < 1000)) { + rtw_mdelay_os(1); + tmpidx++; + } + if (tmpidx < 100) { + *data = rtw_read8(pAdapter, EFUSE_CTRL); + bResult = _TRUE; + } else { + *data = 0xff; + bResult = _FALSE; + RTW_INFO("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult); + RTW_INFO("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL)); + } + + return bResult; +} + +static u16 +hal_EfuseGetCurrentSize_BT( + PADAPTER padapter, + u8 bPseudoTest) +{ + u16 btusedbytes; + u16 efuse_addr; + u8 bank, startBank; + u8 hoffset = 0, hworden = 0; + u8 efuse_data, word_cnts = 0; + u16 retU2 = 0; + u8 bContinual = _TRUE; + + btusedbytes = fakeBTEfuseUsedBytes; + + efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN)); + startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN)); + + RTW_INFO("%s: start from bank=%d addr=0x%X\n", __FUNCTION__, startBank, efuse_addr); + retU2 = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK; + + for (bank = startBank; bank < 3; bank++) { + if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) { + RTW_ERR("%s: switch bank(%d) Fail!!\n", __FUNCTION__, bank); + /* bank = EFUSE_MAX_BANK; */ + break; + } + + /* only when bank is switched we have to reset the efuse_addr. */ + if (bank != startBank) + efuse_addr = 0; + + while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { + if (rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data) == _FALSE) { + RTW_ERR("%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __FUNCTION__, efuse_addr); + /* bank = EFUSE_MAX_BANK; */ + break; + } + RTW_INFO("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank); + + if (efuse_data == 0xFF) + break; + + if (EXT_HEADER(efuse_data)) { + hoffset = GET_HDR_OFFSET_2_0(efuse_data); + efuse_addr++; + rtw_efuse_bt_access(padapter, _FALSE, efuse_addr, 1, &efuse_data); + RTW_INFO("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __FUNCTION__, efuse_addr, efuse_data, bank); + + if (ALL_WORDS_DISABLED(efuse_data)) { + efuse_addr++; + continue; + } + + /* hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */ + hoffset |= ((efuse_data & 0xF0) >> 1); + hworden = efuse_data & 0x0F; + } else { + hoffset = (efuse_data >> 4) & 0x0F; + hworden = efuse_data & 0x0F; + } + + RTW_INFO(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n", + FUNC_ADPT_ARG(padapter), hoffset, hworden); + + word_cnts = Efuse_CalculateWordCnts(hworden); + /* read next header */ + efuse_addr += (word_cnts * 2) + 1; + } + /* Check if we need to check next bank efuse */ + if (efuse_addr < retU2) + break;/* don't need to check next bank. */ + } + retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr; + + fakeBTEfuseUsedBytes = retU2; + RTW_INFO("%s: CurrentSize=%d\n", __FUNCTION__, retU2); + return retU2; +} + +static u8 +hal_BT_EfusePgCheckAvailableAddr( + PADAPTER pAdapter, + u8 bPseudoTest) +{ + u16 max_available = EFUSE_BT_REAL_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK; + u16 current_size = 0; + + RTW_INFO("%s: max_available=%d\n", __FUNCTION__, max_available); + current_size = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest); + if (current_size >= max_available) { + RTW_INFO("%s: Error!! current_size(%d)>max_available(%d)\n", __FUNCTION__, current_size, max_available); + return _FALSE; + } + return _TRUE; +} + +u8 EfusePgPacketWrite_BT( + PADAPTER pAdapter, + u8 offset, + u8 word_en, + u8 *pData, + u8 bPseudoTest) +{ + PGPKT_STRUCT targetPkt; + u16 startAddr = 0; + u8 efuseType = EFUSE_BT; + + if (!hal_BT_EfusePgCheckAvailableAddr(pAdapter, bPseudoTest)) + return _FALSE; + + hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); + + if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + return _TRUE; +} + +/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */ +u8 +Efuse_CalculateWordCnts(IN u8 word_en) +{ + u8 word_cnts = 0; + if (!(word_en & BIT(0))) + word_cnts++; /* 0 : write enable */ + if (!(word_en & BIT(1))) + word_cnts++; + if (!(word_en & BIT(2))) + word_cnts++; + if (!(word_en & BIT(3))) + word_cnts++; + return word_cnts; +} + +/*----------------------------------------------------------------------------- + * Function: efuse_WordEnableDataRead + * + * Overview: Read allowed word in current efuse section data. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Create Version 0. + * 11/21/2008 MHC Fix Write bug when we only enable late word. + * + *---------------------------------------------------------------------------*/ +void +efuse_WordEnableDataRead(IN u8 word_en, + IN u8 *sourdata, + IN u8 *targetdata) +{ + if (!(word_en & BIT(0))) { + targetdata[0] = sourdata[0]; + targetdata[1] = sourdata[1]; + } + if (!(word_en & BIT(1))) { + targetdata[2] = sourdata[2]; + targetdata[3] = sourdata[3]; + } + if (!(word_en & BIT(2))) { + targetdata[4] = sourdata[4]; + targetdata[5] = sourdata[5]; + } + if (!(word_en & BIT(3))) { + targetdata[6] = sourdata[6]; + targetdata[7] = sourdata[7]; + } +} + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowMapUpdate + * + * Overview: Transfer current EFUSE content to shadow init and modify map. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/13/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void EFUSE_ShadowMapUpdate( + IN PADAPTER pAdapter, + IN u8 efuseType, + IN BOOLEAN bPseudoTest) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + u16 mapLen = 0; + u8 *efuse_map = NULL; + int err; + + mapLen = EEPROM_MAX_SIZE; + efuse_map = pHalData->efuse_eeprom_data; + /* efuse default content is 0xFF */ + _rtw_memset(efuse_map, 0xFF, EEPROM_MAX_SIZE); + + EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest); + if (!mapLen) { + RTW_WARN("%s: <ERROR> fail to get efuse size!\n", __FUNCTION__); + mapLen = EEPROM_MAX_SIZE; + } + if (mapLen > EEPROM_MAX_SIZE) { + RTW_WARN("%s: <ERROR> size of efuse data(%d) is large than expected(%d)!\n", + __FUNCTION__, mapLen, EEPROM_MAX_SIZE); + mapLen = EEPROM_MAX_SIZE; + } + + if (pHalData->bautoload_fail_flag == _FALSE) { + err = rtw_halmac_read_logical_efuse_map(adapter_to_dvobj(pAdapter), efuse_map, mapLen); + if (err) + RTW_ERR("%s: <ERROR> fail to get efuse map!\n", __FUNCTION__); + } + + rtw_dump_cur_efuse(pAdapter); +} /* EFUSE_ShadowMapUpdate */ + +const u8 _mac_hidden_max_bw_to_hal_bw_cap[MAC_HIDDEN_MAX_BW_NUM] = { + 0, + 0, + (BW_CAP_160M | BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M), + (BW_CAP_5M), + (BW_CAP_10M | BW_CAP_5M), + (BW_CAP_20M | BW_CAP_10M | BW_CAP_5M), + (BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M), + (BW_CAP_80M | BW_CAP_40M | BW_CAP_20M | BW_CAP_10M | BW_CAP_5M), +}; + +const u8 _mac_hidden_proto_to_hal_proto_cap[MAC_HIDDEN_PROTOCOL_NUM] = { + 0, + 0, + (PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B), + (PROTO_CAP_11AC | PROTO_CAP_11N | PROTO_CAP_11G | PROTO_CAP_11B), +}; + +u8 mac_hidden_wl_func_to_hal_wl_func(u8 func) +{ + u8 wl_func = 0; + + if (func & BIT0) + wl_func |= WL_FUNC_MIRACAST; + if (func & BIT1) + wl_func |= WL_FUNC_P2P; + if (func & BIT2) + wl_func |= WL_FUNC_TDLS; + if (func & BIT3) + wl_func |= WL_FUNC_FTM; + + return wl_func; +} + + +u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len) +{ + char *ptmpbuf = NULL, *ptr; + u8 val8; + u32 count, i, j; + int err; + u32 bufsize = 4096; + + ptmpbuf = rtw_zmalloc(bufsize); + if (ptmpbuf == NULL) + return _FALSE; + + count = rtw_retrieve_from_file(filepatch, ptmpbuf, bufsize); + if (count <= 100) { + rtw_mfree(ptmpbuf, bufsize); + RTW_ERR("%s, filepatch %s, size=%d, FAIL!!\n", __FUNCTION__, filepatch, count); + return _FALSE; + } + + i = 0; + j = 0; + ptr = ptmpbuf; + while ((j < len) && (i < count)) { + if (ptmpbuf[i] == '\0') + break; + + ptr = strpbrk(&ptmpbuf[i], " \t\n\r"); + if (ptr) { + if (ptr == &ptmpbuf[i]) { + i++; + continue; + } + + /* Add string terminating null */ + *ptr = 0; + } else { + ptr = &ptmpbuf[count-1]; + } + + err = sscanf(&ptmpbuf[i], "%hhx", &val8); + if (err != 1) { + RTW_WARN("Something wrong to parse efuse file, string=%s\n", &ptmpbuf[i]); + } else { + buf[j] = val8; + RTW_DBG("i=%d, j=%d, 0x%02x\n", i, j, buf[j]); + j++; + } + + i = ptr - ptmpbuf + 1; + } + + rtw_mfree(ptmpbuf, bufsize); + RTW_INFO("%s, filepatch %s, size=%d, done\n", __FUNCTION__, filepatch, count); + return _TRUE; +} + +u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size) +{ + u32 i; + u8 c; + u8 temp[3]; + u8 temp_i; + u8 end = _FALSE; + u32 ret = _FAIL; + + u8 *file_data = NULL; + u32 file_size, read_size, pos = 0; + u8 *map = NULL; + + if (rtw_is_file_readable_with_size(path, &file_size) != _TRUE) { + RTW_PRINT("%s %s is not readable\n", __func__, path); + goto exit; + } + + file_data = rtw_vmalloc(file_size); + if (!file_data) { + RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, file_size); + goto exit; + } + + read_size = rtw_retrieve_from_file(path, file_data, file_size); + if (read_size == 0) { + RTW_ERR("%s read from %s fail\n", __func__, path); + goto exit; + } + + map = rtw_vmalloc(map_size); + if (!map) { + RTW_ERR("%s rtw_vmalloc(%d) fail\n", __func__, map_size); + goto exit; + } + _rtw_memset(map, 0xff, map_size); + + temp[2] = 0; /* end of string '\0' */ + + for (i = 0 ; i < map_size ; i++) { + temp_i = 0; + + while (1) { + if (pos >= read_size) { + end = _TRUE; + break; + } + c = file_data[pos++]; + + /* bypass spece or eol or null before first hex digit */ + if (temp_i == 0 && (is_eol(c) == _TRUE || is_space(c) == _TRUE || is_null(c) == _TRUE)) + continue; + + if (IsHexDigit(c) == _FALSE) { + RTW_ERR("%s invalid 8-bit hex format for offset:0x%03x\n", __func__, i); + goto exit; + } + + temp[temp_i++] = c; + + if (temp_i == 2) { + /* parse value */ + if (sscanf(temp, "%hhx", &map[i]) != 1) { + RTW_ERR("%s sscanf fail for offset:0x%03x\n", __func__, i); + goto exit; + } + break; + } + } + + if (end == _TRUE) { + if (temp_i != 0) { + RTW_ERR("%s incomplete 8-bit hex format for offset:0x%03x\n", __func__, i); + goto exit; + } + break; + } + } + + RTW_PRINT("efuse file:%s, 0x%03x byte content read\n", path, i); + + _rtw_memcpy(buf, map, map_size); + + ret = _SUCCESS; + +exit: + if (file_data) + rtw_vmfree(file_data, file_size); + if (map) + rtw_vmfree(map, map_size); + + return ret; +} + +u32 rtw_read_macaddr_from_file(const char *path, u8 *buf) +{ + u32 i; + u8 temp[3]; + u32 ret = _FAIL; + + u8 file_data[17]; + u32 read_size, pos = 0; + u8 addr[ETH_ALEN]; + + if (rtw_is_file_readable(path) != _TRUE) { + RTW_PRINT("%s %s is not readable\n", __func__, path); + goto exit; + } + + read_size = rtw_retrieve_from_file(path, file_data, 17); + if (read_size != 17) { + RTW_ERR("%s read from %s fail\n", __func__, path); + goto exit; + } + + temp[2] = 0; /* end of string '\0' */ + + for (i = 0 ; i < ETH_ALEN ; i++) { + if (IsHexDigit(file_data[i * 3]) == _FALSE || IsHexDigit(file_data[i * 3 + 1]) == _FALSE) { + RTW_ERR("%s invalid 8-bit hex format for address offset:%u\n", __func__, i); + goto exit; + } + + if (i < ETH_ALEN - 1 && file_data[i * 3 + 2] != ':') { + RTW_ERR("%s invalid separator after address offset:%u\n", __func__, i); + goto exit; + } + + temp[0] = file_data[i * 3]; + temp[1] = file_data[i * 3 + 1]; + if (sscanf(temp, "%hhx", &addr[i]) != 1) { + RTW_ERR("%s sscanf fail for address offset:0x%03x\n", __func__, i); + goto exit; + } + } + + _rtw_memcpy(buf, addr, ETH_ALEN); + + RTW_PRINT("wifi_mac file: %s\n", path); + RTW_INFO(MAC_FMT"\n", MAC_ARG(buf)); + + ret = _SUCCESS; + +exit: + return ret; +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_ap.c b/drivers/staging/rtl8821ce/core/rtw_ap.c new file mode 100644 index 000000000000..48448aa28fc0 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_ap.c @@ -0,0 +1,3263 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_AP_C_ + +#include <drv_types.h> +#include <hal_data.h> + + +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WMM_OUI[]; +extern unsigned char WPS_OUI[]; +extern unsigned char P2P_OUI[]; +extern unsigned char WFD_OUI[]; + +void init_mlme_ap_info(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + _rtw_spinlock_init(&pmlmepriv->bcn_update_lock); + + /* pmlmeext->bstart_bss = _FALSE; */ + +} + +void free_mlme_ap_info(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + stop_ap_mode(padapter); + _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); + +} + +static void update_BCNTIM(_adapter *padapter) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); + unsigned char *pie = pnetwork_mlmeext->IEs; + + if (_TRUE) { + u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; + u16 tim_bitmap_le; + uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen; + + tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap); + + p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_); + if (p != NULL && tim_ielen > 0) { + tim_ielen += 2; + + premainder_ie = p + tim_ielen; + + tim_ie_offset = (sint)(p - pie); + + remainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen; + + /*append TIM IE from dst_ie offset*/ + dst_ie = p; + } else { + tim_ielen = 0; + + /*calculate head_len*/ + offset = _FIXED_IE_LENGTH_; + + /* get ssid_ie len */ + p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_)); + if (p != NULL) + offset += tmp_len + 2; + + /*get supported rates len*/ + p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_)); + if (p != NULL) + offset += tmp_len + 2; + + /*DS Parameter Set IE, len=3*/ + offset += 3; + + premainder_ie = pie + offset; + + remainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen; + + /*append TIM IE from offset*/ + dst_ie = pie + offset; + + } + + if (remainder_ielen > 0) { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if (pbackup_remainder_ie && premainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + *dst_ie++ = _TIM_IE_; + + if ((pstapriv->tim_bitmap & 0xff00) && (pstapriv->tim_bitmap & 0x00fe)) + tim_ielen = 5; + else + tim_ielen = 4; + + *dst_ie++ = tim_ielen; + + *dst_ie++ = 0;/*DTIM count*/ + *dst_ie++ = 1;/*DTIM period*/ + + if (pstapriv->tim_bitmap & BIT(0))/*for bc/mc frames*/ + *dst_ie++ = BIT(0);/*bitmap ctrl */ + else + *dst_ie++ = 0; + + if (tim_ielen == 4) { + u8 pvb = 0; + + if (pstapriv->tim_bitmap & 0x00fe) + pvb = (u8)tim_bitmap_le; + else if (pstapriv->tim_bitmap & 0xff00) + pvb = (u8)(tim_bitmap_le >> 8); + else + pvb = (u8)tim_bitmap_le; + + *dst_ie++ = pvb; + + } else if (tim_ielen == 5) { + _rtw_memcpy(dst_ie, &tim_bitmap_le, 2); + dst_ie += 2; + } + + /*copy remainder IE*/ + if (pbackup_remainder_ie) { + _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); + + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + } + + offset = (uint)(dst_ie - pie); + pnetwork_mlmeext->IELength = offset + remainder_ielen; + + } +} + +void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len) +{ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 bmatch = _FALSE; + u8 *pie = pnetwork->IEs; + u8 *p = NULL, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; + u32 i, offset, ielen, ie_offset, remainder_ielen = 0; + + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); + + if (pIE->ElementID > index) + break; + else if (pIE->ElementID == index) { /* already exist the same IE */ + p = (u8 *)pIE; + ielen = pIE->Length; + bmatch = _TRUE; + break; + } + + p = (u8 *)pIE; + ielen = pIE->Length; + i += (pIE->Length + 2); + } + + if (p != NULL && ielen > 0) { + ielen += 2; + + premainder_ie = p + ielen; + + ie_offset = (sint)(p - pie); + + remainder_ielen = pnetwork->IELength - ie_offset - ielen; + + if (bmatch) + dst_ie = p; + else + dst_ie = (p + ielen); + } + + if (dst_ie == NULL) + return; + + if (remainder_ielen > 0) { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if (pbackup_remainder_ie && premainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + *dst_ie++ = index; + *dst_ie++ = len; + + _rtw_memcpy(dst_ie, data, len); + dst_ie += len; + + /* copy remainder IE */ + if (pbackup_remainder_ie) { + _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); + + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + } + + offset = (uint)(dst_ie - pie); + pnetwork->IELength = offset + remainder_ielen; +} + +void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index) +{ + u8 *p, *dst_ie = NULL, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; + uint offset, ielen, ie_offset, remainder_ielen = 0; + u8 *pie = pnetwork->IEs; + + p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_); + if (p != NULL && ielen > 0) { + ielen += 2; + + premainder_ie = p + ielen; + + ie_offset = (sint)(p - pie); + + remainder_ielen = pnetwork->IELength - ie_offset - ielen; + + dst_ie = p; + } else + return; + + if (remainder_ielen > 0) { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if (pbackup_remainder_ie && premainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + /* copy remainder IE */ + if (pbackup_remainder_ie) { + _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); + + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + } + + offset = (uint)(dst_ie - pie); + pnetwork->IELength = offset + remainder_ielen; +} + +u8 chk_sta_is_alive(struct sta_info *psta); +u8 chk_sta_is_alive(struct sta_info *psta) +{ + u8 ret = _FALSE; + + /* if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) */ + if ((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts)) { + } else + ret = _TRUE; + + sta_update_last_rx_pkts(psta); + + return ret; +} + +void expire_timeout_chk(_adapter *padapter) +{ + _irqL irqL; + _list *phead, *plist; + u8 updated = _FALSE; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 chk_alive_num = 0; + char chk_alive_list[NUM_STA]; + int i; + + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + + phead = &pstapriv->auth_list; + plist = get_next(phead); + + /* check auth_queue */ + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, auth_list); + + plist = get_next(plist); + + if (psta->expire_to > 0) { + psta->expire_to--; + if (psta->expire_to == 0) { + rtw_list_delete(&psta->auth_list); + pstapriv->auth_list_cnt--; + + RTW_INFO("auth expire %02X%02X%02X%02X%02X%02X\n", + psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2], psta->hwaddr[3], psta->hwaddr[4], psta->hwaddr[5]); + + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(padapter, psta); + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + } + } + + } + + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + psta = NULL; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + /* check asoc_queue */ + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + if (chk_sta_is_alive(psta) || !psta->expire_to) { + psta->expire_to = pstapriv->expire_to; + psta->keep_alive_trycnt = 0; + psta->under_exist_checking = 0; + } else + psta->expire_to--; + + + if (psta->expire_to <= 0) { + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (padapter->registrypriv.wifi_spec == 1) { + psta->expire_to = pstapriv->expire_to; + continue; + } + + if (psta->state & WIFI_SLEEP_STATE) { + if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) { + /* to check if alive by another methods if staion is at ps mode. */ + psta->expire_to = pstapriv->expire_to; + psta->state |= WIFI_STA_ALIVE_CHK_STATE; + + /* RTW_INFO("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->hwaddr)); */ + + /* to update bcn with tim_bitmap for this station */ + pstapriv->tim_bitmap |= BIT(psta->aid); + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + + if (!pmlmeext->active_keep_alive_check) + continue; + } + } + if (pmlmeext->active_keep_alive_check) { + int stainfo_offset; + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) + chk_alive_list[chk_alive_num++] = stainfo_offset; + + continue; + } + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); + updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + } else { + /* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */ + if (psta->sleepq_len > (NR_XMITFRAME / pstapriv->asoc_list_cnt) + && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME / pstapriv->asoc_list_cnt) / 2) + ) { + RTW_INFO("%s sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n", __func__ + , MAC_ARG(psta->hwaddr) + , psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt); + wakeup_sta_to_xmit(padapter, psta); + } + } + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + if (chk_alive_num) { + + u8 backup_ch = 0, backup_bw, backup_offset; + u8 union_ch = 0, union_bw, union_offset; + u8 switch_channel = _TRUE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + goto bypass_active_keep_alive; + + /* switch to correct channel of current network before issue keep-alive frames */ + if (switch_channel == _TRUE && rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + } + + /* issue null data to check sta alive*/ + for (i = 0; i < chk_alive_num; i++) { + int ret = _FAIL; + + psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); + if (!(psta->state & _FW_LINKED)) + continue; + + if (psta->state & WIFI_SLEEP_STATE) + ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50); + else + ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50); + + psta->keep_alive_trycnt++; + if (ret == _SUCCESS) { + RTW_INFO("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->hwaddr)); + psta->expire_to = pstapriv->expire_to; + psta->keep_alive_trycnt = 0; + continue; + } else if (psta->keep_alive_trycnt <= 3) { + RTW_INFO("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); + psta->expire_to = 1; + continue; + } + + psta->keep_alive_trycnt = 0; + RTW_INFO("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } + + /* back to the original operation channel */ + if (switch_channel && backup_ch > 0) + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + +bypass_active_keep_alive: + ; + } + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); +} + +void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw) +{ + int i; + u8 rf_type; + unsigned char sta_band = 0; + u64 tx_ra_bitmap = 0; + struct ht_priv *psta_ht = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + + if (psta) + psta_ht = &psta->htpriv; + else + return; + + if (!(psta->state & _FW_LINKED)) + return; + + rtw_hal_update_sta_rate_mask(padapter, psta); + tx_ra_bitmap = psta->ra_mask; + + if (pcur_network->Configuration.DSConfig > 14) { + + if (tx_ra_bitmap & 0xffff000) + sta_band |= WIRELESS_11_5N ; + + if (tx_ra_bitmap & 0xff0) + sta_band |= WIRELESS_11A; + + /* 5G band */ + if (psta->vhtpriv.vht_option) + sta_band = WIRELESS_11_5AC; + + } else { + if (tx_ra_bitmap & 0xffff000) + sta_band |= WIRELESS_11_24N; + + if (tx_ra_bitmap & 0xff0) + sta_band |= WIRELESS_11G; + + if (tx_ra_bitmap & 0x0f) + sta_band |= WIRELESS_11B; + } + + psta->wireless_mode = sta_band; + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + + if (psta->aid < NUM_STA) { + RTW_INFO("%s=> mac_id:%d , raid:%d, tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", + __FUNCTION__, psta->mac_id, psta->raid, tx_ra_bitmap, psta->wireless_mode); + + rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); + } else + RTW_INFO("station aid %d exceed the max number\n", psta->aid); + +} + +void update_bmc_sta(_adapter *padapter) +{ + _irqL irqL; + unsigned char network_type; + int supportRateNum = 0; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); + + if (psta) { + psta->aid = 0;/* default set to 0 */ + psta->qos_option = 0; + psta->htpriv.ht_option = _FALSE; + + psta->ieee8021x_blocked = 0; + + _rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); + + /* psta->dot118021XPrivacy = _NO_PRIVACY_; */ /* !!! remove it, because it has been set before this. */ + + /* prepare for add_RATid */ + supportRateNum = rtw_get_rateset_len((u8 *)&pcur_network->SupportedRates); + network_type = rtw_check_network_type((u8 *)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig); + if (IsSupportedTxCCK(network_type)) + network_type = WIRELESS_11B; + else if (network_type == WIRELESS_INVALID) { /* error handling */ + if (pcur_network->Configuration.DSConfig > 14) + network_type = WIRELESS_11A; + else + network_type = WIRELESS_11B; + } + update_sta_basic_rate(psta, network_type); + psta->wireless_mode = network_type; + + rtw_hal_update_sta_rate_mask(padapter, psta); + + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + + _enter_critical_bh(&psta->lock, &irqL); + psta->state = _FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + + rtw_sta_media_status_rpt(padapter, psta, 1); + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); + } else + RTW_INFO("add_RATid_bmc_sta error!\n"); + +} + +/* notes: + * AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode */ +void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; + struct ht_priv *phtpriv_sta = &psta->htpriv; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0; + /* set intf_tag to if1 */ + /* psta->intf_tag = 0; */ + + RTW_INFO("%s\n", __FUNCTION__); + + /*alloc macid when call rtw_alloc_stainfo(),release macid when call rtw_free_stainfo()*/ + + /* ap mode */ + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); + + if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + psta->ieee8021x_blocked = _TRUE; + else + psta->ieee8021x_blocked = _FALSE; + + /* update sta's cap */ + + /* ERP */ + VCS_update(padapter, psta); + /* HT related cap */ + if (phtpriv_sta->ht_option) { + /* check if sta supports rx ampdu */ + phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable; + + phtpriv_sta->rx_ampdu_min_spacing = (phtpriv_sta->ht_cap.ampdu_params_info & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2; + + /* bwmode */ + if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) + psta->bw_mode = CHANNEL_WIDTH_40; + else + psta->bw_mode = CHANNEL_WIDTH_20; + + if (psta->ht_40mhz_intolerant) + psta->bw_mode = CHANNEL_WIDTH_20; + + if (pmlmeext->cur_bwmode < psta->bw_mode) + psta->bw_mode = pmlmeext->cur_bwmode; + + phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; + + /* check if sta support s Short GI 20M */ + if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)) + phtpriv_sta->sgi_20m = _TRUE; + + /* check if sta support s Short GI 40M */ + if ((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) { + if (psta->bw_mode == CHANNEL_WIDTH_40) /* according to psta->bw_mode */ + phtpriv_sta->sgi_40m = _TRUE; + else + phtpriv_sta->sgi_40m = _FALSE; + } + + psta->qos_option = _TRUE; + + /* B0 Config LDPC Coding Capability */ + if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) && + GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) { + SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); + RTW_INFO("Enable HT Tx LDPC for STA(%d)\n", psta->aid); + } + + /* B7 B8 B9 Config STBC setting */ + if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) && + GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) { + SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); + RTW_INFO("Enable HT Tx STBC for STA(%d)\n", psta->aid); + } + + } else { + phtpriv_sta->ampdu_enable = _FALSE; + + phtpriv_sta->sgi_20m = _FALSE; + phtpriv_sta->sgi_40m = _FALSE; + psta->bw_mode = CHANNEL_WIDTH_20; + phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + phtpriv_sta->ldpc_cap = cur_ldpc_cap; + phtpriv_sta->stbc_cap = cur_stbc_cap; + phtpriv_sta->beamform_cap = cur_beamform_cap; + + /* Rx AMPDU */ + send_delba(padapter, 0, psta->hwaddr);/* recipient */ + + /* TX AMPDU */ + send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + phtpriv_sta->agg_enable_bitmap = 0x0;/* reset */ + phtpriv_sta->candidate_tid_bitmap = 0x0;/* reset */ + + update_sta_vht_info_apmode(padapter, psta); + + update_ldpc_stbc_cap(psta); + + /* todo: init other variables */ + + _rtw_memset((void *)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); + + /* add ratid */ + /* add_RATid(padapter, psta); */ /* move to ap_sta_info_defer_update() */ + + _enter_critical_bh(&psta->lock, &irqL); + psta->state |= _FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + +} + +static void update_ap_info(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; + + psta->wireless_mode = pmlmeext->cur_wireless_mode; + + psta->bssratelen = rtw_get_rateset_len(pnetwork->SupportedRates); + _rtw_memcpy(psta->bssrateset, pnetwork->SupportedRates, psta->bssratelen); + + /* HT related cap */ + if (phtpriv_ap->ht_option) { + /* check if sta supports rx ampdu */ + /* phtpriv_ap->ampdu_enable = phtpriv_ap->ampdu_enable; */ + + /* check if sta support s Short GI 20M */ + if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)) + phtpriv_ap->sgi_20m = _TRUE; + /* check if sta support s Short GI 40M */ + if ((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) + phtpriv_ap->sgi_40m = _TRUE; + + psta->qos_option = _TRUE; + } else { + phtpriv_ap->ampdu_enable = _FALSE; + + phtpriv_ap->sgi_20m = _FALSE; + phtpriv_ap->sgi_40m = _FALSE; + } + + psta->bw_mode = pmlmeext->cur_bwmode; + phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset; + + phtpriv_ap->agg_enable_bitmap = 0x0;/* reset */ + phtpriv_ap->candidate_tid_bitmap = 0x0;/* reset */ + + _rtw_memcpy(&psta->htpriv, &pmlmepriv->htpriv, sizeof(struct ht_priv)); + + _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); + + + psta->state |= WIFI_AP_STATE; /* Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 */ +} + +static void rtw_set_hw_wmm_param(_adapter *padapter) +{ + u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; + u8 acm_mask; + u16 TXOP; + u32 acParm, i; + u32 edca[4], inx[4]; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + + acm_mask = 0; + + if (is_supported_5g(pmlmeext->cur_wireless_mode) || + (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) + aSifsTime = 16; + else + aSifsTime = 10; + + if (pmlmeinfo->WMM_enable == 0) { + padapter->mlmepriv.acm_mask = 0; + + AIFS = aSifsTime + (2 * pmlmeinfo->slotTime); + + if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) { + ECWMin = 4; + ECWMax = 10; + } else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) { + ECWMin = 5; + ECWMax = 10; + } else { + ECWMin = 4; + ECWMax = 10; + } + + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + + ECWMin = 2; + ECWMax = 3; + TXOP = 0x2f; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + + } else { + edca[0] = edca[1] = edca[2] = edca[3] = 0; + + /*TODO:*/ + acm_mask = 0; + padapter->mlmepriv.acm_mask = acm_mask; + + AIFS = (7 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 4; + ECWMax = 10; + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + edca[XMIT_BK_QUEUE] = acParm; + RTW_INFO("WMM(BK): %x\n", acParm); + + /* BE */ + AIFS = (3 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 4; + ECWMax = 6; + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + edca[XMIT_BE_QUEUE] = acParm; + RTW_INFO("WMM(BE): %x\n", acParm); + + /* VI */ + AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 3; + ECWMax = 4; + TXOP = 94; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + edca[XMIT_VI_QUEUE] = acParm; + RTW_INFO("WMM(VI): %x\n", acParm); + + /* VO */ + AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 2; + ECWMax = 3; + TXOP = 47; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + edca[XMIT_VO_QUEUE] = acParm; + RTW_INFO("WMM(VO): %x\n", acParm); + + if (padapter->registrypriv.acm_method == 1) + rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); + else + padapter->mlmepriv.acm_mask = acm_mask; + + inx[0] = 0; + inx[1] = 1; + inx[2] = 2; + inx[3] = 3; + + if (pregpriv->wifi_spec == 1) { + u32 j, tmp, change_inx = _FALSE; + + /* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */ + for (i = 0 ; i < 4 ; i++) { + for (j = i + 1 ; j < 4 ; j++) { + /* compare CW and AIFS */ + if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF)) + change_inx = _TRUE; + else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) { + /* compare TXOP */ + if ((edca[j] >> 16) > (edca[i] >> 16)) + change_inx = _TRUE; + } + + if (change_inx) { + tmp = edca[i]; + edca[i] = edca[j]; + edca[j] = tmp; + + tmp = inx[i]; + inx[i] = inx[j]; + inx[j] = tmp; + + change_inx = _FALSE; + } + } + } + } + + for (i = 0 ; i < 4 ; i++) { + pxmitpriv->wmm_para_seq[i] = inx[i]; + RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); + } + + } + +} + +static void update_hw_ht_param(_adapter *padapter) +{ + unsigned char max_AMPDU_len; + unsigned char min_MPDU_spacing; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + RTW_INFO("%s\n", __FUNCTION__); + + /* handle A-MPDU parameter field */ + /* + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k + AMPDU_para [4:2]:Min MPDU Start Spacing + */ + max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); + + /* */ + /* Config SM Power Save setting */ + /* */ + pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; + if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) { + RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__); + } + + /* */ + /* Config current HT Protection mode. */ + /* */ + /* pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; */ + +} + +static void rtw_ap_check_scan(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + u32 delta_time, lifetime; + struct wlan_network *pnetwork = NULL; + WLAN_BSSID_EX *pbss = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + u8 do_scan = _FALSE; + u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED; + + lifetime = SCANQUEUE_LIFETIME; /* 20 sec */ + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + if (rtw_end_of_queue_search(phead, get_next(phead)) == _TRUE) + if (padapter->registrypriv.wifi_spec) { + do_scan = _TRUE; + reason |= RTW_AUTO_SCAN_REASON_2040_BSS; + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + + if (_TRUE == do_scan) { + RTW_INFO("%s : drv scans by itself and wait_completed\n", __func__); + rtw_drv_scan_by_self(padapter, reason); + rtw_scan_wait_completed(padapter); + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) { + delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned); + + if (delta_time < lifetime) { + + uint ie_len = 0; + u8 *pbuf = NULL; + u8 *ie = NULL; + + pbss = &pnetwork->network; + ie = pbss->IEs; + + /*check if HT CAP INFO IE exists or not*/ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss->IELength - _BEACON_IE_OFFSET_)); + if (pbuf == NULL) { + /* HT CAP INFO IE don't exist, it is b/g mode bss.*/ + + if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc)) + ATOMIC_SET(&pmlmepriv->olbc, _TRUE); + + if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) + ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE); + + if (padapter->registrypriv.wifi_spec) + RTW_INFO("%s: %s is a/b/g ap\n", __func__, pnetwork->network.Ssid.Ssid); + } + } + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + pmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/ + +} + +void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter) +{ + WLAN_BSSID_EX *pnetwork = &(adapter->mlmepriv.cur_network.network); + struct sta_info *sta = NULL; + + /* update cur_wireless_mode */ + update_wireless_mode(adapter); + + /* update RRSR and RTS_INIT_RATE register after set channel and bandwidth */ + UpdateBrateTbl(adapter, pnetwork->SupportedRates); + rtw_hal_set_hwreg(adapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates); + + /* update capability after cur_wireless_mode updated */ + update_capinfo(adapter, rtw_get_capability(pnetwork)); + + /* update bc/mc sta_info */ + update_bmc_sta(adapter); + + /* update AP's sta info */ + sta = rtw_get_stainfo(&adapter->stapriv, pnetwork->MacAddress); + if (!sta) { + RTW_INFO(FUNC_ADPT_FMT" !sta for macaddr="MAC_FMT"\n", FUNC_ADPT_ARG(adapter), MAC_ARG(pnetwork->MacAddress)); + rtw_warn_on(1); + return; + } + + update_ap_info(adapter, sta); +} + +void start_bss_network(_adapter *padapter, struct createbss_parm *parm) +{ +#define DUMP_ADAPTERS_STATUS 0 + + u8 val8; + u16 bcn_interval; + u32 acparm; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv *psecuritypriv = &(padapter->securitypriv); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; /* used as input */ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); + struct dvobj_priv *pdvobj = padapter->dvobj; + s16 req_ch = -1, req_bw = -1, req_offset = -1; + bool ch_setting_changed = _FALSE; + u8 ch_to_set = 0, bw_to_set, offset_to_set; + u8 doiqk = _FALSE; + /* use for check ch bw offset can be allowed or not */ + u8 chbw_allow = _TRUE; + + if (parm->req_ch != 0) { + /* bypass other setting, go checking ch, bw, offset */ + req_ch = parm->req_ch; + req_bw = parm->req_bw; + req_offset = parm->req_offset; + goto chbw_decision; + } else { + /* inform this request comes from upper layer */ + req_ch = 0; + } + + bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; + + /* check if there is wps ie, */ + /* if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, */ + /* and at first time the security ie ( RSN/WPA IE) will not include in beacon. */ + if (NULL == rtw_get_wps_ie(pnetwork->IEs + _FIXED_IE_LENGTH_, pnetwork->IELength - _FIXED_IE_LENGTH_, NULL, NULL)) + pmlmeext->bstart_bss = _TRUE; + + /* todo: update wmm, ht cap */ + /* pmlmeinfo->WMM_enable; */ + /* pmlmeinfo->HT_enable; */ + if (pmlmepriv->qospriv.qos_option) + pmlmeinfo->WMM_enable = _TRUE; + if (pmlmepriv->htpriv.ht_option) { + pmlmeinfo->WMM_enable = _TRUE; + pmlmeinfo->HT_enable = _TRUE; + /* pmlmeinfo->HT_info_enable = _TRUE; */ + /* pmlmeinfo->HT_caps_enable = _TRUE; */ + + update_hw_ht_param(padapter); + } + + if (pmlmepriv->vhtpriv.vht_option) { + pmlmeinfo->VHT_enable = _TRUE; + update_hw_vht_param(padapter); + } + + if (pmlmepriv->cur_network.join_res != _TRUE) { /* setting only at first time */ + /* WEP Key will be set before this function, do not clear CAM. */ + if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)) + flush_all_cam_entry(padapter); /* clear CAM */ + } + + /* set MSR to AP_Mode */ + Set_MSR(padapter, _HW_STATE_AP_); + + /* Set BSSID REG */ + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress); + + /* Set EDCA param reg */ + acparm = 0x002F3217; /* VO */ + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); + acparm = 0x005E4317; /* VI */ + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); + /* acparm = 0x00105320; */ /* BE */ + acparm = 0x005ea42b; + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); + acparm = 0x0000A444; /* BK */ + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); + + /* Set Security */ + val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf; + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + + /* Beacon Control related register */ + rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval)); + +chbw_decision: + ch_setting_changed = rtw_ap_chbw_decision(padapter, req_ch, req_bw, req_offset + , &ch_to_set, &bw_to_set, &offset_to_set, &chbw_allow); + + /* let pnetwork_mlmeext == pnetwork_mlme. */ + _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); + + rtw_start_bss_hdl_after_chbw_decided(padapter); + + + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + if (ch_to_set != 0) { + set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set); + rtw_mi_update_union_chan_inf(padapter, ch_to_set, offset_to_set, bw_to_set); + } + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter)); + dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter)); + } + + /* update beacon content only if bstart_bss is _TRUE */ + if (_TRUE == pmlmeext->bstart_bss) { + + _irqL irqL; + + if ((ATOMIC_READ(&pmlmepriv->olbc) == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc_ht) == _TRUE)) { + /* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */ + + pmlmepriv->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK); + pmlmepriv->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS; + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); + } + + update_beacon(padapter, _TIM_IE_, NULL, _FALSE); + + + } + + rtw_scan_wait_completed(padapter); + + /* send beacon */ + if (!rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) { + + /*update_beacon(padapter, _TIM_IE_, NULL, _TRUE);*/ + } + + /*Set EDCA param reg after update cur_wireless_mode & update_capinfo*/ + if (pregpriv->wifi_spec == 1) + rtw_set_hw_wmm_param(padapter); + + /*pmlmeext->bstart_bss = _TRUE;*/ +} + +int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) +{ + int ret = _SUCCESS; + u8 *p; + u8 *pHT_caps_ie = NULL; + u8 *pHT_info_ie = NULL; + u16 cap, ht_cap = _FALSE; + uint ie_len = 0; + int group_cipher, pairwise_cipher; + u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX]; + int supportRateNum = 0; + u8 OUI1[] = {0x00, 0x50, 0xf2, 0x01}; + u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; + u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *ie = pbss_network->IEs; + u8 vht_cap = _FALSE; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 rf_num = 0; + + /* SSID */ + /* Supported rates */ + /* DS Params */ + /* WLAN_EID_COUNTRY */ + /* ERP Information element */ + /* Extended supported rates */ + /* WPA/WPA2 */ + /* Wi-Fi Wireless Multimedia Extensions */ + /* ht_capab, ht_oper */ + /* WPS IE */ + + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return _FAIL; + + if (len > MAX_IE_SZ) + return _FAIL; + + pbss_network->IELength = len; + + _rtw_memset(ie, 0, MAX_IE_SZ); + + _rtw_memcpy(ie, pbuf, pbss_network->IELength); + + if (pbss_network->InfrastructureMode != Ndis802_11APMode) + return _FAIL; + + rtw_ap_check_scan(padapter); + + pbss_network->Rssi = 0; + + _rtw_memcpy(pbss_network->MacAddress, adapter_mac_addr(padapter), ETH_ALEN); + + /* beacon interval */ + p = rtw_get_beacon_interval_from_ie(ie);/* ie + 8; */ /* 8: TimeStamp, 2: Beacon Interval 2:Capability */ + /* pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); */ + pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p); + + /* capability */ + /* cap = *(unsigned short *)rtw_get_capability_from_ie(ie); */ + /* cap = le16_to_cpu(cap); */ + cap = RTW_GET_LE16(ie); + + /* SSID */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) { + _rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len); + pbss_network->Ssid.SsidLength = ie_len; + _rtw_memcpy(padapter->wdinfo.p2p_group_ssid, pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength); + padapter->wdinfo.p2p_group_ssid_len = pbss_network->Ssid.SsidLength; + } + + /* chnnel */ + channel = 0; + pbss_network->Configuration.Length = 0; + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + channel = *(p + 2); + + pbss_network->Configuration.DSConfig = channel; + + _rtw_memset(supportRate, 0, NDIS_802_11_LENGTH_RATES_EX); + /* get supported rates */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p != NULL) { + _rtw_memcpy(supportRate, p + 2, ie_len); + supportRateNum = ie_len; + } + + /* get ext_supported rates */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_); + if (p != NULL) { + _rtw_memcpy(supportRate + supportRateNum, p + 2, ie_len); + supportRateNum += ie_len; + + } + + network_type = rtw_check_network_type(supportRate, supportRateNum, channel); + + rtw_set_supported_rate(pbss_network->SupportedRates, network_type); + + /* parsing ERP_IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p); + + /* update privacy/security */ + if (cap & BIT(4)) + pbss_network->Privacy = 1; + else + pbss_network->Privacy = 0; + + psecuritypriv->wpa_psk = 0; + + /* wpa2 */ + group_cipher = 0; + pairwise_cipher = 0; + psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; + psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) { + if (rtw_parse_wpa2_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + + psecuritypriv->dot8021xalg = 1;/* psk, todo:802.1x */ + psecuritypriv->wpa_psk |= BIT(1); + + psecuritypriv->wpa2_group_cipher = group_cipher; + psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher; + } + + } + + /* wpa */ + ie_len = 0; + group_cipher = 0; + pairwise_cipher = 0; + psecuritypriv->wpa_group_cipher = _NO_PRIVACY_; + psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; + for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) { + p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if ((p) && (_rtw_memcmp(p + 2, OUI1, 4))) { + if (rtw_parse_wpa_ie(p, ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + + psecuritypriv->dot8021xalg = 1;/* psk, todo:802.1x */ + + psecuritypriv->wpa_psk |= BIT(0); + + psecuritypriv->wpa_group_cipher = group_cipher; + psecuritypriv->wpa_pairwise_cipher = pairwise_cipher; + } + + break; + + } + + if ((p == NULL) || (ie_len == 0)) + break; + + } + + /* wmm */ + ie_len = 0; + pmlmepriv->qospriv.qos_option = 0; + if (pregistrypriv->wmm_enable) { + for (p = ie + _BEACON_IE_OFFSET_; ; p += (ie_len + 2)) { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if ((p) && _rtw_memcmp(p + 2, WMM_PARA_IE, 6)) { + pmlmepriv->qospriv.qos_option = 1; + + *(p + 8) |= BIT(7); /* QoS Info, support U-APSD */ + + /* disable all ACM bits since the WMM admission control is not supported */ + *(p + 10) &= ~BIT(4); /* BE */ + *(p + 14) &= ~BIT(4); /* BK */ + *(p + 18) &= ~BIT(4); /* VI */ + *(p + 22) &= ~BIT(4); /* VO */ + + break; + } + + if ((p == NULL) || (ie_len == 0)) + break; + } + } + /* parsing HT_CAP_IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) { + u8 rf_type = 0; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor = MAX_AMPDU_FACTOR_64K; + struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); + + if (0) { + RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter)); + dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); + } + + pHT_caps_ie = p; + + ht_cap = _TRUE; + network_type |= WIRELESS_11_24N; + + rtw_ht_use_default_setting(padapter); + + /* Update HT Capabilities Info field */ + if (pmlmepriv->htpriv.sgi_20m == _FALSE) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20); + + if (pmlmepriv->htpriv.sgi_40m == _FALSE) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40); + + if (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX)) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING); + + if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC); + + if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX)) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R); + + /* Update A-MPDU Parameters field */ + pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR | IEEE80211_HT_CAP_AMPDU_DENSITY); + + if ((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) || + (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (0x07 << 2)); + else + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00); + + rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); /* set Max Rx AMPDU size to 64K */ + + _rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element)); + + /* Update Supported MCS Set field */ + { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + u8 rx_nss = 0; + int i; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); + + /* RX MCS Bitmask */ + switch (rx_nss) { + case 1: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R); + break; + case 2: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R); + break; + case 3: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R); + break; + case 4: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_4R); + break; + default: + RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num); + } + for (i = 0; i < 10; i++) + *(HT_CAP_ELE_RX_MCS_MAP(pht_cap) + i) &= padapter->mlmeextpriv.default_supported_mcs_set[i]; + } + + + _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p + 2, ie_len); + + if (0) { + RTW_INFO(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter)); + dump_ht_cap_ie_content(RTW_DBGDUMP, p + 2, ie_len); + } + } + + /* parsing HT_INFO_IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + pHT_info_ie = p; + switch (network_type) { + case WIRELESS_11B: + pbss_network->NetworkTypeInUse = Ndis802_11DS; + break; + case WIRELESS_11G: + case WIRELESS_11BG: + case WIRELESS_11G_24N: + case WIRELESS_11BG_24N: + pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; + break; + case WIRELESS_11A: + pbss_network->NetworkTypeInUse = Ndis802_11OFDM5; + break; + default: + pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; + break; + } + + pmlmepriv->cur_network.network_type = network_type; + + pmlmepriv->htpriv.ht_option = _FALSE; + + if ((psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) || + (psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_TKIP)) { + /* todo: */ + /* ht_cap = _FALSE; */ + } + + /* ht_cap */ + if (pregistrypriv->ht_enable && ht_cap == _TRUE) { + pmlmepriv->htpriv.ht_option = _TRUE; + pmlmepriv->qospriv.qos_option = 1; + + pmlmepriv->htpriv.ampdu_enable = pregistrypriv->ampdu_enable ? _TRUE : _FALSE; + + HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie); + + HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie); + } + + + /* Parsing VHT CAP IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + vht_cap = _TRUE; + /* Parsing VHT OPERATION IE */ + + pmlmepriv->vhtpriv.vht_option = _FALSE; + /* if channel in 5G band, then add vht ie . */ + if ((pbss_network->Configuration.DSConfig > 14) + && (pmlmepriv->htpriv.ht_option == _TRUE) + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) + ) { + if (vht_cap == _TRUE) + pmlmepriv->vhtpriv.vht_option = _TRUE; + else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) { + u8 cap_len, operation_len; + + rtw_vht_use_default_setting(padapter); + + { + /* VHT Operation mode notifiy bit in Extended IE (127) */ + uint len = 0; + + SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1); + pmlmepriv->ext_capab_ie_len = 10; + rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); + pbss_network->IELength += pmlmepriv->ext_capab_ie_len; + } + + /* VHT Capabilities element */ + cap_len = rtw_build_vht_cap_ie(padapter, pbss_network->IEs + pbss_network->IELength); + pbss_network->IELength += cap_len; + + /* VHT Operation element */ + operation_len = rtw_build_vht_operation_ie(padapter, pbss_network->IEs + pbss_network->IELength, pbss_network->Configuration.DSConfig); + pbss_network->IELength += operation_len; + + pmlmepriv->vhtpriv.vht_option = _TRUE; + } + } + + if(pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1) { + uint len = 0; + + SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1); + pmlmepriv->ext_capab_ie_len = 10; + rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); + pbss_network->IELength += pmlmepriv->ext_capab_ie_len; + } + + pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); + + rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_ + , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset); + rtw_warn_on(pmlmepriv->ori_ch == 0); + + { + /* alloc sta_info for ap itself */ + + struct sta_info *sta; + + sta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress); + if (!sta) { + sta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress); + if (sta == NULL) + return _FAIL; + } + } + + rtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK); + { + int sk_band = RTW_GET_SCAN_BAND_SKIP(padapter); + + if (sk_band) + RTW_CLR_SCAN_BAND_SKIP(padapter, sk_band); + } + + rtw_indicate_connect(padapter); + + pmlmepriv->cur_network.join_res = _TRUE;/* for check if already set beacon */ + + /* update bc/mc sta_info */ + /* update_bmc_sta(padapter); */ + + return ret; + +} + +void rtw_macaddr_acl_init(_adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl = &stapriv->acl_list; + _queue *acl_node_q = &acl->acl_node_q; + int i; + _irqL irqL; + + _enter_critical_bh(&(acl_node_q->lock), &irqL); + _rtw_init_listhead(&(acl_node_q->queue)); + acl->num = 0; + acl->mode = RTW_ACL_MODE_DISABLED; + for (i = 0; i < NUM_ACL; i++) { + _rtw_init_listhead(&acl->aclnode[i].list); + acl->aclnode[i].valid = _FALSE; + } + _exit_critical_bh(&(acl_node_q->lock), &irqL); +} + +void rtw_macaddr_acl_deinit(_adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl = &stapriv->acl_list; + _queue *acl_node_q = &acl->acl_node_q; + _irqL irqL; + _list *head, *list; + struct rtw_wlan_acl_node *acl_node; + + _enter_critical_bh(&(acl_node_q->lock), &irqL); + head = get_list_head(acl_node_q); + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list); + list = get_next(list); + + if (acl_node->valid == _TRUE) { + acl_node->valid = _FALSE; + rtw_list_delete(&acl_node->list); + acl->num--; + } + } + _exit_critical_bh(&(acl_node_q->lock), &irqL); + + rtw_warn_on(acl->num); + acl->mode = RTW_ACL_MODE_DISABLED; +} + +void rtw_set_macaddr_acl(_adapter *adapter, int mode) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl = &stapriv->acl_list; + + RTW_INFO(FUNC_ADPT_FMT" mode=%d\n", FUNC_ADPT_ARG(adapter), mode); + + acl->mode = mode; + + if (mode == RTW_ACL_MODE_DISABLED) + rtw_macaddr_acl_deinit(adapter); +} + +int rtw_acl_add_sta(_adapter *adapter, const u8 *addr) +{ + _irqL irqL; + _list *list, *head; + u8 existed = 0; + int i = -1, ret = 0; + struct rtw_wlan_acl_node *acl_node; + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl = &stapriv->acl_list; + _queue *acl_node_q = &acl->acl_node_q; + + _enter_critical_bh(&(acl_node_q->lock), &irqL); + + head = get_list_head(acl_node_q); + list = get_next(head); + + /* search for existed entry */ + while (rtw_end_of_queue_search(head, list) == _FALSE) { + acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list); + list = get_next(list); + + if (_rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) { + if (acl_node->valid == _TRUE) { + existed = 1; + break; + } + } + } + if (existed) + goto release_lock; + + if (acl->num >= NUM_ACL) + goto release_lock; + + /* find empty one and use */ + for (i = 0; i < NUM_ACL; i++) { + + acl_node = &acl->aclnode[i]; + if (acl_node->valid == _FALSE) { + + _rtw_init_listhead(&acl_node->list); + _rtw_memcpy(acl_node->addr, addr, ETH_ALEN); + acl_node->valid = _TRUE; + + rtw_list_insert_tail(&acl_node->list, get_list_head(acl_node_q)); + acl->num++; + break; + } + } + +release_lock: + _exit_critical_bh(&(acl_node_q->lock), &irqL); + + if (!existed && (i < 0 || i >= NUM_ACL)) + ret = -1; + + RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr) + , (existed ? "existed" : ((i < 0 || i >= NUM_ACL) ? "no room" : "added")) + , acl->num); + + return ret; +} + +int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr) +{ + _irqL irqL; + _list *list, *head; + int ret = 0; + struct rtw_wlan_acl_node *acl_node; + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl = &stapriv->acl_list; + _queue *acl_node_q = &acl->acl_node_q; + u8 is_baddr = is_broadcast_mac_addr(addr); + u8 match = 0; + + _enter_critical_bh(&(acl_node_q->lock), &irqL); + + head = get_list_head(acl_node_q); + list = get_next(head); + + while (rtw_end_of_queue_search(head, list) == _FALSE) { + acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list); + list = get_next(list); + + if (is_baddr || _rtw_memcmp(acl_node->addr, addr, ETH_ALEN)) { + if (acl_node->valid == _TRUE) { + acl_node->valid = _FALSE; + rtw_list_delete(&acl_node->list); + acl->num--; + match = 1; + } + } + } + + _exit_critical_bh(&(acl_node_q->lock), &irqL); + + RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" %s (acl_num=%d)\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr) + , is_baddr ? "clear all" : (match ? "match" : "no found") + , acl->num); + + return ret; +} + +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) +{ + struct cmd_obj *ph2c; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if (psetstakey_para == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); + + psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; + + _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); + + _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx) +{ + u8 keylen; + struct cmd_obj *pcmd; + struct setkey_parm *psetkeyparm; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + int res = _SUCCESS; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd == NULL) { + res = _FAIL; + goto exit; + } + psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm)); + if (psetkeyparm == NULL) { + rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); + + psetkeyparm->keyid = (u8)keyid; + if (is_wep_enc(alg)) + padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); + + psetkeyparm->algorithm = alg; + + psetkeyparm->set_tx = set_tx; + + switch (alg) { + case _WEP40_: + keylen = 5; + break; + case _WEP104_: + keylen = 13; + break; + case _TKIP_: + case _TKIP_WTMIC_: + case _AES_: + default: + keylen = 16; + } + + _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen); + + pcmd->cmdcode = _SetKey_CMD_; + pcmd->parmbuf = (u8 *)psetkeyparm; + pcmd->cmdsz = (sizeof(struct setkey_parm)); + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + _rtw_init_listhead(&pcmd->list); + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + +exit: + + return res; +} + +int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid) +{ + RTW_INFO("%s\n", __FUNCTION__); + + return rtw_ap_set_key(padapter, key, alg, keyid, 1); +} + +int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx) +{ + u8 alg; + + switch (keylen) { + case 5: + alg = _WEP40_; + break; + case 13: + alg = _WEP104_; + break; + default: + alg = _NO_PRIVACY_; + } + + RTW_INFO("%s\n", __FUNCTION__); + + return rtw_ap_set_key(padapter, key, alg, keyid, set_tx); +} + +static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, u32 sta_info_type) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + RTW_INFO("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->hwaddr), sta_info_type); + + if (sta_info_type & STA_INFO_UPDATE_BW) { + + if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) { + if (pmlmepriv->sw_to_20mhz) { + psta->bw_mode = CHANNEL_WIDTH_20; + /*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/ + psta->htpriv.sgi_40m = _FALSE; + } else { + /*TODO: Switch back to 40MHZ?80MHZ*/ + } + } + } + + /* + if (sta_info_type & STA_INFO_UPDATE_RATE) { + + } + */ + + if (sta_info_type & STA_INFO_UPDATE_PROTECTION_MODE) + VCS_update(padapter, psta); + + /* + if (sta_info_type & STA_INFO_UPDATE_CAP) { + + } + + if (sta_info_type & STA_INFO_UPDATE_HT_CAP) { + + } + + if (sta_info_type & STA_INFO_UPDATE_VHT_CAP) { + + } + */ + +} + +static void update_bcn_ext_capab_ie(_adapter *padapter) +{ + sint ie_len = 0; + unsigned char *pbuf; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + u8 *ie = pnetwork->IEs; + u8 null_extcap_data[8] = {0}; + + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) + rtw_remove_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_); + + if ((pmlmepriv->ext_capab_ie_len > 0) && + (_rtw_memcmp(pmlmepriv->ext_capab_ie_data, null_extcap_data, sizeof(null_extcap_data)) == _FALSE)) + rtw_add_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_, pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len); + +} + +static void update_bcn_fixed_ie(_adapter *padapter) +{ + RTW_INFO("%s\n", __FUNCTION__); + +} + +static void update_bcn_erpinfo_ie(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + unsigned char *p, *ie = pnetwork->IEs; + u32 len = 0; + + RTW_INFO("%s, ERP_enable=%d\n", __FUNCTION__, pmlmeinfo->ERP_enable); + + if (!pmlmeinfo->ERP_enable) + return; + + /* parsing ERP_IE */ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (p && len > 0) { + PNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p; + + if (pmlmepriv->num_sta_non_erp == 1) + pIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION; + else + pIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT | RTW_ERP_INFO_USE_PROTECTION); + + if (pmlmepriv->num_sta_no_short_preamble > 0) + pIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE; + else + pIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE); + + ERP_IE_handler(padapter, pIE); + } + +} + +static void update_bcn_htcap_ie(_adapter *padapter) +{ + RTW_INFO("%s\n", __FUNCTION__); + +} + +static void update_bcn_htinfo_ie(_adapter *padapter) +{ + /* + u8 beacon_updated = _FALSE; + u32 sta_info_update_type = STA_INFO_UPDATE_NONE; + */ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + unsigned char *p, *ie = pnetwork->IEs; + u32 len = 0; + + if (pmlmepriv->htpriv.ht_option == _FALSE) + return; + + if (pmlmeinfo->HT_info_enable != 1) + return; + + RTW_INFO("%s current operation mode=0x%X\n", + __FUNCTION__, pmlmepriv->ht_op_mode); + + RTW_INFO("num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\n", + pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, ATOMIC_READ(&pmlmepriv->olbc)); + + /*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (p && len > 0) { + struct HT_info_element *pht_info = NULL; + + pht_info = (struct HT_info_element *)(p + 2); + + /* for STA Channel Width/Secondary Channel Offset*/ + if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) { + if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE) + || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (ATOMIC_READ(&pmlmepriv->olbc) == _TRUE)) { + SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0); + SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0); + + pmlmepriv->sw_to_20mhz = 1; + /* + sta_info_update_type |= STA_INFO_UPDATE_BW; + beacon_updated = _TRUE; + */ + + RTW_INFO("%s:switching to 20Mhz\n", __FUNCTION__); + + /*TODO : cur_bwmode/cur_ch_offset switches to 20Mhz*/ + } + } else { + + if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE) + && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (ATOMIC_READ(&pmlmepriv->olbc) == _FALSE)) { + + if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) { + + SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 1); + + SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, + (pmlmeext->cur_ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ? + HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE : HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW); + + pmlmepriv->sw_to_20mhz = 0; + /* + sta_info_update_type |= STA_INFO_UPDATE_BW; + beacon_updated = _TRUE; + */ + + RTW_INFO("%s:switching back to 40Mhz\n", __FUNCTION__); + } + } + } + + /* to update ht_op_mode*/ + *(u16 *)(pht_info->infos + 1) = cpu_to_le16(pmlmepriv->ht_op_mode); + + } + + /*associated_clients_update(padapter, beacon_updated, sta_info_update_type);*/ + +} + +static void update_bcn_rsn_ie(_adapter *padapter) +{ + RTW_INFO("%s\n", __FUNCTION__); + +} + +static void update_bcn_wpa_ie(_adapter *padapter) +{ + RTW_INFO("%s\n", __FUNCTION__); + +} + +static void update_bcn_wmm_ie(_adapter *padapter) +{ + RTW_INFO("%s\n", __FUNCTION__); + +} + +static void update_bcn_wps_ie(_adapter *padapter) +{ + u8 *pwps_ie = NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie = NULL; + uint wps_ielen = 0, wps_offset, remainder_ielen; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + unsigned char *ie = pnetwork->IEs; + u32 ielen = pnetwork->IELength; + + RTW_INFO("%s\n", __FUNCTION__); + + pwps_ie = rtw_get_wps_ie(ie + _FIXED_IE_LENGTH_, ielen - _FIXED_IE_LENGTH_, NULL, &wps_ielen); + + if (pwps_ie == NULL || wps_ielen == 0) + return; + + pwps_ie_src = pmlmepriv->wps_beacon_ie; + if (pwps_ie_src == NULL) + return; + + wps_offset = (uint)(pwps_ie - ie); + + premainder_ie = pwps_ie + wps_ielen; + + remainder_ielen = ielen - wps_offset - wps_ielen; + + if (remainder_ielen > 0) { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if (pbackup_remainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + wps_ielen = (uint)pwps_ie_src[1];/* to get ie data len */ + if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) { + _rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen + 2); + pwps_ie += (wps_ielen + 2); + + if (pbackup_remainder_ie) + _rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen); + + /* update IELength */ + pnetwork->IELength = wps_offset + (wps_ielen + 2) + remainder_ielen; + } + + if (pbackup_remainder_ie) + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + + /* deal with the case without set_tx_beacon_cmd() in update_beacon() */ + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + u8 sr = 0; + rtw_get_wps_attr_content(pwps_ie_src, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); + + if (sr) { + set_fwstate(pmlmepriv, WIFI_UNDER_WPS); + RTW_INFO("%s, set WIFI_UNDER_WPS\n", __func__); + } else { + clr_fwstate(pmlmepriv, WIFI_UNDER_WPS); + RTW_INFO("%s, clr WIFI_UNDER_WPS\n", __func__); + } + } +} + +static void update_bcn_p2p_ie(_adapter *padapter) +{ + +} + +static void update_bcn_vendor_spec_ie(_adapter *padapter, u8 *oui) +{ + RTW_INFO("%s\n", __FUNCTION__); + + if (_rtw_memcmp(RTW_WPA_OUI, oui, 4)) + update_bcn_wpa_ie(padapter); + else if (_rtw_memcmp(WMM_OUI, oui, 4)) + update_bcn_wmm_ie(padapter); + else if (_rtw_memcmp(WPS_OUI, oui, 4)) + update_bcn_wps_ie(padapter); + else if (_rtw_memcmp(P2P_OUI, oui, 4)) + update_bcn_p2p_ie(padapter); + else + RTW_INFO("unknown OUI type!\n"); + +} + +void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv; + struct mlme_ext_priv *pmlmeext; + /* struct mlme_ext_info *pmlmeinfo; */ + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + if (!padapter) + return; + + pmlmepriv = &(padapter->mlmepriv); + pmlmeext = &(padapter->mlmeextpriv); + /* pmlmeinfo = &(pmlmeext->mlmext_info); */ + + if (_FALSE == pmlmeext->bstart_bss) + return; + + _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); + + switch (ie_id) { + case 0xFF: + + update_bcn_fixed_ie(padapter);/* 8: TimeStamp, 2: Beacon Interval 2:Capability */ + + break; + + case _TIM_IE_: + + update_BCNTIM(padapter); + + break; + + case _ERPINFO_IE_: + + update_bcn_erpinfo_ie(padapter); + + break; + + case _HT_CAPABILITY_IE_: + + update_bcn_htcap_ie(padapter); + + break; + + case _RSN_IE_2_: + + update_bcn_rsn_ie(padapter); + + break; + + case _HT_ADD_INFO_IE_: + + update_bcn_htinfo_ie(padapter); + + break; + + case _EXT_CAP_IE_: + + update_bcn_ext_capab_ie(padapter); + + break; + + case _VENDOR_SPECIFIC_IE_: + + update_bcn_vendor_spec_ie(padapter, oui); + + break; + + default: + break; + } + + pmlmepriv->update_bcn = _TRUE; + + _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); +} + + +void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len) +{ + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + uint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta == NULL) + return; + + category = frame_body[0]; + action = frame_body[1]; + + if (frame_body_len > 0) { + if ((frame_body[2] == EID_BSSCoexistence) && (frame_body[3] > 0)) { + u8 ie_data = frame_body[4]; + + if (ie_data & RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL) { + if (psta->ht_40mhz_intolerant == 0) { + psta->ht_40mhz_intolerant = 1; + pmlmepriv->num_sta_40mhz_intolerant++; + beacon_updated = _TRUE; + } + } else if (ie_data & RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ) { + if (pmlmepriv->ht_20mhz_width_req == _FALSE) { + pmlmepriv->ht_20mhz_width_req = _TRUE; + beacon_updated = _TRUE; + } + } else + beacon_updated = _FALSE; + } + } + + if (frame_body_len > 8) { + /* if EID_BSSIntolerantChlReport ie exists */ + if ((frame_body[5] == EID_BSSIntolerantChlReport) && (frame_body[6] > 0)) { + /*todo:*/ + if (pmlmepriv->ht_intolerant_ch_reported == _FALSE) { + pmlmepriv->ht_intolerant_ch_reported = _TRUE; + beacon_updated = _TRUE; + } + } + } + + if (beacon_updated) { + + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + + associated_stainfo_update(padapter, psta, STA_INFO_UPDATE_BW); + } + +} + +void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field) +{ + u8 e_field, m_field; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + psta = rtw_get_stainfo(pstapriv, ta); + if (psta == NULL) + return; + + e_field = (ctrl_field & BIT(0)) ? 1 : 0; + m_field = (ctrl_field & BIT(1)) ? 1 : 0; + + if (e_field) { + + /* enable */ + /* 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + + if (m_field) /*mode*/ + psta->htpriv.smps_cap = 1; + else + psta->htpriv.smps_cap = 0; + } else { + /*disable*/ + psta->htpriv.smps_cap = 3; + } + + rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); + +} + +/* +op_mode +Set to 0 (HT pure) under the followign conditions + - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or + - all STAs in the BSS are 20 MHz HT in 20 MHz BSS +Set to 1 (HT non-member protection) if there may be non-HT STAs + in both the primary and the secondary channel +Set to 2 if only HT STAs are associated in BSS, + however and at least one 20 MHz HT STA is associated +Set to 3 (HT mixed mode) when one or more non-HT STAs are associated + (currently non-GF HT station is considered as non-HT STA also) +*/ +int rtw_ht_operation_update(_adapter *padapter) +{ + u16 cur_op_mode, new_op_mode; + int op_mode_changes = 0; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; + + if (pmlmepriv->htpriv.ht_option == _FALSE) + return 0; + + /*if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed) + return 0;*/ + + RTW_INFO("%s current operation mode=0x%X\n", + __FUNCTION__, pmlmepriv->ht_op_mode); + + if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) + && pmlmepriv->num_sta_ht_no_gf) { + pmlmepriv->ht_op_mode |= + HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; + op_mode_changes++; + } else if ((pmlmepriv->ht_op_mode & + HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) && + pmlmepriv->num_sta_ht_no_gf == 0) { + pmlmepriv->ht_op_mode &= + ~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; + op_mode_changes++; + } + + if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && + (pmlmepriv->num_sta_no_ht || ATOMIC_READ(&pmlmepriv->olbc_ht))) { + pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; + op_mode_changes++; + } else if ((pmlmepriv->ht_op_mode & + HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && + (pmlmepriv->num_sta_no_ht == 0 && !ATOMIC_READ(&pmlmepriv->olbc_ht))) { + pmlmepriv->ht_op_mode &= + ~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; + op_mode_changes++; + } + + /* Note: currently we switch to the MIXED op mode if HT non-greenfield + * station is associated. Probably it's a theoretical case, since + * it looks like all known HT STAs support greenfield. + */ + new_op_mode = 0; + if (pmlmepriv->num_sta_no_ht /*|| + (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/) + new_op_mode = OP_MODE_MIXED; + else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH) + && pmlmepriv->num_sta_ht_20mhz) + new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED; + else if (ATOMIC_READ(&pmlmepriv->olbc_ht)) + new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS; + else + new_op_mode = OP_MODE_PURE; + + cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK; + if (cur_op_mode != new_op_mode) { + pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK; + pmlmepriv->ht_op_mode |= new_op_mode; + op_mode_changes++; + } + + RTW_INFO("%s new operation mode=0x%X changes=%d\n", + __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes); + + return op_mode_changes; + +} + + +void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type) +{ + /* update associcated stations cap. */ + if (updated == _TRUE) { + _irqL irqL; + _list *phead, *plist; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + /* check asoc_queue */ + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + + plist = get_next(plist); + + associated_stainfo_update(padapter, psta, sta_info_type); + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } + +} + +/* called > TSR LEVEL for USB or SDIO Interface*/ +void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) +{ + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + if (!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) { + if (!psta->no_short_preamble_set) { + psta->no_short_preamble_set = 1; + + pmlmepriv->num_sta_no_short_preamble++; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_preamble == 1)) { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + + } + } else { + if (psta->no_short_preamble_set) { + psta->no_short_preamble_set = 0; + + pmlmepriv->num_sta_no_short_preamble--; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_preamble == 0)) { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + + } + } + + if (psta->flags & WLAN_STA_NONERP) { + if (!psta->nonerp_set) { + psta->nonerp_set = 1; + + pmlmepriv->num_sta_non_erp++; + + if (pmlmepriv->num_sta_non_erp == 1) { + beacon_updated = _TRUE; + update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + } + } + + } else { + if (psta->nonerp_set) { + psta->nonerp_set = 0; + + pmlmepriv->num_sta_non_erp--; + + if (pmlmepriv->num_sta_non_erp == 0) { + beacon_updated = _TRUE; + update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + } + } + + } + + if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) { + if (!psta->no_short_slot_time_set) { + psta->no_short_slot_time_set = 1; + + pmlmepriv->num_sta_no_short_slot_time++; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_slot_time == 1)) { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + + } + } else { + if (psta->no_short_slot_time_set) { + psta->no_short_slot_time_set = 0; + + pmlmepriv->num_sta_no_short_slot_time--; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_slot_time == 0)) { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + } + } + + + if (psta->flags & WLAN_STA_HT) { + u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); + + RTW_INFO("HT: STA " MAC_FMT " HT Capabilities " + "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab); + + if (psta->no_ht_set) { + psta->no_ht_set = 0; + pmlmepriv->num_sta_no_ht--; + } + + if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) { + if (!psta->no_ht_gf_set) { + psta->no_ht_gf_set = 1; + pmlmepriv->num_sta_ht_no_gf++; + } + RTW_INFO("%s STA " MAC_FMT " - no " + "greenfield, num of non-gf stations %d\n", + __FUNCTION__, MAC_ARG(psta->hwaddr), + pmlmepriv->num_sta_ht_no_gf); + } + + if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) { + if (!psta->ht_20mhz_set) { + psta->ht_20mhz_set = 1; + pmlmepriv->num_sta_ht_20mhz++; + } + RTW_INFO("%s STA " MAC_FMT " - 20 MHz HT, " + "num of 20MHz HT STAs %d\n", + __FUNCTION__, MAC_ARG(psta->hwaddr), + pmlmepriv->num_sta_ht_20mhz); + } + + } else { + if (!psta->no_ht_set) { + psta->no_ht_set = 1; + pmlmepriv->num_sta_no_ht++; + } + if (pmlmepriv->htpriv.ht_option == _TRUE) { + RTW_INFO("%s STA " MAC_FMT + " - no HT, num of non-HT stations %d\n", + __FUNCTION__, MAC_ARG(psta->hwaddr), + pmlmepriv->num_sta_no_ht); + } + } + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + /*beacon_updated = _TRUE;*/ + } + + + /* update associcated stations cap. */ + associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); + + RTW_INFO("%s, updated=%d\n", __func__, beacon_updated); + +} + +u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) +{ + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + if (!psta) + return beacon_updated; + + if (psta->no_short_preamble_set) { + psta->no_short_preamble_set = 0; + pmlmepriv->num_sta_no_short_preamble--; + if (pmlmeext->cur_wireless_mode > WIRELESS_11B + && pmlmepriv->num_sta_no_short_preamble == 0) { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + } + + if (psta->nonerp_set) { + psta->nonerp_set = 0; + pmlmepriv->num_sta_non_erp--; + if (pmlmepriv->num_sta_non_erp == 0) { + beacon_updated = _TRUE; + update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + } + } + + if (psta->no_short_slot_time_set) { + psta->no_short_slot_time_set = 0; + pmlmepriv->num_sta_no_short_slot_time--; + if (pmlmeext->cur_wireless_mode > WIRELESS_11B + && pmlmepriv->num_sta_no_short_slot_time == 0) { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + } + + + if (psta->no_ht_gf_set) { + psta->no_ht_gf_set = 0; + pmlmepriv->num_sta_ht_no_gf--; + } + + if (psta->no_ht_set) { + psta->no_ht_set = 0; + pmlmepriv->num_sta_no_ht--; + } + + if (psta->ht_20mhz_set) { + psta->ht_20mhz_set = 0; + pmlmepriv->num_sta_ht_20mhz--; + } + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + } + + RTW_INFO("%s, updated=%d\n", __func__, beacon_updated); + + return beacon_updated; +} + +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue) +{ + _irqL irqL; + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + if (!psta) + return beacon_updated; + + if (active == _TRUE) { + /* tear down Rx AMPDU */ + send_delba(padapter, 0, psta->hwaddr);/* recipient */ + + /* tear down TX AMPDU */ + send_delba(padapter, 1, psta->hwaddr);/* */ /* originator */ + + + issue_deauth(padapter, psta->hwaddr, reason); + } + + + psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ + psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ + + /* clear cam entry / key */ + rtw_clearstakey_cmd(padapter, psta, enqueue); + + _enter_critical_bh(&psta->lock, &irqL); + psta->state &= ~_FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + + { + rtw_indicate_sta_disassoc_event(padapter, psta); + } + + report_del_sta_event(padapter, psta->hwaddr, reason, enqueue, _FALSE); + + beacon_updated = bss_cap_update_on_sta_leave(padapter, psta); + + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(padapter, psta); + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + + return beacon_updated; + +} + +int rtw_sta_flush(_adapter *padapter, bool enqueue) +{ + _irqL irqL; + _list *phead, *plist; + int ret = 0; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 flush_num = 0; + char flush_list[NUM_STA]; + int i; + + if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + return ret; + + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); + + /* pick sta from sta asoc_queue */ + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) + flush_list[flush_num++] = stainfo_offset; + else + rtw_warn_on(1); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + /* call ap_free_sta() for each sta picked */ + for (i = 0; i < flush_num; i++) { + psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]); + ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue); + } + + issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); + + associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL); + + return ret; +} + +/* called > TSR LEVEL for USB or SDIO Interface*/ +void sta_info_update(_adapter *padapter, struct sta_info *psta) +{ + int flags = psta->flags; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + /* update wmm cap. */ + if (WLAN_STA_WME & flags) + psta->qos_option = 1; + else + psta->qos_option = 0; + + if (pmlmepriv->qospriv.qos_option == 0) + psta->qos_option = 0; + + /* update 802.11n ht cap. */ + if (WLAN_STA_HT & flags) { + psta->htpriv.ht_option = _TRUE; + psta->qos_option = 1; + + psta->htpriv.smps_cap = (psta->htpriv.ht_cap.cap_info & IEEE80211_HT_CAP_SM_PS) >> 2; + } else + psta->htpriv.ht_option = _FALSE; + + if (pmlmepriv->htpriv.ht_option == _FALSE) + psta->htpriv.ht_option = _FALSE; + + /* update 802.11AC vht cap. */ + if (WLAN_STA_VHT & flags) + psta->vhtpriv.vht_option = _TRUE; + else + psta->vhtpriv.vht_option = _FALSE; + + if (pmlmepriv->vhtpriv.vht_option == _FALSE) + psta->vhtpriv.vht_option = _FALSE; + + update_sta_info_apmode(padapter, psta); +} + +/* called >= TSR LEVEL for USB or SDIO Interface*/ +void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) +{ + if (psta->state & _FW_LINKED) + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); /* DM_RATR_STA_INIT */ +} +/* restore hw setting from sw data structures */ +void rtw_ap_restore_network(_adapter *padapter) +{ + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + struct security_priv *psecuritypriv = &(padapter->securitypriv); + _irqL irqL; + _list *phead, *plist; + u8 chk_alive_num = 0; + char chk_alive_list[NUM_STA]; + int i; + + rtw_setopmode_cmd(padapter, Ndis802_11APMode, _FALSE); + + set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + rtw_startbss_cmd(padapter, RTW_CMDF_DIRECTLY); + + if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { + /* restore group key, WEP keys is restored in ips_leave() */ + rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0, _FALSE); + } + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) + chk_alive_list[chk_alive_num++] = stainfo_offset; + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + for (i = 0; i < chk_alive_num; i++) { + psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); + + if (psta == NULL) + RTW_INFO(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter)); + else if (psta->state & _FW_LINKED) { + rtw_sta_media_status_rpt(padapter, psta, 1); + Update_RA_Entry(padapter, psta); + /* pairwise key */ + /* per sta pairwise key and settings */ + if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE); + } + } + +} + +void start_ap_mode(_adapter *padapter) +{ + int i; + struct sta_info *psta = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct security_priv *psecuritypriv = &padapter->securitypriv; + + pmlmepriv->update_bcn = _FALSE; + + /*init_mlme_ap_info(padapter);*/ + + pmlmeext->bstart_bss = _FALSE; + + pmlmepriv->num_sta_non_erp = 0; + + pmlmepriv->num_sta_no_short_slot_time = 0; + + pmlmepriv->num_sta_no_short_preamble = 0; + + pmlmepriv->num_sta_ht_no_gf = 0; + pmlmepriv->num_sta_no_ht = 0; + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_enable = 0; + + pmlmepriv->num_sta_ht_20mhz = 0; + pmlmepriv->num_sta_40mhz_intolerant = 0; + ATOMIC_SET(&pmlmepriv->olbc, _FALSE); + ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE); + + pmlmepriv->ht_20mhz_width_req = _FALSE; + pmlmepriv->ht_intolerant_ch_reported = _FALSE; + pmlmepriv->ht_op_mode = 0; + pmlmepriv->sw_to_20mhz = 0; + + _rtw_memset(pmlmepriv->ext_capab_ie_data, 0, sizeof(pmlmepriv->ext_capab_ie_data)); + pmlmepriv->ext_capab_ie_len = 0; + + + for (i = 0 ; i < NUM_STA ; i++) + pstapriv->sta_aid[i] = NULL; + + rtw_macaddr_acl_init(padapter); + + psta = rtw_get_bcmc_stainfo(padapter); + /*_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ + if (psta) + rtw_free_stainfo(padapter, psta); + /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ + + rtw_init_bcmc_stainfo(padapter); + + if (rtw_mi_get_ap_num(padapter)) + RTW_SET_SCAN_BAND_SKIP(padapter, BAND_5G); + +} + +void stop_ap_mode(_adapter *padapter) +{ + _irqL irqL; + struct sta_info *psta = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct dvobj_priv *pdvobj = padapter->dvobj; + + RTW_INFO("%s -"ADPT_FMT"\n", __func__, ADPT_ARG(padapter)); + + pmlmepriv->update_bcn = _FALSE; + /*pmlmeext->bstart_bss = _FALSE;*/ + padapter->netif_up = _FALSE; + /* _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); */ + + /* reset and init security priv , this can refine with rtw_reset_securitypriv */ + _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof(struct security_priv)); + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; + + + /* free scan queue */ + rtw_free_network_queue(padapter, _TRUE); + + rtw_macaddr_acl_deinit(padapter); + + rtw_sta_flush(padapter, _TRUE); + + /* free_assoc_sta_resources */ + rtw_free_all_stainfo(padapter); + + psta = rtw_get_bcmc_stainfo(padapter); + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(padapter, psta); + /*_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL);*/ + + rtw_free_mlme_priv_ie_data(pmlmepriv); + + + pmlmeext->bstart_bss = _FALSE; + + rtw_btcoex_MediaStatusNotify(padapter, 0); /* disconnect */ + +} + + +void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset) +{ +#define UPDATE_VHT_CAP 1 +#define UPDATE_HT_CAP 1 + + { + struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv; + u8 *vht_cap_ie, *vht_op_ie; + int vht_cap_ielen, vht_op_ielen; + u8 center_freq; + + vht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTCapability, &vht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + vht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTOperation, &vht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + center_freq = rtw_get_center_ch(ch, bw, offset); + + /* update vht cap ie */ + if (vht_cap_ie && vht_cap_ielen) { + /* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m) + SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1); + else */ + SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0); + + if (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m) + SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1); + else + SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0); + } + + /* update vht op ie */ + if (vht_op_ie && vht_op_ielen) { + if (bw < CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); + } else if (bw == CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 1); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, center_freq); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); + } else { + RTW_ERR(FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw); + rtw_warn_on(1); + } + } + } + { + struct ht_priv *htpriv = &adapter->mlmepriv.htpriv; + u8 *ht_cap_ie, *ht_op_ie; + int ht_cap_ielen, ht_op_ielen; + + ht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTCapability, &ht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + ht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTInfo, &ht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + + /* update ht cap ie */ + if (ht_cap_ie && ht_cap_ielen) { + if (bw >= CHANNEL_WIDTH_40) + SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1); + else + SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 0); + + if (bw >= CHANNEL_WIDTH_40 && htpriv->sgi_40m) + SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 1); + else + SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 0); + + if (htpriv->sgi_20m) + SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1); + else + SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0); + } + + /* update ht op ie */ + if (ht_op_ie && ht_op_ielen) { + SET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2, ch); + switch (offset) { + case HAL_PRIME_CHNL_OFFSET_LOWER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCA); + break; + case HAL_PRIME_CHNL_OFFSET_UPPER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCB); + break; + case HAL_PRIME_CHNL_OFFSET_DONT_CARE: + default: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCN); + break; + } + + if (bw >= CHANNEL_WIDTH_40) + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 1); + else + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 0); + } + } + + { + u8 *p; + int ie_len; + u8 old_ch = bss->Configuration.DSConfig; + bool change_band = _FALSE; + + if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14)) + change_band = _TRUE; + + /* update channel in IE */ + p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + if (p && ie_len > 0) + *(p + 2) = ch; + + bss->Configuration.DSConfig = ch; + + /* band is changed, update ERP, support rate, ext support rate IE */ + if (change_band == _TRUE) + change_band_update_ie(adapter, bss, ch); + } + +} + +bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset + , u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow) +{ + u8 cur_ie_ch, cur_ie_bw, cur_ie_offset; + u8 dec_ch, dec_bw, dec_offset; + u8 u_ch = 0, u_offset, u_bw; + bool changed = _FALSE; + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + WLAN_BSSID_EX *network = &(adapter->mlmepriv.cur_network.network); + struct mi_state mstate; + bool set_u_ch = _FALSE, set_dec_ch = _FALSE; + + rtw_ies_get_chbw(network->IEs + sizeof(NDIS_802_11_FIXED_IEs) + , network->IELength - sizeof(NDIS_802_11_FIXED_IEs) + , &cur_ie_ch, &cur_ie_bw, &cur_ie_offset); + + /* use chbw of cur_ie updated with specifying req as temporary decision */ + dec_ch = (req_ch <= 0) ? cur_ie_ch : req_ch; + dec_bw = (req_bw < 0) ? cur_ie_bw : req_bw; + dec_offset = (req_offset < 0) ? cur_ie_offset : req_offset; + + rtw_mi_status_no_self(adapter, &mstate); + RTW_INFO(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u\n" + , FUNC_ADPT_ARG(adapter), MSTATE_STA_LD_NUM(&mstate), MSTATE_STA_LG_NUM(&mstate), MSTATE_AP_NUM(&mstate)); + + if (MSTATE_STA_LD_NUM(&mstate) || MSTATE_AP_NUM(&mstate)) { + /* has linked STA or AP mode, follow */ + + rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); + + RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + + rtw_adjust_chbw(adapter, u_ch, &dec_bw, &dec_offset); + rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset + , &u_ch, &u_bw, &u_offset); + + rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) + , dec_ch, dec_bw, dec_offset); + + set_u_ch = _TRUE; + } else if (MSTATE_STA_LG_NUM(&mstate)) { + /* has linking STA */ + + rtw_warn_on(!rtw_mi_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); + + RTW_INFO(FUNC_ADPT_FMT" union no self: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + + rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); + + if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) { + + rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset + , &u_ch, &u_bw, &u_offset); + + rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) + , dec_ch, dec_bw, dec_offset); + + set_u_ch = _TRUE; + + /* channel bw offset can be allowed, not need MCC */ + *chbw_allow = _TRUE; + } else { + /* set this for possible ch change when join down*/ + set_fwstate(&adapter->mlmepriv, WIFI_OP_CH_SWITCHING); + } + } else { + /* single AP mode */ + + RTW_INFO(FUNC_ADPT_FMT" req: %d,%d,%d\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + + /* check temporary decision first */ + rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); + if (!rtw_get_offset_by_chbw(dec_ch, dec_bw, &dec_offset)) { + if (req_ch == -1 || req_bw == -1) + goto choose_chbw; + RTW_WARN(FUNC_ADPT_FMT" req: %u,%u has no valid offset\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw); + *chbw_allow = _FALSE; + goto exit; + } + + if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, dec_ch, dec_bw, dec_offset)) { + if (req_ch == -1 || req_bw == -1) + goto choose_chbw; + RTW_WARN(FUNC_ADPT_FMT" req: %u,%u,%u doesn't fit in chplan\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + *chbw_allow = _FALSE; + goto exit; + } + + if (rtw_odm_dfs_domain_unknown(adapter) && rtw_is_dfs_chbw(dec_ch, dec_bw, dec_offset)) { + if (req_ch >= 0) + RTW_WARN(FUNC_ADPT_FMT" DFS channel %u,%u,%u can't be used\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + if (req_ch > 0) { + /* specific channel and not from IE => don't change channel setting */ + *chbw_allow = _FALSE; + goto exit; + } + goto choose_chbw; + } + + if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, dec_ch, dec_bw, dec_offset) == _FALSE) + goto update_bss_chbw; + +choose_chbw: + if (req_bw < 0) + req_bw = cur_ie_bw; + + if (rtw_choose_shortest_waiting_ch(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_DFS) == _FALSE) { + RTW_WARN(FUNC_ADPT_FMT" no available channel\n", FUNC_ADPT_ARG(adapter)); + *chbw_allow = _FALSE; + goto exit; + } + +update_bss_chbw: + rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) + , dec_ch, dec_bw, dec_offset); + + /* channel bw offset can be allowed for single AP, not need MCC */ + *chbw_allow = _TRUE; + set_dec_ch = _TRUE; + } + + if (rtw_mi_check_fwstate(adapter, _FW_UNDER_SURVEY)) { + /* scanning, leave ch setting to scan state machine */ + set_u_ch = set_dec_ch = _FALSE; + } + + if (mlmeext->cur_channel != dec_ch + || mlmeext->cur_bwmode != dec_bw + || mlmeext->cur_ch_offset != dec_offset) + changed = _TRUE; + + if (changed == _TRUE && rtw_linked_check(adapter) == _TRUE) + rtw_sta_flush(adapter, _FALSE); + + mlmeext->cur_channel = dec_ch; + mlmeext->cur_bwmode = dec_bw; + mlmeext->cur_ch_offset = dec_offset; + + if (u_ch != 0) + RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + + RTW_INFO(FUNC_ADPT_FMT" dec: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + + if (set_u_ch == _TRUE) { + *ch = u_ch; + *bw = u_bw; + *offset = u_offset; + } else if (set_dec_ch == _TRUE) { + *ch = dec_ch; + *bw = dec_bw; + *offset = dec_offset; + } +exit: + return changed; +} + +/*#define DBG_SWTIMER_BASED_TXBCN*/ + + diff --git a/drivers/staging/rtl8821ce/core/rtw_br_ext.c b/drivers/staging/rtl8821ce/core/rtw_br_ext.c new file mode 100644 index 000000000000..7554391408f6 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_br_ext.c @@ -0,0 +1,1286 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_BR_EXT_C_ + +#include <linux/if_arp.h> +#include <net/ip.h> +#include <net/ipx.h> +#include <linux/atalk.h> +#include <linux/udp.h> +#include <linux/if_pppox.h> + +#include <drv_types.h> + +#include <linux/ipv6.h> +#include <linux/icmpv6.h> +#include <net/ndisc.h> +#include <net/ip6_checksum.h> + +#define NAT25_IPV4 01 +#define NAT25_IPV6 02 +#define NAT25_IPX 03 +#define NAT25_APPLE 04 +#define NAT25_PPPOE 05 + +#define RTL_RELAY_TAG_LEN (ETH_ALEN) +#define TAG_HDR_LEN 4 + +#define MAGIC_CODE 0x8186 +#define MAGIC_CODE_LEN 2 +#define WAIT_TIME_PPPOE 5 /* waiting time for pppoe server in sec */ + +/*----------------------------------------------------------------- + How database records network address: + 0 1 2 3 4 5 6 7 8 9 10 + |----|----|----|----|----|----|----|----|----|----|----| + IPv4 |type| | IP addr | + IPX |type| Net addr | Node addr | + IPX |type| Net addr |Sckt addr| + Apple |type| Network |node| + PPPoE |type| SID | AC MAC | +-----------------------------------------------------------------*/ + +/* Find a tag in pppoe frame and return the pointer */ +static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type) +{ + unsigned char *cur_ptr, *start_ptr; + unsigned short tagLen, tagType; + + start_ptr = cur_ptr = (unsigned char *)ph->tag; + while ((cur_ptr - start_ptr) < ntohs(ph->length)) { + /* prevent un-alignment access */ + tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]); + tagLen = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]); + if (tagType == type) + return cur_ptr; + cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen; + } + return 0; +} + +static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag) +{ + struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); + int data_len; + + data_len = tag->tag_len + TAG_HDR_LEN; + if (skb_tailroom(skb) < data_len) { + _DEBUG_ERR("skb_tailroom() failed in add SID tag!\n"); + return -1; + } + + skb_put(skb, data_len); + /* have a room for new tag */ + memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length)); + ph->length = htons(ntohs(ph->length) + data_len); + memcpy((unsigned char *)ph->tag, tag, data_len); + return data_len; +} + +static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len) +{ + int tail_len; + unsigned long end, tail; + + if ((src + len) > skb_tail_pointer(skb) || skb->len < len) + return -1; + + tail = (unsigned long)skb_tail_pointer(skb); + end = (unsigned long)src + len; + if (tail < end) + return -1; + + tail_len = (int)(tail - end); + if (tail_len > 0) + memmove(src, src + len, tail_len); + + skb_trim(skb, skb->len - len); + return 0; +} + +static __inline__ unsigned long __nat25_timeout(_adapter *priv) +{ + unsigned long timeout; + + timeout = jiffies - NAT25_AGEING_TIME * HZ; + + return timeout; +} + +static __inline__ int __nat25_has_expired(_adapter *priv, + struct nat25_network_db_entry *fdb) +{ + if (time_before_eq(fdb->ageing_timer, __nat25_timeout(priv))) + return 1; + + return 0; +} + +static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr, + unsigned int *ipAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPV4; + memcpy(networkAddr + 7, (unsigned char *)ipAddr, 4); +} + +static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPX; + memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4); + memcpy(networkAddr + 5, ipxNodeAddr, 6); +} + +static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPX; + memcpy(networkAddr + 1, (unsigned char *)ipxNetAddr, 4); + memcpy(networkAddr + 5, (unsigned char *)ipxSocketAddr, 2); +} + +static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr, + unsigned short *network, unsigned char *node) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_APPLE; + memcpy(networkAddr + 1, (unsigned char *)network, 2); + networkAddr[3] = *node; +} + +static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr, + unsigned char *ac_mac, unsigned short *sid) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_PPPOE; + memcpy(networkAddr + 1, (unsigned char *)sid, 2); + memcpy(networkAddr + 3, (unsigned char *)ac_mac, 6); +} + +static void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr, + unsigned int *ipAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPV6; + memcpy(networkAddr + 1, (unsigned char *)ipAddr, 16); +} + +static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b) +{ + while (len > 0) { + if (*data == tag && *(data + 1) == len8b && len >= len8b * 8) + return data + 2; + + len -= (*(data + 1)) * 8; + data += (*(data + 1)) * 8; + } + return NULL; +} + +static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac) +{ + struct icmp6hdr *icmphdr = (struct icmp6hdr *)data; + unsigned char *mac; + + if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) { + if (len >= 8) { + mac = scan_tlv(&data[8], len - 8, 1, 1); + if (mac) { + RTW_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], + replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) { + if (len >= 16) { + mac = scan_tlv(&data[16], len - 16, 1, 1); + if (mac) { + RTW_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], + replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) { + if (len >= 24) { + mac = scan_tlv(&data[24], len - 24, 1, 1); + if (mac) { + RTW_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], + replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) { + if (len >= 24) { + mac = scan_tlv(&data[24], len - 24, 2, 1); + if (mac) { + RTW_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], + replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } else if (icmphdr->icmp6_type == NDISC_REDIRECT) { + if (len >= 40) { + mac = scan_tlv(&data[40], len - 40, 2, 1); + if (mac) { + RTW_INFO("Redirect, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], + replace_mac[0], replace_mac[1], replace_mac[2], replace_mac[3], replace_mac[4], replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } + return 0; +} + +static __inline__ int __nat25_network_hash(unsigned char *networkAddr) +{ + if (networkAddr[0] == NAT25_IPV4) { + unsigned long x; + + x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + + return x & (NAT25_HASH_SIZE - 1); + } else if (networkAddr[0] == NAT25_IPX) { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ + networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + + return x & (NAT25_HASH_SIZE - 1); + } else if (networkAddr[0] == NAT25_APPLE) { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3]; + + return x & (NAT25_HASH_SIZE - 1); + } else if (networkAddr[0] == NAT25_PPPOE) { + unsigned long x; + + x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8]; + + return x & (NAT25_HASH_SIZE - 1); + } + else if (networkAddr[0] == NAT25_IPV6) { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ + networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^ + networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^ + networkAddr[16]; + + return x & (NAT25_HASH_SIZE - 1); + } + else { + unsigned long x = 0; + int i; + + for (i = 0; i < MAX_NETWORK_ADDR_LEN; i++) + x ^= networkAddr[i]; + + return x & (NAT25_HASH_SIZE - 1); + } +} + +static __inline__ void __network_hash_link(_adapter *priv, + struct nat25_network_db_entry *ent, int hash) +{ + /* Caller must _enter_critical_bh already! */ + /* _irqL irqL; */ + /* _enter_critical_bh(&priv->br_ext_lock, &irqL); */ + + ent->next_hash = priv->nethash[hash]; + if (ent->next_hash != NULL) + ent->next_hash->pprev_hash = &ent->next_hash; + priv->nethash[hash] = ent; + ent->pprev_hash = &priv->nethash[hash]; + + /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ +} + +static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent) +{ + /* Caller must _enter_critical_bh already! */ + /* _irqL irqL; */ + /* _enter_critical_bh(&priv->br_ext_lock, &irqL); */ + + *(ent->pprev_hash) = ent->next_hash; + if (ent->next_hash != NULL) + ent->next_hash->pprev_hash = ent->pprev_hash; + ent->next_hash = NULL; + ent->pprev_hash = NULL; + + /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ +} + +static int __nat25_db_network_lookup_and_replace(_adapter *priv, + struct sk_buff *skb, unsigned char *networkAddr) +{ + struct nat25_network_db_entry *db; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + db = priv->nethash[__nat25_network_hash(networkAddr)]; + while (db != NULL) { + if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { + if (!__nat25_has_expired(priv, db)) { + /* replace the destination mac address */ + memcpy(skb->data, db->macAddr, ETH_ALEN); + atomic_inc(&db->use_count); + + RTW_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" + "%02x%02x%02x%02x%02x%02x\n", + db->macAddr[0], + db->macAddr[1], + db->macAddr[2], + db->macAddr[3], + db->macAddr[4], + db->macAddr[5], + db->networkAddr[0], + db->networkAddr[1], + db->networkAddr[2], + db->networkAddr[3], + db->networkAddr[4], + db->networkAddr[5], + db->networkAddr[6], + db->networkAddr[7], + db->networkAddr[8], + db->networkAddr[9], + db->networkAddr[10], + db->networkAddr[11], + db->networkAddr[12], + db->networkAddr[13], + db->networkAddr[14], + db->networkAddr[15], + db->networkAddr[16]); + } + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return 1; + } + + db = db->next_hash; + } + + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return 0; +} + +static void __nat25_db_network_insert(_adapter *priv, + unsigned char *macAddr, unsigned char *networkAddr) +{ + struct nat25_network_db_entry *db; + int hash; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + hash = __nat25_network_hash(networkAddr); + db = priv->nethash[hash]; + while (db != NULL) { + if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { + memcpy(db->macAddr, macAddr, ETH_ALEN); + db->ageing_timer = jiffies; + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return; + } + + db = db->next_hash; + } + + db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db)); + if (db == NULL) { + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return; + } + + memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN); + memcpy(db->macAddr, macAddr, ETH_ALEN); + atomic_set(&db->use_count, 1); + db->ageing_timer = jiffies; + + __network_hash_link(priv, db, hash); + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + +static void __nat25_db_print(_adapter *priv) +{ + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + +/* + * NAT2.5 interface + */ + +void nat25_db_cleanup(_adapter *priv) +{ + int i; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + for (i = 0; i < NAT25_HASH_SIZE; i++) { + struct nat25_network_db_entry *f; + f = priv->nethash[i]; + while (f != NULL) { + struct nat25_network_db_entry *g; + + g = f->next_hash; + if (priv->scdb_entry == f) { + memset(priv->scdb_mac, 0, ETH_ALEN); + memset(priv->scdb_ip, 0, 4); + priv->scdb_entry = NULL; + } + __network_hash_unlink(f); + rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); + + f = g; + } + } + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + +void nat25_db_expire(_adapter *priv) +{ + int i; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + /* if(!priv->ethBrExtInfo.nat25_disable) */ + { + for (i = 0; i < NAT25_HASH_SIZE; i++) { + struct nat25_network_db_entry *f; + f = priv->nethash[i]; + + while (f != NULL) { + struct nat25_network_db_entry *g; + g = f->next_hash; + + if (__nat25_has_expired(priv, f)) { + if (atomic_dec_and_test(&f->use_count)) { + if (priv->scdb_entry == f) { + memset(priv->scdb_mac, 0, ETH_ALEN); + memset(priv->scdb_ip, 0, 4); + priv->scdb_entry = NULL; + } + __network_hash_unlink(f); + rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); + } + } + + f = g; + } + } + } + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + + +int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) +{ + unsigned short protocol; + unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; + + if (skb == NULL) + return -1; + + if ((method <= NAT25_MIN) || (method >= NAT25_MAX)) + return -1; + + protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); + + /*---------------------------------------------------*/ + /* Handle IP frame */ + /*---------------------------------------------------*/ + if (protocol == __constant_htons(ETH_P_IP)) { + struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN); + + if (((unsigned char *)(iph) + (iph->ihl << 2)) >= (skb->data + ETH_HLEN + skb->len)) { + DEBUG_WARN("NAT25: malformed IP packet !\n"); + return -1; + } + + switch (method) { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: { + /* some muticast with source IP is all zero, maybe other case is illegal */ + /* in class A, B, C, host address is all zero or all one is illegal */ + if (iph->saddr == 0) + return 0; + RTW_INFO("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); + __nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr); + /* record source IP address and , source mac address into db */ + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + RTW_INFO("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); + { + __nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr); + + if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { + if (*((unsigned char *)&iph->daddr + 3) == 0xff) { + /* L2 is unicast but L3 is broadcast, make L2 bacome broadcast */ + RTW_INFO("NAT25: Set DA as boardcast\n"); + memset(skb->data, 0xff, ETH_ALEN); + } else { + /* forward unknow IP packet to upper TCP/IP */ + RTW_INFO("NAT25: Replace DA with BR's MAC\n"); + if ((*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac + 4)) == 0) { + void netdev_br_init(struct net_device *netdev); + printk("Re-init netdev_br_init() due to br_mac==0!\n"); + netdev_br_init(priv->pnetdev); + } + memcpy(skb->data, priv->br_mac, ETH_ALEN); + } + } + } + } + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle ARP frame */ + /*---------------------------------------------------*/ + else if (protocol == __constant_htons(ETH_P_ARP)) { + struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN); + unsigned char *arp_ptr = (unsigned char *)(arp + 1); + unsigned int *sender, *target; + + if (arp->ar_pro != __constant_htons(ETH_P_IP)) { + DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro)); + return -1; + } + + switch (method) { + case NAT25_CHECK: + return 0; /* skb_copy for all ARP frame */ + + case NAT25_INSERT: { + RTW_INFO("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0], + arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]); + + /* change to ARP sender mac address to wlan STA address */ + memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN); + + arp_ptr += arp->ar_hln; + sender = (unsigned int *)arp_ptr; + + __nat25_generate_ipv4_network_addr(networkAddr, sender); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + RTW_INFO("NAT25: Lookup ARP\n"); + + arp_ptr += arp->ar_hln; + sender = (unsigned int *)arp_ptr; + arp_ptr += (arp->ar_hln + arp->ar_pln); + target = (unsigned int *)arp_ptr; + + __nat25_generate_ipv4_network_addr(networkAddr, target); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + /* change to ARP target mac address to Lookup result */ + arp_ptr = (unsigned char *)(arp + 1); + arp_ptr += (arp->ar_hln + arp->ar_pln); + memcpy(arp_ptr, skb->data, ETH_ALEN); + } + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle IPX and Apple Talk frame */ + /*---------------------------------------------------*/ + else if ((protocol == __constant_htons(ETH_P_IPX)) || + (protocol == __constant_htons(ETH_P_ATALK)) || + (protocol == __constant_htons(ETH_P_AARP))) { + unsigned char ipx_header[2] = {0xFF, 0xFF}; + struct ipxhdr *ipx = NULL; + struct elapaarp *ea = NULL; + struct ddpehdr *ddp = NULL; + unsigned char *framePtr = skb->data + ETH_HLEN; + + if (protocol == __constant_htons(ETH_P_IPX)) { + RTW_INFO("NAT25: Protocol=IPX (Ethernet II)\n"); + ipx = (struct ipxhdr *)framePtr; + } else { /* if(protocol <= __constant_htons(ETH_FRAME_LEN)) */ + if (!memcmp(ipx_header, framePtr, 2)) { + RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.3)\n"); + ipx = (struct ipxhdr *)framePtr; + } else { + unsigned char ipx_8022_type = 0xE0; + unsigned char snap_8022_type = 0xAA; + + if (*framePtr == snap_8022_type) { + unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37}; /* IPX SNAP ID */ + unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3}; /* Apple Talk AARP SNAP ID */ + unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B}; /* Apple Talk DDP SNAP ID */ + + framePtr += 3; /* eliminate the 802.2 header */ + + if (!memcmp(ipx_snap_id, framePtr, 5)) { + framePtr += 5; /* eliminate the SNAP header */ + + RTW_INFO("NAT25: Protocol=IPX (Ethernet SNAP)\n"); + ipx = (struct ipxhdr *)framePtr; + } else if (!memcmp(aarp_snap_id, framePtr, 5)) { + framePtr += 5; /* eliminate the SNAP header */ + + ea = (struct elapaarp *)framePtr; + } else if (!memcmp(ddp_snap_id, framePtr, 5)) { + framePtr += 5; /* eliminate the SNAP header */ + + ddp = (struct ddpehdr *)framePtr; + } else { + DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0], + framePtr[1], framePtr[2], framePtr[3], framePtr[4]); + return -1; + } + } else if (*framePtr == ipx_8022_type) { + framePtr += 3; /* eliminate the 802.2 header */ + + if (!memcmp(ipx_header, framePtr, 2)) { + RTW_INFO("NAT25: Protocol=IPX (Ethernet 802.2)\n"); + ipx = (struct ipxhdr *)framePtr; + } else + return -1; + } + } + } + + /* IPX */ + if (ipx != NULL) { + switch (method) { + case NAT25_CHECK: + if (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) { + RTW_INFO("NAT25: Check IPX skb_copy\n"); + return 0; + } + return -1; + + case NAT25_INSERT: { + RTW_INFO("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n", + ipx->ipx_dest.net, + ipx->ipx_dest.node[0], + ipx->ipx_dest.node[1], + ipx->ipx_dest.node[2], + ipx->ipx_dest.node[3], + ipx->ipx_dest.node[4], + ipx->ipx_dest.node[5], + ipx->ipx_dest.sock, + ipx->ipx_source.net, + ipx->ipx_source.node[0], + ipx->ipx_source.node[1], + ipx->ipx_source.node[2], + ipx->ipx_source.node[3], + ipx->ipx_source.node[4], + ipx->ipx_source.node[5], + ipx->ipx_source.sock); + + if (!memcmp(skb->data + ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) { + RTW_INFO("NAT25: Use IPX Net, and Socket as network addr\n"); + + __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock); + + /* change IPX source node addr to wlan STA address */ + memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN); + } else + __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + if (!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) { + RTW_INFO("NAT25: Lookup IPX, Modify Destination IPX Node addr\n"); + + __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + /* replace IPX destination node addr with Lookup destination MAC addr */ + memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN); + } else { + __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + } + } + return 0; + + default: + return -1; + } + } + + /* AARP */ + else if (ea != NULL) { + /* Sanity check fields. */ + if (ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) { + DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n"); + return -1; + } + + switch (method) { + case NAT25_CHECK: + return 0; + + case NAT25_INSERT: { + /* change to AARP source mac address to wlan STA address */ + memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN); + + RTW_INFO("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n", + ea->pa_src_net, + ea->pa_src_node, + ea->pa_dst_net, + ea->pa_dst_node); + + __nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + RTW_INFO("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n", + ea->pa_src_net, + ea->pa_src_node, + ea->pa_dst_net, + ea->pa_dst_node); + + __nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + /* change to AARP destination mac address to Lookup result */ + memcpy(ea->hw_dst, skb->data, ETH_ALEN); + } + return 0; + + default: + return -1; + } + } + + /* DDP */ + else if (ddp != NULL) { + switch (method) { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: { + RTW_INFO("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n", + ddp->deh_snet, + ddp->deh_snode, + ddp->deh_dnet, + ddp->deh_dnode); + + __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: { + RTW_INFO("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n", + ddp->deh_snet, + ddp->deh_snode, + ddp->deh_dnet, + ddp->deh_dnode); + + __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + } + return 0; + + default: + return -1; + } + } + + return -1; + } + + /*---------------------------------------------------*/ + /* Handle PPPoE frame */ + /*---------------------------------------------------*/ + else if ((protocol == __constant_htons(ETH_P_PPP_DISC)) || + (protocol == __constant_htons(ETH_P_PPP_SES))) { + struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); + unsigned short *pMagic; + + switch (method) { + case NAT25_CHECK: + if (ph->sid == 0) + return 0; + return 1; + + case NAT25_INSERT: + if (ph->sid == 0) { /* Discovery phase according to tag */ + if (ph->code == PADI_CODE || ph->code == PADR_CODE) { + if (priv->ethBrExtInfo.addPPPoETag) { + struct pppoe_tag *tag, *pOldTag; + unsigned char tag_buf[40]; + int old_tag_len = 0; + + tag = (struct pppoe_tag *)tag_buf; + pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID)); + if (pOldTag) { /* if SID existed, copy old value and delete it */ + old_tag_len = ntohs(pOldTag->tag_len); + if (old_tag_len + TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN > sizeof(tag_buf)) { + DEBUG_ERR("SID tag length too long!\n"); + return -1; + } + + memcpy(tag->tag_data + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN, + pOldTag->tag_data, old_tag_len); + + if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN + old_tag_len) < 0) { + DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n"); + return -1; + } + ph->length = htons(ntohs(ph->length) - TAG_HDR_LEN - old_tag_len); + } + + tag->tag_type = PTT_RELAY_SID; + tag->tag_len = htons(MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN + old_tag_len); + + /* insert the magic_code+client mac in relay tag */ + pMagic = (unsigned short *)tag->tag_data; + *pMagic = htons(MAGIC_CODE); + memcpy(tag->tag_data + MAGIC_CODE_LEN, skb->data + ETH_ALEN, ETH_ALEN); + + /* Add relay tag */ + if (__nat25_add_pppoe_tag(skb, tag) < 0) + return -1; + + RTW_INFO("NAT25: Insert PPPoE, forward %s packet\n", + (ph->code == PADI_CODE ? "PADI" : "PADR")); + } else { /* not add relay tag */ + if (priv->pppoe_connection_in_progress && + memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) { + DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n"); + return -2; + } + + if (priv->pppoe_connection_in_progress == 0) + memcpy(priv->pppoe_addr, skb->data + ETH_ALEN, ETH_ALEN); + + priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; + } + } else + return -1; + } else { /* session phase */ + RTW_INFO("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name); + + __nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid)); + + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + + if (!priv->ethBrExtInfo.addPPPoETag && + priv->pppoe_connection_in_progress && + !memcmp(skb->data + ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) + priv->pppoe_connection_in_progress = 0; + } + return 0; + + case NAT25_LOOKUP: + if (ph->code == PADO_CODE || ph->code == PADS_CODE) { + if (priv->ethBrExtInfo.addPPPoETag) { + struct pppoe_tag *tag; + unsigned char *ptr; + unsigned short tagType, tagLen; + int offset = 0; + + ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID)); + if (ptr == 0) { + DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n"); + return -1; + } + + tag = (struct pppoe_tag *)ptr; + tagType = (unsigned short)((ptr[0] << 8) + ptr[1]); + tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]); + + if ((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN))) { + DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen); + return -1; + } + + pMagic = (unsigned short *)tag->tag_data; + if (ntohs(*pMagic) != MAGIC_CODE) { + DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n", + (ph->code == PADO_CODE ? "PADO" : "PADS")); + return -1; + } + + memcpy(skb->data, tag->tag_data + MAGIC_CODE_LEN, ETH_ALEN); + + if (tagLen > MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN) + offset = TAG_HDR_LEN; + + if (skb_pull_and_merge(skb, ptr + offset, TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset) < 0) { + DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n"); + return -1; + } + ph->length = htons(ntohs(ph->length) - (TAG_HDR_LEN + MAGIC_CODE_LEN + RTL_RELAY_TAG_LEN - offset)); + if (offset > 0) + tag->tag_len = htons(tagLen - MAGIC_CODE_LEN - RTL_RELAY_TAG_LEN); + + RTW_INFO("NAT25: Lookup PPPoE, forward %s Packet from %s\n", + (ph->code == PADO_CODE ? "PADO" : "PADS"), skb->dev->name); + } else { /* not add relay tag */ + if (!priv->pppoe_connection_in_progress) { + DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n"); + return -1; + } + memcpy(skb->data, priv->pppoe_addr, ETH_ALEN); + priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; + } + } else { + if (ph->sid != 0) { + RTW_INFO("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name); + __nat25_generate_pppoe_network_addr(networkAddr, skb->data + ETH_ALEN, &(ph->sid)); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + __nat25_db_print(priv); + } else + return -1; + + } + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle EAP frame */ + /*---------------------------------------------------*/ + else if (protocol == __constant_htons(0x888e)) { + switch (method) { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: + return 0; + + case NAT25_LOOKUP: + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle C-Media proprietary frame */ + /*---------------------------------------------------*/ + else if ((protocol == __constant_htons(0xe2ae)) || + (protocol == __constant_htons(0xe2af))) { + switch (method) { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: + return 0; + + case NAT25_LOOKUP: + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle IPV6 frame */ + /*---------------------------------------------------*/ + else if (protocol == __constant_htons(ETH_P_IPV6)) { + struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); + + if (sizeof(*iph) >= (skb->len - ETH_HLEN)) { + DEBUG_WARN("NAT25: malformed IPv6 packet !\n"); + return -1; + } + + switch (method) { + case NAT25_CHECK: + if (skb->data[0] & 1) + return 0; + return -1; + + case NAT25_INSERT: { + RTW_INFO("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," + " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", + iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3], + iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7], + iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3], + iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]); + + if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) { + __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr); + __nat25_db_network_insert(priv, skb->data + ETH_ALEN, networkAddr); + __nat25_db_print(priv); + + if (iph->nexthdr == IPPROTO_ICMPV6 && + skb->len > (ETH_HLEN + sizeof(*iph) + 4)) { + if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph), + skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) { + struct icmp6hdr *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph)); + hdr->icmp6_cksum = 0; + hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr, + iph->payload_len, + IPPROTO_ICMPV6, + csum_partial((__u8 *)hdr, iph->payload_len, 0)); + } + } + } + } + return 0; + + case NAT25_LOOKUP: + RTW_INFO("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," + " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", + iph->saddr.s6_addr16[0], iph->saddr.s6_addr16[1], iph->saddr.s6_addr16[2], iph->saddr.s6_addr16[3], + iph->saddr.s6_addr16[4], iph->saddr.s6_addr16[5], iph->saddr.s6_addr16[6], iph->saddr.s6_addr16[7], + iph->daddr.s6_addr16[0], iph->daddr.s6_addr16[1], iph->daddr.s6_addr16[2], iph->daddr.s6_addr16[3], + iph->daddr.s6_addr16[4], iph->daddr.s6_addr16[5], iph->daddr.s6_addr16[6], iph->daddr.s6_addr16[7]); + + __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr); + if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { +#ifdef SUPPORT_RX_UNI2MCAST + if (iph->daddr.s6_addr[0] == 0xff) + convert_ipv6_mac_to_mc(skb); +#endif + } + return 0; + + default: + return -1; + } + } + + return -1; +} + +int nat25_handle_frame(_adapter *priv, struct sk_buff *skb) +{ + + if (!(skb->data[0] & 1)) { + int is_vlan_tag = 0, i, retval = 0; + unsigned short vlan_hdr = 0; + + if (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_8021Q)) { + is_vlan_tag = 1; + vlan_hdr = *((unsigned short *)(skb->data + ETH_ALEN * 2 + 2)); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + ETH_ALEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + ETH_ALEN * 2 - 2 - i * 2)); + skb_pull(skb, 4); + } + + if (!priv->ethBrExtInfo.nat25_disable) { + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + /* + * This function look up the destination network address from + * the NAT2.5 database. Return value = -1 means that the + * corresponding network protocol is NOT support. + */ + if (!priv->ethBrExtInfo.nat25sc_disable && + (*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) && + !memcmp(priv->scdb_ip, skb->data + ETH_HLEN + 16, 4)) { + memcpy(skb->data, priv->scdb_mac, ETH_ALEN); + + _exit_critical_bh(&priv->br_ext_lock, &irqL); + } else { + _exit_critical_bh(&priv->br_ext_lock, &irqL); + + retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); + } + } else { + if (((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_IP)) && + !memcmp(priv->br_ip, skb->data + ETH_HLEN + 16, 4)) || + ((*((unsigned short *)(skb->data + ETH_ALEN * 2)) == __constant_htons(ETH_P_ARP)) && + !memcmp(priv->br_ip, skb->data + ETH_HLEN + 24, 4))) { + /* for traffic to upper TCP/IP */ + retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); + } + } + + if (is_vlan_tag) { + skb_push(skb, 4); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2)); + *((unsigned short *)(skb->data + ETH_ALEN * 2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data + ETH_ALEN * 2 + 2)) = vlan_hdr; + } + + if (retval == -1) { + /* DEBUG_ERR("NAT25: Lookup fail!\n"); */ + return -1; + } + } + + return 0; +} + +#define SERVER_PORT 67 +#define CLIENT_PORT 68 +#define DHCP_MAGIC 0x63825363 +#define BROADCAST_FLAG 0x8000 + +struct dhcpMessage { + u_int8_t op; + u_int8_t htype; + u_int8_t hlen; + u_int8_t hops; + u_int32_t xid; + u_int16_t secs; + u_int16_t flags; + u_int32_t ciaddr; + u_int32_t yiaddr; + u_int32_t siaddr; + u_int32_t giaddr; + u_int8_t chaddr[16]; + u_int8_t sname[64]; + u_int8_t file[128]; + u_int32_t cookie; + u_int8_t options[308]; /* 312 - cookie */ +}; + +void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb) +{ + if (skb == NULL) + return; + + if (!priv->ethBrExtInfo.dhcp_bcst_disable) { + unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); + + if (protocol == __constant_htons(ETH_P_IP)) { /* IP */ + struct iphdr *iph = (struct iphdr *)(skb->data + ETH_HLEN); + + if (iph->protocol == IPPROTO_UDP) { /* UDP */ + struct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2)); + + if ((udph->source == __constant_htons(CLIENT_PORT)) + && (udph->dest == __constant_htons(SERVER_PORT))) { /* DHCP request */ + struct dhcpMessage *dhcph = + (struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr)); + + if (dhcph->cookie == __constant_htonl(DHCP_MAGIC)) { /* match magic word */ + if (!(dhcph->flags & htons(BROADCAST_FLAG))) { /* if not broadcast */ + register int sum = 0; + + RTW_INFO("DHCP: change flag of DHCP request to broadcast.\n"); + /* or BROADCAST flag */ + dhcph->flags |= htons(BROADCAST_FLAG); + /* recalculate checksum */ + sum = ~(udph->check) & 0xffff; + sum += dhcph->flags; + while (sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + udph->check = ~sum; + } + } + } + } + } + } +} + +void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, + unsigned char *ipAddr) +{ + unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; + struct nat25_network_db_entry *db; + int hash; + /* _irqL irqL; */ + /* _enter_critical_bh(&priv->br_ext_lock, &irqL); */ + + __nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr); + hash = __nat25_network_hash(networkAddr); + db = priv->nethash[hash]; + while (db != NULL) { + if (!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { + /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ + return (void *)db; + } + + db = db->next_hash; + } + + /* _exit_critical_bh(&priv->br_ext_lock, &irqL); */ + return NULL; +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_btcoex.c b/drivers/staging/rtl8821ce/core/rtw_btcoex.c new file mode 100644 index 000000000000..6abf7db3f012 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_btcoex.c @@ -0,0 +1,363 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <hal_btcoex.h> +#include <hal_data.h> + +void rtw_btcoex_Initialize(PADAPTER padapter) +{ + hal_btcoex_Initialize(padapter); +} + +void rtw_btcoex_PowerOnSetting(PADAPTER padapter) +{ + hal_btcoex_PowerOnSetting(padapter); +} + +void rtw_btcoex_PowerOffSetting(PADAPTER padapter) +{ + hal_btcoex_PowerOffSetting(padapter); +} + +void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly) +{ + hal_btcoex_InitHwConfig(padapter, bWifiOnly); +} + +void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_IpsNotify(padapter, type); +} + +void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_LpsNotify(padapter, type); +} + +void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + if (_FALSE == type) { + + if (DEV_MGMT_TX_NUM(adapter_to_dvobj(padapter)) + || DEV_ROCH_NUM(adapter_to_dvobj(padapter))) + return; + } + + hal_btcoex_ScanNotify(padapter, type); +} + +void rtw_btcoex_ConnectNotify(PADAPTER padapter, u8 action) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + + + hal_btcoex_ConnectNotify(padapter, action); +} + +void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + + + if ((RT_MEDIA_CONNECT == mediaStatus) + && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)) + rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL); + + hal_btcoex_MediaStatusNotify(padapter, mediaStatus); +} + +void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_SpecialPacketNotify(padapter, pktType); +} + +void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_BtInfoNotify(padapter, length, tmpBuf); +} + +void rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + if (padapter->registrypriv.mp_mode == 1) + return; + + hal_btcoex_BtMpRptNotify(padapter, length, tmpBuf); +} + +void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_SuspendNotify(padapter, state); +} + +void rtw_btcoex_HaltNotify(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + u8 do_halt = 1; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + do_halt = 0; + + if (_FALSE == padapter->bup) { + RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n", + FUNC_ADPT_ARG(padapter), padapter->bup); + do_halt = 0; + } + + if (rtw_is_surprise_removed(padapter)) { + RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n", + FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter) ? "True" : "False"); + do_halt = 0; + } + + hal_btcoex_HaltNotify(padapter, do_halt); +} + +void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type) +{ + hal_btcoex_switchband_notify(under_scan, band_type); +} + +u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter) +{ + return hal_btcoex_IsBtDisabled(padapter); +} + +void rtw_btcoex_Handler(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_Hanlder(padapter); +} + +s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter) +{ + s32 coexctrl; + + coexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter); + + return coexctrl; +} + +s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter) +{ + s32 coexctrl; + + coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter); + + return coexctrl; +} + +u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter) +{ + u32 size; + + size = hal_btcoex_GetAMPDUSize(padapter); + + return size; +} + +void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual) +{ + if (_TRUE == manual) + hal_btcoex_SetManualControl(padapter, _TRUE); + else + hal_btcoex_SetManualControl(padapter, _FALSE); +} + +u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter) +{ + return hal_btcoex_IsBtControlLps(padapter); +} + +u8 rtw_btcoex_IsLpsOn(PADAPTER padapter) +{ + return hal_btcoex_IsLpsOn(padapter); +} + +u8 rtw_btcoex_RpwmVal(PADAPTER padapter) +{ + return hal_btcoex_RpwmVal(padapter); +} + +u8 rtw_btcoex_LpsVal(PADAPTER padapter) +{ + return hal_btcoex_LpsVal(padapter); +} + +u32 rtw_btcoex_GetRaMask(PADAPTER padapter) +{ + return hal_btcoex_GetRaMask(padapter); +} + +void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen) +{ + hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen); +} + +/* ================================================== + * Below Functions are called by BT-Coex + * ================================================== */ +void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter) +{ + rtw_rx_ampdu_apply(padapter); +} + +void rtw_btcoex_LPS_Enter(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrpriv; + u8 lpsVal; + + pwrpriv = adapter_to_pwrctl(padapter); + + pwrpriv->bpower_saving = _TRUE; + lpsVal = rtw_btcoex_LpsVal(padapter); + rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX"); +} + +u8 rtw_btcoex_LPS_Leave(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrpriv; + + pwrpriv = adapter_to_pwrctl(padapter); + + if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) { + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX"); + LPS_RF_ON_check(padapter, 100); + pwrpriv->bpower_saving = _FALSE; + } + + return _TRUE; +} + +u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + return pHalData->EEPROMBluetoothCoexist; +} + +u8 rtw_btcoex_get_chip_type(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + return pHalData->EEPROMBluetoothType; +} + +u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + return pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1; +} + +u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + return pHalData->ant_path; +} + +u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + return pHalData->rfe_type; +} + +u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + return _FALSE; +} + +u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + + return (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE; +} + +/* ================================================== + * Below Functions are BT-Coex socket related function + * ================================================== */ + diff --git a/drivers/staging/rtl8821ce/core/rtw_btcoex_wifionly.c b/drivers/staging/rtl8821ce/core/rtw_btcoex_wifionly.c new file mode 100644 index 000000000000..bbbecfbf6177 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_btcoex_wifionly.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#include <drv_types.h> +#include <hal_btcoex_wifionly.h> +#include <hal_data.h> + +void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter) +{ + hal_btcoex_wifionly_switchband_notify(padapter); +} + +void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter) +{ + hal_btcoex_wifionly_scan_notify(padapter); +} + +void rtw_btcoex_wifionly_hw_config(PADAPTER padapter) +{ + hal_btcoex_wifionly_hw_config(padapter); +} + +void rtw_btcoex_wifionly_initialize(PADAPTER padapter) +{ + hal_btcoex_wifionly_initlizevariables(padapter); +} diff --git a/drivers/staging/rtl8821ce/core/rtw_cmd.c b/drivers/staging/rtl8821ce/core/rtw_cmd.c new file mode 100644 index 000000000000..9df8a03223f8 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_cmd.c @@ -0,0 +1,3016 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <hal_data.h> + +#ifndef DBG_CMD_EXECUTE + #define DBG_CMD_EXECUTE 0 +#endif + +struct cmd_hdl wlancmds[] = { + GEN_DRV_CMD_HANDLER(sizeof(struct readMAC_parm), rtw_getmacreg) /*0*/ + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*10*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct joinbss_parm), join_cmd_hdl) /*14*/ + GEN_MLME_EXT_HANDLER(sizeof(struct disconnect_parm), disconnect_hdl) + GEN_MLME_EXT_HANDLER(sizeof(struct createbss_parm), createbss_hdl) + GEN_MLME_EXT_HANDLER(sizeof(struct setopmode_parm), setopmode_hdl) + GEN_MLME_EXT_HANDLER(sizeof(struct sitesurvey_parm), sitesurvey_cmd_hdl) /*18*/ + GEN_MLME_EXT_HANDLER(sizeof(struct setauth_parm), setauth_hdl) + GEN_MLME_EXT_HANDLER(sizeof(struct setkey_parm), setkey_hdl) /*20*/ + GEN_MLME_EXT_HANDLER(sizeof(struct set_stakey_parm), set_stakey_hdl) + GEN_MLME_EXT_HANDLER(sizeof(struct set_assocsta_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct del_assocsta_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct setstapwrstate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct setbasicrate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct getbasicrate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct setdatarate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct getdatarate_parm), NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*30*/ + GEN_MLME_EXT_HANDLER(sizeof(struct setphy_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct getphy_parm), NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*40*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl) + GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*50*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/ + + GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/ + GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/ + + GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/ + GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/ + GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/ + + GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/ + GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/ + GEN_MLME_EXT_HANDLER(0, chk_bmc_sleepq_hdl) /*63*/ + GEN_MLME_EXT_HANDLER(sizeof(struct RunInThread_param), run_in_thread_hdl) /*64*/ + GEN_MLME_EXT_HANDLER(sizeof(struct addBaRsp_parm), add_ba_rsp_hdl) /* 65 */ +}; + +struct _cmd_callback rtw_cmd_callback[] = { + {GEN_CMD_CODE(_Read_MACREG), &rtw_getmacreg_cmdrsp_callback}, /*0*/ + {GEN_CMD_CODE(_Write_MACREG), NULL}, + {GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback}, + {GEN_CMD_CODE(_Write_BBREG), NULL}, + {GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback}, + {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/ + {GEN_CMD_CODE(_Read_EEPROM), NULL}, + {GEN_CMD_CODE(_Write_EEPROM), NULL}, + {GEN_CMD_CODE(_Read_EFUSE), NULL}, + {GEN_CMD_CODE(_Write_EFUSE), NULL}, + + {GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/ + {GEN_CMD_CODE(_Write_CAM), NULL}, + {GEN_CMD_CODE(_setBCNITV), NULL}, + {GEN_CMD_CODE(_setMBIDCFG), NULL}, + {GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/ + {GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/ + {GEN_CMD_CODE(_CreateBss), NULL}, + {GEN_CMD_CODE(_SetOpMode), NULL}, + {GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/ + {GEN_CMD_CODE(_SetAuth), NULL}, + + {GEN_CMD_CODE(_SetKey), NULL}, /*20*/ + {GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback}, + {GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback}, + {GEN_CMD_CODE(_DelAssocSta), NULL}, + {GEN_CMD_CODE(_SetStaPwrState), NULL}, + {GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/ + {GEN_CMD_CODE(_GetBasicRate), NULL}, + {GEN_CMD_CODE(_SetDataRate), NULL}, + {GEN_CMD_CODE(_GetDataRate), NULL}, + {GEN_CMD_CODE(_SetPhyInfo), NULL}, + + {GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/ + {GEN_CMD_CODE(_SetPhy), NULL}, + {GEN_CMD_CODE(_GetPhy), NULL}, + {GEN_CMD_CODE(_readRssi), NULL}, + {GEN_CMD_CODE(_readGain), NULL}, + {GEN_CMD_CODE(_SetAtim), NULL}, /*35*/ + {GEN_CMD_CODE(_SetPwrMode), NULL}, + {GEN_CMD_CODE(_JoinbssRpt), NULL}, + {GEN_CMD_CODE(_SetRaTable), NULL}, + {GEN_CMD_CODE(_GetRaTable) , NULL}, + + {GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/ + {GEN_CMD_CODE(_GetDTMReport), NULL}, + {GEN_CMD_CODE(_GetTXRateStatistics), NULL}, + {GEN_CMD_CODE(_SetUsbSuspend), NULL}, + {GEN_CMD_CODE(_SetH2cLbk), NULL}, + {GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/ + {GEN_CMD_CODE(_SetChannel), NULL}, /*46*/ + {GEN_CMD_CODE(_SetTxPower), NULL}, + {GEN_CMD_CODE(_SwitchAntenna), NULL}, + {GEN_CMD_CODE(_SetCrystalCap), NULL}, + {GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/ + + {GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/ + {GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL}, + {GEN_CMD_CODE(_SetContinuousTx), NULL}, + {GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/ + {GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/ + + {GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/ + {GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/ + {GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/ + {GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/ + {GEN_CMD_CODE(_LedBlink), NULL},/*60*/ + + {GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/ + {GEN_CMD_CODE(_TDLS), NULL},/*62*/ + {GEN_CMD_CODE(_ChkBMCSleepq), NULL}, /*63*/ + + {GEN_CMD_CODE(_RunInThreadCMD), NULL},/*64*/ + {GEN_CMD_CODE(_AddBARsp), NULL}, /*65*/ +}; + +/* +Caller and the rtw_cmd_thread can protect cmd_q by spin_lock. +No irqsave is necessary. +*/ + +sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) +{ + sint res = _SUCCESS; + + _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0); + /* _rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); */ + /*_rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0);*/ + _rtw_init_sema(&(pcmdpriv->start_cmdthread_sema), 0); + _rtw_init_completion(&pcmdpriv->cmdthread_comp); + + _rtw_init_queue(&(pcmdpriv->cmd_queue)); + + /* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */ + + pcmdpriv->cmd_seq = 1; + + pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ); + + if (pcmdpriv->cmd_allocated_buf == NULL) { + res = _FAIL; + goto exit; + } + + pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ((SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ - 1)); + + pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4); + + if (pcmdpriv->rsp_allocated_buf == NULL) { + res = _FAIL; + goto exit; + } + + pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ((SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3); + + pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0; + + _rtw_mutex_init(&pcmdpriv->sctx_mutex); +exit: + + return res; + +} + + +sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) +{ + sint res = _SUCCESS; + + + /* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */ + ATOMIC_SET(&pevtpriv->event_seq, 0); + pevtpriv->evt_done_cnt = 0; + + + + return res; +} + +void _rtw_free_evt_priv(struct evt_priv *pevtpriv) +{ + + + +} + +void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) +{ + + if (pcmdpriv) { + _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); + _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); + /* _rtw_free_sema(&(pcmdpriv->cmd_done_sema)); */ + /*_rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema));*/ + _rtw_free_sema(&(pcmdpriv->start_cmdthread_sema)); + + if (pcmdpriv->cmd_allocated_buf) + rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ); + + if (pcmdpriv->rsp_allocated_buf) + rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4); + + _rtw_mutex_free(&pcmdpriv->sctx_mutex); + } +} + +/* +Calling Context: + +rtw_enqueue_cmd can only be called between kernel thread, +since only spin_lock is used. + +ISR/Call-Back functions can't call this sub-function. + +*/ + +sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head) +{ + _irqL irqL; + + if (obj == NULL) + goto exit; + + /* _enter_critical_bh(&queue->lock, &irqL); */ + _enter_critical(&queue->lock, &irqL); + + if (to_head) + rtw_list_insert_head(&obj->list, &queue->queue); + else + rtw_list_insert_tail(&obj->list, &queue->queue); + + + /* _exit_critical_bh(&queue->lock, &irqL); */ + _exit_critical(&queue->lock, &irqL); + +exit: + + return _SUCCESS; +} + +struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) +{ + _irqL irqL; + struct cmd_obj *obj; + + /* _enter_critical_bh(&(queue->lock), &irqL); */ + _enter_critical(&queue->lock, &irqL); + + + if (rtw_is_list_empty(&(queue->queue))) + obj = NULL; + else { + obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list); + + + rtw_list_delete(&obj->list); + } + + /* _exit_critical_bh(&(queue->lock), &irqL); */ + _exit_critical(&queue->lock, &irqL); + + return obj; +} + +u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) +{ + u32 res; + res = _rtw_init_cmd_priv(pcmdpriv); + return res; +} + +u32 rtw_init_evt_priv(struct evt_priv *pevtpriv) +{ + int res; + res = _rtw_init_evt_priv(pevtpriv); + return res; +} + +void rtw_free_evt_priv(struct evt_priv *pevtpriv) +{ + _rtw_free_evt_priv(pevtpriv); +} + +void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv) +{ + _rtw_free_cmd_priv(pcmdpriv); +} + +int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj); +int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) +{ + u8 bAllow = _FALSE; /* set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE */ + + + if (cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan)) + bAllow = _TRUE; + + if (cmd_obj->no_io) + bAllow = _TRUE; + + if ((!rtw_is_hw_init_completed(pcmdpriv->padapter) && (bAllow == _FALSE)) + || ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _FALSE /* com_thread not running */ + ) { + if (DBG_CMD_EXECUTE) + RTW_INFO(ADPT_FMT" drop "CMD_FMT" hw_init_completed:%u, cmdthd_running:%u\n", ADPT_ARG(cmd_obj->padapter) + , CMD_ARG(cmd_obj), rtw_get_hw_init_completed(cmd_obj->padapter), ATOMIC_READ(&pcmdpriv->cmdthd_running)); + if (0) + rtw_warn_on(1); + + return _FAIL; + } + return _SUCCESS; +} + +u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) +{ + int res = _FAIL; + PADAPTER padapter = pcmdpriv->padapter; + + if (cmd_obj == NULL) + goto exit; + + cmd_obj->padapter = padapter; + + + res = rtw_cmd_filter(pcmdpriv, cmd_obj); + if ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) { + if (cmd_obj->cmdsz > MAX_CMDSZ) { + RTW_INFO("%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\n", __func__, cmd_obj->cmdsz, MAX_CMDSZ); + rtw_warn_on(1); + } + + if (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { + struct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; + + if (extra_parm->pbuf && extra_parm->size > 0) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + rtw_free_cmd_obj(cmd_obj); + goto exit; + } + + res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj, 0); + + if (res == _SUCCESS) + _rtw_up_sema(&pcmdpriv->cmd_queue_sema); + +exit: + + return res; +} + +struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv) +{ + struct cmd_obj *cmd_obj; + + cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue); + + return cmd_obj; +} + +void rtw_free_cmd_obj(struct cmd_obj *pcmd) +{ + struct drvextra_cmd_parm *extra_parm = NULL; + + if (pcmd->parmbuf != NULL) { + /* free parmbuf in cmd_obj */ + rtw_mfree((unsigned char *)pcmd->parmbuf, pcmd->cmdsz); + } + if (pcmd->rsp != NULL) { + if (pcmd->rspsz != 0) { + /* free rsp in cmd_obj */ + rtw_mfree((unsigned char *)pcmd->rsp, pcmd->rspsz); + } + } + + /* free cmd_obj */ + rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + +} + +void rtw_stop_cmd_thread(_adapter *adapter) +{ + if (adapter->cmdThread && + ATOMIC_READ(&(adapter->cmdpriv.cmdthd_running)) == _TRUE && + adapter->cmdpriv.stop_req == 0) { + adapter->cmdpriv.stop_req = 1; + _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema); + /*_rtw_down_sema(&adapter->cmdpriv.terminate_cmdthread_sema);*/ + rtw_wait_for_thread_stop(&adapter->cmdpriv.cmdthread_comp); + } +} + +thread_return rtw_cmd_thread(thread_context context) +{ + u8 ret; + struct cmd_obj *pcmd; + u8 *pcmdbuf, *prspbuf; + u32 cmd_start_time; + u32 cmd_process_time; + u8(*cmd_hdl)(_adapter *padapter, u8 *pbuf); + void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); + PADAPTER padapter = (PADAPTER)context; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct drvextra_cmd_parm *extra_parm = NULL; + _irqL irqL; + + thread_enter("RTW_CMD_THREAD"); + + pcmdbuf = pcmdpriv->cmd_buf; + prspbuf = pcmdpriv->rsp_buf; + + pcmdpriv->stop_req = 0; + ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE); + /*_rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);*/ + _rtw_up_sema(&pcmdpriv->start_cmdthread_sema); + + while (1) { + if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) { + RTW_PRINT(FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter)); + break; + } + + if (RTW_CANNOT_RUN(padapter)) { + RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n", + __func__ + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False" + , __LINE__); + break; + } + + if (pcmdpriv->stop_req) { + RTW_PRINT(FUNC_ADPT_FMT" stop_req:%u, break\n", FUNC_ADPT_ARG(padapter), pcmdpriv->stop_req); + break; + } + + _enter_critical(&pcmdpriv->cmd_queue.lock, &irqL); + if (rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) { + /* RTW_INFO("%s: cmd queue is empty!\n", __func__); */ + _exit_critical(&pcmdpriv->cmd_queue.lock, &irqL); + continue; + } + _exit_critical(&pcmdpriv->cmd_queue.lock, &irqL); + +_next: + if (RTW_CANNOT_RUN(padapter)) { + RTW_PRINT("%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n", + __func__ + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False" + , __LINE__); + break; + } + + pcmd = rtw_dequeue_cmd(pcmdpriv); + if (!pcmd) { + continue; + } + + cmd_start_time = rtw_get_current_time(); + pcmdpriv->cmd_issued_cnt++; + + if (pcmd->cmdsz > MAX_CMDSZ) { + RTW_ERR("%s cmdsz:%d > MAX_CMDSZ:%d\n", __func__, pcmd->cmdsz, MAX_CMDSZ); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } + + if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct cmd_hdl))) { + RTW_ERR("%s undefined cmdcode:%d\n", __func__, pcmd->cmdcode); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } + + cmd_hdl = wlancmds[pcmd->cmdcode].h2cfuns; + if (!cmd_hdl) { + RTW_ERR("%s no cmd_hdl for cmdcode:%d\n", __func__, pcmd->cmdcode); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } + + if (_FAIL == rtw_cmd_filter(pcmdpriv, pcmd)) { + pcmd->res = H2C_DROPPED; + if (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { + extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf; + if (extra_parm && extra_parm->pbuf && extra_parm->size > 0) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + goto post_process; + } + + + if (DBG_CMD_EXECUTE) + RTW_INFO(ADPT_FMT" "CMD_FMT" %sexecute\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd) + , pcmd->res == H2C_ENQ_HEAD ? "ENQ_HEAD " : (pcmd->res == H2C_ENQ_HEAD_FAIL ? "ENQ_HEAD_FAIL " : "")); + + _rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz); + ret = cmd_hdl(pcmd->padapter, pcmdbuf); + pcmd->res = ret; + + pcmdpriv->cmd_seq++; + +post_process: + + _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + if (pcmd->sctx) { + if (0) + RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); + if (pcmd->res == H2C_SUCCESS) + rtw_sctx_done(&pcmd->sctx); + else + rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR); + } + _exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + + cmd_process_time = rtw_get_passing_time_ms(cmd_start_time); + if (cmd_process_time > 1000) { + RTW_INFO(ADPT_FMT" "CMD_FMT" process_time=%d\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd), cmd_process_time); + if (0) + rtw_warn_on(1); + } + + /* call callback function for post-processed */ + if (pcmd->cmdcode < (sizeof(rtw_cmd_callback) / sizeof(struct _cmd_callback))) { + pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback; + if (pcmd_callback == NULL) { + rtw_free_cmd_obj(pcmd); + } else { + /* todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) */ + pcmd_callback(pcmd->padapter, pcmd);/* need conider that free cmd_obj in rtw_cmd_callback */ + } + } else { + rtw_free_cmd_obj(pcmd); + } + + flush_signals_thread(); + + goto _next; + + } + + + /* to avoid enqueue cmd after free all cmd_obj */ + ATOMIC_SET(&(pcmdpriv->cmdthd_running), _FALSE); + + /* free all cmd_obj resources */ + do { + pcmd = rtw_dequeue_cmd(pcmdpriv); + if (pcmd == NULL) + break; + + if (0) + RTW_INFO("%s: leaving... drop "CMD_FMT"\n", __func__, CMD_ARG(pcmd)); + + if (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { + extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf; + if (extra_parm->pbuf && extra_parm->size > 0) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + + _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + if (pcmd->sctx) { + if (0) + RTW_PRINT(FUNC_ADPT_FMT" pcmd->sctx\n", FUNC_ADPT_ARG(pcmd->padapter)); + rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_DROP); + } + _exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + + rtw_free_cmd_obj(pcmd); + } while (1); + + /*_rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema);*/ + thread_exit(&pcmdpriv->cmdthread_comp); + return 0; +} + +/* +rtw_sitesurvey_cmd(~) + ### NOTE:#### (!!!!) + MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock +*/ +u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, + struct rtw_ieee80211_channel *ch, int ch_num) +{ + u8 res = _FAIL; + struct cmd_obj *ph2c; + struct sitesurvey_parm *psurveyPara; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1); + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) + return _FAIL; + + psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm)); + if (psurveyPara == NULL) { + rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); + return _FAIL; + } + + rtw_free_network_queue(padapter, _FALSE); + + init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); + + /* psurveyPara->bsslimit = 48; */ + psurveyPara->scan_mode = pmlmepriv->scan_mode; + + /* prepare ssid list */ + if (ssid) { + int i; + for (i = 0; i < ssid_num && i < RTW_SSID_SCAN_AMOUNT; i++) { + if (ssid[i].SsidLength) { + _rtw_memcpy(&psurveyPara->ssid[i], &ssid[i], sizeof(NDIS_802_11_SSID)); + psurveyPara->ssid_num++; + if (0) + RTW_INFO(FUNC_ADPT_FMT" ssid:(%s, %d)\n", FUNC_ADPT_ARG(padapter), + psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength); + } + } + } + + /* prepare channel list */ + if (ch) { + int i; + for (i = 0; i < ch_num && i < RTW_CHANNEL_SCAN_AMOUNT; i++) { + if (ch[i].hw_value && !(ch[i].flags & RTW_IEEE80211_CHAN_DISABLED)) { + _rtw_memcpy(&psurveyPara->ch[i], &ch[i], sizeof(struct rtw_ieee80211_channel)); + psurveyPara->ch_num++; + if (0) + RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), + psurveyPara->ch[i].hw_value); + } + } + } + + set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + + if (res == _SUCCESS) { + + pmlmepriv->scan_start_time = rtw_get_current_time(); + + mlme_set_scan_to_timer(pmlmepriv, SCANNING_TIMEOUT); + + rtw_led_control(padapter, LED_CTL_SITE_SURVEY); + } else + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + + return res; +} + +u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset) +{ + struct cmd_obj *ph2c; + struct setdatarate_parm *pbsetdataratepara; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pbsetdataratepara = (struct setdatarate_parm *)rtw_zmalloc(sizeof(struct setdatarate_parm)); + if (pbsetdataratepara == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, pbsetdataratepara, GEN_CMD_CODE(_SetDataRate)); + pbsetdataratepara->mac_id = 5; + _rtw_memcpy(pbsetdataratepara->datarates, rateset, NumRates); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: + + return res; +} + +void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) +{ + + /* rtw_free_cmd_obj(pcmd); */ + rtw_mfree((unsigned char *) pcmd->parmbuf, pcmd->cmdsz); + rtw_mfree((unsigned char *) pcmd, sizeof(struct cmd_obj)); + + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.workparam.bcompleted = _TRUE; +} + +static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc + , s16 req_ch, s8 req_bw, s8 req_offset) +{ + struct cmd_obj *cmdobj; + struct createbss_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + if (req_ch > 0 && req_bw >= 0 && req_offset >= 0) { + if (!rtw_chset_is_chbw_valid(adapter->mlmeextpriv.channel_set, req_ch, req_bw, req_offset)) { + res = _FAIL; + goto exit; + } + } + + /* prepare cmd parameter */ + parm = (struct createbss_parm *)rtw_zmalloc(sizeof(*parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + + if (adhoc) { + /* for now, adhoc doesn't support ch,bw,offset request */ + parm->adhoc = 1; + } else { + parm->adhoc = 0; + parm->req_ch = req_ch; + parm->req_bw = req_bw; + parm->req_offset = req_offset; + } + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != createbss_hdl(adapter, (u8 *)parm)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_CreateBss)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } + +exit: + return res; +} + +inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags) +{ + return rtw_createbss_cmd(adapter, flags + , 1 + , 0, -1, -1 /* for now, adhoc doesn't support ch,bw,offset request */ + ); +} + +inline u8 rtw_startbss_cmd(_adapter *adapter, int flags) +{ + return rtw_createbss_cmd(adapter, flags + , 0 + , 0, -1, -1 /* excute entire AP setup cmd */ + ); +} + +u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork) +{ + u8 *auth, res = _SUCCESS; + uint t_len = 0; + WLAN_BSSID_EX *psecnetwork; + struct cmd_obj *pcmd; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u32 tmp_len; + u8 *ptmp = NULL; + + rtw_led_control(padapter, LED_CTL_START_TO_LINK); + + pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd == NULL) { + res = _FAIL; + goto exit; + } + /* for IEs is fix buf size */ + t_len = sizeof(WLAN_BSSID_EX); + + /* for hidden ap to set fw_state here */ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) != _TRUE) { + switch (ndis_network_mode) { + case Ndis802_11IBSS: + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + break; + + case Ndis802_11Infrastructure: + set_fwstate(pmlmepriv, WIFI_STATION_STATE); + break; + + case Ndis802_11APMode: + case Ndis802_11AutoUnknown: + case Ndis802_11InfrastructureMax: + case Ndis802_11Monitor: + break; + + } + } + + pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength); + + /* + Modified by Arvin 2015/05/13 + Solution for allocating a new WLAN_BSSID_EX to avoid race condition issue between disconnect and joinbss + */ + psecnetwork = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX)); + if (psecnetwork == NULL) { + if (pcmd != NULL) + rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + + res = _FAIL; + + goto exit; + } + + _rtw_memset(psecnetwork, 0, t_len); + + _rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network)); + + auth = &psecuritypriv->authenticator_ie[0]; + psecuritypriv->authenticator_ie[0] = (unsigned char)psecnetwork->IELength; + + if ((psecnetwork->IELength - 12) < (256 - 1)) + _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength - 12); + else + _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256 - 1)); + + psecnetwork->IELength = 0; + /* Added by Albert 2009/02/18 */ + /* If the the driver wants to use the bssid to create the connection. */ + /* If not, we have to copy the connecting AP's MAC address to it so that */ + /* the driver just has the bssid information for PMKIDList searching. */ + + if (pmlmepriv->assoc_by_bssid == _FALSE) + _rtw_memcpy(&pmlmepriv->assoc_bssid[0], &pnetwork->network.MacAddress[0], ETH_ALEN); + + psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength); + + pqospriv->qos_option = 0; + + if (pregistrypriv->wmm_enable) { + tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength); + + if (psecnetwork->IELength != tmp_len) { + psecnetwork->IELength = tmp_len; + pqospriv->qos_option = 1; /* There is WMM IE in this corresp. beacon */ + } else { + pqospriv->qos_option = 0;/* There is no WMM IE in this corresp. beacon */ + } + } + + phtpriv->ht_option = _FALSE; + ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength - 12); + if (pregistrypriv->ht_enable && ptmp && tmp_len > 0) { + /* Added by Albert 2010/06/23 */ + /* For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. */ + /* Especially for Realtek 8192u SoftAP. */ + if ((padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_) && + (padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_) && + (padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_)) { + rtw_ht_use_default_setting(padapter); + + rtw_build_wmm_ie_ht(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); + + /* rtw_restructure_ht_ie */ + rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0], + pnetwork->network.IELength - 12, &psecnetwork->IELength, + pnetwork->network.Configuration.DSConfig); + } + } + + pvhtpriv->vht_option = _FALSE; + if (phtpriv->ht_option + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) + ) { + rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], + pnetwork->network.IELength, &psecnetwork->IELength); + } + + rtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); + + + pcmd->cmdsz = sizeof(WLAN_BSSID_EX); + + _rtw_init_listhead(&pcmd->list); + pcmd->cmdcode = _JoinBss_CMD_;/* GEN_CMD_CODE(_JoinBss) */ + pcmd->parmbuf = (unsigned char *)psecnetwork; + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + +exit: + + return res; +} + +u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags) /* for sta_mode */ +{ + struct cmd_obj *cmdobj = NULL; + struct disconnect_parm *param = NULL; + struct cmd_priv *cmdpriv = &padapter->cmdpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + /* prepare cmd parameter */ + param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param)); + if (param == NULL) { + res = _FAIL; + goto exit; + } + param->deauth_timeout_ms = deauth_timeout_ms; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (disconnect_hdl(padapter, (u8 *)param) != H2C_SUCCESS) + res = _FAIL; + rtw_mfree((u8 *)param, sizeof(*param)); + + } else { + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)param, sizeof(*param)); + goto exit; + } + init_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_); + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } + +exit: + + return res; +} + +u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue) +{ + struct cmd_obj *ph2c; + struct setopmode_parm *psetop; + + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + psetop = (struct setopmode_parm *)rtw_zmalloc(sizeof(struct setopmode_parm)); + + if (psetop == NULL) { + res = _FAIL; + goto exit; + } + psetop->mode = (u8)networktype; + + if (enqueue) { + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + rtw_mfree((u8 *)psetop, sizeof(*psetop)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } else { + setopmode_hdl(padapter, (u8 *)psetop); + rtw_mfree((u8 *)psetop, sizeof(*psetop)); + } +exit: + + return res; +} + +u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue) +{ + struct cmd_obj *ph2c; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct set_stakey_rsp *psetstakey_rsp = NULL; + + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + u8 res = _SUCCESS; + + psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if (psetstakey_para == NULL) { + res = _FAIL; + goto exit; + } + + _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + psetstakey_para->algorithm = (unsigned char) psecuritypriv->dot11PrivacyAlgrthm; + else + GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); + + if (key_type == GROUP_KEY) + _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16); + else if (key_type == UNICAST_KEY) + _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16); + + /* jeff: set this becasue at least sw key is ready */ + padapter->securitypriv.busetkipkey = _TRUE; + + if (enqueue) { + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res = _FAIL; + goto exit; + } + + psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp)); + if (psetstakey_rsp == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); + ph2c->rsp = (u8 *) psetstakey_rsp; + ph2c->rspsz = sizeof(struct set_stakey_rsp); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } else { + set_stakey_hdl(padapter, (u8 *)psetstakey_para); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + } +exit: + + return res; +} + +u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) +{ + struct cmd_obj *ph2c; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct set_stakey_rsp *psetstakey_rsp = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + s16 cam_id = 0; + u8 res = _SUCCESS; + + if (!enqueue) { + while ((cam_id = rtw_camid_search(padapter, sta->hwaddr, -1, -1)) >= 0) { + RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->hwaddr), cam_id); + clear_cam_entry(padapter, cam_id); + rtw_camid_free(padapter, cam_id); + } + } else { + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + psetstakey_para = (struct set_stakey_parm *)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if (psetstakey_para == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + psetstakey_rsp = (struct set_stakey_rsp *)rtw_zmalloc(sizeof(struct set_stakey_rsp)); + if (psetstakey_rsp == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); + ph2c->rsp = (u8 *) psetstakey_rsp; + ph2c->rspsz = sizeof(struct set_stakey_rsp); + + _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); + + psetstakey_para->algorithm = _NO_PRIVACY_; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + + } + +exit: + + return res; +} + +u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr) +{ + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj *ph2c; + struct addBaReq_parm *paddbareq_parm; + + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + paddbareq_parm = (struct addBaReq_parm *)rtw_zmalloc(sizeof(struct addBaReq_parm)); + if (paddbareq_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + paddbareq_parm->tid = tid; + _rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN); + + init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, GEN_CMD_CODE(_AddBAReq)); + + /* RTW_INFO("rtw_addbareq_cmd, tid=%d\n", tid); */ + + /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; +} + +u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq) +{ + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj *ph2c; + struct addBaRsp_parm *paddBaRsp_parm; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + paddBaRsp_parm = (struct addBaRsp_parm *)rtw_zmalloc(sizeof(struct addBaRsp_parm)); + + if (paddBaRsp_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + _rtw_memcpy(paddBaRsp_parm->addr, addr, ETH_ALEN); + paddBaRsp_parm->tid = tid; + paddBaRsp_parm->status = status; + paddBaRsp_parm->size = size; + paddBaRsp_parm->start_seq = start_seq; + + init_h2fwcmd_w_parm_no_rsp(ph2c, paddBaRsp_parm, GEN_CMD_CODE(_AddBARsp)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; +} +/* add for CONFIG_IEEE80211W, none 11w can use it */ +u8 rtw_reset_securitypriv_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +u8 rtw_free_assoc_resources_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +u8 rtw_dynamic_chk_wk_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + /* only primary padapter does this cmd */ + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) +{ + struct cmd_obj *pcmdobj; + struct set_ch_parm *set_ch_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res = _SUCCESS; + + RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset); + + /* check input parameter */ + + /* prepare cmd parameter */ + set_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm)); + if (set_ch_parm == NULL) { + res = _FAIL; + goto exit; + } + set_ch_parm->ch = ch; + set_ch_parm->bw = bw; + set_ch_parm->ch_offset = ch_offset; + + if (enqueue) { + /* need enqueue, prepare cmd_obj and enqueue */ + pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmdobj == NULL) { + rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel)); + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + } else { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != set_ch_hdl(padapter, (u8 *)set_ch_parm)) + res = _FAIL; + + rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + } + + /* do something based on res... */ + +exit: + + RTW_INFO(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res); + + return res; +} + +u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct country_chplan *country_ent, u8 swconfig) +{ + struct cmd_obj *cmdobj; + struct SetChannelPlan_param *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + /* check if allow software config */ + if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) { + res = _FAIL; + goto exit; + } + + /* if country_entry is provided, replace chplan */ + if (country_ent) + chplan = country_ent->chplan; + + /* check input parameter */ + if (!rtw_is_channel_plan_valid(chplan)) { + res = _FAIL; + goto exit; + } + + /* prepare cmd parameter */ + parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + parm->country_ent = country_ent; + parm->channel_plan = chplan; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_SetChannelPlan)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } + +exit: + + return res; +} + +inline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig) +{ + return _rtw_set_chplan_cmd(adapter, flags, chplan, NULL, swconfig); +} + +inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig) +{ + const struct country_chplan *ent; + + if (is_alpha(country_code[0]) == _FALSE + || is_alpha(country_code[1]) == _FALSE + ) { + RTW_PRINT("%s input country_code is not alpha2\n", __func__); + return _FAIL; + } + + ent = rtw_get_chplan_from_country(country_code); + + if (ent == NULL) { + RTW_PRINT("%s unsupported country_code:\"%c%c\"\n", __func__, country_code[0], country_code[1]); + return _FAIL; + } + + RTW_PRINT("%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan); + + return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_MAX, ent, swconfig); +} + +u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = EN_HW_UPDATE_TSF_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; +} + +/* from_timer == 1 means driver is in LPS */ +u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) +{ + u8 bEnterPS = _FALSE; + u16 BusyThresholdHigh; + u16 BusyThresholdLow; + u16 BusyThreshold; + u8 bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE; + u8 bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE; + + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + RT_LINK_DETECT_T *link_detect = &pmlmepriv->LinkDetectInfo; + + if (padapter->registrypriv.wifi_spec != 1) { + BusyThresholdHigh = 25; + BusyThresholdLow = 10; + } else + { + BusyThresholdHigh = 100; + BusyThresholdLow = 75; + } + BusyThreshold = BusyThresholdHigh; + + /* */ + /* Determine if our traffic is busy now */ + /* */ + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) { + /* if we raise bBusyTraffic in last watchdog, using lower threshold. */ + if (pmlmepriv->LinkDetectInfo.bBusyTraffic) + BusyThreshold = BusyThresholdLow; + + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold || + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold) { + bBusyTraffic = _TRUE; + + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) + bRxBusyTraffic = _TRUE; + else + bTxBusyTraffic = _TRUE; + } + + /* Higher Tx/Rx data. */ + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 || + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000) { + bHigherBusyTraffic = _TRUE; + + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) + bHigherBusyRxTraffic = _TRUE; + else + bHigherBusyTxTraffic = _TRUE; + } + +#define TX_ACTIVE_TH 10 +#define RX_ACTIVE_TH 20 +#define TRAFFIC_PROTECT_PERIOD_MS 4500 + + if (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH + || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) { + + RTW_INFO(FUNC_ADPT_FMT" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\n", + FUNC_ADPT_ARG(padapter), + TRAFFIC_PROTECT_PERIOD_MS, + link_detect->NumTxOkInPeriod, + link_detect->NumRxUnicastOkInPeriod); + + rtw_lock_traffic_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS); + } + + /* check traffic for powersaving. */ + if (((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8) || + (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4) + ) { + bEnterPS = _FALSE; + + } else { + bEnterPS = _TRUE; + } + + + /* LeisurePS only work in infra mode. */ + if (bEnterPS) { + if (!from_timer) { + LPS_Enter(padapter, "TRAFFIC_IDLE"); + } else { + /* do this at caller */ + /* rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 1); */ + /* rtw_hal_dm_watchdog_in_lps(padapter); */ + } + } else { + if (!from_timer) + LPS_Leave(padapter, "TRAFFIC_BUSY"); + else { + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 1); + } + } + + } else { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + int n_assoc_iface = 0; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) + n_assoc_iface++; + } + + if (!from_timer && n_assoc_iface == 0) + LPS_Leave(padapter, "NON_LINKED"); + } + + session_tracker_chk_cmd(padapter, NULL); + + + pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0; + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0; + pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; + pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic; + pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic; + pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic; + pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic; + pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic; + pmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic; + + return bEnterPS; + +} + +/* for 11n Logo 4.2.31/4.2.32 */ +static void dynamic_update_bcn_check(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (!padapter->registrypriv.wifi_spec) + return; + + if (!MLME_IS_AP(padapter)) + return; + + if (pmlmeext->bstart_bss) { + /* In 10 * 2 = 20s, there are no legacy AP, update HT info */ + static u8 count = 1; + + if (count % 10 == 0) { + count = 1; + + if (_FALSE == ATOMIC_READ(&pmlmepriv->olbc) + && _FALSE == ATOMIC_READ(&pmlmepriv->olbc_ht)) { + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + } + } + } + + /* In 2s, there are any legacy AP, update HT info, and then reset count */ + + if (_FALSE != ATOMIC_READ(&pmlmepriv->olbc) + && _FALSE != ATOMIC_READ(&pmlmepriv->olbc_ht)) { + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + + } + ATOMIC_SET(&pmlmepriv->olbc, _FALSE); + ATOMIC_SET(&pmlmepriv->olbc_ht, _FALSE); + count = 0; + } + + count ++; + } +} +void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + expire_timeout_chk(padapter); + dynamic_update_bcn_check(padapter); + + linked_status_chk(padapter, 0); + traffic_status_watchdog(padapter, 0); + + /* for debug purpose */ + _linked_info_dump(padapter); + + +} +void rtw_dynamic_chk_wk_hdl(_adapter *padapter) +{ + rtw_mi_dynamic_chk_wk_hdl(padapter); + + rtw_hal_sreset_xmit_status_check(padapter); + rtw_hal_sreset_linked_status_check(padapter); + + /* if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) */ + { + dm_DynamicUsbTxAgg(padapter, 0); + } + rtw_hal_dm_watchdog(padapter); + + /* check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); */ + + /* BT-Coexist */ + rtw_btcoex_Handler(padapter); + +#ifdef CONFIG_IPS_CHECK_IN_WD + /* always call rtw_ps_processor() at last one. */ + rtw_ps_processor(padapter); +#endif + +} + + +void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type); +void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 mstatus; + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) + || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + return; + + switch (lps_ctrl_type) { + case LPS_CTRL_SCAN: + /* RTW_INFO("LPS_CTRL_SCAN\n"); */ + rtw_btcoex_ScanNotify(padapter, _TRUE); + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + /* connect */ + LPS_Leave(padapter, "LPS_CTRL_SCAN"); + } + break; + case LPS_CTRL_JOINBSS: + /* RTW_INFO("LPS_CTRL_JOINBSS\n"); */ + LPS_Leave(padapter, "LPS_CTRL_JOINBSS"); + break; + case LPS_CTRL_CONNECT: + /* RTW_INFO("LPS_CTRL_CONNECT\n"); */ + mstatus = 1;/* connect */ + /* Reset LPS Setting */ + pwrpriv->LpsIdleCount = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); + rtw_btcoex_MediaStatusNotify(padapter, mstatus); + break; + case LPS_CTRL_DISCONNECT: + /* RTW_INFO("LPS_CTRL_DISCONNECT\n"); */ + mstatus = 0;/* disconnect */ + rtw_btcoex_MediaStatusNotify(padapter, mstatus); + LPS_Leave(padapter, "LPS_CTRL_DISCONNECT"); + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); + break; + case LPS_CTRL_SPECIAL_PACKET: + /* RTW_INFO("LPS_CTRL_SPECIAL_PACKET\n"); */ + pwrpriv->DelayLPSLastTimeStamp = rtw_get_current_time(); + rtw_btcoex_SpecialPacketNotify(padapter, PACKET_DHCP); + LPS_Leave(padapter, "LPS_CTRL_SPECIAL_PACKET"); + break; + case LPS_CTRL_LEAVE: + LPS_Leave(padapter, "LPS_CTRL_LEAVE"); + break; + case LPS_CTRL_LEAVE_CFG80211_PWRMGMT: + LPS_Leave(padapter, "CFG80211_PWRMGMT"); + break; + case LPS_CTRL_TRAFFIC_BUSY: + LPS_Leave(padapter, "LPS_CTRL_TRAFFIC_BUSY"); + break; + case LPS_CTRL_TX_TRAFFIC_LEAVE: + LPS_Leave(padapter, "LPS_CTRL_TX_TRAFFIC_LEAVE"); + break; + case LPS_CTRL_RX_TRAFFIC_LEAVE: + LPS_Leave(padapter, "LPS_CTRL_RX_TRAFFIC_LEAVE"); + break; + case LPS_CTRL_ENTER: + LPS_Enter(padapter, "TRAFFIC_IDLE_1"); + break; + default: + break; + } + +} + +u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + /* struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); */ + u8 res = _SUCCESS; + + /* if(!pwrctrlpriv->bLeisurePs) */ + /* return res; */ + + if (enqueue) { + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = LPS_CTRL_WK_CID; + pdrvextra_cmd_parm->type = lps_ctrl_type; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } else + lps_ctrl_wk_hdl(padapter, lps_ctrl_type); + +exit: + + return res; + +} + +void rtw_dm_in_lps_hdl(_adapter *padapter) +{ + rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS, NULL); +} + +void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + if (dtim <= 0 || dtim > 16) + return; + + if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + return; + + + if (pwrpriv->dtim != dtim) { + RTW_INFO("change DTIM from %d to %d, bFwCurrentInPSMode=%d, ps_mode=%d\n", pwrpriv->dtim, dtim, + pwrpriv->bFwCurrentInPSMode, pwrpriv->pwr_mode); + + pwrpriv->dtim = dtim; + } + + if ((pwrpriv->bFwCurrentInPSMode == _TRUE) && (pwrpriv->pwr_mode > PS_MODE_ACTIVE)) { + u8 ps_mode = pwrpriv->pwr_mode; + + /* RTW_INFO("change DTIM from %d to %d, ps_mode=%d\n", pwrpriv->dtim, dtim, ps_mode); */ + + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + } + + +} + + +u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + { + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = LPS_CHANGE_DTIM_CID; + pdrvextra_cmd_parm->type = dtim; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + +exit: + + return res; + +} + + + +void rtw_dm_ra_mask_hdl(_adapter *padapter, struct sta_info *psta) +{ + if (psta) + set_sta_rate(padapter, psta); +} + +u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = DM_RA_MSK_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = psta; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +void power_saving_wk_hdl(_adapter *padapter) +{ + rtw_ps_processor(padapter); +} + +/* add for CONFIG_IEEE80211W, none 11w can use it */ +void reset_securitypriv_hdl(_adapter *padapter) +{ + rtw_reset_securitypriv(padapter); +} + +void free_assoc_resources_hdl(_adapter *padapter) +{ + rtw_free_assoc_resources(padapter, 1); +} + +u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return res; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID; + pdrvextra_cmd_parm->type = intCmdType; /* As the command tppe. */ + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; /* Must be NULL here */ + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + + +u8 rtw_ps_cmd(_adapter *padapter) +{ + struct cmd_obj *ppscmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res = _SUCCESS; + + + ppscmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ppscmd == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ppscmd); + +exit: + + return res; + +} + + +static void rtw_chk_hi_queue_hdl(_adapter *padapter) +{ + struct sta_info *psta_bmc; + struct sta_priv *pstapriv = &padapter->stapriv; + u32 start = rtw_get_current_time(); + u8 empty = _FALSE; + + psta_bmc = rtw_get_bcmc_stainfo(padapter); + if (!psta_bmc) + return; + + rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty); + + while (_FALSE == empty && rtw_get_passing_time_ms(start) < rtw_get_wait_hiq_empty_ms()) { + rtw_msleep_os(100); + rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty); + } + + if (psta_bmc->sleepq_len == 0) { + if (empty == _SUCCESS) { + bool update_tim = _FALSE; + + if (pstapriv->tim_bitmap & BIT(0)) + update_tim = _TRUE; + + pstapriv->tim_bitmap &= ~BIT(0); + pstapriv->sta_dz_bitmap &= ~BIT(0); + + if (update_tim == _TRUE) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty"); + } else /* re check again */ + rtw_chk_hi_queue_cmd(padapter); + + } + +} + +u8 rtw_chk_hi_queue_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + + + +struct btinfo { + u8 cid; + u8 len; + + u8 bConnection:1; + u8 bSCOeSCO:1; + u8 bInQPage:1; + u8 bACLBusy:1; + u8 bSCOBusy:1; + u8 bHID:1; + u8 bA2DP:1; + u8 bFTP:1; + + u8 retry_cnt:4; + u8 rsvd_34:1; + u8 rsvd_35:1; + u8 rsvd_36:1; + u8 rsvd_37:1; + + u8 rssi; + + u8 rsvd_50:1; + u8 rsvd_51:1; + u8 rsvd_52:1; + u8 rsvd_53:1; + u8 rsvd_54:1; + u8 rsvd_55:1; + u8 eSCO_SCO:1; + u8 Master_Slave:1; + + u8 rsvd_6; + u8 rsvd_7; +}; + +void btinfo_evt_dump(void *sel, void *buf) +{ + struct btinfo *info = (struct btinfo *)buf; + + RTW_PRINT_SEL(sel, "cid:0x%02x, len:%u\n", info->cid, info->len); + + if (info->len > 2) + RTW_PRINT_SEL(sel, "byte2:%s%s%s%s%s%s%s%s\n" + , info->bConnection ? "bConnection " : "" + , info->bSCOeSCO ? "bSCOeSCO " : "" + , info->bInQPage ? "bInQPage " : "" + , info->bACLBusy ? "bACLBusy " : "" + , info->bSCOBusy ? "bSCOBusy " : "" + , info->bHID ? "bHID " : "" + , info->bA2DP ? "bA2DP " : "" + , info->bFTP ? "bFTP" : "" + ); + + if (info->len > 3) + RTW_PRINT_SEL(sel, "retry_cnt:%u\n", info->retry_cnt); + + if (info->len > 4) + RTW_PRINT_SEL(sel, "rssi:%u\n", info->rssi); + + if (info->len > 5) + RTW_PRINT_SEL(sel, "byte5:%s%s\n" + , info->eSCO_SCO ? "eSCO_SCO " : "" + , info->Master_Slave ? "Master_Slave " : "" + ); +} + +static void rtw_btinfo_hdl(_adapter *adapter, u8 *buf, u16 buf_len) +{ +#define BTINFO_WIFI_FETCH 0x23 +#define BTINFO_BT_AUTO_RPT 0x27 + struct btinfo *info = (struct btinfo *)buf; + u8 cmd_idx; + u8 len; + + cmd_idx = info->cid; + + if (info->len > buf_len - 2) { + rtw_warn_on(1); + len = buf_len - 2; + } else + len = info->len; + + /* #define DBG_PROC_SET_BTINFO_EVT */ +#ifdef DBG_PROC_SET_BTINFO_EVT + btinfo_evt_dump(RTW_DBGDUMP, info); +#endif /* DBG_PROC_SET_BTINFO_EVT */ + + /* transform BT-FW btinfo to WiFI-FW C2H format and notify */ + if (cmd_idx == BTINFO_WIFI_FETCH) + buf[1] = 0; + else if (cmd_idx == BTINFO_BT_AUTO_RPT) + buf[1] = 2; + rtw_btcoex_BtInfoNotify(adapter , len + 1, &buf[1]); +} + +u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len) +{ + struct cmd_obj *pcmdobj; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + u8 *ph2c_content; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + u8 res = _SUCCESS; + + pcmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmdobj == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + ph2c_content = rtw_zmalloc(len); + if (ph2c_content == NULL) { + rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = TEST_H2C_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = len; + pdrvextra_cmd_parm->pbuf = ph2c_content; + + _rtw_memcpy(ph2c_content, buf, len); + + init_h2fwcmd_w_parm_no_rsp(pcmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + +exit: + return res; +} + +static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + int ret = H2C_SUCCESS; + u8 rfreg0; + + if (mp_cmd_id == MP_START) { + if (padapter->registrypriv.mp_mode == 0) { + rtw_hal_deinit(padapter); + padapter->registrypriv.mp_mode = 1; + rtw_hal_init(padapter); + MPT_InitializeAdapter(padapter, 1); + } + + if (padapter->registrypriv.mp_mode == 0) { + ret = H2C_REJECTED; + goto exit; + } + + if (padapter->mppriv.mode == MP_OFF) { + if (mp_start_test(padapter) == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } + padapter->mppriv.mode = MP_ON; + MPT_PwrCtlDM(padapter, 0); + } + padapter->mppriv.bmac_filter = _FALSE; + odm_write_dig(&pHalData->odmpriv, 0x20); + + } else if (mp_cmd_id == MP_STOP) { + if (padapter->registrypriv.mp_mode == 1) { + MPT_DeInitAdapter(padapter); + rtw_hal_deinit(padapter); + padapter->registrypriv.mp_mode = 0; + rtw_hal_init(padapter); + } + + if (padapter->mppriv.mode != MP_OFF) { + mp_stop_test(padapter); + padapter->mppriv.mode = MP_OFF; + } + + } else { + RTW_INFO(FUNC_ADPT_FMT"invalid id:%d\n", FUNC_ADPT_ARG(padapter), mp_cmd_id); + ret = H2C_PARAMETERS_ERROR; + rtw_warn_on(1); + } + +exit: + return ret; +} + +u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + + parm->ec_id = MP_CMD_WK_CID; + parm->type = mp_cmd_id; + parm->size = 0; + parm->pbuf = NULL; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } + +exit: + return res; +} + +u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length, u8 type) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 *extra_cmd_buf; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + extra_cmd_buf = rtw_zmalloc(length); + if (extra_cmd_buf == NULL) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + _rtw_memcpy(extra_cmd_buf, pbuf, length); + pdrvextra_cmd_parm->ec_id = C2H_WK_CID; + pdrvextra_cmd_parm->type = type; + pdrvextra_cmd_parm->size = length; + pdrvextra_cmd_parm->pbuf = extra_cmd_buf; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; +} + + +inline u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length) +{ + return rtw_c2h_wk_cmd(adapter, c2h_evt, length, C2H_TYPE_PKT); +} + +u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context) +{ + struct cmd_priv *pcmdpriv; + struct cmd_obj *ph2c; + struct RunInThread_param *parm; + s32 res = _SUCCESS; + + pcmdpriv = &padapter->cmdpriv; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (NULL == ph2c) { + res = _FAIL; + goto exit; + } + + parm = (struct RunInThread_param *)rtw_zmalloc(sizeof(struct RunInThread_param)); + if (NULL == parm) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + parm->func = func; + parm->context = context; + init_h2fwcmd_w_parm_no_rsp(ph2c, parm, GEN_CMD_CODE(_RunInThreadCMD)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: + + return res; +} + +u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *cmd_parm; + struct st_cmd_parm *st_parm; + u8 res = _SUCCESS; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { + res = _FAIL; + goto exit; + } + + cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (cmd_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + st_parm = (struct st_cmd_parm *)rtw_zmalloc(sizeof(struct st_cmd_parm)); + if (st_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + st_parm->cmd = cmd; + st_parm->sta = sta; + if (cmd != ST_CMD_CHK) { + _rtw_memcpy(&st_parm->local_naddr, local_naddr, 4); + _rtw_memcpy(&st_parm->local_port, local_port, 2); + _rtw_memcpy(&st_parm->remote_naddr, remote_naddr, 4); + _rtw_memcpy(&st_parm->remote_port, remote_port, 2); + } + + cmd_parm->ec_id = SESSION_TRACKER_WK_CID; + cmd_parm->type = 0; + cmd_parm->size = sizeof(struct st_cmd_parm); + cmd_parm->pbuf = (u8 *)st_parm; + init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + cmdobj->no_io = 1; + + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + +exit: + return res; +} + +inline u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta) +{ + return session_tracker_cmd(adapter, ST_CMD_CHK, sta, NULL, NULL, NULL, NULL); +} + +inline u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + return session_tracker_cmd(adapter, ST_CMD_ADD, sta, local_naddr, local_port, remote_naddr, remote_port); +} + +inline u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + return session_tracker_cmd(adapter, ST_CMD_DEL, sta, local_naddr, local_port, remote_naddr, remote_port); +} + +void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta) +{ + struct st_ctl_t *st_ctl = &sta->st_ctl; + int i; + _irqL irqL; + _list *plist, *phead, *pnext; + _list dlist; + struct session_tracker *st = NULL; + u8 op_wfd_mode = MIRACAST_DISABLED; + + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" sta:%p\n", FUNC_ADPT_ARG(adapter), sta); + + if (!(sta->state & _FW_LINKED)) + goto exit; + + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) { + if (st_ctl->reg[i].s_proto != 0) + break; + } + if (i >= SESSION_TRACKER_REG_ID_NUM) + goto chk_sta; + + _rtw_init_listhead(&dlist); + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + phead = &st_ctl->tracker_q.queue; + plist = get_next(phead); + pnext = get_next(plist); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + plist = pnext; + pnext = get_next(pnext); + + if (st->status != ST_STATUS_ESTABLISH + && rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS + ) { + rtw_list_delete(&st->list); + rtw_list_insert_tail(&st->list, &dlist); + } + + /* TODO: check OS for status update */ + if (st->status == ST_STATUS_CHECK) + st->status = ST_STATUS_ESTABLISH; + + if (st->status != ST_STATUS_ESTABLISH) + continue; + + if (0) + RTW_INFO(FUNC_ADPT_FMT" local:%u, remote:%u, rtsp:%u, %u, %u\n", FUNC_ADPT_ARG(adapter) + , ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport + , adapter->wfd_info.peer_rtsp_ctrlport); + if (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport) + op_wfd_mode |= MIRACAST_SINK; + if (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport) + op_wfd_mode |= MIRACAST_SINK; + if (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport) + op_wfd_mode |= MIRACAST_SOURCE; + } + + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + plist = get_next(&dlist); + while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + plist = get_next(plist); + rtw_mfree((u8 *)st, sizeof(struct session_tracker)); + } + +chk_sta: + if (STA_OP_WFD_MODE(sta) != op_wfd_mode) { + STA_SET_OP_WFD_MODE(sta, op_wfd_mode); + rtw_sta_media_status_rpt_cmd(adapter, sta, 1); + } + +exit: + return; +} + +void session_tracker_chk_for_adapter(_adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + int i; + _irqL irqL; + _list *plist, *phead; + u8 op_wfd_mode = MIRACAST_DISABLED; + + _enter_critical_bh(&stapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + phead = &(stapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + + session_tracker_chk_for_sta(adapter, sta); + + op_wfd_mode |= STA_OP_WFD_MODE(sta); + } + } + + _exit_critical_bh(&stapriv->sta_hash_lock, &irqL); + + adapter->wfd_info.op_wfd_mode = MIRACAST_MODE_REVERSE(op_wfd_mode); +} + +void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) +{ + u8 cmd = parm->cmd; + struct sta_info *sta = parm->sta; + + if (cmd == ST_CMD_CHK) { + if (sta) + session_tracker_chk_for_sta(adapter, sta); + else + session_tracker_chk_for_adapter(adapter); + + goto exit; + + } else if (cmd == ST_CMD_ADD || cmd == ST_CMD_DEL) { + struct st_ctl_t *st_ctl; + u32 local_naddr = parm->local_naddr; + u16 local_port = parm->local_port; + u32 remote_naddr = parm->remote_naddr; + u16 remote_port = parm->remote_port; + struct session_tracker *st = NULL; + _irqL irqL; + _list *plist, *phead; + u8 free_st = 0; + u8 alloc_st = 0; + + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" cmd:%u, sta:%p, local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT"\n" + , FUNC_ADPT_ARG(adapter), cmd, sta + , IP_ARG(&local_naddr), PORT_ARG(&local_port) + , IP_ARG(&remote_naddr), PORT_ARG(&remote_port) + ); + + if (!(sta->state & _FW_LINKED)) + goto exit; + + st_ctl = &sta->st_ctl; + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + phead = &st_ctl->tracker_q.queue; + plist = get_next(phead); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + + if (st->local_naddr == local_naddr + && st->local_port == local_port + && st->remote_naddr == remote_naddr + && st->remote_port == remote_port) + break; + + plist = get_next(plist); + } + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + st = NULL; + + switch (cmd) { + case ST_CMD_DEL: + if (st) { + rtw_list_delete(plist); + free_st = 1; + } + goto unlock; + case ST_CMD_ADD: + if (!st) + alloc_st = 1; + } + +unlock: + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + if (free_st) { + rtw_mfree((u8 *)st, sizeof(struct session_tracker)); + goto exit; + } + + if (alloc_st) { + st = (struct session_tracker *)rtw_zmalloc(sizeof(struct session_tracker)); + if (!st) + goto exit; + + st->local_naddr = local_naddr; + st->local_port = local_port; + st->remote_naddr = remote_naddr; + st->remote_port = remote_port; + st->set_time = rtw_get_current_time(); + st->status = ST_STATUS_CHECK; + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + rtw_list_insert_tail(&st->list, phead); + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + } + } + +exit: + return; +} + +u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) +{ + int ret = H2C_SUCCESS; + struct drvextra_cmd_parm *pdrvextra_cmd; + + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + pdrvextra_cmd = (struct drvextra_cmd_parm *)pbuf; + + switch (pdrvextra_cmd->ec_id) { + case STA_MSTATUS_RPT_WK_CID: + rtw_sta_media_status_rpt_cmd_hdl(padapter, (struct sta_media_status_rpt_cmd_parm *)pdrvextra_cmd->pbuf); + break; + + case DYNAMIC_CHK_WK_CID:/*only primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */ + rtw_dynamic_chk_wk_hdl(padapter); + break; + case POWER_SAVING_CTRL_WK_CID: + power_saving_wk_hdl(padapter); + break; + case LPS_CTRL_WK_CID: + lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type); + break; + case DM_IN_LPS_WK_CID: + rtw_dm_in_lps_hdl(padapter); + break; + case LPS_CHANGE_DTIM_CID: + rtw_lps_change_dtim_hdl(padapter, (u8)pdrvextra_cmd->type); + break; + case P2P_PS_WK_CID: + p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type); + break; + case P2P_PROTO_WK_CID: + /* + * Commented by Albert 2011/07/01 + * I used the type_size as the type command + */ + ret = p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); + break; + case CHECK_HIQ_WK_CID: + rtw_chk_hi_queue_hdl(padapter); + break; + /* add for CONFIG_IEEE80211W, none 11w can use it */ + case RESET_SECURITYPRIV: + reset_securitypriv_hdl(padapter); + break; + case FREE_ASSOC_RESOURCES: + free_assoc_resources_hdl(padapter); + break; + case C2H_WK_CID: + switch (pdrvextra_cmd->type) { + case C2H_TYPE_PKT: + rtw_hal_c2h_pkt_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); + break; + default: + RTW_ERR("unknown C2H type:%d\n", pdrvextra_cmd->type); + rtw_warn_on(1); + break; + } + break; + case DM_RA_MSK_WK_CID: + rtw_dm_ra_mask_hdl(padapter, (struct sta_info *)pdrvextra_cmd->pbuf); + break; + case BTINFO_WK_CID: + rtw_btinfo_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); + break; + case SESSION_TRACKER_WK_CID: + session_tracker_cmd_hdl(padapter, (struct st_cmd_parm *)pdrvextra_cmd->pbuf); + break; + case EN_HW_UPDATE_TSF_WK_CID: + rtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL); + break; + case TEST_H2C_CID: + rtw_hal_fill_h2c_cmd(padapter, pdrvextra_cmd->pbuf[0], pdrvextra_cmd->size - 1, &pdrvextra_cmd->pbuf[1]); + break; + case MP_CMD_WK_CID: + ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type); + break; + default: + break; + } + + if (pdrvextra_cmd->pbuf && pdrvextra_cmd->size > 0) + rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size); + + return ret; +} + +void rtw_survey_cmd_callback(_adapter *padapter , struct cmd_obj *pcmd) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (pcmd->res == H2C_DROPPED) { + /* TODO: cancel timer and do timeout handler directly... */ + /* need to make timeout handlerOS independent */ + mlme_set_scan_to_timer(pmlmepriv, 1); + } else if (pcmd->res != H2C_SUCCESS) { + mlme_set_scan_to_timer(pmlmepriv, 1); + } + + /* free cmd */ + rtw_free_cmd_obj(pcmd); + +} +void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (pcmd->res != H2C_SUCCESS) { + _enter_critical_bh(&pmlmepriv->lock, &irqL); + set_fwstate(pmlmepriv, _FW_LINKED); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + goto exit; + } + else /* clear bridge database */ + nat25_db_cleanup(padapter); + + /* free cmd */ + rtw_free_cmd_obj(pcmd); + +exit: + return; +} + +void rtw_getmacreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) +{ + + rtw_free_cmd_obj(pcmd); + +} + +void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (pcmd->res == H2C_DROPPED) { + /* TODO: cancel timer and do timeout handler directly... */ + /* need to make timeout handlerOS independent */ + _set_timer(&pmlmepriv->assoc_timer, 1); + } else if (pcmd->res != H2C_SUCCESS) + _set_timer(&pmlmepriv->assoc_timer, 1); + + rtw_free_cmd_obj(pcmd); + +} + +void rtw_create_ibss_post_hdl(_adapter *padapter, int status) +{ + _irqL irqL; + struct sta_info *psta = NULL; + struct wlan_network *pwlan = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; + struct wlan_network *mlme_cur_network = &(pmlmepriv->cur_network); + + if (status != H2C_SUCCESS) + _set_timer(&pmlmepriv->assoc_timer, 1); + + _cancel_timer_ex(&pmlmepriv->assoc_timer); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + { + _irqL irqL; + + pwlan = _rtw_alloc_network(pmlmepriv); + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + if (pwlan == NULL) { + pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue); + if (pwlan == NULL) { + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto createbss_cmd_fail; + } + pwlan->last_scanned = rtw_get_current_time(); + } else + rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue); + + pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network); + _rtw_memcpy(&(pwlan->network), pdev_network, pdev_network->Length); + /* pwlan->fixed = _TRUE; */ + + /* copy pdev_network information to pmlmepriv->cur_network */ + _rtw_memcpy(&mlme_cur_network->network, pdev_network, (get_WLAN_BSSID_EX_sz(pdev_network))); + + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + /* we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback) */ + } + +createbss_cmd_fail: + _exit_critical_bh(&pmlmepriv->lock, &irqL); + return; +} + +void rtw_setstaKey_cmdrsp_callback(_adapter *padapter , struct cmd_obj *pcmd) +{ + + struct sta_priv *pstapriv = &padapter->stapriv; + struct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp); + struct sta_info *psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr); + + if (psta == NULL) { + goto exit; + } + + /* psta->aid = psta->mac_id = psetstakey_rsp->keyid; */ /* CAM_ID(CAM_ENTRY) */ + +exit: + + rtw_free_cmd_obj(pcmd); + +} +void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) +{ + _irqL irqL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct set_assocsta_parm *passocsta_parm = (struct set_assocsta_parm *)(pcmd->parmbuf); + struct set_assocsta_rsp *passocsta_rsp = (struct set_assocsta_rsp *)(pcmd->rsp); + struct sta_info *psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr); + + if (psta == NULL) { + goto exit; + } + + psta->aid = psta->mac_id = passocsta_rsp->cam_id; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)) + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + set_fwstate(pmlmepriv, _FW_LINKED); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +exit: + rtw_free_cmd_obj(pcmd); + +} diff --git a/drivers/staging/rtl8821ce/core/rtw_debug.c b/drivers/staging/rtl8821ce/core/rtw_debug.c new file mode 100644 index 000000000000..010920377bee --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_debug.c @@ -0,0 +1,264 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_DEBUG_C_ + +#include <drv_types.h> +#include <hal_data.h> +#include <rtw_version.h> + +void dump_drv_version(void *sel) +{ + RTW_PRINT_SEL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION); +} + +void mac_reg_dump(void *sel, _adapter *adapter) +{ + int i, j = 1; + + RTW_PRINT_SEL(sel, "======= MAC REG =======\n"); + + for (i = 0x0; i < 0x800; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (i = 0x1000; i < 0x1800; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } +} + +void bb_reg_dump(void *sel, _adapter *adapter) +{ + int i, j = 1; + + RTW_PRINT_SEL(sel, "======= BB REG =======\n"); + for (i = 0x800; i < 0x1000; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + + for (i = 0x1800; i < 0x2000; i += 4) { + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } +} + +void bb_reg_dump_ex(void *sel, _adapter *adapter) +{ + int i, j = 1; + + RTW_PRINT_SEL(sel, "======= BB REG =======\n"); + for (i = 0x800; i < 0x1000; i += 4) { + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + _RTW_PRINT_SEL(sel, "\n"); + } + + for (i = 0x1800; i < 0x2000; i += 4) { + RTW_PRINT_SEL(sel, "0x%04x", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", rtw_read32(adapter, i)); + _RTW_PRINT_SEL(sel, "\n"); + } +} + +void rf_reg_dump(void *sel, _adapter *adapter) +{ + int i, j = 1, path; + u32 value; + u8 rf_type = 0; + u8 path_nums = 0; + + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if ((RF_1T2R == rf_type) || (RF_1T1R == rf_type)) + path_nums = 1; + else + path_nums = 2; + + RTW_PRINT_SEL(sel, "======= RF REG =======\n"); + + for (path = 0; path < path_nums; path++) { + RTW_PRINT_SEL(sel, "RF_Path(%x)\n", path); + for (i = 0; i < 0x100; i++) { + value = rtw_hal_read_rfreg(adapter, path, i, 0xffffffff); + if (j % 4 == 1) + RTW_PRINT_SEL(sel, "0x%02x ", i); + _RTW_PRINT_SEL(sel, " 0x%08x ", value); + if ((j++) % 4 == 0) + _RTW_PRINT_SEL(sel, "\n"); + } + } +} + +void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt) +{ + struct recv_priv *precvpriv = &(adapter->recvpriv); + if (precvpriv->sink_udpport > 0) { + if (*((u16 *)((pkt->data) + 0x24)) == cpu_to_be16(precvpriv->sink_udpport)) { + precvpriv->pre_rtp_rxseq = precvpriv->cur_rtp_rxseq; + precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16 *)((pkt->data) + 0x2C))); + if (precvpriv->pre_rtp_rxseq + 1 != precvpriv->cur_rtp_rxseq) + RTW_INFO("%s : RTP Seq num from %d to %d\n", __FUNCTION__, precvpriv->pre_rtp_rxseq, precvpriv->cur_rtp_rxseq); + } + } +} + +void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta) +{ + struct recv_reorder_ctrl *reorder_ctl; + int i; + + for (i = 0; i < 16; i++) { + reorder_ctl = &sta->recvreorder_ctrl[i]; + if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID || reorder_ctl->indicate_seq != 0xFFFF) { + RTW_PRINT_SEL(sel, "tid=%d, enable=%d, ampdu_size=%u, indicate_seq=%u\n" + , i, reorder_ctl->enable, reorder_ctl->ampdu_size, reorder_ctl->indicate_seq + ); + } + } +} + +void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + int i; + _adapter *iface; + u8 u_ch, u_bw, u_offset; + + dump_mi_status(sel, dvobj); + + + RTW_PRINT_SEL(sel, "dev status:%s%s\n\n" + , dev_is_surprise_removed(dvobj) ? " SR" : "" + , dev_is_drv_stopped(dvobj) ? " DS" : "" + ); + +#define P2P_INFO_TITLE_FMT " %-3s %-4s" +#define P2P_INFO_TITLE_ARG , "lch", "p2ps" +#define P2P_INFO_VALUE_FMT " %3u %4u" +#define P2P_INFO_VALUE_ARG , iface->wdinfo.listen_channel, rtw_p2p_state(&iface->wdinfo) +#define P2P_INFO_DASH "---------" + + RTW_PRINT_SEL(sel, "%-2s %-15s %c %-3s %-3s %-3s %-17s %-4s %-7s" + P2P_INFO_TITLE_FMT + " %s\n" + , "id", "ifname", ' ', "bup", "nup", "ncd", "macaddr", "port", "ch" + P2P_INFO_TITLE_ARG + , "status"); + + RTW_PRINT_SEL(sel, "---------------------------------------------------------------" + P2P_INFO_DASH + "-------\n"); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + RTW_PRINT_SEL(sel, "%2d %-15s %c %3u %3u %3u "MAC_FMT" %4hhu %3u,%u,%u" + P2P_INFO_VALUE_FMT + " "MLME_STATE_FMT"\n" + , i, iface->registered ? ADPT_ARG(iface) : NULL + , iface->registered ? 'R' : ' ' + , iface->bup + , iface->netif_up + , iface->net_closed + , MAC_ARG(adapter_mac_addr(iface)) + , get_hw_port(iface) + , iface->mlmeextpriv.cur_channel + , iface->mlmeextpriv.cur_bwmode + , iface->mlmeextpriv.cur_ch_offset + P2P_INFO_VALUE_ARG + , MLME_STATE_ARG(iface) + ); + } + } + + RTW_PRINT_SEL(sel, "---------------------------------------------------------------" + P2P_INFO_DASH + "-------\n"); + + rtw_mi_get_ch_setting_union(dvobj_get_primary_adapter(dvobj), &u_ch, &u_bw, &u_offset); + RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n" + , "union:" + , u_ch, u_bw, u_offset + ); + + RTW_PRINT_SEL(sel, "%55s %3u,%u,%u\n" + , "oper:" + , dvobj->oper_channel + , dvobj->oper_bwmode + , dvobj->oper_ch_offset + ); + +} + +static u8 fwdl_test_chksum_fail = 0; +static u8 fwdl_test_wintint_rdy_fail = 0; + +static u8 del_rx_ampdu_test_no_tx_fail = 0; + +bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void) +{ + if (del_rx_ampdu_test_no_tx_fail) { + RTW_PRINT("del_rx_ampdu test case: trigger no_tx_fail\n"); + del_rx_ampdu_test_no_tx_fail--; + return _TRUE; + } + return _FALSE; +} + +static u32 g_wait_hiq_empty_ms = 0; + +u32 rtw_get_wait_hiq_empty_ms(void) +{ + return g_wait_hiq_empty_ms; +} + +static u32 sta_linking_test_start_time = 0; +static u32 sta_linking_test_wait_ms = 0; +static u8 sta_linking_test_force_fail = 0; + +void rtw_sta_linking_test_set_start(void) +{ + sta_linking_test_start_time = rtw_get_current_time(); +} + +bool rtw_sta_linking_test_wait_done(void) +{ + return rtw_get_passing_time_ms(sta_linking_test_start_time) >= sta_linking_test_wait_ms; +} + +bool rtw_sta_linking_test_force_fail(void) +{ + return sta_linking_test_force_fail; +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_ieee80211.c b/drivers/staging/rtl8821ce/core/rtw_ieee80211.c new file mode 100644 index 000000000000..1ff6a2b353a3 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_ieee80211.c @@ -0,0 +1,2271 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _IEEE80211_C + +#include <drv_types.h> + +u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 }; +u16 RTW_WPA_VERSION = 1; +u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 }; +u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 }; +u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 }; +u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 }; +u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 }; +u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 }; +u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 }; +u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 }; +u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 }; + +u16 RSN_VERSION_BSD = 1; +u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x0f, 0xac, 1 }; +u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x0f, 0xac, 2 }; +u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 }; +u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 }; +u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 }; +u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 }; +u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 }; +u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 }; +/* ----------------------------------------------------------- + * for adhoc-master to generate ie and provide supported-rate to fw + * ----------------------------------------------------------- */ + +static u8 WIFI_CCKRATES[] = { + (IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK), + (IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK), + (IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK), + (IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK) +}; + +static u8 WIFI_OFDMRATES[] = { + (IEEE80211_OFDM_RATE_6MB), + (IEEE80211_OFDM_RATE_9MB), + (IEEE80211_OFDM_RATE_12MB), + (IEEE80211_OFDM_RATE_18MB), + (IEEE80211_OFDM_RATE_24MB), + IEEE80211_OFDM_RATE_36MB, + IEEE80211_OFDM_RATE_48MB, + IEEE80211_OFDM_RATE_54MB +}; + +u8 mgn_rates_cck[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; +u8 mgn_rates_ofdm[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; +u8 mgn_rates_mcs0_7[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}; +u8 mgn_rates_mcs8_15[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}; +u8 mgn_rates_mcs16_23[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}; +u8 mgn_rates_mcs24_31[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31}; +u8 mgn_rates_vht1ss[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4 + , MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9 + }; +u8 mgn_rates_vht2ss[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4 + , MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9 + }; +u8 mgn_rates_vht3ss[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4 + , MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9 + }; +u8 mgn_rates_vht4ss[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4 + , MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9 + }; + +static const char *const _rate_section_str[] = { + "CCK", + "OFDM", + "HT_1SS", + "HT_2SS", + "HT_3SS", + "HT_4SS", + "VHT_1SS", + "VHT_2SS", + "VHT_3SS", + "VHT_4SS", + "RATE_SECTION_UNKNOWN", +}; + +const char *rate_section_str(u8 section) +{ + section = (section >= RATE_SECTION_NUM) ? RATE_SECTION_NUM : section; + return _rate_section_str[section]; +} + +struct rate_section_ent rates_by_sections[RATE_SECTION_NUM] = { + {RF_1TX, 4, mgn_rates_cck}, + {RF_1TX, 8, mgn_rates_ofdm}, + {RF_1TX, 8, mgn_rates_mcs0_7}, + {RF_2TX, 8, mgn_rates_mcs8_15}, + {RF_3TX, 8, mgn_rates_mcs16_23}, + {RF_4TX, 8, mgn_rates_mcs24_31}, + {RF_1TX, 10, mgn_rates_vht1ss}, + {RF_2TX, 10, mgn_rates_vht2ss}, + {RF_3TX, 10, mgn_rates_vht3ss}, + {RF_4TX, 10, mgn_rates_vht4ss}, +}; + +int rtw_get_bit_value_from_ieee_value(u8 val) +{ + unsigned char dot11_rate_table[] = {2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 0}; /* last element must be zero!! */ + + int i = 0; + while (dot11_rate_table[i] != 0) { + if (dot11_rate_table[i] == val) + return BIT(i); + i++; + } + return 0; +} + +uint rtw_is_cckrates_included(u8 *rate) +{ + u32 i = 0; + + while (rate[i] != 0) { + if ((((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || + (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22)) + return _TRUE; + i++; + } + + return _FALSE; +} + +uint rtw_is_cckratesonly_included(u8 *rate) +{ + u32 i = 0; + + while (rate[i] != 0) { + if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && + (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22)) + return _FALSE; + + i++; + } + + return _TRUE; + +} + +int rtw_check_network_type(unsigned char *rate, int ratelen, int channel) +{ + if (channel > 14) { + if ((rtw_is_cckrates_included(rate)) == _TRUE) + return WIRELESS_INVALID; + else + return WIRELESS_11A; + } else { /* could be pure B, pure G, or B/G */ + if ((rtw_is_cckratesonly_included(rate)) == _TRUE) + return WIRELESS_11B; + else if ((rtw_is_cckrates_included(rate)) == _TRUE) + return WIRELESS_11BG; + else + return WIRELESS_11G; + } + +} + +u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, + unsigned int *frlen) +{ + _rtw_memcpy((void *)pbuf, (void *)source, len); + *frlen = *frlen + len; + return pbuf + len; +} + +/* rtw_set_ie will update frame length */ +u8 *rtw_set_ie +( + u8 *pbuf, + sint index, + uint len, + u8 *source, + uint *frlen /* frame length */ +) +{ + *pbuf = (u8)index; + + *(pbuf + 1) = (u8)len; + + if (len > 0) + _rtw_memcpy((void *)(pbuf + 2), (void *)source, len); + + *frlen = *frlen + (len + 2); + + return pbuf + len + 2; +} + +inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, + u8 new_ch, u8 ch_switch_cnt) +{ + u8 ie_data[3]; + + ie_data[0] = ch_switch_mode; + ie_data[1] = new_ch; + ie_data[2] = ch_switch_cnt; + return rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH, 3, ie_data, buf_len); +} + +inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset) +{ + if (ch_offset == SCN) + return HAL_PRIME_CHNL_OFFSET_DONT_CARE; + else if (ch_offset == SCA) + return HAL_PRIME_CHNL_OFFSET_UPPER; + else if (ch_offset == SCB) + return HAL_PRIME_CHNL_OFFSET_LOWER; + + return HAL_PRIME_CHNL_OFFSET_DONT_CARE; +} + +inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset) +{ + if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) + return SCN; + else if (ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + return SCB; + else if (ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + return SCA; + + return SCN; +} + +inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset) +{ + return rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET, 1, &secondary_ch_offset, buf_len); +} + +/*---------------------------------------------------------------------------- +index: the information element id index, limit is the limit for search +-----------------------------------------------------------------------------*/ +u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) +{ + sint tmp, i; + u8 *p; + if (limit < 1) { + return NULL; + } + + p = pbuf; + i = 0; + *len = 0; + while (1) { + if (*p == index) { + *len = *(p + 1); + return p; + } else { + tmp = *(p + 1); + p += (tmp + 2); + i += (tmp + 2); + } + if (i >= limit) + break; + } + return NULL; +} + +void rtw_set_supported_rate(u8 *SupportedRates, uint mode) +{ + + _rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); + + switch (mode) { + case WIRELESS_11B: + _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN); + break; + + case WIRELESS_11G: + case WIRELESS_11A: + case WIRELESS_11_5N: + case WIRELESS_11A_5N: /* Todo: no basic rate for ofdm ? */ + case WIRELESS_11_5AC: + _rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN); + break; + + case WIRELESS_11BG: + case WIRELESS_11G_24N: + case WIRELESS_11_24N: + case WIRELESS_11BG_24N: + _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN); + _rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN); + break; + + } +} + +uint rtw_get_rateset_len(u8 *rateset) +{ + uint i = 0; + while (1) { + if ((rateset[i]) == 0) + break; + + if (i > 12) + break; + + i++; + } + return i; +} + +int rtw_generate_ie(struct registry_priv *pregistrypriv) +{ + u8 wireless_mode; + int sz = 0, rateLen; + WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; + u8 *ie = pdev_network->IEs; + + /* timestamp will be inserted by hardware */ + sz += 8; + ie += sz; + + /* beacon interval : 2bytes */ + *(u16 *)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod); /* BCN_INTERVAL; */ + sz += 2; + ie += 2; + + /* capability info */ + *(u16 *)ie = 0; + + *(u16 *)ie |= cpu_to_le16(cap_IBSS); + + if (pregistrypriv->preamble == PREAMBLE_SHORT) + *(u16 *)ie |= cpu_to_le16(cap_ShortPremble); + + if (pdev_network->Privacy) + *(u16 *)ie |= cpu_to_le16(cap_Privacy); + + sz += 2; + ie += 2; + + /* SSID */ + ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz); + + /* supported rates */ + if (pregistrypriv->wireless_mode == WIRELESS_11ABGN) { + if (pdev_network->Configuration.DSConfig > 14) + wireless_mode = WIRELESS_11A_5N; + else + wireless_mode = WIRELESS_11BG_24N; + } else if (pregistrypriv->wireless_mode == WIRELESS_MODE_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */ + if (pdev_network->Configuration.DSConfig > 14) + wireless_mode = WIRELESS_11_5AC; + else + wireless_mode = WIRELESS_11BG_24N; + } else + wireless_mode = pregistrypriv->wireless_mode; + + rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ; + + rateLen = rtw_get_rateset_len(pdev_network->SupportedRates); + + if (rateLen > 8) { + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz); + /* ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); */ + } else + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz); + + /* DS parameter set */ + ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz); + + /* IBSS Parameter Set */ + + ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz); + + if (rateLen > 8) + ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); + + /* HT Cap. */ + if (((pregistrypriv->wireless_mode & WIRELESS_11_5N) || (pregistrypriv->wireless_mode & WIRELESS_11_24N)) + && (pregistrypriv->ht_enable == _TRUE)) { + /* todo: */ + } + + /* pdev_network->IELength = sz; */ /* update IELength */ + + /* return _SUCCESS; */ + + return sz; + +} + +unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit) +{ + int len; + u16 val16; + unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01}; + u8 *pbuf = pie; + int limit_new = limit; + + while (1) { + pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new); + + if (pbuf) { + + /* check if oui matches... */ + if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof(wpa_oui_type)) == _FALSE) + + goto check_next_ie; + + /* check version... */ + _rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16)); + + val16 = le16_to_cpu(val16); + if (val16 != 0x0001) + goto check_next_ie; + + *wpa_ie_len = *(pbuf + 1); + + return pbuf; + + } else { + + *wpa_ie_len = 0; + return NULL; + } + +check_next_ie: + + limit_new = limit - (pbuf - pie) - 2 - len; + + if (limit_new <= 0) + break; + + pbuf += (2 + len); + + } + + *wpa_ie_len = 0; + + return NULL; + +} + +unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit) +{ + + return rtw_get_ie(pie, _WPA2_IE_ID_, rsn_ie_len, limit); + +} + +int rtw_get_wpa_cipher_suite(u8 *s) +{ + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_NONE; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP40; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_TKIP; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_CCMP; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP104; + + return 0; +} + +int rtw_get_wpa2_cipher_suite(u8 *s) +{ + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_NONE; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP40; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_TKIP; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_CCMP; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP104; + + return 0; +} + +int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) +{ + int i, ret = _SUCCESS; + int left, count; + u8 *pos; + u8 SUITE_1X[4] = {0x00, 0x50, 0xf2, 1}; + + if (wpa_ie_len <= 0) { + /* No WPA IE - fail silently */ + return _FAIL; + } + + if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie + 1) != (u8)(wpa_ie_len - 2)) || + (_rtw_memcmp(wpa_ie + 2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE)) + return _FAIL; + + pos = wpa_ie; + + pos += 8; + left = wpa_ie_len - 8; + + /* group_cipher */ + if (left >= WPA_SELECTOR_LEN) { + + *group_cipher = rtw_get_wpa_cipher_suite(pos); + + pos += WPA_SELECTOR_LEN; + left -= WPA_SELECTOR_LEN; + + } else if (left > 0) { + + return _FAIL; + } + + /* pairwise_cipher */ + if (left >= 2) { + /* count = le16_to_cpu(*(u16*)pos); */ + count = RTW_GET_LE16(pos); + pos += 2; + left -= 2; + + if (count == 0 || left < count * WPA_SELECTOR_LEN) { + return _FAIL; + } + + for (i = 0; i < count; i++) { + *pairwise_cipher |= rtw_get_wpa_cipher_suite(pos); + + pos += WPA_SELECTOR_LEN; + left -= WPA_SELECTOR_LEN; + } + + } else if (left == 1) { + return _FAIL; + } + + if (is_8021x) { + if (left >= 6) { + pos += 2; + if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { + *is_8021x = 1; + } + } + } + + return ret; + +} + +int rtw_parse_wpa2_ie(u8 *rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) +{ + int i, ret = _SUCCESS; + int left, count; + u8 *pos; + u8 SUITE_1X[4] = {0x00, 0x0f, 0xac, 0x01}; + + if (rsn_ie_len <= 0) { + /* No RSN IE - fail silently */ + return _FAIL; + } + + if ((*rsn_ie != _WPA2_IE_ID_) || (*(rsn_ie + 1) != (u8)(rsn_ie_len - 2))) + return _FAIL; + + pos = rsn_ie; + pos += 4; + left = rsn_ie_len - 4; + + /* group_cipher */ + if (left >= RSN_SELECTOR_LEN) { + + *group_cipher = rtw_get_wpa2_cipher_suite(pos); + + pos += RSN_SELECTOR_LEN; + left -= RSN_SELECTOR_LEN; + + } else if (left > 0) { + return _FAIL; + } + + /* pairwise_cipher */ + if (left >= 2) { + /* count = le16_to_cpu(*(u16*)pos); */ + count = RTW_GET_LE16(pos); + pos += 2; + left -= 2; + + if (count == 0 || left < count * RSN_SELECTOR_LEN) { + return _FAIL; + } + + for (i = 0; i < count; i++) { + *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos); + + pos += RSN_SELECTOR_LEN; + left -= RSN_SELECTOR_LEN; + } + + } else if (left == 1) { + + return _FAIL; + } + + if (is_8021x) { + if (left >= 6) { + pos += 2; + if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { + *is_8021x = 1; + } + } + } + + return ret; + +} + +int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len) +{ + u8 authmode, sec_idx, i; + u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01}; + uint cnt; + + /* Search required WPA or WPA2 IE and copy to sec_ie[ ] */ + + cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_); + + sec_idx = 0; + + while (cnt < in_len) { + authmode = in_ie[cnt]; + + if ((authmode == _WPA_IE_ID_) && (_rtw_memcmp(&in_ie[cnt + 2], &wpa_oui[0], 4) == _TRUE)) { + + if (wpa_ie) + _rtw_memcpy(wpa_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + *wpa_len = in_ie[cnt + 1] + 2; + cnt += in_ie[cnt + 1] + 2; /* get next */ + } else { + if (authmode == _WPA2_IE_ID_) { + + if (rsn_ie) + _rtw_memcpy(rsn_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + *rsn_len = in_ie[cnt + 1] + 2; + cnt += in_ie[cnt + 1] + 2; /* get next */ + } else { + cnt += in_ie[cnt + 1] + 2; /* get next */ + } + } + + } + + return *rsn_len + *wpa_len; + +} + +u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen) +{ + u8 match = _FALSE; + u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; + + if (ie_ptr == NULL) + return match; + + eid = ie_ptr[0]; + + if ((eid == _WPA_IE_ID_) && (_rtw_memcmp(&ie_ptr[2], wps_oui, 4) == _TRUE)) { + /* RTW_INFO("==> found WPS_IE.....\n"); */ + *wps_ielen = ie_ptr[1] + 2; + match = _TRUE; + } + return match; +} + +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type) +{ + u8 *wps = NULL; + + RTW_INFO("[%s] frame_type = %d\n", __FUNCTION__, frame_type); + switch (frame_type) { + case 1: + case 3: { + /* Beacon or Probe Response */ + wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen); + break; + } + case 2: { + /* Probe Request */ + wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen); + break; + } + } + return wps; +} + +/** + * rtw_get_wps_ie - Search WPS IE from a series of IEs + * @in_ie: Address of IEs to search + * @in_len: Length limit from in_ie + * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie + * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE + * + * Returns: The address of the WPS IE found, or NULL + */ +u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) +{ + uint cnt; + u8 *wpsie_ptr = NULL; + u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04}; + + if (wps_ielen) + *wps_ielen = 0; + + if (!in_ie) { + rtw_warn_on(1); + return wpsie_ptr; + } + + if (in_len <= 0) + return wpsie_ptr; + + cnt = 0; + + while (cnt + 1 + 4 < in_len) { + eid = in_ie[cnt]; + + if (cnt + 1 + 4 >= MAX_IE_SZ) { + rtw_warn_on(1); + return NULL; + } + + if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wps_oui, 4) == _TRUE) { + wpsie_ptr = in_ie + cnt; + + if (wps_ie) + _rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + if (wps_ielen) + *wps_ielen = in_ie[cnt + 1] + 2; + + break; + } else + cnt += in_ie[cnt + 1] + 2; + + } + + return wpsie_ptr; +} + +/** + * rtw_get_wps_attr - Search a specific WPS attribute from a given WPS IE + * @wps_ie: Address of WPS IE to search + * @wps_ielen: Length limit from wps_ie + * @target_attr_id: The attribute ID of WPS attribute to search + * @buf_attr: If not NULL and the WPS attribute is found, WPS attribute will be copied to the buf starting from buf_attr + * @len_attr: If not NULL and the WPS attribute is found, will set to the length of the entire WPS attribute + * + * Returns: the address of the specific WPS attribute found, or NULL + */ +u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr) +{ + u8 *attr_ptr = NULL; + u8 *target_attr_ptr = NULL; + u8 wps_oui[4] = {0x00, 0x50, 0xF2, 0x04}; + + if (len_attr) + *len_attr = 0; + + if ((wps_ie[0] != _VENDOR_SPECIFIC_IE_) || + (_rtw_memcmp(wps_ie + 2, wps_oui , 4) != _TRUE)) + return attr_ptr; + + /* 6 = 1(Element ID) + 1(Length) + 4(WPS OUI) */ + attr_ptr = wps_ie + 6; /* goto first attr */ + + while (attr_ptr - wps_ie < wps_ielen) { + /* 4 = 2(Attribute ID) + 2(Length) */ + u16 attr_id = RTW_GET_BE16(attr_ptr); + u16 attr_data_len = RTW_GET_BE16(attr_ptr + 2); + u16 attr_len = attr_data_len + 4; + + /* RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len); */ + if (attr_id == target_attr_id) { + target_attr_ptr = attr_ptr; + + if (buf_attr) + _rtw_memcpy(buf_attr, attr_ptr, attr_len); + + if (len_attr) + *len_attr = attr_len; + + break; + } else { + attr_ptr += attr_len; /* goto next */ + } + + } + + return target_attr_ptr; +} + +/** + * rtw_get_wps_attr_content - Search a specific WPS attribute content from a given WPS IE + * @wps_ie: Address of WPS IE to search + * @wps_ielen: Length limit from wps_ie + * @target_attr_id: The attribute ID of WPS attribute to search + * @buf_content: If not NULL and the WPS attribute is found, WPS attribute content will be copied to the buf starting from buf_content + * @len_content: If not NULL and the WPS attribute is found, will set to the length of the WPS attribute content + * + * Returns: the address of the specific WPS attribute content found, or NULL + */ +u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content) +{ + u8 *attr_ptr; + u32 attr_len; + + if (len_content) + *len_content = 0; + + attr_ptr = rtw_get_wps_attr(wps_ie, wps_ielen, target_attr_id, NULL, &attr_len); + + if (attr_ptr && attr_len) { + if (buf_content) + _rtw_memcpy(buf_content, attr_ptr + 4, attr_len - 4); + + if (len_content) + *len_content = attr_len - 4; + + return attr_ptr + 4; + } + + return NULL; +} + +static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen, + struct rtw_ieee802_11_elems *elems, + int show_errors) +{ + unsigned int oui; + + /* first 3 bytes in vendor specific information element are the IEEE + * OUI of the vendor. The following byte is used a vendor specific + * sub-type. */ + if (elen < 4) { + if (show_errors) { + RTW_INFO("short vendor specific " + "information element ignored (len=%lu)\n", + (unsigned long) elen); + } + return -1; + } + + oui = RTW_GET_BE24(pos); + switch (oui) { + case OUI_MICROSOFT: + /* Microsoft/Wi-Fi information elements are further typed and + * subtyped */ + switch (pos[3]) { + case 1: + /* Microsoft OUI (00:50:F2) with OUI Type 1: + * real WPA information element */ + elems->wpa_ie = pos; + elems->wpa_ie_len = elen; + break; + case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */ + if (elen < 5) { + RTW_DBG("short WME " + "information element ignored " + "(len=%lu)\n", + (unsigned long) elen); + return -1; + } + switch (pos[4]) { + case WME_OUI_SUBTYPE_INFORMATION_ELEMENT: + case WME_OUI_SUBTYPE_PARAMETER_ELEMENT: + elems->wme = pos; + elems->wme_len = elen; + break; + case WME_OUI_SUBTYPE_TSPEC_ELEMENT: + elems->wme_tspec = pos; + elems->wme_tspec_len = elen; + break; + default: + RTW_DBG("unknown WME " + "information element ignored " + "(subtype=%d len=%lu)\n", + pos[4], (unsigned long) elen); + return -1; + } + break; + case 4: + /* Wi-Fi Protected Setup (WPS) IE */ + elems->wps_ie = pos; + elems->wps_ie_len = elen; + break; + default: + RTW_DBG("Unknown Microsoft " + "information element ignored " + "(type=%d len=%lu)\n", + pos[3], (unsigned long) elen); + return -1; + } + break; + + case OUI_BROADCOM: + switch (pos[3]) { + case VENDOR_HT_CAPAB_OUI_TYPE: + elems->vendor_ht_cap = pos; + elems->vendor_ht_cap_len = elen; + break; + default: + RTW_DBG("Unknown Broadcom " + "information element ignored " + "(type=%d len=%lu)\n", + pos[3], (unsigned long) elen); + return -1; + } + break; + + default: + RTW_DBG("unknown vendor specific information " + "element ignored (vendor OUI %02x:%02x:%02x " + "len=%lu)\n", + pos[0], pos[1], pos[2], (unsigned long) elen); + return -1; + } + + return 0; + +} + +/** + * ieee802_11_parse_elems - Parse information elements in management frames + * @start: Pointer to the start of IEs + * @len: Length of IE buffer in octets + * @elems: Data structure for parsed elements + * @show_errors: Whether to show parsing errors in debug log + * Returns: Parsing result + */ +ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, + struct rtw_ieee802_11_elems *elems, + int show_errors) +{ + uint left = len; + u8 *pos = start; + int unknown = 0; + + _rtw_memset(elems, 0, sizeof(*elems)); + + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) { + if (show_errors) { + RTW_INFO("IEEE 802.11 element " + "parse failed (id=%d elen=%d " + "left=%lu)\n", + id, elen, (unsigned long) left); + } + return ParseFailed; + } + + switch (id) { + case WLAN_EID_SSID: + elems->ssid = pos; + elems->ssid_len = elen; + break; + case WLAN_EID_SUPP_RATES: + elems->supp_rates = pos; + elems->supp_rates_len = elen; + break; + case WLAN_EID_FH_PARAMS: + elems->fh_params = pos; + elems->fh_params_len = elen; + break; + case WLAN_EID_DS_PARAMS: + elems->ds_params = pos; + elems->ds_params_len = elen; + break; + case WLAN_EID_CF_PARAMS: + elems->cf_params = pos; + elems->cf_params_len = elen; + break; + case WLAN_EID_TIM: + elems->tim = pos; + elems->tim_len = elen; + break; + case WLAN_EID_IBSS_PARAMS: + elems->ibss_params = pos; + elems->ibss_params_len = elen; + break; + case WLAN_EID_CHALLENGE: + elems->challenge = pos; + elems->challenge_len = elen; + break; + case WLAN_EID_ERP_INFO: + elems->erp_info = pos; + elems->erp_info_len = elen; + break; + case WLAN_EID_EXT_SUPP_RATES: + elems->ext_supp_rates = pos; + elems->ext_supp_rates_len = elen; + break; + case WLAN_EID_VENDOR_SPECIFIC: + if (rtw_ieee802_11_parse_vendor_specific(pos, elen, + elems, + show_errors)) + unknown++; + break; + case WLAN_EID_RSN: + elems->rsn_ie = pos; + elems->rsn_ie_len = elen; + break; + case WLAN_EID_PWR_CAPABILITY: + elems->power_cap = pos; + elems->power_cap_len = elen; + break; + case WLAN_EID_SUPPORTED_CHANNELS: + elems->supp_channels = pos; + elems->supp_channels_len = elen; + break; + case WLAN_EID_MOBILITY_DOMAIN: + elems->mdie = pos; + elems->mdie_len = elen; + break; + case WLAN_EID_FAST_BSS_TRANSITION: + elems->ftie = pos; + elems->ftie_len = elen; + break; + case WLAN_EID_TIMEOUT_INTERVAL: + elems->timeout_int = pos; + elems->timeout_int_len = elen; + break; + case WLAN_EID_HT_CAP: + elems->ht_capabilities = pos; + elems->ht_capabilities_len = elen; + break; + case WLAN_EID_HT_OPERATION: + elems->ht_operation = pos; + elems->ht_operation_len = elen; + break; + case WLAN_EID_VHT_CAPABILITY: + elems->vht_capabilities = pos; + elems->vht_capabilities_len = elen; + break; + case WLAN_EID_VHT_OPERATION: + elems->vht_operation = pos; + elems->vht_operation_len = elen; + break; + case WLAN_EID_VHT_OP_MODE_NOTIFY: + elems->vht_op_mode_notify = pos; + elems->vht_op_mode_notify_len = elen; + break; + default: + unknown++; + if (!show_errors) + break; + RTW_DBG("IEEE 802.11 element parse " + "ignored unknown element (id=%d elen=%d)\n", + id, elen); + break; + } + + left -= elen; + pos += elen; + } + + if (left) + return ParseFailed; + + return unknown ? ParseUnknown : ParseOK; + +} + +static u8 key_char2num(u8 ch); +static u8 key_char2num(u8 ch) +{ + if ((ch >= '0') && (ch <= '9')) + return ch - '0'; + else if ((ch >= 'a') && (ch <= 'f')) + return ch - 'a' + 10; + else if ((ch >= 'A') && (ch <= 'F')) + return ch - 'A' + 10; + else + return 0xff; +} + +u8 key_2char2num(u8 hch, u8 lch); +u8 key_2char2num(u8 hch, u8 lch) +{ + return (key_char2num(hch) << 4) | key_char2num(lch); +} + +void macstr2num(u8 *dst, u8 *src); +void macstr2num(u8 *dst, u8 *src) +{ + int jj, kk; + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + dst[jj] = key_2char2num(src[kk], src[kk + 1]); +} + +/* + * Description: + * rtw_check_invalid_mac_address: + * This is only used for checking mac address valid or not. + * + * Input: + * adapter: mac_address pointer. + * check_local_bit: check locally bit or not. + * + * Output: + * _TRUE: The mac address is invalid. + * _FALSE: The mac address is valid. + * + * Auther: Isaac.Li + */ +u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit) +{ + u8 null_mac_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; + u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 res = _FALSE; + + if (_rtw_memcmp(mac_addr, null_mac_addr, ETH_ALEN)) { + res = _TRUE; + goto func_exit; + } + + if (_rtw_memcmp(mac_addr, multi_mac_addr, ETH_ALEN)) { + res = _TRUE; + goto func_exit; + } + + if (mac_addr[0] & BIT0) { + res = _TRUE; + goto func_exit; + } + + if (check_local_bit == _TRUE) { + if (mac_addr[0] & BIT1) { + res = _TRUE; + goto func_exit; + } + } + +func_exit: + return res; +} + +extern char *rtw_initmac; +/** + * rtw_macaddr_cfg - Decide the mac address used + * @out: buf to store mac address decided + * @hw_mac_addr: mac address from efuse/epprom + */ +void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr) +{ +#define DEFAULT_RANDOM_MACADDR 1 + u8 mac[ETH_ALEN]; + + if (out == NULL) { + rtw_warn_on(1); + return; + } + + /* Users specify the mac address */ + if (rtw_initmac) { + int jj, kk; + + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk + 1]); + + goto err_chk; + } + + /* platform specified */ + + /* Use the mac address stored in the Efuse */ + if (hw_mac_addr) { + _rtw_memcpy(mac, hw_mac_addr, ETH_ALEN); + goto err_chk; + } + +err_chk: + if (rtw_check_invalid_mac_address(mac, _TRUE) == _TRUE) { + RTW_ERR("invalid mac addr:"MAC_FMT", assign random MAC\n", MAC_ARG(mac)); + *((u32 *)(&mac[2])) = rtw_random32(); + mac[0] = 0x00; + mac[1] = 0xe0; + mac[2] = 0x4c; + } + + _rtw_memcpy(out, mac, ETH_ALEN); + RTW_INFO("%s mac addr:"MAC_FMT"\n", __func__, MAC_ARG(out)); +} + +void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len) +{ + if (buf_len != 26) { + RTW_PRINT_SEL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, 26); + return; + } + + RTW_PRINT_SEL(sel, "HT Capabilities Info:%02x%02x\n", *(buf), *(buf + 1)); + RTW_PRINT_SEL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n" + , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf))); + RTW_PRINT_SEL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n" + , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf))); +} + +void dump_ht_cap_ie(void *sel, u8 *ie, u32 ie_len) +{ + u8 *pos = (u8 *)ie; + u16 id; + u16 len; + + u8 *ht_cap_ie; + sint ht_cap_ielen; + + ht_cap_ie = rtw_get_ie(ie, _HT_CAPABILITY_IE_, &ht_cap_ielen, ie_len); + if (!ie || ht_cap_ie != ie) + return; + + dump_ht_cap_ie_content(sel, ht_cap_ie + 2, ht_cap_ielen); +} + +void dump_ies(void *sel, u8 *buf, u32 buf_len) +{ + u8 *pos = (u8 *)buf; + u8 id, len; + + while (pos - buf + 1 < buf_len) { + id = *pos; + len = *(pos + 1); + + RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); + dump_ht_cap_ie(sel, pos, len + 2); + dump_wps_ie(sel, pos, len + 2); + dump_p2p_ie(sel, pos, len + 2); + dump_wfd_ie(sel, pos, len + 2); + + pos += (2 + len); + } +} + +void dump_wps_ie(void *sel, u8 *ie, u32 ie_len) +{ + u8 *pos = (u8 *)ie; + u16 id; + u16 len; + + u8 *wps_ie; + uint wps_ielen; + + wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen); + if (wps_ie != ie || wps_ielen == 0) + return; + + pos += 6; + while (pos - ie + 4 <= ie_len) { + id = RTW_GET_BE16(pos); + len = RTW_GET_BE16(pos + 2); + + RTW_PRINT_SEL(sel, "%s ID:0x%04x, LEN:%u%s\n", __func__, id, len + , ((pos - ie + 4 + len) <= ie_len) ? "" : "(exceed ie_len)"); + + pos += (4 + len); + } +} + +/** + * rtw_ies_get_chbw - get operation ch, bw, offset from IEs of BSS. + * @ies: pointer of the first tlv IE + * @ies_len: length of @ies + * @ch: pointer of ch, used as output + * @bw: pointer of bw, used as output + * @offset: pointer of offset, used as output + */ +void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset) +{ + u8 *p; + int ie_len; + + *ch = 0; + *bw = CHANNEL_WIDTH_20; + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + p = rtw_get_ie(ies, _DSSET_IE_, &ie_len, ies_len); + if (p && ie_len > 0) + *ch = *(p + 2); + + { + u8 *ht_cap_ie, *ht_op_ie; + int ht_cap_ielen, ht_op_ielen; + + ht_cap_ie = rtw_get_ie(ies, EID_HTCapability, &ht_cap_ielen, ies_len); + if (ht_cap_ie && ht_cap_ielen) { + if (GET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2)) + *bw = CHANNEL_WIDTH_40; + } + + ht_op_ie = rtw_get_ie(ies, EID_HTInfo, &ht_op_ielen, ies_len); + if (ht_op_ie && ht_op_ielen) { + if (*ch == 0) + *ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2); + else if (*ch != 0 && *ch != GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)) { + RTW_INFO("%s ch inconsistent, DSSS:%u, HT primary:%u\n" + , __func__, *ch, GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)); + } + + if (!GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) + *bw = CHANNEL_WIDTH_20; + + if (*bw == CHANNEL_WIDTH_40) { + switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) { + case SCA: + *offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case SCB: + *offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + } + } + } + } + { + u8 *vht_op_ie; + int vht_op_ielen; + + vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); + if (vht_op_ie && vht_op_ielen) { + /* enable VHT 80 before check enable HT40 or not */ + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1) { + /* for HT40, enable VHT80 */ + if (*bw == CHANNEL_WIDTH_40) + *bw = CHANNEL_WIDTH_80; + /* for HT20, enable VHT20 */ + else if (*bw == CHANNEL_WIDTH_20) { + /* modify VHT OP IE */ + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); + /* reset to 0 for VHT20 */ + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); + } + } else { + /* + VHT OP WIDTH = 0 under HT20/HT40 + if REGSTY_BW_5G(pregistrypriv) < CHANNEL_WIDTH_80 in rtw_build_vht_operation_ie + */ + } + } + } +} + +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset) +{ + rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs) + , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs) + , ch, bw, offset); + + if (*ch == 0) + *ch = bss->Configuration.DSConfig; + else if (*ch != bss->Configuration.DSConfig) { + RTW_INFO("inconsistent ch - ies:%u bss->Configuration.DSConfig:%u\n" + , *ch, bss->Configuration.DSConfig); + *ch = bss->Configuration.DSConfig; + rtw_warn_on(1); + } +} + +/** + * rtw_is_chbw_grouped - test if the two ch settings can be grouped together + * @ch_a: ch of set a + * @bw_a: bw of set a + * @offset_a: offset of set a + * @ch_b: ch of set b + * @bw_b: bw of set b + * @offset_b: offset of set b + */ +bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a + , u8 ch_b, u8 bw_b, u8 offset_b) +{ + bool is_grouped = _FALSE; + + if (ch_a != ch_b) { + /* ch is different */ + goto exit; + } else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80) + && (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80) + ) { + if (offset_a != offset_b) + goto exit; + } + + is_grouped = _TRUE; + +exit: + return is_grouped; +} + +/** + * rtw_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset + * @req_ch: pointer of the request ch, may be modified further + * @req_bw: pointer of the request bw, may be modified further + * @req_offset: pointer of the request offset, may be modified further + * @g_ch: pointer of the ongoing group ch + * @g_bw: pointer of the ongoing group bw, may be modified further + * @g_offset: pointer of the ongoing group offset, may be modified further + */ +void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset) +{ + + *req_ch = *g_ch; + + if (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) { + /*2.4G ch, downgrade to 40Mhz */ + *req_bw = CHANNEL_WIDTH_40; + } + + switch (*req_bw) { + case CHANNEL_WIDTH_80: + if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) + *req_offset = *g_offset; + else if (*g_bw == CHANNEL_WIDTH_20) + *req_offset = rtw_get_offset_by_ch(*req_ch); + + if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + RTW_ERR("%s req 80MHz BW without offset, down to 20MHz\n", __func__); + rtw_warn_on(1); + *req_bw = CHANNEL_WIDTH_20; + } + break; + case CHANNEL_WIDTH_40: + if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) + *req_offset = *g_offset; + else if (*g_bw == CHANNEL_WIDTH_20) + *req_offset = rtw_get_offset_by_ch(*req_ch); + + if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + RTW_ERR("%s req 40MHz BW without offset, down to 20MHz\n", __func__); + rtw_warn_on(1); + *req_bw = CHANNEL_WIDTH_20; + } + break; + case CHANNEL_WIDTH_20: + *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + default: + RTW_ERR("%s req unsupported BW:%u\n", __func__, *req_bw); + rtw_warn_on(1); + } + + if (*req_bw > *g_bw) { + *g_bw = *req_bw; + *g_offset = *req_offset; + } +} + +/** + * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies. + * @in_ie: Pointer of the first p2p ie + * @in_len: Total len of muiltiple p2p ies + * Returns: Length of merged p2p ie length + */ +u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len) +{ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 }; + int i = 0; + int j = 0, len = 0; + + while (i < in_len) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i); + + if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) { + len += pIE->Length - 4; /* 4 is P2P OUI length, don't count it in this loop */ + } + + i += (pIE->Length + 2); + } + + return len + 4; /* Append P2P OUI length at last. */ +} + +/** + * rtw_p2p_merge_ies - Merge muitiple p2p ies into one + * @in_ie: Pointer of the first p2p ie + * @in_len: Total len of muiltiple p2p ies + * @merge_ie: Pointer of merged ie + * Returns: Length of merged p2p ie + */ +int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie) +{ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 len = 0; + u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 }; + u8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 }; /* EID;Len;OUI, Len would copy at the end of function */ + int i = 0; + + if (merge_ie != NULL) { + /* Set first P2P OUI */ + _rtw_memcpy(merge_ie, ELOUI, 6); + merge_ie += 6; + + while (i < in_len) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie + i); + + /* Take out the rest of P2P OUIs */ + if (pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4)) { + _rtw_memcpy(merge_ie, pIE->data + 4, pIE->Length - 4); + len += pIE->Length - 4; + merge_ie += pIE->Length - 4; + } + + i += (pIE->Length + 2); + } + + return len + 4; /* 4 is for P2P OUI */ + + } + + return 0; +} + +void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len) +{ + u8 *pos = (u8 *)ie; + u8 id; + u16 len; + + u8 *p2p_ie; + uint p2p_ielen; + + p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen); + if (p2p_ie != ie || p2p_ielen == 0) + return; + + pos += 6; + while (pos - ie + 3 <= ie_len) { + id = *pos; + len = RTW_GET_LE16(pos + 1); + + RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len + , ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)"); + + pos += (3 + len); + } +} + +/** + * rtw_get_p2p_ie - Search P2P IE from a series of IEs + * @in_ie: Address of IEs to search + * @in_len: Length limit from in_ie + * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie + * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE + * + * Returns: The address of the P2P IE found, or NULL + */ +u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) +{ + uint cnt; + u8 *p2p_ie_ptr = NULL; + u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09}; + + if (p2p_ielen) + *p2p_ielen = 0; + + if (!in_ie || in_len < 0) { + rtw_warn_on(1); + return p2p_ie_ptr; + } + + if (in_len <= 0) + return p2p_ie_ptr; + + cnt = 0; + + while (cnt + 1 + 4 < in_len) { + eid = in_ie[cnt]; + + if (cnt + 1 + 4 >= MAX_IE_SZ) { + rtw_warn_on(1); + return NULL; + } + + if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], p2p_oui, 4) == _TRUE) { + p2p_ie_ptr = in_ie + cnt; + + if (p2p_ie) + _rtw_memcpy(p2p_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + if (p2p_ielen) + *p2p_ielen = in_ie[cnt + 1] + 2; + + break; + } else + cnt += in_ie[cnt + 1] + 2; + + } + + return p2p_ie_ptr; +} + +/** + * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE + * @p2p_ie: Address of P2P IE to search + * @p2p_ielen: Length limit from p2p_ie + * @target_attr_id: The attribute ID of P2P attribute to search + * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr + * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute + * + * Returns: the address of the specific WPS attribute found, or NULL + */ +u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_attr, u32 *len_attr) +{ + u8 *attr_ptr = NULL; + u8 *target_attr_ptr = NULL; + u8 p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09}; + + if (len_attr) + *len_attr = 0; + + if (!p2p_ie + || p2p_ielen <= 6 + || (p2p_ie[0] != WLAN_EID_VENDOR_SPECIFIC) + || (_rtw_memcmp(p2p_ie + 2, p2p_oui, 4) != _TRUE)) + return attr_ptr; + + /* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */ + attr_ptr = p2p_ie + 6; /* goto first attr */ + + while ((attr_ptr - p2p_ie + 3) <= p2p_ielen) { + /* 3 = 1(Attribute ID) + 2(Length) */ + u8 attr_id = *attr_ptr; + u16 attr_data_len = RTW_GET_LE16(attr_ptr + 1); + u16 attr_len = attr_data_len + 3; + + if (0) + RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len); + + if ((attr_ptr - p2p_ie + attr_len) > p2p_ielen) + break; + + if (attr_id == target_attr_id) { + target_attr_ptr = attr_ptr; + + if (buf_attr) + _rtw_memcpy(buf_attr, attr_ptr, attr_len); + + if (len_attr) + *len_attr = attr_len; + + break; + } else + attr_ptr += attr_len; + } + + return target_attr_ptr; +} + +/** + * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE + * @p2p_ie: Address of P2P IE to search + * @p2p_ielen: Length limit from p2p_ie + * @target_attr_id: The attribute ID of P2P attribute to search + * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content + * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content + * + * Returns: the address of the specific P2P attribute content found, or NULL + */ +u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id , u8 *buf_content, uint *len_content) +{ + u8 *attr_ptr; + u32 attr_len; + + if (len_content) + *len_content = 0; + + attr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len); + + if (attr_ptr && attr_len) { + if (buf_content) + _rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3); + + if (len_content) + *len_content = attr_len - 3; + + return attr_ptr + 3; + } + + return NULL; +} + +u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr) +{ + u32 a_len; + + *pbuf = attr_id; + + /* *(u16*)(pbuf + 1) = cpu_to_le16(attr_len); */ + RTW_PUT_LE16(pbuf + 1, attr_len); + + if (pdata_attr) + _rtw_memcpy(pbuf + 3, pdata_attr, attr_len); + + a_len = attr_len + 3; + + return a_len; +} + +uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id) +{ +#define DBG_DEL_P2P_ATTR 0 + + u8 *target_attr; + u32 target_attr_len; + uint ielen = ielen_ori; + int index = 0; + + while (1) { + target_attr = rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len); + if (target_attr && target_attr_len) { + u8 *next_attr = target_attr + target_attr_len; + uint remain_len = ielen - (next_attr - ie); + + if (DBG_DEL_P2P_ATTR) { + RTW_INFO("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, ie, ielen); + + RTW_INFO("ie:%p, ielen:%u\n", ie, ielen); + RTW_INFO("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len); + RTW_INFO("next_attr:%p, remain_len:%u\n", next_attr, remain_len); + } + + _rtw_memmove(target_attr, next_attr, remain_len); + _rtw_memset(target_attr + remain_len, 0, target_attr_len); + *(ie + 1) -= target_attr_len; + ielen -= target_attr_len; + + if (DBG_DEL_P2P_ATTR) { + RTW_INFO("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, ie, ielen); + } + + index++; + } else + break; + } + + return ielen; +} + +inline u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen) +{ + return rtw_get_p2p_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), p2p_ie, p2p_ielen); +} + +void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) +{ +#define DBG_BSS_EX_DEL_P2P_ATTR 0 + + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex); + + u8 *ie; + uint ie_len, ie_len_ori; + + int index = 0; + + while (1) { + ie = rtw_get_p2p_ie(ies, ies_len, NULL, &ie_len_ori); + if (ie) { + u8 *next_ie_ori = ie + ie_len_ori; + uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs); + u8 has_target_attr = 0; + + if (DBG_BSS_EX_DEL_P2P_ATTR) { + if (rtw_get_p2p_attr(ie, ie_len_ori, attr_id, NULL, NULL)) { + RTW_INFO("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex)); + + RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len); + RTW_INFO("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori); + RTW_INFO("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len); + has_target_attr = 1; + } + } + + ie_len = rtw_del_p2p_attr(ie, ie_len_ori, attr_id); + if (ie_len != ie_len_ori) { + u8 *next_ie = ie + ie_len; + + _rtw_memmove(next_ie, next_ie_ori, remain_len); + _rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len); + bss_ex->IELength -= ie_len_ori - ie_len; + + ies = next_ie; + } else + ies = next_ie_ori; + + if (DBG_BSS_EX_DEL_P2P_ATTR) { + if (has_target_attr) { + RTW_INFO("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex)); + } + } + + ies_len = remain_len; + + index++; + } else + break; + } +} + +void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len) +{ + u8 *pos = (u8 *)ie; + u8 id; + u16 len; + + u8 *wfd_ie; + uint wfd_ielen; + + wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen); + if (wfd_ie != ie || wfd_ielen == 0) + return; + + pos += 6; + while (pos - ie + 3 <= ie_len) { + id = *pos; + len = RTW_GET_BE16(pos + 1); + + RTW_PRINT_SEL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len + , ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)"); + + pos += (3 + len); + } +} + +/** + * rtw_get_wfd_ie - Search WFD IE from a series of IEs + * @in_ie: Address of IEs to search + * @in_len: Length limit from in_ie + * @wfd_ie: If not NULL and WFD IE is found, WFD IE will be copied to the buf starting from wfd_ie + * @wfd_ielen: If not NULL and WFD IE is found, will set to the length of the entire WFD IE + * + * Returns: The address of the P2P IE found, or NULL + */ +u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) +{ + uint cnt; + u8 *wfd_ie_ptr = NULL; + u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A}; + + if (wfd_ielen) + *wfd_ielen = 0; + + if (!in_ie || in_len < 0) { + rtw_warn_on(1); + return wfd_ie_ptr; + } + + if (in_len <= 0) + return wfd_ie_ptr; + + cnt = 0; + + while (cnt + 1 + 4 < in_len) { + eid = in_ie[cnt]; + + if (cnt + 1 + 4 >= MAX_IE_SZ) { + rtw_warn_on(1); + return NULL; + } + + if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wfd_oui, 4) == _TRUE) { + wfd_ie_ptr = in_ie + cnt; + + if (wfd_ie) + _rtw_memcpy(wfd_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + if (wfd_ielen) + *wfd_ielen = in_ie[cnt + 1] + 2; + + break; + } else + cnt += in_ie[cnt + 1] + 2; + + } + + return wfd_ie_ptr; +} + +/** + * rtw_get_wfd_attr - Search a specific WFD attribute from a given WFD IE + * @wfd_ie: Address of WFD IE to search + * @wfd_ielen: Length limit from wfd_ie + * @target_attr_id: The attribute ID of WFD attribute to search + * @buf_attr: If not NULL and the WFD attribute is found, WFD attribute will be copied to the buf starting from buf_attr + * @len_attr: If not NULL and the WFD attribute is found, will set to the length of the entire WFD attribute + * + * Returns: the address of the specific WPS attribute found, or NULL + */ +u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr) +{ + u8 *attr_ptr = NULL; + u8 *target_attr_ptr = NULL; + u8 wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A}; + + if (len_attr) + *len_attr = 0; + + if (!wfd_ie + || wfd_ielen <= 6 + || (wfd_ie[0] != WLAN_EID_VENDOR_SPECIFIC) + || (_rtw_memcmp(wfd_ie + 2, wfd_oui, 4) != _TRUE)) + return attr_ptr; + + /* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */ + attr_ptr = wfd_ie + 6; /* goto first attr */ + + while ((attr_ptr - wfd_ie + 3) <= wfd_ielen) { + /* 3 = 1(Attribute ID) + 2(Length) */ + u8 attr_id = *attr_ptr; + u16 attr_data_len = RTW_GET_BE16(attr_ptr + 1); + u16 attr_len = attr_data_len + 3; + + if (0) + RTW_INFO("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len); + + if ((attr_ptr - wfd_ie + attr_len) > wfd_ielen) + break; + + if (attr_id == target_attr_id) { + target_attr_ptr = attr_ptr; + + if (buf_attr) + _rtw_memcpy(buf_attr, attr_ptr, attr_len); + + if (len_attr) + *len_attr = attr_len; + + break; + } else + attr_ptr += attr_len; + } + + return target_attr_ptr; +} + +/** + * rtw_get_wfd_attr_content - Search a specific WFD attribute content from a given WFD IE + * @wfd_ie: Address of WFD IE to search + * @wfd_ielen: Length limit from wfd_ie + * @target_attr_id: The attribute ID of WFD attribute to search + * @buf_content: If not NULL and the WFD attribute is found, WFD attribute content will be copied to the buf starting from buf_content + * @len_content: If not NULL and the WFD attribute is found, will set to the length of the WFD attribute content + * + * Returns: the address of the specific WFD attribute content found, or NULL + */ +u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content) +{ + u8 *attr_ptr; + u32 attr_len; + + if (len_content) + *len_content = 0; + + attr_ptr = rtw_get_wfd_attr(wfd_ie, wfd_ielen, target_attr_id, NULL, &attr_len); + + if (attr_ptr && attr_len) { + if (buf_content) + _rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3); + + if (len_content) + *len_content = attr_len - 3; + + return attr_ptr + 3; + } + + return NULL; +} + +uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg) +{ +#define DBG_DEL_WFD_IE 0 + + u8 *target_ie; + u32 target_ie_len; + uint ies_len = ies_len_ori; + int index = 0; + + while (1) { + target_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len); + if (target_ie && target_ie_len) { + u8 *next_ie = target_ie + target_ie_len; + uint remain_len = ies_len - (next_ie - ies); + + if (DBG_DEL_WFD_IE && msg) { + RTW_INFO("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + + RTW_INFO("ies:%p, ies_len:%u\n", ies, ies_len); + RTW_INFO("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len); + RTW_INFO("next_ie:%p, remain_len:%u\n", next_ie, remain_len); + } + + _rtw_memmove(target_ie, next_ie, remain_len); + _rtw_memset(target_ie + remain_len, 0, target_ie_len); + ies_len -= target_ie_len; + + if (DBG_DEL_WFD_IE && msg) { + RTW_INFO("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + } + + index++; + } else + break; + } + + return ies_len; +} + +inline u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen) +{ + return rtw_get_wfd_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), wfd_ie, wfd_ielen); +} + +void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex) +{ +#define DBG_BSS_EX_DEL_WFD_IE 0 + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex); + uint ies_len; + + ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL); + bss_ex->IELength -= ies_len_ori - ies_len; +} + +int rtw_get_cipher_info(struct wlan_network *pnetwork) +{ + u32 wpa_ielen; + unsigned char *pbuf; + int group_cipher = 0, pairwise_cipher = 0, is8021x = 0; + int ret = _FAIL; + pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); + + if (pbuf && (wpa_ielen > 0)) { + if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) { + + pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; + pnetwork->BcnInfo.group_cipher = group_cipher; + pnetwork->BcnInfo.is_8021x = is8021x; + ret = _SUCCESS; + } + } else { + + pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); + + if (pbuf && (wpa_ielen > 0)) { + if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen + 2, &group_cipher, &pairwise_cipher, &is8021x)) { + pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; + pnetwork->BcnInfo.group_cipher = group_cipher; + pnetwork->BcnInfo.is_8021x = is8021x; + ret = _SUCCESS; + } + } + } + + return ret; +} + +void rtw_get_bcn_info(struct wlan_network *pnetwork) +{ + unsigned short cap = 0; + u8 bencrypt = 0; + /* u8 wpa_ie[255],rsn_ie[255]; */ + u16 wpa_len = 0, rsn_len = 0; + struct HT_info_element *pht_info = NULL; + struct rtw_ieee80211_ht_cap *pht_cap = NULL; + unsigned int len; + unsigned char *p; + + _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); + cap = le16_to_cpu(cap); + if (cap & WLAN_CAPABILITY_PRIVACY) { + bencrypt = 1; + pnetwork->network.Privacy = 1; + } else + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_OPENSYS; + rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, NULL, &rsn_len, NULL, &wpa_len); + + if (rsn_len > 0) + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA2; + else if (wpa_len > 0) + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA; + else { + if (bencrypt) + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WEP; + } + rtw_get_cipher_info(pnetwork); + + /* get bwmode and ch_offset */ + /* parsing HT_CAP_IE */ + p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_); + if (p && len > 0) { + pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); + pnetwork->BcnInfo.ht_cap_info = pht_cap->cap_info; + } else + pnetwork->BcnInfo.ht_cap_info = 0; + /* parsing HT_INFO_IE */ + p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_); + if (p && len > 0) { + pht_info = (struct HT_info_element *)(p + 2); + pnetwork->BcnInfo.ht_info_infos_0 = pht_info->infos[0]; + } else + pnetwork->BcnInfo.ht_info_infos_0 = 0; +} + +u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set) +{ + u8 nss = 1; + + if (supp_mcs_set[3]) + nss = 4; + else if (supp_mcs_set[2]) + nss = 3; + else if (supp_mcs_set[1]) + nss = 2; + else if (supp_mcs_set[0]) + nss = 1; + else + RTW_INFO("%s,%d, warning! supp_mcs_set is zero\n", __func__, __LINE__); + /* RTW_INFO("%s HT: %dSS\n", __FUNCTION__, nss); */ + return nss; +} + +u32 rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss) +{ + u8 i; + u32 bitmap = 0; + + for (i = 0; i < nss; i++) + bitmap |= mcs_set[i] << (i * 8); + + RTW_INFO("ht_mcs_set=%02x %02x %02x %02x, nss=%u, bitmap=%08x\n" + , mcs_set[0], mcs_set[1], mcs_set[2], mcs_set[3], nss, bitmap); + + return bitmap; +} + +/* show MCS rate, unit: 100Kbps */ +u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate) +{ + u16 max_rate = 0; + + if (MCS_rate[3]) { + if (MCS_rate[3] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI) ? 6000 : 5400) : ((short_GI) ? 2889 : 2600); + else if (MCS_rate[3] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI) ? 5400 : 4860) : ((short_GI) ? 2600 : 2340); + else if (MCS_rate[3] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI) ? 4800 : 4320) : ((short_GI) ? 2311 : 2080); + else if (MCS_rate[3] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560); + else if (MCS_rate[3] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040); + else if (MCS_rate[3] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780); + else if (MCS_rate[3] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520); + else if (MCS_rate[3] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260); + } else if (MCS_rate[2]) { + if (MCS_rate[2] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI) ? 4500 : 4050) : ((short_GI) ? 2167 : 1950); + else if (MCS_rate[2] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI) ? 4050 : 3645) : ((short_GI) ? 1950 : 1750); + else if (MCS_rate[2] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI) ? 3600 : 3240) : ((short_GI) ? 1733 : 1560); + else if (MCS_rate[2] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170); + else if (MCS_rate[2] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780); + else if (MCS_rate[2] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585); + else if (MCS_rate[2] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390); + else if (MCS_rate[2] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195); + } else if (MCS_rate[1]) { + if (MCS_rate[1] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI) ? 3000 : 2700) : ((short_GI) ? 1444 : 1300); + else if (MCS_rate[1] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI) ? 2700 : 2430) : ((short_GI) ? 1300 : 1170); + else if (MCS_rate[1] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI) ? 2400 : 2160) : ((short_GI) ? 1156 : 1040); + else if (MCS_rate[1] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1800 : 1620) : ((short_GI) ? 867 : 780); + else if (MCS_rate[1] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520); + else if (MCS_rate[1] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390); + else if (MCS_rate[1] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260); + else if (MCS_rate[1] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130); + } else { + if (MCS_rate[0] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1500 : 1350) : ((short_GI) ? 722 : 650); + else if (MCS_rate[0] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1350 : 1215) : ((short_GI) ? 650 : 585); + else if (MCS_rate[0] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI) ? 1200 : 1080) : ((short_GI) ? 578 : 520); + else if (MCS_rate[0] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI) ? 900 : 810) : ((short_GI) ? 433 : 390); + else if (MCS_rate[0] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI) ? 600 : 540) : ((short_GI) ? 289 : 260); + else if (MCS_rate[0] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI) ? 450 : 405) : ((short_GI) ? 217 : 195); + else if (MCS_rate[0] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130); + else if (MCS_rate[0] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65); + } + + return max_rate; +} + +/*static const char *_action_public_str[] = { + "ACT_PUB_BSSCOEXIST", + "ACT_PUB_DSE_ENABLE", + "ACT_PUB_DSE_DEENABLE", + "ACT_PUB_DSE_REG_LOCATION", + "ACT_PUB_EXT_CHL_SWITCH", + "ACT_PUB_DSE_MSR_REQ", + "ACT_PUB_DSE_MSR_RPRT", + "ACT_PUB_MP", + "ACT_PUB_DSE_PWR_CONSTRAINT", + "ACT_PUB_VENDOR", + "ACT_PUB_GAS_INITIAL_REQ", + "ACT_PUB_GAS_INITIAL_RSP", + "ACT_PUB_GAS_COMEBACK_REQ", + "ACT_PUB_GAS_COMEBACK_RSP", + "ACT_PUB_TDLS_DISCOVERY_RSP", + "ACT_PUB_LOCATION_TRACK", + "ACT_PUB_RSVD", +};*/ + diff --git a/drivers/staging/rtl8821ce/core/rtw_io.c b/drivers/staging/rtl8821ce/core/rtw_io.c new file mode 100644 index 000000000000..b331e656704d --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_io.c @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _RTW_IO_C_ + +#include <drv_types.h> +#include <hal_data.h> + +#if defined(CONFIG_PLATFORM_RTL8197D) + #define rtw_le16_to_cpu(val) val + #define rtw_le32_to_cpu(val) val + #define rtw_cpu_to_le16(val) val + #define rtw_cpu_to_le32(val) val +#else + #define rtw_le16_to_cpu(val) le16_to_cpu(val) + #define rtw_le32_to_cpu(val) le32_to_cpu(val) + #define rtw_cpu_to_le16(val) cpu_to_le16(val) + #define rtw_cpu_to_le32(val) cpu_to_le32(val) +#endif + +u8 _rtw_read8(_adapter *adapter, u32 addr) +{ + u8 r_val; + /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr); + _read8 = pintfhdl->io_ops._read8; + + r_val = _read8(pintfhdl, addr); + return r_val; +} + +u16 _rtw_read16(_adapter *adapter, u32 addr) +{ + u16 r_val; + /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr); + _read16 = pintfhdl->io_ops._read16; + + r_val = _read16(pintfhdl, addr); + return rtw_le16_to_cpu(r_val); +} + +u32 _rtw_read32(_adapter *adapter, u32 addr) +{ + u32 r_val; + /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr); + _read32 = pintfhdl->io_ops._read32; + + r_val = _read32(pintfhdl, addr); + return rtw_le32_to_cpu(r_val); + +} + +int _rtw_write8(_adapter *adapter, u32 addr, u8 val) +{ + /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int ret; + _write8 = pintfhdl->io_ops._write8; + + ret = _write8(pintfhdl, addr, val); + + return RTW_STATUS_CODE(ret); +} + +int _rtw_write16(_adapter *adapter, u32 addr, u16 val) +{ + /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int ret; + _write16 = pintfhdl->io_ops._write16; + + val = rtw_cpu_to_le16(val); + ret = _write16(pintfhdl, addr, val); + + return RTW_STATUS_CODE(ret); +} + +int _rtw_write32(_adapter *adapter, u32 addr, u32 val) +{ + /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + int ret; + _write32 = pintfhdl->io_ops._write32; + + val = rtw_cpu_to_le32(val); + ret = _write32(pintfhdl, addr, val); + + return RTW_STATUS_CODE(ret); +} + +u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) +{ + u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + /* struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; */ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u32 ret = _SUCCESS; + + _write_port = pintfhdl->io_ops._write_port; + + ret = _write_port(pintfhdl, addr, cnt, pmem); + + return ret; +} + +int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops)) +{ + struct io_priv *piopriv = &padapter->iopriv; + struct intf_hdl *pintf = &piopriv->intf; + + if (set_intf_ops == NULL) + return _FAIL; + + piopriv->padapter = padapter; + pintf->padapter = padapter; + pintf->pintf_dev = adapter_to_dvobj(padapter); + + set_intf_ops(padapter, &pintf->io_ops); + + return _SUCCESS; +} + + diff --git a/drivers/staging/rtl8821ce/core/rtw_ioctl_query.c b/drivers/staging/rtl8821ce/core/rtw_ioctl_query.c new file mode 100644 index 000000000000..4971f02a066c --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_ioctl_query.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_IOCTL_QUERY_C_ + +#include <drv_types.h> + diff --git a/drivers/staging/rtl8821ce/core/rtw_ioctl_set.c b/drivers/staging/rtl8821ce/core/rtw_ioctl_set.c new file mode 100644 index 000000000000..e5a864f299a0 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_ioctl_set.c @@ -0,0 +1,602 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_IOCTL_SET_C_ + +#include <drv_types.h> +#include <hal_data.h> + +extern void indicate_wx_scan_complete_event(_adapter *padapter); + +#define IS_MAC_ADDRESS_BROADCAST(addr) \ + (\ + ((addr[0] == 0xff) && (addr[1] == 0xff) && \ + (addr[2] == 0xff) && (addr[3] == 0xff) && \ + (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \ + ) + +u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) +{ + u8 i; + u8 ret = _TRUE; + + if (ssid->SsidLength > 32) { + ret = _FALSE; + goto exit; + } + +#ifdef CONFIG_VALIDATE_SSID + for (i = 0; i < ssid->SsidLength; i++) { + /* wifi, printable ascii code must be supported */ + if (!((ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e))) { + ret = _FALSE; + break; + } + } +#endif /* CONFIG_VALIDATE_SSID */ + +exit: + + return ret; +} + +u8 rtw_do_join(_adapter *padapter); +u8 rtw_do_join(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + u8 *pibss = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + u8 ret = _SUCCESS; + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + + pmlmepriv->cur_network.join_res = -2; + + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + + pmlmepriv->pscanned = plist; + + pmlmepriv->to_join = _TRUE; + + if (_rtw_queue_empty(queue) == _TRUE) { + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + /* when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty */ + /* we try to issue sitesurvey firstly */ + + if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE + || rtw_to_roam(padapter) > 0 + ) { + /* submit site_survey_cmd */ + ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); + if (_SUCCESS != ret) { + pmlmepriv->to_join = _FALSE; + } + } else { + pmlmepriv->to_join = _FALSE; + ret = _FAIL; + } + + goto exit; + } else { + int select_ret; + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + select_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv); + if (select_ret == _SUCCESS) { + pmlmepriv->to_join = _FALSE; + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + } else { + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) { + /* submit createbss_cmd to change to a ADHOC_MASTER */ + + /* pmlmepriv->lock has been acquired by caller... */ + WLAN_BSSID_EX *pdev_network = &(padapter->registrypriv.dev_network); + + /*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/ + init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + + pibss = padapter->registrypriv.dev_network.MacAddress; + + _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(padapter); + + rtw_generate_random_ibss(pibss); + + if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) { + ret = _FALSE; + goto exit; + } + + pmlmepriv->to_join = _FALSE; + + } else { + /* can't associate ; reset under-linking */ + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + /* when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue */ + /* we try to issue sitesurvey firstly */ + if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _FALSE + || rtw_to_roam(padapter) > 0 + ) { + /* RTW_INFO("rtw_do_join() when no desired bss in scanning queue\n"); */ + ret = rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); + if (_SUCCESS != ret) { + pmlmepriv->to_join = _FALSE; + } + } else { + ret = _FAIL; + pmlmepriv->to_join = _FALSE; + } + } + + } + + } + +exit: + + return ret; +} + +u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid) +{ + _irqL irqL; + u8 status = _SUCCESS; + + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + RTW_PRINT("set bssid:%pM\n", bssid); + + if ((bssid[0] == 0x00 && bssid[1] == 0x00 && bssid[2] == 0x00 && bssid[3] == 0x00 && bssid[4] == 0x00 && bssid[5] == 0x00) || + (bssid[0] == 0xFF && bssid[1] == 0xFF && bssid[2] == 0xFF && bssid[3] == 0xFF && bssid[4] == 0xFF && bssid[5] == 0xFF)) { + status = _FAIL; + goto exit; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + RTW_INFO("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) + goto handle_tkip_countermeasure; + else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) + goto release_mlme_lock; + + if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) { + + if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE) + goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */ + } else { + + rtw_disassoc_cmd(padapter, 0, 0); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + rtw_indicate_disconnect(padapter, 0, _FALSE); + + rtw_free_assoc_resources(padapter, 1); + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + } + } + } + +handle_tkip_countermeasure: + if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { + status = _FAIL; + goto release_mlme_lock; + } + + _rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN); + pmlmepriv->assoc_by_bssid = _TRUE; + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) + pmlmepriv->to_join = _TRUE; + else + status = rtw_do_join(padapter); + +release_mlme_lock: + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +exit: + + return status; +} + +u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid) +{ + _irqL irqL; + u8 status = _SUCCESS; + u32 cur_time = 0; + + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *pnetwork = &pmlmepriv->cur_network; + + RTW_PRINT("set ssid [%s] fw_state=0x%08x\n", + ssid->Ssid, get_fwstate(pmlmepriv)); + + if (!rtw_is_hw_init_completed(padapter)) { + status = _FAIL; + goto exit; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + RTW_INFO("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) + goto handle_tkip_countermeasure; + else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) + goto release_mlme_lock; + + if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) { + + if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) && + (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) { + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) { + + if (rtw_is_same_ibss(padapter, pnetwork) == _FALSE) { + /* if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again */ + rtw_disassoc_cmd(padapter, 0, 0); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + rtw_indicate_disconnect(padapter, 0, _FALSE); + + rtw_free_assoc_resources(padapter, 1); + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + } + } else { + goto release_mlme_lock;/* it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. */ + } + } + else + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1); + } else { + + rtw_disassoc_cmd(padapter, 0, 0); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + rtw_indicate_disconnect(padapter, 0, _FALSE); + + rtw_free_assoc_resources(padapter, 1); + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + } + } + } + +handle_tkip_countermeasure: + if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { + status = _FAIL; + goto release_mlme_lock; + } + + if (rtw_validate_ssid(ssid) == _FALSE) { + status = _FAIL; + goto release_mlme_lock; + } + + _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID)); + pmlmepriv->assoc_by_bssid = _FALSE; + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) + pmlmepriv->to_join = _TRUE; + else + status = rtw_do_join(padapter); + +release_mlme_lock: + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +exit: + + return status; + +} + +u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, + NDIS_802_11_NETWORK_INFRASTRUCTURE networktype) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + NDIS_802_11_NETWORK_INFRASTRUCTURE *pold_state = &(cur_network->network.InfrastructureMode); + + if (*pold_state != networktype) { + /* RTW_INFO("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); */ + + if (*pold_state == Ndis802_11APMode) { + /* change to other mode from Ndis802_11APMode */ + cur_network->join_res = -1; + + stop_ap_mode(padapter); + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (*pold_state == Ndis802_11IBSS)) + rtw_disassoc_cmd(padapter, 0, 0); + + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) + rtw_free_assoc_resources(padapter, 1); + + if ((*pold_state == Ndis802_11Infrastructure) || (*pold_state == Ndis802_11IBSS)) { + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + rtw_indicate_disconnect(padapter, 0, _FALSE); /*will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not*/ + } + } + + *pold_state = networktype; + + _clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE); + + switch (networktype) { + case Ndis802_11IBSS: + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + break; + + case Ndis802_11Infrastructure: + set_fwstate(pmlmepriv, WIFI_STATION_STATE); + break; + + case Ndis802_11APMode: + set_fwstate(pmlmepriv, WIFI_AP_STATE); + start_ap_mode(padapter); + /* rtw_indicate_connect(padapter); */ + + break; + + case Ndis802_11AutoUnknown: + case Ndis802_11InfrastructureMax: + break; + case Ndis802_11Monitor: + set_fwstate(pmlmepriv, WIFI_MONITOR_STATE); + break; + } + + /* SecClearAllKeys(adapter); */ + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + } + + return _TRUE; +} + +u8 rtw_set_802_11_disassociate(_adapter *padapter) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + + rtw_disassoc_cmd(padapter, 0, 0); + rtw_indicate_disconnect(padapter, 0, _FALSE); + /* modify for CONFIG_IEEE80211W, none 11w can use it */ + rtw_free_assoc_resources_cmd(padapter); + if (_FAIL == rtw_pwr_wakeup(padapter)) + RTW_INFO("%s(): rtw_pwr_wakeup fail !!!\n", __FUNCTION__); + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + return _TRUE; +} + +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 res = _TRUE; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, ch, ch_num); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + return res; +} + +u8 rtw_set_802_11_authentication_mode(_adapter *padapter, NDIS_802_11_AUTHENTICATION_MODE authmode) +{ + struct security_priv *psecuritypriv = &padapter->securitypriv; + int res; + u8 ret; + + psecuritypriv->ndisauthtype = authmode; + + if (psecuritypriv->ndisauthtype > 3) + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + + res = rtw_set_auth(padapter, psecuritypriv); + + if (res == _SUCCESS) + ret = _TRUE; + else + ret = _FALSE; + + return ret; +} + +u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep) +{ + + u8 bdefaultkey; + u8 btransmitkey; + sint keyid, res; + struct security_priv *psecuritypriv = &(padapter->securitypriv); + u8 ret = _SUCCESS; + + bdefaultkey = (wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; /* for ??? */ + btransmitkey = (wep->KeyIndex & 0x80000000) > 0 ? _TRUE : _FALSE; /* for ??? */ + keyid = wep->KeyIndex & 0x3fffffff; + + if (keyid >= 4) { + ret = _FALSE; + goto exit; + } + + switch (wep->KeyLength) { + case 5: + psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; + break; + case 13: + psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; + break; + default: + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + break; + } + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]), &(wep->KeyMaterial), wep->KeyLength); + + psecuritypriv->dot11DefKeylen[keyid] = wep->KeyLength; + + psecuritypriv->dot11PrivacyKeyIndex = keyid; + + res = rtw_set_key(padapter, psecuritypriv, keyid, 1, _TRUE); + + if (res == _FAIL) + ret = _FALSE; +exit: + + return ret; + +} + +/* +* rtw_get_cur_max_rate - +* @adapter: pointer to _adapter structure +* +* Return 0 or 100Kbps +*/ +u16 rtw_get_cur_max_rate(_adapter *adapter) +{ + int i = 0; + u16 rate = 0, max_rate = 0; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + struct sta_info *psta = NULL; + u8 short_GI = 0; + u8 rf_type = 0; + + if (adapter->registrypriv.mp_mode == 1) { + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + return 0; + } + + if ((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) + && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE)) + return 0; + + psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv)); + if (psta == NULL) + return 0; + + short_GI = query_ra_short_GI(psta, psta->bw_mode); + + if (is_supported_ht(psta->wireless_mode)) { + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + max_rate = rtw_mcs_rate(rf_type + , (psta->bw_mode == CHANNEL_WIDTH_40) ? 1 : 0 + , short_GI + , psta->htpriv.ht_cap.supp_mcs_set + ); + } + else if (is_supported_vht(psta->wireless_mode)) + max_rate = ((rtw_vht_mcs_to_data_rate(psta->bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; + else + { + while ((pcur_bss->SupportedRates[i] != 0) && (pcur_bss->SupportedRates[i] != 0xFF)) { + rate = pcur_bss->SupportedRates[i] & 0x7F; + if (rate > max_rate) + max_rate = rate; + i++; + } + + max_rate = max_rate * 10 / 2; + } + + return max_rate; +} + +/* +* rtw_set_channel_plan - +* @adapter: pointer to _adapter structure +* @channel_plan: +* +* Return _SUCCESS or _FAIL +*/ +int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan) +{ + struct registry_priv *pregistrypriv = &adapter->registrypriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + /* handle by cmd_thread to sync with scan operation */ + return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1); +} + +/* +* rtw_set_country - +* @adapter: pointer to _adapter structure +* @country_code: string of country code +* +* Return _SUCCESS or _FAIL +*/ +int rtw_set_country(_adapter *adapter, const char *country_code) +{ +#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY + return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1); +#else + return _FAIL; +#endif +} + +/* +* rtw_set_band - +* @adapter: pointer to _adapter structure +* @band: band to set +* +* Return _SUCCESS or _FAIL +*/ +int rtw_set_band(_adapter *adapter, u8 band) +{ + if (rtw_band_valid(band)) { + RTW_INFO(FUNC_ADPT_FMT" band:%d\n", FUNC_ADPT_ARG(adapter), band); + adapter->setband = band; + return _SUCCESS; + } + + RTW_PRINT(FUNC_ADPT_FMT" band:%d fail\n", FUNC_ADPT_ARG(adapter), band); + return _FAIL; +} diff --git a/drivers/staging/rtl8821ce/core/rtw_mi.c b/drivers/staging/rtl8821ce/core/rtw_mi.c new file mode 100644 index 000000000000..ba80d27371b5 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_mi.c @@ -0,0 +1,834 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2015 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MI_C_ + +#include <drv_types.h> +#include <hal_data.h> + +void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mi_state *iface_state = &dvobj->iface_state; + + iface_state->union_ch = ch; + iface_state->union_bw = bw; + iface_state->union_offset = offset; +} + +/* Find union about ch, bw, ch_offset of all linked/linking interfaces */ +int _rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, bool include_self) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_ext_priv *mlmeext; + int i; + u8 ch_ret = 0; + u8 bw_ret = CHANNEL_WIDTH_20; + u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int num = 0; + + if (ch) + *ch = 0; + if (bw) + *bw = CHANNEL_WIDTH_20; + if (offset) + *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlmeext = &iface->mlmeextpriv; + + if (!check_fwstate(&iface->mlmepriv, _FW_LINKED | _FW_UNDER_LINKING)) + continue; + + if (check_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING)) + continue; + + if (include_self == _FALSE && adapter == iface) + continue; + + if (num == 0) { + ch_ret = mlmeext->cur_channel; + bw_ret = mlmeext->cur_bwmode; + offset_ret = mlmeext->cur_ch_offset; + num++; + continue; + } + + if (ch_ret != mlmeext->cur_channel) { + num = 0; + break; + } + + if (bw_ret < mlmeext->cur_bwmode) { + bw_ret = mlmeext->cur_bwmode; + offset_ret = mlmeext->cur_ch_offset; + } else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) { + num = 0; + break; + } + + num++; + } + + if (num) { + if (ch) + *ch = ch_ret; + if (bw) + *bw = bw_ret; + if (offset) + *offset = offset_ret; + } + + return num; +} + +inline int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ + return _rtw_mi_get_ch_setting_union(adapter, ch, bw, offset, 1); +} + +inline int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ + return _rtw_mi_get_ch_setting_union(adapter, ch, bw, offset, 0); +} + +/* For now, not return union_ch/bw/offset */ +void _rtw_mi_status(_adapter *adapter, struct mi_state *mstate, bool include_self) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + int i; + + _rtw_memset(mstate, 0, sizeof(struct mi_state)); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + + if (include_self == _FALSE && iface == adapter) + continue; + + if (check_fwstate(&iface->mlmepriv, WIFI_STATION_STATE) == _TRUE) { + MSTATE_STA_NUM(mstate)++; + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) + MSTATE_STA_LD_NUM(mstate)++; + + if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE) + MSTATE_STA_LG_NUM(mstate)++; + + } else if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + MSTATE_AP_NUM(mstate)++; + if (iface->stapriv.asoc_sta_count > 2) + MSTATE_AP_LD_NUM(mstate)++; + + } else if (check_fwstate(&iface->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + MSTATE_ADHOC_NUM(mstate)++; + if (iface->stapriv.asoc_sta_count > 2) + MSTATE_ADHOC_LD_NUM(mstate)++; + } + + if (check_fwstate(&iface->mlmepriv, WIFI_UNDER_WPS) == _TRUE) + MSTATE_WPS_NUM(mstate)++; + + + } +} + +inline void rtw_mi_status(_adapter *adapter, struct mi_state *mstate) +{ + return _rtw_mi_status(adapter, mstate, 1); +} +inline void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate) +{ + return _rtw_mi_status(adapter, mstate, 0); +} +void dump_mi_status(void *sel, struct dvobj_priv *dvobj) +{ + RTW_PRINT_SEL(sel, "== dvobj-iface_state ==\n"); + RTW_PRINT_SEL(sel, "sta_num:%d\n", DEV_STA_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linking_sta_num:%d\n", DEV_STA_LG_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_sta_num:%d\n", DEV_STA_LD_NUM(dvobj)); + RTW_PRINT_SEL(sel, "ap_num:%d\n", DEV_AP_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_ap_num:%d\n", DEV_AP_LD_NUM(dvobj)); + RTW_PRINT_SEL(sel, "adhoc_num:%d\n", DEV_ADHOC_NUM(dvobj)); + RTW_PRINT_SEL(sel, "linked_adhoc_num:%d\n", DEV_ADHOC_LD_NUM(dvobj)); + RTW_PRINT_SEL(sel, "p2p_device_num:%d\n", rtw_mi_stay_in_p2p_mode(dvobj->padapters[IFACE_ID0])); + RTW_PRINT_SEL(sel, "under_wps_num:%d\n", DEV_WPS_NUM(dvobj)); + RTW_PRINT_SEL(sel, "union_ch:%d\n", DEV_U_CH(dvobj)); + RTW_PRINT_SEL(sel, "union_bw:%d\n", DEV_U_BW(dvobj)); + RTW_PRINT_SEL(sel, "union_offset:%d\n", DEV_U_OFFSET(dvobj)); + RTW_PRINT_SEL(sel, "================\n\n"); +} + +inline void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state) +{ + _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mi_state *iface_state = &dvobj->iface_state; + struct mi_state tmp_mstate; + u8 i; + u8 u_ch, u_offset, u_bw; + _adapter *iface; + + if (state == WIFI_MONITOR_STATE + || state == WIFI_SITE_MONITOR + || state == 0xFFFFFFFF + ) + return; + + if (0) + RTW_INFO("%s => will change or clean state to 0x%08x\n", __func__, state); + + rtw_mi_status(adapter, &tmp_mstate); + _rtw_memcpy(iface_state, &tmp_mstate, sizeof(struct mi_state)); + + if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) + rtw_mi_update_union_chan_inf(adapter , u_ch, u_offset , u_bw); + else { + if (0) { + dump_adapters_status(RTW_DBGDUMP , dvobj); + RTW_INFO("%s-[ERROR] cannot get union channel\n", __func__); + rtw_warn_on(1); + } + } + +} +u8 rtw_mi_check_status(_adapter *adapter, u8 type) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct mi_state *iface_state = &dvobj->iface_state; + u8 ret = _FALSE; + + + switch (type) { + case MI_LINKED: + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_NUM(iface_state) || MSTATE_ADHOC_NUM(iface_state)) /*check_fwstate(&iface->mlmepriv, _FW_LINKED)*/ + ret = _TRUE; + break; + case MI_ASSOC: + if (MSTATE_STA_LD_NUM(iface_state) || MSTATE_AP_LD_NUM(iface_state) || MSTATE_ADHOC_LD_NUM(iface_state)) + ret = _TRUE; + break; + case MI_UNDER_WPS: + if (MSTATE_WPS_NUM(iface_state)) + ret = _TRUE; + break; + + case MI_AP_MODE: + if (MSTATE_AP_NUM(iface_state)) + ret = _TRUE; + break; + case MI_AP_ASSOC: + if (MSTATE_AP_LD_NUM(iface_state)) + ret = _TRUE; + break; + + case MI_ADHOC: + if (MSTATE_ADHOC_NUM(iface_state)) + ret = _TRUE; + break; + case MI_ADHOC_ASSOC: + if (MSTATE_ADHOC_LD_NUM(iface_state)) + ret = _TRUE; + break; + + case MI_STA_NOLINK: /* this is misleading, but not used now */ + if (MSTATE_STA_NUM(iface_state) && (!(MSTATE_STA_LD_NUM(iface_state) || MSTATE_STA_LG_NUM(iface_state)))) + ret = _TRUE; + break; + case MI_STA_LINKED: + if (MSTATE_STA_LD_NUM(iface_state)) + ret = _TRUE; + break; + case MI_STA_LINKING: + if (MSTATE_STA_LG_NUM(iface_state)) + ret = _TRUE; + break; + + default: + break; + } + return ret; +} + +u8 rtw_mi_mp_mode_check(_adapter *padapter) +{ + if (padapter->registrypriv.mp_mode == 1) + return _TRUE; + return _FALSE; +} + +/* +* return value : 0 is failed or have not interface meet condition +* return value : !0 is success or interface numbers which meet condition +* return value of ops_func must be _TRUE or _FALSE +*/ +static u8 _rtw_mi_process(_adapter *padapter, bool exclude_self, + void *data, u8(*ops_func)(_adapter *padapter, void *data)) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + u8 ret = 0; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + + if ((exclude_self) && (iface == padapter)) + continue; + + if (ops_func) + if (_TRUE == ops_func(iface, data)) + ret++; + } + } + return ret; +} +static u8 _rtw_mi_process_without_schk(_adapter *padapter, bool exclude_self, + void *data, u8(*ops_func)(_adapter *padapter, void *data)) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + u8 ret = 0; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + if ((exclude_self) && (iface == padapter)) + continue; + + if (ops_func) + if (ops_func(iface, data) == _TRUE) + ret++; + } + } + return ret; +} + +static u8 _rtw_mi_netif_stop_queue(_adapter *padapter, void *data) +{ + bool carrier_off = *(bool *)data; + struct net_device *pnetdev = padapter->pnetdev; + + if (carrier_off) + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off) +{ + bool in_data = carrier_off; + + return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_netif_stop_queue); +} +u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off) +{ + bool in_data = carrier_off; + + return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_netif_stop_queue); +} + +static u8 _rtw_mi_netif_wake_queue(_adapter *padapter, void *data) +{ + struct net_device *pnetdev = padapter->pnetdev; + + if (pnetdev) + rtw_netif_wake_queue(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_wake_queue(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_wake_queue); +} +u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_wake_queue); +} + +static u8 _rtw_mi_netif_carrier_on(_adapter *padapter, void *data) +{ + struct net_device *pnetdev = padapter->pnetdev; + + if (pnetdev) + rtw_netif_carrier_on(pnetdev); + return _TRUE; +} +u8 rtw_mi_netif_carrier_on(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_netif_carrier_on); +} +u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_netif_carrier_on); +} + +static u8 _rtw_mi_scan_abort(_adapter *adapter, void *data) +{ + bool bwait = *(bool *)data; + + if (bwait) + rtw_scan_abort(adapter); + else + rtw_scan_abort_no_wait(adapter); + + return _TRUE; +} +void rtw_mi_scan_abort(_adapter *adapter, bool bwait) +{ + bool in_data = bwait; + + _rtw_mi_process(adapter, _FALSE, &in_data, _rtw_mi_scan_abort); + +} +void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait) +{ + bool in_data = bwait; + + _rtw_mi_process(adapter, _TRUE, &in_data, _rtw_mi_scan_abort); +} + +static u8 _rtw_mi_start_drv_threads(_adapter *adapter, void *data) +{ + rtw_start_drv_threads(adapter); + return _TRUE; +} +void rtw_mi_start_drv_threads(_adapter *adapter) +{ + _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_start_drv_threads); +} +void rtw_mi_buddy_start_drv_threads(_adapter *adapter) +{ + _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_start_drv_threads); +} + +static u8 _rtw_mi_stop_drv_threads(_adapter *adapter, void *data) +{ + rtw_stop_drv_threads(adapter); + return _TRUE; +} +void rtw_mi_stop_drv_threads(_adapter *adapter) +{ + _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_stop_drv_threads); +} +void rtw_mi_buddy_stop_drv_threads(_adapter *adapter) +{ + _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_stop_drv_threads); +} + +static u8 _rtw_mi_cancel_all_timer(_adapter *adapter, void *data) +{ + rtw_cancel_all_timer(adapter); + return _TRUE; +} +void rtw_mi_cancel_all_timer(_adapter *adapter) +{ + _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_cancel_all_timer); +} +void rtw_mi_buddy_cancel_all_timer(_adapter *adapter) +{ + _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_cancel_all_timer); +} + +static u8 _rtw_mi_reset_drv_sw(_adapter *adapter, void *data) +{ + rtw_reset_drv_sw(adapter); + return _TRUE; +} +void rtw_mi_reset_drv_sw(_adapter *adapter) +{ + _rtw_mi_process_without_schk(adapter, _FALSE, NULL, _rtw_mi_reset_drv_sw); +} +void rtw_mi_buddy_reset_drv_sw(_adapter *adapter) +{ + _rtw_mi_process_without_schk(adapter, _TRUE, NULL, _rtw_mi_reset_drv_sw); +} + +static u8 _rtw_mi_intf_start(_adapter *adapter, void *data) +{ + rtw_intf_start(adapter); + return _TRUE; +} +void rtw_mi_intf_start(_adapter *adapter) +{ + _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_start); +} +void rtw_mi_buddy_intf_start(_adapter *adapter) +{ + _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_start); +} + +static u8 _rtw_mi_intf_stop(_adapter *adapter, void *data) +{ + rtw_intf_stop(adapter); + return _TRUE; +} +void rtw_mi_intf_stop(_adapter *adapter) +{ + _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_intf_stop); +} +void rtw_mi_buddy_intf_stop(_adapter *adapter) +{ + _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_intf_stop); +} + +static u8 _rtw_mi_suspend_free_assoc_resource(_adapter *padapter, void *data) +{ + return rtw_suspend_free_assoc_resource(padapter); +} +void rtw_mi_suspend_free_assoc_resource(_adapter *adapter) +{ + _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_suspend_free_assoc_resource); +} +void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter) +{ + _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_suspend_free_assoc_resource); +} + +static u8 _rtw_mi_is_scan_deny(_adapter *adapter, void *data) +{ + return rtw_is_scan_deny(adapter); +} + +u8 rtw_mi_is_scan_deny(_adapter *adapter) +{ + return _rtw_mi_process(adapter, _FALSE, NULL, _rtw_mi_is_scan_deny); + +} +u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter) +{ + return _rtw_mi_process(adapter, _TRUE, NULL, _rtw_mi_is_scan_deny); +} + + +struct nulldata_param { + unsigned char *da; + unsigned int power_mode; + int try_cnt; + int wait_ms; +}; + +static u8 _rtw_mi_issue_nulldata(_adapter *padapter, void *data) +{ + struct nulldata_param *pnulldata_param = (struct nulldata_param *)data; + + if (is_client_associated_to_ap(padapter) == _TRUE) { + /* TODO: TDLS peers */ + issue_nulldata(padapter, pnulldata_param->da, pnulldata_param->power_mode, pnulldata_param->try_cnt, pnulldata_param->wait_ms); + return _TRUE; + } + return _FALSE; +} + +u8 rtw_mi_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) +{ + struct nulldata_param nparam; + + nparam.da = da; + nparam.power_mode = power_mode;/*0 or 1*/ + nparam.try_cnt = try_cnt; + nparam.wait_ms = wait_ms; + + return _rtw_mi_process(padapter, _FALSE, &nparam, _rtw_mi_issue_nulldata); +} +u8 rtw_mi_buddy_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) +{ + struct nulldata_param nparam; + + nparam.da = da; + nparam.power_mode = power_mode; + nparam.try_cnt = try_cnt; + nparam.wait_ms = wait_ms; + + return _rtw_mi_process(padapter, _TRUE, &nparam, _rtw_mi_issue_nulldata); +} + +static u8 _rtw_mi_beacon_update(_adapter *padapter, void *data) +{ + struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + + if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE + && check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) { + RTW_INFO(ADPT_FMT"-WIFI_FW_AP_STATE - update_beacon\n", ADPT_ARG(padapter)); + update_beacon(padapter, 0, NULL, _TRUE); + } + return _TRUE; +} + +void rtw_mi_beacon_update(_adapter *padapter) +{ + _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_beacon_update); +} + +void rtw_mi_buddy_beacon_update(_adapter *padapter) +{ + _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_beacon_update); +} + +static u8 _rtw_mi_hal_dump_macaddr(_adapter *padapter, void *data) +{ + u8 mac_addr[ETH_ALEN] = {0}; + + rtw_hal_get_macaddr_port(padapter, mac_addr); + RTW_INFO(ADPT_FMT"MAC Address ="MAC_FMT"\n", ADPT_ARG(padapter), MAC_ARG(mac_addr)); + return _TRUE; +} +void rtw_mi_hal_dump_macaddr(_adapter *padapter) +{ + _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_hal_dump_macaddr); +} +void rtw_mi_buddy_hal_dump_macaddr(_adapter *padapter) +{ + _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_hal_dump_macaddr); +} + +static u8 _rtw_mi_xmit_tasklet_schedule(_adapter *padapter, void *data) +{ + if (rtw_txframes_pending(padapter)) { + /* try to deal with the pending packets */ + tasklet_hi_schedule(&(padapter->xmitpriv.xmit_tasklet)); + } + return _TRUE; +} +void rtw_mi_xmit_tasklet_schedule(_adapter *padapter) +{ + _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_xmit_tasklet_schedule); +} +void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter) +{ + _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_xmit_tasklet_schedule); +} + +u8 _rtw_mi_busy_traffic_check(_adapter *padapter, void *data) +{ + u32 passtime; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + bool check_sc_interval = *(bool *)data; + + if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) { + if (check_sc_interval) { + /* Miracast can't do AP scan*/ + passtime = rtw_get_passing_time_ms(pmlmepriv->lastscantime); + pmlmepriv->lastscantime = rtw_get_current_time(); + if (passtime > BUSY_TRAFFIC_SCAN_DENY_PERIOD) { + RTW_INFO(ADPT_FMT" bBusyTraffic == _TRUE\n", ADPT_ARG(padapter)); + return _TRUE; + } + } else + return _TRUE; + } + + return _FALSE; +} + +u8 rtw_mi_busy_traffic_check(_adapter *padapter, bool check_sc_interval) +{ + bool in_data = check_sc_interval; + + return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_busy_traffic_check); +} +u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter, bool check_sc_interval) +{ + bool in_data = check_sc_interval; + + return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_busy_traffic_check); +} +static u8 _rtw_mi_check_mlmeinfo_state(_adapter *padapter, void *data) +{ + u32 state = *(u32 *)data; + struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + + /*if (mlmeext_msr(mlmeext) == state)*/ + if (check_mlmeinfo_state(mlmeext, state)) + return _TRUE; + else + return _FALSE; +} + +u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state) +{ + u32 in_data = state; + + return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_mlmeinfo_state); +} + +u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state) +{ + u32 in_data = state; + + return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_mlmeinfo_state); +} + + +static u8 _rtw_mi_check_fwstate(_adapter *padapter, void *data) +{ + u8 ret = _FALSE; + + sint state = *(sint *)data; + + if ((state == WIFI_FW_NULL_STATE) && + (padapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE)) + ret = _TRUE; + else if (_TRUE == check_fwstate(&padapter->mlmepriv, state)) + ret = _TRUE; + return ret; +} +u8 rtw_mi_check_fwstate(_adapter *padapter, sint state) +{ + sint in_data = state; + + return _rtw_mi_process(padapter, _FALSE, &in_data, _rtw_mi_check_fwstate); +} +u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state) +{ + sint in_data = state; + + return _rtw_mi_process(padapter, _TRUE, &in_data, _rtw_mi_check_fwstate); +} + +static u8 _rtw_mi_traffic_statistics(_adapter *padapter , void *data) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + /* Tx */ + pdvobjpriv->traffic_stat.tx_bytes += padapter->xmitpriv.tx_bytes; + pdvobjpriv->traffic_stat.tx_pkts += padapter->xmitpriv.tx_pkts; + pdvobjpriv->traffic_stat.tx_drop += padapter->xmitpriv.tx_drop; + + /* Rx */ + pdvobjpriv->traffic_stat.rx_bytes += padapter->recvpriv.rx_bytes; + pdvobjpriv->traffic_stat.rx_pkts += padapter->recvpriv.rx_pkts; + pdvobjpriv->traffic_stat.rx_drop += padapter->recvpriv.rx_drop; + return _TRUE; +} +u8 rtw_mi_traffic_statistics(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_traffic_statistics); +} + +static u8 _rtw_mi_check_miracast_enabled(_adapter *padapter , void *data) +{ + return is_miracast_enabled(padapter); +} +u8 rtw_mi_check_miracast_enabled(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_check_miracast_enabled); +} + +static u8 _rtw_mi_dynamic_check_timer_handlder(_adapter *adapter, void *data) +{ + rtw_iface_dynamic_check_timer_handlder(adapter); + return _TRUE; +} +u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_check_timer_handlder); +} + +static u8 _rtw_mi_dynamic_chk_wk_hdl(_adapter *adapter, void *data) +{ + rtw_iface_dynamic_chk_wk_hdl(adapter); + return _TRUE; +} +u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_dynamic_chk_wk_hdl); +} + +static u8 _rtw_mi_os_xmit_schedule(_adapter *adapter, void *data) +{ + rtw_os_xmit_schedule(adapter); + return _TRUE; +} +u8 rtw_mi_os_xmit_schedule(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_os_xmit_schedule); +} +u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _TRUE, NULL, _rtw_mi_os_xmit_schedule); +} + +static u8 _rtw_mi_report_survey_event(_adapter *adapter, void *data) +{ + union recv_frame *precv_frame = (union recv_frame *)data; + + report_survey_event(adapter, precv_frame); + return _TRUE; +} +u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame) +{ + return _rtw_mi_process(padapter, _FALSE, precv_frame, _rtw_mi_report_survey_event); +} + +static u8 _rtw_mi_tx_beacon_hdl(_adapter *adapter, void *data) +{ + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE + && check_fwstate(&adapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE + ) { + adapter->mlmepriv.update_bcn = _TRUE; + } + return _TRUE; +} +u8 rtw_mi_tx_beacon_hdl(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_tx_beacon_hdl); +} + +static u8 _rtw_mi_stay_in_p2p_mode(_adapter *adapter, void *data) +{ + struct wifidirect_info *pwdinfo = &(adapter->wdinfo); + + if (rtw_p2p_role(pwdinfo) != P2P_ROLE_DISABLE) + return _TRUE; + return _FALSE; +} +u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter) +{ + return _rtw_mi_process(padapter, _FALSE, NULL, _rtw_mi_stay_in_p2p_mode); +} + +/*API be created temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/ +_adapter *rtw_mi_get_ap_adapter(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + int i; + _adapter *iface = NULL; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE) + break; + + } + return iface; +} diff --git a/drivers/staging/rtl8821ce/core/rtw_mlme.c b/drivers/staging/rtl8821ce/core/rtw_mlme.c new file mode 100644 index 000000000000..778790acda72 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_mlme.c @@ -0,0 +1,3606 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MLME_C_ + +#include <hal_data.h> + +extern void indicate_wx_scan_complete_event(_adapter *padapter); +extern u8 rtw_do_join(_adapter *padapter); + +void rtw_init_mlme_timer(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + rtw_init_timer(&(pmlmepriv->assoc_timer), padapter, rtw_join_timeout_handler, padapter); + rtw_init_timer(&(pmlmepriv->scan_to_timer), padapter, rtw_scan_timeout_handler, padapter); + + + +} + +sint _rtw_init_mlme_priv(_adapter *padapter) +{ + sint i; + u8 *pbuf; + struct wlan_network *pnetwork; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + sint res = _SUCCESS; + + /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ + /* _rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); */ + + /*qos_priv*/ + /*pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable;*/ + + /*ht_priv*/ + pmlmepriv->htpriv.ampdu_enable = _FALSE;/*set to disabled*/ + + pmlmepriv->nic_hdl = (u8 *)padapter; + + pmlmepriv->pscanned = NULL; + /*pmlmepriv->fw_state = WIFI_STATION_STATE; */ /*Must sync with rtw_wdev_alloc()*/ + /*init_fwstate(pmlmepriv, WIFI_STATION_STATE);*/ + init_fwstate(pmlmepriv, WIFI_NULL_STATE);/*assigned interface role(STA/AP) must after execute set_opmode*/ + + /* wdev->iftype = NL80211_IFTYPE_STATION*/ + pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown; + pmlmepriv->scan_mode = SCAN_ACTIVE; /* 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) */ + + _rtw_spinlock_init(&(pmlmepriv->lock)); + _rtw_init_queue(&(pmlmepriv->free_bss_pool)); + _rtw_init_queue(&(pmlmepriv->scanned_queue)); + + set_scanned_network_val(pmlmepriv, 0); + + _rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID)); + + pbuf = rtw_zvmalloc(MAX_BSS_CNT * (sizeof(struct wlan_network))); + + if (pbuf == NULL) { + res = _FAIL; + goto exit; + } + pmlmepriv->free_bss_buf = pbuf; + + pnetwork = (struct wlan_network *)pbuf; + + for (i = 0; i < MAX_BSS_CNT; i++) { + _rtw_init_listhead(&(pnetwork->list)); + + rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue)); + + pnetwork++; + } + + /* allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf */ + + rtw_clear_scan_deny(padapter); + +#define RTW_ROAM_SCAN_RESULT_EXP_MS (5*1000) +#define RTW_ROAM_RSSI_DIFF_TH 10 +#define RTW_ROAM_SCAN_INTERVAL_MS (10*1000) +#define RTW_ROAM_RSSI_THRESHOLD 70 + + pmlmepriv->roam_flags = 0 + | RTW_ROAM_ON_EXPIRED + | RTW_ROAM_ON_RESUME +#ifdef CONFIG_LAYER2_ROAMING_ACTIVE + | RTW_ROAM_ACTIVE +#endif + ; + + pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS; + pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH; + pmlmepriv->roam_scan_int_ms = RTW_ROAM_SCAN_INTERVAL_MS; + pmlmepriv->roam_rssi_threshold = RTW_ROAM_RSSI_THRESHOLD; + + rtw_init_mlme_timer(padapter); + +exit: + + return res; +} + +void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv); +void rtw_mfree_mlme_priv_lock(struct mlme_priv *pmlmepriv) +{ + _rtw_spinlock_free(&pmlmepriv->lock); + _rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock)); + _rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock)); +} + +static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen) +{ + if (*ppie) { + rtw_mfree(*ppie, *plen); + *plen = 0; + *ppie = NULL; + } +} + +void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv) +{ + rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); + rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len); + + rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len); + + +} + + +void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) +{ + if (NULL == pmlmepriv) { + rtw_warn_on(1); + goto exit; + } + rtw_free_mlme_priv_ie_data(pmlmepriv); + + if (pmlmepriv) { + rtw_mfree_mlme_priv_lock(pmlmepriv); + + if (pmlmepriv->free_bss_buf) + rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network)); + } +exit: + return; +} + +sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) +{ + _irqL irqL; + + if (pnetwork == NULL) + goto exit; + + _enter_critical_bh(&queue->lock, &irqL); + + rtw_list_insert_tail(&pnetwork->list, &queue->queue); + + _exit_critical_bh(&queue->lock, &irqL); + +exit: + + return _SUCCESS; +} + +/* +struct wlan_network *_rtw_dequeue_network(_queue *queue) +{ + _irqL irqL; + + struct wlan_network *pnetwork; + + _enter_critical_bh(&queue->lock, &irqL); + + if (_rtw_queue_empty(queue) == _TRUE) + + pnetwork = NULL; + + else + { + pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list); + + rtw_list_delete(&(pnetwork->list)); + } + + _exit_critical_bh(&queue->lock, &irqL); + + return pnetwork; +} +*/ + +struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue *free_queue) */ +{ + _irqL irqL; + struct wlan_network *pnetwork; + _queue *free_queue = &pmlmepriv->free_bss_pool; + _list *plist = NULL; + + _enter_critical_bh(&free_queue->lock, &irqL); + + if (_rtw_queue_empty(free_queue) == _TRUE) { + pnetwork = NULL; + goto exit; + } + plist = get_next(&(free_queue->queue)); + + pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list); + + rtw_list_delete(&pnetwork->list); + + pnetwork->network_type = 0; + pnetwork->fixed = _FALSE; + pnetwork->last_scanned = rtw_get_current_time(); + pnetwork->aid = 0; + pnetwork->join_res = 0; + + pmlmepriv->num_of_scanned++; + +exit: + _exit_critical_bh(&free_queue->lock, &irqL); + + return pnetwork; +} + +void _rtw_free_network(struct mlme_priv *pmlmepriv , struct wlan_network *pnetwork, u8 isfreeall) +{ + u32 delta_time; + u32 lifetime = SCANQUEUE_LIFETIME; + _irqL irqL; + _queue *free_queue = &(pmlmepriv->free_bss_pool); + + if (pnetwork == NULL) + goto exit; + + if (pnetwork->fixed == _TRUE) + goto exit; + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + lifetime = 1; + + if (!isfreeall) { + delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned); + if (delta_time < lifetime) /* unit:msec */ + goto exit; + } + + _enter_critical_bh(&free_queue->lock, &irqL); + + rtw_list_delete(&(pnetwork->list)); + + rtw_list_insert_tail(&(pnetwork->list), &(free_queue->queue)); + + pmlmepriv->num_of_scanned--; + + /* RTW_INFO("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); */ + + _exit_critical_bh(&free_queue->lock, &irqL); + +exit: + return; +} + +void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork) +{ + + _queue *free_queue = &(pmlmepriv->free_bss_pool); + + if (pnetwork == NULL) + goto exit; + + if (pnetwork->fixed == _TRUE) + goto exit; + + /* _enter_critical(&free_queue->lock, &irqL); */ + + rtw_list_delete(&(pnetwork->list)); + + rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue)); + + pmlmepriv->num_of_scanned--; + + /* _exit_critical(&free_queue->lock, &irqL); */ + +exit: + return; +} + +/* + return the wlan_network with the matching addr + + Shall be calle under atomic context... to avoid possible racing condition... +*/ +struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) +{ + + /* _irqL irqL; */ + _list *phead, *plist; + struct wlan_network *pnetwork = NULL; + u8 zero_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; + + if (_rtw_memcmp(zero_addr, addr, ETH_ALEN)) { + pnetwork = NULL; + goto exit; + } + + /* _enter_critical_bh(&scanned_queue->lock, &irqL); */ + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (plist != phead) { + pnetwork = LIST_CONTAINOR(plist, struct wlan_network , list); + + if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) + break; + + plist = get_next(plist); + } + + if (plist == phead) + pnetwork = NULL; + + /* _exit_critical_bh(&scanned_queue->lock, &irqL); */ + +exit: + + return pnetwork; + +} + +void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) +{ + _irqL irqL; + _list *phead, *plist; + struct wlan_network *pnetwork; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _queue *scanned_queue = &pmlmepriv->scanned_queue; + + _enter_critical_bh(&scanned_queue->lock, &irqL); + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + plist = get_next(plist); + + _rtw_free_network(pmlmepriv, pnetwork, isfreeall); + + } + + _exit_critical_bh(&scanned_queue->lock, &irqL); + +} + +sint rtw_if_up(_adapter *padapter) +{ + + sint res; + + if (RTW_CANNOT_RUN(padapter) || + (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) { + res = _FALSE; + } else + res = _TRUE; + + return res; +} + +void rtw_generate_random_ibss(u8 *pibss) +{ + *((u32 *)(&pibss[2])) = rtw_random32(); + pibss[0] = 0x02; /* in ad-hoc mode local bit must set to 1 */ + pibss[1] = 0x11; + pibss[2] = 0x87; +} + +u8 *rtw_get_capability_from_ie(u8 *ie) +{ + return ie + 8 + 2; +} + +u16 rtw_get_capability(WLAN_BSSID_EX *bss) +{ + u16 val; + + _rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2); + + return le16_to_cpu(val); +} + +u8 *rtw_get_beacon_interval_from_ie(u8 *ie) +{ + return ie + 8; +} + +int rtw_init_mlme_priv(_adapter *padapter) /* (struct mlme_priv *pmlmepriv) */ +{ + int res; + res = _rtw_init_mlme_priv(padapter);/* (pmlmepriv); */ + return res; +} + +void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv) +{ + _rtw_free_mlme_priv(pmlmepriv); +} + +/* +static struct wlan_network *rtw_dequeue_network(_queue *queue) +{ + struct wlan_network *pnetwork; + pnetwork = _rtw_dequeue_network(queue); + return pnetwork; +} +*/ + +struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv); +struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv) /* (_queue *free_queue) */ +{ + struct wlan_network *pnetwork; + pnetwork = _rtw_alloc_network(pmlmepriv); + return pnetwork; +} + +void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork); +void rtw_free_network_nolock(_adapter *padapter, struct wlan_network *pnetwork) +{ + _rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork); +} + +void rtw_free_network_queue(_adapter *dev, u8 isfreeall) +{ + _rtw_free_network_queue(dev, isfreeall); +} + +/* + return the wlan_network with the matching addr + + Shall be calle under atomic context... to avoid possible racing condition... +*/ +struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr) +{ + struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr); + + return pnetwork; +} + +int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork) +{ + int ret = _TRUE; + struct security_priv *psecuritypriv = &adapter->securitypriv; + + if ((psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_) && + (pnetwork->network.Privacy == 0)) + ret = _FALSE; + else if ((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_) && + (pnetwork->network.Privacy == 1)) + ret = _FALSE; + else + ret = _TRUE; + + return ret; + +} + +inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) +{ + return (a->Ssid.SsidLength == b->Ssid.SsidLength) + && _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength) == _TRUE; +} + +int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) +{ + u16 s_cap, d_cap; + + if (rtw_bug_check(dst, src, &s_cap, &d_cap) == _FALSE) + return _FALSE; + + _rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2); + _rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2); + + s_cap = le16_to_cpu(s_cap); + d_cap = le16_to_cpu(d_cap); + + if ((feature == 1) && /* 1: P2P supported */ + (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE) + ) + return _TRUE; + + return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && + /* (src->Configuration.DSConfig == dst->Configuration.DSConfig) && */ + ((_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && + ((_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) && + ((s_cap & WLAN_CAPABILITY_IBSS) == + (d_cap & WLAN_CAPABILITY_IBSS)) && + ((s_cap & WLAN_CAPABILITY_BSS) == + (d_cap & WLAN_CAPABILITY_BSS))); + +} + +struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network) +{ + _list *phead, *plist; + struct wlan_network *found = NULL; + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (plist != phead) { + found = LIST_CONTAINOR(plist, struct wlan_network , list); + + if (is_same_network(&network->network, &found->network, 0)) + break; + + plist = get_next(plist); + } + + if (plist == phead) + found = NULL; + + return found; +} + +struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue) +{ + _list *plist, *phead; + + struct wlan_network *pwlan = NULL; + struct wlan_network *oldest = NULL; + phead = get_list_head(scanned_queue); + + plist = get_next(phead); + + while (1) { + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pwlan = LIST_CONTAINOR(plist, struct wlan_network, list); + + if (pwlan->fixed != _TRUE) { + if (oldest == NULL || time_after(oldest->last_scanned, pwlan->last_scanned)) + oldest = pwlan; + } + + plist = get_next(plist); + } + return oldest; + +} + +void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, + _adapter *padapter, bool update_ie) +{ + u8 ss_ori = dst->PhyInfo.SignalStrength; + u8 sq_ori = dst->PhyInfo.SignalQuality; + long rssi_ori = dst->Rssi; + + u8 ss_smp = src->PhyInfo.SignalStrength; + u8 sq_smp = src->PhyInfo.SignalQuality; + long rssi_smp = src->Rssi; + + u8 ss_final; + u8 sq_final; + long rssi_final; + + + + /* The rule below is 1/5 for sample value, 4/5 for history value */ + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) { + /* Take the recvpriv's value for the connected AP*/ + ss_final = padapter->recvpriv.signal_strength; + sq_final = padapter->recvpriv.signal_qual; + /* the rssi value here is undecorated, and will be used for antenna diversity */ + if (sq_smp != 101) /* from the right channel */ + rssi_final = (src->Rssi + dst->Rssi * 4) / 5; + else + rssi_final = rssi_ori; + } else { + if (sq_smp != 101) { /* from the right channel */ + ss_final = ((u32)(src->PhyInfo.SignalStrength) + (u32)(dst->PhyInfo.SignalStrength) * 4) / 5; + sq_final = ((u32)(src->PhyInfo.SignalQuality) + (u32)(dst->PhyInfo.SignalQuality) * 4) / 5; + rssi_final = (src->Rssi + dst->Rssi * 4) / 5; + } else { + /* bss info not receving from the right channel, use the original RX signal infos */ + ss_final = dst->PhyInfo.SignalStrength; + sq_final = dst->PhyInfo.SignalQuality; + rssi_final = dst->Rssi; + } + + } + + if (update_ie) { + dst->Reserved[0] = src->Reserved[0]; + dst->Reserved[1] = src->Reserved[1]; + _rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src)); + } + + dst->PhyInfo.SignalStrength = ss_final; + dst->PhyInfo.SignalQuality = sq_final; + dst->Rssi = rssi_final; + +} + +static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + + rtw_bug_check(&(pmlmepriv->cur_network.network), + &(pmlmepriv->cur_network.network), + &(pmlmepriv->cur_network.network), + &(pmlmepriv->cur_network.network)); + + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) { + + /* if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) */ + { + update_network(&(pmlmepriv->cur_network.network), pnetwork, adapter, _TRUE); + rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof(NDIS_802_11_FIXED_IEs), + pmlmepriv->cur_network.network.IELength); + } + } + +} + +/* + +Caller must hold pmlmepriv->lock first. + +*/ +void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) +{ + _irqL irqL; + _list *plist, *phead; + ULONG bssid_ex_sz; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct wifidirect_info *pwdinfo = &(adapter->wdinfo); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + struct wlan_network *oldest = NULL; + int target_find = 0; + u8 feature = 0; + + _enter_critical_bh(&queue->lock, &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + feature = 1; /* p2p enable */ + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + rtw_bug_check(pnetwork, pnetwork, pnetwork, pnetwork); + + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && + (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) == _TRUE)) { + target_find = 1; + break; + } + + if (is_same_network(&(pnetwork->network), target, feature)) { + target_find = 1; + break; + } + + if (rtw_roam_flags(adapter)) { + /* TODO: don't select netowrk in the same ess as oldest if it's new enough*/ + } +#ifdef CONFIG_RSSI_PRIORITY + if ((oldest == NULL) || (pnetwork->network.PhyInfo.SignalStrength < oldest->network.PhyInfo.SignalStrength)) + oldest = pnetwork; +#else + if (oldest == NULL || time_after(oldest->last_scanned, pnetwork->last_scanned)) + oldest = pnetwork; +#endif + plist = get_next(plist); + + } + + /* If we didn't find a match, then get a new network slot to initialize + * with this beacon's information */ + /* if (rtw_end_of_queue_search(phead,plist)== _TRUE) { */ + if (!target_find) { + if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) { + /* If there are no more slots, expire the oldest */ + /* list_del_init(&oldest->list); */ + pnetwork = oldest; + if (pnetwork == NULL) { + goto exit; + } +#ifdef CONFIG_RSSI_PRIORITY + RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue (rssi:%ld , ss:%d)\n", + __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Rssi, pnetwork->network.PhyInfo.SignalStrength); +#else + RTW_DBG("%s => ssid:%s ,bssid:"MAC_FMT" will be deleted from scanned_queue\n", + __func__, pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); +#endif + + _rtw_memcpy(&(pnetwork->network), target, get_WLAN_BSSID_EX_sz(target)); + /* pnetwork->last_scanned = rtw_get_current_time(); */ + /* variable initialize */ + pnetwork->fixed = _FALSE; + pnetwork->last_scanned = rtw_get_current_time(); + + pnetwork->network_type = 0; + pnetwork->aid = 0; + pnetwork->join_res = 0; + + /* bss info not receving from the right channel */ + if (pnetwork->network.PhyInfo.SignalQuality == 101) + pnetwork->network.PhyInfo.SignalQuality = 0; + } else { + /* Otherwise just pull from the free list */ + + pnetwork = rtw_alloc_network(pmlmepriv); /* will update scan_time */ + + if (pnetwork == NULL) { + goto exit; + } + + bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); + target->Length = bssid_ex_sz; + _rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz); + + pnetwork->last_scanned = rtw_get_current_time(); + + /* bss info not receving from the right channel */ + if (pnetwork->network.PhyInfo.SignalQuality == 101) + pnetwork->network.PhyInfo.SignalQuality = 0; + + rtw_list_insert_tail(&(pnetwork->list), &(queue->queue)); + + } + } else { + /* we have an entry and we are going to update it. But this entry may + * be already expired. In this case we do the same as we found a new + * net and call the new_net handler + */ + bool update_ie = _TRUE; + + pnetwork->last_scanned = rtw_get_current_time(); + + /* target.Reserved[0]==1, means that scaned network is a bcn frame. */ + if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == 1)) + update_ie = _FALSE; + + /* probe resp(3) > beacon(1) > probe req(2) */ + if ((target->Reserved[0] != 2) && + (target->Reserved[0] >= pnetwork->network.Reserved[0]) + ) + update_ie = _TRUE; + else + update_ie = _FALSE; + + update_network(&(pnetwork->network), target, adapter, update_ie); + } + +exit: + _exit_critical_bh(&queue->lock, &irqL); + +} + +void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); +void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv); + /* _queue *queue = &(pmlmepriv->scanned_queue); */ + + /* _enter_critical_bh(&queue->lock, &irqL); */ + + if (adapter->registrypriv.wifi_spec == 0) + rtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO); + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + rtw_bss_ex_del_wfd_ie(pnetwork); + + update_current_network(adapter, pnetwork); + + rtw_update_scanned_network(adapter, pnetwork); + + /* _exit_critical_bh(&queue->lock, &irqL); */ + +} + +/* select the desired network based on the capability of the (i)bss. + * check items: (1) security + * (2) network_type + * (3) WMM + * (4) HT + * (5) others */ +int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork); +int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) +{ + struct security_priv *psecuritypriv = &adapter->securitypriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u32 desired_encmode; + u32 privacy; + + /* u8 wps_ie[512]; */ + uint wps_ielen; + + int bselected = _TRUE; + + desired_encmode = psecuritypriv->ndisencryptstatus; + privacy = pnetwork->network.Privacy; + + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + if (rtw_get_wps_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, pnetwork->network.IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen) != NULL) + return _TRUE; + else + return _FALSE; + } + if (adapter->registrypriv.wifi_spec == 1) { /* for correct flow of 8021X to do.... */ + u8 *p = NULL; + uint ie_len = 0; + + if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0)) + bselected = _FALSE; + + if (psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { + p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len > 0) + bselected = _TRUE; + else + bselected = _FALSE; + } + } + + if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) { + RTW_INFO("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy); + bselected = _FALSE; + } + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) { + if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) + bselected = _FALSE; + } + + return bselected; +} + +/* TODO: Perry : For Power Management */ +void rtw_atimdone_event_callback(_adapter *adapter , u8 *pbuf) +{ + + return; +} + +void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL; + u32 len; + WLAN_BSSID_EX *pnetwork; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + + pnetwork = (WLAN_BSSID_EX *)pbuf; + + len = get_WLAN_BSSID_EX_sz(pnetwork); + if (len > (sizeof(WLAN_BSSID_EX))) { + return; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + /* update IBSS_network 's timestamp */ + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) { + if (_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) { + struct wlan_network *ibss_wlan = NULL; + _irqL irqL; + + _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); + if (ibss_wlan) { + _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto exit; + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + } + } + + /* lock pmlmepriv->lock when you accessing network_q */ + if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE) { + if (pnetwork->Ssid.Ssid[0] == 0) + pnetwork->Ssid.SsidLength = 0; + rtw_add_network(adapter, pnetwork); + } + +exit: + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + return; +} + +void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + +#ifdef CONFIG_MLME_EXT + mlmeext_surveydone_event_callback(adapter); +#endif + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + if (pmlmepriv->wps_probe_req_ie) { + u32 free_len = pmlmepriv->wps_probe_req_ie_len; + pmlmepriv->wps_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); + pmlmepriv->wps_probe_req_ie = NULL; + } + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _FALSE) { + RTW_INFO(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + /* rtw_warn_on(1); */ + } + + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + _cancel_timer_ex(&pmlmepriv->scan_to_timer); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + rtw_set_signal_stat_timer(&adapter->recvpriv); + + if (pmlmepriv->to_join == _TRUE) { + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { + if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + + if (rtw_select_and_join_from_scanned_queue(pmlmepriv) == _SUCCESS) + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + else { + WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network); + u8 *pibss = adapter->registrypriv.dev_network.MacAddress; + + /* pmlmepriv->fw_state ^= _FW_UNDER_SURVEY; */ /* because don't set assoc_timer */ + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + + _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(adapter); + rtw_generate_random_ibss(pibss); + + /*pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE;*/ + init_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + + if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) + RTW_ERR("rtw_create_ibss_cmd FAIL\n"); + + pmlmepriv->to_join = _FALSE; + } + } + } else { + int s_ret; + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + pmlmepriv->to_join = _FALSE; + s_ret = rtw_select_and_join_from_scanned_queue(pmlmepriv); + if (_SUCCESS == s_ret) + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + else if (s_ret == 2) { /* there is no need to wait for join */ + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + rtw_indicate_connect(adapter); + } else { + RTW_INFO("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter)); + + if (rtw_to_roam(adapter) != 0) { + if (rtw_dec_to_roam(adapter) == 0 + || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1, NULL, 0) + ) { + rtw_set_to_roam(adapter, 0); + rtw_free_assoc_resources(adapter, 1); + rtw_indicate_disconnect(adapter, 0, _FALSE); + } else + pmlmepriv->to_join = _TRUE; + } else + rtw_indicate_disconnect(adapter, 0, _FALSE); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + } + } + } else { + if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) + && check_fwstate(pmlmepriv, _FW_LINKED)) { + if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { + receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); + } + } + } + } + + /* RTW_INFO("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); */ + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0); + + rtw_mi_os_xmit_schedule(adapter); + +#ifdef CONFIG_DRVEXT_MODULE_WSC + drvext_surveydone_callback(&adapter->drvextpriv); +#endif + + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + if (pmlmeext->sitesurvey_res.bss_cnt == 0) { + /* rtw_hal_sreset_reset(adapter); */ + } + } + + + rtw_indicate_scan_done(adapter, _FALSE); + + +} + +void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf) +{ + +} + +void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf) +{ + +} + +static void free_scanqueue(struct mlme_priv *pmlmepriv) +{ + _irqL irqL, irqL0; + _queue *free_queue = &pmlmepriv->free_bss_pool; + _queue *scan_queue = &pmlmepriv->scanned_queue; + _list *plist, *phead, *ptemp; + + _enter_critical_bh(&scan_queue->lock, &irqL0); + _enter_critical_bh(&free_queue->lock, &irqL); + + phead = get_list_head(scan_queue); + plist = get_next(phead); + + while (plist != phead) { + ptemp = get_next(plist); + rtw_list_delete(plist); + rtw_list_insert_tail(plist, &free_queue->queue); + plist = ptemp; + pmlmepriv->num_of_scanned--; + } + + _exit_critical_bh(&free_queue->lock, &irqL); + _exit_critical_bh(&scan_queue->lock, &irqL0); + +} + +void rtw_reset_rx_info(struct debug_priv *pdbgpriv) +{ + pdbgpriv->dbg_rx_ampdu_drop_count = 0; + pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0; + pdbgpriv->dbg_rx_ampdu_loss_count = 0; + pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0; + pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0; +} + +/* +*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock +*/ +void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) +{ + _irqL irqL; + struct wlan_network *pwlan = NULL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct dvobj_priv *psdpriv = adapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + RTW_INFO("%s-"ADPT_FMT" tgt_network MacAddress=" MAC_FMT"ssid=%s\n", + __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + struct sta_info *psta; + + psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); + + { + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(adapter, psta); + } + + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + + } + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { + struct sta_info *psta; + + rtw_free_all_stainfo(adapter); + + psta = rtw_get_bcmc_stainfo(adapter); + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(adapter, psta); + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + + rtw_init_bcmc_stainfo(adapter); + } + + if (lock_scanned_queue) + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + pwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network); + if ((pwlan) && (!check_fwstate(pmlmepriv, WIFI_UNDER_WPS))) { + pwlan->fixed = _FALSE; + + RTW_INFO("free disconnecting network of scanned_queue\n"); + rtw_free_network_nolock(adapter, pwlan); + if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + rtw_mi_set_scan_deny(adapter, 2000); + /* rtw_clear_scan_deny(adapter); */ + } + } else { + if (pwlan == NULL) + RTW_INFO("free disconnecting network of scanned_queue failed due to pwlan== NULL\n\n"); + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + RTW_INFO("donot free disconnecting network of scanned_queue when WIFI_UNDER_WPS\n\n"); + } + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count == 1)) + /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) { + if (pwlan) + rtw_free_network_nolock(adapter, pwlan); + } + + if (lock_scanned_queue) + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + adapter->securitypriv.key_mask = 0; + + rtw_reset_rx_info(pdbgpriv); + +} + +/* +*rtw_indicate_connect: the caller has to lock pmlmepriv->lock +*/ +void rtw_indicate_connect(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + pmlmepriv->to_join = _FALSE; + + if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { + + set_fwstate(pmlmepriv, _FW_LINKED); + + rtw_led_control(padapter, LED_CTL_LINK); + + { + rtw_os_indicate_connect(padapter); + } + + } + + rtw_set_to_roam(padapter, 0); + if (!check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE)) + rtw_mi_set_scan_deny(padapter, 3000); + +} + +/* +*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock +*/ +void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *wps_ie = NULL; + uint wpsie_len = 0; + + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING | WIFI_UNDER_WPS); + + /* force to clear cur_network_scanned's SELECTED REGISTRAR */ + if (pmlmepriv->cur_network_scanned) { + WLAN_BSSID_EX *current_joined_bss = &(pmlmepriv->cur_network_scanned->network); + if (current_joined_bss) { + wps_ie = rtw_get_wps_ie(current_joined_bss->IEs + _FIXED_IE_LENGTH_, + current_joined_bss->IELength - _FIXED_IE_LENGTH_, NULL, &wpsie_len); + if (wps_ie && wpsie_len > 0) { + u8 *attr = NULL; + u32 attr_len; + attr = rtw_get_wps_attr(wps_ie, wpsie_len, WPS_ATTR_SELECTED_REGISTRAR, + NULL, &attr_len); + if (attr) + *(attr + 4) = 0; + } + } + } + /* RTW_INFO("clear wps when %s\n", __func__); */ + + if (rtw_to_roam(padapter) > 0) + _clr_fwstate_(pmlmepriv, _FW_LINKED); + + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) + || (rtw_to_roam(padapter) <= 0) + ) { + + rtw_os_indicate_disconnect(padapter, reason, locally_generated); + + /* set ips_deny_time to avoid enter IPS before LPS leave */ + rtw_set_ips_deny(padapter, 3000); + + _clr_fwstate_(pmlmepriv, _FW_LINKED); + + rtw_led_control(padapter, LED_CTL_NO_LINK); + + rtw_clear_scan_deny(padapter); + } + + p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); + + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 1); + + +} + +inline void rtw_indicate_scan_done(_adapter *padapter, bool aborted) +{ + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + rtw_os_indicate_scan_done(padapter, aborted); + + if (is_primary_adapter(padapter) + && (_FALSE == adapter_to_pwrctl(padapter)->bInSuspend) + && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE | WIFI_UNDER_LINKING) == _FALSE)) { + struct pwrctrl_priv *pwrpriv; + + pwrpriv = adapter_to_pwrctl(padapter); + rtw_set_ips_deny(padapter, 0); +#ifdef CONFIG_IPS_CHECK_IN_WD + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 1); +#else /* !CONFIG_IPS_CHECK_IN_WD */ + _rtw_set_pwr_state_check_timer(pwrpriv, 1); +#endif /* !CONFIG_IPS_CHECK_IN_WD */ + } +} + +static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) +{ + u32 start; + u32 pass_ms; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + start = rtw_get_current_time(); + + pmlmeext->scan_abort = abort; + + while (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) + && rtw_get_passing_time_ms(start) <= timeout_ms) { + + if (RTW_CANNOT_RUN(adapter)) + break; + + RTW_INFO(FUNC_NDEV_FMT"fw_state=_FW_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev)); + rtw_msleep_os(20); + } + + if (_TRUE == abort) { + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + if (!RTW_CANNOT_RUN(adapter)) + RTW_INFO(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev)); +#ifdef CONFIG_PLATFORM_MSTAR + /*_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);*/ + set_survey_timer(pmlmeext, 0); + mlme_set_scan_to_timer(pmlmepriv, 50); +#endif + rtw_indicate_scan_done(adapter, _TRUE); + } + } + + pmlmeext->scan_abort = _FALSE; + pass_ms = rtw_get_passing_time_ms(start); + + return pass_ms; + +} + +void rtw_scan_wait_completed(_adapter *adapter) +{ + u32 scan_to = SCANNING_TIMEOUT; + + + _rtw_wait_scan_done(adapter, _FALSE, scan_to); +} + +u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms) +{ + return _rtw_wait_scan_done(adapter, _TRUE, timeout_ms); +} + +void rtw_scan_abort_no_wait(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) + pmlmeext->scan_abort = _TRUE; +} + +void rtw_scan_abort(_adapter *adapter) +{ + rtw_scan_abort_timeout(adapter, 200); +} + +static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) +{ + int i; + struct sta_info *bmc_sta, *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress); + if (psta == NULL) + psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress); + + if (psta) { /* update ptarget_sta */ + RTW_INFO("%s\n", __FUNCTION__); + + psta->aid = pnetwork->join_res; + + update_sta_info(padapter, psta); + + /* update station supportRate */ + psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates); + _rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen); + rtw_hal_update_sta_rate_mask(padapter, psta); + + psta->wireless_mode = pmlmeext->cur_wireless_mode; + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + + /* sta mode */ + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); + + /* security related */ + if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { + padapter->securitypriv.binstallGrpkey = _FALSE; + padapter->securitypriv.busetkipkey = _FALSE; + padapter->securitypriv.bgrpkey_handshake = _FALSE; + + psta->ieee8021x_blocked = _TRUE; + psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + + _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof(union Keytype)); + + _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof(union Keytype)); + _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof(union Keytype)); + + _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof(union pn48)); + psta->dot11txpn.val = psta->dot11txpn.val + 1; + _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof(union pn48)); + } + + /* Commented by Albert 2012/07/21 */ + /* When doing the WPS, the wps_ie_len won't equal to 0 */ + /* And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. */ + if (padapter->securitypriv.wps_ie_len != 0) { + psta->ieee8021x_blocked = _TRUE; + padapter->securitypriv.wps_ie_len = 0; + } + + /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */ + /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff */ + /* todo: check if AP can send A-MPDU packets */ + for (i = 0; i < 16 ; i++) { + /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ + preorder_ctrl = &psta->recvreorder_ctrl[i]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->indicate_seq = 0xffff; + preorder_ctrl->wend_b = 0xffff; + preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + } + + bmc_sta = rtw_get_bcmc_stainfo(padapter); + if (bmc_sta) { + for (i = 0; i < 16 ; i++) { + /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ + preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->indicate_seq = 0xffff; + preorder_ctrl->wend_b = 0xffff; + preorder_ctrl->wsize_b = 64;/* max_ampdu_sz; */ /* ex. 32(kbytes) -> wsize_b=32 */ + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + } + } + } + + return psta; + +} + +/* pnetwork : returns from rtw_joinbss_event_callback + * ptarget_wlan: found from scanned_queue */ +static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + + RTW_INFO("%s\n", __FUNCTION__); + + /* why not use ptarget_wlan?? */ + _rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length); + /* some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs */ + cur_network->network.IELength = ptarget_wlan->network.IELength; + _rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ); + + cur_network->aid = pnetwork->join_res; + + rtw_set_signal_stat_timer(&padapter->recvpriv); + padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength; + padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality; + /* the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) */ + padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); + rtw_set_signal_stat_timer(&padapter->recvpriv); + + /* update fw_state */ /* will clr _FW_UNDER_LINKING here indirectly */ + + switch (pnetwork->network.InfrastructureMode) { + case Ndis802_11Infrastructure: + + if (pmlmepriv->fw_state & WIFI_UNDER_WPS) + /*pmlmepriv->fw_state = WIFI_STATION_STATE|WIFI_UNDER_WPS;*/ + init_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_UNDER_WPS); + else + /*pmlmepriv->fw_state = WIFI_STATION_STATE;*/ + init_fwstate(pmlmepriv, WIFI_STATION_STATE); + break; + case Ndis802_11IBSS: + /*pmlmepriv->fw_state = WIFI_ADHOC_STATE;*/ + init_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + break; + default: + /*pmlmepriv->fw_state = WIFI_NULL_STATE;*/ + init_fwstate(pmlmepriv, WIFI_NULL_STATE); + break; + } + + rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof(NDIS_802_11_FIXED_IEs), + (cur_network->network.IELength)); + + rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig); +} + +/* Notes: the fucntion could be > passive_level (the same context as Rx tasklet) + * pnetwork : returns from rtw_joinbss_event_callback + * ptarget_wlan: found from scanned_queue + * if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if "ptarget_sta" & "ptarget_wlan" exist. + * if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist. + * if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL). + */ +/* #define REJOIN */ +void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL, irqL2; + static u8 retry = 0; + struct sta_info *ptarget_sta = NULL, *pcur_sta = NULL; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct wlan_network *pnetwork = (struct wlan_network *)pbuf; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL; + unsigned int the_same_macaddr = _FALSE; + + rtw_get_encrypt_decrypt_from_registrypriv(adapter); + + the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN); + + pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network); + if (pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) { + goto ignore_joinbss_callback; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + + if (pnetwork->join_res > 0) { + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + retry = 0; + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) { + /* s1. find ptarget_wlan */ + if (check_fwstate(pmlmepriv, _FW_LINKED)) { + if (the_same_macaddr == _TRUE) + ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + else { + pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + if (pcur_wlan) + pcur_wlan->fixed = _FALSE; + + pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (pcur_sta) { + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + rtw_free_stainfo(adapter, pcur_sta); + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + } + + ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (ptarget_wlan) + ptarget_wlan->fixed = _TRUE; + } + } + + } else { + ptarget_wlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, pnetwork); + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + if (ptarget_wlan) + ptarget_wlan->fixed = _TRUE; + } + } + + /* s2. update cur_network */ + if (ptarget_wlan) + rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork); + else { + RTW_PRINT("Can't find ptarget_wlan when joinbss_event callback\n"); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto ignore_joinbss_callback; + } + + /* s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode */ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork); + if (ptarget_sta == NULL) { + RTW_ERR("Can't update stainfo when joinbss_event callback\n"); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto ignore_joinbss_callback; + } + } + + /* s4. indicate connect */ + if (MLME_IS_STA(adapter) || MLME_IS_ADHOC(adapter)) { + pmlmepriv->cur_network_scanned = ptarget_wlan; + rtw_indicate_connect(adapter); + } + + /* s5. Cancle assoc_timer */ + _cancel_timer_ex(&pmlmepriv->assoc_timer); + + } else { + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto ignore_joinbss_callback; + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + } else if (pnetwork->join_res == -4) { + rtw_reset_securitypriv(adapter); + _set_timer(&pmlmepriv->assoc_timer, 1); + + /* rtw_free_assoc_resources(adapter, 1); */ + + if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) { + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + } + + } else { /* if join_res < 0 (join fails), then try again */ + + + _set_timer(&pmlmepriv->assoc_timer, 1); + /* rtw_free_assoc_resources(adapter, 1); */ + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + } + +ignore_joinbss_callback: + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf) +{ + struct wlan_network *pnetwork = (struct wlan_network *)pbuf; + + mlmeext_joinbss_event_callback(adapter, pnetwork->join_res); + + rtw_mi_os_xmit_schedule(adapter); + +} + +void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + bool miracast_enabled = 0; + bool miracast_sink = 0; + u8 role = H2C_MSR_ROLE_RSVD; + + if (sta == NULL) { + RTW_PRINT(FUNC_ADPT_FMT" sta is NULL\n" + , FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + return; + } + + if (sta->mac_id >= macid_ctl->num) { + RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" + , FUNC_ADPT_ARG(adapter), sta->mac_id); + rtw_warn_on(1); + return; + } + + if (!rtw_macid_is_used(macid_ctl, sta->mac_id)) { + RTW_PRINT(FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n" + , FUNC_ADPT_ARG(adapter), sta->mac_id); + connected = 0; + rtw_warn_on(1); + } + + if (connected && !rtw_macid_is_bmc(macid_ctl, sta->mac_id)) { + miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter); + miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK); + + if (MLME_IS_STA(adapter)) { + if (MLME_IS_GC(adapter)) + role = H2C_MSR_ROLE_GO; + else + role = H2C_MSR_ROLE_AP; + } else if (MLME_IS_AP(adapter)) { + if (MLME_IS_GO(adapter)) + role = H2C_MSR_ROLE_GC; + else + role = H2C_MSR_ROLE_STA; + } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter)) + role = H2C_MSR_ROLE_ADHOC; + + if (role == H2C_MSR_ROLE_GC + || role == H2C_MSR_ROLE_GO + || role == H2C_MSR_ROLE_TDLS + ) { + if (adapter->wfd_info.rtsp_ctrlport + || adapter->wfd_info.tdls_rtsp_ctrlport + || adapter->wfd_info.peer_rtsp_ctrlport) + rtw_wfd_st_switch(sta, 1); + } + } + + rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter + , connected + , miracast_enabled + , miracast_sink + , role + , sta->mac_id + ); +} + +u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected) +{ + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *cmd_parm; + struct sta_media_status_rpt_cmd_parm *rpt_parm; + u8 res = _SUCCESS; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { + res = _FAIL; + goto exit; + } + + cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (cmd_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + rpt_parm = (struct sta_media_status_rpt_cmd_parm *)rtw_zmalloc(sizeof(struct sta_media_status_rpt_cmd_parm)); + if (rpt_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + rpt_parm->sta = sta; + rpt_parm->connected = connected; + + cmd_parm->ec_id = STA_MSTATUS_RPT_WK_CID; + cmd_parm->type = 0; + cmd_parm->size = sizeof(struct sta_media_status_rpt_cmd_parm); + cmd_parm->pbuf = (u8 *)rpt_parm; + init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + +exit: + return res; +} + +inline void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm) +{ + rtw_sta_media_status_rpt(adapter, parm->sta, parm->connected); +} + +void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL; + struct sta_info *psta; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct stassoc_event *pstassoc = (struct stassoc_event *)pbuf; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct wlan_network *ptarget_wlan = NULL; + + if (rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE) + return; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); + if (psta) { + u8 *passoc_req = NULL; + u32 assoc_req_len = 0; + + rtw_sta_media_status_rpt(adapter, psta, 1); + + + ap_sta_info_defer_update(adapter, psta); + + /* report to upper layer */ + RTW_INFO("indicate_sta_assoc_event to upper layer - hostapd\n"); + rtw_indicate_sta_assoc_event(adapter, psta); + + if (is_wep_enc(adapter->securitypriv.dot11PrivacyAlgrthm)) + rtw_ap_wep_pk_setting(adapter, psta); + } + goto exit; + } + + /* for AD-HOC mode */ + psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); + if (psta == NULL) { + RTW_ERR(FUNC_ADPT_FMT" get no sta_info with "MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pstassoc->macaddr)); + rtw_warn_on(1); + goto exit; + } + + rtw_hal_set_odm_var(adapter, HAL_ODM_STA_INFO, psta, _TRUE); + + rtw_sta_media_status_rpt(adapter, psta, 1); + + if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) + psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm; + + psta->ieee8021x_blocked = _FALSE; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { + if (adapter->stapriv.asoc_sta_count == 2) { + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + pmlmepriv->cur_network_scanned = ptarget_wlan; + if (ptarget_wlan) + ptarget_wlan->fixed = _TRUE; + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + /* a sta + bc/mc_stainfo (not Ibss_stainfo) */ + rtw_indicate_connect(adapter); + } + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + mlmeext_sta_add_event_callback(adapter, psta); + +exit: + return; +} + + + +void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + + RTW_INFO("%s "ADPT_FMT" - mac_id=%d\n", __func__, ADPT_ARG(adapter), mac_id); + + if (mac_id >= 0 && mac_id < macid_ctl->num) { + rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id); + /* + * For safety, prevent from keeping macid sleep. + * If we can sure all power mode enter/leave are paired, + * this check can be removed. + * Lucas@20131113 + */ + /* wakeup macid after disconnect. */ + /*if (MLME_IS_STA(adapter))*/ + rtw_hal_macid_wakeup(adapter, mac_id); + } else { + RTW_PRINT(FUNC_ADPT_FMT" invalid macid:%u\n" + , FUNC_ADPT_ARG(adapter), mac_id); + rtw_warn_on(1); + } +} +void rtw_sta_mstatus_report(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct sta_info *psta = NULL; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, WIFI_ASOC_STATE)) { + psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); + if (psta) + rtw_sta_mstatus_disc_rpt(adapter, psta->mac_id); + else { + RTW_INFO("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress)); + rtw_warn_on(1); + } + } +} + +void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL, irqL2; + + struct sta_info *psta; + struct wlan_network *pwlan = NULL; + WLAN_BSSID_EX *pdev_network = NULL; + u8 *pibss = NULL; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct stadel_event *pstadel = (struct stadel_event *)pbuf; + struct sta_priv *pstapriv = &adapter->stapriv; + struct wlan_network *tgt_network = &(pmlmepriv->cur_network); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + RTW_INFO("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); + rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id); + + psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); + + if (psta == NULL) { + RTW_INFO("%s(mac_id=%d)=" MAC_FMT " psta == NULL\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); + /*rtw_warn_on(1);*/ + } + + if (psta) + rtw_wfd_st_switch(psta, 0); + + /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) */ + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + + return; + } + + mlmeext_sta_del_event_callback(adapter); + + _enter_critical_bh(&pmlmepriv->lock, &irqL2); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + u16 reason = *((unsigned short *)(pstadel->rsvd)); + bool roam = _FALSE; + struct wlan_network *roam_target = NULL; + + if (adapter->registrypriv.wifi_spec == 1) + roam = _FALSE; + else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED)) + roam = _TRUE; + else if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { + roam = _TRUE; + roam_target = pmlmepriv->roam_network; + } + + if (roam == _TRUE) { + if (rtw_to_roam(adapter) > 0) + rtw_dec_to_roam(adapter); /* this stadel_event is caused by roaming, decrease to_roam */ + else if (rtw_to_roam(adapter) == 0) + rtw_set_to_roam(adapter, adapter->registrypriv.max_roaming_times); + } else + rtw_set_to_roam(adapter, 0); + + rtw_free_uc_swdec_pending_queue(adapter); + + rtw_free_assoc_resources(adapter, 1); + rtw_free_mlme_priv_ie_data(pmlmepriv); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + /* remove the network entry in scanned_queue */ + pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); + if ((pwlan) && (!check_fwstate(pmlmepriv, WIFI_UNDER_WPS))) { + pwlan->fixed = _FALSE; + rtw_free_network_nolock(adapter, pwlan); + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + rtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated); + + _rtw_roaming(adapter, roam_target); + } + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) || + check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { + + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + rtw_free_stainfo(adapter, psta); + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + + if (adapter->stapriv.asoc_sta_count == 1) { /* a sta + bc/mc_stainfo (not Ibss_stainfo) */ + /* rtw_indicate_disconnect(adapter); */ /* removed@20091105 */ + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + /* free old ibss network */ + /* pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); */ + pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); + if (pwlan) { + pwlan->fixed = _FALSE; + rtw_free_network_nolock(adapter, pwlan); + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + /* re-create ibss */ + pdev_network = &(adapter->registrypriv.dev_network); + pibss = adapter->registrypriv.dev_network.MacAddress; + + _rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network)); + + _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(adapter); + + rtw_generate_random_ibss(pibss); + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { + set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE); + } + + if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) + RTW_ERR("rtw_create_ibss_cmd FAIL\n"); + + } + + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL2); + +} + +void rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf) +{ + + +} + +void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf) +{ + + WMMOnAssocRsp(padapter); + +} + +/* +* rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss +*/ +void rtw_join_timeout_handler(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + RTW_INFO("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); + + if (RTW_CANNOT_RUN(adapter)) + return; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */ + while (1) { + rtw_dec_to_roam(adapter); + if (rtw_to_roam(adapter) != 0) { /* try another */ + int do_join_r; + RTW_INFO("%s try another roaming\n", __FUNCTION__); + do_join_r = rtw_do_join(adapter); + if (_SUCCESS != do_join_r) { + RTW_INFO("%s roaming do_join return %d\n", __FUNCTION__ , do_join_r); + continue; + } + break; + } else { + RTW_INFO("%s We've try roaming but fail\n", __FUNCTION__); + rtw_indicate_disconnect(adapter, 0, _FALSE); + break; + } + } + + } else + { + rtw_indicate_disconnect(adapter, 0, _FALSE); + free_scanqueue(pmlmepriv);/* ??? */ + + + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +#ifdef CONFIG_DRVEXT_MODULE_WSC + drvext_assoc_fail_indicate(&adapter->drvextpriv); +#endif + +} + +/* +* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey +* @adapter: pointer to _adapter structure +*/ +void rtw_scan_timeout_handler(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + RTW_INFO(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + + rtw_indicate_scan_done(adapter, _TRUE); + +} + +void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 u_ch; + u32 interval_ms = 0xffffffff; /* 0xffffffff: special value to make min() works well, also means no auto scan */ + + *reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED; + rtw_mi_get_ch_setting_union(adapter, &u_ch, NULL, NULL); + + if (hal_chk_bw_cap(adapter, BW_CAP_40M) + && is_client_associated_to_ap(adapter) == _TRUE + && u_ch >= 1 && u_ch <= 14 + && adapter->registrypriv.wifi_spec + /* TODO: AP Connected is 40MHz capability? */ + ) { + interval_ms = rtw_min(interval_ms, 60 * 1000); + *reason |= RTW_AUTO_SCAN_REASON_2040_BSS; + } + + if (interval_ms == 0xffffffff) + interval_ms = 0; + + rtw_mlme_set_auto_scan_int(adapter, interval_ms); + return; +} + +void rtw_drv_scan_by_self(_adapter *padapter, u8 reason) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct rtw_ieee80211_channel ch_for_2040_bss[14] = { + {1, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {2, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {3, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {4, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {5, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {6, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {7, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {8, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {9, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {10, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {11, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {12, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {13, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + {14, RTW_IEEE80211_CHAN_PASSIVE_SCAN}, + }; + struct rtw_ieee80211_channel *ch_sel = NULL; + int ch_num = 0; + + if (rtw_is_scan_deny(padapter)) + goto exit; + + if (!rtw_is_adapter_up(padapter)) + goto exit; + + if (rtw_mi_busy_traffic_check(padapter, _FALSE)) { + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE) && pmlmepriv->need_to_roam == _TRUE) { + RTW_INFO("need to roam, don't care BusyTraffic\n"); + } else + { + RTW_INFO(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + } + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + RTW_INFO(FUNC_ADPT_FMT" WIFI_AP_STATE && WIFI_UNDER_WPS\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + if (check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" _FW_UNDER_SURVEY|_FW_UNDER_LINKING\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + + + RTW_INFO(FUNC_ADPT_FMT" reason:0x%02x\n", FUNC_ADPT_ARG(padapter), reason); + + /* only for 20/40 BSS */ + if (reason == RTW_AUTO_SCAN_REASON_2040_BSS) { + ch_sel = ch_for_2040_bss; + ch_num = 14; + } + + rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, ch_sel, ch_num); +exit: + return; +} + +static void rtw_auto_scan_handler(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 reason = RTW_AUTO_SCAN_REASON_UNSPECIFIED; + + rtw_mlme_reset_auto_scan_int(padapter, &reason); + + if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) + goto exit; + + if (pmlmepriv->auto_scan_int_ms == 0 + || rtw_get_passing_time_ms(pmlmepriv->scan_start_time) < pmlmepriv->auto_scan_int_ms) + goto exit; + + rtw_drv_scan_by_self(padapter, reason); + +exit: + return; +} +static u8 is_drv_in_lps(_adapter *adapter) +{ + u8 is_in_lps = _FALSE; + + return is_in_lps; +} +void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + if (adapter->net_closed == _TRUE) + return; + + /* auto site survey */ + rtw_auto_scan_handler(adapter); + + + rcu_read_lock(); + + if (rcu_dereference(adapter->pnetdev->rx_handler_data) + && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) { + /* expire NAT2.5 entry */ + void nat25_db_expire(_adapter *priv); + nat25_db_expire(adapter); + + if (adapter->pppoe_connection_in_progress > 0) + adapter->pppoe_connection_in_progress--; + /* due to rtw_dynamic_check_timer_handlder() is called every 2 seconds */ + if (adapter->pppoe_connection_in_progress > 0) + adapter->pppoe_connection_in_progress--; + } + + rcu_read_unlock(); + +} + +/*#define DBG_TRAFFIC_STATISTIC*/ +static void collect_traffic_statistics(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + /*_rtw_memset(&pdvobjpriv->traffic_stat, 0, sizeof(struct rtw_traffic_statistics));*/ + + /* Tx bytes reset*/ + pdvobjpriv->traffic_stat.tx_bytes = 0; + pdvobjpriv->traffic_stat.tx_pkts = 0; + pdvobjpriv->traffic_stat.tx_drop = 0; + + /* Rx bytes reset*/ + pdvobjpriv->traffic_stat.rx_bytes = 0; + pdvobjpriv->traffic_stat.rx_pkts = 0; + pdvobjpriv->traffic_stat.rx_drop = 0; + + rtw_mi_traffic_statistics(padapter); + + /* Calculate throughput in last interval */ + pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes; + pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes; + pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes; + pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes; + + pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes * 8 / 2 / 1024 / 1024); + pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes * 8 / 2 / 1024 / 1024); + + #ifdef DBG_TRAFFIC_STATISTIC + RTW_INFO("\n========================\n"); + RTW_INFO("cur_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_tx_bytes); + RTW_INFO("cur_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.cur_rx_bytes); + + RTW_INFO("last_tx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_tx_bytes); + RTW_INFO("last_rx_bytes:%lld\n", pdvobjpriv->traffic_stat.last_rx_bytes); + + RTW_INFO("cur_tx_tp:%d\n", pdvobjpriv->traffic_stat.cur_tx_tp); + RTW_INFO("cur_rx_tp:%d\n", pdvobjpriv->traffic_stat.cur_rx_tp); + #endif +} + +void rtw_dynamic_check_timer_handlder(void *ctx) +{ + struct dvobj_priv *pdvobj = (struct dvobj_priv *)ctx; + _adapter *adapter = dvobj_get_primary_adapter(pdvobj); + + if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm == 0) { /* for MP ODM dynamic Tx power tracking */ + /* RTW_INFO("%s mp_dm =0 return\n", __func__); */ + goto exit; + } + + if (!adapter) + goto exit; + + if (!rtw_is_hw_init_completed(adapter)) + goto exit; + + if (RTW_CANNOT_RUN(adapter)) + goto exit; + + collect_traffic_statistics(adapter); + + rtw_mi_dynamic_check_timer_handlder(adapter); + + if (!is_drv_in_lps(adapter)) + rtw_dynamic_chk_wk_cmd(adapter); + +exit: + _set_timer(&pdvobj->dynamic_chk_timer, 2000); +} + + +/* +* Select a new roaming candidate from the original @param candidate and @param competitor +* @return _TRUE: candidate is updated +* @return _FALSE: candidate is not updated +*/ +static int rtw_check_roaming_candidate(struct mlme_priv *mlme + , struct wlan_network **candidate, struct wlan_network *competitor) +{ + int updated = _FALSE; + _adapter *adapter = container_of(mlme, _adapter, mlmepriv); + + if (is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE) + goto exit; + + if (rtw_is_desired_network(adapter, competitor) == _FALSE) + goto exit; + + if (mlme->need_to_roam == _FALSE) + goto exit; + + + RTW_INFO("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d, age:%5d\n", + (competitor == mlme->cur_network_scanned) ? "*" : " " , + competitor->network.Ssid.Ssid, + MAC_ARG(competitor->network.MacAddress), + competitor->network.Configuration.DSConfig, + (int)competitor->network.Rssi, + rtw_get_passing_time_ms(competitor->last_scanned) + ); + + /* got specific addr to roam */ + if (!is_zero_mac_addr(mlme->roam_tgt_addr)) { + if (_rtw_memcmp(mlme->roam_tgt_addr, competitor->network.MacAddress, ETH_ALEN) == _TRUE) + goto update; + else + goto exit; + } + if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms) + goto exit; + + if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th) + goto exit; + + if (*candidate != NULL && (*candidate)->network.Rssi >= competitor->network.Rssi) + goto exit; + +update: + *candidate = competitor; + updated = _TRUE; + +exit: + return updated; +} + +int rtw_select_roaming_candidate(struct mlme_priv *mlme) +{ + _irqL irqL; + int ret = _FAIL; + _list *phead; + _adapter *adapter; + _queue *queue = &(mlme->scanned_queue); + struct wlan_network *pnetwork = NULL; + struct wlan_network *candidate = NULL; + u8 bSupportAntDiv = _FALSE; + + if (mlme->cur_network_scanned == NULL) { + rtw_warn_on(1); + goto exit; + } + + _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + adapter = (_adapter *)mlme->nic_hdl; + + mlme->pscanned = get_next(phead); + + while (!rtw_end_of_queue_search(phead, mlme->pscanned)) { + + pnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list); + if (pnetwork == NULL) { + ret = _FAIL; + goto exit; + } + + mlme->pscanned = get_next(mlme->pscanned); + + if (0) + RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n" + , pnetwork->network.Ssid.Ssid + , MAC_ARG(pnetwork->network.MacAddress) + , pnetwork->network.Configuration.DSConfig + , (int)pnetwork->network.Rssi); + + rtw_check_roaming_candidate(mlme, &candidate, pnetwork); + + } + + if (candidate == NULL) { + RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); + ret = _FAIL; + goto exit; + } else { + RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, + candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), + candidate->network.Configuration.DSConfig); + + mlme->roam_network = candidate; + + if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE) + _rtw_memset(mlme->roam_tgt_addr, 0, ETH_ALEN); + } + + ret = _SUCCESS; +exit: + _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + + return ret; +} + +/* +* Select a new join candidate from the original @param candidate and @param competitor +* @return _TRUE: candidate is updated +* @return _FALSE: candidate is not updated +*/ +static int rtw_check_join_candidate(struct mlme_priv *mlme + , struct wlan_network **candidate, struct wlan_network *competitor) +{ + int updated = _FALSE; + _adapter *adapter = container_of(mlme, _adapter, mlmepriv); + + /* check bssid, if needed */ + if (mlme->assoc_by_bssid == _TRUE) { + if (_rtw_memcmp(competitor->network.MacAddress, mlme->assoc_bssid, ETH_ALEN) == _FALSE) + goto exit; + } + + /* check ssid, if needed */ + if (mlme->assoc_ssid.Ssid[0] && mlme->assoc_ssid.SsidLength) { + if (competitor->network.Ssid.SsidLength != mlme->assoc_ssid.SsidLength + || _rtw_memcmp(competitor->network.Ssid.Ssid, mlme->assoc_ssid.Ssid, mlme->assoc_ssid.SsidLength) == _FALSE + ) + goto exit; + } + + if (rtw_is_desired_network(adapter, competitor) == _FALSE) + goto exit; + + if (rtw_to_roam(adapter) > 0) { + if (rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms + || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE + ) + goto exit; + } + + if (*candidate == NULL || (*candidate)->network.Rssi < competitor->network.Rssi) { + *candidate = competitor; + updated = _TRUE; + } + + if (updated) { + RTW_INFO("[by_bssid:%u][assoc_ssid:%s][to_roam:%u] " + "new candidate: %s("MAC_FMT", ch%u) rssi:%d\n", + mlme->assoc_by_bssid, + mlme->assoc_ssid.Ssid, + rtw_to_roam(adapter), + (*candidate)->network.Ssid.Ssid, + MAC_ARG((*candidate)->network.MacAddress), + (*candidate)->network.Configuration.DSConfig, + (int)(*candidate)->network.Rssi + ); + } + +exit: + return updated; +} + +/* +Calling context: +The caller of the sub-routine will be in critical section... + +The caller must hold the following spinlock + +pmlmepriv->lock + +*/ + +int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv) +{ + _irqL irqL; + int ret; + _list *phead; + _adapter *adapter; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + struct wlan_network *candidate = NULL; + u8 bSupportAntDiv = _FALSE; + + adapter = (_adapter *)pmlmepriv->nic_hdl; + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (pmlmepriv->roam_network) { + candidate = pmlmepriv->roam_network; + pmlmepriv->roam_network = NULL; + goto candidate_exist; + } + + phead = get_list_head(queue); + pmlmepriv->pscanned = get_next(phead); + + while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) { + + pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); + if (pnetwork == NULL) { + ret = _FAIL; + goto exit; + } + + pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); + + if (0) + RTW_INFO("%s("MAC_FMT", ch%u) rssi:%d\n" + , pnetwork->network.Ssid.Ssid + , MAC_ARG(pnetwork->network.MacAddress) + , pnetwork->network.Configuration.DSConfig + , (int)pnetwork->network.Rssi); + + rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork); + + } + + if (candidate == NULL) { + RTW_INFO("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); + ret = _FAIL; + goto exit; + } else { + RTW_INFO("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, + candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), + candidate->network.Configuration.DSConfig); + goto candidate_exist; + } + +candidate_exist: + + /* check for situation of _FW_LINKED */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + RTW_INFO("%s: _FW_LINKED while ask_for_joinbss!!!\n", __FUNCTION__); + { + rtw_disassoc_cmd(adapter, 0, 0); + rtw_indicate_disconnect(adapter, 0, _FALSE); + rtw_free_assoc_resources(adapter, 0); + } + } + + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + ret = rtw_joinbss_cmd(adapter, candidate); + +exit: + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + return ret; +} + +sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv) +{ + struct cmd_obj *pcmd; + struct setauth_parm *psetauthparm; + struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); + sint res = _SUCCESS; + + pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd == NULL) { + res = _FAIL; /* try again */ + goto exit; + } + + psetauthparm = (struct setauth_parm *)rtw_zmalloc(sizeof(struct setauth_parm)); + if (psetauthparm == NULL) { + rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + _rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm)); + psetauthparm->mode = (unsigned char)psecuritypriv->dot11AuthAlgrthm; + + pcmd->cmdcode = _SetAuth_CMD_; + pcmd->parmbuf = (unsigned char *)psetauthparm; + pcmd->cmdsz = (sizeof(struct setauth_parm)); + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + _rtw_init_listhead(&pcmd->list); + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + +exit: + + return res; + +} + +sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue) +{ + u8 keylen; + struct cmd_obj *pcmd; + struct setkey_parm *psetkeyparm; + struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + sint res = _SUCCESS; + + psetkeyparm = (struct setkey_parm *)rtw_zmalloc(sizeof(struct setkey_parm)); + if (psetkeyparm == NULL) { + res = _FAIL; + goto exit; + } + _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); + + if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { + psetkeyparm->algorithm = (unsigned char)psecuritypriv->dot118021XGrpPrivacy; + } else { + psetkeyparm->algorithm = (u8)psecuritypriv->dot11PrivacyAlgrthm; + + } + psetkeyparm->keyid = (u8)keyid;/* 0~3 */ + psetkeyparm->set_tx = set_tx; + if (is_wep_enc(psetkeyparm->algorithm)) + adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); + + RTW_INFO("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n", psetkeyparm->algorithm, psetkeyparm->keyid, adapter->securitypriv.key_mask); + + switch (psetkeyparm->algorithm) { + + case _WEP40_: + keylen = 5; + _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); + break; + case _WEP104_: + keylen = 13; + _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); + break; + case _TKIP_: + keylen = 16; + _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); + psetkeyparm->grpkey = 1; + break; + case _AES_: + keylen = 16; + _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); + psetkeyparm->grpkey = 1; + break; + default: + res = _FAIL; + rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); + goto exit; + } + + if (enqueue) { + pcmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd == NULL) { + rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); + res = _FAIL; /* try again */ + goto exit; + } + + pcmd->cmdcode = _SetKey_CMD_; + pcmd->parmbuf = (u8 *)psetkeyparm; + pcmd->cmdsz = (sizeof(struct setkey_parm)); + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + _rtw_init_listhead(&pcmd->list); + + /* _rtw_init_sema(&(pcmd->cmd_sem), 0); */ + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + } else { + setkey_hdl(adapter, (u8 *)psetkeyparm); + rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm)); + } +exit: + return res; + +} + +/* adjust IEs for rtw_joinbss_cmd in WMM */ +int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len) +{ + unsigned int ielength = 0; + unsigned int i, j; + + i = 12; /* after the fixed IE */ + while (i < in_len) { + ielength = initial_out_len; + + if (in_ie[i] == 0xDD && in_ie[i + 2] == 0x00 && in_ie[i + 3] == 0x50 && in_ie[i + 4] == 0xF2 && in_ie[i + 5] == 0x02 && i + 5 < in_len) { /* WMM element ID and OUI */ + + /* Append WMM IE to the last index of out_ie */ + for (j = i; j < i + 9; j++) { + out_ie[ielength] = in_ie[j]; + ielength++; + } + out_ie[initial_out_len + 1] = 0x07; + out_ie[initial_out_len + 6] = 0x00; + out_ie[initial_out_len + 8] = 0x00; + + break; + } + + i += (in_ie[i + 1] + 2); /* to the next IE element */ + } + + return ielength; + +} + +/* + * Ported from 8185: IsInPreAuthKeyList(). (Renamed from SecIsInPreAuthKeyList(), 2006-10-13.) + * Added by Annie, 2006-05-07. + * + * Search by BSSID, + * Return Value: + * -1 :if there is no pre-auth key in the table + * >=0 :if there is pre-auth key, and return the entry id + * + * */ + +static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) +{ + struct security_priv *psecuritypriv = &Adapter->securitypriv; + int i = 0; + + do { + if ((psecuritypriv->PMKIDList[i].bUsed) && + (_rtw_memcmp(psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN) == _TRUE)) + break; + else { + i++; + /* continue; */ + } + + } while (i < NUM_PMKID_CACHE); + + if (i == NUM_PMKID_CACHE) { + i = -1;/* Could not find. */ + } else { + /* There is one Pre-Authentication Key for the specific BSSID. */ + } + + return i; + +} + +/* + * Check the RSN IE length + * If the RSN IE length <= 20, the RSN IE didn't include the PMKID information + * 0-11th element in the array are the fixed IE + * 12th element in the array is the IE + * 13th element in the array is the IE length + * */ + +static int rtw_append_pmkid(_adapter *adapter, int iEntry, u8 *ie, uint ie_len) +{ + struct security_priv *sec = &adapter->securitypriv; + + if (ie[13] > 20) { + int i; + u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20); + if (pmkid_cnt == 1 && _rtw_memcmp(ie + 14 + 20 + 2, &sec->PMKIDList[iEntry].PMKID, 16)) { + RTW_INFO(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n" + , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID)); + goto exit; + } + + RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" + , FUNC_ADPT_ARG(adapter), pmkid_cnt); + + for (i = 0; i < pmkid_cnt; i++) + RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16)); + + ie_len -= 2 + pmkid_cnt * 16; + ie[13] = 20; + } + + if (ie[13] <= 20) { + /* The RSN IE didn't include the PMK ID, append the PMK information */ + + RTW_INFO(FUNC_ADPT_FMT" append PMKID:"KEY_FMT"\n" + , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID)); + + RTW_PUT_LE16(&ie[ie_len], 1); + ie_len += 2; + + _rtw_memcpy(&ie[ie_len], &sec->PMKIDList[iEntry].PMKID, 16); + ie_len += 16; + + ie[13] += 18;/* PMKID length = 2+16 */ + } + +exit: + return ie_len; +} + +static int rtw_remove_pmkid(_adapter *adapter, u8 *ie, uint ie_len) +{ + struct security_priv *sec = &adapter->securitypriv; + int i; + u16 pmkid_cnt = RTW_GET_LE16(ie + 14 + 20); + + if (ie[13] <= 20) + goto exit; + + RTW_INFO(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" + , FUNC_ADPT_ARG(adapter), pmkid_cnt); + + for (i = 0; i < pmkid_cnt; i++) + RTW_INFO(" "KEY_FMT"\n", KEY_ARG(ie + 14 + 20 + 2 + i * 16)); + + ie_len -= 2 + pmkid_cnt * 16; + ie[13] = 20; + +exit: + return ie_len; +} + +sint rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len) +{ + u8 authmode = 0x0, securitytype, match; + u8 sec_ie[255], uncst_oui[4], bkup_ie[255]; + u8 wpa_oui[4] = {0x0, 0x50, 0xf2, 0x01}; + uint ielength, cnt, remove_cnt; + int iEntry; + + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct security_priv *psecuritypriv = &adapter->securitypriv; + uint ndisauthmode = psecuritypriv->ndisauthtype; + uint ndissecuritytype = psecuritypriv->ndisencryptstatus; + + /* copy fixed ie only */ + _rtw_memcpy(out_ie, in_ie, 12); + ielength = 12; + if ((ndisauthmode == Ndis802_11AuthModeWPA) || (ndisauthmode == Ndis802_11AuthModeWPAPSK)) + authmode = _WPA_IE_ID_; + if ((ndisauthmode == Ndis802_11AuthModeWPA2) || (ndisauthmode == Ndis802_11AuthModeWPA2PSK)) + authmode = _WPA2_IE_ID_; + + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + _rtw_memcpy(out_ie + ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); + + ielength += psecuritypriv->wps_ie_len; + } else if ((authmode == _WPA_IE_ID_) || (authmode == _WPA2_IE_ID_)) { + /* copy RSN or SSN */ + _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1] + 2); + /* debug for CONFIG_IEEE80211W + { + int jj; + printk("supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\n", psecuritypriv->supplicant_ie[1]+2); + for(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++) + printk(" %02x ", psecuritypriv->supplicant_ie[jj]); + printk("\n"); + }*/ + ielength += psecuritypriv->supplicant_ie[1] + 2; + rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie); + + } + + iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); + if (iEntry < 0) { + if (authmode == _WPA2_IE_ID_) + ielength = rtw_remove_pmkid(adapter, out_ie, ielength); + } else { + if (authmode == _WPA2_IE_ID_) + ielength = rtw_append_pmkid(adapter, iEntry, out_ie, ielength); + } + + return ielength; +} + +void rtw_init_registrypriv_dev_network(_adapter *adapter) +{ + struct registry_priv *pregistrypriv = &adapter->registrypriv; + WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; + u8 *myhwaddr = adapter_mac_addr(adapter); + + _rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN); + + _rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID)); + + pdev_network->Configuration.Length = sizeof(NDIS_802_11_CONFIGURATION); + pdev_network->Configuration.BeaconPeriod = 100; + pdev_network->Configuration.FHConfig.Length = 0; + pdev_network->Configuration.FHConfig.HopPattern = 0; + pdev_network->Configuration.FHConfig.HopSet = 0; + pdev_network->Configuration.FHConfig.DwellTime = 0; + +} + +void rtw_update_registrypriv_dev_network(_adapter *adapter) +{ + int sz = 0; + struct registry_priv *pregistrypriv = &adapter->registrypriv; + WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; + struct security_priv *psecuritypriv = &adapter->securitypriv; + struct wlan_network *cur_network = &adapter->mlmepriv.cur_network; + /* struct xmit_priv *pxmitpriv = &adapter->xmitpriv; */ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; /* adhoc no 802.1x */ + + pdev_network->Rssi = 0; + + switch (pregistrypriv->wireless_mode) { + case WIRELESS_11B: + pdev_network->NetworkTypeInUse = (Ndis802_11DS); + break; + case WIRELESS_11G: + case WIRELESS_11BG: + case WIRELESS_11_24N: + case WIRELESS_11G_24N: + case WIRELESS_11BG_24N: + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); + break; + case WIRELESS_11A: + case WIRELESS_11A_5N: + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); + break; + case WIRELESS_11ABGN: + if (pregistrypriv->channel > 14) + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); + else + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); + break; + default: + /* TODO */ + break; + } + + pdev_network->Configuration.DSConfig = (pregistrypriv->channel); + + if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) { + pdev_network->Configuration.ATIMWindow = (0); + + if (pmlmeext->cur_channel != 0) + pdev_network->Configuration.DSConfig = pmlmeext->cur_channel; + else + pdev_network->Configuration.DSConfig = 1; + } + + pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode); + + /* 1. Supported rates */ + /* 2. IE */ + + /* rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; */ /* will be called in rtw_generate_ie */ + sz = rtw_generate_ie(pregistrypriv); + + pdev_network->IELength = sz; + + pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network); + + /* notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); */ + /* pdev_network->IELength = cpu_to_le32(sz); */ + +} + +void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter) +{ + +} + +/* the fucntion is at passive_level */ +void rtw_joinbss_reset(_adapter *padapter) +{ + u8 threshold; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + /* todo: if you want to do something io/reg/hw setting before join_bss, please add code here */ + + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + + pmlmepriv->num_FortyMHzIntolerant = 0; + + pmlmepriv->num_sta_no_ht = 0; + + phtpriv->ampdu_enable = _FALSE;/* reset to disabled */ + + +} + +void rtw_ht_use_default_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + + if (pregistrypriv->wifi_spec) + phtpriv->bss_coexist = 1; + else + phtpriv->bss_coexist = 0; + + phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE; + phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE; + + /* LDPC support */ + rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport); + CLEAR_FLAGS(phtpriv->ldpc_cap); + if (bHwLDPCSupport) { + if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT4)) + SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport); + if (bHwLDPCSupport) { + if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT5)) + SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX); + } + if (phtpriv->ldpc_cap) + RTW_INFO("[HT] HAL Support LDPC = 0x%02X\n", phtpriv->ldpc_cap); + + /* STBC */ + rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport); + CLEAR_FLAGS(phtpriv->stbc_cap); + if (bHwSTBCSupport) { + if (TEST_FLAG(pregistrypriv->stbc_cap, BIT5)) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport); + if (bHwSTBCSupport) { + if (TEST_FLAG(pregistrypriv->stbc_cap, BIT4)) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX); + } + if (phtpriv->stbc_cap) + RTW_INFO("[HT] HAL Support STBC = 0x%02X\n", phtpriv->stbc_cap); + + /* Beamforming setting */ + CLEAR_FLAGS(phtpriv->beamform_cap); +} +void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len) +{ + unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; + int out_len; + u8 *pframe; + + if (padapter->mlmepriv.qospriv.qos_option == 0) { + out_len = *pout_len; + pframe = rtw_set_ie(out_ie + out_len, _VENDOR_SPECIFIC_IE_, + _WMM_IE_Length_, WMM_IE, pout_len); + + padapter->mlmepriv.qospriv.qos_option = 1; + } +} + +/* the fucntion is >= passive_level */ +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel) +{ + u32 ielen, out_len; + u32 rx_packet_offset, max_recvbuf_sz; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; + HT_CAP_AMPDU_DENSITY best_ampdu_density; + unsigned char *p, *pframe; + struct rtw_ieee80211_ht_cap ht_capie; + u8 cbw40_enable = 0, rf_type = 0, operation_bw = 0, rf_num = 0, rx_stbc_nss = 0, rx_nss = 0; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + + phtpriv->ht_option = _FALSE; + + out_len = *pout_len; + + _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); + + ht_capie.cap_info = IEEE80211_HT_CAP_DSSSCCK40; + + if (phtpriv->sgi_20m) + ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20; + + /* Get HT BW */ + if (in_ie == NULL) { + /* TDLS: TODO 20/40 issue */ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + operation_bw = padapter->mlmeextpriv.cur_bwmode; + if (operation_bw > CHANNEL_WIDTH_40) + operation_bw = CHANNEL_WIDTH_40; + } else + /* TDLS: TODO 40? */ + operation_bw = CHANNEL_WIDTH_40; + } else { + p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len); + if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) { + struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2); + if (pht_info->infos[0] & BIT(2)) { + switch (pht_info->infos[0] & 0x3) { + case 1: + case 3: + operation_bw = CHANNEL_WIDTH_40; + break; + default: + operation_bw = CHANNEL_WIDTH_20; + break; + } + } else + operation_bw = CHANNEL_WIDTH_20; + } + } + + /* to disable 40M Hz support while gd_bw_40MHz_en = 0 */ + if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { + if (channel > 14) { + if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } else { + if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } + } + + if ((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) { + ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH; + if (phtpriv->sgi_40m) + ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40; + } + + /* todo: disable SM power save mode */ + ht_capie.cap_info |= IEEE80211_HT_CAP_SM_PS; + + /* RX LDPC */ + if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) { + ht_capie.cap_info |= IEEE80211_HT_CAP_LDPC_CODING; + RTW_INFO("[HT] Declare supporting RX LDPC\n"); + } + + /* TX STBC */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) { + ht_capie.cap_info |= IEEE80211_HT_CAP_TX_STBC; + RTW_INFO("[HT] Declare supporting TX STBC\n"); + } + + /* RX STBC */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { + if ((pregistrypriv->rx_stbc == 0x3) || /* enable for 2.4/5 GHz */ + ((channel <= 14) && (pregistrypriv->rx_stbc == 0x1)) || /* enable for 2.4GHz */ + ((channel > 14) && (pregistrypriv->rx_stbc == 0x2)) || /* enable for 5GHz */ + (pregistrypriv->wifi_spec == 1)) { + /* HAL_DEF_RX_STBC means STBC RX spatial stream, todo: VHT 4 streams */ + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss)); + SET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss); + RTW_INFO("[HT] Declare supporting RX STBC = %d\n", rx_stbc_nss); + } + } + + /* fill default supported_mcs_set */ + _rtw_memcpy(ht_capie.supp_mcs_set, pmlmeext->default_supported_mcs_set, 16); + + /* update default supported_mcs_set */ + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); + + switch (rx_nss) { + case 1: + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R); + break; + case 2: + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R); + break; + case 3: + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R); + break; + case 4: + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_4R); + break; + default: + RTW_WARN("rf_type:%d or rx_nss:%u is not expected\n", rf_type, hal_spec->rx_nss_num); + } + + { + rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); + rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); + if (max_recvbuf_sz - rx_packet_offset >= (8191 - 256)) { + RTW_INFO("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__); + ht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU; + } + } + /* + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k + AMPDU_para [4:2]:Min MPDU Start Spacing + */ + + if (padapter->driver_rx_ampdu_factor != 0xFF) + max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)padapter->driver_rx_ampdu_factor; + else + rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + + /* rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); */ + ht_capie.ampdu_params_info = (max_rx_ampdu_factor & 0x03); + + if (padapter->driver_rx_ampdu_spacing != 0xFF) + ht_capie.ampdu_params_info |= ((padapter->driver_rx_ampdu_spacing & 0x07) << 2); + else { + if (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) { + /* + * Todo : Each chip must to ask DD , this chip best ampdu_density setting + * By yiwei.sun + */ + rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density); + + ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2)); + + } else + ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & 0x00); + } + + pframe = rtw_set_ie(out_ie + out_len, _HT_CAPABILITY_IE_, + sizeof(struct rtw_ieee80211_ht_cap), (unsigned char *)&ht_capie, pout_len); + + phtpriv->ht_option = _TRUE; + + if (in_ie != NULL) { + p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len); + if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) { + out_len = *pout_len; + pframe = rtw_set_ie(out_ie + out_len, _HT_ADD_INFO_IE_, ielen, p + 2 , pout_len); + } + } + + return phtpriv->ht_option; + +} + +/* the fucntion is > passive_level (in critical_section) */ +void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) +{ + u8 *p, max_ampdu_sz; + int len; + /* struct sta_info *bmc_sta, *psta; */ + struct rtw_ieee80211_ht_cap *pht_capie; + struct ieee80211_ht_addt_info *pht_addtinfo; + /* struct recv_reorder_ctrl *preorder_ctrl; */ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + /* struct recv_priv *precvpriv = &padapter->recvpriv; */ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + /* struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; */ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 cbw40_enable = 0; + + if (!phtpriv->ht_option) + return; + + if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable)) + return; + + RTW_INFO("+rtw_update_ht_cap()\n"); + + /* maybe needs check if ap supports rx ampdu. */ + if ((phtpriv->ampdu_enable == _FALSE) && (pregistrypriv->ampdu_enable == 1)) { + if (pregistrypriv->wifi_spec == 1) { + /* remove this part because testbed AP should disable RX AMPDU */ + /* phtpriv->ampdu_enable = _FALSE; */ + phtpriv->ampdu_enable = _TRUE; + } else + phtpriv->ampdu_enable = _TRUE; + } + + /* check Max Rx A-MPDU Size */ + len = 0; + p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs)); + if (p && len > 0) { + pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2); + max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR); + max_ampdu_sz = 1 << (max_ampdu_sz + 3); /* max_ampdu_sz (kbytes); */ + + /* RTW_INFO("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz); */ + phtpriv->rx_ampdu_maxlen = max_ampdu_sz; + + } + + len = 0; + p = rtw_get_ie(pie + sizeof(NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len - sizeof(NDIS_802_11_FIXED_IEs)); + if (p && len > 0) { + pht_addtinfo = (struct ieee80211_ht_addt_info *)(p + 2); + /* todo: */ + } + + if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { + if (channel > 14) { + if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } else { + if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } + } + + /* update cur_bwmode & cur_ch_offset */ + if ((cbw40_enable) && + (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && + (pmlmeinfo->HT_info.infos[0] & BIT(2))) { + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + int i; + u8 rf_type = RF_1T1R; + u8 tx_nss = 0; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + + /* update the MCS set */ + for (i = 0; i < 16; i++) + pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; + + /* update the MCS rates */ + switch (tx_nss) { + case 1: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); + break; + case 2: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); + break; + case 3: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); + break; + case 4: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R); + break; + default: + RTW_WARN("rf_type:%d or tx_nss_num:%u is not expected\n", rf_type, hal_spec->tx_nss_num); + } + + /* switch to the 40M Hz mode accoring to the AP */ + /* pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; */ + switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) { + case EXTCHNL_OFFSET_UPPER: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + + case EXTCHNL_OFFSET_LOWER: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + + default: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + } + + /* */ + /* Config SM Power Save setting */ + /* */ + pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; + if (pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) { + RTW_INFO("%s(): WLAN_HT_CAP_SM_PS_STATIC\n", __FUNCTION__); + } + + /* */ + /* Config current HT Protection mode. */ + /* */ + pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; +} + +void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + u8 issued; + int priority; + struct sta_info *psta = NULL; + struct ht_priv *phtpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + s32 bmcst = IS_MCAST(pattrib->ra); + + /* if(bmcst || (padapter->mlmepriv.LinkDetectInfo.bTxBusyTraffic == _FALSE)) */ + if (bmcst || (padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod < 100)) + return; + + priority = pattrib->priority; + + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return; + } + + if (psta == NULL) { + RTW_INFO("%s, psta==NUL\n", __func__); + return; + } + + if (!(psta->state & _FW_LINKED)) { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return; + } + + phtpriv = &psta->htpriv; + + if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) { + issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1; + issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1; + + if (0 == issued) { + RTW_INFO("rtw_issue_addbareq_cmd, p=%d\n", priority); + psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); + rtw_addbareq_cmd(padapter, (u8) priority, pattrib->ra); + } + } + +} + +void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + u8 cap_content[8] = { 0 }; + u8 *pframe; + u8 null_content[8] = {0}; + + if (phtpriv->bss_coexist) + SET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1); + + if (pvhtpriv->vht_option) + SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1); + /* + From 802.11 specification,if a STA does not support any of capabilities defined + in the Extended Capabilities element, then the STA is not required to + transmit the Extended Capabilities element. + */ + if (_FALSE == _rtw_memcmp(cap_content, null_content, 8)) + pframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content , pout_len); +} + +inline void rtw_set_to_roam(_adapter *adapter, u8 to_roam) +{ + if (to_roam == 0) + adapter->mlmepriv.to_join = _FALSE; + adapter->mlmepriv.to_roam = to_roam; +} + +inline u8 rtw_dec_to_roam(_adapter *adapter) +{ + adapter->mlmepriv.to_roam--; + return adapter->mlmepriv.to_roam; +} + +inline u8 rtw_to_roam(_adapter *adapter) +{ + return adapter->mlmepriv.to_roam; +} + +void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_roaming(padapter, tgt_network); + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} +void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + int do_join_r; + + if (0 < rtw_to_roam(padapter)) { + RTW_INFO("roaming from %s("MAC_FMT"), length:%d\n", + cur_network->network.Ssid.Ssid, MAC_ARG(cur_network->network.MacAddress), + cur_network->network.Ssid.SsidLength); + _rtw_memcpy(&pmlmepriv->assoc_ssid, &cur_network->network.Ssid, sizeof(NDIS_802_11_SSID)); + + pmlmepriv->assoc_by_bssid = _FALSE; + + while (1) { + do_join_r = rtw_do_join(padapter); + if (_SUCCESS == do_join_r) + break; + else { + RTW_INFO("roaming do_join return %d\n", do_join_r); + rtw_dec_to_roam(padapter); + + if (rtw_to_roam(padapter) > 0) + continue; + else { + RTW_INFO("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__, __LINE__); + rtw_indicate_disconnect(padapter, 0, _FALSE); + break; + } + } + } + } + +} + +bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + u8 allowed_bw; + + if (req_ch <= 14) + allowed_bw = REGSTY_BW_2G(regsty); + else + allowed_bw = REGSTY_BW_5G(regsty); + + allowed_bw = hal_largest_bw(adapter, allowed_bw); + + if (allowed_bw == CHANNEL_WIDTH_80 && *req_bw > CHANNEL_WIDTH_80) + *req_bw = CHANNEL_WIDTH_80; + else if (allowed_bw == CHANNEL_WIDTH_40 && *req_bw > CHANNEL_WIDTH_40) + *req_bw = CHANNEL_WIDTH_40; + else if (allowed_bw == CHANNEL_WIDTH_20 && *req_bw > CHANNEL_WIDTH_20) { + *req_bw = CHANNEL_WIDTH_20; + *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } else + return _FALSE; + + return _TRUE; +} + +sint rtw_linked_check(_adapter *padapter) +{ + if ((check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) || + (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + if (padapter->stapriv.asoc_sta_count > 2) + return _TRUE; + } else { + /* Station mode */ + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _TRUE) + return _TRUE; + } + return _FALSE; +} +u8 rtw_is_adapter_up(_adapter *padapter) +{ + if (padapter == NULL) + return _FALSE; + + if (RTW_CANNOT_RUN(padapter)) { + RTW_INFO(FUNC_ADPT_FMT "-(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", FUNC_ADPT_ARG(padapter)); + return _FALSE; + } + + if (!rtw_is_hw_init_completed(padapter)) { + /*RTW_INFO(FUNC_ADPT_FMT "-(hw_init_completed == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/ + return _FALSE; + } + + if (padapter->bup == _FALSE) { + /*RTW_INFO(FUNC_ADPT_FMT "-(bup == _FALSE)\n", FUNC_ADPT_ARG(padapter));*/ + return _FALSE; + } + + return _TRUE; +} + +bool is_miracast_enabled(_adapter *adapter) +{ + bool enabled = 0; + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + enabled = (wfdinfo->stack_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK)) + || (wfdinfo->op_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK)); + + return enabled; +} + +bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode) +{ + bool ret = 0; + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + ret = (wfdinfo->stack_wfd_mode & mode) || (wfdinfo->op_wfd_mode & mode); + + return ret; +} + +const char *get_miracast_mode_str(int mode) +{ + if (mode == MIRACAST_SOURCE) + return "SOURCE"; + else if (mode == MIRACAST_SINK) + return "SINK"; + else if (mode == (MIRACAST_SOURCE | MIRACAST_SINK)) + return "SOURCE&SINK"; + else if (mode == MIRACAST_DISABLED) + return "DISABLED"; + else + return "INVALID"; +} + +static bool wfd_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + if (ntohs(*((u16 *)local_port)) == wfdinfo->rtsp_ctrlport + || ntohs(*((u16 *)local_port)) == wfdinfo->tdls_rtsp_ctrlport + || ntohs(*((u16 *)remote_port)) == wfdinfo->peer_rtsp_ctrlport) + return _TRUE; + return _FALSE; +} + +static struct st_register wfd_st_reg = { + .s_proto = 0x06, + .rule = wfd_st_match_rule, +}; + +inline void rtw_wfd_st_switch(struct sta_info *sta, bool on) +{ + if (on) + rtw_st_ctl_register(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD, &wfd_st_reg); + else + rtw_st_ctl_unregister(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD); +} diff --git a/drivers/staging/rtl8821ce/core/rtw_mlme_ext.c b/drivers/staging/rtl8821ce/core/rtw_mlme_ext.c new file mode 100644 index 000000000000..61c548a450fd --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_mlme_ext.c @@ -0,0 +1,11868 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MLME_EXT_C_ + +#include <drv_types.h> +#include <hal_data.h> + +struct mlme_handler mlme_sta_tbl[] = { + {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, + {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp}, + {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq}, + {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp}, + {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq}, + {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp}, + + /*---------------------------------------------------------- + below 2 are reserved + -----------------------------------------------------------*/ + {0, "DoReserved", &DoReserved}, + {0, "DoReserved", &DoReserved}, + {WIFI_BEACON, "OnBeacon", &OnBeacon}, + {WIFI_ATIM, "OnATIM", &OnAtim}, + {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc}, + {WIFI_AUTH, "OnAuth", &OnAuthClient}, + {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth}, + {WIFI_ACTION, "OnAction", &OnAction}, + {WIFI_ACTION_NOACK, "OnActionNoAck", &OnAction}, +}; + +struct action_handler OnAction_tbl[] = { + {RTW_WLAN_CATEGORY_SPECTRUM_MGMT, "ACTION_SPECTRUM_MGMT", on_action_spct}, + {RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos}, + {RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls}, + {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back}, + {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public}, + {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved}, + {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &OnAction_ft}, + {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht}, + {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved}, + {RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved}, + {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved}, + {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, + {RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht}, + {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p}, +}; + +u8 null_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; + +/************************************************** +OUI definitions for the vendor specific IE +***************************************************/ +unsigned char RTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01}; +unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02}; +unsigned char WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04}; +unsigned char P2P_OUI[] = {0x50, 0x6F, 0x9A, 0x09}; +unsigned char WFD_OUI[] = {0x50, 0x6F, 0x9A, 0x0A}; + +unsigned char WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; +unsigned char WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + +unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02}; +unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02}; + +extern unsigned char REALTEK_96B_IE[]; + +static struct ch_list_t RTW_ChannelPlan2G[] = { + /* 0, RTW_RD_2G_NULL */ CH_LIST_ENT(0), + /* 1, RTW_RD_2G_WORLD */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 2, RTW_RD_2G_ETSI1 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 3, RTW_RD_2G_FCC1 */ CH_LIST_ENT(11, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11), + /* 4, RTW_RD_2G_MKK1 */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), + /* 5, RTW_RD_2G_ETSI2 */ CH_LIST_ENT(4, 10, 11, 12, 13), + /* 6, RTW_RD_2G_GLOBAL */ CH_LIST_ENT(14, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14), + /* 7, RTW_RD_2G_MKK2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), + /* 8, RTW_RD_2G_FCC2 */ CH_LIST_ENT(13, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13), +}; + +static struct ch_list_t RTW_ChannelPlan5G[] = { + /* 0, RTW_RD_5G_NULL */ CH_LIST_ENT(0), + /* 1, RTW_RD_5G_ETSI1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 2, RTW_RD_5G_ETSI2 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 3, RTW_RD_5G_ETSI3 */ CH_LIST_ENT(22, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165), + /* 4, RTW_RD_5G_FCC1 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 5, RTW_RD_5G_FCC2 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 6, RTW_RD_5G_FCC3 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 7, RTW_RD_5G_FCC4 */ CH_LIST_ENT(12, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161), + /* 8, RTW_RD_5G_FCC5 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 9, RTW_RD_5G_FCC6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 10, RTW_RD_5G_FCC7 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 11, RTW_RD_5G_KCC1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161), + /* 12, RTW_RD_5G_MKK1 */ CH_LIST_ENT(19, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 13, RTW_RD_5G_MKK2 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 14, RTW_RD_5G_MKK3 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 15, RTW_RD_5G_NCC1 */ CH_LIST_ENT(16, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 16, RTW_RD_5G_NCC2 */ CH_LIST_ENT(8, 56, 60, 64, 149, 153, 157, 161, 165), + /* 17, RTW_RD_5G_NCC3 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 18, RTW_RD_5G_ETSI4 */ CH_LIST_ENT(4, 36, 40, 44, 48), + /* 19, RTW_RD_5G_ETSI5 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 20, RTW_RD_5G_FCC8 */ CH_LIST_ENT(4, 149, 153, 157, 161), + /* 21, RTW_RD_5G_ETSI6 */ CH_LIST_ENT(8, 36, 40, 44, 48, 52, 56, 60, 64), + /* 22, RTW_RD_5G_ETSI7 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 23, RTW_RD_5G_ETSI8 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 24, RTW_RD_5G_ETSI9 */ CH_LIST_ENT(11, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140), + /* 25, RTW_RD_5G_ETSI10 */ CH_LIST_ENT(5, 149, 153, 157, 161, 165), + /* 26, RTW_RD_5G_ETSI11 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165), + /* 27, RTW_RD_5G_NCC4 */ CH_LIST_ENT(17, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 28, RTW_RD_5G_ETSI12 */ CH_LIST_ENT(4, 149, 153, 157, 161), + /* 29, RTW_RD_5G_FCC9 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 30, RTW_RD_5G_ETSI13 */ CH_LIST_ENT(16, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140), + /* 31, RTW_RD_5G_FCC10 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161), + /* 32, RTW_RD_5G_MKK4 */ CH_LIST_ENT(4, 36, 40, 44, 48), + /* 33, RTW_RD_5G_ETSI14 */ CH_LIST_ENT(11, 36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140), + /* 34, RTW_RD_5G_FCC11 */ CH_LIST_ENT(25, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 149, 153, 157, 161, 165), + /* 35, RTW_RD_5G_ETSI15 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 149, 153, 157, 161, 165), + /* 36, RTW_RD_5G_MKK5 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 37, RTW_RD_5G_ETSI16 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 38, RTW_RD_5G_ETSI17 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 39, RTW_RD_5G_FCC12*/ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 40, RTW_RD_5G_FCC13 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + /* 41, RTW_RD_5G_FCC14 */ CH_LIST_ENT(21, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165), + /* 42, RTW_RD_5G_FCC15 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 43, RTW_RD_5G_FCC16 */ CH_LIST_ENT(13, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165), + /* 44, RTW_RD_5G_ETSI18 */ CH_LIST_ENT(9, 36, 40, 44, 48, 149, 153, 157, 161, 165), + /* 45, RTW_RD_5G_ETSI19 */ CH_LIST_ENT(24, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165), + + /* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */ + /* RTW_RD_5G_OLD_FCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), + /* RTW_RD_5G_OLD_NCC1 */ CH_LIST_ENT(15, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165), + /* RTW_RD_5G_OLD_KCC1 */ CH_LIST_ENT(20, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165), +}; + +static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { + /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC), /* 0x00, RTW_CHPLAN_FCC */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC), /* 0x01, RTW_CHPLAN_IC */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x02, RTW_CHPLAN_ETSI */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x03, RTW_CHPLAN_SPAIN */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x04, RTW_CHPLAN_FRANCE */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x05, RTW_CHPLAN_MKK */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x06, RTW_CHPLAN_MKK1 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x07, RTW_CHPLAN_ISRAEL */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK), /* 0x08, RTW_CHPLAN_TELEC */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC), /* 0x0B, RTW_CHPLAN_TAIWAN */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x0C, RTW_CHPLAN_CHINA */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW), /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI), /* 0x0E, RTW_CHPLAN_KOREA */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI), /* 0x0F, RTW_CHPLAN_TURKEY */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK), /* 0x10, RTW_CHPLAN_JAPAN */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI), /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI), /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK), /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI), /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x1E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW), /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */ + + /* ===== 0x20 ~ 0x7F, new channel plan ===== */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x20, RTW_CHPLAN_WORLD_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x21, RTW_CHPLAN_ETSI1_NULL */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x22, RTW_CHPLAN_FCC1_NULL */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK), /* 0x23, RTW_CHPLAN_MKK1_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI), /* 0x24, RTW_CHPLAN_ETSI2_NULL */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x25, RTW_CHPLAN_FCC1_FCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI), /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK), /* 0x27, RTW_CHPLAN_MKK1_MKK1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_ETSI), /* 0x28, RTW_CHPLAN_WORLD_KCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x29, RTW_CHPLAN_WORLD_FCC2 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC), /* 0x2A, RTW_CHPLAN_FCC2_NULL */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x2F, */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC), /* 0x30, RTW_CHPLAN_WORLD_FCC3 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC), /* 0x31, RTW_CHPLAN_WORLD_FCC4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x32, RTW_CHPLAN_WORLD_FCC5 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC), /* 0x33, RTW_CHPLAN_WORLD_FCC6 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x34, RTW_CHPLAN_FCC1_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI), /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI), /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK), /* 0x37, RTW_CHPLAN_MKK1_MKK2 */ + CHPLAN_ENT(RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK), /* 0x38, RTW_CHPLAN_MKK1_MKK3 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC), /* 0x39, RTW_CHPLAN_FCC1_NCC1 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x3F, */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC), /* 0x40, RTW_CHPLAN_FCC1_NCC2 */ + CHPLAN_ENT(RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x41, RTW_CHPLAN_GLOBAL_NULL */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI), /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC), /* 0x43, RTW_CHPLAN_FCC1_FCC2 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC), /* 0x44, RTW_CHPLAN_FCC1_NCC3 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI5, TXPWR_LMT_ETSI), /* 0x45, RTW_CHPLAN_WORLD_ETSI5 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC), /* 0x46, RTW_CHPLAN_FCC1_FCC8 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI), /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI), /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x4F, */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI), /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI), /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI), /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC), /* 0x53, RTW_CHPLAN_FCC1_NCC4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI), /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC), /* 0x55, RTW_CHPLAN_FCC1_FCC9 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI), /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC), /* 0x57, RTW_CHPLAN_FCC1_FCC10 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK), /* 0x58, RTW_CHPLAN_MKK2_MKK4 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI), /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5A, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5B, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5C, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5D, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5E, */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW), /* 0x5F, */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC), /* 0x60, RTW_CHPLAN_FCC1_FCC5 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC7, TXPWR_LMT_FCC), /* 0x61, RTW_CHPLAN_FCC2_FCC7 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC1, TXPWR_LMT_FCC), /* 0x62, RTW_CHPLAN_FCC2_FCC1 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_ETSI15, TXPWR_LMT_ETSI), /* 0x63, RTW_CHPLAN_WORLD_ETSI15 */ + CHPLAN_ENT(RTW_RD_2G_MKK2, RTW_RD_5G_MKK5, TXPWR_LMT_MKK), /* 0x64, RTW_CHPLAN_MKK2_MKK5 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI16, TXPWR_LMT_ETSI), /* 0x65, RTW_CHPLAN_ETSI1_ETSI16 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x66, RTW_CHPLAN_FCC1_FCC14 */ + CHPLAN_ENT(RTW_RD_2G_FCC1, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x67, RTW_CHPLAN_FCC1_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC14, TXPWR_LMT_FCC), /* 0x68, RTW_CHPLAN_FCC2_FCC14 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x69, RTW_CHPLAN_FCC2_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x6A, RTW_CHPLAN_ETSI1_ETSI17 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC16, TXPWR_LMT_FCC), /* 0x6B, RTW_CHPLAN_WORLD_FCC16 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC13, TXPWR_LMT_FCC), /* 0x6C, RTW_CHPLAN_WORLD_FCC13 */ + CHPLAN_ENT(RTW_RD_2G_FCC2, RTW_RD_5G_FCC15, TXPWR_LMT_FCC), /* 0x6D, RTW_CHPLAN_FCC2_FCC15 */ + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC12, TXPWR_LMT_FCC), /* 0x6E, RTW_CHPLAN_WORLD_FCC12 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI), /* 0x6F, RTW_CHPLAN_NULL_ETSI8 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI18, TXPWR_LMT_ETSI), /* 0x70, RTW_CHPLAN_NULL_ETSI18 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI17, TXPWR_LMT_ETSI), /* 0x71, RTW_CHPLAN_NULL_ETSI17 */ + CHPLAN_ENT(RTW_RD_2G_NULL, RTW_RD_5G_ETSI19, TXPWR_LMT_ETSI), /* 0x72, RTW_CHPLAN_NULL_ETSI19 */ +}; + +static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = + CHPLAN_ENT(RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC); /* 0x7F, Realtek Define */ + +bool rtw_chplan_is_empty(u8 id) +{ + RT_CHANNEL_PLAN_MAP *chplan_map; + + if (id == RTW_CHPLAN_REALTEK_DEFINE) + chplan_map = &RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE; + else + chplan_map = &RTW_ChannelPlanMap[id]; + + if (chplan_map->Index2G == RTW_RD_2G_NULL + && chplan_map->Index5G == RTW_RD_5G_NULL + ) + return _TRUE; + + return _FALSE; +} + +inline u8 rtw_rd_5g_band1_passive(u8 rtw_rd_5g) +{ + u8 passive = 0; + + switch (rtw_rd_5g) { + case RTW_RD_5G_FCC13: + case RTW_RD_5G_FCC16: + case RTW_RD_5G_ETSI18: + case RTW_RD_5G_ETSI19: + passive = 1; + }; + + return passive; +} + +inline u8 rtw_rd_5g_band4_passive(u8 rtw_rd_5g) +{ + u8 passive = 0; + + switch (rtw_rd_5g) { + case RTW_RD_5G_MKK5: + case RTW_RD_5G_ETSI16: + case RTW_RD_5G_ETSI18: + case RTW_RD_5G_ETSI19: + passive = 1; + }; + + return passive; +} + +void rtw_rfctl_init(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + _rtw_memset(rfctl, 0, sizeof(*rfctl)); + +} + +/* choose channel with shortest waiting (non ocp + cac) time */ +bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags) +{ +#ifndef DBG_CHOOSE_SHORTEST_WAITING_CH +#define DBG_CHOOSE_SHORTEST_WAITING_CH 0 +#endif + + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct registry_priv *regsty = adapter_to_regsty(adapter); + u8 ch, bw, offset; + u8 ch_c = 0, bw_c = 0, offset_c = 0; + int i; + u32 min_waiting_ms = 0; + + if (!dec_ch || !dec_bw || !dec_offset) { + rtw_warn_on(1); + return _FALSE; + } + + /* full search and narrow bw judegement first to avoid potetial judegement timing issue */ + for (bw = CHANNEL_WIDTH_20; bw <= req_bw; bw++) { + if (!hal_is_bw_support(adapter, bw)) + continue; + + for (i = 0; i < mlmeext->max_chan_nums; i++) { + u32 non_ocp_ms = 0; + u32 cac_ms = 0; + u32 waiting_ms = 0; + + ch = mlmeext->channel_set[i].ChannelNum; + + if ((d_flags & RTW_CHF_2G) && ch <= 14) + continue; + + if ((d_flags & RTW_CHF_5G) && ch > 14) + continue; + + if (ch > 14) { + if (bw > REGSTY_BW_5G(regsty)) + continue; + } else { + if (bw > REGSTY_BW_2G(regsty)) + continue; + } + + if (!rtw_get_offset_by_chbw(ch, bw, &offset)) + continue; + + if (!rtw_chset_is_chbw_valid(mlmeext->channel_set, ch, bw, offset)) + continue; + + if ((d_flags & RTW_CHF_NON_OCP) && rtw_chset_is_ch_non_ocp(mlmeext->channel_set, ch, bw, offset)) + continue; + + if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_chbw(ch, bw, offset)) + continue; + + if ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter))) + continue; + + if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_chbw(ch, bw, offset)) + continue; + + if ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(ch, bw, offset, rtw_odm_get_dfs_domain(adapter))) + continue; + + + if (DBG_CHOOSE_SHORTEST_WAITING_CH) + RTW_INFO(FUNC_ADPT_FMT":%u,%u,%u %u(non_ocp:%u, cac:%u)\n" + , FUNC_ADPT_ARG(adapter), ch, bw, offset, waiting_ms, non_ocp_ms, cac_ms); + + if (ch_c == 0 + || min_waiting_ms > waiting_ms + || (min_waiting_ms == waiting_ms && bw > bw_c) /* wider bw first */ + ) { + ch_c = ch; + bw_c = bw; + offset_c = offset; + min_waiting_ms = waiting_ms; + } + } + } + + if (ch_c != 0) { + RTW_INFO(FUNC_ADPT_FMT": d_flags:0x%02x %u,%u,%u waiting_ms:%u\n" + , FUNC_ADPT_ARG(adapter), d_flags, ch_c, bw_c, offset_c, min_waiting_ms); + + *dec_ch = ch_c; + *dec_bw = bw_c; + *dec_offset = offset_c; + return _TRUE; + } + + if (d_flags == 0) + rtw_warn_on(1); + + return _FALSE; +} + +void dump_country_chplan(void *sel, const struct country_chplan *ent) +{ + _RTW_PRINT_SEL(sel, "\"%c%c\", 0x%02X%s\n" + , ent->alpha2[0], ent->alpha2[1], ent->chplan + , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" + ); +} + +void dump_country_chplan_map(void *sel) +{ + const struct country_chplan *ent; + u8 code[2]; + + + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { + for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { + ent = rtw_get_chplan_from_country(code); + if (!ent) + continue; + + dump_country_chplan(sel, ent); + } + } +} + +void dump_chplan_id_list(void *sel) +{ + int i; + + for (i = 0; i < RTW_CHPLAN_MAX; i++) { + if (!rtw_is_channel_plan_valid(i)) + continue; + + _RTW_PRINT_SEL(sel, "0x%02X ", i); + } + + RTW_PRINT_SEL(sel, "0x7F\n"); +} + +void dump_chplan_test(void *sel) +{ + int i, j; + + /* check invalid channel */ + for (i = 0; i < RTW_RD_2G_MAX; i++) { + for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan2G[i]); j++) { + if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan2G[i], j)) == 0) + RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan2G[i], j), i, j); + } + } + + for (i = 0; i < RTW_RD_5G_MAX; i++) { + for (j = 0; j < CH_LIST_LEN(RTW_ChannelPlan5G[i]); j++) { + if (rtw_ch2freq(CH_LIST_CH(RTW_ChannelPlan5G[i], j)) == 0) + RTW_PRINT_SEL(sel, "invalid ch:%u at (%d,%d)\n", CH_LIST_CH(RTW_ChannelPlan5G[i], j), i, j); + } + } +} + +void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set) +{ + u8 i; + + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { + RTW_PRINT_SEL(sel, "ch:%3u, freq:%u, scan_type:%d" + , ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), ch_set[i].ScanType); + + _RTW_PRINT_SEL(sel, ", rx_count:%u", ch_set[i].rx_count); + + + _RTW_PRINT_SEL(sel, "\n"); + } + + RTW_PRINT_SEL(sel, "total ch number:%d\n", i); +} + +void dump_cur_chset(void *sel, _adapter *adapter) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct registry_priv *regsty = adapter_to_regsty(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int i; + + if (mlme->country_ent) + dump_country_chplan(sel, mlme->country_ent); + else + RTW_PRINT_SEL(sel, "chplan:0x%02X\n", mlme->ChannelPlan); + + RTW_PRINT_SEL(sel, "2G_PLS:%u, 5G_PLS:%u\n" + , hal_data->Regulation2_4G, hal_data->Regulation5G); + + + for (i = 0; i < MAX_CHANNEL_NUM; i++) + if (regsty->excl_chs[i] != 0) + break; + + if (i < MAX_CHANNEL_NUM) { + _RTW_PRINT_SEL(sel, "excl_chs:"); + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + if (regsty->excl_chs[i] == 0) + break; + _RTW_PRINT_SEL(sel, "%u ", regsty->excl_chs[i]); + } + RTW_PRINT_SEL(sel, "\n"); + } + + dump_chset(sel, mlmeext->channel_set); +} + +/* + * Search the @param ch in given @param ch_set + * @ch_set: the given channel set + * @ch: the given channel number + * + * return the index of channel_num in channel_set, -1 if not found + */ +int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch) +{ + int i; + + if (ch == 0) + return -1; + + for (i = 0; i < MAX_CHANNEL_NUM && ch_set[i].ChannelNum != 0; i++) { + if (ch == ch_set[i].ChannelNum) + return i; + } + + return -1; +} + +/* + * Check if the @param ch, bw, offset is valid for the given @param ch_set + * @ch_set: the given channel set + * @ch: the given channel number + * @bw: the given bandwidth + * @offset: the given channel offset + * + * return valid (1) or not (0) + */ +u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) +{ + u8 cch; + u8 *op_chs; + u8 op_ch_num; + u8 valid = 0; + int i; + + cch = rtw_get_center_ch(ch, bw, offset); + + if (!rtw_get_op_chs_by_cch_bw(cch, bw, &op_chs, &op_ch_num)) + goto exit; + + for (i = 0; i < op_ch_num; i++) { + if (0) + RTW_INFO("%u,%u,%u - cch:%u, bw:%u, op_ch:%u\n", ch, bw, offset, cch, bw, *(op_chs + i)); + if (rtw_chset_search_ch(ch_set, *(op_chs + i)) == -1) + break; + } + + if (op_ch_num != 0 && i == op_ch_num) + valid = 1; + +exit: + return valid; +} + +/* + * Check the @param ch is fit with setband setting of @param adapter + * @adapter: the given adapter + * @ch: the given channel number + * + * return _TRUE when check valid, _FALSE not valid + */ +bool rtw_mlme_band_check(_adapter *adapter, const u32 ch) +{ + if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */ + || (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */ + || (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */ + ) + return _TRUE; + return _FALSE; +} +inline void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band) +{ + int bs = ATOMIC_READ(&padapter->bandskip); + + bs |= skip_band; + ATOMIC_SET(&padapter->bandskip, bs); +} + +inline void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band) +{ + int bs = ATOMIC_READ(&padapter->bandskip); + + bs &= ~(skip_band); + ATOMIC_SET(&padapter->bandskip, bs); +} +inline int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter) +{ + return ATOMIC_READ(&padapter->bandskip); +} + +#define RTW_IS_SCAN_BAND_SKIP(padapter, skip_band) (ATOMIC_READ(&padapter->bandskip) & (skip_band)) + +bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch) +{ + if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_24G) && ch < 35) /* SKIP 2.4G Band channel */ + return _TRUE; + if (RTW_IS_SCAN_BAND_SKIP(adapter, BAND_5G) && ch > 35) /* SKIP 5G Band channel */ + return _TRUE; + + return _FALSE; +} + +/**************************************************************************** + +Following are the initialization functions for WiFi MLME + +*****************************************************************************/ + +int init_hw_mlme_ext(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + /* set_opmode_cmd(padapter, infra_client_with_mlme); */ /* removed */ + + set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + return _SUCCESS; +} + +void init_mlme_default_rate_set(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + unsigned char mixed_datarate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_, _9M_RATE_, _12M_RATE_, _18M_RATE_, _24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_, 0xff}; + unsigned char mixed_basicrate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_, _12M_RATE_, _24M_RATE_, 0xff,}; + unsigned char supported_mcs_set[16] = {0xff, 0xff, 0xff, 0x00, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + + _rtw_memcpy(pmlmeext->datarate, mixed_datarate, NumRates); + _rtw_memcpy(pmlmeext->basicrate, mixed_basicrate, NumRates); + + _rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set)); +} + +static void init_mlme_ext_priv_value(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + ATOMIC_SET(&pmlmeext->event_seq, 0); + pmlmeext->mgnt_seq = 0;/* reset to zero when disconnect at client mode */ + pmlmeext->cur_channel = padapter->registrypriv.channel; + pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + pmlmeext->retry = 0; + + pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode; + + init_mlme_default_rate_set(padapter); + + if (pmlmeext->cur_channel > 14) + pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB; + else + pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB; + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + pmlmeext->sitesurvey_res.channel_idx = 0; + pmlmeext->sitesurvey_res.bss_cnt = 0; + pmlmeext->sitesurvey_res.scan_ch_ms = SURVEY_TO; + pmlmeext->sitesurvey_res.rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; + pmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID; + pmlmeext->scan_abort = _FALSE; + + pmlmeinfo->state = WIFI_FW_NULL_STATE; + pmlmeinfo->reauth_count = 0; + pmlmeinfo->reassoc_count = 0; + pmlmeinfo->link_count = 0; + pmlmeinfo->auth_seq = 0; + pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; + pmlmeinfo->key_index = 0; + pmlmeinfo->iv = 0; + + pmlmeinfo->enc_algo = _NO_PRIVACY_; + pmlmeinfo->authModeToggle = 0; + + _rtw_memset(pmlmeinfo->chg_txt, 0, 128); + + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + pmlmeinfo->preamble_mode = PREAMBLE_AUTO; + + pmlmeinfo->dialogToken = 0; + + pmlmeext->action_public_rxseq = 0xffff; + pmlmeext->action_public_dialog_token = 0xff; +} + +static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set + , struct p2p_channels *channel_list) +{ + struct registry_priv *regsty = adapter_to_regsty(padapter); + + struct p2p_oper_class_map op_class[] = { + { IEEE80211G, 81, 1, 13, 1, BW20 }, + { IEEE80211G, 82, 14, 14, 1, BW20 }, + { IEEE80211A, 115, 36, 48, 4, BW20 }, + { IEEE80211A, 116, 36, 44, 8, BW40PLUS }, + { IEEE80211A, 117, 40, 48, 8, BW40MINUS }, + { IEEE80211A, 124, 149, 161, 4, BW20 }, + { IEEE80211A, 125, 149, 169, 4, BW20 }, + { IEEE80211A, 126, 149, 157, 8, BW40PLUS }, + { IEEE80211A, 127, 153, 161, 8, BW40MINUS }, + { -1, 0, 0, 0, 0, BW20 } + }; + + int cla, op; + + cla = 0; + + for (op = 0; op_class[op].op_class; op++) { + u8 ch; + struct p2p_oper_class_map *o = &op_class[op]; + struct p2p_reg_class *reg = NULL; + + for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { + if (rtw_chset_search_ch(channel_set, ch) == -1) + continue; + + if ((0 == padapter->registrypriv.ht_enable) && (8 == o->inc)) + continue; + + if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) && + ((BW40MINUS == o->bw) || (BW40PLUS == o->bw))) + continue; + + if (reg == NULL) { + reg = &channel_list->reg_class[cla]; + cla++; + reg->reg_class = o->op_class; + reg->channels = 0; + } + reg->channel[reg->channels] = ch; + reg->channels++; + } + } + channel_list->reg_classes = cla; + +} + +bool rtw_regsty_is_excl_chs(struct registry_priv *regsty, u8 ch) +{ + int i; + + for (i = 0; i < MAX_CHANNEL_NUM; i++) { + if (regsty->excl_chs[i] == 0) + break; + if (regsty->excl_chs[i] == ch) + return _TRUE; + } + return _FALSE; +} + +static u8 init_channel_set(_adapter *padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) +{ + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 index, chanset_size = 0; + u8 b5GBand = _FALSE, b2_4GBand = _FALSE; + u8 Index2G = 0, Index5G = 0; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + int i; + + if (!rtw_is_channel_plan_valid(ChannelPlan)) { + RTW_ERR("ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan); + return chanset_size; + } + + _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO) * MAX_CHANNEL_NUM); + + if (IsSupported24G(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_2G)) + b2_4GBand = _TRUE; + + if (is_supported_5g(regsty->wireless_mode) && hal_chk_band_cap(padapter, BAND_CAP_5G)) + b5GBand = _TRUE; + + if (b2_4GBand == _FALSE && b5GBand == _FALSE) { + RTW_WARN("HW band_cap has no intersection with SW wireless_mode setting\n"); + return chanset_size; + } + + if (b2_4GBand) { + if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) + Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G; + else + Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G; + + for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan2G[Index2G]); index++) { + if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index)) == _TRUE) + continue; + + if (chanset_size >= MAX_CHANNEL_NUM) { + RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); + break; + } + + channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan2G[Index2G], index); + + if (RTW_CHPLAN_GLOBAL_DOAMIN == ChannelPlan + || RTW_CHPLAN_GLOBAL_NULL == ChannelPlan + ) { + /* Channel 1~11 is active, and 12~14 is passive */ + if (channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else if ((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else if (RTW_CHPLAN_WORLD_WIDE_13 == ChannelPlan + || RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan + || RTW_RD_2G_WORLD == Index2G + ) { + /* channel 12~13, passive scan */ + if (channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + + chanset_size++; + } + } + + if (b5GBand) { + if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) + Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G; + else + Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G; + + for (index = 0; index < CH_LIST_LEN(RTW_ChannelPlan5G[Index5G]); index++) { + if (rtw_regsty_is_excl_chs(regsty, CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index)) == _TRUE) + continue; + if (rtw_is_dfs_ch(CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index))) + continue; + + if (chanset_size >= MAX_CHANNEL_NUM) { + RTW_WARN("chset size can't exceed MAX_CHANNEL_NUM(%u)\n", MAX_CHANNEL_NUM); + break; + } + + channel_set[chanset_size].ChannelNum = CH_LIST_CH(RTW_ChannelPlan5G[Index5G], index); + + if ((ChannelPlan == RTW_CHPLAN_WORLD_WIDE_5G) /* all channels passive */ + || (rtw_is_5g_band1(channel_set[chanset_size].ChannelNum) + && rtw_rd_5g_band1_passive(Index5G)) /* band1 passive */ + || (rtw_is_5g_band4(channel_set[chanset_size].ChannelNum) + && rtw_rd_5g_band4_passive(Index5G)) /* band4 passive */ + || (rtw_is_dfs_ch(channel_set[chanset_size].ChannelNum)) /* DFS channel(band2, 3) passive */ + ) + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + + chanset_size++; + } + } + + + if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) { + hal_data->Regulation2_4G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; + hal_data->Regulation5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; + } else { + hal_data->Regulation2_4G = RTW_ChannelPlanMap[ChannelPlan].regd; + hal_data->Regulation5G = RTW_ChannelPlanMap[ChannelPlan].regd; + } + + if (chanset_size) + RTW_INFO(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n" + , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size); + else + RTW_WARN(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, final chset has no channel\n" + , FUNC_ADPT_ARG(padapter), ChannelPlan); + + return chanset_size; +} + +void init_mlme_ext_timer(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + rtw_init_timer(&pmlmeext->survey_timer, padapter, survey_timer_hdl, padapter); + rtw_init_timer(&pmlmeext->link_timer, padapter, link_timer_hdl, padapter); +} + +int init_mlme_ext_priv(_adapter *padapter) +{ + int res = _SUCCESS; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ + /* _rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); */ + + pmlmeext->padapter = padapter; + + /* fill_fwpriv(padapter, &(pmlmeext->fwpriv)); */ + + init_mlme_ext_priv_value(padapter); + pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq; + + init_mlme_ext_timer(padapter); + + init_mlme_ap_info(padapter); + + pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan, pmlmeext->channel_set); + init_channel_list(padapter, pmlmeext->channel_set, &pmlmeext->channel_list); + pmlmeext->last_scan_time = 0; + pmlmeext->mlmeext_init = _TRUE; + + pmlmeext->active_keep_alive_check = _TRUE; + + + return res; + +} + +void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext) +{ + _adapter *padapter = pmlmeext->padapter; + + if (!padapter) + return; + + if (rtw_is_drv_stopped(padapter)) { + _cancel_timer_ex(&pmlmeext->survey_timer); + _cancel_timer_ex(&pmlmeext->link_timer); + } +} + +static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame) +{ + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 *pframe = precv_frame->u.hdr.rx_data; + + if (ptable->func) { + /* receive the frames that ra(a1) is my address or ra(a1) is bc address. */ + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && + !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) + return; + + ptable->func(padapter, precv_frame); + } + +} + +void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) +{ + int index; + struct mlme_handler *ptable; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(pframe)); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + if (GetFrameType(pframe) != WIFI_MGT_TYPE) { + return; + } + + /* receive the frames that ra(a1) is my address or ra(a1) is bc address. */ + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && + !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) + return; + + ptable = mlme_sta_tbl; + + index = get_frame_sub_type(pframe) >> 4; + + if (index >= (sizeof(mlme_sta_tbl) / sizeof(struct mlme_handler))) { + return; + } + ptable += index; + + if (psta != NULL) { + if (GetRetry(pframe)) { + if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) { + /* drop the duplicate management frame */ + pdbgpriv->dbg_rx_dup_mgt_frame_drop_count++; + RTW_INFO("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num); + return; + } + } + psta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num; + } + + switch (get_frame_sub_type(pframe)) { + case WIFI_AUTH: + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + ptable->func = &OnAuth; + else + ptable->func = &OnAuthClient; + /* pass through */ + case WIFI_ASSOCREQ: + case WIFI_REASSOCREQ: + _mgt_dispatcher(padapter, ptable, precv_frame); + break; + case WIFI_PROBEREQ: + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + _mgt_dispatcher(padapter, ptable, precv_frame); + } else + _mgt_dispatcher(padapter, ptable, precv_frame); + break; + case WIFI_BEACON: + _mgt_dispatcher(padapter, ptable, precv_frame); + break; + case WIFI_ACTION: + /* if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) */ + _mgt_dispatcher(padapter, ptable, precv_frame); + break; + default: + _mgt_dispatcher(padapter, ptable, precv_frame); + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_hostapd_mlme_rx(padapter, precv_frame); + break; + } + +} + +u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da) +{ + bool response = _TRUE; + + if (padapter->wdinfo.driver_interface == DRIVER_WEXT) { + /* do nothing if the device name is empty */ + if (!padapter->wdinfo.device_name_len) + response = _FALSE; + } + + if (response == _TRUE) + issue_probersp_p2p(padapter, da); + + return _SUCCESS; +} + +/**************************************************************************** + +Following are the callback functions for each subtype of the management frames + +*****************************************************************************/ + +unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int ielen; + unsigned char *p; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur = &(pmlmeinfo->network); + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + u8 is_valid_p2p_probereq = _FALSE; + + + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + u8 wifi_test_chk_rate = 1; + + + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && + !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) && + !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && + !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) && + !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + ) { + /* Commented by Albert 2011/03/17 */ + /* mcs_rate = 0->CCK 1M rate */ + /* mcs_rate = 1->CCK 2M rate */ + /* mcs_rate = 2->CCK 5.5M rate */ + /* mcs_rate = 3->CCK 11M rate */ + /* In the P2P mode, the driver should not support the CCK rate */ + + /* Commented by Kurt 2012/10/16 */ + /* IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client */ + if (padapter->registrypriv.wifi_spec == 1) { + if (pattrib->data_rate <= 3) + wifi_test_chk_rate = 0; + } + + if (wifi_test_chk_rate == 1) { + is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len); + if (is_valid_p2p_probereq == _TRUE) { + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) { + /* FIXME */ + if (padapter->wdinfo.driver_interface == DRIVER_WEXT) + report_survey_event(padapter, precv_frame); + + p2p_listen_state_process(padapter, get_sa(pframe)); + + return _SUCCESS; + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + goto _continue; + } + } + } + +_continue: + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + return _SUCCESS; + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE && + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == _FALSE) + return _SUCCESS; + + /* RTW_INFO("+OnProbeReq\n"); */ + + + + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + /* check (wildcard) SSID */ + if (p != NULL) { + if (is_valid_p2p_probereq == _TRUE) + goto _issue_probersp; + + if ((ielen != 0 && _FALSE == _rtw_memcmp((void *)(p + 2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) + || (ielen == 0 && pmlmeinfo->hidden_ssid_mode) + ) + return _SUCCESS; + +_issue_probersp: + if (((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && + pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) { + /* RTW_INFO("+issue_probersp during ap mode\n"); */ + issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq); + } + + } + + return _SUCCESS; + +} + +unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) +{ + struct sta_info *psta; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { + if (_TRUE == pwdinfo->tx_prov_disc_info.benable) { + if (_rtw_memcmp(pwdinfo->tx_prov_disc_info.peerIFAddr, get_addr2_ptr(pframe), ETH_ALEN)) { + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { + pwdinfo->tx_prov_disc_info.benable = _FALSE; + issue_p2p_provision_request(padapter, + pwdinfo->tx_prov_disc_info.ssid.Ssid, + pwdinfo->tx_prov_disc_info.ssid.SsidLength, + pwdinfo->tx_prov_disc_info.peerDevAddr); + } else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + pwdinfo->tx_prov_disc_info.benable = _FALSE; + issue_p2p_provision_request(padapter, + NULL, + 0, + pwdinfo->tx_prov_disc_info.peerDevAddr); + } + } + } + return _SUCCESS; + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) { + if (_TRUE == pwdinfo->nego_req_info.benable) { + RTW_INFO("[%s] P2P State is GONEGO ING!\n", __FUNCTION__); + if (_rtw_memcmp(pwdinfo->nego_req_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN)) { + pwdinfo->nego_req_info.benable = _FALSE; + issue_p2p_GO_request(padapter, pwdinfo->nego_req_info.peerDevAddr); + } + } + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) { + if (_TRUE == pwdinfo->invitereq_info.benable) { + RTW_INFO("[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__); + if (_rtw_memcmp(pwdinfo->invitereq_info.peer_macaddr, get_addr2_ptr(pframe), ETH_ALEN)) { + pwdinfo->invitereq_info.benable = _FALSE; + issue_p2p_invitation_request(padapter, pwdinfo->invitereq_info.peer_macaddr); + } + } + } + + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + rtw_mi_report_survey_event(padapter, precv_frame); + return _SUCCESS; + } + + return _SUCCESS; +} + +/* for 11n Logo 4.2.31/4.2.32 */ +static void rtw_check_legacy_ap(_adapter *padapter, u8 *pframe, u32 len) +{ + + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (!padapter->registrypriv.wifi_spec) + return; + + if(!MLME_IS_AP(padapter)) + return; + + + if (pmlmeext->bstart_bss == _TRUE) { + int left; + u16 capability; + unsigned char *pos; + struct rtw_ieee802_11_elems elems; + struct HT_info_element *pht_info = NULL; + u16 cur_op_mode; + + /* checking IEs */ + left = len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_; + pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_; + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) { + RTW_INFO("%s: parse fail for "MAC_FMT"\n", __func__, MAC_ARG(GetAddr3Ptr(pframe))); + return; + } + + cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK; + + /* for legacy ap */ + if (elems.ht_capabilities == NULL && elems.ht_capabilities_len == 0) { + + if (0) + RTW_INFO("%s: "MAC_FMT" is legacy ap\n", __func__, MAC_ARG(GetAddr3Ptr(pframe))); + + ATOMIC_SET(&pmlmepriv->olbc, _TRUE); + ATOMIC_SET(&pmlmepriv->olbc_ht, _TRUE); + } + + } +} + +unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) +{ + struct sta_info *psta; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + WLAN_BSSID_EX *pbss; + int ret = _SUCCESS; + u8 *p = NULL; + u32 ielen = 0; + + if (validate_beacon_len(pframe, len) == _FALSE) + return _SUCCESS; + p = rtw_get_ie(pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ielen, + precv_frame->u.hdr.len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_); + if ((p != NULL) && (ielen > 0)) { + if ((*(p + 1 + ielen) == 0x2D) && (*(p + 2 + ielen) != 0x2D)) { + /* Invalid value 0x2D is detected in Extended Supported Rates (ESR) IE. Try to fix the IE length to avoid failed Beacon parsing. */ + RTW_INFO("[WIFIDBG] Error in ESR IE is detected in Beacon of BSSID:"MAC_FMT". Fix the length of ESR IE to avoid failed Beacon parsing.\n", MAC_ARG(GetAddr3Ptr(pframe))); + *(p + 1) = ielen - 1; + } + } + + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + rtw_mi_report_survey_event(padapter, precv_frame); + return _SUCCESS; + } + + rtw_check_legacy_ap(padapter, pframe, len); + + if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) { + if ((pmlmeinfo->state & WIFI_FW_AUTH_NULL) + && rtw_sta_linking_test_wait_done() + ) { + if (rtw_sta_linking_test_force_fail()) { + set_link_timer(pmlmeext, 1); + return _SUCCESS; + } + + /* we should update current network before auth, or some IE is wrong */ + pbss = (WLAN_BSSID_EX *)rtw_malloc(sizeof(WLAN_BSSID_EX)); + if (pbss) { + if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) { + struct beacon_keys recv_beacon; + + update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); + rtw_get_bcn_info(&(pmlmepriv->cur_network)); + + /* update bcn keys */ + if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) { + RTW_INFO("%s: beacon keys ready\n", __func__); + _rtw_memcpy(&pmlmepriv->cur_beacon_keys, + &recv_beacon, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } else { + RTW_ERR("%s: get beacon keys failed\n", __func__); + _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } + } + rtw_mfree((u8 *)pbss, sizeof(WLAN_BSSID_EX)); + } + + /* check the vendor of the assoc AP */ + pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe + sizeof(struct rtw_ieee80211_hdr_3addr), len - sizeof(struct rtw_ieee80211_hdr_3addr)); + + /* update TSF Value */ + update_TSF(pmlmeext, pframe, len); + + /* reset for adaptive_early_32k */ + pmlmeext->adaptive_tsf_done = _FALSE; + pmlmeext->DrvBcnEarly = 0xff; + pmlmeext->DrvBcnTimeOut = 0xff; + pmlmeext->bcn_cnt = 0; + _rtw_memset(pmlmeext->bcn_delay_cnt, 0, sizeof(pmlmeext->bcn_delay_cnt)); + _rtw_memset(pmlmeext->bcn_delay_ratio, 0, sizeof(pmlmeext->bcn_delay_ratio)); + + /* Comment by YiWei , in wifi p2p spec the "3.3 P2P Power Management" , "These mechanisms are available in a P2P Group in which only P2P Devices are associated." */ + /* process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); */ + + + /* start auth */ + start_clnt_auth(padapter); + + return _SUCCESS; + } + + if (((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta != NULL) { +#ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL + /* Merge from 8712 FW code */ + if (cmp_pkt_chnl_diff(padapter, pframe, len) != 0) { + /* join wrong channel, deauth and reconnect */ + issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING); + + report_del_sta_event(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL, _TRUE, _FALSE); + pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS); + return _SUCCESS; + } +#endif /* CONFIG_PATCH_JOIN_WRONG_CHANNEL */ + + ret = rtw_check_bcn_info(padapter, pframe, len); + if (!ret) { + RTW_PRINT("ap has changed, disconnect now\n "); + receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE); + return _SUCCESS; + } + /* update WMM, ERP in the beacon */ + /* todo: the timer is used instead of the number of the beacon received */ + if ((sta_rx_pkts(psta) & 0xf) == 0) { + /* RTW_INFO("update_bcn_info\n"); */ + update_beacon_info(padapter, pframe, len, psta); + } + + pmlmepriv->cur_network_scanned->network.Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; + + adaptive_early_32k(pmlmeext, pframe, len); + + + process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); + + if (pmlmeext->en_hw_update_tsf) + rtw_enable_hw_update_tsf_cmd(padapter); + + } + + } else if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + _irqL irqL; + u8 rate_set[16]; + u8 rate_num = 0; + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta != NULL) { + /* + * update WMM, ERP in the beacon + * todo: the timer is used instead of the number of the beacon received + */ + if ((sta_rx_pkts(psta) & 0xf) == 0) + update_beacon_info(padapter, pframe, len, psta); + + if (pmlmeext->en_hw_update_tsf) + rtw_enable_hw_update_tsf_cmd(padapter); + } else { + rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num); + if (rate_num == 0) { + RTW_INFO(FUNC_ADPT_FMT" RX beacon with no supported rate\n", FUNC_ADPT_ARG(padapter)); + goto _END_ONBEACON_; + } + + psta = rtw_alloc_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta == NULL) { + RTW_INFO(FUNC_ADPT_FMT" Exceed the upper limit of supported clients\n", FUNC_ADPT_ARG(padapter)); + goto _END_ONBEACON_; + } + + psta->expire_to = pstapriv->adhoc_expire_to; + + _rtw_memcpy(psta->bssrateset, rate_set, rate_num); + psta->bssratelen = rate_num; + + /* update TSF Value */ + update_TSF(pmlmeext, pframe, len); + + /* report sta add event */ + report_add_sta_event(padapter, get_addr2_ptr(pframe)); + } + } + } + +_END_ONBEACON_: + + return _SUCCESS; + +} + +unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) +{ + _irqL irqL; + unsigned int auth_mode, seq, ie_len; + unsigned char *sa, *p; + u16 algorithm; + int status; + static struct sta_info stat; + struct sta_info *pstat = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + u8 offset = 0; + + + if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + return _FAIL; + + RTW_INFO("+OnAuth\n"); + + sa = get_addr2_ptr(pframe); + + auth_mode = psecuritypriv->dot11AuthAlgrthm; + + if (GetPrivacy(pframe)) { + u8 *iv; + struct rx_pkt_attrib *prxattrib = &(precv_frame->u.hdr.attrib); + + prxattrib->hdrlen = WLAN_HDR_A3_LEN; + prxattrib->encrypt = _WEP40_; + + iv = pframe + prxattrib->hdrlen; + prxattrib->key_index = ((iv[3] >> 6) & 0x3); + + prxattrib->iv_len = 4; + prxattrib->icv_len = 4; + + rtw_wep_decrypt(padapter, (u8 *)precv_frame); + + offset = 4; + } + + algorithm = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset)); + seq = le16_to_cpu(*(u16 *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2)); + + RTW_INFO("auth alg=%x, seq=%X\n", algorithm, seq); + + if (auth_mode == 2 && + psecuritypriv->dot11PrivacyAlgrthm != _WEP40_ && + psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) + auth_mode = 0; + + if ((algorithm > 0 && auth_mode == 0) || /* rx a shared-key auth but shared not enabled */ + (algorithm == 0 && auth_mode == 1)) { /* rx a open-system auth but shared-key is enabled */ + RTW_INFO("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n", + algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]); + + status = _STATS_NO_SUPP_ALG_; + + goto auth_fail; + } + + if (rtw_access_ctrl(padapter, sa) == _FALSE) { + status = _STATS_UNABLE_HANDLE_STA_; + goto auth_fail; + } + + pstat = rtw_get_stainfo(pstapriv, sa); + if (pstat == NULL) { + + /* allocate a new one */ + RTW_INFO("going to alloc stainfo for sa="MAC_FMT"\n", MAC_ARG(sa)); + pstat = rtw_alloc_stainfo(pstapriv, sa); + if (pstat == NULL) { + RTW_INFO(" Exceed the upper limit of supported clients...\n"); + status = _STATS_UNABLE_HANDLE_STA_; + goto auth_fail; + } + + pstat->state = WIFI_FW_AUTH_NULL; + pstat->auth_seq = 0; + + /* pstat->flags = 0; */ + /* pstat->capability = 0; */ + } else { + { + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&pstat->asoc_list) == _FALSE) { + rtw_list_delete(&pstat->asoc_list); + pstapriv->asoc_list_cnt--; + if (pstat->expire_to > 0) + ;/* TODO: STA re_auth within expire_to */ + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + if (seq == 1) + ; /* TODO: STA re_auth and auth timeout */ + + } + } + + { + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + if (rtw_is_list_empty(&pstat->auth_list)) { + + rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list); + pstapriv->auth_list_cnt++; + } + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + } + + if (pstat->auth_seq == 0) + pstat->expire_to = pstapriv->auth_to; + + if ((pstat->auth_seq + 1) != seq) { + RTW_INFO("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", + seq, pstat->auth_seq + 1); + status = _STATS_OUT_OF_AUTH_SEQ_; + goto auth_fail; + } + + if (algorithm == 0 && (auth_mode == 0 || auth_mode == 2 || auth_mode == 3)) { + if (seq == 1) { + { + pstat->state &= ~WIFI_FW_AUTH_NULL; + pstat->state |= WIFI_FW_AUTH_SUCCESS; + pstat->expire_to = pstapriv->assoc_to; + } + pstat->authalg = algorithm; + } else { + RTW_INFO("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", + seq, pstat->auth_seq + 1); + status = _STATS_OUT_OF_AUTH_SEQ_; + goto auth_fail; + } + } else { /* shared system or auto authentication */ + if (seq == 1) { + /* prepare for the challenging txt... */ + + /* get_random_bytes((void *)pstat->chg_txt, 128); */ /* TODO: */ + _rtw_memset((void *)pstat->chg_txt, 78, 128); + { + pstat->state &= ~WIFI_FW_AUTH_NULL; + pstat->state |= WIFI_FW_AUTH_STATE; + } + pstat->authalg = algorithm; + pstat->auth_seq = 2; + } else if (seq == 3) { + /* checking for challenging txt... */ + RTW_INFO("checking for challenging txt...\n"); + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len, + len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4); + + if ((p == NULL) || (ie_len <= 0)) { + RTW_INFO("auth rejected because challenge failure!(1)\n"); + status = _STATS_CHALLENGE_FAIL_; + goto auth_fail; + } + + if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) { + { + pstat->state &= (~WIFI_FW_AUTH_STATE); + pstat->state |= WIFI_FW_AUTH_SUCCESS; + /* challenging txt is correct... */ + pstat->expire_to = pstapriv->assoc_to; + } + } else { + RTW_INFO("auth rejected because challenge failure!\n"); + status = _STATS_CHALLENGE_FAIL_; + goto auth_fail; + } + } else { + RTW_INFO("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", + seq, pstat->auth_seq + 1); + status = _STATS_OUT_OF_AUTH_SEQ_; + goto auth_fail; + } + } + + /* Now, we are going to issue_auth... */ + pstat->auth_seq = seq + 1; + + issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_)); + + if ((pstat->state & WIFI_FW_AUTH_SUCCESS) || (pstat->state & WIFI_FW_ASSOC_SUCCESS)) + pstat->auth_seq = 0; + + return _SUCCESS; + +auth_fail: + + if (pstat) + rtw_free_stainfo(padapter , pstat); + + pstat = &stat; + _rtw_memset((char *)pstat, '\0', sizeof(stat)); + pstat->auth_seq = 2; + _rtw_memcpy(pstat->hwaddr, sa, 6); + + issue_auth(padapter, pstat, (unsigned short)status); + + return _FAIL; + +} + +unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int seq, len, status, algthm, offset; + unsigned char *p; + unsigned int go2asoc = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + uint pkt_len = precv_frame->u.hdr.len; + + RTW_INFO("%s\n", __FUNCTION__); + + /* check A1 matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) + return _SUCCESS; + + if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE)) + return _SUCCESS; + + offset = (GetPrivacy(pframe)) ? 4 : 0; + + algthm = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset)); + seq = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2)); + status = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4)); + + if (status != 0) { + RTW_INFO("clnt auth fail, status: %d\n", status); + if (status == 13) { /* && pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) */ + if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) + pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; + else + pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; + /* pmlmeinfo->reauth_count = 0; */ + } + + set_link_timer(pmlmeext, 1); + goto authclnt_fail; + } + + if (seq == 2) { + if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) { + /* legendary shared system */ + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len, + pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_); + + if (p == NULL) { + /* RTW_INFO("marc: no challenge text?\n"); */ + goto authclnt_fail; + } + + _rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len); + pmlmeinfo->auth_seq = 3; + issue_auth(padapter, NULL, 0); + set_link_timer(pmlmeext, REAUTH_TO); + + return _SUCCESS; + } else { + /* open, or 802.11r FTAA system */ + go2asoc = 1; + } + } else if (seq == 4) { + if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) + go2asoc = 1; + else + goto authclnt_fail; + } else { + /* this is also illegal */ + /* RTW_INFO("marc: clnt auth failed due to illegal seq=%x\n", seq); */ + goto authclnt_fail; + } + + if (go2asoc) { + + RTW_PRINT("auth success, start assoc\n"); + start_clnt_assoc(padapter); + return _SUCCESS; + } + +authclnt_fail: + + /* pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); */ + + return _FAIL; + +} + +unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) +{ + _irqL irqL; + u16 capab_info, listen_interval; + struct rtw_ieee802_11_elems elems; + struct sta_info *pstat; + unsigned char reassoc, *p, *pos, *wpa_ie; + unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; + int i, ie_len, wpa_ie_len, left; + u8 rate_set[16]; + u8 rate_num; + unsigned short status = _STATS_SUCCESSFUL_; + unsigned short frame_type, ie_offset = 0; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint pkt_len = precv_frame->u.hdr.len; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 p2p_status_code = P2P_STATUS_SUCCESS; + u8 *p2pie; + u32 p2pielen = 0; + + + if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + return _FAIL; + + frame_type = get_frame_sub_type(pframe); + if (frame_type == WIFI_ASSOCREQ) { + reassoc = 0; + ie_offset = _ASOCREQ_IE_OFFSET_; + } else { /* WIFI_REASSOCREQ */ + reassoc = 1; + ie_offset = _REASOCREQ_IE_OFFSET_; + } + + if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) { + RTW_INFO("handle_assoc(reassoc=%d) - too short payload (len=%lu)" + "\n", reassoc, (unsigned long)pkt_len); + return _FAIL; + } + + pstat = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (pstat == (struct sta_info *)NULL) { + status = _RSON_CLS2_; + goto asoc_class2_error; + } + + capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN); + /* capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); */ + /* listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); */ + listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN + 2); + + left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); + pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); + + RTW_INFO("%s\n", __FUNCTION__); + + /* check if this stat has been successfully authenticated/assocated */ + if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) { + if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) { + status = _RSON_CLS2_; + goto asoc_class2_error; + } else { + pstat->state &= (~WIFI_FW_ASSOC_SUCCESS); + pstat->state |= WIFI_FW_ASSOC_STATE; + } + } else { + pstat->state &= (~WIFI_FW_AUTH_SUCCESS); + pstat->state |= WIFI_FW_ASSOC_STATE; + } + + pstat->capability = capab_info; + + /* now parse all ieee802_11 ie to point to elems */ + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed || + !elems.ssid) { + RTW_INFO("STA " MAC_FMT " sent invalid association request\n", + MAC_ARG(pstat->hwaddr)); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + + /* now we should check all the fields... */ + /* checking SSID */ + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len, + pkt_len - WLAN_HDR_A3_LEN - ie_offset); + if (p == NULL) + status = _STATS_FAILURE_; + + if (ie_len == 0) /* broadcast ssid, however it is not allowed in assocreq */ + status = _STATS_FAILURE_; + else { + /* check if ssid match */ + if (!_rtw_memcmp((void *)(p + 2), cur->Ssid.Ssid, cur->Ssid.SsidLength)) + status = _STATS_FAILURE_; + + if (ie_len != cur->Ssid.SsidLength) + status = _STATS_FAILURE_; + } + + if (_STATS_SUCCESSFUL_ != status) + goto OnAssocReqFail; + + rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, rate_set, &rate_num); + if (rate_num == 0) { + RTW_INFO(FUNC_ADPT_FMT" RX assoc-req with no supported rate\n", FUNC_ADPT_ARG(padapter)); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + _rtw_memcpy(pstat->bssrateset, rate_set, rate_num); + pstat->bssratelen = rate_num; + UpdateBrateTblForSoftAP(pstat->bssrateset, pstat->bssratelen); + + /* check RSN/WPA/WPS */ + pstat->dot8021xalg = 0; + pstat->wpa_psk = 0; + pstat->wpa_group_cipher = 0; + pstat->wpa2_group_cipher = 0; + pstat->wpa_pairwise_cipher = 0; + pstat->wpa2_pairwise_cipher = 0; + _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie)); + if ((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { + + int group_cipher = 0, pairwise_cipher = 0; + + wpa_ie = elems.rsn_ie; + wpa_ie_len = elems.rsn_ie_len; + + if (rtw_parse_wpa2_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + pstat->dot8021xalg = 1;/* psk, todo:802.1x */ + pstat->wpa_psk |= BIT(1); + + pstat->wpa2_group_cipher = group_cipher & psecuritypriv->wpa2_group_cipher; + pstat->wpa2_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa2_pairwise_cipher; + + if (!pstat->wpa2_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if (!pstat->wpa2_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + } else + status = WLAN_STATUS_INVALID_IE; + + } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { + + int group_cipher = 0, pairwise_cipher = 0; + + wpa_ie = elems.wpa_ie; + wpa_ie_len = elems.wpa_ie_len; + + if (rtw_parse_wpa_ie(wpa_ie - 2, wpa_ie_len + 2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + pstat->dot8021xalg = 1;/* psk, todo:802.1x */ + pstat->wpa_psk |= BIT(0); + + pstat->wpa_group_cipher = group_cipher & psecuritypriv->wpa_group_cipher; + pstat->wpa_pairwise_cipher = pairwise_cipher & psecuritypriv->wpa_pairwise_cipher; + + if (!pstat->wpa_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if (!pstat->wpa_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + + } else + status = WLAN_STATUS_INVALID_IE; + + } else { + wpa_ie = NULL; + wpa_ie_len = 0; + } + + if (_STATS_SUCCESSFUL_ != status) + goto OnAssocReqFail; + + pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); + /* if (hapd->conf->wps_state && wpa_ie == NULL) { */ /* todo: to check ap if supporting WPS */ + if (wpa_ie == NULL) { + if (elems.wps_ie) { + RTW_INFO("STA included WPS IE in " + "(Re)Association Request - assume WPS is " + "used\n"); + pstat->flags |= WLAN_STA_WPS; + /* wpabuf_free(sta->wps_ie); */ + /* sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, */ + /* elems.wps_ie_len - 4); */ + } else { + RTW_INFO("STA did not include WPA/RSN IE " + "in (Re)Association Request - possible WPS " + "use\n"); + pstat->flags |= WLAN_STA_MAYBE_WPS; + } + + /* AP support WPA/RSN, and sta is going to do WPS, but AP is not ready */ + /* that the selected registrar of AP is _FLASE */ + if ((psecuritypriv->wpa_psk > 0) + && (pstat->flags & (WLAN_STA_WPS | WLAN_STA_MAYBE_WPS))) { + if (pmlmepriv->wps_beacon_ie) { + u8 selected_registrar = 0; + + rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL); + + if (!selected_registrar) { + RTW_INFO("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); + + status = _STATS_UNABLE_HANDLE_STA_; + + goto OnAssocReqFail; + } + } + } + + } else { + int copy_len; + + if (psecuritypriv->wpa_psk == 0) { + RTW_INFO("STA " MAC_FMT ": WPA/RSN IE in association " + "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr)); + + status = WLAN_STATUS_INVALID_IE; + + goto OnAssocReqFail; + + } + + if (elems.wps_ie) { + RTW_INFO("STA included WPS IE in " + "(Re)Association Request - WPS is " + "used\n"); + pstat->flags |= WLAN_STA_WPS; + copy_len = 0; + } else + copy_len = ((wpa_ie_len + 2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)) : (wpa_ie_len + 2); + + if (copy_len > 0) + _rtw_memcpy(pstat->wpa_ie, wpa_ie - 2, copy_len); + + } + + /* check if there is WMM IE & support WWM-PS */ + pstat->flags &= ~WLAN_STA_WME; + pstat->qos_option = 0; + pstat->qos_info = 0; + pstat->has_legacy_ac = _TRUE; + pstat->uapsd_vo = 0; + pstat->uapsd_vi = 0; + pstat->uapsd_be = 0; + pstat->uapsd_bk = 0; + if (pmlmepriv->qospriv.qos_option) { + p = pframe + WLAN_HDR_A3_LEN + ie_offset; + ie_len = 0; + for (;;) { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); + if (p != NULL) { + if (_rtw_memcmp(p + 2, WMM_IE, 6)) { + + pstat->flags |= WLAN_STA_WME; + + pstat->qos_option = 1; + pstat->qos_info = *(p + 8); + + pstat->max_sp_len = (pstat->qos_info >> 5) & 0x3; + + if ((pstat->qos_info & 0xf) != 0xf) + pstat->has_legacy_ac = _TRUE; + else + pstat->has_legacy_ac = _FALSE; + + if (pstat->qos_info & 0xf) { + if (pstat->qos_info & BIT(0)) + pstat->uapsd_vo = BIT(0) | BIT(1); + else + pstat->uapsd_vo = 0; + + if (pstat->qos_info & BIT(1)) + pstat->uapsd_vi = BIT(0) | BIT(1); + else + pstat->uapsd_vi = 0; + + if (pstat->qos_info & BIT(2)) + pstat->uapsd_bk = BIT(0) | BIT(1); + else + pstat->uapsd_bk = 0; + + if (pstat->qos_info & BIT(3)) + pstat->uapsd_be = BIT(0) | BIT(1); + else + pstat->uapsd_be = 0; + + } + + break; + } + } else + break; + p = p + ie_len + 2; + } + } + + if (pmlmepriv->htpriv.ht_option == _FALSE) + goto bypass_ht_chk; + + /* save HT capabilities in the sta object */ + _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); + if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) { + pstat->flags |= WLAN_STA_HT; + + pstat->flags |= WLAN_STA_WME; + + _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); + + } else + pstat->flags &= ~WLAN_STA_HT; +bypass_ht_chk: + + if ((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags & WLAN_STA_HT)) { + rtw_warn_on(1); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + + if (pmlmepriv->vhtpriv.vht_option == _FALSE) + goto bypass_vht_chk; + + _rtw_memset(&pstat->vhtpriv, 0, sizeof(struct vht_priv)); + if (elems.vht_capabilities && elems.vht_capabilities_len == 12) { + pstat->flags |= WLAN_STA_VHT; + + _rtw_memcpy(pstat->vhtpriv.vht_cap, elems.vht_capabilities, 12); + + if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1) + _rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1); + else /* for Frame without Operating Mode notify ie; default: 80M */ + pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; + } else + pstat->flags &= ~WLAN_STA_VHT; +bypass_vht_chk: + + if ((pmlmepriv->vhtpriv.vht_option == _FALSE) && (pstat->flags & WLAN_STA_VHT)) { + rtw_warn_on(1); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + + if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) && + ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) || + (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) { + + RTW_INFO("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->hwaddr)); + + pstat->flags &= ~WLAN_STA_HT; + pstat->flags &= ~WLAN_STA_VHT; + /*status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY; + * goto OnAssocReqFail; + */ + } + + /* + * if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G) */ /* ? */ + pstat->flags |= WLAN_STA_NONERP; + for (i = 0; i < pstat->bssratelen; i++) { + if ((pstat->bssrateset[i] & 0x7f) > 22) { + pstat->flags &= ~WLAN_STA_NONERP; + break; + } + } + + if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) + pstat->flags |= WLAN_STA_SHORT_PREAMBLE; + else + pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE; + + if (status != _STATS_SUCCESSFUL_) + goto OnAssocReqFail; + + pstat->is_p2p_device = _FALSE; + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen); + if (p2pie) { + pstat->is_p2p_device = _TRUE; + p2p_status_code = (u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat); + if (p2p_status_code > 0) { + pstat->p2p_status_code = p2p_status_code; + status = _STATS_CAP_FAIL_; + goto OnAssocReqFail; + } + } + rtw_process_wfd_ies(padapter, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, __func__); + } + pstat->p2p_status_code = p2p_status_code; + + /* TODO: identify_proprietary_vendor_ie(); */ + /* Realtek proprietary IE */ + /* identify if this is Broadcom sta */ + /* identify if this is ralink sta */ + /* Customer proprietary IE */ + + /* get a unique AID */ + if (pstat->aid > 0) + RTW_INFO(" old AID %d\n", pstat->aid); + else { + for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) { + if (pstapriv->sta_aid[pstat->aid - 1] == NULL) { + if (pstat->aid > pstapriv->max_num_sta) { + pstat->aid = 0; + + RTW_INFO(" no room for more AIDs\n"); + + status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; + + goto OnAssocReqFail; + + } else { + pstapriv->sta_aid[pstat->aid - 1] = pstat; + RTW_INFO("allocate new AID = (%d)\n", pstat->aid); + break; + } + } + } + } + + pstat->state &= (~WIFI_FW_ASSOC_STATE); + pstat->state |= WIFI_FW_ASSOC_SUCCESS; + /* RTW_INFO("==================%s, %d, (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n" + , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->hwaddr)); */ + { + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + if (!rtw_is_list_empty(&pstat->auth_list)) { + rtw_list_delete(&pstat->auth_list); + pstapriv->auth_list_cnt--; + } + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&pstat->asoc_list)) { + pstat->expire_to = pstapriv->expire_to; + rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list); + pstapriv->asoc_list_cnt++; + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + } + + /* now the station is qualified to join our BSS... */ + if (pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_ == status)) { + { + /* .1 bss_cap_update & sta_info_update */ + bss_cap_update_on_sta_join(padapter, pstat); + sta_info_update(padapter, pstat); + } + /* .2 issue assoc rsp before notify station join event. */ + if (frame_type == WIFI_ASSOCREQ) + issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); + else + issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); + + { + /* .3-(1) report sta add event */ + report_add_sta_event(padapter, pstat->hwaddr); + } + } + + return _SUCCESS; + +asoc_class2_error: + + issue_deauth(padapter, (void *)get_addr2_ptr(pframe), status); + + return _FAIL; + +OnAssocReqFail: + + pstat->aid = 0; + if (frame_type == WIFI_ASSOCREQ) + issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); + else + issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); + + + return _FAIL; + +} + +unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) +{ + uint i; + int res; + unsigned short status; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ + u8 *pframe = precv_frame->u.hdr.rx_data; + uint pkt_len = precv_frame->u.hdr.len; + PNDIS_802_11_VARIABLE_IEs pWapiIE = NULL; + + RTW_INFO("%s\n", __FUNCTION__); + + /* check A1 matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) + return _SUCCESS; + + if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE))) + return _SUCCESS; + + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + return _SUCCESS; + + _cancel_timer_ex(&pmlmeext->link_timer); + + /* status */ + status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2)); + if (status > 0) { + RTW_INFO("assoc reject, status code: %d\n", status); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + res = -4; + goto report_assoc_result; + } + + /* get capabilities */ + pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + + /* set slot time */ + pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10)) ? 9 : 20; + + /* AID */ + res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4)) & 0x3fff); + + /* following are moved to join event callback function */ + /* to handle HT, WMM, rate adaptive, update MAC reg */ + /* for not to handle the synchronous IO in the tasklet */ + for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) /* WMM */ + WMM_param_handler(padapter, pIE); + else if (_rtw_memcmp(pIE->data, WFD_OUI, 4)) /* WFD */ + rtw_process_wfd_ie(padapter, (u8 *)pIE, pIE->Length, __func__); + break; + + case _HT_CAPABILITY_IE_: /* HT caps */ + HT_caps_handler(padapter, pIE); + break; + + case _HT_EXTRA_INFO_IE_: /* HT info */ + HT_info_handler(padapter, pIE); + break; + + case EID_VHTCapability: + VHT_caps_handler(padapter, pIE); + break; + + case EID_VHTOperation: + VHT_operation_handler(padapter, pIE); + break; + + case _ERPINFO_IE_: + ERP_IE_handler(padapter, pIE); + break; + default: + break; + } + + i += (pIE->Length + 2); + } + + pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE); + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + + /* Update Basic Rate Table for spec, 2010-12-28 , by thomas */ + UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates); + +report_assoc_result: + if (res > 0) + rtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len); + else + rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); + + report_join_res(padapter, res); + + return _SUCCESS; +} + +unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned short reason; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + /* check A3 */ + if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) + return _SUCCESS; + + RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter)); + + if (pwdinfo->rx_invitereq_info.scan_op_ch_only) { + _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); + _set_timer(&pwdinfo->reset_ch_sitesurvey, 10); + } + + reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + + rtw_lock_rx_suspend_timeout(8000); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + _irqL irqL; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* rtw_free_stainfo(padapter, psta); */ + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + + RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta) { + u8 updated = _FALSE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE); + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + } + + return _SUCCESS; + } else + { + int ignore_received_deauth = 0; + + /* Commented by Albert 20130604 */ + /* Before sending the auth frame to start the STA/GC mode connection with AP/GO, */ + /* we will send the deauth first. */ + /* However, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth. */ + /* Added the following code to avoid this case. */ + if ((pmlmeinfo->state & WIFI_FW_AUTH_STATE) || + (pmlmeinfo->state & WIFI_FW_ASSOC_STATE)) { + if (reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA) + ignore_received_deauth = 1; + else if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) { + /* TODO: 802.11r */ + ignore_received_deauth = 1; + } + } + + RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n" + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe), ignore_received_deauth); + + if (0 == ignore_received_deauth) + receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE); + } + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + return _SUCCESS; + +} + +unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned short reason; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + /* check A3 */ + if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) + return _SUCCESS; + + RTW_INFO(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter)); + + if (pwdinfo->rx_invitereq_info.scan_op_ch_only) { + _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); + _set_timer(&pwdinfo->reset_ch_sitesurvey, 10); + } + + reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + + rtw_lock_rx_suspend_timeout(8000); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + _irqL irqL; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + /* rtw_free_stainfo(padapter, psta); */ + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */ + + RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta) { + u8 updated = _FALSE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE); + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + } + + return _SUCCESS; + } else + { + RTW_PRINT(FUNC_ADPT_FMT" reason=%u, ta=%pM\n" + , FUNC_ADPT_ARG(padapter), reason, get_addr2_ptr(pframe)); + + receive_disconnect(padapter, get_addr2_ptr(pframe), reason, _FALSE); + } + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + return _SUCCESS; + +} + +unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame) +{ + RTW_INFO("%s\n", __FUNCTION__); + return _SUCCESS; +} + +unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len) +{ + unsigned int ret = _FAIL; + struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(mlmeext->mlmext_info); + + if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { + ret = _SUCCESS; + goto exit; + } + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { + + int ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1; + int ch_offset = -1; + u8 bwmode; + struct ieee80211_info_element *ie; + + RTW_INFO(FUNC_NDEV_FMT" from "MAC_FMT"\n", + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->hwaddr)); + + for_each_ie(ie, ies, ies_len) { + if (ie->id == WLAN_EID_CHANNEL_SWITCH) { + ch_switch_mode = ie->data[0]; + ch = ie->data[1]; + ch_switch_cnt = ie->data[2]; + RTW_INFO("ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\n", + ch_switch_mode, ch, ch_switch_cnt); + } else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) { + ch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]); + RTW_INFO("ch_offset:%d\n", ch_offset); + } + } + + if (ch == -1) + return _SUCCESS; + + if (ch_offset == -1) + bwmode = mlmeext->cur_bwmode; + else + bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ? + CHANNEL_WIDTH_20 : CHANNEL_WIDTH_40; + + ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset; + + /* todo: + * 1. the decision of channel switching + * 2. things after channel switching + */ + + ret = rtw_set_ch_cmd(padapter, ch, bwmode, ch_offset, _TRUE); + } + +exit: + return ret; +} + +unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 category; + u8 action; + + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + + if (!psta) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT) + goto exit; + + action = frame_body[1]; + +exit: + return ret; +} + +unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} + +unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} + +/** + * rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter + * @adapter: the adapter to get target RX AMPDU buffer size + * + * Returns: the target RX AMPDU buffer size + */ +u8 rtw_rx_ampdu_size(_adapter *adapter) +{ + u8 size; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; + + if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) { + size = rtw_btcoex_GetAMPDUSize(adapter); + goto exit; + } + + /* for scan */ + if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE) + && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE) + && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size != RX_AMPDU_SIZE_INVALID + ) { + size = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size; + goto exit; + } + + /* default value based on max_rx_ampdu_factor */ + if (adapter->driver_rx_ampdu_factor != 0xFF) + max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor; + else + rtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + + /* In Maximum A-MPDU Length Exponent subfield of A-MPDU Parameters field of HT Capabilities element, + the unit of max_rx_ampdu_factor are octets. 8K, 16K, 32K, 64K is right. + But the buffer size subfield of Block Ack Parameter Set field in ADDBA action frame indicates + the number of buffers available for this particular TID. Each buffer is equal to max. size of + MSDU or AMSDU. + The size variable means how many MSDUs or AMSDUs, it's not Kbytes. + */ + if (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor) + size = 64; + else if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor) + size = 32; + else if (MAX_AMPDU_FACTOR_16K == max_rx_ampdu_factor) + size = 16; + else if (MAX_AMPDU_FACTOR_8K == max_rx_ampdu_factor) + size = 8; + else + size = 64; + +exit: + + if (size > 127) + size = 127; + + return size; +} + +/** + * rtw_rx_ampdu_is_accept - Get the permission if RX AMPDU should be set up for the specific @adapter + * @adapter: the adapter to get the permission if RX AMPDU should be set up + * + * Returns: accept or not + */ +bool rtw_rx_ampdu_is_accept(_adapter *adapter) +{ + bool accept; + + if (adapter->fix_rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID) { + accept = adapter->fix_rx_ampdu_accept; + goto exit; + } + + if (rtw_btcoex_IsBTCoexRejectAMPDU(adapter) == _TRUE) { + accept = _FALSE; + goto exit; + } + + /* for scan */ + if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE) + && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE) + && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID + ) { + accept = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept; + goto exit; + } + + /* default value for other cases */ + accept = adapter->mlmeextpriv.mlmext_info.bAcceptAddbaReq; + +exit: + return accept; +} + +/** + * rtw_rx_ampdu_set_size - Set the target RX AMPDU buffer size for the specific @adapter and specific @reason + * @adapter: the adapter to set target RX AMPDU buffer size + * @size: the target RX AMPDU buffer size to set + * @reason: reason for the target RX AMPDU buffer size setting + * + * Returns: whether the target RX AMPDU buffer size is changed + */ +bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason) +{ + bool is_adj = _FALSE; + struct mlme_ext_priv *mlmeext; + struct mlme_ext_info *mlmeinfo; + + mlmeext = &adapter->mlmeextpriv; + mlmeinfo = &mlmeext->mlmext_info; + + if (reason == RX_AMPDU_DRV_FIXED) { + if (adapter->fix_rx_ampdu_size != size) { + adapter->fix_rx_ampdu_size = size; + is_adj = _TRUE; + RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size); + } + } else if (reason == RX_AMPDU_DRV_SCAN) { + struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; + + if (ss->rx_ampdu_size != size) { + ss->rx_ampdu_size = size; + is_adj = _TRUE; + RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size); + } + } + + return is_adj; +} + +/** + * rtw_rx_ampdu_set_accept - Set the permission if RX AMPDU should be set up for the specific @adapter and specific @reason + * @adapter: the adapter to set if RX AMPDU should be set up + * @accept: if RX AMPDU should be set up + * @reason: reason for the permission if RX AMPDU should be set up + * + * Returns: whether the permission if RX AMPDU should be set up is changed + */ +bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason) +{ + bool is_adj = _FALSE; + struct mlme_ext_priv *mlmeext; + struct mlme_ext_info *mlmeinfo; + + mlmeext = &adapter->mlmeextpriv; + mlmeinfo = &mlmeext->mlmext_info; + + if (reason == RX_AMPDU_DRV_FIXED) { + if (adapter->fix_rx_ampdu_accept != accept) { + adapter->fix_rx_ampdu_accept = accept; + is_adj = _TRUE; + RTW_INFO(FUNC_ADPT_FMT" fix_rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept); + } + } else if (reason == RX_AMPDU_DRV_SCAN) { + if (adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != accept) { + adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept = accept; + is_adj = _TRUE; + RTW_INFO(FUNC_ADPT_FMT" ss.rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept); + } + } + + return is_adj; +} + +/** + * rx_ampdu_apply_sta_tid - Apply RX AMPDU setting to the specific @sta and @tid + * @adapter: the adapter to which @sta belongs + * @sta: the sta to be checked + * @tid: the tid to be checked + * @accept: the target permission if RX AMPDU should be set up + * @size: the target RX AMPDU buffer size + * + * Returns: + * 0: no canceled + * 1: canceled by no permission + * 2: canceled by different buffer size + * 3: canceled by potential mismatched status + * + * Blocking function, may sleep + */ +u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size) +{ + u8 ret = 0; + struct recv_reorder_ctrl *reorder_ctl = &sta->recvreorder_ctrl[tid]; + + if (reorder_ctl->enable == _FALSE) { + if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID) { + send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 1); + ret = 3; + } + goto exit; + } + + if (accept == _FALSE) { + send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0); + ret = 1; + } else if (reorder_ctl->ampdu_size != size) { + send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0); + ret = 2; + } + +exit: + return ret; +} + +u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta) +{ + u8 sz_limit = 0xFF; + + struct registry_priv *regsty = adapter_to_regsty(adapter); + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; + s8 nss = -1; + u8 bw = rtw_min(sta->bw_mode, adapter->mlmeextpriv.cur_bwmode); + + if (is_supported_vht(sta->wireless_mode)) { + nss = rtw_min(rtw_vht_mcsmap_to_nss(mlme->vhtpriv.vht_mcs_map) + , rtw_vht_mcsmap_to_nss(sta->vhtpriv.vht_mcs_map)); + } else + if (is_supported_ht(sta->wireless_mode)) { + nss = rtw_min(rtw_ht_mcsset_to_nss(mlmeinfo->HT_caps.u.HT_cap_element.MCS_rate) + , rtw_ht_mcsset_to_nss(sta->htpriv.ht_cap.supp_mcs_set)); + } + + if (nss >= 1) + sz_limit = regsty->rx_ampdu_sz_limit_by_nss_bw[nss - 1][bw]; + + return sz_limit; +} + +/** + * rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta + * @adapter: the adapter to which @sta belongs + * @sta: the sta to be checked + * @accept: the target permission if RX AMPDU should be set up + * @size: the target RX AMPDU buffer size + * + * Returns: number of the RX AMPDU assciation canceled for applying current target setting + * + * Blocking function, may sleep + */ +u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size) +{ + u8 change_cnt = 0; + int i; + + for (i = 0; i < TID_NUM; i++) { + if (rx_ampdu_apply_sta_tid(adapter, sta, i, accept, size) != 0) + change_cnt++; + } + + return change_cnt; +} + +/** + * rtw_rx_ampdu_apply - Apply the current target RX AMPDU setting for the specific @adapter + * @adapter: the adapter to be applied + * + * Returns: number of the RX AMPDU assciation canceled for applying current target setting + */ +u16 rtw_rx_ampdu_apply(_adapter *adapter) +{ + u16 adj_cnt = 0; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct sta_info *sta; + u8 accept = rtw_rx_ampdu_is_accept(adapter); + u8 size; + + if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) + size = adapter->fix_rx_ampdu_size; + else + size = rtw_rx_ampdu_size(adapter); + + if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) { + sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); + if (sta) { + u8 sta_size = size; + + if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) + sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta)); + adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); + } + + } else if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE) { + _irqL irqL; + _list *phead, *plist; + u8 peer_num = 0; + char peers[NUM_STA]; + struct sta_priv *pstapriv = &adapter->stapriv; + int i; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + + sta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + stainfo_offset = rtw_stainfo_offset(pstapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + peers[peer_num++] = stainfo_offset; + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + for (i = 0; i < peer_num; i++) { + sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]); + if (sta) { + u8 sta_size = size; + + if (adapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) + sta_size = rtw_min(size, rx_ampdu_size_sta_limit(adapter, sta)); + adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, sta_size); + } + } + } + + return adj_cnt; +} + +unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *addr; + struct sta_info *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl; + unsigned char *frame_body; + unsigned char category, action; + unsigned short tid, status, reason_code = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_priv *pstapriv = &padapter->stapriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + + + RTW_INFO("%s\n", __FUNCTION__); + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + return _SUCCESS; + + if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) + return _SUCCESS; + + addr = get_addr2_ptr(pframe); + psta = rtw_get_stainfo(pstapriv, addr); + + if (psta == NULL) + return _SUCCESS; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + category = frame_body[0]; + if (category == RTW_WLAN_CATEGORY_BACK) { /* representing Block Ack */ + if (!pmlmeinfo->HT_enable) + return _SUCCESS; + + action = frame_body[1]; + RTW_INFO("%s, action=%d\n", __FUNCTION__, action); + switch (action) { + case RTW_WLAN_ACTION_ADDBA_REQ: /* ADDBA request */ + + _rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request)); + /* process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); */ + process_addba_req(padapter, (u8 *)&(pmlmeinfo->ADDBA_req), addr); + + break; + + case RTW_WLAN_ACTION_ADDBA_RESP: /* ADDBA response */ + + /* status = frame_body[3] | (frame_body[4] << 8); */ /* endian issue */ + status = RTW_GET_LE16(&frame_body[3]); + tid = ((frame_body[5] >> 2) & 0x7); + if (status == 0) { + /* successful */ + RTW_INFO("agg_enable for TID=%d\n", tid); + psta->htpriv.agg_enable_bitmap |= 1 << tid; + psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); + /* amsdu in ampdu */ + if (pregpriv->tx_ampdu_amsdu == 0) + psta->htpriv.tx_amsdu_enable = _FALSE; + else if (pregpriv->tx_ampdu_amsdu == 1) + psta->htpriv.tx_amsdu_enable = _TRUE; + else { + if (frame_body[5] & 1) + psta->htpriv.tx_amsdu_enable = _TRUE; + } + } else + psta->htpriv.agg_enable_bitmap &= ~BIT(tid); + + if (psta->state & WIFI_STA_ALIVE_CHK_STATE) { + RTW_INFO("%s alive check - rx ADDBA response\n", __func__); + psta->htpriv.agg_enable_bitmap &= ~BIT(tid); + psta->expire_to = pstapriv->expire_to; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + } + + /* RTW_INFO("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); */ + break; + + case RTW_WLAN_ACTION_DELBA: /* DELBA */ + if ((frame_body[3] & BIT(3)) == 0) { + psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); + psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); + + /* reason_code = frame_body[4] | (frame_body[5] << 8); */ + reason_code = RTW_GET_LE16(&frame_body[4]); + } else if ((frame_body[3] & BIT(3)) == BIT(3)) { + tid = (frame_body[3] >> 4) & 0x0F; + + preorder_ctrl = &psta->recvreorder_ctrl[tid]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + } + + RTW_INFO("%s(): DELBA: %x(%x)\n", __FUNCTION__, pmlmeinfo->agg_enable_bitmap, reason_code); + /* todo: how to notify the host while receiving DELETE BA */ + break; + + default: + break; + } + } + return _SUCCESS; +} + + +static int get_reg_classes_full_count(struct p2p_channels channel_list) +{ + int cnt = 0; + int i; + + for (i = 0; i < channel_list.reg_classes; i++) + cnt += channel_list.reg_class[i].channels; + + return cnt; +} + +void issue_p2p_GO_request(_adapter *padapter, u8 *raddr) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_NEGO_REQ; + u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; + u8 wpsielen = 0, p2pielen = 0, i; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u16 len_channellist_attr = 0; + u32 wfdielen = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + RTW_INFO("[%s] In\n", __FUNCTION__); + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pwdinfo->negotiation_dialog_token = 1; /* Initialize the dialog value */ + pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen)); + + /* WPS Section */ + wpsielen = 0; + /* WPS OUI */ + *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); + wpsielen += 4; + + /* WPS version */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + + /* Device Password ID */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); + wpsielen += 2; + + /* Value: */ + + if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC); + else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN) + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC); + else if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC); + + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + + /* P2P IE Section. */ + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20110306 */ + /* According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes */ + /* 1. P2P Capability */ + /* 2. Group Owner Intent */ + /* 3. Configuration Timeout */ + /* 4. Listen Channel */ + /* 5. Extended Listen Timing */ + /* 6. Intended P2P Interface Address */ + /* 7. Channel List */ + /* 8. P2P Device Info */ + /* 9. Operating Channel */ + + /* P2P Capability */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + + /* Group Capability Bitmap, 1 byte */ + if (pwdinfo->persistent_supported) + p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; + else + p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN; + + /* Group Owner Intent */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GO_INTENT; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); + p2pielen += 2; + + /* Value: */ + /* Todo the tie breaker bit. */ + p2pie[p2pielen++] = ((pwdinfo->intent << 1) & 0xFE); + + /* Configuration Timeout */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ + + /* Listen Channel */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Operating Class */ + p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->listen_channel; /* listening channel number */ + + /* Extended Listen Timing ATTR */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004); + p2pielen += 2; + + /* Value: */ + /* Availability Period */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); + p2pielen += 2; + + /* Availability Interval */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); + p2pielen += 2; + + /* Intended P2P Interface Address */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Channel List */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + + /* Length: */ + /* Country String(3) */ + /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ + /* + number of channels in all classes */ + len_channellist_attr = 3 + + (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes) + + get_reg_classes_full_count(pmlmeext->channel_list); + + + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); + + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Channel Entry List */ + + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + /* Operating Class */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + /* Number of Channels */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + /* Channel List */ + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + + /* Device Info */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + + /* Length: */ + /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ + /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address */ + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Config Method */ + /* This field should be big endian. Noted by P2P specification. */ + + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm); + + p2pielen += 2; + + /* Primary Device Type */ + /* Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + /* OUI */ + *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); + p2pielen += 4; + + /* Sub Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + + /* Number of Secondary Device Types */ + p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ + + /* Device Name */ + /* Type: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len); + p2pielen += pwdinfo->device_name_len; + + /* Operating Channel */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Operating Class */ + if (pwdinfo->operating_channel <= 14) { + /* Operating Class */ + p2pie[p2pielen++] = 0x51; + } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { + /* Operating Class */ + p2pie[p2pielen++] = 0x73; + } else { + /* Operating Class */ + p2pie[p2pielen++] = 0x7c; + } + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + + wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_GO_response(_adapter *padapter, u8 *raddr, u8 *frame_body, uint len, u8 result) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_NEGO_RESP; + u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; + u8 p2pielen = 0, i; + uint wpsielen = 0; + u16 wps_devicepassword_id = 0x0000; + uint wps_devicepassword_id_len = 0; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh; + u16 len_channellist_attr = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + u32 wfdielen = 0; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + RTW_INFO("[%s] In, result = %d\n", __FUNCTION__, result); + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pwdinfo->negotiation_dialog_token = frame_body[7]; /* The Dialog Token of provisioning discovery request frame. */ + pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); + + /* Commented by Albert 20110328 */ + /* Try to get the device password ID from the WPS IE of group negotiation request frame */ + /* WiFi Direct test plan 5.1.15 */ + rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); + rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len); + wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id); + + _rtw_memset(wpsie, 0x00, 255); + wpsielen = 0; + + /* WPS Section */ + wpsielen = 0; + /* WPS OUI */ + *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); + wpsielen += 4; + + /* WPS version */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + + /* Device Password ID */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); + wpsielen += 2; + + /* Value: */ + if (wps_devicepassword_id == WPS_DPID_USER_SPEC) + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC); + else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_USER_SPEC); + else + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_PBC); + wpsielen += 2; + + /* Commented by Kurt 20120113 */ + /* If some device wants to do p2p handshake without sending prov_disc_req */ + /* We have to get peer_req_cm from here. */ + if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) { + if (wps_devicepassword_id == WPS_DPID_USER_SPEC) + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3); + else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3); + else + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3); + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + + /* P2P IE Section. */ + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20100908 */ + /* According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes */ + /* 1. Status */ + /* 2. P2P Capability */ + /* 3. Group Owner Intent */ + /* 4. Configuration Timeout */ + /* 5. Operating Channel */ + /* 6. Intended P2P Interface Address */ + /* 7. Channel List */ + /* 8. Device Info */ + /* 9. Group ID ( Only GO ) */ + + /* ToDo: */ + + /* P2P Status */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_STATUS; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); + p2pielen += 2; + + /* Value: */ + p2pie[p2pielen++] = result; + + /* P2P Capability */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { + /* Commented by Albert 2011/03/08 */ + /* According to the P2P specification */ + /* if the sending device will be client, the P2P Capability should be reserved of group negotation response frame */ + p2pie[p2pielen++] = 0; + } else { + /* Be group owner or meet the error case */ + p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + } + + /* Group Capability Bitmap, 1 byte */ + if (pwdinfo->persistent_supported) + p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; + else + p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN; + + /* Group Owner Intent */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GO_INTENT; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); + p2pielen += 2; + + /* Value: */ + if (pwdinfo->peer_intent & 0x01) { + /* Peer's tie breaker bit is 1, our tie breaker bit should be 0 */ + p2pie[p2pielen++] = (pwdinfo->intent << 1); + } else { + /* Peer's tie breaker bit is 0, our tie breaker bit should be 1 */ + p2pie[p2pielen++] = ((pwdinfo->intent << 1) | BIT(0)); + } + + /* Configuration Timeout */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ + + /* Operating Channel */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Operating Class */ + if (pwdinfo->operating_channel <= 14) { + /* Operating Class */ + p2pie[p2pielen++] = 0x51; + } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { + /* Operating Class */ + p2pie[p2pielen++] = 0x73; + } else { + /* Operating Class */ + p2pie[p2pielen++] = 0x7c; + } + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ + + /* Intended P2P Interface Address */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_INTENDED_IF_ADDR; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Channel List */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + + /* Country String(3) */ + /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ + /* + number of channels in all classes */ + len_channellist_attr = 3 + + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes + + get_reg_classes_full_count(pmlmeext->channel_list); + + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); + + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Channel Entry List */ + + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + /* Operating Class */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + /* Number of Channels */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + /* Channel List */ + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + + /* Device Info */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + + /* Length: */ + /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ + /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address */ + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Config Method */ + /* This field should be big endian. Noted by P2P specification. */ + + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->supported_wps_cm); + + p2pielen += 2; + + /* Primary Device Type */ + /* Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + /* OUI */ + *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); + p2pielen += 4; + + /* Sub Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + + /* Number of Secondary Device Types */ + p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ + + /* Device Name */ + /* Type: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len); + p2pielen += pwdinfo->device_name_len; + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* Group ID Attribute */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen); + p2pielen += 2; + + /* Value: */ + /* p2P Device Address */ + _rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN); + p2pielen += ETH_ALEN; + + /* SSID */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); + p2pielen += pwdinfo->nego_ssidlen; + + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + + wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_GO_confirm(_adapter *padapter, u8 *raddr, u8 result) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_NEGO_CONF; + u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; + u8 wpsielen = 0, p2pielen = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u32 wfdielen = 0; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + RTW_INFO("[%s] In\n", __FUNCTION__); + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); + + /* P2P IE Section. */ + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20110306 */ + /* According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes */ + /* 1. Status */ + /* 2. P2P Capability */ + /* 3. Operating Channel */ + /* 4. Channel List */ + /* 5. Group ID ( if this WiFi is GO ) */ + + /* P2P Status */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_STATUS; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); + p2pielen += 2; + + /* Value: */ + p2pie[p2pielen++] = result; + + /* P2P Capability */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + + /* Group Capability Bitmap, 1 byte */ + if (pwdinfo->persistent_supported) + p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; + else + p2pie[p2pielen++] = P2P_GRPCAP_CROSS_CONN; + + /* Operating Channel */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { + if (pwdinfo->peer_operating_ch <= 14) { + /* Operating Class */ + p2pie[p2pielen++] = 0x51; + } else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) { + /* Operating Class */ + p2pie[p2pielen++] = 0x73; + } else { + /* Operating Class */ + p2pie[p2pielen++] = 0x7c; + } + + p2pie[p2pielen++] = pwdinfo->peer_operating_ch; + } else { + if (pwdinfo->operating_channel <= 14) { + /* Operating Class */ + p2pie[p2pielen++] = 0x51; + } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { + /* Operating Class */ + p2pie[p2pielen++] = 0x73; + } else { + /* Operating Class */ + p2pie[p2pielen++] = 0x7c; + } + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->operating_channel; /* Use the listen channel as the operating channel */ + } + + /* Channel List */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + + *(u16 *)(p2pie + p2pielen) = 6; + p2pielen += 2; + + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Value: */ + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { + if (pwdinfo->peer_operating_ch <= 14) { + /* Operating Class */ + p2pie[p2pielen++] = 0x51; + } else if ((pwdinfo->peer_operating_ch >= 36) && (pwdinfo->peer_operating_ch <= 48)) { + /* Operating Class */ + p2pie[p2pielen++] = 0x73; + } else { + /* Operating Class */ + p2pie[p2pielen++] = 0x7c; + } + p2pie[p2pielen++] = 1; + p2pie[p2pielen++] = pwdinfo->peer_operating_ch; + } else { + if (pwdinfo->operating_channel <= 14) { + /* Operating Class */ + p2pie[p2pielen++] = 0x51; + } else if ((pwdinfo->operating_channel >= 36) && (pwdinfo->operating_channel <= 48)) { + /* Operating Class */ + p2pie[p2pielen++] = 0x73; + } else { + /* Operating Class */ + p2pie[p2pielen++] = 0x7c; + } + + /* Channel Number */ + p2pie[p2pielen++] = 1; + p2pie[p2pielen++] = pwdinfo->operating_channel; /* Use the listen channel as the operating channel */ + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* Group ID Attribute */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN + pwdinfo->nego_ssidlen); + p2pielen += 2; + + /* Value: */ + /* p2P Device Address */ + _rtw_memcpy(p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN); + p2pielen += ETH_ALEN; + + /* SSID */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); + p2pielen += pwdinfo->nego_ssidlen; + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + + wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_INVIT_REQ; + u8 p2pie[255] = { 0x00 }; + u8 p2pielen = 0, i; + u8 dialogToken = 3; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u16 len_channellist_attr = 0; + u32 wfdielen = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + /* P2P IE Section. */ + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20101011 */ + /* According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes */ + /* 1. Configuration Timeout */ + /* 2. Invitation Flags */ + /* 3. Operating Channel ( Only GO ) */ + /* 4. P2P Group BSSID ( Should be included if I am the GO ) */ + /* 5. Channel List */ + /* 6. P2P Group ID */ + /* 7. P2P Device Info */ + + /* Configuration Timeout */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ + + /* Invitation Flags */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_INVITATION_FLAGS; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); + p2pielen += 2; + + /* Value: */ + p2pie[p2pielen++] = P2P_INVITATION_FLAGS_PERSISTENT; + + /* Operating Channel */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Operating Class */ + if (pwdinfo->invitereq_info.operating_ch <= 14) + p2pie[p2pielen++] = 0x51; + else if ((pwdinfo->invitereq_info.operating_ch >= 36) && (pwdinfo->invitereq_info.operating_ch <= 48)) + p2pie[p2pielen++] = 0x73; + else + p2pie[p2pielen++] = 0x7c; + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->invitereq_info.operating_ch; /* operating channel number */ + + if (_rtw_memcmp(adapter_mac_addr(padapter), pwdinfo->invitereq_info.go_bssid, ETH_ALEN)) { + /* P2P Group BSSID */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address for GO */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN); + p2pielen += ETH_ALEN; + } + + /* Channel List */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + + /* Length: */ + /* Country String(3) */ + /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ + /* + number of channels in all classes */ + len_channellist_attr = 3 + + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes + + get_reg_classes_full_count(pmlmeext->channel_list); + + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Channel Entry List */ + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + /* Operating Class */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + /* Number of Channels */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + /* Channel List */ + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + + /* P2P Group ID */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(6 + pwdinfo->invitereq_info.ssidlen); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address for GO */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN); + p2pielen += ETH_ALEN; + + /* SSID */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen); + p2pielen += pwdinfo->invitereq_info.ssidlen; + + /* Device Info */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + + /* Length: */ + /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ + /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address */ + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Config Method */ + /* This field should be big endian. Noted by P2P specification. */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY); + p2pielen += 2; + + /* Primary Device Type */ + /* Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + /* OUI */ + *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); + p2pielen += 4; + + /* Sub Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + + /* Number of Secondary Device Types */ + p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ + + /* Device Name */ + /* Type: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); + p2pielen += pwdinfo->device_name_len; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + + wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 status_code) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_INVIT_RESP; + u8 p2pie[255] = { 0x00 }; + u8 p2pielen = 0, i; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u16 len_channellist_attr = 0; + u32 wfdielen = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + /* P2P IE Section. */ + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20101005 */ + /* According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes */ + /* 1. Status */ + /* 2. Configuration Timeout */ + /* 3. Operating Channel ( Only GO ) */ + /* 4. P2P Group BSSID ( Only GO ) */ + /* 5. Channel List */ + + /* P2P Status */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_STATUS; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0001); + p2pielen += 2; + + /* Value: */ + /* When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. */ + /* Sent the event receiving the P2P Invitation Req frame to DMP UI. */ + /* DMP had to compare the MAC address to find out the profile. */ + /* So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. */ + /* If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req */ + /* to NB to rebuild the persistent group. */ + p2pie[p2pielen++] = status_code; + + /* Configuration Timeout */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CONF_TIMEOUT; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P GO */ + p2pie[p2pielen++] = 200; /* 2 seconds needed to be the P2P Client */ + + if (status_code == P2P_STATUS_SUCCESS) { + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO */ + /* In this case, the P2P Invitation response frame should carry the two more P2P attributes. */ + /* First one is operating channel attribute. */ + /* Second one is P2P Group BSSID attribute. */ + + /* Operating Channel */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Operating Class */ + p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ + + /* P2P Group BSSID */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GROUP_BSSID; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(ETH_ALEN); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address for GO */ + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + } + + /* Channel List */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CH_LIST; + + /* Length: */ + /* Country String(3) */ + /* + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) */ + /* + number of channels in all classes */ + len_channellist_attr = 3 + + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes + + get_reg_classes_full_count(pmlmeext->channel_list); + + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(len_channellist_attr); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Channel Entry List */ + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + /* Operating Class */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + /* Number of Channels */ + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + /* Channel List */ + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + + wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr) +{ + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u8 dialogToken = 1; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PROVISION_DISC_REQ; + u8 wpsie[100] = { 0x00 }; + u8 wpsielen = 0; + u32 p2pielen = 0; + u32 wfdielen = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + RTW_INFO("[%s] In\n", __FUNCTION__); + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + p2pielen = build_prov_disc_request_p2p_ie(pwdinfo, pframe, pssid, ussidlen, pdev_raddr); + + pframe += p2pielen; + pattrib->pktlen += p2pielen; + + wpsielen = 0; + /* WPS OUI */ + *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); + wpsielen += 4; + + /* WPS version */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + + /* Config Method */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); + wpsielen += 2; + + /* Value: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->tx_prov_disc_info.wps_config_method_request); + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + + wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +u8 is_matched_in_profilelist(u8 *peermacaddr, struct profile_info *profileinfo) +{ + u8 i, match_result = 0; + + RTW_INFO("[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, + peermacaddr[0], peermacaddr[1], peermacaddr[2], peermacaddr[3], peermacaddr[4], peermacaddr[5]); + + for (i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++) { + RTW_INFO("[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, + profileinfo->peermac[0], profileinfo->peermac[1], profileinfo->peermac[2], profileinfo->peermac[3], profileinfo->peermac[4], profileinfo->peermac[5]); + if (_rtw_memcmp(peermacaddr, profileinfo->peermac, ETH_ALEN)) { + match_result = 1; + RTW_INFO("[%s] Match!\n", __FUNCTION__); + break; + } + } + + return match_result ; +} + +void issue_probersp_p2p(_adapter *padapter, unsigned char *da) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + /* WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); */ + u16 beacon_interval = 100; + u16 capInfo = 0; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 wpsie[255] = { 0x00 }; + u32 wpsielen = 0, p2pielen = 0; + u32 wfdielen = 0; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + if (IS_CCK_RATE(pattrib->rate)) { + /* force OFDM 6M rate */ + pattrib->rate = MGN_6M; + pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); + } + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + + /* Use the device address for BSSID field. */ + _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(fctrl, WIFI_PROBERSP); + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = pattrib->hdrlen; + pframe += pattrib->hdrlen; + + /* timestamp will be inserted by hardware */ + pframe += 8; + pattrib->pktlen += 8; + + /* beacon interval: 2 bytes */ + _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2); + pframe += 2; + pattrib->pktlen += 2; + + /* capability info: 2 bytes */ + /* ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) */ + capInfo |= cap_ShortPremble; + capInfo |= cap_ShortSlot; + + _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2); + pframe += 2; + pattrib->pktlen += 2; + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen); + + /* supported rates... */ + /* Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */ + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen); + + { + + /* Todo: WPS IE */ + /* Noted by Albert 20100907 */ + /* According to the WPS specification, all the WPS attribute is presented by Big Endian. */ + + wpsielen = 0; + /* WPS OUI */ + *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); + wpsielen += 4; + + /* WPS version */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + + /* WiFi Simple Config State */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SIMPLE_CONF_STATE); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG; /* Not Configured. */ + + /* Response Type */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_RESP_TYPE); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X; + + /* UUID-E */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010); + wpsielen += 2; + + /* Value: */ + if (pwdinfo->external_uuid == 0) { + _rtw_memset(wpsie + wpsielen, 0x0, 16); + _rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN); + } else + _rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10); + wpsielen += 0x10; + + /* Manufacturer */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MANUFACTURER); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0007); + wpsielen += 2; + + /* Value: */ + _rtw_memcpy(wpsie + wpsielen, "Realtek", 7); + wpsielen += 7; + + /* Model Name */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NAME); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0006); + wpsielen += 2; + + /* Value: */ + _rtw_memcpy(wpsie + wpsielen, "8192CU", 6); + wpsielen += 6; + + /* Model Number */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_MODEL_NUMBER); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = 0x31; /* character 1 */ + + /* Serial Number */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_SERIAL_NUMBER); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(ETH_ALEN); + wpsielen += 2; + + /* Value: */ + _rtw_memcpy(wpsie + wpsielen, "123456" , ETH_ALEN); + wpsielen += ETH_ALEN; + + /* Primary Device Type */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008); + wpsielen += 2; + + /* Value: */ + /* Category ID */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); + wpsielen += 2; + + /* OUI */ + *(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI); + wpsielen += 4; + + /* Sub Category ID */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); + wpsielen += 2; + + /* Device Name */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len); + wpsielen += 2; + + /* Value: */ + _rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len); + wpsielen += pwdinfo->device_name_len; + + /* Config Method */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); + wpsielen += 2; + + /* Value: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm); + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + + p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe); + pframe += p2pielen; + pattrib->pktlen += p2pielen; + } + + wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac; + unsigned char bssrate[NumRates]; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int bssrate_len = 0; + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 wpsie[255] = { 0x00 }, p2pie[255] = { 0x00 }; + u16 wpsielen = 0, p2pielen = 0; + u32 wfdielen = 0; + + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + if (IS_CCK_RATE(pattrib->rate)) { + /* force OFDM 6M rate */ + pattrib->rate = MGN_6M; + pattrib->raid = rtw_get_mgntframe_raid(padapter, WIRELESS_11G); + } + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if (da) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + } else { + if ((pwdinfo->p2p_info.scan_op_ch_only) || (pwdinfo->rx_invitereq_info.scan_op_ch_only)) { + /* This two flags will be set when this is only the P2P client mode. */ + _rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); + } else { + /* broadcast probe request frame */ + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); + } + } + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_PROBEREQ); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) + pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen)); + else + pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen)); + /* Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) */ + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); + + { + + /* WPS IE */ + /* Noted by Albert 20110221 */ + /* According to the WPS specification, all the WPS attribute is presented by Big Endian. */ + + wpsielen = 0; + /* WPS OUI */ + *(u32 *)(wpsie) = cpu_to_be32(WPSOUI); + wpsielen += 4; + + /* WPS version */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_VER1); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0001); + wpsielen += 2; + + /* Value: */ + wpsie[wpsielen++] = WPS_VERSION_1; /* Version 1.0 */ + + if (pmlmepriv->wps_probe_req_ie == NULL) { + /* UUID-E */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_UUID_E); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0010); + wpsielen += 2; + + /* Value: */ + if (pwdinfo->external_uuid == 0) { + _rtw_memset(wpsie + wpsielen, 0x0, 16); + _rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN); + } else + _rtw_memcpy(wpsie + wpsielen, pwdinfo->uuid, 0x10); + wpsielen += 0x10; + + /* Config Method */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_CONF_METHOD); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); + wpsielen += 2; + + /* Value: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->supported_wps_cm); + wpsielen += 2; + } + + /* Device Name */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(pwdinfo->device_name_len); + wpsielen += 2; + + /* Value: */ + _rtw_memcpy(wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len); + wpsielen += pwdinfo->device_name_len; + + /* Primary Device Type */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0008); + wpsielen += 2; + + /* Value: */ + /* Category ID */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_CID_RTK_WIDI); + wpsielen += 2; + + /* OUI */ + *(u32 *)(wpsie + wpsielen) = cpu_to_be32(WPSOUI); + wpsielen += 4; + + /* Sub Category ID */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_PDT_SCID_RTK_DMP); + wpsielen += 2; + + /* Device Password ID */ + /* Type: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_ATTR_DEVICE_PWID); + wpsielen += 2; + + /* Length: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(0x0002); + wpsielen += 2; + + /* Value: */ + *(u16 *)(wpsie + wpsielen) = cpu_to_be16(WPS_DPID_REGISTRAR_SPEC); /* Registrar-specified */ + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20110221 */ + /* According to the P2P Specification, the probe request frame should contain 5 P2P attributes */ + /* 1. P2P Capability */ + /* 2. P2P Device ID if this probe request wants to find the specific P2P device */ + /* 3. Listen Channel */ + /* 4. Extended Listen Timing */ + /* 5. Operating Channel if this WiFi is working as the group owner now */ + + /* P2P Capability */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + + /* Group Capability Bitmap, 1 byte */ + if (pwdinfo->persistent_supported) + p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; + + /* Listen Channel */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_LISTEN_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Operating Class */ + p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->listen_channel; /* listen channel */ + + /* Extended Listen Timing */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004); + p2pielen += 2; + + /* Value: */ + /* Availability Period */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); + p2pielen += 2; + + /* Availability Interval */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); + p2pielen += 2; + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* Operating Channel (if this WiFi is working as the group owner now) */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_OPERATING_CH; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0005); + p2pielen += 2; + + /* Value: */ + /* Country String */ + p2pie[p2pielen++] = 'X'; + p2pie[p2pielen++] = 'X'; + + /* The third byte should be set to 0x04. */ + /* Described in the "Operating Channel Attribute" section. */ + p2pie[p2pielen++] = 0x04; + + /* Operating Class */ + p2pie[p2pielen++] = 0x51; /* Copy from SD7 */ + + /* Channel Number */ + p2pie[p2pielen++] = pwdinfo->operating_channel; /* operating channel number */ + + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + + } + + wfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +inline void issue_probereq_p2p(_adapter *adapter, u8 *da) +{ + _issue_probereq_p2p(adapter, da, _FALSE); +} + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms) +{ + int ret; + int i = 0; + u32 start = rtw_get_current_time(); + + do { + ret = _issue_probereq_p2p(adapter, da, wait_ms > 0 ? _TRUE : _FALSE); + + i++; + + if (RTW_CANNOT_RUN(adapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + + +s32 rtw_action_public_decache(union recv_frame *rframe, u8 token_offset) +{ + _adapter *adapter = rframe->u.hdr.adapter; + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + u8 *frame = rframe->u.hdr.rx_data; + u16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num & 0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf); + u8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset); + + if (GetRetry(frame)) { + if ((seq_ctrl == mlmeext->action_public_rxseq) + && (token == mlmeext->action_public_dialog_token) + ) { + RTW_INFO(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n", + FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token); + return _FAIL; + } + } + + /* TODO: per sta seq & token */ + mlmeext->action_public_rxseq = seq_ctrl; + mlmeext->action_public_dialog_token = token; + + return _SUCCESS; +} + +unsigned int on_action_public_p2p(union recv_frame *precv_frame) +{ + _adapter *padapter = precv_frame->u.hdr.adapter; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + u8 *frame_body; + u8 *p2p_ie; + u32 p2p_ielen, wps_ielen; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 result = P2P_STATUS_SUCCESS; + u8 empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + u8 *merged_p2pie = NULL; + u32 merged_p2p_ielen = 0; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); + { + /* Do nothing if the driver doesn't enable the P2P function. */ + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + return _SUCCESS; + + len -= sizeof(struct rtw_ieee80211_hdr_3addr); + + switch (frame_body[6]) { /* OUI Subtype */ + case P2P_GO_NEGO_REQ: { + RTW_INFO("[%s] Got GO Nego Req Frame\n", __FUNCTION__); + _rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info)); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) { + /* Commented by Albert 20110526 */ + /* In this case, this means the previous nego fail doesn't be reset yet. */ + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + /* Restore the previous p2p state */ + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + RTW_INFO("[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo)); + } + + /* Commented by Kurt 20110902 */ + /* Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + + /* Commented by Kurt 20120113 */ + /* Get peer_dev_addr here if peer doesn't issue prov_disc frame. */ + if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN)) + _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN); + + result = process_p2p_group_negotation_req(pwdinfo, frame_body, len); + issue_p2p_GO_response(padapter, get_addr2_ptr(pframe), frame_body, len, result); + + /* Commented by Albert 20110718 */ + /* No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. */ + _set_timer(&pwdinfo->restore_p2p_state_timer, 5000); + break; + } + case P2P_GO_NEGO_RESP: { + RTW_INFO("[%s] Got GO Nego Resp Frame\n", __FUNCTION__); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) { + /* Commented by Albert 20110425 */ + /* The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. */ + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + pwdinfo->nego_req_info.benable = _FALSE; + result = process_p2p_group_negotation_resp(pwdinfo, frame_body, len); + issue_p2p_GO_confirm(pwdinfo->padapter, get_addr2_ptr(pframe), result); + if (P2P_STATUS_SUCCESS == result) { + if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) { + pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch; + pwdinfo->p2p_info.operation_ch[1] = 1; /* Check whether GO is operating in channel 1; */ + pwdinfo->p2p_info.operation_ch[2] = 6; /* Check whether GO is operating in channel 6; */ + pwdinfo->p2p_info.operation_ch[3] = 11; /* Check whether GO is operating in channel 11; */ + pwdinfo->p2p_info.scan_op_ch_only = 1; + _set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH); + } + } + + /* Reset the dialog token for group negotiation frames. */ + pwdinfo->negotiation_dialog_token = 1; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) + _set_timer(&pwdinfo->restore_p2p_state_timer, 5000); + } else + RTW_INFO("[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__); + + break; + } + case P2P_GO_NEGO_CONF: { + RTW_INFO("[%s] Got GO Nego Confirm Frame\n", __FUNCTION__); + result = process_p2p_group_negotation_confirm(pwdinfo, frame_body, len); + if (P2P_STATUS_SUCCESS == result) { + if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) { + pwdinfo->p2p_info.operation_ch[0] = pwdinfo->peer_operating_ch; + pwdinfo->p2p_info.operation_ch[1] = 1; /* Check whether GO is operating in channel 1; */ + pwdinfo->p2p_info.operation_ch[2] = 6; /* Check whether GO is operating in channel 6; */ + pwdinfo->p2p_info.operation_ch[3] = 11; /* Check whether GO is operating in channel 11; */ + pwdinfo->p2p_info.scan_op_ch_only = 1; + _set_timer(&pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH); + } + } + break; + } + case P2P_INVIT_REQ: { + /* Added by Albert 2010/10/05 */ + /* Received the P2P Invite Request frame. */ + + RTW_INFO("[%s] Got invite request frame!\n", __FUNCTION__); + p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen); + if (p2p_ie) { + /* Parse the necessary information from the P2P Invitation Request frame. */ + /* For example: The MAC address of sending this P2P Invitation Request frame. */ + u32 attr_contentlen = 0; + u8 status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + struct group_id_info group_id; + u8 invitation_flag = 0; + int j = 0; + + merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_); + + merged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2); /* 2 is for EID and Length */ + if (merged_p2pie == NULL) { + RTW_INFO("[%s] Malloc p2p ie fail\n", __FUNCTION__); + goto exit; + } + _rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen); + + merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie); + + rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen); + if (attr_contentlen) { + + rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen); + /* Commented by Albert 20120510 */ + /* Copy to the pwdinfo->p2p_peer_interface_addr. */ + /* So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. */ + /* #> iwpriv wlan0 p2p_get peer_ifa */ + /* After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. */ + + if (attr_contentlen) { + RTW_INFO("[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], + pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3], + pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + } + + if (invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT) { + /* Re-invoke the persistent group. */ + + _rtw_memset(&group_id, 0x00, sizeof(struct group_id_info)); + rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen); + if (attr_contentlen) { + if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) { + /* The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. */ + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + status_code = P2P_STATUS_SUCCESS; + } else { + /* The p2p device sending this p2p invitation request wants to be the persistent GO. */ + if (is_matched_in_profilelist(pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[0])) { + u8 operatingch_info[5] = { 0x00 }; + if (rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, + &attr_contentlen)) { + if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, (u32)operatingch_info[4]) >= 0) { + /* The operating channel is acceptable for this device. */ + pwdinfo->rx_invitereq_info.operation_ch[0] = operatingch_info[4]; + pwdinfo->rx_invitereq_info.operation_ch[1] = 1; /* Check whether GO is operating in channel 1; */ + pwdinfo->rx_invitereq_info.operation_ch[2] = 6; /* Check whether GO is operating in channel 6; */ + pwdinfo->rx_invitereq_info.operation_ch[3] = 11; /* Check whether GO is operating in channel 11; */ + pwdinfo->rx_invitereq_info.scan_op_ch_only = 1; + _set_timer(&pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + status_code = P2P_STATUS_SUCCESS; + } else { + /* The operating channel isn't supported by this device. */ + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + status_code = P2P_STATUS_FAIL_NO_COMMON_CH; + _set_timer(&pwdinfo->restore_p2p_state_timer, 3000); + } + } else { + /* Commented by Albert 20121130 */ + /* Intel will use the different P2P IE to store the operating channel information */ + /* Workaround for Intel WiDi 3.5 */ + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + status_code = P2P_STATUS_SUCCESS; + } + } else { + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH); + + status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; + } + } + } else { + RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + } else { + /* Received the invitation to join a P2P group. */ + + _rtw_memset(&group_id, 0x00, sizeof(struct group_id_info)); + rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, (u8 *) &group_id, &attr_contentlen); + if (attr_contentlen) { + if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) { + /* In this case, the GO can't be myself. */ + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } else { + /* The p2p device sending this p2p invitation request wants to join an existing P2P group */ + /* Commented by Albert 2012/06/28 */ + /* In this case, this Wi-Fi device should use the iwpriv command to get the peer device address. */ + /* The peer device address should be the destination address for the provisioning discovery request. */ + /* Then, this Wi-Fi device should use the iwpriv command to get the peer interface address. */ + /* The peer interface address should be the address for WPS mac address */ + _rtw_memcpy(pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN); + status_code = P2P_STATUS_SUCCESS; + } + } else { + RTW_INFO("[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + } + } else { + RTW_INFO("[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + + RTW_INFO("[%s] status_code = %d\n", __FUNCTION__, status_code); + + pwdinfo->inviteresp_info.token = frame_body[7]; + issue_p2p_invitation_response(padapter, get_addr2_ptr(pframe), pwdinfo->inviteresp_info.token, status_code); + _set_timer(&pwdinfo->restore_p2p_state_timer, 3000); + } + break; + } + case P2P_INVIT_RESP: { + u8 attr_content = 0x00; + u32 attr_contentlen = 0; + + RTW_INFO("[%s] Got invite response frame!\n", __FUNCTION__); + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen); + if (p2p_ie) { + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); + + if (attr_contentlen == 1) { + RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content); + pwdinfo->invitereq_info.benable = _FALSE; + + if (attr_content == P2P_STATUS_SUCCESS) { + if (_rtw_memcmp(pwdinfo->invitereq_info.go_bssid, adapter_mac_addr(padapter), ETH_ALEN)) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + else + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_OK); + } else { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL); + } + } else { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL); + } + } else { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL); + } + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL)) + _set_timer(&pwdinfo->restore_p2p_state_timer, 5000); + break; + } + case P2P_DEVDISC_REQ: + + process_p2p_devdisc_req(pwdinfo, pframe, len); + + break; + + case P2P_DEVDISC_RESP: + + process_p2p_devdisc_resp(pwdinfo, pframe, len); + + break; + + case P2P_PROVISION_DISC_REQ: + RTW_INFO("[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__); + process_p2p_provdisc_req(pwdinfo, pframe, len); + _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, get_addr2_ptr(pframe), ETH_ALEN); + + /* 20110902 Kurt */ + /* Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ); + _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT); + break; + + case P2P_PROVISION_DISC_RESP: + /* Commented by Albert 20110707 */ + /* Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? */ + RTW_INFO("[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__); + /* Commented by Albert 20110426 */ + /* The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. */ + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP); + process_p2p_provdisc_resp(pwdinfo, pframe); + _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT); + break; + + } + } + +exit: + + if (merged_p2pie) + rtw_mfree(merged_p2pie, merged_p2p_ielen + 2); + return _SUCCESS; +} + +unsigned int on_action_public_vendor(union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + + if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) { + if (rtw_action_public_decache(precv_frame, 7) == _FAIL) + goto exit; + + if (!hal_chk_wl_func(precv_frame->u.hdr.adapter, WL_FUNC_MIRACAST)) + rtw_rframe_del_wfd_ie(precv_frame, 8); + + ret = on_action_public_p2p(precv_frame); + } + +exit: + return ret; +} + +unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 token; + _adapter *adapter = precv_frame->u.hdr.adapter; + int cnt = 0; + char msg[64]; + + token = frame_body[2]; + + if (rtw_action_public_decache(precv_frame, 2) == _FAIL) + goto exit; + + + ret = _SUCCESS; + +exit: + return ret; +} + +unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_PUBLIC) + goto exit; + + action = frame_body[1]; + switch (action) { + case ACT_PUBLIC_BSSCOEXIST: + /*20/40 BSS Coexistence Management frame is a Public Action frame*/ + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_process_public_act_bsscoex(padapter, pframe, frame_len); + break; + case ACT_PUBLIC_VENDOR: + ret = on_action_public_vendor(precv_frame); + break; + default: + ret = on_action_public_default(precv_frame, action); + break; + } + +exit: + return ret; +} + +unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} + +unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_HT) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_WLAN_ACTION_HT_SM_PS: + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_process_ht_action_smps(padapter, get_addr2_ptr(pframe), frame_body[2]); + break; + case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING: + break; + default: + break; + } + +exit: + + return _SUCCESS; +} + +unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} + +unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + struct sta_info *psta = NULL; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_VHT) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING: + break; + case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION: + /* CategoryCode(1) + ActionCode(1) + OpModeNotification(1) */ + /* RTW_INFO("RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\n"); */ + psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2); + if (psta) + rtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta); + break; + case RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT: + break; + default: + break; + } + +exit: + + return _SUCCESS; +} + +unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *frame_body; + u8 category, OUI_Subtype, dialogToken = 0; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + return _SUCCESS; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_P2P) + return _SUCCESS; + + if (cpu_to_be32(*((u32 *)(frame_body + 1))) != P2POUI) + return _SUCCESS; + + { + len -= sizeof(struct rtw_ieee80211_hdr_3addr); + OUI_Subtype = frame_body[5]; + dialogToken = frame_body[6]; + + switch (OUI_Subtype) { + case P2P_NOTICE_OF_ABSENCE: + + break; + + case P2P_PRESENCE_REQUEST: + + process_p2p_presence_req(pwdinfo, pframe, len); + + break; + + case P2P_PRESENCE_RESPONSE: + + break; + + case P2P_GO_DISC_REQUEST: + + break; + + default: + break; + + } + } + + return _SUCCESS; + +} + +unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame) +{ + int i; + unsigned char category; + struct action_handler *ptable; + unsigned char *frame_body; + u8 *pframe = precv_frame->u.hdr.rx_data; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + category = frame_body[0]; + + for (i = 0; i < sizeof(OnAction_tbl) / sizeof(struct action_handler); i++) { + ptable = &OnAction_tbl[i]; + + if (category == ptable->num) + ptable->func(padapter, precv_frame); + + } + + return _SUCCESS; + +} + +unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame) +{ + + /* RTW_INFO("rcvd mgt frame(%x, %x)\n", (get_frame_sub_type(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); */ + return _SUCCESS; +} + +struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once) +{ + struct xmit_frame *pmgntframe; + struct xmit_buf *pxmitbuf; + + if (once) + pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv); + else + pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv); + + if (pmgntframe == NULL) { + RTW_INFO(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once); + goto exit; + } + + pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv); + if (pxmitbuf == NULL) { + RTW_INFO(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter)); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pmgntframe = NULL; + goto exit; + } + + pmgntframe->frame_tag = MGNT_FRAMETAG; + pmgntframe->pxmitbuf = pxmitbuf; + pmgntframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pmgntframe; + +exit: + return pmgntframe; + +} + +inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv) +{ + return _alloc_mgtxmitframe(pxmitpriv, _FALSE); +} + +inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv) +{ + return _alloc_mgtxmitframe(pxmitpriv, _TRUE); +} + +/**************************************************************************** + +Following are some TX fuctions for WiFi MLME + +*****************************************************************************/ + +void update_mgnt_tx_rate(_adapter *padapter, u8 rate) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + pmlmeext->tx_rate = rate; + /* RTW_INFO("%s(): rate = %x\n",__FUNCTION__, rate); */ +} + +void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 wireless_mode; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *pbcmc_sta = NULL; + + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + + pattrib->hdrlen = 24; + pattrib->nr_frags = 1; + pattrib->priority = 7; + + if (pbcmc_sta) + pattrib->mac_id = pbcmc_sta->mac_id; + else { + pattrib->mac_id = 0; + RTW_INFO("mgmt use mac_id 0 will affect RA\n"); + } + pattrib->qsel = QSLT_MGNT; + + pattrib->pktlen = 0; + + if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB) + wireless_mode = WIRELESS_11B; + else + wireless_mode = WIRELESS_11G; + + pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode); + if (pHalData->rf_type == RF_1T1R) + pattrib->raid = RATEID_IDX_VHT_1SS; + else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) + pattrib->raid = RATEID_IDX_VHT_2SS; + else if (pHalData->rf_type == RF_3T3R) + pattrib->raid = RATEID_IDX_VHT_3SS; + else + pattrib->raid = RATEID_IDX_BGN_40M_1SS; + + pattrib->rate = MGN_VHT1SS_MCS9; + + pattrib->encrypt = _NO_PRIVACY_; + pattrib->bswenc = _FALSE; + + pattrib->qos_en = _FALSE; + pattrib->ht_en = 1; + pattrib->bwmode = CHANNEL_WIDTH_20; + pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pattrib->sgi = _FALSE; + + pattrib->seqnum = pmlmeext->mgnt_seq; + + pattrib->retry_ctrl = _TRUE; + + pattrib->mbssid = 0; + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; + +} + +void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u8 wireless_mode; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *pbcmc_sta = NULL; + /* _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); */ + + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + + pattrib->hdrlen = 24; + pattrib->nr_frags = 1; + pattrib->priority = 7; + + if (pbcmc_sta) + pattrib->mac_id = pbcmc_sta->mac_id; + else { + pattrib->mac_id = 1; /* use STA's BCMC sta-info macid */ + + if (MLME_IS_AP(padapter) || MLME_IS_GO(padapter)) + RTW_INFO("%s-"ADPT_FMT" get bcmc sta_info fail,use MACID=1\n", __func__, ADPT_ARG(padapter)); + } + pattrib->qsel = QSLT_MGNT; + + pattrib->pktlen = 0; + + if (IS_CCK_RATE(pmlmeext->tx_rate)) + wireless_mode = WIRELESS_11B; + else + wireless_mode = WIRELESS_11G; + pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode); + pattrib->rate = pmlmeext->tx_rate; + + pattrib->encrypt = _NO_PRIVACY_; + pattrib->bswenc = _FALSE; + + pattrib->qos_en = _FALSE; + pattrib->ht_en = _FALSE; + pattrib->bwmode = CHANNEL_WIDTH_20; + pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pattrib->sgi = _FALSE; + + pattrib->seqnum = pmlmeext->mgnt_seq; + + pattrib->retry_ctrl = _TRUE; + + pattrib->mbssid = 0; + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; +} + +void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + u8 *pframe; + struct pkt_attrib *pattrib = &pmgntframe->attrib; + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(pframe), ETH_ALEN); + +} + +void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + if (RTW_CANNOT_RUN(padapter)) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return; + } + + rtw_hal_mgnt_xmit(padapter, pmgntframe); +} + +s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) +{ + s32 ret = _FAIL; + _irqL irqL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf; + struct submit_ctx sctx; + + if (RTW_CANNOT_RUN(padapter)) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return ret; + } + + rtw_sctx_init(&sctx, timeout_ms); + pxmitbuf->sctx = &sctx; + + ret = rtw_hal_mgnt_xmit(padapter, pmgntframe); + + if (ret == _SUCCESS) + ret = rtw_sctx_wait(&sctx, __func__); + + _enter_critical(&pxmitpriv->lock_sctx, &irqL); + pxmitbuf->sctx = NULL; + _exit_critical(&pxmitpriv->lock_sctx, &irqL); + + return ret; +} + +s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) +{ + static u8 seq_no = 0; + s32 ret = _FAIL; + struct xmit_priv *pxmitpriv = &(GET_PRIMARY_ADAPTER(padapter))->xmitpriv; + + if (RTW_CANNOT_RUN(padapter)) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return -1; + } + + _enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); + pxmitpriv->ack_tx = _TRUE; + pxmitpriv->seq_no = seq_no++; + pmgntframe->ack_report = 1; + rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms); + if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) + ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__); + + pxmitpriv->ack_tx = _FALSE; + _exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); + + return ret; +} + +s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + /* In this case, use 500 ms as the default wait_ack timeout */ + return dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 500); +} + +int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode) +{ + u8 *ssid_ie; + sint ssid_len_ori; + int len_diff = 0; + + ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len); + + /* RTW_INFO("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); */ + + if (ssid_ie && ssid_len_ori > 0) { + switch (hidden_ssid_mode) { + case 1: { + u8 *next_ie = ssid_ie + 2 + ssid_len_ori; + u32 remain_len = 0; + + remain_len = ies_len - (next_ie - ies); + + ssid_ie[1] = 0; + _rtw_memcpy(ssid_ie + 2, next_ie, remain_len); + len_diff -= ssid_len_ori; + + break; + } + case 2: + _rtw_memset(&ssid_ie[2], 0, ssid_len_ori); + break; + default: + break; + } + } + + return len_diff; +} + +void issue_beacon(_adapter *padapter, int timeout_ms) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned int rate_len; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + _irqL irqL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + pmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv); + if (pmgntframe == NULL) + { + RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__); + return; + } + _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->qsel = QSLT_BEACON; + + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + /* pmlmeext->mgnt_seq++; */ + set_frame_sub_type(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + /* RTW_INFO("ie len=%d\n", cur_network->IELength); */ + /* for P2P : Primary Device Type & Device Name */ + u32 wpsielen = 0, insert_len = 0; + u8 *wpsie = NULL; + wpsie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wpsielen); + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen > 0) { + uint wps_offset, remainder_ielen; + u8 *premainder_ie, *pframe_wscie; + + wps_offset = (uint)(wpsie - cur_network->IEs); + + premainder_ie = wpsie + wpsielen; + + remainder_ielen = cur_network->IELength - wps_offset - wpsielen; + + { + pframe_wscie = pframe + wps_offset; + _rtw_memcpy(pframe, cur_network->IEs, wps_offset + wpsielen); + pframe += (wps_offset + wpsielen); + pattrib->pktlen += (wps_offset + wpsielen); + + /* now pframe is end of wsc ie, insert Primary Device Type & Device Name */ + /* Primary Device Type */ + /* Type: */ + *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_PRIMARY_DEV_TYPE); + insert_len += 2; + + /* Length: */ + *(u16 *)(pframe + insert_len) = cpu_to_be16(0x0008); + insert_len += 2; + + /* Value: */ + /* Category ID */ + *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); + insert_len += 2; + + /* OUI */ + *(u32 *)(pframe + insert_len) = cpu_to_be32(WPSOUI); + insert_len += 4; + + /* Sub Category ID */ + *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); + insert_len += 2; + + /* Device Name */ + /* Type: */ + *(u16 *)(pframe + insert_len) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); + insert_len += 2; + + /* Length: */ + *(u16 *)(pframe + insert_len) = cpu_to_be16(pwdinfo->device_name_len); + insert_len += 2; + + /* Value: */ + _rtw_memcpy(pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len); + insert_len += pwdinfo->device_name_len; + + /* update wsc ie length */ + *(pframe_wscie + 1) = (wpsielen - 2) + insert_len; + + /* pframe move to end */ + pframe += insert_len; + pattrib->pktlen += insert_len; + + /* copy remainder_ie to pframe */ + _rtw_memcpy(pframe, premainder_ie, remainder_ielen); + pframe += remainder_ielen; + pattrib->pktlen += remainder_ielen; + } + } else + { + int len_diff; + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + len_diff = update_hidden_ssid( + pframe + _BEACON_IE_OFFSET_ + , cur_network->IELength - _BEACON_IE_OFFSET_ + , pmlmeinfo->hidden_ssid_mode + ); + pframe += (cur_network->IELength + len_diff); + pattrib->pktlen += (cur_network->IELength + len_diff); + } + + { + u8 *wps_ie; + uint wps_ielen; + u8 sr = 0; + wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, + pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_, NULL, &wps_ielen); + if (wps_ie && wps_ielen > 0) + rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8 *)(&sr), NULL); + if (sr != 0) + set_fwstate(pmlmepriv, WIFI_UNDER_WPS); + else + _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS); + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + u32 len; + { + len = build_beacon_p2p_ie(pwdinfo, pframe); + } + + pframe += len; + pattrib->pktlen += len; + + len = rtw_append_beacon_wfd_ie(padapter, pframe); + pframe += len; + pattrib->pktlen += len; + } + + goto _issue_bcn; + + } + + /* below for ad-hoc mode */ + + /* timestamp will be inserted by hardware */ + pframe += 8; + pattrib->pktlen += 8; + + /* beacon interval: 2 bytes */ + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + /* capability info: 2 bytes */ + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); + + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); + + /* if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) */ + { + u8 erpinfo = 0; + u32 ATIMWindow; + /* IBSS Parameter Set... */ + /* ATIMWindow = cur->Configuration.ATIMWindow; */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); + + /* ERP IE */ + pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); + } + + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); + + /* todo:HT for adhoc */ + +_issue_bcn: + + pmlmepriv->update_bcn = _FALSE; + + _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); + + if ((pattrib->pktlen + TXDESC_SIZE) > 512) { + RTW_INFO("beacon frame too large\n"); + return; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + /* RTW_INFO("issue bcn_sz=%d\n", pattrib->last_txcmdsz); */ + if (timeout_ms > 0) + dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms); + else + dump_mgntframe(padapter, pmgntframe); + +} + +void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac, *bssid; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + u8 *pwps_ie; + uint wps_ielen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + unsigned int rate_len; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u32 wfdielen = 0; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + if (da == NULL) + return; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + RTW_INFO("%s, alloc mgnt frame fail\n", __FUNCTION__); + return; + } + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + bssid = cur_network->MacAddress; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(fctrl, WIFI_PROBERSP); + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = pattrib->hdrlen; + pframe += pattrib->hdrlen; + + if (cur_network->IELength > MAX_IE_SZ) + return; + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + pwps_ie = rtw_get_wps_ie(cur_network->IEs + _FIXED_IE_LENGTH_, cur_network->IELength - _FIXED_IE_LENGTH_, NULL, &wps_ielen); + + /* inerset & update wps_probe_resp_ie */ + if ((pmlmepriv->wps_probe_resp_ie != NULL) && pwps_ie && (wps_ielen > 0)) { + uint wps_offset, remainder_ielen; + u8 *premainder_ie; + + wps_offset = (uint)(pwps_ie - cur_network->IEs); + + premainder_ie = pwps_ie + wps_ielen; + + remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; + + _rtw_memcpy(pframe, cur_network->IEs, wps_offset); + pframe += wps_offset; + pattrib->pktlen += wps_offset; + + wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];/* to get ie data len */ + if ((wps_offset + wps_ielen + 2) <= MAX_IE_SZ) { + _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen + 2); + pframe += wps_ielen + 2; + pattrib->pktlen += wps_ielen + 2; + } + + if ((wps_offset + wps_ielen + 2 + remainder_ielen) <= MAX_IE_SZ) { + _rtw_memcpy(pframe, premainder_ie, remainder_ielen); + pframe += remainder_ielen; + pattrib->pktlen += remainder_ielen; + } + } else { + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pattrib->pktlen += cur_network->IELength; + } + + /* retrieve SSID IE from cur_network->Ssid */ + { + u8 *ssid_ie; + sint ssid_ielen; + sint ssid_ielen_diff; + u8 buf[MAX_IE_SZ]; + u8 *ies = pmgntframe->buf_addr + TXDESC_OFFSET + sizeof(struct rtw_ieee80211_hdr_3addr); + + ssid_ie = rtw_get_ie(ies + _FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen, + (pframe - ies) - _FIXED_IE_LENGTH_); + + ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen; + + if (ssid_ie && cur_network->Ssid.SsidLength) { + uint remainder_ielen; + u8 *remainder_ie; + remainder_ie = ssid_ie + 2; + remainder_ielen = (pframe - remainder_ie); + + if (remainder_ielen > MAX_IE_SZ) { + RTW_WARN(FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter)); + remainder_ielen = MAX_IE_SZ; + } + + _rtw_memcpy(buf, remainder_ie, remainder_ielen); + _rtw_memcpy(remainder_ie + ssid_ielen_diff, buf, remainder_ielen); + *(ssid_ie + 1) = cur_network->Ssid.SsidLength; + _rtw_memcpy(ssid_ie + 2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength); + + pframe += ssid_ielen_diff; + pattrib->pktlen += ssid_ielen_diff; + } + } + } else + { + + /* timestamp will be inserted by hardware */ + pframe += 8; + pattrib->pktlen += 8; + + /* beacon interval: 2 bytes */ + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + /* capability info: 2 bytes */ + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + /* below for ad-hoc mode */ + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); + + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pattrib->pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + u8 erpinfo = 0; + u32 ATIMWindow; + /* IBSS Parameter Set... */ + /* ATIMWindow = cur->Configuration.ATIMWindow; */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); + + /* ERP IE */ + pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); + } + + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); + + /* todo:HT for adhoc */ + + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) + /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */ + && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) { + u32 len; + { + len = build_probe_resp_p2p_ie(pwdinfo, pframe); + } + + pframe += len; + pattrib->pktlen += len; + + len = rtw_append_probe_resp_wfd_ie(padapter, pframe); + pframe += len; + pattrib->pktlen += len; + } + + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac; + unsigned char bssrate[NumRates]; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int bssrate_len = 0; + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if (da) { + /* unicast probe request frame */ + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + } else { + /* broadcast probe request frame */ + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); + } + + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_PROBEREQ); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + if (pssid) + pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); + else + pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); + + get_rate_set(padapter, bssrate, &bssrate_len); + + if (bssrate_len > 8) { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); + } else + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); + + if (ch) + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen); + + if (append_wps) { + /* add wps_ie for wps2.0 */ + if (pmlmepriv->wps_probe_req_ie_len > 0 && pmlmepriv->wps_probe_req_ie) { + _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); + pframe += pmlmepriv->wps_probe_req_ie_len; + pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; + /* pmlmepriv->wps_probe_req_ie_len = 0 ; */ /* reset to zero */ + } + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da) +{ + _issue_probereq(padapter, pssid, da, 0, 1, _FALSE); +} + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, + int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return _FAIL; + + do { + ret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms > 0 ? _TRUE : _FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + +/* if psta == NULL, indiate we are station(client) now... */ +void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned int val32; + unsigned short val16; + int use_shared_key = 0; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_AUTH); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + if (psta) { /* for AP mode */ + + _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + /* setting auth algo number */ + val16 = (u16)psta->authalg; + + if (status != _STATS_SUCCESSFUL_) + val16 = 0; + + if (val16) { + val16 = cpu_to_le16(val16); + use_shared_key = 1; + } + + pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + /* setting auth seq number */ + val16 = (u16)psta->auth_seq; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + /* setting status code... */ + val16 = status; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); + + /* added challenging text... */ + if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) + pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen)); + } else { + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + + { + /* setting auth algo number */ + val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ? 1 : 0; /* 0:OPEN System, 1:Shared key */ + if (val16) { + val16 = cpu_to_le16(val16); + use_shared_key = 1; + } + } + + /* RTW_INFO("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); */ + + /* setting IV for auth seq #3 */ + if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) { + /* RTW_INFO("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); */ + val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30)); + val32 = cpu_to_le32(val32); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen)); + + pattrib->iv_len = 4; + } + + pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + /* setting auth seq number */ + val16 = pmlmeinfo->auth_seq; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + /* setting status code... */ + val16 = status; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); + + + /* then checking to see if sending challenging text... */ + if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key == 1)) { + pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen)); + + SetPrivacy(fctrl); + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pattrib->encrypt = _WEP40_; + + pattrib->icv_len = 4; + + pattrib->pktlen += pattrib->icv_len; + + } + + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + rtw_wep_encrypt(padapter, (u8 *)pmgntframe); + RTW_INFO("%s\n", __FUNCTION__); + dump_mgntframe(padapter, pmgntframe); + + return; +} + +void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type) +{ + struct xmit_frame *pmgntframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + unsigned char *pbuf, *pframe; + unsigned short val, ie_status; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + u8 *ie = pnetwork->IEs; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u32 wfdielen = 0; + + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; + + RTW_INFO("%s\n", __FUNCTION__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN); + _rtw_memcpy((void *)get_addr2_ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP)) + set_frame_sub_type(pwlanhdr, pkt_type); + else + return; + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen += pattrib->hdrlen; + pframe += pattrib->hdrlen; + + /* capability */ + val = *(unsigned short *)rtw_get_capability_from_ie(ie); + + pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen)); + + ie_status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen)); + + val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); + pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); + + if (pstat->bssratelen <= 8) + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen)); + else { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen - 8), pstat->bssrateset + 8, &(pattrib->pktlen)); + } + + + if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) { + uint ie_len = 0; + + /* FILL HT CAP INFO IE */ + /* p = hostapd_eid_ht_capabilities_info(hapd, p); */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } + + /* FILL HT ADD INFO IE */ + /* p = hostapd_eid_ht_operation(hapd, p); */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } + + } + + /*adding EXT_CAPAB_IE */ + if (pmlmepriv->ext_capab_ie_len > 0) { + uint ie_len = 0; + + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } + } + + if ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option) + && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP) + && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) { + u32 ie_len = 0; + + /* FILL VHT CAP IE */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } + + /* FILL VHT OPERATION IE */ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + } + } + + /* FILL WMM IE */ + if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) { + uint ie_len = 0; + unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + + for (pbuf = ie + _BEACON_IE_OFFSET_; ; pbuf += (ie_len + 2)) { + pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if (pbuf && _rtw_memcmp(pbuf + 2, WMM_PARA_IE, 6)) { + _rtw_memcpy(pframe, pbuf, ie_len + 2); + pframe += (ie_len + 2); + pattrib->pktlen += (ie_len + 2); + + break; + } + + if ((pbuf == NULL) || (ie_len == 0)) + break; + } + + } + + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); + + /* add WPS IE ie for wps 2.0 */ + if (pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len > 0) { + _rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); + + pframe += pmlmepriv->wps_assoc_resp_ie_len; + pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len; + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) { + u32 len; + + if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { + len = 0; + if (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) { + len = pmlmepriv->p2p_assoc_resp_ie_len; + _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len); + } + } else + len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code); + pframe += len; + pattrib->pktlen += len; + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + wfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +void _issue_assocreq(_adapter *padapter, u8 is_reassoc) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe, *p; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned short val16; + unsigned int i, j, ie_len, index = 0; + unsigned char rf_type, bssrate[NumRates], sta_bssrate[NumRates]; + PNDIS_802_11_VARIABLE_IEs pIE; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int bssrate_len = 0, sta_bssrate_len = 0; + u8 vs_ie_length = 0; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 p2pie[255] = { 0x00 }; + u16 p2pielen = 0; + u32 wfdielen = 0; + + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + if (is_reassoc == _TRUE) + set_frame_sub_type(pframe, WIFI_REASSOCREQ); + else + set_frame_sub_type(pframe, WIFI_ASSOCREQ); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* caps */ + + _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); + + pframe += 2; + pattrib->pktlen += 2; + + /* listen interval */ + /* todo: listen interval for power saving */ + val16 = cpu_to_le16(3); + _rtw_memcpy(pframe , (unsigned char *)&val16, 2); + pframe += 2; + pattrib->pktlen += 2; + + /*Construct Current AP Field for Reassoc-Req only*/ + if (is_reassoc == _TRUE) { + _rtw_memcpy(pframe, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + pframe += ETH_ALEN; + pattrib->pktlen += ETH_ALEN; + } + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen)); + + + /* supported rate & extended supported rate */ + + get_rate_set(padapter, sta_bssrate, &sta_bssrate_len); + /* RTW_INFO("sta_bssrate_len=%d\n", sta_bssrate_len); */ + + if (pmlmeext->cur_channel == 14) /* for JAPAN, channel 14 can only uses B Mode(CCK) */ + sta_bssrate_len = 4; + + /* for (i = 0; i < sta_bssrate_len; i++) { */ + /* RTW_INFO("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); */ + /* } */ + + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->network.SupportedRates[i] == 0) + break; + RTW_INFO("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]); + } + + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->network.SupportedRates[i] == 0) + break; + + /* Check if the AP's supported rates are also supported by STA. */ + for (j = 0; j < sta_bssrate_len; j++) { + /* Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP */ + if ((pmlmeinfo->network.SupportedRates[i] | IEEE80211_BASIC_RATE_MASK) + == (sta_bssrate[j] | IEEE80211_BASIC_RATE_MASK)) { + /* RTW_INFO("match i = %d, j=%d\n", i, j); */ + break; + } else { + /* RTW_INFO("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); */ + } + } + + if (j == sta_bssrate_len) { + /* the rate is not supported by STA */ + RTW_INFO("%s(): the rate[%d]=%02X is not supported by STA!\n", __FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]); + } else { + /* the rate is supported by STA */ + bssrate[index++] = pmlmeinfo->network.SupportedRates[i]; + } + } + + bssrate_len = index; + RTW_INFO("bssrate_len = %d\n", bssrate_len); + + if ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; /* don't connect to AP if no joint supported rate */ + } + + if (bssrate_len > 8) { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); + } else if (bssrate_len > 0) + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); + else + RTW_INFO("%s: Connect to AP without 11b and 11g data rate!\n", __FUNCTION__); + + /* vendor specific IE, such as WPA, WMM, WPS */ + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) || + (_rtw_memcmp(pIE->data, WMM_OUI, 4)) || + (_rtw_memcmp(pIE->data, WPS_OUI, 4))) { + vs_ie_length = pIE->Length; + if ((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) { + /* Commented by Kurt 20110629 */ + /* In some older APs, WPS handshake */ + /* would be fail if we append vender extensions informations to AP */ + + vs_ie_length = 14; + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen)); + } + break; + + case EID_WPA2: + pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; + case EID_HTCapability: + if (padapter->mlmepriv.htpriv.ht_option == _TRUE) { + if (!(is_ap_in_tkip(padapter))) { + _rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element)); + + pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); + + pframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen)); + } + } + break; + + case EID_EXTCapability: + if (padapter->mlmepriv.htpriv.ht_option == _TRUE) + pframe = rtw_set_ie(pframe, EID_EXTCapability, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; + case EID_VHTCapability: + if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE) + pframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; + + case EID_OpModeNotification: + if (padapter->mlmepriv.vhtpriv.vht_option == _TRUE) + pframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; + default: + break; + } + + i += (pIE->Length + 2); + } + + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); + + + { + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) { + /* Should add the P2P IE in the association request frame. */ + /* P2P OUI */ + + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20101109 */ + /* According to the P2P Specification, the association request frame should contain 3 P2P attributes */ + /* 1. P2P Capability */ + /* 2. Extended Listen Timing */ + /* 3. Device Info */ + /* Commented by Albert 20110516 */ + /* 4. P2P Interface */ + + /* P2P Capability */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0002); + p2pielen += 2; + + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + + /* Group Capability Bitmap, 1 byte */ + if (pwdinfo->persistent_supported) + p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; + + /* Extended Listen Timing */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x0004); + p2pielen += 2; + + /* Value: */ + /* Availability Period */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); + p2pielen += 2; + + /* Availability Interval */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0xFFFF); + p2pielen += 2; + + /* Device Info */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + + /* Length: */ + /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ + /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(21 + pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address */ + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Config Method */ + /* This field should be big endian. Noted by P2P specification. */ + if ((pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN) || + (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN)) + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_DISPLAY); + else + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_CONFIG_METHOD_PBC); + + p2pielen += 2; + + /* Primary Device Type */ + /* Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + /* OUI */ + *(u32 *)(p2pie + p2pielen) = cpu_to_be32(WPSOUI); + p2pielen += 4; + + /* Sub Category ID */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + + /* Number of Secondary Device Types */ + p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ + + /* Device Name */ + /* Type: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_be16(pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); + p2pielen += pwdinfo->device_name_len; + + /* P2P Interface */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_INTERFACE; + + /* Length: */ + *(u16 *)(p2pie + p2pielen) = cpu_to_le16(0x000D); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); /* P2P Device Address */ + p2pielen += ETH_ALEN; + + p2pie[p2pielen++] = 1; /* P2P Interface Address Count */ + + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); /* P2P Interface Address List */ + p2pielen += ETH_ALEN; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen); + } + } + + + wfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(padapter, pmgntframe); + + ret = _SUCCESS; + +exit: + if (ret == _SUCCESS) + rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen); + else + rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); + + return; +} + +void issue_assocreq(_adapter *padapter) +{ + _issue_assocreq(padapter, _FALSE); +} + +void issue_reassocreq(_adapter *padapter) +{ + _issue_assocreq(padapter, _TRUE); +} + +/* when wait_ack is ture, this function shoule be called at process context */ +static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + + /* RTW_INFO("%s:%d\n", __FUNCTION__, power_mode); */ + + if (!padapter) + goto exit; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + + pxmitpriv = &(padapter->xmitpriv); + pmlmeext = &(padapter->mlmeextpriv); + pmlmeinfo = &(pmlmeext->mlmext_info); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + SetFrDs(fctrl); + else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + SetToDs(fctrl); + + if (power_mode) + SetPwrMgt(fctrl); + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_DATA_NULL); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +/* + * [IMPORTANT] Don't call this function in interrupt context + * + * When wait_ms > 0, this function should be called at process context + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + * da == NULL for station mode + */ +int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_info *psta; + u8 macid_sleep_reg_access = _TRUE; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return _FAIL; + + /* da == NULL, assum it's null data for sta to ap*/ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); + + psta = rtw_get_stainfo(&padapter->stapriv, da); + if (psta) { + if (macid_sleep_reg_access) { + if (power_mode) + rtw_hal_macid_sleep(padapter, psta->mac_id); + else + rtw_hal_macid_wakeup(padapter, psta->mac_id); + } + } else { + RTW_INFO(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode ? "sleep" : "wakeup"); + rtw_warn_on(1); + } + + do { + ret = _issue_nulldata(padapter, da, power_mode, wait_ms > 0 ? _TRUE : _FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + +/* + * [IMPORTANT] This function run in interrupt context + * + * The null data packet would be sent without power bit, + * and not guarantee success. + */ +s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode) +{ + int ret; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + /* da == NULL, assum it's null data for sta to ap*/ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); + + ret = _issue_nulldata(padapter, da, power_mode, _FALSE); + + return ret; +} + +/* when wait_ack is ture, this function shoule be called at process context */ +static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl, *qc; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + + RTW_INFO("%s\n", __FUNCTION__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + pattrib->hdrlen += 2; + pattrib->qos_en = _TRUE; + pattrib->eosp = 1; + pattrib->ack_policy = 0; + pattrib->mdata = 0; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) + SetFrDs(fctrl); + else if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + SetToDs(fctrl); + + if (pattrib->mdata) + SetMData(fctrl); + + qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); + + SetPriority(qc, tid); + + SetEOSP(qc, pattrib->eosp); + + SetAckpolicy(qc, pattrib->ack_policy); + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +/* + * when wait_ms >0 , this function should be called at process context + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + * da == NULL for station mode + */ +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return _FAIL; + + /* da == NULL, assum it's null data for sta to ap*/ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); + + do { + ret = _issue_qos_nulldata(padapter, da, tid, wait_ms > 0 ? _TRUE : _FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + +static int _issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason, u8 wait_ack, u8 key_type) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int ret = _FAIL; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + /* RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); */ + + if (!(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) && (pwdinfo->rx_invitereq_info.scan_op_ch_only)) { + _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); + _set_timer(&pwdinfo->reset_ch_sitesurvey, 10); + } + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + pattrib->key_type = key_type; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_DEAUTH); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + reason = cpu_to_le16(reason); + pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen)); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason) +{ + RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); + return _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY); +} + + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, + int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return _FAIL; + + do { + ret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE : _FALSE, IEEE80211W_RIGHT_KEY); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + +void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset) +{ + _irqL irqL; + _list *plist, *phead; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; + + RTW_INFO(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ + _rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */ + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* category, action */ + { + u8 category, action; + category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT; + action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH; + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + } + + pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0); + pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen), + hal_ch_offset_to_secondary_ch_offset(ch_offset)); + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + + +/** + * issue_action_ba - internal function to TX Block Ack action frame + * @padapter: the adapter to TX + * @raddr: receiver address + * @action: Block Ack Action + * @tid: tid + * @size: the announced AMPDU buffer size. used by ADDBA_RESP + * @status: status/reason code. used by ADDBA_RESP, DELBA + * @initiator: if we are the initiator of AMPDU association. used by DELBA + * @wait_ack: used xmit ack + * + * Returns: + * _SUCCESS: No xmit ack is used or acked + * _FAIL: not acked when using xmit ack + */ +static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned char action + , u8 tid, u8 size, u16 status, u8 initiator, int wait_ack) +{ + int ret = _FAIL; + u8 category = RTW_WLAN_CATEGORY_BACK; + u16 start_seq; + u16 BA_para_set; + u16 BA_timeout_value; + u16 BA_starting_seqctrl; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + u8 *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + goto exit; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto exit; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + /* _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); */ + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + if (category == 3) { + switch (action) { + case RTW_WLAN_ACTION_ADDBA_REQ: + do { + pmlmeinfo->dialogToken++; + } while (pmlmeinfo->dialogToken == 0); + pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen)); + + BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */ + + BA_para_set = cpu_to_le16(BA_para_set); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + + /* BA_timeout_value = 0xffff; */ /* max: 65535 TUs(~ 65 ms) */ + BA_timeout_value = 5000;/* ~ 5ms */ + BA_timeout_value = cpu_to_le16(BA_timeout_value); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen)); + + /* if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) */ + psta = rtw_get_stainfo(pstapriv, raddr); + if (psta != NULL) { + start_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07] & 0xfff) + 1; + + RTW_INFO("BA_starting_seqctrl = %d for TID=%d\n", start_seq, tid & 0x07); + + psta->BA_starting_seqctrl[tid & 0x07] = start_seq; + + BA_starting_seqctrl = start_seq << 4; + } + + BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen)); + break; + + case RTW_WLAN_ACTION_ADDBA_RESP: + pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen)); + status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen)); + + BA_para_set = le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set); + + BA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK; + BA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK; + + BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; + BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; + + if (!padapter->registrypriv.wifi_spec) { + if (pregpriv->rx_ampdu_amsdu == 0) /* disabled */ + BA_para_set &= ~BIT(0); + else if (pregpriv->rx_ampdu_amsdu == 1) /* enabled */ + BA_para_set |= BIT(0); + } + + BA_para_set = cpu_to_le16(BA_para_set); + + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen)); + break; + + case RTW_WLAN_ACTION_DELBA: + BA_para_set = 0; + BA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK; + BA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK; + + BA_para_set = cpu_to_le16(BA_para_set); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen)); + break; + default: + break; + } + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +/** + * issue_addba_req - TX ADDBA_REQ + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + */ +inline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid) +{ + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ + , tid + , 0 /* unused */ + , 0 /* unused */ + , 0 /* unused */ + , _FALSE + ); + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid); + +} + +/** + * issue_addba_rsp - TX ADDBA_RESP + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @status: status code + * @size: the announced AMPDU buffer size + */ +inline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size) +{ + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP + , tid + , size + , status + , 0 /* unused */ + , _FALSE + ); + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" status=%u, tid=%u, size=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size); +} + +/** + * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @status: status code + * @size: the announced AMPDU buffer size + * @try_cnt: the maximal TX count to try + * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + */ +inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) + return _FAIL; + + do { + ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP + , tid + , size + , status + , 0 /* unused */ + , _TRUE + ); + + i++; + + if (RTW_CANNOT_RUN(adapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + +/** + * issue_del_ba - TX DELBA + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @reason: reason code + * @initiator: if we are the initiator of AMPDU association. used by DELBA + */ +inline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator) +{ + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA + , tid + , 0 /* unused */ + , reason + , initiator + , _FALSE + ); + RTW_INFO(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator); +} + +/** + * issue_del_ba_ex - TX DELBA with xmit ack options + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @reason: reason code + * @initiator: if we are the initiator of AMPDU association. used by DELBA + * @try_cnt: the maximal TX count to try + * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + */ +int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator + , int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(adapter))) + return _FAIL; + + do { + ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA + , tid + , 0 /* unused */ + , reason + , initiator + , wait_ms > 0 ? _TRUE : _FALSE + ); + + i++; + + if (RTW_CANNOT_RUN(adapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + +static void issue_action_BSSCoexistPacket(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + unsigned char category, action; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct wlan_network *pnetwork = NULL; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + _queue *queue = &(pmlmepriv->scanned_queue); + u8 InfoContent[16] = {0}; + u8 ICS[8][15]; + if ((pmlmepriv->num_FortyMHzIntolerant == 0) || (pmlmepriv->num_sta_no_ht == 0)) + return; + + if (_TRUE == pmlmeinfo->bwmode_updated) + return; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return; + + RTW_INFO("%s\n", __FUNCTION__); + + category = RTW_WLAN_CATEGORY_PUBLIC; + action = ACT_PUBLIC_BSSCOEXIST; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + /* */ + if (pmlmepriv->num_FortyMHzIntolerant > 0) { + u8 iedata = 0; + + iedata |= BIT(2);/* 20 MHz BSS Width Request */ + + pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); + + } + + /* */ + _rtw_memset(ICS, 0, sizeof(ICS)); + if (pmlmepriv->num_sta_no_ht > 0) { + int i; + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + int len; + u8 *p; + WLAN_BSSID_EX *pbss_network; + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + plist = get_next(plist); + + pbss_network = (WLAN_BSSID_EX *)&pnetwork->network; + + p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_); + if ((p == NULL) || (len == 0)) { /* non-HT */ + if ((pbss_network->Configuration.DSConfig <= 0) || (pbss_network->Configuration.DSConfig > 14)) + continue; + + ICS[0][pbss_network->Configuration.DSConfig] = 1; + + if (ICS[0][0] == 0) + ICS[0][0] = 1; + } + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + for (i = 0; i < 8; i++) { + if (ICS[i][0] == 1) { + int j, k = 0; + + InfoContent[k] = i; + /* SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); */ + k++; + + for (j = 1; j <= 14; j++) { + if (ICS[i][j] == 1) { + if (k < 16) { + InfoContent[k] = j; /* channel number */ + /* SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); */ + k++; + } + } + } + + pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen)); + + } + + } + + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); +} + +/* Spatial Multiplexing Powersave (SMPS) action frame */ +int _issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode , u8 wait_ack) +{ + + int ret = _FAIL; + unsigned char category = RTW_WLAN_CATEGORY_HT; + u8 action = RTW_WLAN_ACTION_HT_SM_PS; + u8 sm_power_control = 0; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DISABLED) { + sm_power_control = sm_power_control & ~(BIT(0)); /* SM Power Save Enable = 0 SM Power Save Disable */ + } else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_STATIC) { + sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable */ + sm_power_control = sm_power_control & ~(BIT(1)); /* SM Mode = 0 Static Mode */ + } else if (NewMimoPsMode == WLAN_HT_CAP_SM_PS_DYNAMIC) { + sm_power_control = sm_power_control | BIT(0); /* SM Power Save Enable = 1 SM Power Save Enable */ + sm_power_control = sm_power_control | BIT(1); /* SM Mode = 1 Dynamic Mode */ + } else + return ret; + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return ret; + + RTW_INFO("%s, sm_power_control=%u, NewMimoPsMode=%u\n", __FUNCTION__ , sm_power_control , NewMimoPsMode); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return ret; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */ + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* category, action */ + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + pframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen)); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + + if (ret != _SUCCESS) + RTW_INFO("%s, ack to\n", __func__); + + return ret; +} + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_ch_waiting(adapter_to_rfctl(padapter))) + return _FAIL; + + do { + ret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms > 0 ? _TRUE : _FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + return ret == _FAIL ? _FAIL : _SUCCESS; +} + +int issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode) +{ + RTW_INFO("%s to "MAC_FMT"\n", __func__, MAC_ARG(raddr)); + return _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , _FALSE); +} + +/** + * _send_delba_sta_tid - Cancel the AMPDU association for the specific @sta, @tid + * @adapter: the adapter to which @sta belongs + * @initiator: if we are the initiator of AMPDU association + * @sta: the sta to be checked + * @tid: the tid to be checked + * @force: cancel and send DELBA even when no AMPDU association is setup + * @wait_ack: send delba with xmit ack (valid when initiator == 0) + * + * Returns: + * _FAIL if sta is NULL + * when initiator is 1, always _SUCCESS + * when initiator is 0, _SUCCESS if DELBA is acked + */ +static unsigned int _send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force, int wait_ack) +{ + int ret = _SUCCESS; + + if (sta == NULL) { + ret = _FAIL; + goto exit; + } + + if (initiator == 0) { + /* recipient */ + if (force || sta->recvreorder_ctrl[tid].enable == _TRUE) { + u8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size; + + sta->recvreorder_ctrl[tid].enable = _FALSE; + sta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID; + + if (rtw_del_rx_ampdu_test_trigger_no_tx_fail()) + ret = _FAIL; + else if (wait_ack) + ret = issue_del_ba_ex(adapter, sta->hwaddr, tid, 37, initiator, 3, 1); + else + issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + + if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE) + sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak; + } + } else if (initiator == 1) { + /* originator */ + if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) { + sta->htpriv.agg_enable_bitmap &= ~BIT(tid); + sta->htpriv.candidate_tid_bitmap &= ~BIT(tid); + issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + } + } + +exit: + return ret; +} + +inline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force) +{ + return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0); +} + +inline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force) +{ + return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1); +} + +unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u16 tid; + + if ((pmlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) + return _SUCCESS; + + psta = rtw_get_stainfo(pstapriv, addr); + if (psta == NULL) + return _SUCCESS; + + for (tid = 0; tid < TID_NUM; tid++) + send_delba_sta_tid(padapter, initiator, psta, tid, 0); + + return _SUCCESS; +} + +unsigned int send_beacon(_adapter *padapter) +{ + u8 bxmitok = _FALSE; + int issue = 0; + int poll = 0; +#if defined(RTL8814AE_SW_BCN) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); +#endif + + /* bypass TX BCN queue because op ch is switching/waiting */ + if (check_fwstate(&padapter->mlmepriv, WIFI_OP_CH_SWITCHING) + ) + return _SUCCESS; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + + /* 8192EE Port select for Beacon DL */ + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + + issue_beacon(padapter, 0); + +#ifdef RTL8814AE_SW_BCN + if (pHalData->bCorrectBCN != 0) + RTW_INFO("%s, line%d, Warnning, pHalData->bCorrectBCN != 0\n", __func__, __LINE__); + pHalData->bCorrectBCN = 1; +#endif + + return _SUCCESS; + +} + +/**************************************************************************** + +Following are some utitity fuctions for WiFi MLME + +*****************************************************************************/ + +BOOLEAN IsLegal5GChannel( + IN PADAPTER Adapter, + IN u8 channel) +{ + + int i = 0; + u8 Channel_5G[45] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, + 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, + 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, + 161, 163, 165 + }; + for (i = 0; i < sizeof(Channel_5G); i++) + if (channel == Channel_5G[i]) + return _TRUE; + return _FALSE; +} + +/* collect bss info from Beacon and Probe request/response frames. */ +u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid) +{ + int i; + u32 len; + u8 *p; + u16 val16, subtype; + u8 *pframe = precv_frame->u.hdr.rx_data; + u32 packet_len = precv_frame->u.hdr.len; + u8 ie_offset; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); + + if (len > MAX_IE_SZ) { + /* RTW_INFO("IE too long for survey event\n"); */ + return _FAIL; + } + + _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX)); + + subtype = get_frame_sub_type(pframe); + + if (subtype == WIFI_BEACON) { + bssid->Reserved[0] = 1; + ie_offset = _BEACON_IE_OFFSET_; + } else { + /* FIXME : more type */ + if (subtype == WIFI_PROBERSP) { + ie_offset = _PROBERSP_IE_OFFSET_; + bssid->Reserved[0] = 3; + } else if (subtype == WIFI_PROBEREQ) { + ie_offset = _PROBEREQ_IE_OFFSET_; + bssid->Reserved[0] = 2; + } else { + bssid->Reserved[0] = 0; + ie_offset = _FIXED_IE_LENGTH_; + } + } + + bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; + + /* below is to copy the information element */ + bssid->IELength = len; + _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); + + /* get the signal strength */ + /* bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; */ /* 0-100 index. */ + bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; /* in dBM.raw data */ + bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.SignalQuality;/* in percentage */ + bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.SignalStrength;/* in percentage */ + + /* checking SSID */ + p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset); + if (p == NULL) { + RTW_INFO("marc: cannot find SSID for survey event\n"); + return _FAIL; + } + + if (*(p + 1)) { + if (len > NDIS_802_11_LENGTH_SSID) { + RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } + _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); + bssid->Ssid.SsidLength = *(p + 1); + } else + bssid->Ssid.SsidLength = 0; + + _rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); + + /* checking rate info... */ + i = 0; + p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); + if (p != NULL) { + if (len > NDIS_802_11_LENGTH_RATES_EX) { + RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } + _rtw_memcpy(bssid->SupportedRates, (p + 2), len); + i = len; + } + + p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); + if (p != NULL) { + if (len > (NDIS_802_11_LENGTH_RATES_EX - i)) { + RTW_INFO("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } + _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len); + } + + bssid->NetworkTypeInUse = Ndis802_11OFDM24; + + if (subtype == WIFI_PROBEREQ) { + u8 *p2p_ie; + u32 p2p_ielen; + /* Set Listion Channel */ + p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen); + if (p2p_ie) { + u32 attr_contentlen = 0; + u8 listen_ch[5] = { 0x00 }; + + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen); + bssid->Configuration.DSConfig = listen_ch[4]; + } else { + /* use current channel */ + bssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel; + RTW_INFO("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig); + } + + /* FIXME */ + bssid->InfrastructureMode = Ndis802_11Infrastructure; + _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); + bssid->Privacy = 1; + return _SUCCESS; + } + + if (bssid->IELength < 12) + return _FAIL; + + /* Checking for DSConfig */ + p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset); + + bssid->Configuration.DSConfig = 0; + bssid->Configuration.Length = 0; + + if (p) + bssid->Configuration.DSConfig = *(p + 2); + else { + /* In 5G, some ap do not have DSSET IE */ + /* checking HT info for channel */ + p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset); + if (p) { + struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2); + bssid->Configuration.DSConfig = HT_info->primary_channel; + } else { + /* use current channel */ + bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter); + } + } + + _rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2); + bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod); + + val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); + + if (val16 & BIT(0)) { + bssid->InfrastructureMode = Ndis802_11Infrastructure; + _rtw_memcpy(bssid->MacAddress, get_addr2_ptr(pframe), ETH_ALEN); + } else { + bssid->InfrastructureMode = Ndis802_11IBSS; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } + + if (val16 & BIT(4)) + bssid->Privacy = 1; + else + bssid->Privacy = 0; + + bssid->Configuration.ATIMWindow = 0; + + /* 20/40 BSS Coexistence check */ + if ((pregistrypriv->wifi_spec == 1) && (_FALSE == pmlmeinfo->bwmode_updated)) { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset); + if (p && len > 0) { + struct HT_caps_element *pHT_caps; + pHT_caps = (struct HT_caps_element *)(p + 2); + + if (pHT_caps->u.HT_cap_element.HT_caps_info & BIT(14)) + pmlmepriv->num_FortyMHzIntolerant++; + } else + pmlmepriv->num_sta_no_ht++; + + } + + + /* mark bss info receving from nearby channel as SignalQuality 101 */ + if (bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter)) + bssid->PhyInfo.SignalQuality = 101; + + return _SUCCESS; +} + +void start_create_ibss(_adapter *padapter) +{ + unsigned short caps; + u8 val8; + u8 join_type; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u8 doiqk = _FALSE; + pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig; + pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); + + /* update wireless mode */ + update_wireless_mode(padapter); + + /* udpate capability */ + caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); + update_capinfo(padapter, caps); + if (caps & cap_IBSS) { /* adhoc master */ + /* set_opmode_cmd(padapter, adhoc); */ /* removed */ + + val8 = 0xcf; + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + /* switch channel */ + set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + beacon_timing_control(padapter); + + /* set msr to WIFI_FW_ADHOC_STATE */ + pmlmeinfo->state = WIFI_FW_ADHOC_STATE; + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + + /* issue beacon */ + if (send_beacon(padapter) == _FAIL) { + + report_join_res(padapter, -1); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else { + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); + join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + + report_join_res(padapter, 1); + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + rtw_indicate_connect(padapter); + } + } else { + RTW_INFO("start_create_ibss, invalid cap:%x\n", caps); + return; + } + /* update bc/mc sta_info */ + update_bmc_sta(padapter); + +} + +void start_clnt_join(_adapter *padapter) +{ + unsigned short caps; + u8 val8; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + int beacon_timeout; + u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; + + /* update wireless mode */ + update_wireless_mode(padapter); + + /* udpate capability */ + caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); + update_capinfo(padapter, caps); + + /* check if sta is ASIX peer and fix IOT issue if it is. */ + if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) { + u8 iot_flag = _TRUE; + rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); + } + + if (caps & cap_ESS) { + Set_MSR(padapter, WIFI_FW_STATION_STATE); + + val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) ? 0xcc : 0xcf; + + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + +#ifdef CONFIG_DEAUTH_BEFORE_CONNECT + /* Because of AP's not receiving deauth before */ + /* AP may: 1)not response auth or 2)deauth us after link is complete */ + /* issue deauth before issuing auth to deal with the situation */ + + /* Commented by Albert 2012/07/21 */ + /* For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. */ + { + _queue *queue = &(padapter->mlmepriv.scanned_queue); + _list *head = get_list_head(queue); + _list *pos = get_next(head); + struct wlan_network *scanned = NULL; + u8 ie_offset = 0; + _irqL irqL; + bool has_p2p_ie = _FALSE; + + _enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); + + for (pos = get_next(head); !rtw_end_of_queue_search(head, pos); pos = get_next(pos)) { + + scanned = LIST_CONTAINOR(pos, struct wlan_network, list); + + if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE + && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE + ) { + ie_offset = (scanned->network.Reserved[0] == 2 ? 0 : 12); + if (rtw_get_p2p_ie(scanned->network.IEs + ie_offset, scanned->network.IELength - ie_offset, NULL, NULL)) + has_p2p_ie = _TRUE; + break; + } + } + + _exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); + + if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE) + /* To avoid connecting to AP fail during resume process, change retry count from 5 to 1 */ + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); + } +#endif /* CONFIG_DEAUTH_BEFORE_CONNECT */ + + /* here wait for receiving the beacon to start auth */ + /* and enable a timer */ + beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval); + set_link_timer(pmlmeext, beacon_timeout); + _set_timer(&padapter->mlmepriv.assoc_timer, + (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO * REASSOC_LIMIT) + beacon_timeout); + + { + rtw_sta_linking_test_set_start(); + pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; + } + } else if (caps & cap_IBSS) { /* adhoc client */ + Set_MSR(padapter, WIFI_FW_ADHOC_STATE); + + val8 = 0xcf; + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + + beacon_timing_control(padapter); + + pmlmeinfo->state = WIFI_FW_ADHOC_STATE; + + report_join_res(padapter, 1); + } else { + /* RTW_INFO("marc: invalid cap:%x\n", caps); */ + return; + } + +} + +void start_clnt_auth(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + _cancel_timer_ex(&pmlmeext->link_timer); + + pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL); + pmlmeinfo->state |= WIFI_FW_AUTH_STATE; + + pmlmeinfo->auth_seq = 1; + pmlmeinfo->reauth_count = 0; + pmlmeinfo->reassoc_count = 0; + pmlmeinfo->link_count = 0; + pmlmeext->retry = 0; + + RTW_PRINT("start auth\n"); + issue_auth(padapter, NULL, 0); + + set_link_timer(pmlmeext, REAUTH_TO); + +} + +void start_clnt_assoc(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + _cancel_timer_ex(&pmlmeext->link_timer); + + pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE)); + pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); + + issue_assocreq(padapter); + + set_link_timer(pmlmeext, REASSOC_TO); +} + +unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) + return _SUCCESS; + + RTW_INFO("%s\n", __FUNCTION__); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { + if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL) + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) { + if (report_join_res(padapter, -2) != _FAIL) + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else + RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter)); + } + + return _SUCCESS; +} + +static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) +{ + struct registry_priv *pregistrypriv; + struct mlme_ext_priv *pmlmeext; + RT_CHANNEL_INFO *chplan_new; + u8 channel; + u8 i; + + pregistrypriv = &padapter->registrypriv; + pmlmeext = &padapter->mlmeextpriv; + + /* Adjust channel plan by AP Country IE */ + if (pregistrypriv->enable80211d + && (!pmlmeext->update_channel_plan_by_ap_done)) { + u8 *ie, *p; + u32 len; + RT_CHANNEL_PLAN chplan_ap; + RT_CHANNEL_INFO chplan_sta[MAX_CHANNEL_NUM]; + u8 country[4]; + u8 fcn; /* first channel number */ + u8 noc; /* number of channel */ + u8 j, k; + + ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); + if (!ie) + return; + if (len < 6) + return; + + ie += 2; + p = ie; + ie += len; + + _rtw_memset(country, 0, 4); + _rtw_memcpy(country, p, 3); + p += 3; + RTW_INFO("%s: 802.11d country=%s\n", __FUNCTION__, country); + + i = 0; + while ((ie - p) >= 3) { + fcn = *(p++); + noc = *(p++); + p++; + + for (j = 0; j < noc; j++) { + if (fcn <= 14) + channel = fcn + j; /* 2.4 GHz */ + else + channel = fcn + j * 4; /* 5 GHz */ + + chplan_ap.Channel[i++] = channel; + } + } + chplan_ap.Len = i; + + i = 0; + RTW_INFO("%s: AP[%s] channel plan {", __FUNCTION__, bssid->Ssid.Ssid); + while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) { + _RTW_INFO("%02d,", chplan_ap.Channel[i]); + i++; + } + _RTW_INFO("}\n"); + + _rtw_memcpy(chplan_sta, pmlmeext->channel_set, sizeof(chplan_sta)); + i = 0; + RTW_INFO("%s: STA channel plan {", __FUNCTION__); + while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) { + _RTW_INFO("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].ScanType == SCAN_PASSIVE ? 'p' : 'a'); + i++; + } + _RTW_INFO("}\n"); + + _rtw_memset(pmlmeext->channel_set, 0, sizeof(pmlmeext->channel_set)); + chplan_new = pmlmeext->channel_set; + + i = j = k = 0; + if (pregistrypriv->wireless_mode & WIRELESS_11G) { + do { + if ((i == MAX_CHANNEL_NUM) + || (chplan_sta[i].ChannelNum == 0) + || (chplan_sta[i].ChannelNum > 14)) + break; + + if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14)) + break; + + if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + i++; + j++; + k++; + } else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } while (1); + + /* change AP not support channel to Passive scan */ + while ((i < MAX_CHANNEL_NUM) + && (chplan_sta[i].ChannelNum != 0) + && (chplan_sta[i].ChannelNum <= 14)) { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } + + /* add channel AP supported */ + while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } else { + /* keep original STA 2.4G channel plan */ + while ((i < MAX_CHANNEL_NUM) + && (chplan_sta[i].ChannelNum != 0) + && (chplan_sta[i].ChannelNum <= 14)) { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = chplan_sta[i].ScanType; + i++; + k++; + } + + /* skip AP 2.4G channel plan */ + while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) + j++; + } + + if (pregistrypriv->wireless_mode & WIRELESS_11A) { + do { + if ((i >= MAX_CHANNEL_NUM) + || (chplan_sta[i].ChannelNum == 0)) + break; + + if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0)) + break; + + if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + i++; + j++; + k++; + } else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } while (1); + + /* change AP not support channel to Passive scan */ + while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } + + /* add channel AP supported */ + while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } else { + /* keep original STA 5G channel plan */ + while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = chplan_sta[i].ScanType; + i++; + k++; + } + } + + pmlmeext->update_channel_plan_by_ap_done = 1; + + k = 0; + RTW_INFO("%s: new STA channel plan {", __FUNCTION__); + while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) { + _RTW_INFO("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].ScanType == SCAN_PASSIVE ? 'p' : 'c'); + k++; + } + _RTW_INFO("}\n"); + } + + /* If channel is used by AP, set channel scan type to active */ + channel = bssid->Configuration.DSConfig; + chplan_new = pmlmeext->channel_set; + i = 0; + while (i < MAX_CHANNEL_NUM && chplan_new[i].ChannelNum != 0) { + if (chplan_new[i].ChannelNum == channel) { + if (chplan_new[i].ScanType == SCAN_PASSIVE) { + /* 5G Bnad 2, 3 (DFS) doesn't change to active scan */ + if (rtw_is_dfs_ch(channel)) + break; + + chplan_new[i].ScanType = SCAN_ACTIVE; + RTW_INFO("%s: change channel %d scan type from passive to active\n", + __FUNCTION__, channel); + } + break; + } + i++; + } +} + +/**************************************************************************** + +Following are the functions to report events + +*****************************************************************************/ + +void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct survey_event *psurvey_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext; + struct cmd_priv *pcmdpriv; + /* u8 *pframe = precv_frame->u.hdr.rx_data; */ + /* uint len = precv_frame->u.hdr.len; */ + int ch_set_idx = -1; + + if (!padapter) + return; + + pmlmeext = &padapter->mlmeextpriv; + pcmdpriv = &padapter->cmdpriv; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + + cmdsz = (sizeof(struct survey_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct survey_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_Survey); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + psurvey_evt = (struct survey_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + + if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pevtcmd, cmdsz); + return; + } + + process_80211d(padapter, &psurvey_evt->bss); + + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + pmlmeext->sitesurvey_res.bss_cnt++; + + return; + +} + +void report_surveydone_event(_adapter *padapter) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct surveydone_event *psurveydone_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + + cmdsz = (sizeof(struct surveydone_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct surveydone_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_SurveyDone); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + psurveydone_evt = (struct surveydone_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt; + + RTW_INFO("survey done event(%x) band:%d for "ADPT_FMT"\n", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter)); + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; + +} + +u32 report_join_res(_adapter *padapter, int res) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct joinbss_event *pjoinbss_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u32 ret = _FAIL; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + goto exit; + + cmdsz = (sizeof(struct joinbss_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + goto exit; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct joinbss_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_JoinBss); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + pjoinbss_evt = (struct joinbss_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); + pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res; + + RTW_INFO("report_join_res(%d)\n", res); + + rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network); + + ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + +exit: + return ret; +} + +void report_wmm_edca_update(_adapter *padapter) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct wmm_event *pwmm_event; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + + cmdsz = (sizeof(struct wmm_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct wmm_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_WMM); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + pwmm_event = (struct wmm_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + pwmm_event->wmm = 0; + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; + +} + +u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct sta_info *psta; + int mac_id = -1; + struct stadel_event *pdel_sta_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + /* prepare cmd parameter */ + cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + res = _FAIL; + goto exit; + } + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct stadel_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_DelSTA); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); + _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); + psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); + if (psta) + mac_id = (int)psta->mac_id; + else + mac_id = (-1); + pdel_sta_evt->mac_id = mac_id; + pdel_sta_evt->locally_generated = locally_generated; + + if (!enqueue) { + /* do directly */ + rtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt); + rtw_mfree(pevtcmd, cmdsz); + } else { + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) { + rtw_mfree(pevtcmd, cmdsz); + res = _FAIL; + goto exit; + } + + _rtw_init_listhead(&pcmd_obj->list); + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + res = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + } + +exit: + + RTW_INFO(FUNC_ADPT_FMT" "MAC_FMT" mac_id=%d, enqueue:%d, res:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res); + + return res; +} + +void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct stassoc_event *padd_sta_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + + cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct stassoc_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_AddSTA); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + padd_sta_evt = (struct stassoc_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN); + + RTW_INFO("report_add_sta_event: add STA\n"); + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; +} + +bool rtw_port_switch_chk(_adapter *adapter) +{ + bool switch_needed = _FALSE; + return switch_needed; +} + +/**************************************************************************** + +Following are the event callback functions + +*****************************************************************************/ + +/* for sta/adhoc mode */ +void update_sta_info(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* ERP */ + VCS_update(padapter, psta); + + /* HT */ + if (pmlmepriv->htpriv.ht_option) { + psta->htpriv.ht_option = _TRUE; + + psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable; + + psta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & IEEE80211_HT_CAP_AMPDU_DENSITY) >> 2; + + if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20)) + psta->htpriv.sgi_20m = _TRUE; + + if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40)) + psta->htpriv.sgi_40m = _TRUE; + + psta->qos_option = _TRUE; + + psta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap; + psta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap; + psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; + + _rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap)); + } else + { + psta->htpriv.ht_option = _FALSE; + psta->htpriv.ampdu_enable = _FALSE; + psta->htpriv.tx_amsdu_enable = _FALSE; + psta->htpriv.sgi_20m = _FALSE; + psta->htpriv.sgi_40m = _FALSE; + psta->qos_option = _FALSE; + + } + + psta->htpriv.ch_offset = pmlmeext->cur_ch_offset; + + psta->htpriv.agg_enable_bitmap = 0x0;/* reset */ + psta->htpriv.candidate_tid_bitmap = 0x0;/* reset */ + + psta->bw_mode = pmlmeext->cur_bwmode; + + /* QoS */ + if (pmlmepriv->qospriv.qos_option) + psta->qos_option = _TRUE; + + _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); + + update_ldpc_stbc_cap(psta); + + _enter_critical_bh(&psta->lock, &irqL); + psta->state = _FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + +} + +static void rtw_mlmeext_disconnect(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u8 state_backup = (pmlmeinfo->state & 0x03); + u8 ASIX_ID[] = {0x00, 0x0E, 0xC6}; + + /* set_opmode_cmd(padapter, infra_client_with_mlme); */ + + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); + + /* set MSR to no link state->infra. mode */ + Set_MSR(padapter, _HW_STATE_STATION_); + + /* check if sta is ASIX peer and fix IOT issue if it is. */ + if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) , ASIX_ID , 3)) { + u8 iot_flag = _FALSE; + rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); + } + pmlmeinfo->state = WIFI_FW_NULL_STATE; + + if (state_backup == WIFI_FW_STATION_STATE) { + if (rtw_port_switch_chk(padapter) == _TRUE) { + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); + { + _adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter)); + if (port0_iface) + rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, 0); + } + } + } + + /* switch to the 20M Hz mode after disconnect */ + pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + +#ifdef CONFIG_FCS_MODE + if (EN_FCS(padapter)) + rtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL); +#endif + + + { + u8 ch, bw, offset; + + if (rtw_mi_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0) { + set_channel_bwmode(padapter, ch, offset, bw); + rtw_mi_update_union_chan_inf(padapter, ch, offset, bw); + } + } + + flush_all_cam_entry(padapter); + + _cancel_timer_ex(&pmlmeext->link_timer); + + /* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */ + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + +} + +void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) +{ + struct sta_info *psta, *psta_bmc; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + u8 join_type; + struct security_priv *psecuritypriv = &padapter->securitypriv; + + if (join_res < 0) { + join_type = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); + + goto exit_mlmeext_joinbss_event_callback; + } + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + /* update bc/mc sta_info */ + update_bmc_sta(padapter); + } + + /* turn on dynamic functions */ + /* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); */ + + /* update IOT-releated issue */ + update_IOT_info(padapter); + + rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates); + + /* BCN interval */ + rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval)); + + /* udpate capability */ + update_capinfo(padapter, pmlmeinfo->capability); + + /* WMM, Update EDCA param */ + WMMOnAssocRsp(padapter); + + /* HT */ + HTOnAssocRsp(padapter); + + /* VHT */ + VHTOnAssocRsp(padapter); + + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) { /* only for infra. mode */ + /* RTW_INFO("set_sta_rate\n"); */ + + psta->wireless_mode = pmlmeext->cur_wireless_mode; + + + /* set per sta rate after updating HT cap. */ + set_sta_rate(padapter, psta); + + rtw_sta_media_status_rpt(padapter, psta, 1); + + /* wakeup macid after join bss successfully to ensure + the subsequent data frames can be sent out normally */ + rtw_hal_macid_wakeup(padapter, psta->mac_id); + } + + if (is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm)) + rtw_sec_restore_wep_key(padapter); + + if (rtw_port_switch_chk(padapter) == _TRUE) + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); + + join_type = 2; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { + /* correcting TSF */ + correct_TSF(padapter, pmlmeext); + + /* set_link_timer(pmlmeext, DISCONNECT_TO); */ + } + + if (get_hw_port(padapter) == HW_PORT0) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0); + + +exit_mlmeext_joinbss_event_callback: + + rtw_join_done_chk_ch(padapter, join_res); + + RTW_INFO("=>%s - End to Connection without 4-way\n", __FUNCTION__); +} + +/* currently only adhoc mode will go here */ +void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 join_type; + + RTW_INFO("%s\n", __FUNCTION__); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { /* adhoc master or sta_count>1 */ + /* nothing to do */ + } else { /* adhoc client */ + /* update TSF Value */ + /* update_TSF(pmlmeext, pframe, len); */ + + /* correcting TSF */ + correct_TSF(padapter, pmlmeext); + + /* start beacon */ + if (send_beacon(padapter) == _FAIL) + rtw_warn_on(1); + + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + } + + join_type = 2; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + } + + /* update adhoc sta_info */ + update_sta_info(padapter, psta); + + rtw_hal_update_sta_rate_mask(padapter, psta); + + /* ToDo: HT for Ad-hoc */ + psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel); + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + + /* rate radaptive */ + Update_RA_Entry(padapter, psta); +} + +void mlmeext_sta_del_event_callback(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter)) + rtw_mlmeext_disconnect(padapter); + +} + +/**************************************************************************** + +Following are the functions for the timer handlers + +*****************************************************************************/ +void _linked_info_dump(_adapter *padapter) +{ + int i; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter); + int undecorated_smoothed_pwdb = 0; + + if (padapter->bLinkInfoDump) { + + RTW_INFO("\n============["ADPT_FMT"] linked status check ===================\n", ADPT_ARG(padapter)); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { + rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &undecorated_smoothed_pwdb); + + RTW_INFO("AP[" MAC_FMT "] - undecorated_smoothed_pwdb:%d\n", + MAC_ARG(padapter->mlmepriv.cur_network.network.MacAddress), undecorated_smoothed_pwdb); + } else if ((pmlmeinfo->state & 0x03) == _HW_STATE_AP_) { + _irqL irqL; + _list *phead, *plist; + + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + RTW_INFO("STA[" MAC_FMT "]:undecorated_smoothed_pwdb:%d\n", + MAC_ARG(psta->hwaddr), psta->rssi_stat.undecorated_smoothed_pwdb); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } + + /*============ tx info ============ */ + rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP); + + rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE); + + } + +} +/******************************************************************** + +When station does not receive any packet in MAX_CONTINUAL_NORXPACKET_COUNT*2 seconds, +recipient station will teardown the block ack by issuing DELBA frame. + +*********************************************************************/ +void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) +{ + int i = 0; + int ret = _SUCCESS; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* + IOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300). + AP is originator.AP does not transmit unicast packets when STA response its BAR. + This case probably occur ap issue BAR after AP builds BA. + + Follow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup. + The inactivity timer is not reset when MPDUs corresponding to other TIDs are received. + */ + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) { + for (i = 0; i < TID_NUM ; i++) { + if ((psta->recvreorder_ctrl[i].enable) && + (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) ) { + if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { + /* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */ + if (!from_timer) + ret = issue_del_ba_ex(padapter, psta->hwaddr, i, 39, 0, 3, 1); + else + issue_del_ba(padapter, psta->hwaddr, i, 39, 0); + psta->recvreorder_ctrl[i].enable = _FALSE; + if (ret != _FAIL) + psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID; + rtw_reset_continual_no_rx_packet(psta, i); + } + } else { + /* The inactivity timer is reset when MPDUs to the TID is received. */ + rtw_reset_continual_no_rx_packet(psta, i); + } + } + } +} + +u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) +{ + u8 ret = _FALSE; + int i = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + if ((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)) + && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) + && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta) + ) + ret = _FALSE; + else + ret = _TRUE; + + sta_update_last_rx_pkts(psta); + + /* + record last rx data packets for every tid. + */ + for (i = 0; i < TID_NUM; i++) + psta->sta_stats.last_rx_data_qos_pkts[i] = psta->sta_stats.rx_data_qos_pkts[i]; + + return ret; +} + +u8 chk_adhoc_peer_is_alive(struct sta_info *psta) +{ + u8 ret = _TRUE; + + + if (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta) + && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) + && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)) + ret = _FALSE; + + sta_update_last_rx_pkts(psta); + + return ret; +} + +/* from_timer == 1 means driver is in LPS */ +void linked_status_chk(_adapter *padapter, u8 from_timer) +{ + u32 i; + struct sta_info *psta; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct recv_priv *precvpriv = &padapter->recvpriv; + + if (padapter->registrypriv.mp_mode == _TRUE) + return; + + if (is_client_associated_to_ap(padapter)) { + /* linked infrastructure client mode */ + + int tx_chk = _SUCCESS, rx_chk = _SUCCESS; + int rx_chk_limit; + int link_count_limit; + + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ACTIVE)) { + RTW_INFO("signal_strength_data.avg_val = %d\n", precvpriv->signal_strength_data.avg_val); + if (precvpriv->signal_strength_data.avg_val < pmlmepriv->roam_rssi_threshold) { + pmlmepriv->need_to_roam = _TRUE; + rtw_drv_scan_by_self(padapter, RTW_AUTO_SCAN_REASON_ROAM); + } else { + pmlmepriv->need_to_roam = _FALSE; + } + } + +#if defined(DBG_ROAMING_TEST) + rx_chk_limit = 1; +#else + rx_chk_limit = 4; +#endif + if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) { + if (!from_timer) + link_count_limit = 3; /* 8 sec */ + else + link_count_limit = 15; /* 32 sec */ + } else + { + if (!from_timer) + link_count_limit = 7; /* 16 sec */ + else + link_count_limit = 29; /* 60 sec */ + } + + psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + if (psta != NULL) { + bool is_p2p_enable = _FALSE; + is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE); + +#ifdef CONFIG_ISSUE_DELBA_WHEN_NO_TRAFFIC + /*issue delba when ap does not tx data packet that is Broadcom ap */ + rtw_delba_check(padapter, psta, from_timer); +#endif + if (chk_ap_is_alive(padapter, psta) == _FALSE) + rx_chk = _FAIL; + + if (pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts) + tx_chk = _FAIL; + + if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL) + ) { + u8 backup_ch = 0, backup_bw, backup_offset; + u8 union_ch = 0, union_bw, union_offset; + + if (!rtw_mi_get_ch_setting_union(padapter, &union_ch, &union_bw, &union_offset) + || pmlmeext->cur_channel != union_ch) + goto bypass_active_keep_alive; + + /* switch to correct channel of current network before issue keep-alive frames */ + if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_ch = rtw_get_oper_ch(padapter); + backup_bw = rtw_get_oper_bw(padapter); + backup_offset = rtw_get_oper_choffset(padapter); + set_channel_bwmode(padapter, union_ch, union_offset, union_bw); + } + + if (rx_chk != _SUCCESS) + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->hwaddr, 0, 0, 3, 1); + + if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) { + tx_chk = issue_nulldata(padapter, psta->hwaddr, 0, 3, 1); + /* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */ + if (tx_chk == _SUCCESS && !is_p2p_enable) + rx_chk = _SUCCESS; + } + + /* back to the original operation channel */ + if (backup_ch > 0) + set_channel_bwmode(padapter, backup_ch, backup_offset, backup_bw); + +bypass_active_keep_alive: + ; + } else + { + if (rx_chk != _SUCCESS) { + if (pmlmeext->retry == 0) { + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + } + } + + if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit + ) { + tx_chk = issue_nulldata_in_interrupt(padapter, NULL, from_timer ? 1 : 0); + } + } + + if (rx_chk == _FAIL) { + pmlmeext->retry++; + if (pmlmeext->retry > rx_chk_limit) { + RTW_PRINT(FUNC_ADPT_FMT" disconnect or roaming\n", + FUNC_ADPT_ARG(padapter)); + receive_disconnect(padapter, pmlmeinfo->network.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); + return; + } + } else + pmlmeext->retry = 0; + + if (tx_chk == _FAIL) + pmlmeinfo->link_count %= (link_count_limit + 1); + else { + pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts; + pmlmeinfo->link_count = 0; + } + + } /* end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) */ + + } else if (is_client_associated_to_ibss(padapter)) { + _irqL irqL; + _list *phead, *plist, dlist; + + _rtw_init_listhead(&dlist); + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + + if (is_broadcast_mac_addr(psta->hwaddr)) + continue; + + if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to) + psta->expire_to = pstapriv->adhoc_expire_to; + else + psta->expire_to--; + + if (psta->expire_to <= 0) { + rtw_list_delete(&psta->list); + rtw_list_insert_tail(&psta->list, &dlist); + } + } + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + plist = get_next(&dlist); + while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, list); + plist = get_next(plist); + rtw_list_delete(&psta->list); + RTW_INFO(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->hwaddr)); + report_del_sta_event(padapter, psta->hwaddr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); + } + } + +} + +void survey_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + struct cmd_obj *cmd; + struct sitesurvey_parm *psurveyPara; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { + rtw_warn_on(1); + goto exit; + } + + psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm)); + if (psurveyPara == NULL) { + rtw_warn_on(1); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); + rtw_enqueue_cmd(pcmdpriv, cmd); + } + +exit: + return; +} + +void link_timer_hdl(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + /* static unsigned int rx_pkt = 0; */ + /* static u64 tx_cnt = 0; */ + /* struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); */ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + /* struct sta_priv *pstapriv = &padapter->stapriv; */ + + if (rtw_sta_linking_test_force_fail()) + RTW_INFO("rtw_sta_linking_test_force_fail\n"); + + if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) { + RTW_INFO("link_timer_hdl:no beacon while connecting\n"); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -3); + } else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) { + /* re-auth timer */ + if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) { + /* if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) */ + /* { */ + pmlmeinfo->state = 0; + report_join_res(padapter, -1); + return; + /* } */ + /* else */ + /* { */ + /* pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; */ + /* pmlmeinfo->reauth_count = 0; */ + /* } */ + } + + RTW_INFO("link_timer_hdl: auth timeout and try again\n"); + pmlmeinfo->auth_seq = 1; + issue_auth(padapter, NULL, 0); + set_link_timer(pmlmeext, REAUTH_TO); + } else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) { + /* re-assoc timer */ + if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) { + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -2); + return; + } + + { + RTW_INFO("link_timer_hdl: assoc timeout and try again\n"); + issue_assocreq(padapter); + } + + set_link_timer(pmlmeext, REASSOC_TO); + } + + return; +} + +void addba_timer_hdl(void *ctx) +{ + struct sta_info *psta = (struct sta_info *)ctx; + + struct ht_priv *phtpriv; + + if (!psta) + return; + + phtpriv = &psta->htpriv; + + if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) { + if (phtpriv->candidate_tid_bitmap) + phtpriv->candidate_tid_bitmap = 0x0; + + } +} + + + +u8 NULL_hdl(_adapter *padapter, u8 *pbuf) +{ + return H2C_SUCCESS; +} + + +u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) +{ + u8 type; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; + + if (psetop->mode == Ndis802_11APMode) { + pmlmeinfo->state = WIFI_FW_AP_STATE; + type = _HW_STATE_AP_; + /* start_ap_mode(padapter); */ + } else if (psetop->mode == Ndis802_11Infrastructure) { + pmlmeinfo->state &= ~(BIT(0) | BIT(1)); /* clear state */ + pmlmeinfo->state |= WIFI_FW_STATION_STATE;/* set to STATION_STATE */ + type = _HW_STATE_STATION_; + } else if (psetop->mode == Ndis802_11IBSS) + type = _HW_STATE_ADHOC_; + else if (psetop->mode == Ndis802_11Monitor) + type = _HW_STATE_MONITOR_; + else + type = _HW_STATE_NOLINK_; + + + rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); + + + if (rtw_port_switch_chk(padapter) == _TRUE) { + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); + + if (psetop->mode == Ndis802_11APMode) + adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; /* ap mode won't dowload rsvd pages */ + else if (psetop->mode == Ndis802_11Infrastructure) { + _adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter)); + if (port0_iface) + rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, 0); + } + } + + if (psetop->mode == Ndis802_11APMode || + psetop->mode == Ndis802_11Monitor) { + /* Do this after port switch to */ + /* prevent from downloading rsvd page to wrong port */ + rtw_btcoex_MediaStatusNotify(padapter, 1); /* connect */ + } + + return H2C_SUCCESS; + +} + +u8 createbss_hdl(_adapter *padapter, u8 *pbuf) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; + struct createbss_parm *parm = (struct createbss_parm *)pbuf; + u8 ret = H2C_SUCCESS; + /* u8 initialgain; */ + + if (pmlmeinfo->state == WIFI_FW_AP_STATE) { + start_bss_network(padapter, parm); + goto exit; + } + + /* below is for ad-hoc master */ + if (parm->adhoc) { + rtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS); + rtw_joinbss_reset(padapter); + + pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pmlmeinfo->ERP_enable = 0; + pmlmeinfo->WMM_enable = 0; + pmlmeinfo->HT_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->agg_enable_bitmap = 0; + pmlmeinfo->candidate_tid_bitmap = 0; + + /* config the initial gain under linking, need to write the BB registers */ + /* initialgain = 0x1E; */ + /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ + + /* disable dynamic functions, such as high power, DIG */ + rtw_phydm_ability_backup(padapter); + rtw_phydm_func_disable_all(padapter); + + /* cancel link timer */ + _cancel_timer_ex(&pmlmeext->link_timer); + + /* clear CAM */ + flush_all_cam_entry(padapter); + + pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network); + _rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); + pnetwork->IELength = pdev_network->IELength; + + if (pnetwork->IELength > MAX_IE_SZ) { + ret = H2C_PARAMETERS_ERROR; + goto ibss_post_hdl; + } + + _rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength); + start_create_ibss(padapter); + } else { + rtw_warn_on(1); + ret = H2C_PARAMETERS_ERROR; + } + +ibss_post_hdl: + rtw_create_ibss_post_hdl(padapter, ret); + +exit: + return ret; +} + +u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) +{ + u8 join_type; + PNDIS_802_11_VARIABLE_IEs pIE; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u32 i; + /* u8 initialgain; */ + /* u32 acparm; */ + u8 u_ch, u_bw, u_offset; + u8 doiqk = _FALSE; + + /* check already connecting to AP or not */ + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { + if (pmlmeinfo->state & WIFI_FW_STATION_STATE) + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + + /* clear CAM */ + flush_all_cam_entry(padapter); + + _cancel_timer_ex(&pmlmeext->link_timer); + + /* set MSR to nolink->infra. mode */ + /* Set_MSR(padapter, _HW_STATE_NOLINK_); */ + Set_MSR(padapter, _HW_STATE_STATION_); + + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); + } + + + rtw_joinbss_reset(padapter); + + pmlmeinfo->ERP_enable = 0; + pmlmeinfo->WMM_enable = 0; + pmlmeinfo->HT_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->agg_enable_bitmap = 0; + pmlmeinfo->candidate_tid_bitmap = 0; + pmlmeinfo->bwmode_updated = _FALSE; + /* pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; */ + pmlmeinfo->VHT_enable = 0; + + _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); + pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; + + if (pnetwork->IELength > MAX_IE_SZ) /* Check pbuf->IELength */ + return H2C_PARAMETERS_ERROR; + + if (pnetwork->IELength < 2) { + report_join_res(padapter, (-4)); + return H2C_SUCCESS; + } + _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); + + pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); + + /* Check AP vendor to move rtw_joinbss_cmd() */ + /* pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); */ + + /* sizeof(NDIS_802_11_FIXED_IEs) */ + for (i = _FIXED_IE_LENGTH_ ; i < pnetwork->IELength - 2 ;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: /* Get WMM IE. */ + if (_rtw_memcmp(pIE->data, WMM_OUI, 4)) + WMM_param_handler(padapter, pIE); + break; + + case _HT_CAPABILITY_IE_: /* Get HT Cap IE. */ + pmlmeinfo->HT_caps_enable = 1; + break; + + case _HT_EXTRA_INFO_IE_: /* Get HT Info IE. */ + pmlmeinfo->HT_info_enable = 1; + break; + + case EID_VHTCapability: /* Get VHT Cap IE. */ + pmlmeinfo->VHT_enable = 1; + break; + + case EID_VHTOperation: /* Get VHT Operation IE. */ + break; + default: + break; + } + + i += (pIE->Length + 2); + } + + rtw_bss_get_chbw(pnetwork + , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); + + rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); + + /* check channel, bandwidth, offset and switch */ + if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) { + report_join_res(padapter, (-4)); + return H2C_SUCCESS; + } + + /* disable dynamic functions, such as high power, DIG */ + /*rtw_phydm_func_disable_all(padapter);*/ + + /* config the initial gain under linking, need to write the BB registers */ + /* initialgain = 0x1E; */ + /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); + join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + set_channel_bwmode(padapter, u_ch, u_offset, u_bw); + rtw_mi_update_union_chan_inf(padapter, u_ch, u_offset, u_bw); + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + /* cancel link timer */ + _cancel_timer_ex(&pmlmeext->link_timer); + + start_clnt_join(padapter); + + return H2C_SUCCESS; + +} + +u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct disconnect_parm *param = (struct disconnect_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + u8 val8; + + if (is_client_associated_to_ap(padapter)) { + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms / 100, 100); + } + + + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { + /* Stop BCN */ + val8 = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8)); + } + + rtw_mlmeext_disconnect(padapter); + + rtw_free_uc_swdec_pending_queue(padapter); + + rtw_sta_mstatus_report(padapter); + + return H2C_SUCCESS; +} + +static const char *const _scan_state_str[] = { + "SCAN_DISABLE", + "SCAN_START", + "SCAN_PS_ANNC_WAIT", + "SCAN_ENTER", + "SCAN_PROCESS", + "SCAN_BACKING_OP", + "SCAN_BACK_OP", + "SCAN_LEAVING_OP", + "SCAN_LEAVE_OP", + "SCAN_SW_ANTDIV_BL", + "SCAN_TO_P2P_LISTEN", + "SCAN_P2P_LISTEN", + "SCAN_COMPLETE", + "SCAN_STATE_MAX", +}; + +const char *scan_state_str(u8 state) +{ + state = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state; + return _scan_state_str[state]; +} + +static bool scan_abort_hdl(_adapter *adapter) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct ss_res *ss = &pmlmeext->sitesurvey_res; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + bool ret = _FALSE; + + if (pmlmeext->scan_abort == _TRUE) { + if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX); + ss->channel_idx = 3; + RTW_INFO("%s idx:%d, cnt:%u\n", __FUNCTION__ + , ss->channel_idx + , pwdinfo->find_phase_state_exchange_cnt + ); + } else + { + ss->channel_idx = ss->ch_num; + RTW_INFO("%s idx:%d\n", __FUNCTION__ + , ss->channel_idx + ); + } + pmlmeext->scan_abort = _FALSE; + ret = _TRUE; + } + + return ret; +} + +u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num) +{ + /* interval larger than this is treated as backgroud scan */ +#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS +#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000 +#endif + +#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST +#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1 +#endif +#ifndef RTW_SCAN_SPARSE_CH_NUM_BG +#define RTW_SCAN_SPARSE_CH_NUM_BG 4 +#endif +#ifndef RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE +#define RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE 1 +#endif + +#define SCAN_SPARSE_CH_NUM_INVALID 255 + + static u8 token = 255; + u32 interval; + bool busy_traffic = _FALSE; + bool miracast_enabled = _FALSE; + bool bg_scan = _FALSE; + u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID; + u8 scan_division_num; + u8 ret_num = ch_num; + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + if (regsty->wifi_spec) + goto exit; + + /* assume ch_num > 6 is normal scan */ + if (ch_num <= 6) + goto exit; + + if (mlmeext->last_scan_time == 0) + mlmeext->last_scan_time = rtw_get_current_time(); + + interval = rtw_get_passing_time_ms(mlmeext->last_scan_time); + + if (rtw_mi_busy_traffic_check(adapter, _FALSE)) + busy_traffic = _TRUE; + + if (rtw_mi_check_miracast_enabled(adapter)) + miracast_enabled = _TRUE; + + if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS) + bg_scan = _TRUE; + + /* max_allow_ch by conditions*/ + +#if RTW_SCAN_SPARSE_MIRACAST + if (miracast_enabled == _TRUE && busy_traffic == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST); +#endif + +#if RTW_SCAN_SPARSE_BG + if (bg_scan == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG); +#endif + +#if defined(RTW_SCAN_SPARSE_ROAMING_ACTIVE) + if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { + if (busy_traffic == _TRUE && adapter->mlmepriv.need_to_roam == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_ROAMING_ACTIVE); + } +#endif + + if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) { + int i; + int k = 0; + + scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch) ? 1 : 0); + token = (token + 1) % scan_division_num; + + if (0) + RTW_INFO("scan_division_num:%u, token:%u\n", scan_division_num, token); + + for (i = 0; i < ch_num; i++) { + if (ch[i].hw_value && (i % scan_division_num) == token + ) { + if (i != k) + _rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel)); + k++; + } + } + + _rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel)); + + ret_num = k; + mlmeext->last_scan_time = rtw_get_current_time(); + } + +exit: + return ret_num; +} + +static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out, + u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num) +{ + int i, j; + int scan_ch_num = 0; + int set_idx; + u8 chan; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + /* clear first */ + _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel) * out_num); + + /* acquire channels from in */ + j = 0; + for (i = 0; i < in_num; i++) { + + if (0) + RTW_INFO(FUNC_ADPT_FMT" "CHAN_FMT"\n", FUNC_ADPT_ARG(padapter), CHAN_ARG(&in[i])); + + if (!in[i].hw_value || (in[i].flags & RTW_IEEE80211_CHAN_DISABLED)) + continue; + if (rtw_mlme_band_check(padapter, in[i].hw_value) == _FALSE) + continue; + + set_idx = rtw_chset_search_ch(pmlmeext->channel_set, in[i].hw_value); + if (set_idx >= 0) { + if (j >= out_num) { + RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", + FUNC_ADPT_ARG(padapter), out_num); + break; + } + + _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel)); + + if (pmlmeext->channel_set[set_idx].ScanType == SCAN_PASSIVE) + out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; + + j++; + } + if (j >= out_num) + break; + } + + /* if out is empty, use channel_set as default */ + if (j == 0) { + for (i = 0; i < pmlmeext->max_chan_nums; i++) { + chan = pmlmeext->channel_set[i].ChannelNum; + if (rtw_mlme_band_check(padapter, chan) == _TRUE) { + if (rtw_mlme_ignore_chan(padapter, chan) == _TRUE) + continue; + + if (0) + RTW_INFO(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), chan); + + if (j >= out_num) { + RTW_PRINT(FUNC_ADPT_FMT" out_num:%u not enough\n", + FUNC_ADPT_ARG(padapter), out_num); + break; + } + + out[j].hw_value = chan; + + if (pmlmeext->channel_set[i].ScanType == SCAN_PASSIVE) + out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; + + j++; + } + } + } + + /* scan_sparse */ + j = rtw_scan_sparse(padapter, out, j); + + return j; +} + +static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm) +{ + struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; + int i; + + ss->bss_cnt = 0; + ss->channel_idx = 0; + ss->igi_scan = 0; + ss->igi_before_scan = 0; + + ss->ssid_num = 0; + for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { + if (parm->ssid[i].SsidLength) { + _rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE); + ss->ssid[i].SsidLength = parm->ssid[i].SsidLength; + ss->ssid_num++; + } else + ss->ssid[i].SsidLength = 0; + } + + ss->ch_num = rtw_scan_ch_decision(adapter + , ss->ch, RTW_CHANNEL_SCAN_AMOUNT + , parm->ch, parm->ch_num + ); + + + ss->scan_mode = parm->scan_mode; +} + +static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type) +{ + u8 next_state; + u8 scan_ch = 0; + RT_SCAN_TYPE scan_type = SCAN_PASSIVE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct ss_res *ss = &pmlmeext->sitesurvey_res; + + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + /* handle scan abort request */ + scan_abort_hdl(padapter); + + if (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) { + if (pwdinfo->rx_invitereq_info.scan_op_ch_only) + scan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx]; + else + scan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx]; + scan_type = SCAN_ACTIVE; + } else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) { + /* + * Commented by Albert 2011/06/03 + * The driver is in the find phase, it should go through the social channel. + */ + int ch_set_idx; + + scan_ch = pwdinfo->social_chan[ss->channel_idx]; + ch_set_idx = rtw_chset_search_ch(pmlmeext->channel_set, scan_ch); + if (ch_set_idx >= 0) + scan_type = pmlmeext->channel_set[ch_set_idx].ScanType; + else + scan_type = SCAN_ACTIVE; + } else + { + struct rtw_ieee80211_channel *ch; + + + if (ss->channel_idx < ss->ch_num) { + ch = &ss->ch[ss->channel_idx]; + scan_ch = ch->hw_value; + scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; + } + } + + if (scan_ch != 0) { + next_state = SCAN_PROCESS; + } else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) { + /* go p2p listen */ + next_state = SCAN_TO_P2P_LISTEN; + + } else { + next_state = SCAN_COMPLETE; + + } + + + + if (ch) + *ch = scan_ch; + if (type) + *type = scan_type; + + return next_state; +} + +void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct ss_res *ss = &pmlmeext->sitesurvey_res; + u8 ssid_scan = 0; + + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (survey_channel != 0) { + set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + + + if (ScanType == SCAN_ACTIVE) { + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) + { + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + } else + { + if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) { + /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, NULL, NULL); + else + issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0); + issue_probereq(padapter, NULL, NULL); + } + + ssid_scan = 1; + } + } + + if (ssid_scan) { + int i; + + for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { + if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) { + /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + else + issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0); + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + } + } + } + } else { + /* channel number is 0 or this channel is not valid. */ + rtw_warn_on(1); + } + + return; +} + +void survey_done_set_ch_bw(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 cur_channel = 0; + u8 cur_bwmode; + u8 cur_ch_offset; + + if (rtw_mi_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) { + if (0) + RTW_INFO(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); + } else { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + _adapter *iface; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + + if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) { + cur_channel = iface->wdinfo.listen_channel; + cur_bwmode = CHANNEL_WIDTH_20; + cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + if (0) + RTW_INFO(FUNC_ADPT_FMT" back to "ADPT_FMT"'s listen ch - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset); + break; + } + } + + if (cur_channel == 0) { + cur_channel = pmlmeext->cur_channel; + cur_bwmode = pmlmeext->cur_bwmode; + cur_ch_offset = pmlmeext->cur_ch_offset; + if (0) + RTW_INFO(FUNC_ADPT_FMT" back to ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); + } + } + set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); +} + +/** + * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj + * @padapter + * @ps: power saving or not + * + * Returns: 0: no ps announcement is doing. 1: ps announcement is doing + */ + +u8 sitesurvey_ps_annc(_adapter *padapter, bool ps) +{ + u8 ps_anc = 0; + + if (rtw_mi_issue_nulldata(padapter, NULL, ps, 3, 500)) + ps_anc = 1; + return ps_anc; +} + +void sitesurvey_set_igi(_adapter *adapter) +{ + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; + u8 igi; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + switch (mlmeext_scan_state(mlmeext)) { + case SCAN_ENTER: + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + igi = 0x28; + else + igi = 0x1e; + + /* record IGI status */ + ss->igi_scan = igi; + rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL); + + /* disable DIG and set IGI for scan */ + rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); + break; + case SCAN_COMPLETE: + case SCAN_TO_P2P_LISTEN: + /* enable DIG and restore IGI */ + igi = 0xff; + rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); + break; + default: + rtw_warn_on(1); + break; + } +} +void sitesurvey_set_msr(_adapter *adapter, bool enter) +{ + u8 network_type; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (enter) { + /* set MSR to no link state */ + network_type = _HW_STATE_NOLINK_; + } else { + network_type = pmlmeinfo->state & 0x3; + } + Set_MSR(adapter, network_type); +} +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) +{ + struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct ss_res *ss = &pmlmeext->sitesurvey_res; + u8 val8; + + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + + /* increase channel idx */ + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) + ss->channel_idx++; + + /* update scan state to next state (assigned by previous cmd hdl) */ + if (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext)) + mlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext)); + +operation_by_state: + switch (mlmeext_scan_state(pmlmeext)) { + + case SCAN_DISABLE: + /* + * SW parameter initialization + */ + + sitesurvey_res_reset(padapter, pparm); + mlmeext_set_scan_state(pmlmeext, SCAN_START); + goto operation_by_state; + + case SCAN_START: + /* + * prepare to leave operating channel + */ + + /* apply rx ampdu setting */ + if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID + || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID) + rtw_rx_ampdu_apply(padapter); + + /* clear HW TX queue before scan */ + rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + + /* power save state announcement */ + if (sitesurvey_ps_annc(padapter, 1)) { + mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); + mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER); + set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ + } else { + mlmeext_set_scan_state(pmlmeext, SCAN_ENTER); + goto operation_by_state; + } + + break; + + case SCAN_ENTER: + /* + * HW register and DM setting for enter scan + */ + + rtw_phydm_ability_backup(padapter); + + sitesurvey_set_igi(padapter); + + /* config dynamic functions for off channel */ + rtw_phydm_func_for_offchannel(padapter); + /* set MSR to no link state */ + sitesurvey_set_msr(padapter, _TRUE); + + val8 = 1; /* under site survey */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + goto operation_by_state; + + case SCAN_PROCESS: { + u8 scan_ch; + RT_SCAN_TYPE scan_type; + u8 next_state; + u32 scan_ms; + + + next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type); + if (next_state != SCAN_PROCESS) { + + mlmeext_set_scan_state(pmlmeext, next_state); + goto operation_by_state; + } + + /* still SCAN_PROCESS state */ + if (0) + RTW_INFO(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , scan_ch + , pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + , scan_type ? 'A' : 'P', ss->scan_mode ? 'A' : 'P' + , ss->ssid[0].SsidLength ? 'S' : ' ' + ); + + + site_survey(padapter, scan_ch, scan_type); + + scan_ms = ss->scan_ch_ms; + + + + set_survey_timer(pmlmeext, scan_ms); + break; + } + + + + case SCAN_TO_P2P_LISTEN: + /* + * Set the P2P State to the listen state of find phase + * and set the current channel to the listen channel + */ + set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN); + + /* turn on phy-dynamic functions */ + rtw_phydm_ability_restore(padapter); + + sitesurvey_set_igi(padapter); + + mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN); + _set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100)); + break; + + case SCAN_P2P_LISTEN: + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + ss->channel_idx = 0; + goto operation_by_state; + + case SCAN_COMPLETE: + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) + ) { + + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + } + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); + + /* switch channel */ + survey_done_set_ch_bw(padapter); + + sitesurvey_set_msr(padapter, _FALSE); + + val8 = 0; /* survey done */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + /* turn on phy-dynamic functions */ + rtw_phydm_ability_restore(padapter); + + sitesurvey_set_igi(padapter); + + sitesurvey_ps_annc(padapter, 0); + + /* apply rx ampdu setting */ + rtw_rx_ampdu_apply(padapter); + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + + report_surveydone_event(padapter); + + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + } + + return H2C_SUCCESS; +} + +u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct setauth_parm *pparm = (struct setauth_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pparm->mode < 4) + pmlmeinfo->auth_algo = pparm->mode; + + return H2C_SUCCESS; +} + +/* +SEC CAM Entry format (32 bytes) +DW0 - MAC_ADDR[15:0] | Valid[15] | MFB[14:8] | RSVD[7] | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] +DW0 - MAC_ADDR[15:0] | Valid[15] |RSVD[14:9] | RPT_MODE[8] | SPP_MODE[7] | GK[6] | MIC_KEY[5] | SEC_TYPE[4:2] | KID[1:0] (92E/8812A/8814A) +DW1 - MAC_ADDR[47:16] +DW2 - KEY[31:0] +DW3 - KEY[63:32] +DW4 - KEY[95:64] +DW5 - KEY[127:96] +DW6 - RSVD +DW7 - RSVD +*/ + +/*Set WEP key or Group Key*/ +u8 setkey_hdl(_adapter *padapter, u8 *pbuf) +{ + u16 ctrl = 0; + s16 cam_id = 0; + struct setkey_parm *pparm = (struct setkey_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + unsigned char null_addr[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + u8 *addr; + bool used = _FALSE; + + /* main tx key for wep. */ + if (pparm->set_tx) + pmlmeinfo->key_index = pparm->keyid; + + cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, &used); + + if (cam_id < 0) + goto enable_mc; + + if (cam_id >= 0 && cam_id <= 3) + addr = null_addr; + else + { + if (((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) + /* for AP mode ,we will force sec cam entry_id so hw dont search cam when tx*/ + addr = adapter_mac_addr(padapter); + else + /* not default key, searched by A2 */ + addr = get_bssid(&padapter->mlmepriv); + } + + /* cam entry searched is pairwise key */ + if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _FALSE) { + s16 camid_clr; + + RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u the same key id as pairwise key\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(addr), pparm->keyid); + + /* HW has problem to distinguish this group key with existing pairwise key, stop HW enc and dec for BMC */ + rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH); + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); + + /* clear group key */ + while ((camid_clr = rtw_camid_search(padapter, addr, -1, 1)) >= 0) { + RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), camid_clr); + clear_cam_entry(padapter, camid_clr); + rtw_camid_free(padapter, camid_clr); + } + + goto enable_mc; + } + + ctrl = BIT(15) | BIT(6) | ((pparm->algorithm) << 2) | pparm->keyid; + + RTW_PRINT("set group key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n" + , cam_id, MAC_ARG(addr), pparm->keyid, security_type_str(pparm->algorithm)); + + write_cam(padapter, cam_id, ctrl, addr, pparm->key); + + /* if ((cam_id > 3) && (((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)))*/ + + if (cam_id >= 0 && cam_id <= 3) + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_TRUE); + + /* 8814au should set both broadcast and unicast CAM entry for WEP key in STA mode */ + if (is_wep_enc(pparm->algorithm) && check_mlmeinfo_state(pmlmeext, WIFI_FW_STATION_STATE) && + _rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC)) { + struct set_stakey_parm sta_pparm; + + sta_pparm.algorithm = pparm->algorithm; + sta_pparm.keyid = pparm->keyid; + _rtw_memcpy(sta_pparm.key, pparm->key, 16); + _rtw_memcpy(sta_pparm.addr, get_bssid(&padapter->mlmepriv), ETH_ALEN); + set_stakey_hdl(padapter, (u8 *)&sta_pparm); + } + +enable_mc: + /* allow multicast packets to driver */ + rtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr); + + return H2C_SUCCESS; +} + +void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta) +{ + struct security_priv *psecuritypriv = &(adapter->securitypriv); + struct set_stakey_parm sta_pparm; + sint keyid; + + if (!is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm)) + return; + + for (keyid = 0; keyid < 4; keyid++) { + if ((psecuritypriv->key_mask & BIT(keyid)) && (keyid == psecuritypriv->dot11PrivacyKeyIndex)) { + sta_pparm.algorithm = psecuritypriv->dot11PrivacyAlgrthm; + sta_pparm.keyid = keyid; + _rtw_memcpy(sta_pparm.key, &(psecuritypriv->dot11DefKey[keyid].skey[0]), 16); + _rtw_memcpy(sta_pparm.addr, psta->hwaddr, ETH_ALEN); + + RTW_PRINT(FUNC_ADPT_FMT"set WEP - PK with "MAC_FMT" keyid:%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(psta->hwaddr), keyid); + + set_stakey_hdl(adapter, (u8 *)&sta_pparm); + } + } +} + +u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) +{ + u16 ctrl = 0; + s16 cam_id = 0; + bool used; + u8 kid = 0; + u8 ret = H2C_SUCCESS; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct set_stakey_parm *pparm = (struct set_stakey_parm *)pbuf; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + + if (pparm->algorithm == _NO_PRIVACY_) + goto write_to_cam; + + psta = rtw_get_stainfo(pstapriv, pparm->addr); + if (!psta) { + RTW_PRINT("%s sta:"MAC_FMT" not found\n", __func__, MAC_ARG(pparm->addr)); + ret = H2C_REJECTED; + goto exit; + } + + pmlmeinfo->enc_algo = pparm->algorithm; + if (is_wep_enc(pparm->algorithm)) + kid = pparm->keyid; + cam_id = rtw_camid_alloc(padapter, psta, kid, &used); + if (cam_id < 0) + goto exit; + + /* cam entry searched is group key */ + if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) { + s16 camid_clr; + + RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pparm->addr), pparm->keyid); + + /* HW has problem to distinguish this pairwise key with existing group key, stop HW enc and dec for BMC */ + rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH); + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); + + /* clear group key */ + while ((camid_clr = rtw_camid_search(padapter, pparm->addr, -1, 1)) >= 0) { + RTW_PRINT("clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), camid_clr); + clear_cam_entry(padapter, camid_clr); + rtw_camid_free(padapter, camid_clr); + } + } + +write_to_cam: + if (pparm->algorithm == _NO_PRIVACY_) { + while ((cam_id = rtw_camid_search(padapter, pparm->addr, -1, -1)) >= 0) { + RTW_PRINT("clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), cam_id); + clear_cam_entry(padapter, cam_id); + rtw_camid_free(padapter, cam_id); + } + } else { + RTW_PRINT("set pairwise key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n", + cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm)); + ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; + write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); + } + ret = H2C_SUCCESS_RSP; + +exit: + return ret; +} + +u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr); + + if (!psta) + return H2C_SUCCESS; + + if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) || + ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) { + /* pmlmeinfo->ADDBA_retry_count = 0; */ + /* pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); */ + /* psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); */ + issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); + _set_timer(&psta->addba_retry_timer, ADDBA_TO); + } + else + psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); + return H2C_SUCCESS; +} + +u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf; + u8 ret = _TRUE, i = 0, try_cnt = 3, wait_ms = 50; + struct recv_reorder_ctrl *preorder_ctrl; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + + psta = rtw_get_stainfo(pstapriv, pparm->addr); + if (!psta) + goto exit; + + preorder_ctrl = &psta->recvreorder_ctrl[pparm->tid]; + ret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, pparm->status, pparm->size, 3, 50); + +#ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ + /* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */ + if (pparm->status == 0) { + preorder_ctrl->indicate_seq = pparm->start_seq; + } +#else + preorder_ctrl->indicate_seq = 0xffff; +#endif + + /* + * status = 0 means accept this addba req + * status = 37 means reject this addba req + */ + if (pparm->status == 0) { + preorder_ctrl->enable = _TRUE; + preorder_ctrl->ampdu_size = pparm->size; + } else if (pparm->status == 37) + preorder_ctrl->enable = _FALSE; + +exit: + return H2C_SUCCESS; +} + +u8 chk_bmc_sleepq_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_parm_rsp(ph2c, GEN_CMD_CODE(_ChkBMCSleepq)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; +} + +u8 set_tx_beacon_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct Tx_Beacon_param *ptxBeacon_parm; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 res = _SUCCESS; + int len_diff = 0; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param)); + if (ptxBeacon_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + _rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); + + len_diff = update_hidden_ssid( + ptxBeacon_parm->network.IEs + _BEACON_IE_OFFSET_ + , ptxBeacon_parm->network.IELength - _BEACON_IE_OFFSET_ + , pmlmeinfo->hidden_ssid_mode + ); + ptxBeacon_parm->network.IELength += len_diff; + + init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, GEN_CMD_CODE(_TX_Beacon)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; +} + +u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) +{ + u8 evt_code, evt_seq; + u16 evt_sz; + uint *peventbuf; + void (*event_callback)(_adapter *dev, u8 *pbuf); + struct evt_priv *pevt_priv = &(padapter->evtpriv); + + if (pbuf == NULL) + goto _abort_event_; + + peventbuf = (uint *)pbuf; + evt_sz = (u16)(*peventbuf & 0xffff); + evt_seq = (u8)((*peventbuf >> 24) & 0x7f); + evt_code = (u8)((*peventbuf >> 16) & 0xff); + +#ifdef CHECK_EVENT_SEQ + /* checking event sequence... */ + if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f)) { + + pevt_priv->event_seq = (evt_seq + 1) & 0x7f; + + goto _abort_event_; + } +#endif + + /* checking if event code is valid */ + if (evt_code >= MAX_C2HEVT) { + goto _abort_event_; + } + + /* checking if event size match the event parm size */ + if ((wlanevents[evt_code].parmsize != 0) && + (wlanevents[evt_code].parmsize != evt_sz)) { + + goto _abort_event_; + + } + + ATOMIC_INC(&pevt_priv->event_seq); + + peventbuf += 2; + + if (peventbuf) { + event_callback = wlanevents[evt_code].event_callback; + event_callback(padapter, (u8 *)peventbuf); + + pevt_priv->evt_done_cnt++; + } + +_abort_event_: + + return H2C_SUCCESS; + +} + +u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf) +{ + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + return H2C_SUCCESS; +} + +u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf) +{ + _irqL irqL; + struct sta_info *psta_bmc; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + + /* for BC/MC Frames */ + psta_bmc = rtw_get_bcmc_stainfo(padapter); + if (!psta_bmc) + return H2C_SUCCESS; + + if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) { + /* _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */ + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta_bmc->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + psta_bmc->sleepq_len--; + if (psta_bmc->sleepq_len > 0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + pxmitframe->attrib.triggered = 1; + + if (xmitframe_hiq_filter(pxmitframe) == _TRUE) + pxmitframe->attrib.qsel = QSLT_HIGH;/* HIQ */ + + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + } + + /* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */ + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + if (rtw_get_intf_type(padapter) != RTW_PCIE) { + /* check hi queue and bmc_sleepq */ + rtw_chk_hi_queue_cmd(padapter); + } + } + + return H2C_SUCCESS; +} + +u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) +{ + + + if (send_beacon(padapter) == _FAIL) { + RTW_INFO("issue_beacon, fail!\n"); + return H2C_PARAMETERS_ERROR; + } + + /* tx bc/mc frames after update TIM */ + chk_bmc_sleepq_hdl(padapter, NULL); + + return H2C_SUCCESS; +} + +/* +* according to channel +* add/remove WLAN_BSSID_EX.IEs's ERP ie +* set WLAN_BSSID_EX.SupportedRates +* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie +*/ +void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch) +{ + u8 network_type, rate_len, total_rate_len, remainder_rate_len; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 erpinfo = 0x4; + + if (ch >= 36) { + network_type = WIRELESS_11A; + total_rate_len = IEEE80211_NUM_OFDM_RATESLEN; + rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_); + } else { + network_type = WIRELESS_11BG; + total_rate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; + rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1); + } + + rtw_set_supported_rate(pnetwork->SupportedRates, network_type); + + UpdateBrateTbl(padapter, pnetwork->SupportedRates); + + if (total_rate_len > 8) { + rate_len = 8; + remainder_rate_len = total_rate_len - 8; + } else { + rate_len = total_rate_len; + remainder_rate_len = 0; + } + + rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len); + + if (remainder_rate_len) + rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates + 8), remainder_rate_len); + else + rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_); + + pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork); +} + +void rtw_join_done_chk_ch(_adapter *adapter, int join_res) +{ +#define DUMP_ADAPTERS_STATUS 0 + + struct dvobj_priv *dvobj; + _adapter *iface; + struct mlme_priv *mlme; + struct mlme_ext_priv *mlmeext; + u8 u_ch, u_offset, u_bw; + int i; + + dvobj = adapter_to_dvobj(adapter); + + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); + } + + if (join_res >= 0) { + + if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset) <= 0) { + dump_adapters_status(RTW_DBGDUMP , dvobj); + rtw_warn_on(1); + } + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; + + if (!iface || iface == adapter) + continue; + + if (check_fwstate(mlme, WIFI_AP_STATE) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + + if (is_grouped == _FALSE) { + /* handle AP which need to switch ch setting */ + + /* restore original bw, adjust bw by registry setting on target ch */ + mlmeext->cur_bwmode = mlme->ori_bw; + mlmeext->cur_channel = u_ch; + rtw_adjust_chbw(iface + , mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); + + rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset + , &u_ch, &u_bw, &u_offset); + + rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network) + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + + _rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX)); + + rtw_start_bss_hdl_after_chbw_decided(iface); + } + + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + update_beacon(iface, 0, NULL, _TRUE); + } + } + + } else { + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; + + if (!iface || iface == adapter) + continue; + + if (check_fwstate(mlme, WIFI_AP_STATE) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + update_beacon(iface, 0, NULL, _TRUE); + } + } + } + + if (rtw_mi_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) { + set_channel_bwmode(adapter, u_ch, u_offset, u_bw); + rtw_mi_update_union_chan_inf(adapter, u_ch, u_offset, u_bw); + } + + if (DUMP_ADAPTERS_STATUS) { + RTW_INFO(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); + } +} + +int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ + bool chbw_allow = _TRUE; + bool connect_allow = _TRUE; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 cur_ch, cur_bw, cur_ch_offset; + u8 u_ch, u_offset, u_bw; + + u_ch = cur_ch = pmlmeext->cur_channel; + u_bw = cur_bw = pmlmeext->cur_bwmode; + u_offset = cur_ch_offset = pmlmeext->cur_ch_offset; + + if (!ch || !bw || !offset) { + connect_allow = _FALSE; + rtw_warn_on(1); + goto exit; + } + + if (cur_ch == 0) { + connect_allow = _FALSE; + RTW_ERR(FUNC_ADPT_FMT" cur_ch:%u\n" + , FUNC_ADPT_ARG(adapter), cur_ch); + rtw_warn_on(1); + goto exit; + } + RTW_INFO(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + + +exit: + + if (connect_allow == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + *ch = u_ch; + *bw = u_bw; + *offset = u_offset; + } + + return connect_allow == _TRUE ? _SUCCESS : _FAIL; +} + +u8 set_ch_hdl(_adapter *padapter, u8 *pbuf) +{ + struct set_ch_parm *set_ch_parm; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + set_ch_parm = (struct set_ch_parm *)pbuf; + + RTW_INFO(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), + set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset); + + pmlmeext->cur_channel = set_ch_parm->ch; + pmlmeext->cur_ch_offset = set_ch_parm->ch_offset; + pmlmeext->cur_bwmode = set_ch_parm->bw; + + set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw); + + return H2C_SUCCESS; +} + +u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct SetChannelPlan_param *setChannelPlan_param; + struct mlme_priv *mlme = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + setChannelPlan_param = (struct SetChannelPlan_param *)pbuf; + + if (!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan)) + return H2C_PARAMETERS_ERROR; + + mlme->country_ent = setChannelPlan_param->country_ent; + mlme->ChannelPlan = setChannelPlan_param->channel_plan; + + pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set); + init_channel_list(padapter, pmlmeext->channel_set, &pmlmeext->channel_list); + + rtw_hal_set_odm_var(padapter, HAL_ODM_REGULATION, NULL, _TRUE); + + + return H2C_SUCCESS; +} + +u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct LedBlink_param *ledBlink_param; + + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + ledBlink_param = (struct LedBlink_param *)pbuf; + + + return H2C_SUCCESS; +} + +u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf) +{ + return H2C_REJECTED; + +} + +u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) +{ + return H2C_REJECTED; + +} + +u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf) +{ + struct RunInThread_param *p; + + if (NULL == pbuf) + return H2C_PARAMETERS_ERROR; + p = (struct RunInThread_param *)pbuf; + + if (p->func) + p->func(p->context); + + return H2C_SUCCESS; +} + +u8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf) +{ + + struct readMAC_parm *preadmacparm = NULL; + u8 sz = 0; + u32 addr = 0; + u32 value = 0; + + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + preadmacparm = (struct readMAC_parm *) pbuf; + sz = preadmacparm->len; + addr = preadmacparm->addr; + value = 0; + + switch (sz) { + case 1: + value = rtw_read8(padapter, addr); + break; + case 2: + value = rtw_read16(padapter, addr); + break; + case 4: + value = rtw_read32(padapter, addr); + break; + default: + RTW_INFO("%s: Unknown size\n", __func__); + break; + } + RTW_INFO("%s: addr:0x%02x valeu:0x%02x\n", __func__, addr, value); + + return H2C_SUCCESS; +} diff --git a/drivers/staging/rtl8821ce/core/rtw_mp.c b/drivers/staging/rtl8821ce/core/rtw_mp.c new file mode 100644 index 000000000000..f1926f1243da --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_mp.c @@ -0,0 +1,1616 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MP_C_ +#include <drv_types.h> + +#include "../hal/phydm/phydm_precomp.h" + +u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask) +{ + return rtw_hal_read_bbreg(padapter, addr, bitmask); +} + +void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val) +{ + rtw_hal_write_bbreg(padapter, addr, bitmask, val); +} + +u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask) +{ + return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask); +} + +void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val) +{ + rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val); +} + +u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr) +{ + return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask); +} + +void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val) +{ + _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val); +} + +static void _init_mp_priv_(struct mp_priv *pmp_priv) +{ + WLAN_BSSID_EX *pnetwork; + + _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv)); + + pmp_priv->mode = MP_OFF; + + pmp_priv->channel = 1; + pmp_priv->bandwidth = CHANNEL_WIDTH_20; + pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pmp_priv->rateidx = RATE_1M; + pmp_priv->txpoweridx = 0x2A; + + pmp_priv->antenna_tx = ANTENNA_A; + pmp_priv->antenna_rx = ANTENNA_AB; + + pmp_priv->check_mp_pkt = 0; + + pmp_priv->tx_pktcount = 0; + + pmp_priv->rx_bssidpktcount = 0; + pmp_priv->rx_pktcount = 0; + pmp_priv->rx_crcerrpktcount = 0; + + pmp_priv->network_macaddr[0] = 0x00; + pmp_priv->network_macaddr[1] = 0xE0; + pmp_priv->network_macaddr[2] = 0x4C; + pmp_priv->network_macaddr[3] = 0x87; + pmp_priv->network_macaddr[4] = 0x66; + pmp_priv->network_macaddr[5] = 0x55; + + pmp_priv->bSetRxBssid = _FALSE; + pmp_priv->bRTWSmbCfg = _FALSE; + pmp_priv->bloopback = _FALSE; + + pmp_priv->bloadefusemap = _FALSE; + + pnetwork = &pmp_priv->mp_network.network; + _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN); + + pnetwork->Ssid.SsidLength = 8; + _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength); + + pmp_priv->tx.payload = 2; + pmp_priv->tx.attrib.ht_en = 1; + +} + +static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + struct pkt_attrib *pattrib; + + /* init xmitframe attribute */ + pattrib = &pmptx->attrib; + _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib)); + _rtw_memset(pmptx->desc, 0, TXDESC_SIZE); + + pattrib->ether_type = 0x8712; + _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); + + /* pattrib->dhcp_pkt = 0; + * pattrib->pktlen = 0; */ + pattrib->ack_policy = 0; + /* pattrib->pkt_hdrlen = ETH_HLEN; */ + pattrib->hdrlen = WLAN_HDR_A3_LEN; + pattrib->subtype = WIFI_DATA; + pattrib->priority = 0; + pattrib->qsel = pattrib->priority; + /* do_queue_select(padapter, pattrib); */ + pattrib->nr_frags = 1; + pattrib->encrypt = 0; + pattrib->bswenc = _FALSE; + pattrib->qos_en = _FALSE; + + pattrib->pktlen = 1500; + + if (pHalData->rf_type == RF_1T1R) + pattrib->raid = RATEID_IDX_VHT_1SS; + else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) + pattrib->raid = RATEID_IDX_VHT_2SS; + else if (pHalData->rf_type == RF_3T3R) + pattrib->raid = RATEID_IDX_VHT_3SS; + else + pattrib->raid = RATEID_IDX_BGN_40M_1SS; +} + +s32 init_mp_priv(PADAPTER padapter) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + + _init_mp_priv_(pmppriv); + pmppriv->papdater = padapter; + pmppriv->mp_dm = 0; + pmppriv->tx.stop = 1; + pmppriv->bSetTxPower = 0; /*for manually set tx power*/ + pmppriv->bTxBufCkFail = _FALSE; + pmppriv->pktInterval = 0; + pmppriv->pktLength = 1000; + + mp_init_xmit_attrib(&pmppriv->tx, padapter); + + switch (padapter->registrypriv.rf_config) { + case RF_1T1R: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_A; + break; + case RF_1T2R: + default: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T2R: + case RF_2T2R_GREEN: + pmppriv->antenna_tx = ANTENNA_AB; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T4R: + pmppriv->antenna_tx = ANTENNA_BC; + pmppriv->antenna_rx = ANTENNA_ABCD; + break; + } + + pHalData->AntennaRxPath = pmppriv->antenna_rx; + pHalData->antenna_tx_path = pmppriv->antenna_tx; + + return _SUCCESS; +} + +void free_mp_priv(struct mp_priv *pmp_priv) +{ + if (pmp_priv->pallocated_mp_xmitframe_buf) { + rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0); + pmp_priv->pallocated_mp_xmitframe_buf = NULL; + } + pmp_priv->pmp_xmtframe_buf = NULL; +} + +void mpt_InitHWConfig(PADAPTER Adapter) +{ + if (IS_HARDWARE_TYPE_8723B(Adapter)) { + /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */ + /* TODO: A better solution is configure it according EFUSE during the run-time. */ + + phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0); /* 0x66[4]=0 */ + phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0); /* 0x66[8]=0 */ + phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0); /* 0x40[4]=0 */ + phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1); /* 0x40[3]=1 */ + phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1); /* 0x4C[24:23]=10 */ + phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /* 0x4C[24:23]=10 */ + phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3); /* 0x944[1:0]=11 */ + phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77 */ + phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */ + + /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */ + phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3); /* Turn off hardware PTA control (Asked by Scott) */ + phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */ + phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0); /* Fix BT can't Tx */ + + /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */ + phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/ + } else if (IS_HARDWARE_TYPE_8821(Adapter)) { + /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock) + <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/ + phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/ + phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/ + } else if (IS_HARDWARE_TYPE_8188ES(Adapter)) + phy_set_mac_reg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/ + else if (IS_HARDWARE_TYPE_8821C(Adapter)) + PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000); +} + +static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) +{ + PHAL_DATA_TYPE pHalData; + u8 b2ant; /* false:1ant, true:2-ant */ + u8 RF_Path; /* 0:S1, 1:S0 */ + + if (IS_HARDWARE_TYPE_8723B(padapter)) { + } else if (IS_HARDWARE_TYPE_8188E(padapter)) { + } else if (IS_HARDWARE_TYPE_8814A(padapter)) { + } else if (IS_HARDWARE_TYPE_8812(padapter)) { + } else if (IS_HARDWARE_TYPE_8821(padapter)) { + } else if (IS_HARDWARE_TYPE_8192E(padapter)) { + } else if (IS_HARDWARE_TYPE_8703B(padapter)) { + } else if (IS_HARDWARE_TYPE_8188F(padapter)) { + } else if (IS_HARDWARE_TYPE_8822B(padapter)) { + } else if (IS_HARDWARE_TYPE_8723D(padapter)) { + } else if (IS_HARDWARE_TYPE_8821C(padapter)) { + phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery); + } + +} + +static void PHY_LCCalibrate(PADAPTER padapter) +{ + if (IS_HARDWARE_TYPE_8723B(padapter)) { + } else if (IS_HARDWARE_TYPE_8188E(padapter)) { + } else if (IS_HARDWARE_TYPE_8814A(padapter)) { + } else if (IS_HARDWARE_TYPE_8812(padapter)) { + } else if (IS_HARDWARE_TYPE_8821(padapter)) { + } else if (IS_HARDWARE_TYPE_8192E(padapter)) { + } else if (IS_HARDWARE_TYPE_8703B(padapter)) { + } else if (IS_HARDWARE_TYPE_8188F(padapter)) { + } else if (IS_HARDWARE_TYPE_8822B(padapter)) { + } else if (IS_HARDWARE_TYPE_8723D(padapter)) { + } else if (IS_HARDWARE_TYPE_8821C(padapter)) { + /*phy_iq_calibrate_8821c(&(GET_HAL_DATA(padapter)->odmpriv));*/ + } + +} + +static u8 PHY_QueryRFPathSwitch(PADAPTER padapter) +{ + u8 bmain = 0; + + if (IS_HARDWARE_TYPE_8821C(padapter)) { + bmain = phy_query_rf_path_switch_8821c(padapter); + } + + return bmain; +} + +static void PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) { + + if (IS_HARDWARE_TYPE_8723B(padapter)) { + } else if (IS_HARDWARE_TYPE_8188E(padapter)) { + } else if (IS_HARDWARE_TYPE_8814A(padapter)) { + } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) { + } else if (IS_HARDWARE_TYPE_8192E(padapter)) { + } else if (IS_HARDWARE_TYPE_8703B(padapter)) { + } else if (IS_HARDWARE_TYPE_8188F(padapter)) { + } else if (IS_HARDWARE_TYPE_8822B(padapter)) { + } else if (IS_HARDWARE_TYPE_8723D(padapter)) { + } else if (IS_HARDWARE_TYPE_8821C(padapter)) { + phy_set_rf_path_switch_8821c(padapter, bMain); + } +} + +s32 +MPT_InitializeAdapter( + IN PADAPTER pAdapter, + IN u8 Channel +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s32 rtStatus = _SUCCESS; + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; + u32 ledsetting; + struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; + + pMptCtx->bMptDrvUnload = _FALSE; + pMptCtx->bMassProdTest = _FALSE; + pMptCtx->bMptIndexEven = _TRUE; /* default gain index is -6.0db */ + pMptCtx->h2cReqNum = 0x0; + /* init for BT MP */ + + mpt_InitHWConfig(pAdapter); + + pMptCtx->bMptWorkItemInProgress = _FALSE; + pMptCtx->CurrMptAct = NULL; + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + /* ------------------------------------------------------------------------- */ + /* Don't accept any packets */ + rtw_write32(pAdapter, REG_RCR, 0); + + /* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */ + /* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */ + + /* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */ + ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); + + PHY_LCCalibrate(pAdapter); + PHY_IQCalibrate(pAdapter, _FALSE); + /* dm_check_txpowertracking(&pHalData->odmpriv); */ /* trigger thermal meter */ + + PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */ + + pMptCtx->backup0xc50 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0); + pMptCtx->backup0xc58 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0); + pMptCtx->backup0xc30 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0); + pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); + return rtStatus; +} + +/*----------------------------------------------------------------------------- + * Function: MPT_DeInitAdapter() + * + * Overview: Extra DeInitialization for Mass Production Test. + * + * Input: PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/08/2007 MHC Create Version 0. + * 05/18/2007 MHC Add normal driver MPHalt code. + * + *---------------------------------------------------------------------------*/ +VOID +MPT_DeInitAdapter( + IN PADAPTER pAdapter +) +{ + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.mpt_ctx; + + pMptCtx->bMptDrvUnload = _TRUE; +} + +static u8 mpt_ProStartTest(PADAPTER padapter) +{ + PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx; + + pMptCtx->bMassProdTest = _TRUE; + pMptCtx->is_start_cont_tx = _FALSE; + pMptCtx->bCckContTx = _FALSE; + pMptCtx->bOfdmContTx = _FALSE; + pMptCtx->bSingleCarrier = _FALSE; + pMptCtx->is_carrier_suppression = _FALSE; + pMptCtx->is_single_tone = _FALSE; + pMptCtx->HWTxmode = PACKETS_TX; + + return _SUCCESS; +} + +/* + * General use + */ +s32 SetPowerTracking(PADAPTER padapter, u8 enable) +{ + + hal_mpt_SetPowerTracking(padapter, enable); + return 0; +} + +void rtw_mp_trigger_iqk(PADAPTER padapter) +{ + PHY_IQCalibrate(padapter, _FALSE); +} + +void rtw_mp_trigger_lck(PADAPTER padapter) +{ + PHY_LCCalibrate(padapter); +} + +static void disable_dm(PADAPTER padapter) +{ + u8 v8; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + + /* 3 1. disable firmware dynamic mechanism */ + /* disable Power Training, Rate Adaptive */ + v8 = rtw_read8(padapter, REG_BCN_CTRL); + v8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, v8); + + /* 3 2. disable driver dynamic mechanism */ + rtw_phydm_func_disable_all(padapter); + + /* enable APK, LCK and IQK but disable power tracking */ + pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; + rtw_phydm_func_set(padapter, ODM_RF_CALIBRATION); + + /* #ifdef CONFIG_BT_COEXIST */ + /* rtw_btcoex_Switch(padapter, 0); */ /* remove for BT MP Down. */ + /* #endif */ +} + +void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + + if (bstart == 1) { + RTW_INFO("in MPT_PwrCtlDM start\n"); + rtw_phydm_func_set(padapter, ODM_RF_TX_PWR_TRACK); + + pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE; + padapter->mppriv.mp_dm = 1; + + } else { + RTW_INFO("in MPT_PwrCtlDM stop\n"); + rtw_phydm_func_clr(padapter, ODM_RF_TX_PWR_TRACK); + pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; + padapter->mppriv.mp_dm = 0; + { + struct _TXPWRTRACK_CFG c; + u1Byte chnl = 0 ; + _rtw_memset(&c, 0, sizeof(struct _TXPWRTRACK_CFG)); + configure_txpower_track(pDM_Odm, &c); + odm_clear_txpowertracking_state(pDM_Odm); + if (*c.odm_tx_pwr_track_set_pwr) { + if (pDM_Odm->support_ic_type == ODM_RTL8188F) + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl); + else if (pDM_Odm->support_ic_type == ODM_RTL8723D) { + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); + SetTxPower(padapter); + } else { + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); + (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl); + } + } + } + } + +} + +u32 mp_join(PADAPTER padapter, u8 mode) +{ + WLAN_BSSID_EX bssid; + struct sta_info *psta; + u32 length; + u8 val8, join_type; + _irqL irqL; + s32 res = _SUCCESS; + + struct mp_priv *pmppriv = &padapter->mppriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + + /* 1. initialize a new WLAN_BSSID_EX */ + _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX)); + RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__, + pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4], + pmppriv->network_macaddr[5]); + _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN); + + if (mode == WIFI_FW_ADHOC_STATE) { + bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc"); + _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength); + bssid.InfrastructureMode = Ndis802_11IBSS; + bssid.NetworkTypeInUse = Ndis802_11DS; + bssid.IELength = 0; + bssid.Configuration.DSConfig = pmppriv->channel; + + } else if (mode == WIFI_FW_STATION_STATE) { + bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION"); + _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength); + bssid.InfrastructureMode = Ndis802_11Infrastructure; + bssid.NetworkTypeInUse = Ndis802_11DS; + bssid.IELength = 0; + } + + length = get_WLAN_BSSID_EX_sz(&bssid); + if (length % 4) + bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */ + else + bssid.Length = length; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + goto end_of_mp_start_test; + + /* init mp_start_test status */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + rtw_disassoc_cmd(padapter, 500, 0); + rtw_indicate_disconnect(padapter, 0, _FALSE); + rtw_free_assoc_resources(padapter, 1); + } + pmppriv->prev_fw_state = get_fwstate(pmlmepriv); + /*pmlmepriv->fw_state = WIFI_MP_STATE;*/ + init_fwstate(pmlmepriv, WIFI_MP_STATE); + + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + + /* 3 2. create a new psta for mp driver */ + /* clear psta in the cur_network, if any */ + psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); + if (psta) + rtw_free_stainfo(padapter, psta); + + psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress); + if (psta == NULL) { + /*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/ + init_fwstate(pmlmepriv, pmppriv->prev_fw_state); + res = _FAIL; + goto end_of_mp_start_test; + } + if (mode == WIFI_FW_ADHOC_STATE) + set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + else + set_fwstate(pmlmepriv, WIFI_STATION_STATE); + /* 3 3. join psudo AdHoc */ + tgt_network->join_res = 1; + tgt_network->aid = psta->aid = 1; + + _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length); + rtw_update_registrypriv_dev_network(padapter); + _rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length); + _rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length); + + rtw_indicate_connect(padapter); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + set_fwstate(pmlmepriv, _FW_LINKED); + +end_of_mp_start_test: + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + if (1) { /* (res == _SUCCESS) */ + /* set MSR to WIFI_FW_ADHOC_STATE */ + if (mode == WIFI_FW_ADHOC_STATE) { + /* set msr to WIFI_FW_ADHOC_STATE */ + pmlmeinfo->state = WIFI_FW_ADHOC_STATE; + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); + join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + + report_join_res(padapter, 1); + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + } else { + Set_MSR(padapter, WIFI_FW_STATION_STATE); + + RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__, + pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4], + pmppriv->network_macaddr[5]); + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr); + } + } + + return res; +} +/* This function initializes the DUT to the MP test mode */ +s32 mp_start_test(PADAPTER padapter) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + s32 res = _SUCCESS; + + padapter->registrypriv.mp_mode = 1; + + /* 3 disable dynamic mechanism */ + disable_dm(padapter); + rtl8821c_phy_init_haldm(padapter); + + /* 3 0. update mp_priv */ + + if (!RF_TYPE_VALID(padapter->registrypriv.rf_config)) { + /* switch (phal->rf_type) { */ + switch (GET_RF_TYPE(padapter)) { + case RF_1T1R: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_A; + break; + case RF_1T2R: + default: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T2R: + case RF_2T2R_GREEN: + pmppriv->antenna_tx = ANTENNA_AB; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T4R: + pmppriv->antenna_tx = ANTENNA_AB; + pmppriv->antenna_rx = ANTENNA_ABCD; + break; + } + } + + mpt_ProStartTest(padapter); + + mp_join(padapter, WIFI_FW_ADHOC_STATE); + + return res; +} +/* ------------------------------------------------------------------------------ + * This function change the DUT from the MP test mode into normal mode */ +void mp_stop_test(PADAPTER padapter) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct sta_info *psta; + + _irqL irqL; + + if (pmppriv->mode == MP_ON) { + pmppriv->bSetTxPower = 0; + _enter_critical_bh(&pmlmepriv->lock, &irqL); + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE) + goto end_of_mp_stop_test; + + /* 3 1. disconnect psudo AdHoc */ + rtw_indicate_disconnect(padapter, 0, _FALSE); + + /* 3 2. clear psta used in mp test mode. + * rtw_free_assoc_resources(padapter, 1); */ + psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); + if (psta) + rtw_free_stainfo(padapter, psta); + + /* 3 3. return to normal state (default:station mode) */ + /*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/ + init_fwstate(pmlmepriv, pmppriv->prev_fw_state); + + /* flush the cur_network */ + _rtw_memset(tgt_network, 0, sizeof(struct wlan_network)); + + _clr_fwstate_(pmlmepriv, WIFI_MP_STATE); + +end_of_mp_stop_test: + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + } +} + +/* + * SetChannel + * Description + * Use H2C command to change channel, + * not only modify rf register, but also other setting need to be done. + */ +void SetChannel(PADAPTER pAdapter) +{ + hal_mpt_SetChannel(pAdapter); +} + +/* + * Notice + * Switch bandwitdth may change center frequency(channel) + */ +void SetBandwidth(PADAPTER pAdapter) +{ + hal_mpt_SetBandwidth(pAdapter); + +} + +void SetAntenna(PADAPTER pAdapter) +{ + hal_mpt_SetAntenna(pAdapter); +} + +int SetTxPower(PADAPTER pAdapter) +{ + + hal_mpt_SetTxPower(pAdapter); + return _TRUE; +} + +void SetDataRate(PADAPTER pAdapter) +{ + hal_mpt_SetDataRate(pAdapter); +} + +void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain) +{ + + PHY_SetRFPathSwitch(pAdapter, bMain); + +} + +u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter) +{ + return PHY_QueryRFPathSwitch(pAdapter); +} + +s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther) +{ + return hal_mpt_SetThermalMeter(pAdapter, target_ther); +} + +void GetThermalMeter(PADAPTER pAdapter, u8 *value) +{ + hal_mpt_GetThermalMeter(pAdapter, value); +} + +void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetSingleCarrierTx(pAdapter, bStart); +} + +void SetSingleToneTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetSingleToneTx(pAdapter, bStart); +} + +void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart); +} + +void SetContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetContinuousTx(pAdapter, bStart); +} + +void PhySetTxPowerLevel(PADAPTER pAdapter) +{ + struct mp_priv *pmp_priv = &pAdapter->mppriv; + + if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */ + rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel); +} + +/* ------------------------------------------------------------------------------ */ +static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe) +{ + rtw_hal_mgnt_xmit(padapter, pmpframe); +} + +static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) +{ + struct xmit_frame *pmpframe; + struct xmit_buf *pxmitbuf; + + pmpframe = rtw_alloc_xmitframe(pxmitpriv); + if (pmpframe == NULL) + return NULL; + + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (pxmitbuf == NULL) { + rtw_free_xmitframe(pxmitpriv, pmpframe); + return NULL; + } + + pmpframe->frame_tag = MP_FRAMETAG; + + pmpframe->pxmitbuf = pxmitbuf; + + pmpframe->buf_addr = pxmitbuf->pbuf; + + pxmitbuf->priv_data = pmpframe; + + return pmpframe; + +} + +static thread_return mp_xmit_packet_thread(thread_context context) +{ + struct xmit_frame *pxmitframe; + struct mp_tx *pmptx; + struct mp_priv *pmp_priv; + struct xmit_priv *pxmitpriv; + PADAPTER padapter; + + pmp_priv = (struct mp_priv *)context; + pmptx = &pmp_priv->tx; + padapter = pmp_priv->papdater; + pxmitpriv = &(padapter->xmitpriv); + + thread_enter("RTW_MP_THREAD"); + + RTW_INFO("%s:pkTx Start\n", __func__); + while (1) { + pxmitframe = alloc_mp_xmitframe(pxmitpriv); + if (pxmitframe == NULL) { + if (pmptx->stop || + RTW_CANNOT_RUN(padapter)) + goto exit; + else { + rtw_usleep_os(10); + continue; + } + } + _rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size); + _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib)); + + rtw_usleep_os(padapter->mppriv.pktInterval); + dump_mpframe(padapter, pxmitframe); + + pmptx->sended++; + pmp_priv->tx_pktcount++; + + if (pmptx->stop || + RTW_CANNOT_RUN(padapter)) + goto exit; + if ((pmptx->count != 0) && + (pmptx->count == pmptx->sended)) + goto exit; + + flush_signals_thread(); + } + +exit: + /* RTW_INFO("%s:pkTx Exit\n", __func__); */ + rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size); + pmptx->pallocated_buf = NULL; + pmptx->stop = 1; + + thread_exit(NULL); + return 0; +} + +void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE); +} + +static void Rtw_MPSetMacTxEDCA(PADAPTER padapter) +{ + + rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */ + /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */ + phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0); + /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/ + phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/ + /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/ + RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord)); + +} + +void SetPacketTx(PADAPTER padapter) +{ + u8 *ptr, *pkt_start, *pkt_end, *fctrl; + u32 pkt_size, offset, startPlace, i; + struct rtw_ieee80211_hdr *hdr; + u8 payload; + s32 bmcast; + struct pkt_attrib *pattrib; + struct mp_priv *pmp_priv; + + pmp_priv = &padapter->mppriv; + + if (pmp_priv->tx.stop) + return; + pmp_priv->tx.sended = 0; + pmp_priv->tx.stop = 0; + pmp_priv->tx_pktcount = 0; + + /* 3 1. update_attrib() */ + pattrib = &pmp_priv->tx.attrib; + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + bmcast = IS_MCAST(pattrib->ra); + if (bmcast) { + pattrib->mac_id = 1; + pattrib->psta = rtw_get_bcmc_stainfo(padapter); + } else { + pattrib->mac_id = 0; + pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); + } + pattrib->mbssid = 0; + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; + + /* 3 2. allocate xmit buffer */ + pkt_size = pattrib->last_txcmdsz; + + if (pmp_priv->tx.pallocated_buf) + rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size); + pmp_priv->tx.write_size = pkt_size; + pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ; + pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size); + if (pmp_priv->tx.pallocated_buf == NULL) { + RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size); + return; + } + pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ); + ptr = pmp_priv->tx.buf; + + _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE); + pkt_start = ptr; + pkt_end = pkt_start + pkt_size; + + /* 3 3. init TX descriptor */ + + if (IS_HARDWARE_TYPE_8821C(padapter)) + rtl8821c_prepare_mp_txdesc(padapter, pmp_priv); + + /* 3 4. make wlan header, make_wlanhdr() */ + hdr = (struct rtw_ieee80211_hdr *)pkt_start; + set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype); + + _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */ + _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */ + _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */ + + /* 3 5. make payload */ + ptr = pkt_start + pattrib->hdrlen; + + switch (pmp_priv->tx.payload) { + case 0: + payload = 0x00; + break; + case 1: + payload = 0x5a; + break; + case 2: + payload = 0xa5; + break; + case 3: + payload = 0xff; + break; + default: + payload = 0x00; + break; + } + pmp_priv->TXradomBuffer = rtw_zmalloc(4096); + if (pmp_priv->TXradomBuffer == NULL) { + RTW_INFO("mp create random buffer fail!\n"); + goto exit; + } + + for (i = 0; i < 4096; i++) + pmp_priv->TXradomBuffer[i] = rtw_random32() % 0xFF; + + /* startPlace = (u32)(rtw_random32() % 3450); */ + _rtw_memcpy(ptr, pmp_priv->TXradomBuffer, pkt_end - ptr); + /* _rtw_memset(ptr, payload, pkt_end - ptr); */ + rtw_mfree(pmp_priv->TXradomBuffer, 4096); + + /* 3 6. start thread */ + pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD"); + if (IS_ERR(pmp_priv->tx.PktTxThread)) + RTW_INFO("Create PktTx Thread Fail !!!!!\n"); + + Rtw_MPSetMacTxEDCA(padapter); +exit: + return; +} + +void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + struct mp_priv *pmppriv = &pAdapter->mppriv; + + if (bStartRx) { + pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL; + pHalData->ReceiveConfig |= RCR_ACRC32; + pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC; + + if (pmppriv->bSetRxBssid == _TRUE) { + RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__, + MAC_ARG(pmppriv->network_macaddr)); + pHalData->ReceiveConfig = 0; + pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF; + + write_bbreg(pAdapter, 0x550, BIT3, bEnable); + rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */ + + } else { + pHalData->ReceiveConfig |= RCR_ADF; + /* Accept all data frames */ + rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF); + } + + if (bAB) + pHalData->ReceiveConfig |= RCR_AB; + } else { + pHalData->ReceiveConfig = 0; + rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */ + } + + rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); +} + +/* reg 0x808[9:0]: FFT data x + * reg 0x808[22]: 0 --> 1 to get 1 FFT data y + * reg 0x8B4[15:0]: FFT data y report */ +static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) +{ + u32 psd_val = 0; + + u16 psd_reg = 0x910; + u16 psd_regL = 0xF44; + + psd_val = rtw_read32(pAdapter, psd_reg); + + psd_val &= 0xFFBFFC00; + psd_val |= point; + + rtw_write32(pAdapter, psd_reg, psd_val); + rtw_mdelay_os(1); + psd_val |= 0x00400000; + + rtw_write32(pAdapter, psd_reg, psd_val); + rtw_mdelay_os(1); + + psd_val = rtw_read32(pAdapter, psd_regL); + psd_val &= 0x0000FFFF; + + return psd_val; +} + +/* + * pts start_point_min stop_point_max + * 128 64 64 + 128 = 192 + * 256 128 128 + 256 = 384 + * 512 256 256 + 512 = 768 + * 1024 512 512 + 1024 = 1536 + * + */ +u32 mp_query_psd(PADAPTER pAdapter, u8 *data) +{ + u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0; + u32 psd_data = 0; + + if (!netif_running(pAdapter->pnetdev)) { + return 0; + } + + if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { + return 0; + } + + if (strlen(data) == 0) { /* default value */ + psd_pts = 128; + psd_start = 64; + psd_stop = 128; + } else + sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); + + data[0] = '\0'; + + i = psd_start; + while (i < psd_stop) { + if (i >= psd_pts) + psd_data = rtw_GetPSDData(pAdapter, i - psd_pts); + else + psd_data = rtw_GetPSDData(pAdapter, i); + sprintf(data, "%s%x ", data, psd_data); + i++; + } + + rtw_msleep_os(100); + + return strlen(data) + 1; +} + +u8 +mpt_to_mgnt_rate( + IN ULONG MptRateIdx +) +{ + /* Mapped to MGN_XXX defined in MgntGen.h */ + switch (MptRateIdx) { + /* CCK rate. */ + case MPT_RATE_1M: + return MGN_1M; + case MPT_RATE_2M: + return MGN_2M; + case MPT_RATE_55M: + return MGN_5_5M; + case MPT_RATE_11M: + return MGN_11M; + + /* OFDM rate. */ + case MPT_RATE_6M: + return MGN_6M; + case MPT_RATE_9M: + return MGN_9M; + case MPT_RATE_12M: + return MGN_12M; + case MPT_RATE_18M: + return MGN_18M; + case MPT_RATE_24M: + return MGN_24M; + case MPT_RATE_36M: + return MGN_36M; + case MPT_RATE_48M: + return MGN_48M; + case MPT_RATE_54M: + return MGN_54M; + + /* HT rate. */ + case MPT_RATE_MCS0: + return MGN_MCS0; + case MPT_RATE_MCS1: + return MGN_MCS1; + case MPT_RATE_MCS2: + return MGN_MCS2; + case MPT_RATE_MCS3: + return MGN_MCS3; + case MPT_RATE_MCS4: + return MGN_MCS4; + case MPT_RATE_MCS5: + return MGN_MCS5; + case MPT_RATE_MCS6: + return MGN_MCS6; + case MPT_RATE_MCS7: + return MGN_MCS7; + case MPT_RATE_MCS8: + return MGN_MCS8; + case MPT_RATE_MCS9: + return MGN_MCS9; + case MPT_RATE_MCS10: + return MGN_MCS10; + case MPT_RATE_MCS11: + return MGN_MCS11; + case MPT_RATE_MCS12: + return MGN_MCS12; + case MPT_RATE_MCS13: + return MGN_MCS13; + case MPT_RATE_MCS14: + return MGN_MCS14; + case MPT_RATE_MCS15: + return MGN_MCS15; + case MPT_RATE_MCS16: + return MGN_MCS16; + case MPT_RATE_MCS17: + return MGN_MCS17; + case MPT_RATE_MCS18: + return MGN_MCS18; + case MPT_RATE_MCS19: + return MGN_MCS19; + case MPT_RATE_MCS20: + return MGN_MCS20; + case MPT_RATE_MCS21: + return MGN_MCS21; + case MPT_RATE_MCS22: + return MGN_MCS22; + case MPT_RATE_MCS23: + return MGN_MCS23; + case MPT_RATE_MCS24: + return MGN_MCS24; + case MPT_RATE_MCS25: + return MGN_MCS25; + case MPT_RATE_MCS26: + return MGN_MCS26; + case MPT_RATE_MCS27: + return MGN_MCS27; + case MPT_RATE_MCS28: + return MGN_MCS28; + case MPT_RATE_MCS29: + return MGN_MCS29; + case MPT_RATE_MCS30: + return MGN_MCS30; + case MPT_RATE_MCS31: + return MGN_MCS31; + + /* VHT rate. */ + case MPT_RATE_VHT1SS_MCS0: + return MGN_VHT1SS_MCS0; + case MPT_RATE_VHT1SS_MCS1: + return MGN_VHT1SS_MCS1; + case MPT_RATE_VHT1SS_MCS2: + return MGN_VHT1SS_MCS2; + case MPT_RATE_VHT1SS_MCS3: + return MGN_VHT1SS_MCS3; + case MPT_RATE_VHT1SS_MCS4: + return MGN_VHT1SS_MCS4; + case MPT_RATE_VHT1SS_MCS5: + return MGN_VHT1SS_MCS5; + case MPT_RATE_VHT1SS_MCS6: + return MGN_VHT1SS_MCS6; + case MPT_RATE_VHT1SS_MCS7: + return MGN_VHT1SS_MCS7; + case MPT_RATE_VHT1SS_MCS8: + return MGN_VHT1SS_MCS8; + case MPT_RATE_VHT1SS_MCS9: + return MGN_VHT1SS_MCS9; + case MPT_RATE_VHT2SS_MCS0: + return MGN_VHT2SS_MCS0; + case MPT_RATE_VHT2SS_MCS1: + return MGN_VHT2SS_MCS1; + case MPT_RATE_VHT2SS_MCS2: + return MGN_VHT2SS_MCS2; + case MPT_RATE_VHT2SS_MCS3: + return MGN_VHT2SS_MCS3; + case MPT_RATE_VHT2SS_MCS4: + return MGN_VHT2SS_MCS4; + case MPT_RATE_VHT2SS_MCS5: + return MGN_VHT2SS_MCS5; + case MPT_RATE_VHT2SS_MCS6: + return MGN_VHT2SS_MCS6; + case MPT_RATE_VHT2SS_MCS7: + return MGN_VHT2SS_MCS7; + case MPT_RATE_VHT2SS_MCS8: + return MGN_VHT2SS_MCS8; + case MPT_RATE_VHT2SS_MCS9: + return MGN_VHT2SS_MCS9; + case MPT_RATE_VHT3SS_MCS0: + return MGN_VHT3SS_MCS0; + case MPT_RATE_VHT3SS_MCS1: + return MGN_VHT3SS_MCS1; + case MPT_RATE_VHT3SS_MCS2: + return MGN_VHT3SS_MCS2; + case MPT_RATE_VHT3SS_MCS3: + return MGN_VHT3SS_MCS3; + case MPT_RATE_VHT3SS_MCS4: + return MGN_VHT3SS_MCS4; + case MPT_RATE_VHT3SS_MCS5: + return MGN_VHT3SS_MCS5; + case MPT_RATE_VHT3SS_MCS6: + return MGN_VHT3SS_MCS6; + case MPT_RATE_VHT3SS_MCS7: + return MGN_VHT3SS_MCS7; + case MPT_RATE_VHT3SS_MCS8: + return MGN_VHT3SS_MCS8; + case MPT_RATE_VHT3SS_MCS9: + return MGN_VHT3SS_MCS9; + case MPT_RATE_VHT4SS_MCS0: + return MGN_VHT4SS_MCS0; + case MPT_RATE_VHT4SS_MCS1: + return MGN_VHT4SS_MCS1; + case MPT_RATE_VHT4SS_MCS2: + return MGN_VHT4SS_MCS2; + case MPT_RATE_VHT4SS_MCS3: + return MGN_VHT4SS_MCS3; + case MPT_RATE_VHT4SS_MCS4: + return MGN_VHT4SS_MCS4; + case MPT_RATE_VHT4SS_MCS5: + return MGN_VHT4SS_MCS5; + case MPT_RATE_VHT4SS_MCS6: + return MGN_VHT4SS_MCS6; + case MPT_RATE_VHT4SS_MCS7: + return MGN_VHT4SS_MCS7; + case MPT_RATE_VHT4SS_MCS8: + return MGN_VHT4SS_MCS8; + case MPT_RATE_VHT4SS_MCS9: + return MGN_VHT4SS_MCS9; + + case MPT_RATE_LAST: /* fully automatiMGN_VHT2SS_MCS1; */ + default: + RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx); + return 0x0; + } +} + +u8 HwRateToMPTRate(u8 rate) +{ + u8 ret_rate = MGN_1M; + + switch (rate) { + case DESC_RATE1M: + ret_rate = MPT_RATE_1M; + break; + case DESC_RATE2M: + ret_rate = MPT_RATE_2M; + break; + case DESC_RATE5_5M: + ret_rate = MPT_RATE_55M; + break; + case DESC_RATE11M: + ret_rate = MPT_RATE_11M; + break; + case DESC_RATE6M: + ret_rate = MPT_RATE_6M; + break; + case DESC_RATE9M: + ret_rate = MPT_RATE_9M; + break; + case DESC_RATE12M: + ret_rate = MPT_RATE_12M; + break; + case DESC_RATE18M: + ret_rate = MPT_RATE_18M; + break; + case DESC_RATE24M: + ret_rate = MPT_RATE_24M; + break; + case DESC_RATE36M: + ret_rate = MPT_RATE_36M; + break; + case DESC_RATE48M: + ret_rate = MPT_RATE_48M; + break; + case DESC_RATE54M: + ret_rate = MPT_RATE_54M; + break; + case DESC_RATEMCS0: + ret_rate = MPT_RATE_MCS0; + break; + case DESC_RATEMCS1: + ret_rate = MPT_RATE_MCS1; + break; + case DESC_RATEMCS2: + ret_rate = MPT_RATE_MCS2; + break; + case DESC_RATEMCS3: + ret_rate = MPT_RATE_MCS3; + break; + case DESC_RATEMCS4: + ret_rate = MPT_RATE_MCS4; + break; + case DESC_RATEMCS5: + ret_rate = MPT_RATE_MCS5; + break; + case DESC_RATEMCS6: + ret_rate = MPT_RATE_MCS6; + break; + case DESC_RATEMCS7: + ret_rate = MPT_RATE_MCS7; + break; + case DESC_RATEMCS8: + ret_rate = MPT_RATE_MCS8; + break; + case DESC_RATEMCS9: + ret_rate = MPT_RATE_MCS9; + break; + case DESC_RATEMCS10: + ret_rate = MPT_RATE_MCS10; + break; + case DESC_RATEMCS11: + ret_rate = MPT_RATE_MCS11; + break; + case DESC_RATEMCS12: + ret_rate = MPT_RATE_MCS12; + break; + case DESC_RATEMCS13: + ret_rate = MPT_RATE_MCS13; + break; + case DESC_RATEMCS14: + ret_rate = MPT_RATE_MCS14; + break; + case DESC_RATEMCS15: + ret_rate = MPT_RATE_MCS15; + break; + case DESC_RATEMCS16: + ret_rate = MPT_RATE_MCS16; + break; + case DESC_RATEMCS17: + ret_rate = MPT_RATE_MCS17; + break; + case DESC_RATEMCS18: + ret_rate = MPT_RATE_MCS18; + break; + case DESC_RATEMCS19: + ret_rate = MPT_RATE_MCS19; + break; + case DESC_RATEMCS20: + ret_rate = MPT_RATE_MCS20; + break; + case DESC_RATEMCS21: + ret_rate = MPT_RATE_MCS21; + break; + case DESC_RATEMCS22: + ret_rate = MPT_RATE_MCS22; + break; + case DESC_RATEMCS23: + ret_rate = MPT_RATE_MCS23; + break; + case DESC_RATEMCS24: + ret_rate = MPT_RATE_MCS24; + break; + case DESC_RATEMCS25: + ret_rate = MPT_RATE_MCS25; + break; + case DESC_RATEMCS26: + ret_rate = MPT_RATE_MCS26; + break; + case DESC_RATEMCS27: + ret_rate = MPT_RATE_MCS27; + break; + case DESC_RATEMCS28: + ret_rate = MPT_RATE_MCS28; + break; + case DESC_RATEMCS29: + ret_rate = MPT_RATE_MCS29; + break; + case DESC_RATEMCS30: + ret_rate = MPT_RATE_MCS30; + break; + case DESC_RATEMCS31: + ret_rate = MPT_RATE_MCS31; + break; + case DESC_RATEVHTSS1MCS0: + ret_rate = MPT_RATE_VHT1SS_MCS0; + break; + case DESC_RATEVHTSS1MCS1: + ret_rate = MPT_RATE_VHT1SS_MCS1; + break; + case DESC_RATEVHTSS1MCS2: + ret_rate = MPT_RATE_VHT1SS_MCS2; + break; + case DESC_RATEVHTSS1MCS3: + ret_rate = MPT_RATE_VHT1SS_MCS3; + break; + case DESC_RATEVHTSS1MCS4: + ret_rate = MPT_RATE_VHT1SS_MCS4; + break; + case DESC_RATEVHTSS1MCS5: + ret_rate = MPT_RATE_VHT1SS_MCS5; + break; + case DESC_RATEVHTSS1MCS6: + ret_rate = MPT_RATE_VHT1SS_MCS6; + break; + case DESC_RATEVHTSS1MCS7: + ret_rate = MPT_RATE_VHT1SS_MCS7; + break; + case DESC_RATEVHTSS1MCS8: + ret_rate = MPT_RATE_VHT1SS_MCS8; + break; + case DESC_RATEVHTSS1MCS9: + ret_rate = MPT_RATE_VHT1SS_MCS9; + break; + case DESC_RATEVHTSS2MCS0: + ret_rate = MPT_RATE_VHT2SS_MCS0; + break; + case DESC_RATEVHTSS2MCS1: + ret_rate = MPT_RATE_VHT2SS_MCS1; + break; + case DESC_RATEVHTSS2MCS2: + ret_rate = MPT_RATE_VHT2SS_MCS2; + break; + case DESC_RATEVHTSS2MCS3: + ret_rate = MPT_RATE_VHT2SS_MCS3; + break; + case DESC_RATEVHTSS2MCS4: + ret_rate = MPT_RATE_VHT2SS_MCS4; + break; + case DESC_RATEVHTSS2MCS5: + ret_rate = MPT_RATE_VHT2SS_MCS5; + break; + case DESC_RATEVHTSS2MCS6: + ret_rate = MPT_RATE_VHT2SS_MCS6; + break; + case DESC_RATEVHTSS2MCS7: + ret_rate = MPT_RATE_VHT2SS_MCS7; + break; + case DESC_RATEVHTSS2MCS8: + ret_rate = MPT_RATE_VHT2SS_MCS8; + break; + case DESC_RATEVHTSS2MCS9: + ret_rate = MPT_RATE_VHT2SS_MCS9; + break; + case DESC_RATEVHTSS3MCS0: + ret_rate = MPT_RATE_VHT3SS_MCS0; + break; + case DESC_RATEVHTSS3MCS1: + ret_rate = MPT_RATE_VHT3SS_MCS1; + break; + case DESC_RATEVHTSS3MCS2: + ret_rate = MPT_RATE_VHT3SS_MCS2; + break; + case DESC_RATEVHTSS3MCS3: + ret_rate = MPT_RATE_VHT3SS_MCS3; + break; + case DESC_RATEVHTSS3MCS4: + ret_rate = MPT_RATE_VHT3SS_MCS4; + break; + case DESC_RATEVHTSS3MCS5: + ret_rate = MPT_RATE_VHT3SS_MCS5; + break; + case DESC_RATEVHTSS3MCS6: + ret_rate = MPT_RATE_VHT3SS_MCS6; + break; + case DESC_RATEVHTSS3MCS7: + ret_rate = MPT_RATE_VHT3SS_MCS7; + break; + case DESC_RATEVHTSS3MCS8: + ret_rate = MPT_RATE_VHT3SS_MCS8; + break; + case DESC_RATEVHTSS3MCS9: + ret_rate = MPT_RATE_VHT3SS_MCS9; + break; + case DESC_RATEVHTSS4MCS0: + ret_rate = MPT_RATE_VHT4SS_MCS0; + break; + case DESC_RATEVHTSS4MCS1: + ret_rate = MPT_RATE_VHT4SS_MCS1; + break; + case DESC_RATEVHTSS4MCS2: + ret_rate = MPT_RATE_VHT4SS_MCS2; + break; + case DESC_RATEVHTSS4MCS3: + ret_rate = MPT_RATE_VHT4SS_MCS3; + break; + case DESC_RATEVHTSS4MCS4: + ret_rate = MPT_RATE_VHT4SS_MCS4; + break; + case DESC_RATEVHTSS4MCS5: + ret_rate = MPT_RATE_VHT4SS_MCS5; + break; + case DESC_RATEVHTSS4MCS6: + ret_rate = MPT_RATE_VHT4SS_MCS6; + break; + case DESC_RATEVHTSS4MCS7: + ret_rate = MPT_RATE_VHT4SS_MCS7; + break; + case DESC_RATEVHTSS4MCS8: + ret_rate = MPT_RATE_VHT4SS_MCS8; + break; + case DESC_RATEVHTSS4MCS9: + ret_rate = MPT_RATE_VHT4SS_MCS9; + break; + + default: + RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate); + break; + } + return ret_rate; +} + +u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr) +{ + u16 i = 0; + u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M", + "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7", + "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15", + "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23", + "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31", + "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9", + "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9", + "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9", + "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9" + }; + + for (i = 0; i <= 83; i++) { + if (strcmp(targetStr, rateindex_Array[i]) == 0) { + RTW_INFO("%s , index = %d\n", __func__ , i); + return i; + } + } + + printk("%s ,please input a Data RATE String as:", __func__); + for (i = 0; i <= 83; i++) { + printk("%s ", rateindex_Array[i]); + if (i % 10 == 0) + printk("\n"); + } + return _FAIL; +} + +ULONG mpt_ProQueryCalTxPower( + PADAPTER pAdapter, + u8 RfPath +) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + + ULONG TxPower = 1; + u1Byte rate = 0; + struct txpwr_idx_comp tic; + u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); + + TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel, &tic); + + RTW_INFO("bw=%d, ch=%d, rate=%d, txPower:%u = %u + (%d=%d:%d) + (%d) + (%d)\n", + pHalData->current_channel_bw, pHalData->current_channel, mgn_rate + , TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); + + pAdapter->mppriv.txpoweridx = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)TxPower; + hal_mpt_SetTxPower(pAdapter); + + return TxPower; +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_odm.c b/drivers/staging/rtl8821ce/core/rtw_odm.c new file mode 100644 index 000000000000..58d0aca93765 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_odm.c @@ -0,0 +1,380 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <rtw_odm.h> +#include <hal_data.h> + +/* set ODM_CMNINFO_IC_TYPE based on chip_type */ +void rtw_odm_init_ic_type(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; + u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter)); + + rtw_warn_on(!ic_type); + + odm_cmn_info_init(odm, ODM_CMNINFO_IC_TYPE, ic_type); +} + +inline void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + hal_data->u1ForcedIgiLb = lb; +} + +inline u8 rtw_odm_get_force_igi_lb(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + return hal_data->u1ForcedIgiLb; +} + +void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter) +{ + RTW_PRINT_SEL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n"); +} + +#define RTW_ADAPTIVITY_EN_DISABLE 0 +#define RTW_ADAPTIVITY_EN_ENABLE 1 + +void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + struct mlme_priv *mlme = &adapter->mlmepriv; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; + + RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_EN_"); + + if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) + _RTW_PRINT_SEL(sel, "DISABLE\n"); + else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) + _RTW_PRINT_SEL(sel, "ENABLE\n"); + else + _RTW_PRINT_SEL(sel, "INVALID\n"); +} + +#define RTW_ADAPTIVITY_MODE_NORMAL 0 +#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1 + +void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_MODE_"); + + if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) + _RTW_PRINT_SEL(sel, "NORMAL\n"); + else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) + _RTW_PRINT_SEL(sel, "CARRIER_SENSE\n"); + else + _RTW_PRINT_SEL(sel, "INVALID\n"); +} + +#define RTW_ADAPTIVITY_DML_DISABLE 0 +#define RTW_ADAPTIVITY_DML_ENABLE 1 + +void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DML_"); + + if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE) + _RTW_PRINT_SEL(sel, "DISABLE\n"); + else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE) + _RTW_PRINT_SEL(sel, "ENABLE\n"); + else + _RTW_PRINT_SEL(sel, "INVALID\n"); +} + +void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + RTW_PRINT_SEL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff); +} + +void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter) +{ + rtw_odm_adaptivity_ver_msg(sel, adapter); + rtw_odm_adaptivity_en_msg(sel, adapter); + rtw_odm_adaptivity_mode_msg(sel, adapter); + rtw_odm_adaptivity_dml_msg(sel, adapter); + rtw_odm_adaptivity_dc_backoff_msg(sel, adapter); +} + +bool rtw_odm_adaptivity_needed(_adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + struct mlme_priv *mlme = &adapter->mlmepriv; + bool ret = _FALSE; + + if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) + ret = _TRUE; + + return ret; +} + +void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; + + rtw_odm_adaptivity_config_msg(sel, adapter); + + RTW_PRINT_SEL(sel, "%10s %16s %16s %22s %12s\n" + , "th_l2h_ini", "th_edcca_hl_diff", "th_l2h_ini_mode2", "th_edcca_hl_diff_mode2", "edcca_enable"); + RTW_PRINT_SEL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n" + , (u8)odm->th_l2h_ini + , odm->th_edcca_hl_diff + , (u8)odm->th_l2h_ini_mode2 + , odm->th_edcca_hl_diff_mode2 + , odm->edcca_enable + ); + + RTW_PRINT_SEL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag"); + RTW_PRINT_SEL(sel, "%-15x %-9x\n" + , odm->adaptivity_enable + , odm->adaptivity_flag + ); +} + +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *odm = &pHalData->odmpriv; + + odm->th_l2h_ini = th_l2h_ini; + odm->th_edcca_hl_diff = th_edcca_hl_diff; + odm->th_l2h_ini_mode2 = th_l2h_ini_mode2; + odm->th_edcca_hl_diff_mode2 = th_edcca_hl_diff_mode2; + odm->edcca_enable = edcca_enable; +} + +void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *odm = &(hal_data->odmpriv); + + RTW_PRINT_SEL(sel, "rx_rate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n", + HDATA_RATE(odm->rx_rate), odm->RSSI_A, odm->RSSI_B); +} + +void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + _irqL irqL; + + switch (type) { + case RT_IQK_SPINLOCK: + _enter_critical_bh(&pHalData->IQKSpinLock, &irqL); + default: + break; + } +} + +void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + _irqL irqL; + + switch (type) { + case RT_IQK_SPINLOCK: + _exit_critical_bh(&pHalData->IQKSpinLock, &irqL); + default: + break; + } +} + +inline u8 rtw_odm_get_dfs_domain(_adapter *adapter) +{ + return PHYDM_DFS_DOMAIN_UNKNOWN; +} + +inline u8 rtw_odm_dfs_domain_unknown(_adapter *adapter) +{ + return 1; +} + + +void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys) +{ +#ifndef DBG_RX_PHYSTATUS_CHINFO +#define DBG_RX_PHYSTATUS_CHINFO 0 +#endif + + _adapter *adapter = rframe->u.hdr.adapter; + struct PHY_DM_STRUCT *phydm = GET_ODM(adapter); + struct rx_pkt_attrib *attrib = &rframe->u.hdr.attrib; + u8 *wlanhdr = get_recvframe_data(rframe); + + if (phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { + /* + * 8723D: + * type_0(CCK) + * l_rxsc + * is filled with primary channel SC, not real rxsc. + * 0:LSC, 1:USC + * type_1(OFDM) + * rf_mode + * RF bandwidth when RX + * l_rxsc(legacy), ht_rxsc + * see below RXSC N-series + * type_2(Not used) + */ + /* + * 8821C, 8822B: + * type_0(CCK) + * l_rxsc + * is filled with primary channel SC, not real rxsc. + * 0:LSC, 1:USC + * type_1(OFDM) + * rf_mode + * RF bandwidth when RX + * l_rxsc(legacy), ht_rxsc + * see below RXSC AC-series + * type_2(Not used) + */ + + if ((*phys & 0xf) == 0) { + struct _phy_status_rpt_jaguar2_type0 *phys_t0 = (struct _phy_status_rpt_jaguar2_type0 *)phys; + + if (DBG_RX_PHYSTATUS_CHINFO) { + RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u)\n" + , *phys & 0xf + , MAC_ARG(get_ta(wlanhdr)) + , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC" + , HDATA_RATE(attrib->data_rate) + , phys_t0->band, phys_t0->channel, phys_t0->rxsc + ); + } + + } else if ((*phys & 0xf) == 1) { + struct _phy_status_rpt_jaguar2_type1 *phys_t1 = (struct _phy_status_rpt_jaguar2_type1 *)phys; + u8 rxsc = (attrib->data_rate > DESC_RATE11M && attrib->data_rate < DESC_RATEMCS0) ? phys_t1->l_rxsc : phys_t1->ht_rxsc; + u8 pkt_cch = 0; + u8 pkt_bw = CHANNEL_WIDTH_20; + + + if (phydm->support_ic_type & ODM_IC_11AC_SERIES) { + /* RXSC AC-series */ + #define RXSC_DUP 0 /* 0: RX from all SC of current rf_mode */ + + #define RXSC_LL20M_OF_160M 8 /* 1~8: RX from 20MHz SC */ + #define RXSC_L20M_OF_160M 6 + #define RXSC_L20M_OF_80M 4 + #define RXSC_L20M_OF_40M 2 + #define RXSC_U20M_OF_40M 1 + #define RXSC_U20M_OF_80M 3 + #define RXSC_U20M_OF_160M 5 + #define RXSC_UU20M_OF_160M 7 + + #define RXSC_L40M_OF_160M 12 /* 9~12: RX from 40MHz SC */ + #define RXSC_L40M_OF_80M 10 + #define RXSC_U40M_OF_80M 9 + #define RXSC_U40M_OF_160M 11 + + #define RXSC_L80M_OF_160M 14 /* 13~14: RX from 80MHz SC */ + #define RXSC_U80M_OF_160M 13 + + static const s8 cch_offset_by_rxsc[15] = {0, 2, -2, 6, -6, 10, -10, 14, -14, 4, -4, 12, -12, 8, -8}; + + if (phys_t1->rf_mode > 3) { + /* invalid rf_mode */ + rtw_warn_on(1); + goto type1_end; + } + + if (phys_t1->rf_mode == 0) { + /* RF 20MHz */ + pkt_cch = phys_t1->channel; + pkt_bw = CHANNEL_WIDTH_20; + goto type1_end; + } + + if (rxsc == 0) { + /* RF and RX with same BW */ + if (attrib->data_rate >= DESC_RATEMCS0) { + pkt_cch = phys_t1->channel; + pkt_bw = phys_t1->rf_mode; + } + goto type1_end; + } + + if ((phys_t1->rf_mode == 1 && rxsc >= 1 && rxsc <= 2) /* RF 40MHz, RX 20MHz */ + || (phys_t1->rf_mode == 2 && rxsc >= 1 && rxsc <= 4) /* RF 80MHz, RX 20MHz */ + || (phys_t1->rf_mode == 3 && rxsc >= 1 && rxsc <= 8) /* RF 160MHz, RX 20MHz */ + ) { + pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc]; + pkt_bw = CHANNEL_WIDTH_20; + } else if ((phys_t1->rf_mode == 2 && rxsc >= 9 && rxsc <= 10) /* RF 80MHz, RX 40MHz */ + || (phys_t1->rf_mode == 3 && rxsc >= 9 && rxsc <= 12) /* RF 160MHz, RX 40MHz */ + ) { + if (attrib->data_rate >= DESC_RATEMCS0) { + pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc]; + pkt_bw = CHANNEL_WIDTH_40; + } + } else if ((phys_t1->rf_mode == 3 && rxsc >= 13 && rxsc <= 14) /* RF 160MHz, RX 80MHz */ + ) { + if (attrib->data_rate >= DESC_RATEMCS0) { + pkt_cch = phys_t1->channel + cch_offset_by_rxsc[rxsc]; + pkt_bw = CHANNEL_WIDTH_80; + } + } else + rtw_warn_on(1); + + } + +type1_end: + if (DBG_RX_PHYSTATUS_CHINFO) { + RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, rf_mode:%u, l_rxsc:%u, ht_rxsc:%u) => %u,%u\n" + , *phys & 0xf + , MAC_ARG(get_ta(wlanhdr)) + , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC" + , HDATA_RATE(attrib->data_rate) + , phys_t1->band, phys_t1->channel, phys_t1->rf_mode, phys_t1->l_rxsc, phys_t1->ht_rxsc + , pkt_cch, pkt_bw + ); + } + + /* for now, only return cneter channel of 20MHz packet */ + if (pkt_cch && pkt_bw == CHANNEL_WIDTH_20) + attrib->ch = pkt_cch; + + } else { + struct _phy_status_rpt_jaguar2_type2 *phys_t2 = (struct _phy_status_rpt_jaguar2_type2 *)phys; + + if (DBG_RX_PHYSTATUS_CHINFO) { + RTW_PRINT("phys_t%u ta="MAC_FMT" %s, %s(band:%u, ch:%u, l_rxsc:%u, ht_rxsc:%u)\n" + , *phys & 0xf + , MAC_ARG(get_ta(wlanhdr)) + , is_broadcast_mac_addr(get_ra(wlanhdr)) ? "BC" : is_multicast_mac_addr(get_ra(wlanhdr)) ? "MC" : "UC" + , HDATA_RATE(attrib->data_rate) + , phys_t2->band, phys_t2->channel, phys_t2->l_rxsc, phys_t2->ht_rxsc + ); + } + } + } + +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_p2p.c b/drivers/staging/rtl8821ce/core/rtw_p2p.c new file mode 100644 index 000000000000..5238f8c6e48d --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_p2p.c @@ -0,0 +1,3661 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_P2P_C_ + +#include <drv_types.h> + + +int rtw_p2p_is_channel_list_ok(u8 desired_ch, u8 *ch_list, u8 ch_cnt) +{ + int found = 0, i = 0; + + for (i = 0; i < ch_cnt; i++) { + if (ch_list[i] == desired_ch) { + found = 1; + break; + } + } + return found ; +} + +int is_any_client_associated(_adapter *padapter) +{ + return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE; +} + +static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + _irqL irqL; + _list *phead, *plist; + u32 len = 0; + u16 attr_len = 0; + u8 tmplen, *pdata_attr, *pstart, *pcur; + struct sta_info *psta = NULL; + _adapter *padapter = pwdinfo->padapter; + struct sta_priv *pstapriv = &padapter->stapriv; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN); + + if (NULL == pdata_attr) { + RTW_INFO("%s pdata_attr malloc failed\n", __FUNCTION__); + goto _exit; + } + + pstart = pdata_attr; + pcur = pdata_attr; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + /* look up sta asoc_queue */ + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + + plist = get_next(plist); + + if (psta->is_p2p_device) { + tmplen = 0; + + pcur++; + + /* P2P device address */ + _rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN); + pcur += ETH_ALEN; + + /* P2P interface address */ + _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN); + pcur += ETH_ALEN; + + *pcur = psta->dev_cap; + pcur++; + + /* *(u16*)(pcur) = cpu_to_be16(psta->config_methods); */ + RTW_PUT_BE16(pcur, psta->config_methods); + pcur += 2; + + _rtw_memcpy(pcur, psta->primary_dev_type, 8); + pcur += 8; + + *pcur = psta->num_of_secdev_type; + pcur++; + + _rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type * 8); + pcur += psta->num_of_secdev_type * 8; + + if (psta->dev_name_len > 0) { + /* *(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */ + RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME); + pcur += 2; + + /* *(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); */ + RTW_PUT_BE16(pcur, psta->dev_name_len); + pcur += 2; + + _rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len); + pcur += psta->dev_name_len; + } + + tmplen = (u8)(pcur - pstart); + + *pstart = (tmplen - 1); + + attr_len += tmplen; + + /* pstart += tmplen; */ + pstart = pcur; + + } + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + if (attr_len > 0) + len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr); + + rtw_mfree(pdata_attr, MAX_P2P_IE_LEN); + +_exit: + return len; + +} + +static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + _adapter *padapter = pwdinfo->padapter; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame */ + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_DISC_REQUEST; + u8 dialogToken = 0; + + RTW_INFO("[%s]\n", __FUNCTION__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* Build P2P action frame header */ + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + /* there is no IE in this P2P action frame */ + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + _adapter *padapter = pwdinfo->padapter; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_DEVDISC_RESP; + u8 p2pie[8] = { 0x00 }; + u32 p2pielen = 0; + + RTW_INFO("[%s]\n", __FUNCTION__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* Build P2P public action frame header */ + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + /* Build P2P IE */ + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* P2P_ATTR_STATUS */ + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen); + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8 *raddr, u8 *frame_body, u16 config_method) +{ + _adapter *padapter = pwdinfo->padapter; + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u8 dialogToken = frame_body[7]; /* The Dialog Token of provisioning discovery request frame. */ + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PROVISION_DISC_RESP; + u8 wpsie[100] = { 0x00 }; + u8 wpsielen = 0; + u32 wfdielen = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + wpsielen = 0; + /* WPS OUI */ + /* *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); */ + RTW_PUT_BE32(wpsie, WPSOUI); + wpsielen += 4; + + /* Config Method */ + /* Type: */ + /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); */ + RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD); + wpsielen += 2; + + /* Length: */ + /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); */ + RTW_PUT_BE16(wpsie + wpsielen, 0x0002); + wpsielen += 2; + + /* Value: */ + /* *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); */ + RTW_PUT_BE16(wpsie + wpsielen, config_method); + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen); + + wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + _adapter *padapter = pwdinfo->padapter; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + unsigned char category = RTW_WLAN_CATEGORY_P2P;/* P2P action frame */ + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PRESENCE_RESPONSE; + u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; + u8 noa_attr_content[32] = { 0x00 }; + u32 p2pielen = 0; + + RTW_INFO("[%s]\n", __FUNCTION__); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + return; + + /* update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + set_frame_sub_type(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* Build P2P action frame header */ + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + /* Add P2P IE header */ + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Add Status attribute in P2P IE */ + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); + + /* Add NoA attribute in P2P IE */ + noa_attr_content[0] = 0x1;/* index */ + noa_attr_content[1] = 0x0;/* CTWindow and OppPS Parameters */ + + /* todo: Notice of Absence Descriptor(s) */ + + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content); + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen)); + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; + u16 capability = 0; + u32 len = 0, p2pielen = 0; + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* According to the P2P Specification, the beacon frame should contain 3 P2P attributes */ + /* 1. P2P Capability */ + /* 2. P2P Device ID */ + /* 3. Notice of Absence ( NOA ) */ + + /* P2P Capability ATTR */ + /* Type: */ + /* Length: */ + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + /* Be able to participate in additional P2P Groups and */ + /* support the P2P Invitation Procedure */ + /* Group Capability Bitmap, 1 byte */ + capability = P2P_DEVCAP_INVITATION_PROC | P2P_DEVCAP_CLIENT_DISCOVERABILITY; + capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8); + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) + capability |= (P2P_GRPCAP_GROUP_FORMATION << 8); + + capability = cpu_to_le16(capability); + + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8 *)&capability); + + /* P2P Device ID ATTR */ + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr); + + /* Notice of Absence ATTR */ + /* Type: */ + /* Length: */ + /* Value: */ + + /* go_add_noa_attr(pwdinfo); */ + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + return len; + +} + +u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16 = 0; + u32 len = 0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110812 */ + /* According to the WFD Specification, the beacon frame should contain 4 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID */ + /* 3. Coupled Sink Information */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + + if (P2P_ROLE_GO == pwdinfo->role) { + if (is_any_client_associated(pwdinfo->padapter)) { + /* WFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } else { + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } + + } else { + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } + + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16 = 0; + u32 len = 0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110812 */ + /* According to the WFD Specification, the probe request frame should contain 4 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID */ + /* 3. Coupled Sink Information */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + + if (1 == pwdinfo->wfd_tdls_enable) { + /* WFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | + WFD_DEVINFO_SESSION_AVAIL | + WFD_DEVINFO_WSD | + WFD_DEVINFO_PC_TDLS; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } else { + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | + WFD_DEVINFO_SESSION_AVAIL | + WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } + + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110812 */ + /* According to the WFD Specification, the probe response frame should contain 4 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID */ + /* 3. Coupled Sink Information */ + /* 4. WFD Session Information */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + available for WFD session + WiFi Direct mode */ + + if (_TRUE == pwdinfo->session_available) { + if (P2P_ROLE_GO == pwdinfo->role) { + if (is_any_client_associated(pwdinfo->padapter)) { + if (pwdinfo->wfd_tdls_enable) { + /* TDLS mode + WSD ( WFD Service Discovery ) */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + } else { + /* WiFi Direct mode + WSD ( WFD Service Discovery ) */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + } + } else { + if (pwdinfo->wfd_tdls_enable) { + /* available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + } else { + /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + } + } + } else { + if (pwdinfo->wfd_tdls_enable) { + /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + } else { + + /* available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + } + } + } else { + if (pwdinfo->wfd_tdls_enable) + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + else + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + + } + + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* WFD Session Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0000); + wfdielen += 2; + + /* Todo: to add the list of WFD device info descriptor in WFD group. */ + + } + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16 = 0; + u32 len = 0, wfdielen = 0; + _adapter *padapter = NULL; + struct mlme_priv *pmlmepriv = NULL; + struct wifi_display_info *pwfd_info = NULL; + + padapter = pwdinfo->padapter; + pmlmepriv = &padapter->mlmepriv; + pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110812 */ + /* According to the WFD Specification, the probe request frame should contain 4 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID */ + /* 3. Coupled Sink Information */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + u16 val16 = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110812 */ + /* According to the WFD Specification, the probe request frame should contain 4 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID */ + /* 3. Coupled Sink Information */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + u16 val16 = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110825 */ + /* According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID ( Optional ) */ + /* 3. Local IP Adress ( Optional ) */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + u16 val16 = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110825 */ + /* According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID ( Optional ) */ + /* 3. Local IP Adress ( Optional ) */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + u16 val16 = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110825 */ + /* According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID ( Optional ) */ + /* 3. Local IP Adress ( Optional ) */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + u16 val16 = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110825 */ + /* According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID ( Optional ) */ + /* 3. Local IP Adress ( Optional ) */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + if (P2P_ROLE_GO == pwdinfo->role) { + /* WFD Session Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0000); + wfdielen += 2; + + /* Todo: to add the list of WFD device info descriptor in WFD group. */ + + } + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16 = 0; + u32 len = 0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110825 */ + /* According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID ( Optional ) */ + /* 3. Local IP Adress ( Optional ) */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + if (P2P_ROLE_GO == pwdinfo->role) { + /* WFD Session Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_SESSION_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0000); + wfdielen += 2; + + /* Todo: to add the list of WFD device info descriptor in WFD group. */ + + } + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + u16 val16 = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110825 */ + /* According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID ( Optional ) */ + /* 3. Local IP Adress ( Optional ) */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[MAX_WFD_IE_LEN] = { 0x00 }; + u32 len = 0, wfdielen = 0; + u16 val16 = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[wfdielen++] = 0x50; + wfdie[wfdielen++] = 0x6F; + wfdie[wfdielen++] = 0x9A; + wfdie[wfdielen++] = 0x0A; /* WFA WFD v1.0 */ + + /* Commented by Albert 20110825 */ + /* According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes */ + /* 1. WFD Device Information */ + /* 2. Associated BSSID ( Optional ) */ + /* 3. Local IP Adress ( Optional ) */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) */ + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[0], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + wfdielen += ETH_ALEN; + + /* Coupled Sink Information ATTR */ + /* Type: */ + wfdie[wfdielen++] = WFD_ATTR_COUPLED_SINK_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + /* Value: */ + /* Coupled Sink Status bitmap */ + /* Not coupled/available for Coupling */ + wfdie[wfdielen++] = 0; + /* MAC Addr. */ + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + wfdie[wfdielen++] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; + u32 len = 0, p2pielen = 0; + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20100907 */ + /* According to the P2P Specification, the probe response frame should contain 5 P2P attributes */ + /* 1. P2P Capability */ + /* 2. Extended Listen Timing */ + /* 3. Notice of Absence ( NOA ) ( Only GO needs this ) */ + /* 4. Device Info */ + /* 5. Group Info ( Only GO need this ) */ + + /* P2P Capability ATTR */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + + /* Length: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */ + RTW_PUT_LE16(p2pie + p2pielen, 0x0002); + p2pielen += 2; + + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + + /* Group Capability Bitmap, 1 byte */ + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + p2pie[p2pielen] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) + p2pie[p2pielen] |= P2P_GRPCAP_GROUP_FORMATION; + + p2pielen++; + } else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) { + /* Group Capability Bitmap, 1 byte */ + if (pwdinfo->persistent_supported) + p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; + } + + /* Extended Listen Timing ATTR */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_EX_LISTEN_TIMING; + + /* Length: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); */ + RTW_PUT_LE16(p2pie + p2pielen, 0x0004); + p2pielen += 2; + + /* Value: */ + /* Availability Period */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */ + RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); + p2pielen += 2; + + /* Availability Interval */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); */ + RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); + p2pielen += 2; + + /* Notice of Absence ATTR */ + /* Type: */ + /* Length: */ + /* Value: */ + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* go_add_noa_attr(pwdinfo); */ + } + + /* Device Info ATTR */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + + /* Length: */ + /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ + /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */ + RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Config Method */ + /* This field should be big endian. Noted by P2P specification. */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); */ + RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm); + p2pielen += 2; + + { + /* Primary Device Type */ + /* Category ID */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + /* OUI */ + /* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */ + RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); + p2pielen += 4; + + /* Sub Category ID */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + } + + /* Number of Secondary Device Types */ + p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ + + /* Device Name */ + /* Type: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + /* Length: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */ + RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); + p2pielen += pwdinfo->device_name_len; + + /* Group Info ATTR */ + /* Type: */ + /* Length: */ + /* Value: */ + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen); + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + return len; + +} + +u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr) +{ + u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; + u32 len = 0, p2pielen = 0; + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* Commented by Albert 20110301 */ + /* According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes */ + /* 1. P2P Capability */ + /* 2. Device Info */ + /* 3. Group ID ( When joining an operating P2P Group ) */ + + /* P2P Capability ATTR */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_CAPABILITY; + + /* Length: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); */ + RTW_PUT_LE16(p2pie + p2pielen, 0x0002); + p2pielen += 2; + + /* Value: */ + /* Device Capability Bitmap, 1 byte */ + p2pie[p2pielen++] = DMP_P2P_DEVCAP_SUPPORT; + + /* Group Capability Bitmap, 1 byte */ + if (pwdinfo->persistent_supported) + p2pie[p2pielen++] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[p2pielen++] = DMP_P2P_GRPCAP_SUPPORT; + + /* Device Info ATTR */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_DEVICE_INFO; + + /* Length: */ + /* 21->P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) */ + /* + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); */ + RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + /* P2P Device Address */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN); + p2pielen += ETH_ALEN; + + /* Config Method */ + /* This field should be big endian. Noted by P2P specification. */ + if (pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC) { + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC); + } else { + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY); + } + + p2pielen += 2; + + /* Primary Device Type */ + /* Category ID */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + /* OUI */ + /* *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); */ + RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); + p2pielen += 4; + + /* Sub Category ID */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + + /* Number of Secondary Device Types */ + p2pie[p2pielen++] = 0x00; /* No Secondary Device Type List */ + + /* Device Name */ + /* Type: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); */ + RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + /* Length: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); */ + RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len); + p2pielen += pwdinfo->device_name_len; + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) { + /* Added by Albert 2011/05/19 */ + /* In this case, the pdev_raddr is the device address of the group owner. */ + + /* P2P Group ID ATTR */ + /* Type: */ + p2pie[p2pielen++] = P2P_ATTR_GROUP_ID; + + /* Length: */ + /* *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); */ + RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen); + p2pielen += 2; + + /* Value: */ + _rtw_memcpy(p2pie + p2pielen, pdev_raddr, ETH_ALEN); + p2pielen += ETH_ALEN; + + _rtw_memcpy(p2pie + p2pielen, pssid, ussidlen); + p2pielen += ussidlen; + + } + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + return len; + +} + +u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code) +{ + u8 p2pie[MAX_P2P_IE_LEN] = { 0x00 }; + u32 len = 0, p2pielen = 0; + + /* P2P OUI */ + p2pielen = 0; + p2pie[p2pielen++] = 0x50; + p2pie[p2pielen++] = 0x6F; + p2pie[p2pielen++] = 0x9A; + p2pie[p2pielen++] = 0x09; /* WFA P2P v1.0 */ + + /* According to the P2P Specification, the Association response frame should contain 2 P2P attributes */ + /* 1. Status */ + /* 2. Extended Listen Timing (optional) */ + + /* Status ATTR */ + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code); + + /* Extended Listen Timing ATTR */ + /* Type: */ + /* Length: */ + /* Value: */ + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + return len; + +} + +u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u32 len = 0; + + return len; +} + +u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + u8 *p; + u32 ret = _FALSE; + u8 *p2pie; + u32 p2pielen = 0; + int ssid_len = 0, rate_cnt = 0; + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + if (rate_cnt <= 4) { + int i, g_rate = 0; + + for (i = 0; i < rate_cnt; i++) { + if (((*(p + 2 + i) & 0xff) != 0x02) && + ((*(p + 2 + i) & 0xff) != 0x04) && + ((*(p + 2 + i) & 0xff) != 0x0B) && + ((*(p + 2 + i) & 0xff) != 0x16)) + g_rate = 1; + } + + if (g_rate == 0) { + /* There is no OFDM rate included in SupportedRates IE of this probe request frame */ + /* The driver should response this probe request. */ + return ret; + } + } else { + /* rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. */ + /* We should proceed the following check for this probe request. */ + } + + /* Added comments by Albert 20100906 */ + /* There are several items we should check here. */ + /* 1. This probe request frame must contain the P2P IE. (Done) */ + /* 2. This probe request frame must contain the wildcard SSID. (Done) */ + /* 3. Wildcard BSSID. (Todo) */ + /* 4. Destination Address. ( Done in mgt_dispatcher function ) */ + /* 5. Requested Device Type in WSC IE. (Todo) */ + /* 6. Device ID attribute in P2P IE. (Todo) */ + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + ssid_len &= 0xff; /* Just last 1 byte is valid for ssid len of the probe request */ + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + p2pie = rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen); + if (p2pie) { + if ((p != NULL) && _rtw_memcmp((void *)(p + 2), (void *) pwdinfo->p2p_wildcard_ssid , 7)) { + /* todo: */ + /* Check Requested Device Type attributes in WSC IE. */ + /* Check Device ID attribute in P2P IE */ + + ret = _TRUE; + } else if ((p != NULL) && (ssid_len == 0)) + ret = _TRUE; + } else { + /* non -p2p device */ + } + + } + + return ret; + +} + +u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta) +{ + u8 status_code = P2P_STATUS_SUCCESS; + u8 *pbuf, *pattr_content = NULL; + u32 attr_contentlen = 0; + u16 cap_attr = 0; + unsigned short frame_type, ie_offset = 0; + u8 *ies; + u32 ies_len; + u8 *p2p_ie; + u32 p2p_ielen = 0; + + if (!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + return P2P_STATUS_FAIL_REQUEST_UNABLE; + + frame_type = get_frame_sub_type(pframe); + if (frame_type == WIFI_ASSOCREQ) + ie_offset = _ASOCREQ_IE_OFFSET_; + else /* WIFI_REASSOCREQ */ + ie_offset = _REASOCREQ_IE_OFFSET_; + + ies = pframe + WLAN_HDR_A3_LEN + ie_offset; + ies_len = len - WLAN_HDR_A3_LEN - ie_offset; + + p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen); + + if (!p2p_ie) { + RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__); + status_code = P2P_STATUS_FAIL_INVALID_PARAM; + } else + RTW_INFO("[%s] P2P IE Found!!\n", __FUNCTION__); + + while (p2p_ie) { + /* Check P2P Capability ATTR */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *) &attr_contentlen)) { + RTW_INFO("[%s] Got P2P Capability Attr!!\n", __FUNCTION__); + cap_attr = le16_to_cpu(cap_attr); + psta->dev_cap = cap_attr & 0xff; + } + + /* Check Extended Listen Timing ATTR */ + + /* Check P2P Device Info ATTR */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint *)&attr_contentlen)) { + RTW_INFO("[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__); + pattr_content = pbuf = rtw_zmalloc(attr_contentlen); + if (pattr_content) { + u8 num_of_secdev_type; + u16 dev_name_len; + + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint *)&attr_contentlen); + + _rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);/* P2P Device Address */ + + pattr_content += ETH_ALEN; + + _rtw_memcpy(&psta->config_methods, pattr_content, 2);/* Config Methods */ + psta->config_methods = be16_to_cpu(psta->config_methods); + + pattr_content += 2; + + _rtw_memcpy(psta->primary_dev_type, pattr_content, 8); + + pattr_content += 8; + + num_of_secdev_type = *pattr_content; + pattr_content += 1; + + if (num_of_secdev_type == 0) + psta->num_of_secdev_type = 0; + else { + u32 len; + + psta->num_of_secdev_type = num_of_secdev_type; + + len = (sizeof(psta->secdev_types_list) < (num_of_secdev_type * 8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type * 8); + + _rtw_memcpy(psta->secdev_types_list, pattr_content, len); + + pattr_content += (num_of_secdev_type * 8); + } + + /* dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); */ + psta->dev_name_len = 0; + if (WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16 *)pattr_content)) { + dev_name_len = be16_to_cpu(*(u16 *)(pattr_content + 2)); + + psta->dev_name_len = (sizeof(psta->dev_name) < dev_name_len) ? sizeof(psta->dev_name) : dev_name_len; + + _rtw_memcpy(psta->dev_name, pattr_content + 4, psta->dev_name_len); + } + + rtw_mfree(pbuf, attr_contentlen); + + } + + } + + /* Get the next P2P IE */ + p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); + + } + + return status_code; + +} + +u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + u8 *frame_body; + u8 status, dialogToken; + struct sta_info *psta = NULL; + _adapter *padapter = pwdinfo->padapter; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *p2p_ie; + u32 p2p_ielen = 0; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + dialogToken = frame_body[7]; + status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; + + p2p_ie = rtw_get_p2p_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen); + if (p2p_ie) { + u8 groupid[38] = { 0x00 }; + u8 dev_addr[ETH_ALEN] = { 0x00 }; + u32 attr_contentlen = 0; + + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) { + if (_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) && + _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid + ETH_ALEN, pwdinfo->p2p_group_ssid_len)) { + attr_contentlen = 0; + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) { + _irqL irqL; + _list *phead, *plist; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + /* look up sta asoc_queue */ + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + + plist = get_next(plist); + + if (psta->is_p2p_device && (psta->dev_cap & P2P_DEVCAP_CLIENT_DISCOVERABILITY) && + _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) { + + /* _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ + /* issue GO Discoverability Request */ + issue_group_disc_req(pwdinfo, psta->hwaddr); + /* _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); */ + + status = P2P_STATUS_SUCCESS; + + break; + } else + status = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } else + status = P2P_STATUS_FAIL_INVALID_PARAM; + + } else + status = P2P_STATUS_FAIL_INVALID_PARAM; + + } + + } + + /* issue Device Discoverability Response */ + issue_p2p_devdisc_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken); + + return (status == P2P_STATUS_SUCCESS) ? _TRUE : _FALSE; + +} + +u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + return _TRUE; +} + +u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + u8 *frame_body; + u8 *wpsie; + uint wps_ielen = 0, attr_contentlen = 0; + u16 uconfig_method = 0; + + frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + wpsie = rtw_get_wps_ie(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen); + if (wpsie) { + if (rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , (u8 *) &uconfig_method, &attr_contentlen)) { + uconfig_method = be16_to_cpu(uconfig_method); + switch (uconfig_method) { + case WPS_CM_DISPLYA: { + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3); + break; + } + case WPS_CM_LABEL: { + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3); + break; + } + case WPS_CM_PUSH_BUTTON: { + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3); + break; + } + case WPS_CM_KEYPAD: { + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3); + break; + } + } + issue_p2p_provision_resp(pwdinfo, get_addr2_ptr(pframe), frame_body, uconfig_method); + } + } + RTW_INFO("[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req); + return _TRUE; + +} + +u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe) +{ + + return _TRUE; +} + +u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list) +{ + u8 i = 0, j = 0; + u8 temp = 0; + u8 ch_no = 0; + ch_content += 3; + ch_cnt -= 3; + + while (ch_cnt > 0) { + ch_content += 1; + ch_cnt -= 1; + temp = *ch_content; + for (i = 0 ; i < temp ; i++, j++) + peer_ch_list[j] = *(ch_content + 1 + i); + ch_content += (temp + 1); + ch_cnt -= (temp + 1); + ch_no += temp ; + } + + return ch_no; +} + +u8 rtw_p2p_ch_inclusion(struct mlme_ext_priv *pmlmeext, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) +{ + int i = 0, j = 0, temp = 0; + u8 ch_no = 0; + + for (i = 0; i < peer_ch_num; i++) { + for (j = temp; j < pmlmeext->max_chan_nums; j++) { + if (*(peer_ch_list + i) == pmlmeext->channel_set[j].ChannelNum) { + ch_list_inclusioned[ch_no++] = *(peer_ch_list + i); + temp = j; + break; + } + } + } + + return ch_no; +} + +u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + _adapter *padapter = pwdinfo->padapter; + u8 result = P2P_STATUS_SUCCESS; + u32 p2p_ielen = 0, wps_ielen = 0; + u8 *ies; + u32 ies_len; + u8 *p2p_ie; + u8 *wpsie; + u16 wps_devicepassword_id = 0x0000; + uint wps_devicepassword_id_len = 0; + wpsie = rtw_get_wps_ie(pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen); + if (wpsie) { + /* Commented by Kurt 20120113 */ + /* If some device wants to do p2p handshake without sending prov_disc_req */ + /* We have to get peer_req_cm from here. */ + if (_rtw_memcmp(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3)) { + rtw_get_wps_attr_content(wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8 *) &wps_devicepassword_id, &wps_devicepassword_id_len); + wps_devicepassword_id = be16_to_cpu(wps_devicepassword_id); + + if (wps_devicepassword_id == WPS_DPID_USER_SPEC) + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3); + else if (wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3); + else + _rtw_memcpy(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3); + } + } else { + RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + return result ; + } + + ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); + + if (!p2p_ie) { + RTW_INFO("[%s] P2P IE not Found!!\n", __FUNCTION__); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + } + + while (p2p_ie) { + u8 attr_content = 0x00; + u32 attr_contentlen = 0; + u8 ch_content[100] = { 0x00 }; + uint ch_cnt = 0; + u8 peer_ch_list[100] = { 0x00 }; + u8 peer_ch_num = 0; + u8 ch_list_inclusioned[100] = { 0x00 }; + u8 ch_num_inclusioned = 0; + u16 cap_attr; + u8 listen_ch_attr[5] = { 0x00 }; + + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); + + /* Check P2P Capability ATTR */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) { + cap_attr = le16_to_cpu(cap_attr); + + } + + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) { + RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01); + pwdinfo->peer_intent = attr_content; /* include both intent and tie breaker values. */ + + if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) { + /* Try to match the tie breaker value */ + if (pwdinfo->intent == P2P_MAX_INTENT) { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; + } else { + if (attr_content & 0x01) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + else + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + } else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + else + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* Store the group id information. */ + _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN); + _rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); + } + } + + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) && attr_contentlen == 5) + pwdinfo->nego_req_info.peer_ch = listen_ch_attr[4]; + + RTW_INFO(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch); + + attr_contentlen = 0; + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { + if (attr_contentlen != ETH_ALEN) + _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); + } + + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt)) { + peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list); + ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + + if (ch_num_inclusioned == 0) { + RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); + result = P2P_STATUS_FAIL_NO_COMMON_CH; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel, + ch_list_inclusioned, ch_num_inclusioned)) { + { + u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; + attr_contentlen = 0; + + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) + peer_operating_ch = operatingch_info[4]; + + if (rtw_p2p_is_channel_list_ok(peer_operating_ch, + ch_list_inclusioned, ch_num_inclusioned)) { + /** + * Change our operating channel as peer's for compatibility. + */ + pwdinfo->operating_channel = peer_operating_ch; + RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); + } else { + /* Take first channel of ch_list_inclusioned as operating channel */ + pwdinfo->operating_channel = ch_list_inclusioned[0]; + RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); + } + } + + } + } + } + + /* Get the next P2P IE */ + p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); + } + + if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) { + result = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY); + return result; + } + + rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__); + + return result ; +} + +u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + _adapter *padapter = pwdinfo->padapter; + u8 result = P2P_STATUS_SUCCESS; + u32 p2p_ielen, wps_ielen; + u8 *ies; + u32 ies_len; + u8 *p2p_ie; + + ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + /* Be able to know which one is the P2P GO and which one is P2P client. */ + + if (rtw_get_wps_ie(ies, ies_len, NULL, &wps_ielen)) { + + } else { + RTW_INFO("[%s] WPS IE not Found!!\n", __FUNCTION__); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + } + + p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); + if (!p2p_ie) { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + } else { + + u8 attr_content = 0x00; + u32 attr_contentlen = 0; + u8 operatingch_info[5] = { 0x00 }; + uint ch_cnt = 0; + u8 ch_content[100] = { 0x00 }; + u8 groupid[38]; + u16 cap_attr; + u8 peer_ch_list[100] = { 0x00 }; + u8 peer_ch_num = 0; + u8 ch_list_inclusioned[100] = { 0x00 }; + u8 ch_num_inclusioned = 0; + + while (p2p_ie) { /* Found the P2P IE. */ + + /* Check P2P Capability ATTR */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8 *)&cap_attr, (uint *)&attr_contentlen)) { + cap_attr = le16_to_cpu(cap_attr); + } + + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); + if (attr_contentlen == 1) { + RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content); + if (attr_content == P2P_STATUS_SUCCESS) { + /* Do nothing. */ + } else { + if (P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content) + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY); + else + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + result = attr_content; + break; + } + } + + /* Try to get the peer's interface address */ + attr_contentlen = 0; + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INTENDED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen)) { + if (attr_contentlen != ETH_ALEN) + _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); + } + + /* Try to get the peer's intent and tie breaker value. */ + attr_content = 0x00; + attr_contentlen = 0; + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen)) { + RTW_INFO("[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01); + pwdinfo->peer_intent = attr_content; /* include both intent and tie breaker values. */ + + if (pwdinfo->intent == (pwdinfo->peer_intent >> 1)) { + /* Try to match the tie breaker value */ + if (pwdinfo->intent == P2P_MAX_INTENT) { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + } else { + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + if (attr_content & 0x01) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + else + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + } else if (pwdinfo->intent > (pwdinfo->peer_intent >> 1)) { + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } else { + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + /* Store the group id information. */ + _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN); + _rtw_memcpy(pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen); + + } + } + + /* Try to get the operation channel information */ + + attr_contentlen = 0; + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) { + RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]); + pwdinfo->peer_operating_ch = operatingch_info[4]; + } + + /* Try to get the channel list information */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len)) { + RTW_INFO("[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len); + + peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list); + ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + + if (ch_num_inclusioned == 0) { + RTW_INFO("[%s] No common channel in channel list!\n", __FUNCTION__); + result = P2P_STATUS_FAIL_NO_COMMON_CH; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + if (!rtw_p2p_is_channel_list_ok(pwdinfo->operating_channel, + ch_list_inclusioned, ch_num_inclusioned)) { + { + u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; + attr_contentlen = 0; + + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) + peer_operating_ch = operatingch_info[4]; + + if (rtw_p2p_is_channel_list_ok(peer_operating_ch, + ch_list_inclusioned, ch_num_inclusioned)) { + /** + * Change our operating channel as peer's for compatibility. + */ + pwdinfo->operating_channel = peer_operating_ch; + RTW_INFO("[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); + } else { + /* Take first channel of ch_list_inclusioned as operating channel */ + pwdinfo->operating_channel = ch_list_inclusioned[0]; + RTW_INFO("[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); + } + } + + } + } + + } else + RTW_INFO("[%s] channel list attribute not found!\n", __FUNCTION__); + + /* Try to get the group id information if peer is GO */ + attr_contentlen = 0; + _rtw_memset(groupid, 0x00, 38); + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) { + _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN); + _rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN); + } + + /* Get the next P2P IE */ + p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); + } + + } + + rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__); + + return result ; + +} + +u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + _adapter *padapter = pwdinfo->padapter; + u8 *ies; + u32 ies_len; + u8 *p2p_ie; + u32 p2p_ielen = 0; + u8 result = P2P_STATUS_SUCCESS; + ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); + while (p2p_ie) { /* Found the P2P IE. */ + u8 attr_content = 0x00, operatingch_info[5] = { 0x00 }; + u8 groupid[38] = { 0x00 }; + u32 attr_contentlen = 0; + + pwdinfo->negotiation_dialog_token = 1; + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); + if (attr_contentlen == 1) { + RTW_INFO("[%s] Status = %d\n", __FUNCTION__, attr_content); + result = attr_content; + + if (attr_content == P2P_STATUS_SUCCESS) { + + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + + /* Commented by Albert 20100911 */ + /* Todo: Need to handle the case which both Intents are the same. */ + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + if ((pwdinfo->intent) > (pwdinfo->peer_intent >> 1)) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + else if ((pwdinfo->intent) < (pwdinfo->peer_intent >> 1)) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + else { + /* Have to compare the Tie Breaker */ + if (pwdinfo->peer_intent & 0x01) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + else + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + + } else { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + } + + /* Try to get the group id information */ + attr_contentlen = 0; + _rtw_memset(groupid, 0x00, 38); + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) { + RTW_INFO("[%s] Ssid = %s, ssidlen = %zu\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN])); + _rtw_memcpy(pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN); + _rtw_memcpy(pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN); + } + + attr_contentlen = 0; + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) { + RTW_INFO("[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4]); + pwdinfo->peer_operating_ch = operatingch_info[4]; + } + + /* Get the next P2P IE */ + p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); + + } + + return result ; +} + +u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + u8 *frame_body; + u8 dialogToken = 0; + u8 status = P2P_STATUS_SUCCESS; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + dialogToken = frame_body[6]; + + /* todo: check NoA attribute */ + + issue_p2p_presence_resp(pwdinfo, get_addr2_ptr(pframe), status, dialogToken); + + return _TRUE; +} + +void find_phase_handler(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + NDIS_802_11_SSID ssid; + _irqL irqL; + u8 _status = 0; + + _rtw_memset((unsigned char *)&ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); + ssid.SsidLength = P2P_WILDCARD_SSID_LEN; + + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + _status = rtw_sitesurvey_cmd(padapter, &ssid, 1, NULL, 0); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +} + +void p2p_concurrent_handler(_adapter *padapter); + +void restore_p2p_state_handler(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + + + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) { + /* In the P2P client mode, the driver should not switch back to its listen channel */ + /* because this P2P client should stay at the operating channel of P2P GO. */ + set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } +} + +void pre_tx_invitereq_handler(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + u8 val8 = 1; + + set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter, NULL); + _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + +} + +void pre_tx_provdisc_handler(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + u8 val8 = 1; + + set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter, NULL); + _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + +} + +void pre_tx_negoreq_handler(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + u8 val8 = 1; + + set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter , NULL); + /* WIN Phone only accept unicast probe request when nego back */ + issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr); + _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + +} + + + +s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf) +{ + int ret = H2C_SUCCESS; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + switch (intCmdType) { + case P2P_FIND_PHASE_WK: + find_phase_handler(padapter); + break; + + case P2P_RESTORE_STATE_WK: + restore_p2p_state_handler(padapter); + break; + + case P2P_PRE_TX_PROVDISC_PROCESS_WK: + pre_tx_provdisc_handler(padapter); + break; + + case P2P_PRE_TX_INVITEREQ_PROCESS_WK: + pre_tx_invitereq_handler(padapter); + break; + + case P2P_PRE_TX_NEGOREQ_PROCESS_WK: + pre_tx_negoreq_handler(padapter); + break; + + + + default: + rtw_warn_on(1); + break; + } + + return ret; +} + +int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) +{ + int ret = _TRUE; + u8 *ies; + u32 ies_len; + u8 *p2p_ie; + u32 p2p_ielen = 0; + u8 p2p_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */ + u32 attr_contentlen = 0; + + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (IELength <= _BEACON_IE_OFFSET_) + return ret; + + ies = IEs + _BEACON_IE_OFFSET_; + ies_len = IELength - _BEACON_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); + + while (p2p_ie) { + /* Get P2P Manageability IE. */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_MANAGEABILITY, p2p_attr, &attr_contentlen)) { + if ((p2p_attr[0] & (BIT(0) | BIT(1))) == 0x01) + ret = _FALSE; + break; + } + /* Get the next P2P IE */ + p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); + } + + return ret; +} + +void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) +{ + u8 *ies; + u32 ies_len; + u8 *p2p_ie; + u32 p2p_ielen = 0; + u8 noa_attr[MAX_P2P_IE_LEN] = { 0x00 };/* NoA length should be n*(13) + 2 */ + u32 attr_contentlen = 0; + + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 find_p2p = _FALSE, find_p2p_ps = _FALSE; + u8 noa_offset, noa_num, noa_index; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + if (IELength <= _BEACON_IE_OFFSET_) + return; + + ies = IEs + _BEACON_IE_OFFSET_; + ies_len = IELength - _BEACON_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &p2p_ielen); + + while (p2p_ie) { + find_p2p = _TRUE; + /* Get Notice of Absence IE. */ + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_NOA, noa_attr, &attr_contentlen)) { + find_p2p_ps = _TRUE; + noa_index = noa_attr[0]; + + if ((pwdinfo->p2p_ps_mode == P2P_PS_NONE) || + (noa_index != pwdinfo->noa_index)) { /* if index change, driver should reconfigure related setting. */ + pwdinfo->noa_index = noa_index; + pwdinfo->opp_ps = noa_attr[1] >> 7; + pwdinfo->ctwindow = noa_attr[1] & 0x7F; + + noa_offset = 2; + noa_num = 0; + /* NoA length should be n*(13) + 2 */ + if (attr_contentlen > 2) { + while (noa_offset < attr_contentlen) { + /* _rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); */ + pwdinfo->noa_count[noa_num] = noa_attr[noa_offset]; + noa_offset += 1; + + _rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4); + noa_offset += 4; + + _rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4); + noa_offset += 4; + + _rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4); + noa_offset += 4; + + noa_num++; + } + } + pwdinfo->noa_num = noa_num; + + if (pwdinfo->opp_ps == 1) { + pwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW; + /* driver should wait LPS for entering CTWindow */ + if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) + p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); + } else if (pwdinfo->noa_num > 0) { + pwdinfo->p2p_ps_mode = P2P_PS_NOA; + p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); + } else if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) + p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); + } + + break; /* find target, just break. */ + } + + /* Get the next P2P IE */ + p2p_ie = rtw_get_p2p_ie(p2p_ie + p2p_ielen, ies_len - (p2p_ie - ies + p2p_ielen), NULL, &p2p_ielen); + + } + + if (find_p2p == _TRUE) { + if ((pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE)) + p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); + } + +} + +void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + /* Pre action for p2p state */ + switch (p2p_ps_state) { + case P2P_PS_DISABLE: + pwdinfo->p2p_ps_state = p2p_ps_state; + + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); + + pwdinfo->noa_index = 0; + pwdinfo->ctwindow = 0; + pwdinfo->opp_ps = 0; + pwdinfo->noa_num = 0; + pwdinfo->p2p_ps_mode = P2P_PS_NONE; + if (pwrpriv->bFwCurrentInPSMode == _TRUE) { + if (pwrpriv->smart_ps == 0) { + pwrpriv->smart_ps = 2; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); + } + } + break; + case P2P_PS_ENABLE: + if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { + pwdinfo->p2p_ps_state = p2p_ps_state; + + if (pwdinfo->ctwindow > 0) { + if (pwrpriv->smart_ps != 0) { + pwrpriv->smart_ps = 0; + RTW_INFO("%s(): Enter CTW, change SmartPS\n", __FUNCTION__); + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); + } + } + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); + } + break; + case P2P_PS_SCAN: + case P2P_PS_SCAN_DONE: + case P2P_PS_ALLSTASLEEP: + if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { + pwdinfo->p2p_ps_state = p2p_ps_state; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); + } + break; + default: + break; + } + +} + +u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + ) + return res; + + if (enqueue) { + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID; + pdrvextra_cmd_parm->type = p2p_ps_state; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } else + p2p_ps_wk_hdl(padapter, p2p_ps_state); + +exit: + + return res; + +} + +static void reset_ch_sitesurvey_timer_process(void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + RTW_INFO("[%s] In\n", __FUNCTION__); + /* Reset the operation channel information */ + pwdinfo->rx_invitereq_info.operation_ch[0] = 0; + pwdinfo->rx_invitereq_info.operation_ch[1] = 0; + pwdinfo->rx_invitereq_info.operation_ch[2] = 0; + pwdinfo->rx_invitereq_info.operation_ch[3] = 0; + pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; +} + +static void reset_ch_sitesurvey_timer_process2(void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + RTW_INFO("[%s] In\n", __FUNCTION__); + /* Reset the operation channel information */ + pwdinfo->p2p_info.operation_ch[0] = 0; + pwdinfo->p2p_info.operation_ch[1] = 0; + pwdinfo->p2p_info.operation_ch[2] = 0; + pwdinfo->p2p_info.operation_ch[3] = 0; + pwdinfo->p2p_info.scan_op_ch_only = 0; +} + +static void restore_p2p_state_timer_process(void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + p2p_protocol_wk_cmd(adapter, P2P_RESTORE_STATE_WK); +} + +static void pre_tx_scan_timer_process(void *FunctionContext) +{ + _adapter *adapter = (_adapter *) FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u8 _status = 0; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) { + if (_TRUE == pwdinfo->tx_prov_disc_info.benable) { /* the provision discovery request frame is trigger to send or not */ + p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK); + /* issue_probereq_p2p(adapter, NULL); */ + /* _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); */ + } + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) { + if (_TRUE == pwdinfo->nego_req_info.benable) + p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK); + } else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ)) { + if (_TRUE == pwdinfo->invitereq_info.benable) + p2p_protocol_wk_cmd(adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK); + } else + RTW_INFO("[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo)); + + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +static void find_phase_timer_process(void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + adapter->wdinfo.find_phase_state_exchange_cnt++; + + p2p_protocol_wk_cmd(adapter, P2P_FIND_PHASE_WK); +} + + +void reset_global_wifidirect_info(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo; + + pwdinfo = &padapter->wdinfo; + pwdinfo->persistent_supported = 0; + pwdinfo->session_available = _TRUE; + rtw_tdls_wfd_enable(padapter, 0); + pwdinfo->wfd_tdls_weaksec = _TRUE; +} + +int rtw_init_wifi_display_info(_adapter *padapter) +{ + int res = _SUCCESS; + struct wifi_display_info *pwfd_info = &padapter->wfd_info; + + /* Used in P2P and TDLS */ + pwfd_info->init_rtsp_ctrlport = 554; + pwfd_info->rtsp_ctrlport = pwfd_info->init_rtsp_ctrlport; /* set non-zero value for legacy wfd */ + pwfd_info->tdls_rtsp_ctrlport = 0; + pwfd_info->peer_rtsp_ctrlport = 0; /* Reset to 0 */ + pwfd_info->wfd_enable = _FALSE; + pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK; + pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY; + + /* Used in P2P */ + pwfd_info->peer_session_avail = _TRUE; + pwfd_info->wfd_pc = _FALSE; + + /* Used in TDLS */ + _rtw_memset(pwfd_info->ip_address, 0x00, 4); + _rtw_memset(pwfd_info->peer_ip_address, 0x00, 4); + return res; + +} + +inline void rtw_wfd_enable(_adapter *adapter, bool on) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + if (on) { + wfdinfo->rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport; + wfdinfo->wfd_enable = _TRUE; + + } else { + wfdinfo->wfd_enable = _FALSE; + wfdinfo->rtsp_ctrlport = 0; + } +} + +inline void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + wfdinfo->init_rtsp_ctrlport = port; + if (wfdinfo->wfd_enable == _TRUE) + wfdinfo->rtsp_ctrlport = port; + if (adapter->wdinfo.wfd_tdls_enable == 1) + wfdinfo->tdls_rtsp_ctrlport = port; +} + +inline void rtw_tdls_wfd_enable(_adapter *adapter, bool on) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + if (on) { + wfdinfo->tdls_rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport; + adapter->wdinfo.wfd_tdls_enable = 1; + + } else { + adapter->wdinfo.wfd_tdls_enable = 0; + wfdinfo->tdls_rtsp_ctrlport = 0; + } +} + +u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_beacon_wfd_ie(wdinfo, pbuf); + +exit: + return len; +} + +u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_probe_req_wfd_ie(wdinfo, pbuf); + +exit: + return len; +} + +u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_probe_resp_wfd_ie(wdinfo, pbuf, 0); + +exit: + return len; +} + +u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_assoc_req_wfd_ie(wdinfo, pbuf); + +exit: + return len; +} + +u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_assoc_resp_wfd_ie(wdinfo, pbuf); + +exit: + return len; +} + + +void rtw_init_wifidirect_timers(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + rtw_init_timer(&pwdinfo->find_phase_timer, padapter, find_phase_timer_process, padapter); + rtw_init_timer(&pwdinfo->restore_p2p_state_timer, padapter, restore_p2p_state_timer_process, padapter); + rtw_init_timer(&pwdinfo->pre_tx_scan_timer, padapter, pre_tx_scan_timer_process, padapter); + rtw_init_timer(&pwdinfo->reset_ch_sitesurvey, padapter, reset_ch_sitesurvey_timer_process, padapter); + rtw_init_timer(&pwdinfo->reset_ch_sitesurvey2, padapter, reset_ch_sitesurvey_timer_process2, padapter); +} + +void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + /*init device&interface address */ + if (dev_addr) + _rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN); + if (iface_addr) + _rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN); +} + +void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role) +{ + struct wifidirect_info *pwdinfo; + struct wifi_display_info *pwfd_info = &padapter->wfd_info; + u8 union_ch = 0; + pwdinfo = &padapter->wdinfo; + + pwdinfo->padapter = padapter; + + /* 1, 6, 11 are the social channel defined in the WiFi Direct specification. */ + pwdinfo->social_chan[0] = 1; + pwdinfo->social_chan[1] = 6; + pwdinfo->social_chan[2] = 11; + pwdinfo->social_chan[3] = 0; /* channel 0 for scanning ending in site survey function. */ + + if (role != P2P_ROLE_DISABLE + && pwdinfo->driver_interface != DRIVER_CFG80211 + ) { + { + /* Use the channel 11 as the listen channel */ + pwdinfo->listen_channel = 11; + } + } + + if (role == P2P_ROLE_DEVICE) { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); + + pwdinfo->intent = 1; + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN); + } else if (role == P2P_ROLE_CLIENT) { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + pwdinfo->intent = 1; + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + } else if (role == P2P_ROLE_GO) { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + pwdinfo->intent = 15; + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + } + + /* Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) */ + pwdinfo->support_rate[0] = 0x8c; /* 6(B) */ + pwdinfo->support_rate[1] = 0x92; /* 9(B) */ + pwdinfo->support_rate[2] = 0x18; /* 12 */ + pwdinfo->support_rate[3] = 0x24; /* 18 */ + pwdinfo->support_rate[4] = 0x30; /* 24 */ + pwdinfo->support_rate[5] = 0x48; /* 36 */ + pwdinfo->support_rate[6] = 0x60; /* 48 */ + pwdinfo->support_rate[7] = 0x6c; /* 54 */ + + _rtw_memcpy((void *) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7); + + _rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN); + pwdinfo->device_name_len = 0; + + _rtw_memset(&pwdinfo->invitereq_info, 0x00, sizeof(struct tx_invite_req_info)); + pwdinfo->invitereq_info.token = 3; /* Token used for P2P invitation request frame. */ + + _rtw_memset(&pwdinfo->inviteresp_info, 0x00, sizeof(struct tx_invite_resp_info)); + pwdinfo->inviteresp_info.token = 0; + + pwdinfo->profileindex = 0; + _rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM); + + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); + + pwdinfo->listen_dwell = (u8)((rtw_get_current_time() % 3) + 1); + /* RTW_INFO( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); */ + + _rtw_memset(&pwdinfo->tx_prov_disc_info, 0x00, sizeof(struct tx_provdisc_req_info)); + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE; + + _rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info)); + + pwdinfo->device_password_id_for_nego = WPS_DPID_PBC; + pwdinfo->negotiation_dialog_token = 1; + + _rtw_memset(pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN); + pwdinfo->nego_ssidlen = 0; + + pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; + pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC; + pwdinfo->wfd_info = pwfd_info; + pwdinfo->channel_list_attr_len = 0; + _rtw_memset(pwdinfo->channel_list_attr, 0x00, 100); + + _rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4); + _rtw_memset(pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3); + _rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info)); + + /* Commented by Kurt 20130319 + * For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. */ + pwdinfo->driver_interface = DRIVER_WEXT; + + pwdinfo->wfd_tdls_enable = 0; + _rtw_memset(pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN); + _rtw_memset(pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN); + + pwdinfo->rx_invitereq_info.operation_ch[0] = 0; + pwdinfo->rx_invitereq_info.operation_ch[1] = 0; /* Used to indicate the scan end in site survey function */ + pwdinfo->rx_invitereq_info.operation_ch[2] = 0; + pwdinfo->rx_invitereq_info.operation_ch[3] = 0; + pwdinfo->rx_invitereq_info.operation_ch[4] = 0; + pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; + pwdinfo->p2p_info.operation_ch[0] = 0; + pwdinfo->p2p_info.operation_ch[1] = 0; /* Used to indicate the scan end in site survey function */ + pwdinfo->p2p_info.operation_ch[2] = 0; + pwdinfo->p2p_info.operation_ch[3] = 0; + pwdinfo->p2p_info.operation_ch[4] = 0; + pwdinfo->p2p_info.scan_op_ch_only = 0; +} + + +int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) +{ + int ret = _SUCCESS; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT || role == P2P_ROLE_GO) { + u8 channel, ch_offset; + u16 bwmode; + + + /* leave IPS/Autosuspend */ + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = _FAIL; + goto exit; + } + + /* Added by Albert 2011/03/22 */ + /* In the P2P mode, the driver should not support the b mode. */ + /* So, the Tx packet shouldn't use the CCK rate */ + update_tx_basic_rate(padapter, WIRELESS_11AGN); + + /* Enable P2P function */ + init_wifidirect_info(padapter, role); + + + rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _TRUE); + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _TRUE); + + } else if (role == P2P_ROLE_DISABLE) { + + + pwdinfo->listen_channel = 0; + + /* Disable P2P function */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + _cancel_timer_ex(&pwdinfo->find_phase_timer); + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + _cancel_timer_ex(&pwdinfo->pre_tx_scan_timer); + _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey); + _cancel_timer_ex(&pwdinfo->reset_ch_sitesurvey2); + reset_ch_sitesurvey_timer_process(padapter); + reset_ch_sitesurvey_timer_process2(padapter); + rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE); + _rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info)); + + /* Remove profiles in wifidirect_info structure. */ + _rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM); + pwdinfo->profileindex = 0; + } + + rtw_hal_set_odm_var(padapter, HAL_ODM_P2P_STATE, NULL, _FALSE); + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _FALSE); + + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = _FAIL; + goto exit; + } + + /* Restore to initial setting. */ + update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode); + + /* For WiDi purpose. */ + pwdinfo->driver_interface = DRIVER_WEXT; + + } + +exit: + return ret; +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_pwrctrl.c b/drivers/staging/rtl8821ce/core/rtw_pwrctrl.c new file mode 100644 index 000000000000..1fae2edac37b --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_pwrctrl.c @@ -0,0 +1,1034 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_PWRCTRL_C_ + +#include <drv_types.h> +#include <hal_data.h> +#include <hal_com_h2c.h> + +int rtw_fw_ps_state(PADAPTER padapter) +{ + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + int ret = _FAIL, dont_care = 0; + u16 fw_ps_state = 0; + u32 start_time; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct registry_priv *registry_par = &padapter->registrypriv; + + if (registry_par->check_fw_ps != 1) + return _SUCCESS; + + _enter_pwrlock(&pwrpriv->check_32k_lock); + + if (RTW_CANNOT_RUN(padapter)) { + RTW_INFO("%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\n", __func__ + , rtw_is_surprise_removed(padapter) ? "True" : "False" + , rtw_get_hw_init_completed(padapter) + , rtw_is_drv_stopped(padapter) ? "True" : "False"); + goto exit_fw_ps_state; + } + rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care); + { + /* 4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. */ + /* Else, hw will keep in active mode. */ + /* debug info: */ + /* 0x88[7] = 32kpermission, */ + /* 0x88[6:0] = current_ps_state */ + /* 0x89[7:0] = last_rpwm */ + + rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state); + + if ((fw_ps_state & 0x80) == 0) + ret = _SUCCESS; + else { + pdbgpriv->dbg_poll_fail_cnt++; + RTW_INFO("%s: fw_ps_state=%04x\n", __FUNCTION__, fw_ps_state); + } + } + +exit_fw_ps_state: + _exit_pwrlock(&pwrpriv->check_32k_lock); + return ret; +} + +void _ips_enter(_adapter *padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + pwrpriv->bips_processing = _TRUE; + + /* syn ips_mode with request */ + pwrpriv->ips_mode = pwrpriv->ips_mode_req; + + pwrpriv->ips_enter_cnts++; + RTW_INFO("==>ips_enter cnts:%d\n", pwrpriv->ips_enter_cnts); + + if (rf_off == pwrpriv->change_rfpwrstate) { + pwrpriv->bpower_saving = _TRUE; + RTW_PRINT("nolinked power save enter\n"); + + if (pwrpriv->ips_mode == IPS_LEVEL_2) + pwrpriv->bkeepfwalive = _TRUE; + + rtw_ips_pwr_down(padapter); + pwrpriv->rf_pwrstate = rf_off; + } + pwrpriv->bips_processing = _FALSE; + +} + +void ips_enter(_adapter *padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req); + + _enter_pwrlock(&pwrpriv->lock); + _ips_enter(padapter); + _exit_pwrlock(&pwrpriv->lock); +} + +int _ips_leave(_adapter *padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + int result = _SUCCESS; + + if ((pwrpriv->rf_pwrstate == rf_off) && (!pwrpriv->bips_processing)) { + pwrpriv->bips_processing = _TRUE; + pwrpriv->change_rfpwrstate = rf_on; + pwrpriv->ips_leave_cnts++; + RTW_INFO("==>ips_leave cnts:%d\n", pwrpriv->ips_leave_cnts); + + result = rtw_ips_pwr_up(padapter); + if (result == _SUCCESS) + pwrpriv->rf_pwrstate = rf_on; + RTW_PRINT("nolinked power save leave\n"); + + RTW_INFO("==> ips_leave.....LED(0x%08x)...\n", rtw_read32(padapter, 0x4c)); + pwrpriv->bips_processing = _FALSE; + + pwrpriv->bkeepfwalive = _FALSE; + pwrpriv->bpower_saving = _FALSE; + } + + return result; +} + +int ips_leave(_adapter *padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + int ret; + + if (!is_primary_adapter(padapter)) + return _SUCCESS; + + _enter_pwrlock(&pwrpriv->lock); + ret = _ips_leave(padapter); + _exit_pwrlock(&pwrpriv->lock); + + if (_SUCCESS == ret) + odm_dm_reset(&GET_HAL_DATA(padapter)->odmpriv); + + if (_SUCCESS == ret) + rtw_btcoex_IpsNotify(padapter, IPS_NONE); + + return ret; +} + + + +bool rtw_pwr_unassociated_idle(_adapter *adapter) +{ + u8 i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct xmit_priv *pxmit_priv = &adapter->xmitpriv; + struct mlme_priv *pmlmepriv; + struct wifidirect_info *pwdinfo; + + bool ret = _FALSE; + + if (adapter_to_pwrctl(adapter)->bpower_saving == _TRUE) { + /* RTW_INFO("%s: already in LPS or IPS mode\n", __func__); */ + goto exit; + } + + if (adapter_to_pwrctl(adapter)->ips_deny_time >= rtw_get_current_time()) { + /* RTW_INFO("%s ips_deny_time\n", __func__); */ + goto exit; + } + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + pmlmepriv = &(iface->mlmepriv); + pwdinfo = &(iface->wdinfo); + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE | WIFI_SITE_MONITOR) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) + || check_fwstate(pmlmepriv, WIFI_AP_STATE) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) + ) + goto exit; + + } + } + + if (adapter->registrypriv.mp_mode == 1) + goto exit; + + + if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF || + pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) { + RTW_PRINT("There are some pkts to transmit\n"); + RTW_PRINT("free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n", + pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt); + goto exit; + } + + ret = _TRUE; + +exit: + return ret; +} + +/* + * ATTENTION: + * rtw_ps_processor() doesn't handle LPS. + */ +void rtw_ps_processor(_adapter *padapter) +{ + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + u32 ps_deny = 0; + + _enter_pwrlock(&adapter_to_pwrctl(padapter)->lock); + ps_deny = rtw_ps_deny_get(padapter); + _exit_pwrlock(&adapter_to_pwrctl(padapter)->lock); + if (ps_deny != 0) { + RTW_INFO(FUNC_ADPT_FMT ": ps_deny=0x%08X, skip power save!\n", + FUNC_ADPT_ARG(padapter), ps_deny); + goto exit; + } + + if (pwrpriv->bInSuspend == _TRUE) { /* system suspend or autosuspend */ + pdbgpriv->dbg_ps_insuspend_cnt++; + RTW_INFO("%s, pwrpriv->bInSuspend == _TRUE ignore this process\n", __FUNCTION__); + return; + } + + pwrpriv->ps_processing = _TRUE; + + + if (pwrpriv->ips_mode_req == IPS_NONE) + goto exit; + + if (rtw_pwr_unassociated_idle(padapter) == _FALSE) + goto exit; + + if ((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts % 4) == 0)) { + RTW_INFO("==>%s .fw_state(%x)\n", __FUNCTION__, get_fwstate(pmlmepriv)); + pwrpriv->change_rfpwrstate = rf_off; + { + + ips_enter(padapter); + } + } +exit: +#ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(pwrpriv); +#endif + pwrpriv->ps_processing = _FALSE; + return; +} + +void pwr_state_check_handler(void *ctx) +{ + _adapter *padapter = (_adapter *)ctx; + rtw_ps_cmd(padapter); +} + +void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) +{ +} + +/* + * Description: + * This function MUST be called under power lock protect + * + * Parameters + * padapter + * pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4 + * + */ +void rtw_set_rpwm(PADAPTER padapter, u8 pslv) +{ + u8 rpwm; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + pslv = PS_STATE(pslv); + + { + if ((pwrpriv->rpwm == pslv) + || (pwrpriv->lps_level == LPS_NORMAL) + ) { + return; + } + } + + if (rtw_is_surprise_removed(padapter) || + (!rtw_is_hw_init_completed(padapter))) { + + pwrpriv->cpwm = PS_STATE_S4; + + return; + } + + if (rtw_is_drv_stopped(padapter)) + if (pslv < PS_STATE_S2) + return; + + rpwm = pslv | pwrpriv->tog; + + pwrpriv->rpwm = pslv; + + + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); + + pwrpriv->tog += 0x80; + + { + pwrpriv->cpwm = pslv; + } + +} + +u8 PS_RDY_CHECK(_adapter *padapter) +{ + u32 curr_time, delta_time; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (_TRUE == pwrpriv->bInSuspend) + return _FALSE; + + curr_time = rtw_get_current_time(); + + delta_time = curr_time - pwrpriv->DelayLPSLastTimeStamp; + + if (delta_time < LPS_DELAY_TIME) + return _FALSE; + + if (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING | WIFI_UNDER_WPS) + || check_fwstate(pmlmepriv, WIFI_AP_STATE) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE) + || rtw_is_scan_deny(padapter) + ) + return _FALSE; + + if ((padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE)) { + RTW_INFO("Group handshake still in progress !!!\n"); + return _FALSE; + } + + + return _TRUE; +} + +#if defined(CONFIG_FWLPS_IN_IPS) +void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + int cnt = 0; + u32 start_time; + u8 val8 = 0; + u8 cpwm_orig = 0, cpwm_now = 0; + u8 parm[H2C_INACTIVE_PS_LEN] = {0}; + + if (padapter->netif_up == _FALSE) { + RTW_INFO("%s: ERROR, netif is down\n", __func__); + return; + } + + /* u8 cmd_param; */ /* BIT0:enable, BIT1:NoConnect32k */ + if (enable) { + rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req); + /* Enter IPS */ + RTW_INFO("%s: issue H2C to FW when entering IPS\n", __func__); + + parm[0] = 0x1;/* suggest by Isaac.Hsu*/ + + rtw_hal_fill_h2c_cmd(padapter, /* H2C_FWLPS_IN_IPS_, */ + H2C_INACTIVE_PS_, + H2C_INACTIVE_PS_LEN, parm); + /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. */ + do { + val8 = rtw_read8(padapter, REG_HMETFR); + cnt++; + RTW_INFO("%s polling REG_HMETFR=0x%x, cnt=%d\n", + __func__, val8, cnt); + rtw_mdelay_os(10); + } while (cnt < 100 && (val8 != 0)); + + } else { + /* Leave IPS */ + RTW_INFO("%s: Leaving IPS in FWLPS state\n", __func__); + + parm[0] = 0x0; + parm[1] = 0x0; + parm[2] = 0x0; + rtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_, + H2C_INACTIVE_PS_LEN, parm); + rtw_btcoex_IpsNotify(padapter, IPS_NONE); + } +} +#endif /* CONFIG_PNO_SUPPORT */ + +void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (ps_mode > PM_Card_Disable) { + return; + } + + if (pwrpriv->pwr_mode == ps_mode) { + if (PS_MODE_ACTIVE == ps_mode) + return; + + } + + + + + /* if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) */ + if (ps_mode == PS_MODE_ACTIVE) { + if (1 + && (((rtw_btcoex_IsBtControlLps(padapter) == _FALSE) + && (pwdinfo->opp_ps == 0) + ) + || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + && (rtw_btcoex_IsLpsOn(padapter) == _FALSE)) + ) + ) { + RTW_INFO(FUNC_ADPT_FMT" Leave 802.11 power save - %s\n", + FUNC_ADPT_ARG(padapter), msg); + + if (pwrpriv->lps_leave_cnts < UINT_MAX) + pwrpriv->lps_leave_cnts++; + else + pwrpriv->lps_leave_cnts = 0; + + pwrpriv->pwr_mode = ps_mode; + rtw_set_rpwm(padapter, PS_STATE_S4); + + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + + + + pwrpriv->bFwCurrentInPSMode = _FALSE; + + rtw_btcoex_LpsNotify(padapter, ps_mode); + } + } else { + if ((PS_RDY_CHECK(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) + || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + && (rtw_btcoex_IsLpsOn(padapter) == _TRUE)) + ) { + u8 pslv; + + RTW_INFO(FUNC_ADPT_FMT" Enter 802.11 power save - %s\n", + FUNC_ADPT_ARG(padapter), msg); + + if (pwrpriv->lps_enter_cnts < UINT_MAX) + pwrpriv->lps_enter_cnts++; + else + pwrpriv->lps_enter_cnts = 0; + + rtw_btcoex_LpsNotify(padapter, ps_mode); + + + pwrpriv->bFwCurrentInPSMode = _TRUE; + pwrpriv->pwr_mode = ps_mode; + pwrpriv->smart_ps = smart_ps; + pwrpriv->bcn_ant_mode = bcn_ant_mode; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + + /* Set CTWindow after LPS */ + if (pwdinfo->opp_ps == 1) + p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0); + + pslv = PS_STATE_S2; + + if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) + && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) { + u8 val8; + + val8 = rtw_btcoex_LpsVal(padapter); + if (val8 & BIT(4)) + pslv = PS_STATE_S2; + + } + + rtw_set_rpwm(padapter, pslv); + } + } + + +} + +/* + * Return: + * 0: Leave OK + * -1: Timeout + * -2: Other error + */ +s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms) +{ + u32 start_time; + u8 bAwake = _FALSE; + s32 err = 0; + + start_time = rtw_get_current_time(); + while (1) { + rtw_hal_get_hwreg(padapter, HW_VAR_FWLPS_RF_ON, &bAwake); + if (_TRUE == bAwake) + break; + + if (rtw_is_surprise_removed(padapter)) { + err = -2; + RTW_INFO("%s: device surprise removed!!\n", __FUNCTION__); + break; + } + + if (rtw_get_passing_time_ms(start_time) > delay_ms) { + err = -1; + RTW_INFO("%s: Wait for FW LPS leave more than %u ms!!!\n", __FUNCTION__, delay_ms); + break; + } + rtw_usleep_os(100); + } + + return err; +} + +/* + * Description: + * Enter the leisure power save mode. + * */ +void LPS_Enter(PADAPTER padapter, const char *msg) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int n_assoc_iface = 0; + int i; + char buf[32] = {0}; + + /* RTW_INFO("+LeisurePSEnter\n"); */ + if (_FALSE == padapter->bFWReady) + return; + + if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + return; + + /* Skip lps enter request if number of assocated adapters is not 1 */ + for (i = 0; i < dvobj->iface_nums; i++) { + if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) + n_assoc_iface++; + } + if (n_assoc_iface != 1) + return; + + /* Skip lps enter request for adapter not port0 */ + if (get_hw_port(padapter) != HW_PORT0) + return; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE) + return; + } + + if (padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) { + return;/* supporting p2p client ps NOA via H2C_8723B_P2P_PS_OFFLOAD */ + } + + if (pwrpriv->bLeisurePs) { + /* Idle for a while if we connect to AP a while ago. */ + if (pwrpriv->LpsIdleCount >= 2) { /* 4 Sec */ + if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { + sprintf(buf, "WIFI-%s", msg); + pwrpriv->bpower_saving = _TRUE; + rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf); + } + } else + pwrpriv->LpsIdleCount++; + } + + /* RTW_INFO("-LeisurePSEnter\n"); */ + +} + +/* + * Description: + * Leave the leisure power save mode. + * */ +void LPS_Leave(PADAPTER padapter, const char *msg) +{ +#define LPS_LEAVE_TIMEOUT_MS 100 + + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + u32 start_time; + u8 bAwake = _FALSE; + char buf[32] = {0}; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + + /* RTW_INFO("+LeisurePSLeave\n"); */ + + if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + return; + + if (pwrpriv->bLeisurePs) { + if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) { + sprintf(buf, "WIFI-%s", msg); + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf); + + if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) + LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS); + } + } + + pwrpriv->bpower_saving = _FALSE; + +} + +void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) +{ + PADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); + struct dvobj_priv *psdpriv = Adapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +#ifndef CONFIG_DETECT_CPWM_BY_POLLING + u8 cpwm_orig, cpwm_now; + u32 start_time; +#endif /* CONFIG_DETECT_CPWM_BY_POLLING */ + + RTW_INFO("%s.....\n", __FUNCTION__); + + if (rtw_is_surprise_removed(Adapter)) { + RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter)); + return; + } + + if (rtw_mi_check_status(Adapter, MI_LINKED)) { /*connect*/ + + if (pwrpriv->pwr_mode == PS_MODE_ACTIVE) { + RTW_INFO("%s: Driver Already Leave LPS\n", __FUNCTION__); + return; + } + + + p2p_ps_wk_cmd(pri_padapter, P2P_PS_DISABLE, 0); + + rtw_lps_ctrl_wk_cmd(pri_padapter, LPS_CTRL_LEAVE, 0); + } else { + if (pwrpriv->rf_pwrstate == rf_off) { + { +#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) + if (_FALSE == ips_leave(pri_padapter)) + RTW_INFO("======> ips_leave fail.............\n"); +#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */ + } + } + } + +} + +/* + * Description: Leave all power save mode: LPS, FwLPS, IPS if needed. + * Move code to function by tynli. 2010.03.26. + * */ +void LeaveAllPowerSaveMode(IN PADAPTER Adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + u8 enqueue = 0; + int n_assoc_iface = 0; + int i; + + /* RTW_INFO("%s.....\n",__FUNCTION__); */ + + if (_FALSE == Adapter->bup) { + RTW_INFO(FUNC_ADPT_FMT ": bup=%d Skip!\n", + FUNC_ADPT_ARG(Adapter), Adapter->bup); + return; + } + + if (rtw_is_surprise_removed(Adapter)) { + RTW_INFO(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter)); + return; + } + + for (i = 0; i < dvobj->iface_nums; i++) { + if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) + n_assoc_iface++; + } + + if (n_assoc_iface) { + /* connect */ + + p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, enqueue); + + rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue); + + } else { + if (adapter_to_pwrctl(Adapter)->rf_pwrstate == rf_off) { + { +#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) + if (_FALSE == ips_leave(Adapter)) + RTW_INFO("======> ips_leave fail.............\n"); +#endif /* CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) */ + } + } + } + +} + + + +void rtw_init_pwrctrl_priv(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + u8 val8 = 0; + + + _init_pwrlock(&pwrctrlpriv->lock); + _init_pwrlock(&pwrctrlpriv->check_32k_lock); + pwrctrlpriv->rf_pwrstate = rf_on; + pwrctrlpriv->ips_enter_cnts = 0; + pwrctrlpriv->ips_leave_cnts = 0; + pwrctrlpriv->lps_enter_cnts = 0; + pwrctrlpriv->lps_leave_cnts = 0; + pwrctrlpriv->bips_processing = _FALSE; + + pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode; + pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode; + pwrctrlpriv->lps_level = padapter->registrypriv.lps_level; + + pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL; + pwrctrlpriv->pwr_state_check_cnts = 0; + pwrctrlpriv->bInternalAutoSuspend = _FALSE; + pwrctrlpriv->bInSuspend = _FALSE; + pwrctrlpriv->bkeepfwalive = _FALSE; + + + pwrctrlpriv->LpsIdleCount = 0; + + + /* pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt; */ /* PS_MODE_MIN; */ + if (padapter->registrypriv.mp_mode == 1) + pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE ; + else + pwrctrlpriv->power_mgnt = padapter->registrypriv.power_mgnt; /* PS_MODE_MIN; */ + pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE; + + pwrctrlpriv->bFwCurrentInPSMode = _FALSE; + + pwrctrlpriv->rpwm = 0; + pwrctrlpriv->cpwm = PS_STATE_S4; + + pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE; + pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps; + pwrctrlpriv->bcn_ant_mode = 0; + pwrctrlpriv->dtim = 0; + + pwrctrlpriv->tog = 0x80; + + + rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler, padapter); + + pwrctrlpriv->wowlan_mode = _FALSE; + pwrctrlpriv->wowlan_ap_mode = _FALSE; + pwrctrlpriv->wowlan_p2p_mode = _FALSE; + pwrctrlpriv->wowlan_last_wake_reason = 0; + + + + + + +} + +void rtw_free_pwrctrl_priv(PADAPTER adapter) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); + + _free_pwrlock(&pwrctrlpriv->lock); + _free_pwrlock(&pwrctrlpriv->check_32k_lock); +} + +inline void rtw_set_ips_deny(_adapter *padapter, u32 ms) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms); +} + +/* +* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend +* @adapter: pointer to _adapter structure +* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup +* Return _SUCCESS or _FAIL +*/ + +int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + struct mlme_priv *pmlmepriv; + int ret = _SUCCESS; + int i; + u32 start = rtw_get_current_time(); + + /* for LPS */ + LeaveAllPowerSaveMode(padapter); + + /* IPS still bound with primary adapter */ + padapter = GET_PRIMARY_ADAPTER(padapter); + pmlmepriv = &padapter->mlmepriv; + + if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); + + if (pwrpriv->ps_processing) { + RTW_INFO("%s wait ps_processing...\n", __func__); + while (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000) + rtw_msleep_os(10); + if (pwrpriv->ps_processing) + RTW_INFO("%s wait ps_processing timeout\n", __func__); + else + RTW_INFO("%s wait ps_processing done\n", __func__); + } + + if (rtw_hal_sreset_inprogress(padapter)) { + RTW_INFO("%s wait sreset_inprogress...\n", __func__); + while (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000) + rtw_msleep_os(10); + if (rtw_hal_sreset_inprogress(padapter)) + RTW_INFO("%s wait sreset_inprogress timeout\n", __func__); + else + RTW_INFO("%s wait sreset_inprogress done\n", __func__); + } + + if (pwrpriv->bInternalAutoSuspend == _FALSE && pwrpriv->bInSuspend) { + RTW_INFO("%s wait bInSuspend...\n", __func__); + while (pwrpriv->bInSuspend + && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv)) + || (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv))) + ) + rtw_msleep_os(10); + if (pwrpriv->bInSuspend) + RTW_INFO("%s wait bInSuspend timeout\n", __func__); + else + RTW_INFO("%s wait bInSuspend done\n", __func__); + } + + /* System suspend is not allowed to wakeup */ + if ((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend)) { + ret = _FAIL; + goto exit; + } + + /* block??? */ + if ((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) { + ret = _FAIL; + goto exit; + } + + /* I think this should be check in IPS, LPS, autosuspend functions... */ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + ret = _SUCCESS; + goto exit; + } + + if (rf_off == pwrpriv->rf_pwrstate) { + { + RTW_INFO("%s call ips_leave....\n", __FUNCTION__); + if (_FAIL == ips_leave(padapter)) { + RTW_INFO("======> ips_leave fail.............\n"); + ret = _FAIL; + goto exit; + } + } + } + + /* TODO: the following checking need to be merged... */ + if (rtw_is_drv_stopped(padapter) + || !padapter->bup + || !rtw_is_hw_init_completed(padapter) + ) { + RTW_INFO("%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\n" + , caller + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , padapter->bup + , rtw_get_hw_init_completed(padapter)); + ret = _FALSE; + goto exit; + } + +exit: + if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); + return ret; + +} + +int rtw_pm_set_lps(_adapter *padapter, u8 mode) +{ + int ret = 0; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (mode < PS_MODE_NUM) { + if (pwrctrlpriv->power_mgnt != mode) { + if (PS_MODE_ACTIVE == mode) + LeaveAllPowerSaveMode(padapter); + else + pwrctrlpriv->LpsIdleCount = 2; + pwrctrlpriv->power_mgnt = mode; + pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt) ? _TRUE : _FALSE; + } + } else + ret = -EINVAL; + + return ret; +} + +int rtw_pm_set_lps_level(_adapter *padapter, u8 level) +{ + int ret = 0; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (level < LPS_LEVEL_MAX) + pwrctrlpriv->lps_level = level; + else + ret = -EINVAL; + + return ret; +} + +int rtw_pm_set_ips(_adapter *padapter, u8 mode) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (mode == IPS_NORMAL || mode == IPS_LEVEL_2) { + rtw_ips_mode_req(pwrctrlpriv, mode); + RTW_INFO("%s %s\n", __FUNCTION__, mode == IPS_NORMAL ? "IPS_NORMAL" : "IPS_LEVEL_2"); + return 0; + } else if (mode == IPS_NONE) { + rtw_ips_mode_req(pwrctrlpriv, mode); + RTW_INFO("%s %s\n", __FUNCTION__, "IPS_NONE"); + if (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter))) + return -EFAULT; + } else + return -EINVAL; + return 0; +} + +/* + * ATTENTION: + * This function will request pwrctrl LOCK! + */ +void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason) +{ + struct pwrctrl_priv *pwrpriv; + s32 ret; + + /* RTW_INFO("+" FUNC_ADPT_FMT ": Request PS deny for %d (0x%08X)\n", + * FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */ + + pwrpriv = adapter_to_pwrctl(padapter); + + _enter_pwrlock(&pwrpriv->lock); + if (pwrpriv->ps_deny & BIT(reason)) { + RTW_INFO(FUNC_ADPT_FMT ": [WARNING] Reason %d had been set before!!\n", + FUNC_ADPT_ARG(padapter), reason); + } + pwrpriv->ps_deny |= BIT(reason); + _exit_pwrlock(&pwrpriv->lock); + + /* RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n", + * FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */ +} + +/* + * ATTENTION: + * This function will request pwrctrl LOCK! + */ +void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason) +{ + struct pwrctrl_priv *pwrpriv; + + /* RTW_INFO("+" FUNC_ADPT_FMT ": Cancel PS deny for %d(0x%08X)\n", + * FUNC_ADPT_ARG(padapter), reason, BIT(reason)); */ + + pwrpriv = adapter_to_pwrctl(padapter); + + _enter_pwrlock(&pwrpriv->lock); + if ((pwrpriv->ps_deny & BIT(reason)) == 0) { + RTW_INFO(FUNC_ADPT_FMT ": [ERROR] Reason %d had been canceled before!!\n", + FUNC_ADPT_ARG(padapter), reason); + } + pwrpriv->ps_deny &= ~BIT(reason); + _exit_pwrlock(&pwrpriv->lock); + + /* RTW_INFO("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n", + * FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); */ +} + +/* + * ATTENTION: + * Before calling this function pwrctrl lock should be occupied already, + * otherwise it may return incorrect value. + */ +u32 rtw_ps_deny_get(PADAPTER padapter) +{ + u32 deny; + + deny = adapter_to_pwrctl(padapter)->ps_deny; + + return deny; +} diff --git a/drivers/staging/rtl8821ce/core/rtw_recv.c b/drivers/staging/rtl8821ce/core/rtw_recv.c new file mode 100644 index 000000000000..9e39d395aba3 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_recv.c @@ -0,0 +1,3210 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_RECV_C_ + +#include <drv_types.h> +#include <hal_data.h> +#include <rtw_recv.h> + +u8 SNAP_ETH_TYPE_IPX[2] = {0x81, 0x37}; +u8 SNAP_ETH_TYPE_APPLETALK_AARP[2] = {0x80, 0xf3}; +u8 SNAP_ETH_TYPE_APPLETALK_DDP[2] = {0x80, 0x9b}; +u8 SNAP_ETH_TYPE_TDLS[2] = {0x89, 0x0d}; +u8 SNAP_HDR_APPLETALK_DDP[3] = {0x08, 0x00, 0x07}; /* Datagram Delivery Protocol */ + +u8 oui_8021h[] = {0x00, 0x00, 0xf8}; +u8 oui_rfc1042[] = {0x00, 0x00, 0x00}; + +u8 rtw_rfc1042_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; +u8 rtw_bridge_tunnel_header[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 }; + +static void rtw_signal_stat_timer_hdl(void *ctx); + +enum { + SIGNAL_STAT_CALC_PROFILE_0 = 0, + SIGNAL_STAT_CALC_PROFILE_1, + SIGNAL_STAT_CALC_PROFILE_MAX +}; + +u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][2] = { + {4, 1}, /* Profile 0 => pre_stat : curr_stat = 4 : 1 */ + {3, 7} /* Profile 1 => pre_stat : curr_stat = 3 : 7 */ +}; + +#ifndef RTW_SIGNAL_STATE_CALC_PROFILE + #define RTW_SIGNAL_STATE_CALC_PROFILE SIGNAL_STAT_CALC_PROFILE_1 +#endif + + +void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) +{ + + _rtw_memset((u8 *)psta_recvpriv, 0, sizeof(struct sta_recv_priv)); + + _rtw_spinlock_init(&psta_recvpriv->lock); + + /* for(i=0; i<MAX_RX_NUMBLKS; i++) */ + /* _rtw_init_queue(&psta_recvpriv->blk_strms[i]); */ + + _rtw_init_queue(&psta_recvpriv->defrag_q); + +} + +sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) +{ + sint i; + + union recv_frame *precvframe; + sint res = _SUCCESS; + + /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ + /* _rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv)); */ + + _rtw_spinlock_init(&precvpriv->lock); + + + _rtw_init_queue(&precvpriv->free_recv_queue); + _rtw_init_queue(&precvpriv->recv_pending_queue); + _rtw_init_queue(&precvpriv->uc_swdec_pending_queue); + + precvpriv->adapter = padapter; + + precvpriv->free_recvframe_cnt = NR_RECVFRAME; + + precvpriv->sink_udpport = 0; + precvpriv->pre_rtp_rxseq = 0; + precvpriv->cur_rtp_rxseq = 0; + + precvpriv->store_law_data_flag = 1; + + rtw_os_recv_resource_init(precvpriv, padapter); + + precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); + + if (precvpriv->pallocated_frame_buf == NULL) { + res = _FAIL; + goto exit; + } + /* _rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); */ + + precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ); + /* precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - */ + /* ((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); */ + + precvframe = (union recv_frame *) precvpriv->precv_frame_buf; + + for (i = 0; i < NR_RECVFRAME ; i++) { + _rtw_init_listhead(&(precvframe->u.list)); + + rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue)); + + res = rtw_os_recv_resource_alloc(padapter, precvframe); + + precvframe->u.hdr.len = 0; + + precvframe->u.hdr.adapter = padapter; + precvframe++; + + } + + res = rtw_hal_init_recv_priv(padapter); + + rtw_init_timer(&precvpriv->signal_stat_timer, padapter, rtw_signal_stat_timer_hdl, padapter); + + precvpriv->signal_stat_sampling_interval = 2000; /* ms */ + /* precvpriv->signal_stat_converging_constant = 5000; */ /* ms */ + + rtw_set_signal_stat_timer(precvpriv); + +exit: + + return res; + +} + +void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv) +{ + _rtw_spinlock_free(&precvpriv->lock); + + _rtw_spinlock_free(&precvpriv->free_recv_queue.lock); + _rtw_spinlock_free(&precvpriv->recv_pending_queue.lock); + + _rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock); + +} + +void _rtw_free_recv_priv(struct recv_priv *precvpriv) +{ + _adapter *padapter = precvpriv->adapter; + + rtw_free_uc_swdec_pending_queue(padapter); + + rtw_mfree_recv_priv_lock(precvpriv); + + rtw_os_recv_resource_free(precvpriv); + + if (precvpriv->pallocated_frame_buf) + rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); + + rtw_hal_free_recv_priv(padapter); + +} + +bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset) +{ +#define DBG_RFRAME_DEL_WFD_IE 0 + u8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset; + uint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data); + uint ies_len; + + ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL); + rframe->u.hdr.len -= ies_len_ori - ies_len; + + return ies_len_ori != ies_len; +} + +union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue) +{ + + union recv_frame *precvframe; + _list *plist, *phead; + _adapter *padapter; + struct recv_priv *precvpriv; + + if (_rtw_queue_empty(pfree_recv_queue) == _TRUE) + precvframe = NULL; + else { + phead = get_list_head(pfree_recv_queue); + + plist = get_next(phead); + + precvframe = LIST_CONTAINOR(plist, union recv_frame, u); + + rtw_list_delete(&precvframe->u.hdr.list); + padapter = precvframe->u.hdr.adapter; + if (padapter != NULL) { + precvpriv = &padapter->recvpriv; + if (pfree_recv_queue == &precvpriv->free_recv_queue) + precvpriv->free_recvframe_cnt--; + } + } + + return precvframe; + +} + +union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue) +{ + _irqL irqL; + union recv_frame *precvframe; + + _enter_critical_bh(&pfree_recv_queue->lock, &irqL); + + precvframe = _rtw_alloc_recvframe(pfree_recv_queue); + + _exit_critical_bh(&pfree_recv_queue->lock, &irqL); + + return precvframe; +} + +int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue) +{ + _irqL irqL; + _adapter *padapter = precvframe->u.hdr.adapter; + struct recv_priv *precvpriv = &padapter->recvpriv; + + + rtw_os_free_recvframe(precvframe); + + _enter_critical_bh(&pfree_recv_queue->lock, &irqL); + + rtw_list_delete(&(precvframe->u.hdr.list)); + + precvframe->u.hdr.len = 0; + + rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue)); + + if (padapter != NULL) { + if (pfree_recv_queue == &precvpriv->free_recv_queue) + precvpriv->free_recvframe_cnt++; + } + + _exit_critical_bh(&pfree_recv_queue->lock, &irqL); + + return _SUCCESS; + +} + +sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) +{ + + _adapter *padapter = precvframe->u.hdr.adapter; + struct recv_priv *precvpriv = &padapter->recvpriv; + + /* _rtw_init_listhead(&(precvframe->u.hdr.list)); */ + rtw_list_delete(&(precvframe->u.hdr.list)); + + rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue)); + + if (padapter != NULL) { + if (queue == &precvpriv->free_recv_queue) + precvpriv->free_recvframe_cnt++; + } + + return _SUCCESS; +} + +sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) +{ + sint ret; + _irqL irqL; + + /* _spinlock(&pfree_recv_queue->lock); */ + _enter_critical_bh(&queue->lock, &irqL); + ret = _rtw_enqueue_recvframe(precvframe, queue); + /* _rtw_spinunlock(&pfree_recv_queue->lock); */ + _exit_critical_bh(&queue->lock, &irqL); + + return ret; +} + +/* +sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) +{ + return rtw_free_recvframe(precvframe, queue); +} +*/ + +/* +caller : defrag ; recvframe_chk_defrag in recv_thread (passive) +pframequeue: defrag_queue : will be accessed in recv_thread (passive) + +using spinlock to protect + +*/ + +void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) +{ + union recv_frame *precvframe; + _list *plist, *phead; + + _rtw_spinlock(&pframequeue->lock); + + phead = get_list_head(pframequeue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + precvframe = LIST_CONTAINOR(plist, union recv_frame, u); + + plist = get_next(plist); + + /* rtw_list_delete(&precvframe->u.hdr.list); */ /* will do this in rtw_free_recvframe() */ + + rtw_free_recvframe(precvframe, pfree_recv_queue); + } + + _rtw_spinunlock(&pframequeue->lock); + +} + +u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter) +{ + u32 cnt = 0; + union recv_frame *pending_frame; + while ((pending_frame = rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) { + rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue); + cnt++; + } + + if (cnt) + RTW_INFO(FUNC_ADPT_FMT" dequeue %d\n", FUNC_ADPT_ARG(adapter), cnt); + + return cnt; +} + +sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe) +{ + + sint i, res = _SUCCESS; + u32 datalen; + u8 miccode[8]; + u8 bmic_err = _FALSE, brpt_micerror = _TRUE; + u8 *pframe, *payload, *pframemic; + u8 *mickey; + /* u8 *iv,rxdata_key_idx=0; */ + struct sta_info *stainfo; + struct rx_pkt_attrib *prxattrib = &precvframe->u.hdr.attrib; + struct security_priv *psecuritypriv = &adapter->securitypriv; + + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + stainfo = rtw_get_stainfo(&adapter->stapriv , &prxattrib->ta[0]); + + if (prxattrib->encrypt == _TKIP_) { + + /* calculate mic code */ + if (stainfo != NULL) { + if (IS_MCAST(prxattrib->ra)) { + /* mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; */ + /* iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; */ + /* rxdata_key_idx =( ((iv[3])>>6)&0x3) ; */ + mickey = &psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0]; + + /* RTW_INFO("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", */ + /* psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); */ + + if (psecuritypriv->binstallGrpkey == _FALSE) { + res = _FAIL; + RTW_INFO("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n"); + goto exit; + } + } else { + mickey = &stainfo->dot11tkiprxmickey.skey[0]; + } + + datalen = precvframe->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len - prxattrib->icv_len - 8; /* icv_len included the mic code */ + pframe = precvframe->u.hdr.rx_data; + payload = pframe + prxattrib->hdrlen + prxattrib->iv_len; + + /* rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); */ /* care the length of the data */ + + rtw_seccalctkipmic(mickey, pframe, payload, datalen , &miccode[0], (unsigned char)prxattrib->priority); /* care the length of the data */ + + pframemic = payload + datalen; + + bmic_err = _FALSE; + + for (i = 0; i < 8; i++) { + if (miccode[i] != *(pframemic + i)) { + bmic_err = _TRUE; + } + } + + if (bmic_err == _TRUE) { + + /* double check key_index for some timing issue , */ + /* cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue */ + if ((IS_MCAST(prxattrib->ra) == _TRUE) && (prxattrib->key_index != pmlmeinfo->key_index)) + brpt_micerror = _FALSE; + + if ((prxattrib->bdecrypted == _TRUE) && (brpt_micerror == _TRUE)) { + rtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra)); + RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted); + } else { + RTW_INFO(" mic error :prxattrib->bdecrypted=%d\n", prxattrib->bdecrypted); + } + + res = _FAIL; + + } else { + /* mic checked ok */ + if ((psecuritypriv->bcheck_grpkey == _FALSE) && (IS_MCAST(prxattrib->ra) == _TRUE)) { + psecuritypriv->bcheck_grpkey = _TRUE; + } + } + + } + + recvframe_pull_tail(precvframe, 8); + + } + +exit: + + return res; + +} + +/*#define DBG_RX_SW_DECRYPTOR*/ + +/* decrypt and set the ivlen,icvlen of the recv_frame */ +union recv_frame *decryptor(_adapter *padapter, union recv_frame *precv_frame) +{ + + struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + union recv_frame *return_packet = precv_frame; + u32 res = _SUCCESS; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt); + + if (prxattrib->encrypt > 0) { + u8 *iv = precv_frame->u.hdr.rx_data + prxattrib->hdrlen; + prxattrib->key_index = (((iv[3]) >> 6) & 0x3) ; + + if (prxattrib->key_index > WEP_KEYS) { + RTW_INFO("prxattrib->key_index(%d) > WEP_KEYS\n", prxattrib->key_index); + + switch (prxattrib->encrypt) { + case _WEP40_: + case _WEP104_: + prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex; + break; + case _TKIP_: + case _AES_: + default: + prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid; + break; + } + } + } + + if ((prxattrib->encrypt > 0) && ((prxattrib->bdecrypted == 0) || (psecuritypriv->sw_decrypt == _TRUE))) { + + psecuritypriv->hw_decrypted = _FALSE; + +#ifdef DBG_RX_SW_DECRYPTOR + RTW_INFO(ADPT_FMT" - sec_type:%s DO SW decryption\n", + ADPT_ARG(padapter), security_type_str(prxattrib->encrypt)); +#endif + + + switch (prxattrib->encrypt) { + case _WEP40_: + case _WEP104_: + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wep); + rtw_wep_decrypt(padapter, (u8 *)precv_frame); + break; + case _TKIP_: + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_tkip); + res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame); + break; + case _AES_: + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_aes); + res = rtw_aes_decrypt(padapter, (u8 *)precv_frame); + break; + default: + break; + } + } else if (prxattrib->bdecrypted == 1 + && prxattrib->encrypt > 0 + && (psecuritypriv->busetkipkey == 1 || prxattrib->encrypt != _TKIP_) + ) { + { + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_hw); + + psecuritypriv->hw_decrypted = _TRUE; + } + } else { + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_unknown); + } + + if (res == _FAIL) { + rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue); + return_packet = NULL; + } else + prxattrib->bdecrypted = _TRUE; + /* recvframe_chkmic(adapter, precv_frame); */ /* move to recvframme_defrag function */ + + return return_packet; + +} +/* ###set the security information in the recv_frame */ +union recv_frame *portctrl(_adapter *adapter, union recv_frame *precv_frame) +{ + u8 *psta_addr = NULL; + u8 *ptr; + uint auth_alg; + struct recv_frame_hdr *pfhdr; + struct sta_info *psta; + struct sta_priv *pstapriv ; + union recv_frame *prtnframe; + u16 ether_type = 0; + u16 eapol_type = 0x888e;/* for Funia BD's WPA issue */ + struct rx_pkt_attrib *pattrib; + + pstapriv = &adapter->stapriv; + + auth_alg = adapter->securitypriv.dot11AuthAlgrthm; + + ptr = get_recvframe_data(precv_frame); + pfhdr = &precv_frame->u.hdr; + pattrib = &pfhdr->attrib; + psta_addr = pattrib->ta; + + prtnframe = NULL; + + psta = rtw_get_stainfo(pstapriv, psta_addr); + + if (auth_alg == dot11AuthAlgrthm_8021X) { + if ((psta != NULL) && (psta->ieee8021x_blocked)) { + /* blocked */ + /* only accept EAPOL frame */ + + prtnframe = precv_frame; + + /* get ether_type */ + ptr = ptr + pfhdr->attrib.hdrlen + pfhdr->attrib.iv_len + LLC_HEADER_SIZE; + _rtw_memcpy(ðer_type, ptr, 2); + ether_type = ntohs((unsigned short)ether_type); + + if (ether_type == eapol_type) + prtnframe = precv_frame; + else { + /* free this frame */ + rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue); + prtnframe = NULL; + } + } else { + /* allowed */ + /* check decryption status, and decrypt the frame if needed */ + + prtnframe = precv_frame; + /* check is the EAPOL frame or not (Rekey) */ + /* if(ether_type == eapol_type){ */ + /* check Rekey */ + + /* prtnframe=precv_frame; */ + /* } */ + } + } else + prtnframe = precv_frame; + + return prtnframe; + +} + +sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache) +{ + sint tid = precv_frame->u.hdr.attrib.priority; + + u16 seq_ctrl = ((precv_frame->u.hdr.attrib.seq_num & 0xffff) << 4) | + (precv_frame->u.hdr.attrib.frag_num & 0xf); + + if (tid > 15) { + + return _FAIL; + } + + if (1) { /* if(bretry) */ + if (seq_ctrl == prxcache->tid_rxseq[tid]) { + /* for non-AMPDU case */ + precv_frame->u.hdr.psta->sta_stats.duplicate_cnt++; + + if (precv_frame->u.hdr.psta->sta_stats.duplicate_cnt % 100 == 0) + RTW_INFO("%s: seq=%d\n", __func__, precv_frame->u.hdr.attrib.seq_num); + + return _FAIL; + } + } + + prxcache->tid_rxseq[tid] = seq_ctrl; + + return _SUCCESS; + +} + +#define PN_LESS_CHK(a, b) (((a-b) & 0x800000000000) != 0) +#define PN_EQUAL_CHK(a, b) (a == b) +sint recv_ucast_pn_decache(union recv_frame *precv_frame, struct stainfo_rxcache *prxcache) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + u8 *pdata = precv_frame->u.hdr.rx_data; + sint tid = precv_frame->u.hdr.attrib.priority; + u64 tmp_iv_hdr = 0; + u64 curr_pn = 0, pkt_pn = 0; + + if (tid > 15) + return _FAIL; + + if (pattrib->encrypt == _AES_) { + _rtw_memcpy(&tmp_iv_hdr, (pdata + pattrib->hdrlen), 8); + tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr); + pkt_pn = (tmp_iv_hdr & 0x000000000000ffff) | + ((tmp_iv_hdr & 0xffffffff00000000) >> 16); + + _rtw_memcpy(&tmp_iv_hdr, prxcache->iv[tid], 8); + tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr); + curr_pn = (tmp_iv_hdr & 0x000000000000ffff) | + ((tmp_iv_hdr & 0xffffffff00000000) >> 16); + + if (curr_pn == 0) { + _rtw_memcpy(prxcache->iv[tid], (pdata + pattrib->hdrlen), sizeof(prxcache->iv[tid])); + goto exit; + } + + if (PN_LESS_CHK(pkt_pn, curr_pn) || PN_EQUAL_CHK(pkt_pn, curr_pn)) { + /* return _FAIL; */ + } else + _rtw_memcpy(prxcache->iv[tid], (pdata + pattrib->hdrlen), sizeof(prxcache->iv[tid])); + } + +exit: + return _SUCCESS; +} + +sint recv_bcast_pn_decache(union recv_frame *precv_frame) +{ + _adapter *padapter = precv_frame->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + u8 *pdata = precv_frame->u.hdr.rx_data; + u64 tmp_iv_hdr = 0; + u64 curr_pn = 0, pkt_pn = 0; + u8 key_id; + + if ((pattrib->encrypt == _AES_) && + (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { + _rtw_memcpy(&tmp_iv_hdr, (pdata + pattrib->hdrlen), 8); + tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr); + key_id = ((tmp_iv_hdr & 0x00000000c0000000) >> 30); + pkt_pn = (tmp_iv_hdr & 0x000000000000ffff) | + ((tmp_iv_hdr & 0xffffffff00000000) >> 16); + + if (key_id >= 4 ) + return _FAIL; + + _rtw_memcpy(&tmp_iv_hdr, psecuritypriv->iv_seq[key_id], 8); + tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr); + + curr_pn = (tmp_iv_hdr & 0x0000ffffffffffff); + + if ((curr_pn == 0) && (pkt_pn >= 0)) { + _rtw_memcpy(psecuritypriv->iv_seq[key_id], &pkt_pn, 8); + goto exit; + } + + if (PN_LESS_CHK(pkt_pn, curr_pn) || PN_EQUAL_CHK(pkt_pn, curr_pn)) { + return _FAIL; + } else + _rtw_memcpy(psecuritypriv->iv_seq[key_id], &pkt_pn, 8); + } + +exit: + return _SUCCESS; +} + +void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned char pwrbit; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + + psta = rtw_get_stainfo(pstapriv, pattrib->src); + + pwrbit = GetPwrMgt(ptr); + + if (psta) { + if (pwrbit) { + if (!(psta->state & WIFI_SLEEP_STATE)) { + /* psta->state |= WIFI_SLEEP_STATE; */ + /* pstapriv->sta_dz_bitmap |= BIT(psta->aid); */ + + stop_sta_xmit(padapter, psta); + + /* RTW_INFO("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */ + } + } else { + if (psta->state & WIFI_SLEEP_STATE) { + /* psta->state ^= WIFI_SLEEP_STATE; */ + /* pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); */ + + wakeup_sta_to_xmit(padapter, psta); + + /* RTW_INFO("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); */ + } + } + + } + +} + +void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + + psta = rtw_get_stainfo(pstapriv, pattrib->src); + + if (!psta) + return; + + if (!psta->qos_option) + return; + + if (!(psta->qos_info & 0xf)) + return; + + if (psta->state & WIFI_SLEEP_STATE) { + u8 wmmps_ac = 0; + + switch (pattrib->priority) { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk & BIT(1); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi & BIT(1); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo & BIT(1); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be & BIT(1); + break; + } + + if (wmmps_ac) { + if (psta->sleepq_ac_len > 0) { + /* process received triggered frame */ + xmit_delivery_enabled_frames(padapter, psta); + } else { + /* issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) */ + issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority, 0, 0); + } + } + + } +} + +void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info *sta) +{ + int sz; + struct sta_info *psta = NULL; + struct stainfo_stats *pstats = NULL; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct recv_priv *precvpriv = &padapter->recvpriv; + + sz = get_recvframe_len(prframe); + precvpriv->rx_bytes += sz; + + padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++; + + if ((!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst))) + padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++; + + if (sta) + psta = sta; + else + psta = prframe->u.hdr.psta; + + if (psta) { + pstats = &psta->sta_stats; + + pstats->rx_data_pkts++; + pstats->rx_bytes += sz; + + pstats->rxratecnt[pattrib->data_rate]++; + /*record rx packets for every tid*/ + pstats->rx_data_qos_pkts[pattrib->priority]++; + + } + + +} + +sint sta2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info **psta +); +sint sta2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info **psta +) +{ + u8 *ptr = precv_frame->u.hdr.rx_data; + sint ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u8 *mybssid = get_bssid(pmlmepriv); + u8 *myhwaddr = adapter_mac_addr(adapter); + u8 *sta_addr = NULL; + sint bmcast = IS_MCAST(pattrib->dst); + + /* RTW_INFO("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); */ + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + + /* filter packets that SA is myself or multicast or broadcast */ + if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { + ret = _FAIL; + goto exit; + } + + if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { + ret = _FAIL; + goto exit; + } + + if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) { + ret = _FAIL; + goto exit; + } + + sta_addr = pattrib->src; + + } else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + { + /* For Station mode, sa and bssid should always be BSSID, and DA is my mac-address */ + if (!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN)) { + ret = _FAIL; + goto exit; + } + + sta_addr = pattrib->bssid; + } + + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + if (bmcast) { + /* For AP mode, if DA == MCAST, then BSSID should be also MCAST */ + if (!IS_MCAST(pattrib->bssid)) { + ret = _FAIL; + goto exit; + } + } else { /* not mc-frame */ + /* For AP mode, if DA is non-MCAST, then it must be BSSID, and bssid == BSSID */ + if (!_rtw_memcmp(pattrib->bssid, pattrib->dst, ETH_ALEN)) { + ret = _FAIL; + goto exit; + } + + sta_addr = pattrib->src; + } + + } else if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) { + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + sta_addr = mybssid; + } else + ret = _FAIL; + + if (bmcast) + *psta = rtw_get_bcmc_stainfo(adapter); + else + *psta = rtw_get_stainfo(pstapriv, sta_addr); /* get ap_info */ + + if (*psta == NULL) { + if (adapter->registrypriv.mp_mode == 1) { + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + adapter->mppriv.rx_pktloss++; + } + ret = _FAIL; + goto exit; + } + +exit: + return ret; + +} + +sint ap2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info **psta); +sint ap2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info **psta) +{ + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + sint ret = _SUCCESS; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u8 *mybssid = get_bssid(pmlmepriv); + u8 *myhwaddr = adapter_mac_addr(adapter); + sint bmcast = IS_MCAST(pattrib->dst); + + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE + || check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) + ) { + + /* filter packets that SA is myself or multicast or broadcast */ + if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { + ret = _FAIL; + goto exit; + } + + /* da should be for me */ + if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { + ret = _FAIL; + goto exit; + } + + /* check BSSID */ + if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) { + + if (!bmcast) { + RTW_INFO(ADPT_FMT" -issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", ADPT_ARG(adapter), MAC_ARG(pattrib->bssid)); + issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + } + + ret = _FAIL; + goto exit; + } + + if (bmcast) + *psta = rtw_get_bcmc_stainfo(adapter); + else + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get ap_info */ + + if (*psta == NULL) { + ret = _FAIL; + goto exit; + } + + /*if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { + } + */ + + if (get_frame_sub_type(ptr) & BIT(6)) { + /* No data, will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, precv_frame, *psta); + ret = RTW_RX_HANDLED; + goto exit; + } + + } else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && + (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ + if (*psta == NULL) { + ret = _FAIL; + goto exit; + } + + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + /* Special case */ + ret = RTW_RX_HANDLED; + goto exit; + } else { + if (_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN) && (!bmcast)) { + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ + if (*psta == NULL) { + + /* for AP multicast issue , modify by yiwei */ + static u32 send_issue_deauth_time = 0; + + /* RTW_INFO("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); */ + + if (rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0) { + send_issue_deauth_time = rtw_get_current_time(); + + RTW_INFO("issue_deauth to the ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid)); + + issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + } + } + } + + ret = _FAIL; + } + +exit: + + return ret; + +} + +sint sta2ap_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info **psta); +sint sta2ap_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info **psta) +{ + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + unsigned char *mybssid = get_bssid(pmlmepriv); + sint ret = _SUCCESS; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + /* For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR */ + if (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) { + ret = _FAIL; + goto exit; + } + + *psta = rtw_get_stainfo(pstapriv, pattrib->src); + if (*psta == NULL) { + + RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); + + issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + + ret = RTW_RX_HANDLED; + goto exit; + } + + process_pwrbit_data(adapter, precv_frame); + + if ((get_frame_sub_type(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) + process_wmmps_data(adapter, precv_frame); + + if (get_frame_sub_type(ptr) & BIT(6)) { + /* No data, will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, precv_frame, *psta); + ret = RTW_RX_HANDLED; + goto exit; + } + } else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && + (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { + /* RTW_INFO("%s ,in WIFI_MP_STATE\n",__func__); */ + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, get_addr2_ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); /* get sta_info */ + if (*psta == NULL) { + ret = _FAIL; + goto exit; + } + + } else { + u8 *myhwaddr = adapter_mac_addr(adapter); + if (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) { + ret = RTW_RX_HANDLED; + goto exit; + } + RTW_INFO("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); + issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + ret = RTW_RX_HANDLED; + goto exit; + } + +exit: + + return ret; + +} + +sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta = NULL; + /* uint len = precv_frame->u.hdr.len; */ + + /* RTW_INFO("+validate_recv_ctrl_frame\n"); */ + + if (GetFrameType(pframe) != WIFI_CTRL_TYPE) + return _FAIL; + + /* receive the frames that ra(a1) is my address */ + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN)) + return _FAIL; + + psta = rtw_get_stainfo(pstapriv, get_addr2_ptr(pframe)); + if (psta == NULL) + return _FAIL; + + /* for rx pkt statistics */ + psta->sta_stats.rx_ctrl_pkts++; + + /* only handle ps-poll */ + if (get_frame_sub_type(pframe) == WIFI_PSPOLL) { + u16 aid; + u8 wmmps_ac = 0; + + aid = GetAid(pframe); + if (psta->aid != aid) + return _FAIL; + + switch (pattrib->priority) { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk & BIT(0); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi & BIT(0); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo & BIT(0); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be & BIT(0); + break; + } + + if (wmmps_ac) + return _FAIL; + + if (psta->state & WIFI_STA_ALIVE_CHK_STATE) { + RTW_INFO("%s alive check-rx ps-poll\n", __func__); + psta->expire_to = pstapriv->expire_to; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + } + + if ((psta->state & WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap & BIT(psta->aid))) { + _irqL irqL; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + psta->sleepq_len--; + + if (psta->sleepq_len > 0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + pxmitframe->attrib.triggered = 1; + + /* RTW_INFO("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + if (psta->sleepq_len == 0) { + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + /* RTW_INFO("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap); */ + + /* upate BCN for TIM IE */ + /* update_BCNTIM(padapter); */ + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + } + + /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + } else { + /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + /* RTW_INFO("no buffered packets to xmit\n"); */ + if (pstapriv->tim_bitmap & BIT(psta->aid)) { + if (psta->sleepq_len == 0) { + RTW_INFO("no buffered packets to xmit\n"); + + /* issue nulldata with More data bit = 0 to indicate we have no buffered packets */ + issue_nulldata_in_interrupt(padapter, psta->hwaddr, 0); + } else { + RTW_INFO("error!psta->sleepq_len=%d\n", psta->sleepq_len); + psta->sleepq_len = 0; + } + + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + /* upate BCN for TIM IE */ + /* update_BCNTIM(padapter); */ + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + } + } + } + } else if (get_frame_sub_type(pframe) == WIFI_NDPA) { + } + + return _FAIL; + +} + +union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); +sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) +{ + /* struct mlme_priv *pmlmepriv = &adapter->mlmepriv; */ + precv_frame = recvframe_chk_defrag(padapter, precv_frame); + if (precv_frame == NULL) { + return _SUCCESS; + } + + { + /* for rx pkt statistics */ + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, get_addr2_ptr(precv_frame->u.hdr.rx_data)); + if (psta) { + psta->sta_stats.rx_mgnt_pkts++; + if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_BEACON) + psta->sta_stats.rx_beacon_pkts++; + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) + psta->sta_stats.rx_probereq_pkts++; + else if (get_frame_sub_type(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { + if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) + psta->sta_stats.rx_probersp_pkts++; + else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) + || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))) + psta->sta_stats.rx_probersp_bm_pkts++; + else + psta->sta_stats.rx_probersp_uo_pkts++; + } + } + } + + mgt_dispatcher(padapter, precv_frame); + + return _SUCCESS; + +} + +sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) +{ + u8 bretry; + u8 *psa, *pda, *pbssid; + struct sta_info *psta = NULL; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct security_priv *psecuritypriv = &adapter->securitypriv; + sint ret = _SUCCESS; + + bretry = GetRetry(ptr); + pda = get_da(ptr); + psa = get_sa(ptr); + pbssid = get_hdr_bssid(ptr); + + if (pbssid == NULL) { + ret = _FAIL; + goto exit; + } + + _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); + _rtw_memcpy(pattrib->src, psa, ETH_ALEN); + + _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); + + switch (pattrib->to_fr_ds) { + case 0: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2sta_data_frame(adapter, precv_frame, &psta); + break; + + case 1: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); + ret = ap2sta_data_frame(adapter, precv_frame, &psta); + break; + + case 2: + _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2ap_data_frame(adapter, precv_frame, &psta); + break; + + case 3: + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + ret = _FAIL; + break; + + default: + ret = _FAIL; + break; + + } + + if (ret == _FAIL) { + goto exit; + } else if (ret == RTW_RX_HANDLED) + goto exit; + + if (psta == NULL) { + ret = _FAIL; + goto exit; + } + + /* psta->rssi = prxcmd->rssi; */ + /* psta->signal_quality= prxcmd->sq; */ + precv_frame->u.hdr.psta = psta; + + pattrib->amsdu = 0; + pattrib->ack_policy = 0; + /* parsing QC field */ + if (pattrib->qos == 1) { + pattrib->priority = GetPriority((ptr + 24)); + pattrib->ack_policy = GetAckpolicy((ptr + 24)); + pattrib->amsdu = GetAMsdu((ptr + 24)); + pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 32 : 26; + + if (pattrib->priority != 0 && pattrib->priority != 3) + adapter->recvpriv.is_any_non_be_pkts = _TRUE; + else + adapter->recvpriv.is_any_non_be_pkts = _FALSE; + } else { + pattrib->priority = 0; + pattrib->hdrlen = pattrib->to_fr_ds == 3 ? 30 : 24; + } + + if (pattrib->order) /* HT-CTRL 11n */ + pattrib->hdrlen += 4; + + precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; + + /* decache, drop duplicate recv packets */ + if (recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) { + ret = _FAIL; + goto exit; + } + + if (!IS_MCAST(pattrib->ra)) { + if (recv_ucast_pn_decache(precv_frame, &psta->sta_recvpriv.rxcache) == _FAIL) { + ret = _FAIL; + goto exit; + } + } else { + if (recv_bcast_pn_decache(precv_frame) == _FAIL) { + ret = _FAIL; + goto exit; + } + } + + if (pattrib->privacy) { + + GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra)); + + SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); + } else { + pattrib->encrypt = 0; + pattrib->iv_len = pattrib->icv_len = 0; + } + +exit: + + return ret; +} + + +static inline void dump_rx_packet(u8 *ptr) +{ + int i; + + RTW_INFO("#############################\n"); + for (i = 0; i < 64; i = i + 8) + RTW_INFO("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr + i), + *(ptr + i + 1), *(ptr + i + 2) , *(ptr + i + 3) , *(ptr + i + 4), *(ptr + i + 5), *(ptr + i + 6), *(ptr + i + 7)); + RTW_INFO("#############################\n"); +} + +sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) +{ + /* shall check frame subtype, to / from ds, da, bssid */ + + /* then call check if rx seq/frag. duplicated. */ + + u8 type; + u8 subtype; + sint retval = _SUCCESS; + + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + + u8 *ptr = precv_frame->u.hdr.rx_data; + u8 ver = (unsigned char)(*ptr) & 0x3 ; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { + int ch_set_idx = rtw_chset_search_ch(pmlmeext->channel_set, rtw_get_oper_ch(adapter)); + if (ch_set_idx >= 0) + pmlmeext->channel_set[ch_set_idx].rx_count++; + } + + + /* add version chk */ + if (ver != 0) { + retval = _FAIL; + DBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err); + goto exit; + } + + type = GetFrameType(ptr); + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ + + pattrib->to_fr_ds = get_tofr_ds(ptr); + + pattrib->frag_num = GetFragNum(ptr); + pattrib->seq_num = GetSequence(ptr); + + pattrib->pw_save = GetPwrMgt(ptr); + pattrib->mfrag = GetMFrag(ptr); + pattrib->mdata = GetMData(ptr); + pattrib->privacy = GetPrivacy(ptr); + pattrib->order = GetOrder(ptr); + + { + u8 bDumpRxPkt = 0; + + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); + if (bDumpRxPkt == 1) /* dump all rx packets */ + dump_rx_packet(ptr); + else if ((bDumpRxPkt == 2) && (type == WIFI_MGT_TYPE)) + dump_rx_packet(ptr); + else if ((bDumpRxPkt == 3) && (type == WIFI_DATA_TYPE)) + dump_rx_packet(ptr); + } + switch (type) { + case WIFI_MGT_TYPE: /* mgnt */ + DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt); + + retval = validate_recv_mgnt_frame(adapter, precv_frame); + if (retval == _FAIL) { + DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err); + } + retval = _FAIL; /* only data frame return _SUCCESS */ + break; + case WIFI_CTRL_TYPE: /* ctrl */ + DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl); + retval = validate_recv_ctrl_frame(adapter, precv_frame); + if (retval == _FAIL) { + DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err); + } + retval = _FAIL; /* only data frame return _SUCCESS */ + break; + case WIFI_DATA_TYPE: /* data */ + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data); + + pattrib->qos = (subtype & BIT(7)) ? 1 : 0; + retval = validate_recv_data_frame(adapter, precv_frame); + if (retval == _FAIL) { + struct recv_priv *precvpriv = &adapter->recvpriv; + precvpriv->rx_drop++; + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err); + } else if (retval == _SUCCESS) { +#ifdef DBG_RX_DUMP_EAP + u8 bDumpRxPkt; + u16 eth_type; + + /* dump eapol */ + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); + /* get ether_type */ + _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE, 2); + eth_type = ntohs((unsigned short) eth_type); + if ((bDumpRxPkt == 4) && (eth_type == 0x888e)) + dump_rx_packet(ptr); +#endif + } else + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled); + break; + default: + DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown); + retval = _FAIL; + break; + } + +exit: + + return retval; +} + +/* remove the wlanhdr and add the eth_hdr */ +sint wlanhdr_to_ethhdr(union recv_frame *precvframe) +{ + sint rmv_len; + u16 eth_type, len; + u8 bsnaphdr; + u8 *psnap_type; + struct ieee80211_snap_hdr *psnap; + + sint ret = _SUCCESS; + _adapter *adapter = precvframe->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + + if (pattrib->encrypt) + recvframe_pull_tail(precvframe, pattrib->icv_len); + + psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len); + psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE; + /* convert hdr + possible LLC headers into Ethernet header */ + /* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */ + if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2) == _FALSE)) || + /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */ + _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) { + /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ + bsnaphdr = _TRUE; + } else { + /* Leave Ethernet header part of hdr and full payload */ + bsnaphdr = _FALSE; + } + + rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); + len = precvframe->u.hdr.len - rmv_len; + + _rtw_memcpy(ð_type, ptr + rmv_len, 2); + eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ + pattrib->eth_type = eth_type; + + + if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) { + ptr += rmv_len ; + *ptr = 0x87; + *(ptr + 1) = 0x12; + + eth_type = 0x8712; + /* append rx status for mp test packets */ + ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + 2) - 24); + if (!ptr) { + ret = _FAIL; + goto exiting; + } + _rtw_memcpy(ptr, get_rxmem(precvframe), 24); + ptr += 24; + } else { + ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (bsnaphdr ? 2 : 0))); + if (!ptr) { + ret = _FAIL; + goto exiting; + } + } + + if (ptr) { + _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); + _rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN); + + if (!bsnaphdr) { + len = htons(len); + _rtw_memcpy(ptr + 12, &len, 2); + } + } + +exiting: + return ret; + +} + +/* perform defrag */ +union recv_frame *recvframe_defrag(_adapter *adapter, _queue *defrag_q) +{ + _list *plist, *phead; + u8 *data, wlanhdr_offset; + u8 curfragnum; + struct recv_frame_hdr *pfhdr, *pnfhdr; + union recv_frame *prframe, *pnextrframe; + _queue *pfree_recv_queue; + + curfragnum = 0; + pfree_recv_queue = &adapter->recvpriv.free_recv_queue; + + phead = get_list_head(defrag_q); + plist = get_next(phead); + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + pfhdr = &prframe->u.hdr; + rtw_list_delete(&(prframe->u.list)); + + if (curfragnum != pfhdr->attrib.frag_num) { + /* the first fragment number must be 0 */ + /* free the whole queue */ + rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + + return NULL; + } + + curfragnum++; + + plist = get_list_head(defrag_q); + + plist = get_next(plist); + + data = get_recvframe_data(prframe); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u); + pnfhdr = &pnextrframe->u.hdr; + + /* check the fragment sequence (2nd ~n fragment frame) */ + + if (curfragnum != pnfhdr->attrib.frag_num) { + /* the fragment number must be increasing (after decache) */ + /* release the defrag_q & prframe */ + rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + return NULL; + } + + curfragnum++; + + /* copy the 2nd~n fragment frame's payload to the first fragment */ + /* get the 2nd~last fragment frame's payload */ + + wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len; + + recvframe_pull(pnextrframe, wlanhdr_offset); + + /* append to first fragment frame's tail (if privacy frame, pull the ICV) */ + recvframe_pull_tail(prframe, pfhdr->attrib.icv_len); + + /* memcpy */ + _rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len); + + recvframe_put(prframe, pnfhdr->len); + + pfhdr->attrib.icv_len = pnfhdr->attrib.icv_len; + plist = get_next(plist); + + }; + + /* free the defrag_q queue and return the prframe */ + rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + + return prframe; +} + +/* check if need to defrag, if needed queue the frame to defrag_q */ +union recv_frame *recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame) +{ + u8 ismfrag; + u8 fragnum; + u8 *psta_addr; + struct recv_frame_hdr *pfhdr; + struct sta_info *psta; + struct sta_priv *pstapriv; + _list *phead; + union recv_frame *prtnframe = NULL; + _queue *pfree_recv_queue, *pdefrag_q; + + pstapriv = &padapter->stapriv; + + pfhdr = &precv_frame->u.hdr; + + pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + + /* need to define struct of wlan header frame ctrl */ + ismfrag = pfhdr->attrib.mfrag; + fragnum = pfhdr->attrib.frag_num; + + psta_addr = pfhdr->attrib.ta; + psta = rtw_get_stainfo(pstapriv, psta_addr); + if (psta == NULL) { + u8 type = GetFrameType(pfhdr->rx_data); + if (type != WIFI_DATA_TYPE) { + psta = rtw_get_bcmc_stainfo(padapter); + pdefrag_q = &psta->sta_recvpriv.defrag_q; + } else + pdefrag_q = NULL; + } else + pdefrag_q = &psta->sta_recvpriv.defrag_q; + + if ((ismfrag == 0) && (fragnum == 0)) { + prtnframe = precv_frame;/* isn't a fragment frame */ + } + + if (ismfrag == 1) { + /* 0~(n-1) fragment frame */ + /* enqueue to defraf_g */ + if (pdefrag_q != NULL) { + if (fragnum == 0) { + /* the first fragment */ + if (_rtw_queue_empty(pdefrag_q) == _FALSE) { + /* free current defrag_q */ + rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue); + } + } + + /* Then enqueue the 0~(n-1) fragment into the defrag_q */ + + /* _rtw_spinlock(&pdefrag_q->lock); */ + phead = get_list_head(pdefrag_q); + rtw_list_insert_tail(&pfhdr->list, phead); + /* _rtw_spinunlock(&pdefrag_q->lock); */ + + prtnframe = NULL; + + } else { + /* can't find this ta's defrag_queue, so free this recv_frame */ + rtw_free_recvframe(precv_frame, pfree_recv_queue); + prtnframe = NULL; + } + + } + + if ((ismfrag == 0) && (fragnum != 0)) { + /* the last fragment frame */ + /* enqueue the last fragment */ + if (pdefrag_q != NULL) { + /* _rtw_spinlock(&pdefrag_q->lock); */ + phead = get_list_head(pdefrag_q); + rtw_list_insert_tail(&pfhdr->list, phead); + /* _rtw_spinunlock(&pdefrag_q->lock); */ + + /* call recvframe_defrag to defrag */ + precv_frame = recvframe_defrag(padapter, pdefrag_q); + prtnframe = precv_frame; + + } else { + /* can't find this ta's defrag_queue, so free this recv_frame */ + rtw_free_recvframe(precv_frame, pfree_recv_queue); + prtnframe = NULL; + } + + } + + if ((prtnframe != NULL) && (prtnframe->u.hdr.attrib.privacy)) { + /* after defrag we must check tkip mic code */ + if (recvframe_chkmic(padapter, prtnframe) == _FAIL) { + rtw_free_recvframe(prtnframe, pfree_recv_queue); + prtnframe = NULL; + } + } + + return prtnframe; + +} + +int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) +{ + int a_len, padding_len; + u16 nSubframe_Length; + u8 nr_subframes, i; + u8 *pdata; + _pkt *sub_pkt, *subframes[MAX_SUBFRAME_COUNT]; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); + int ret = _SUCCESS; + + nr_subframes = 0; + + recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); + + if (prframe->u.hdr.attrib.iv_len > 0) + recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); + + a_len = prframe->u.hdr.len; + + pdata = prframe->u.hdr.rx_data; + + while (a_len > ETH_HLEN) { + + /* Offset 12 denote 2 mac address */ + nSubframe_Length = RTW_GET_BE16(pdata + 12); + + if (a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length)) { + RTW_INFO("nRemain_Length is %d and nSubframe_Length is : %d\n", a_len, nSubframe_Length); + break; + } + + sub_pkt = rtw_os_alloc_msdu_pkt(prframe, nSubframe_Length, pdata); + if (sub_pkt == NULL) { + RTW_INFO("%s(): allocate sub packet fail !!!\n", __FUNCTION__); + break; + } + + /* move the data point to data content */ + pdata += ETH_HLEN; + a_len -= ETH_HLEN; + + subframes[nr_subframes++] = sub_pkt; + + if (nr_subframes >= MAX_SUBFRAME_COUNT) { + RTW_INFO("ParseSubframe(): Too many Subframes! Packets dropped!\n"); + break; + } + + pdata += nSubframe_Length; + a_len -= nSubframe_Length; + if (a_len != 0) { + padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4 - 1)); + if (padding_len == 4) + padding_len = 0; + + if (a_len < padding_len) { + RTW_INFO("ParseSubframe(): a_len < padding_len !\n"); + break; + } + pdata += padding_len; + a_len -= padding_len; + } + } + + for (i = 0; i < nr_subframes; i++) { + sub_pkt = subframes[i]; + + /* Indicat the packets to upper layer */ + if (sub_pkt) + rtw_os_recv_indicate_pkt(padapter, sub_pkt, &prframe->u.hdr.attrib); + } + + prframe->u.hdr.len = 0; + rtw_free_recvframe(prframe, pfree_recv_queue);/* free this recv_frame */ + + return ret; +} + +int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) +{ + PADAPTER padapter = preorder_ctrl->padapter; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + u8 wsize = preorder_ctrl->wsize_b; + u16 wend = (preorder_ctrl->indicate_seq + wsize - 1) & 0xFFF; /* % 4096; */ + + /* Rx Reorder initialize condition. */ + if (preorder_ctrl->indicate_seq == 0xFFFF) { + preorder_ctrl->indicate_seq = seq_num; + + /* DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq); */ + } + + /* DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ + + /* Drop out the packet which SeqNum is smaller than WinStart */ + if (SN_LESS(seq_num, preorder_ctrl->indicate_seq)) { + /* DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ + + + return _FALSE; + } + + /* */ + /* Sliding window manipulation. Conditions includes: */ + /* 1. Incoming SeqNum is equal to WinStart =>Window shift 1 */ + /* 2. Incoming SeqNum is larger than the WinEnd => Window shift N */ + /* */ + if (SN_EQUAL(seq_num, preorder_ctrl->indicate_seq)) { + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; + + } else if (SN_LESS(wend, seq_num)) { + /* DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ + + /* boundary situation, when seq_num cross 0xFFF */ + if (seq_num >= (wsize - 1)) + preorder_ctrl->indicate_seq = seq_num + 1 - wsize; + else + preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1; + pdbgpriv->dbg_rx_ampdu_window_shift_cnt++; + } + + /* DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); */ + + return _TRUE; +} + +int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + _list *phead, *plist; + union recv_frame *pnextrframe; + struct rx_pkt_attrib *pnextattrib; + + /* DbgPrint("+enqueue_reorder_recvframe()\n"); */ + + /* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */ + + phead = get_list_head(ppending_recvframe_queue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u); + pnextattrib = &pnextrframe->u.hdr.attrib; + + if (SN_LESS(pnextattrib->seq_num, pattrib->seq_num)) + plist = get_next(plist); + else if (SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) { + /* Duplicate entry is found!! Do not insert current entry. */ + + /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + + return _FALSE; + } else + break; + + /* DbgPrint("enqueue_reorder_recvframe():while\n"); */ + + } + + /* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */ + + rtw_list_delete(&(prframe->u.hdr.list)); + + rtw_list_insert_tail(&(prframe->u.hdr.list), plist); + + /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ + /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + + return _TRUE; + +} + +void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq) +{ + if (current_seq < prev_seq) + pdbgpriv->dbg_rx_ampdu_loss_count += (4096 + current_seq - prev_seq); + + else + pdbgpriv->dbg_rx_ampdu_loss_count += (current_seq - prev_seq); +} +int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) +{ + /* _irqL irql; */ + _list *phead, *plist; + union recv_frame *prframe; + struct rx_pkt_attrib *pattrib; + /* u8 index = 0; */ + int bPktInBuf = _FALSE; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder); + + /* DbgPrint("+recv_indicatepkts_in_order\n"); */ + + /* _enter_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinlock_ex(&ppending_recvframe_queue->lock); */ + + phead = get_list_head(ppending_recvframe_queue); + plist = get_next(phead); + + /* Handling some condition for forced indicate case. */ + if (bforced == _TRUE) { + pdbgpriv->dbg_rx_ampdu_forced_indicate_count++; + if (rtw_is_list_empty(phead)) { + /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ + return _TRUE; + } + + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + pattrib = &prframe->u.hdr.attrib; + + recv_indicatepkts_pkt_loss_cnt(pdbgpriv, preorder_ctrl->indicate_seq, pattrib->seq_num); + preorder_ctrl->indicate_seq = pattrib->seq_num; + + } + + /* Prepare indication list and indication. */ + /* Check if there is any packet need indicate. */ + while (!rtw_is_list_empty(phead)) { + + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + pattrib = &prframe->u.hdr.attrib; + + if (!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) { + plist = get_next(plist); + rtw_list_delete(&(prframe->u.hdr.list)); + + if (SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) { + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; + } + + /* Set this as a lock to make sure that only one thread is indicating packet. */ + /* pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; */ + + /* Indicate packets */ + /* RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!!\n")); */ + + /* indicate this recv_frame */ + /* DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); */ + if (!pattrib->amsdu) { + /* RTW_INFO("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num); */ + + if (!RTW_CANNOT_RUN(padapter)) + rtw_recv_indicatepkt(padapter, prframe);/*indicate this recv_frame*/ + + } else if (pattrib->amsdu == 1) { + if (amsdu_to_msdu(padapter, prframe) != _SUCCESS) + rtw_free_recvframe(prframe, &precvpriv->free_recv_queue); + } else { + /* error condition; */ + } + + /* Update local variables. */ + bPktInBuf = _FALSE; + + } else { + bPktInBuf = _TRUE; + break; + } + + /* DbgPrint("recv_indicatepkts_in_order():while\n"); */ + + } + + /* _rtw_spinunlock_ex(&ppending_recvframe_queue->lock); */ + /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + + /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + + /* return _TRUE; */ + return bPktInBuf; + +} + +int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) +{ + _irqL irql; + int retval = _SUCCESS; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder); + + if (!pattrib->amsdu) { + /* s1. */ + retval = wlanhdr_to_ethhdr(prframe); + if (retval != _SUCCESS) { + return retval; + } + + /* if ((pattrib->qos!=1) || pattrib->priority!=0 || IS_MCAST(pattrib->ra) */ + /* || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0)) */ + if (pattrib->qos != 1) { + if (!RTW_CANNOT_RUN(padapter)) { + + rtw_recv_indicatepkt(padapter, prframe); + return _SUCCESS; + + } + + + return _FAIL; + + } + + if (preorder_ctrl->enable == _FALSE) { + /* indicate this recv_frame */ + preorder_ctrl->indicate_seq = pattrib->seq_num; + + rtw_recv_indicatepkt(padapter, prframe); + + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096; + + return _SUCCESS; + } + + + } else if (pattrib->amsdu == 1) { /* temp filter->means didn't support A-MSDUs in a A-MPDU */ + if (preorder_ctrl->enable == _FALSE) { + preorder_ctrl->indicate_seq = pattrib->seq_num; + + retval = amsdu_to_msdu(padapter, prframe); + + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) % 4096; + + if (retval != _SUCCESS) { + } + + return retval; + } + } else { + + } + + _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); + + /* s2. check if winstart_b(indicate_seq) needs to been updated */ + if (!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) { + pdbgpriv->dbg_rx_ampdu_drop_count++; + /* pHTInfo->RxReorderDropCounter++; */ + /* ReturnRFDList(Adapter, pRfd); */ + /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* return _FAIL; */ + + goto _err_exit; + } + + /* s3. Insert all packet into Reorder Queue to maintain its ordering. */ + if (!enqueue_reorder_recvframe(preorder_ctrl, prframe)) { + /* DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); */ + /* _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); */ + /* return _FAIL; */ + goto _err_exit; + } + + /* s4. */ + /* Indication process. */ + /* After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets */ + /* with the SeqNum smaller than latest WinStart and buffer other packets. */ + /* */ + /* For Rx Reorder condition: */ + /* 1. All packets with SeqNum smaller than WinStart => Indicate */ + /* 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. */ + /* */ + + if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE) == _TRUE) { + if (!preorder_ctrl->bReorderWaiting) { + preorder_ctrl->bReorderWaiting = _TRUE; + _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); + } + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + } else { + preorder_ctrl->bReorderWaiting = _FALSE; + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); + } + + + return _SUCCESS; + +_err_exit: + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + + return _FAIL; +} + +void rtw_reordering_ctrl_timeout_handler(void *pcontext) +{ + _irqL irql; + struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext; + _adapter *padapter = preorder_ctrl->padapter; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + + if (RTW_CANNOT_RUN(padapter)) + return; + + /* RTW_INFO("+rtw_reordering_ctrl_timeout_handler()=>\n"); */ + + _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); + + if (preorder_ctrl) + preorder_ctrl->bReorderWaiting = _FALSE; + + if (recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE) == _TRUE) + _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); + + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + +} + +int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) +{ + int retval = _SUCCESS; + /* struct recv_priv *precvpriv = &padapter->recvpriv; */ + /* struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; */ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate); + + if (phtpriv->ht_option == _TRUE) /* B/G/N Mode */ + { + /* prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority]; */ + + if (recv_indicatepkt_reorder(padapter, prframe) != _SUCCESS) { /* including perform A-MPDU Rx Ordering Buffer Control */ + + if (!RTW_CANNOT_RUN(padapter)) { + retval = _FAIL; + return retval; + } + } + } else /* B/G mode */ + { + retval = wlanhdr_to_ethhdr(prframe); + if (retval != _SUCCESS) { + return retval; + } + + if (!RTW_CANNOT_RUN(padapter)) { + /* indicate this recv_frame */ + rtw_recv_indicatepkt(padapter, prframe); + } else { + + retval = _FAIL; + return retval; + } + + } + + return retval; + +} + +int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) +{ + int ret = _SUCCESS; + u8 *ptr = precv_frame->u.hdr.rx_data; + u8 type, subtype; + struct mp_priv *pmppriv = &adapter->mppriv; + struct mp_tx *pmptx; + unsigned char *sa , *da, *bs; + + pmptx = &pmppriv->tx; + + if (pmppriv->bloopback) { + if (_rtw_memcmp(ptr + 24, pmptx->buf + 24, precv_frame->u.hdr.len - 24) == _FALSE) { + RTW_INFO("Compare payload content Fail !!!\n"); + ret = _FAIL; + } + } + if (pmppriv->bSetRxBssid == _TRUE) { + + sa = get_addr2_ptr(ptr); + da = GetAddr1Ptr(ptr); + bs = GetAddr3Ptr(ptr); + type = GetFrameType(ptr); + subtype = get_frame_sub_type(ptr); /* bit(7)~bit(2) */ + + if (_rtw_memcmp(bs, adapter->mppriv.network_macaddr, ETH_ALEN) == _FALSE) + ret = _FAIL; + + RTW_DBG("############ type:0x%02x subtype:0x%02x #################\n", type, subtype); + RTW_DBG("A2 sa %02X:%02X:%02X:%02X:%02X:%02X \n", *(sa) , *(sa + 1), *(sa+ 2), *(sa + 3), *(sa + 4), *(sa + 5)); + RTW_DBG("A1 da %02X:%02X:%02X:%02X:%02X:%02X \n", *(da) , *(da + 1), *(da+ 2), *(da + 3), *(da + 4), *(da + 5)); + RTW_DBG("A3 bs %02X:%02X:%02X:%02X:%02X:%02X \n --------------------------\n", *(bs) , *(bs + 1), *(bs+ 2), *(bs + 3), *(bs + 4), *(bs + 5)); + } + + if (!adapter->mppriv.bmac_filter) + return ret; + + if (_rtw_memcmp(get_addr2_ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE) + ret = _FAIL; + + return ret; +} + +static sint MPwlanhdr_to_ethhdr(union recv_frame *precvframe) +{ + sint rmv_len; + u16 eth_type, len; + u8 bsnaphdr; + u8 *psnap_type; + u8 mcastheadermac[] = {0x01, 0x00, 0x5e}; + + struct ieee80211_snap_hdr *psnap; + + sint ret = _SUCCESS; + _adapter *adapter = precvframe->u.hdr.adapter; + + u8 *ptr = get_recvframe_data(precvframe) ; /* point to frame_ctrl field */ + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + + if (pattrib->encrypt) + recvframe_pull_tail(precvframe, pattrib->icv_len); + + psnap = (struct ieee80211_snap_hdr *)(ptr + pattrib->hdrlen + pattrib->iv_len); + psnap_type = ptr + pattrib->hdrlen + pattrib->iv_len + SNAP_SIZE; + /* convert hdr + possible LLC headers into Ethernet header */ + /* eth_type = (psnap_type[0] << 8) | psnap_type[1]; */ + if ((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2) == _FALSE)) || + /* eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || */ + _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)) { + /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ + bsnaphdr = _TRUE; + } else { + /* Leave Ethernet header part of hdr and full payload */ + bsnaphdr = _FALSE; + } + + rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); + len = precvframe->u.hdr.len - rmv_len; + + _rtw_memcpy(ð_type, ptr + rmv_len, 2); + eth_type = ntohs((unsigned short)eth_type); /* pattrib->ether_type */ + pattrib->eth_type = eth_type; + + { + ptr = recvframe_pull(precvframe, (rmv_len - sizeof(struct ethhdr) + (bsnaphdr ? 2 : 0))); + } + + _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); + _rtw_memcpy(ptr + ETH_ALEN, pattrib->src, ETH_ALEN); + + if (!bsnaphdr) { + len = htons(len); + _rtw_memcpy(ptr + 12, &len, 2); + } + + len = htons(pattrib->seq_num); + /* RTW_INFO("wlan seq = %d ,seq_num =%x\n",len,pattrib->seq_num); */ + _rtw_memcpy(ptr + 12, &len, 2); + if (adapter->mppriv.bRTWSmbCfg == _TRUE) { + /* if(_rtw_memcmp(mcastheadermac, pattrib->dst, 3) == _TRUE) */ /* SimpleConfig Dest. */ + /* _rtw_memcpy(ptr+ETH_ALEN, pattrib->bssid, ETH_ALEN); */ + + if (_rtw_memcmp(mcastheadermac, pattrib->bssid, 3) == _TRUE) /* SimpleConfig Dest. */ + _rtw_memcpy(ptr, pattrib->bssid, ETH_ALEN); + + } + + return ret; + +} + +int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) +{ + int ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mp_priv *pmppriv = &padapter->mppriv; + u8 type; + u8 *ptr = rframe->u.hdr.rx_data; + u8 *psa, *pda, *pbssid; + struct sta_info *psta = NULL; + DBG_COUNTER(padapter->rx_logs.core_rx_pre); + + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { /* &&(padapter->mppriv.check_mp_pkt == 0)) */ + if (pattrib->crc_err == 1) + padapter->mppriv.rx_crcerrpktcount++; + else { + if (_SUCCESS == validate_mp_recv_frame(padapter, rframe)) + padapter->mppriv.rx_pktcount++; + else + padapter->mppriv.rx_pktcount_filter_out++; + } + + if (pmppriv->rx_bindicatePkt == _FALSE) { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + goto exit; + } else { + type = GetFrameType(ptr); + pattrib->to_fr_ds = get_tofr_ds(ptr); + pattrib->frag_num = GetFragNum(ptr); + pattrib->seq_num = GetSequence(ptr); + pattrib->pw_save = GetPwrMgt(ptr); + pattrib->mfrag = GetMFrag(ptr); + pattrib->mdata = GetMData(ptr); + pattrib->privacy = GetPrivacy(ptr); + pattrib->order = GetOrder(ptr); + + if (type == WIFI_DATA_TYPE) { + pda = get_da(ptr); + psa = get_sa(ptr); + pbssid = get_hdr_bssid(ptr); + + _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); + _rtw_memcpy(pattrib->src, psa, ETH_ALEN); + _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); + + switch (pattrib->to_fr_ds) { + case 0: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2sta_data_frame(padapter, rframe, &psta); + break; + + case 1: + + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); + ret = ap2sta_data_frame(padapter, rframe, &psta); + + break; + + case 2: + _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2ap_data_frame(padapter, rframe, &psta); + break; + + case 3: + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_addr2_ptr(ptr), ETH_ALEN); + ret = _FAIL; + break; + + default: + ret = _FAIL; + break; + } + + ret = MPwlanhdr_to_ethhdr(rframe); + + if (ret != _SUCCESS) { + rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + ret = _FAIL; + goto exit; + } + if (!RTW_CANNOT_RUN(padapter)) { + /* indicate this recv_frame */ + ret = rtw_recv_indicatepkt(padapter, rframe); + if (ret != _SUCCESS) { + rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + ret = _FAIL; + + goto exit; + } + } else { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + goto exit; + } + + } + } + + } + + rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + ret = _FAIL; + +exit: + return ret; + +} + +static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, u8 *buf) +{ +#define CHAN2FREQ(a) ((a < 14) ? (2407+5*a) : (5000+5*a)) + +#ifndef IEEE80211_RADIOTAP_RX_FLAGS +#define IEEE80211_RADIOTAP_RX_FLAGS 14 +#endif + +#ifndef IEEE80211_RADIOTAP_MCS +#define IEEE80211_RADIOTAP_MCS 19 +#endif +#ifndef IEEE80211_RADIOTAP_VHT +#define IEEE80211_RADIOTAP_VHT 21 +#endif + +#ifndef IEEE80211_RADIOTAP_F_BADFCS +#define IEEE80211_RADIOTAP_F_BADFCS 0x40 /* bad FCS */ +#endif + + sint ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + u16 tmp_16bit = 0; + + u8 data_rate[] = { + 2, 4, 11, 22, /* CCK */ + 12, 18, 24, 36, 48, 72, 93, 108, /* OFDM */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* HT MCS index */ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 1 */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 2 */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 3 */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 4 */ + }; + + _pkt *pskb = NULL; + + struct ieee80211_radiotap_header *rtap_hdr = NULL; + u8 *ptr = NULL; + + u8 hdr_buf[64] = {0}; + u16 rt_len = 8; + + /* create header */ + rtap_hdr = (struct ieee80211_radiotap_header *)&hdr_buf[0]; + rtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION; + + /* tsft */ + if (pattrib->tsfl) { + u64 tmp_64bit; + + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_TSFT); + tmp_64bit = cpu_to_le64(pattrib->tsfl); + memcpy(&hdr_buf[rt_len], &tmp_64bit, 8); + rt_len += 8; + } + + /* flags */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_FLAGS); + if (0) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_CFP; + + if (0) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_SHORTPRE; + + if ((pattrib->encrypt == 1) || (pattrib->encrypt == 5)) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_WEP; + + if (pattrib->mfrag) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FRAG; + + /* always append FCS */ + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FCS; + + if (0) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_DATAPAD; + + if (pattrib->crc_err) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_BADFCS; + + if (pattrib->sgi) { + /* Currently unspecified but used */ + hdr_buf[rt_len] |= 0x80; + } + rt_len += 1; + + /* rate */ + if (pattrib->data_rate < 12) { + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RATE); + if (pattrib->data_rate < 4) { + /* CCK */ + hdr_buf[rt_len] = data_rate[pattrib->data_rate]; + } else { + /* OFDM */ + hdr_buf[rt_len] = data_rate[pattrib->data_rate]; + } + } + rt_len += 1; /* force padding 1 byte for aligned */ + + /* channel */ + tmp_16bit = 0; + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_CHANNEL); + tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter)); + /*tmp_16bit = CHAN2FREQ(pHalData->current_channel);*/ + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 2; + + /* channel flags */ + tmp_16bit = 0; + if (pHalData->current_band_type == 0) + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ); + else + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ); + + if (pattrib->data_rate < 12) { + if (pattrib->data_rate < 4) { + /* CCK */ + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK); + } else { + /* OFDM */ + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_OFDM); + } + } else + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_DYN); + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 2; + + /* dBm Antenna Signal */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL); + hdr_buf[rt_len] = pattrib->phy_info.RecvSignalPower; + rt_len += 1; + + /* Antenna */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_ANTENNA); + hdr_buf[rt_len] = 0; /* pHalData->rf_type; */ + rt_len += 1; + + /* RX flags */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RX_FLAGS); + rt_len += 2; + + /* MCS information */ + if (pattrib->data_rate >= 12 && pattrib->data_rate < 44) { + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_MCS); + /* known, flag */ + hdr_buf[rt_len] |= BIT1; /* MCS index known */ + + /* bandwidth */ + hdr_buf[rt_len] |= BIT0; + hdr_buf[rt_len + 1] |= (pattrib->bw & 0x03); + + /* guard interval */ + hdr_buf[rt_len] |= BIT2; + hdr_buf[rt_len + 1] |= (pattrib->sgi & 0x01) << 2; + + /* STBC */ + hdr_buf[rt_len] |= BIT5; + hdr_buf[rt_len + 1] |= (pattrib->stbc & 0x03) << 5; + + rt_len += 2; + + /* MCS rate index */ + hdr_buf[rt_len] = data_rate[pattrib->data_rate]; + rt_len += 1; + } + + /* VHT */ + if (pattrib->data_rate >= 44 && pattrib->data_rate < 84) { + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_VHT); + + /* known 16 bit, flag 8 bit */ + tmp_16bit = 0; + + /* Bandwidth */ + tmp_16bit |= BIT6; + + /* Group ID */ + tmp_16bit |= BIT7; + + /* Partial AID */ + tmp_16bit |= BIT8; + + /* STBC */ + tmp_16bit |= BIT0; + hdr_buf[rt_len + 2] |= (pattrib->stbc & 0x01); + + /* Guard interval */ + tmp_16bit |= BIT2; + hdr_buf[rt_len + 2] |= (pattrib->sgi & 0x01) << 2; + + /* LDPC extra OFDM symbol */ + tmp_16bit |= BIT4; + hdr_buf[rt_len + 2] |= (pattrib->ldpc & 0x01) << 4; + + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 3; + + /* bandwidth */ + if (pattrib->bw == 0) + hdr_buf[rt_len] |= 0; + else if (pattrib->bw == 1) + hdr_buf[rt_len] |= 1; + else if (pattrib->bw == 2) + hdr_buf[rt_len] |= 4; + else if (pattrib->bw == 3) + hdr_buf[rt_len] |= 11; + rt_len += 1; + + /* mcs_nss */ + if (pattrib->data_rate >= 44 && pattrib->data_rate < 54) { + hdr_buf[rt_len] |= 1; + hdr_buf[rt_len] |= data_rate[pattrib->data_rate] << 4; + } else if (pattrib->data_rate >= 54 && pattrib->data_rate < 64) { + hdr_buf[rt_len + 1] |= 2; + hdr_buf[rt_len + 1] |= data_rate[pattrib->data_rate] << 4; + } else if (pattrib->data_rate >= 64 && pattrib->data_rate < 74) { + hdr_buf[rt_len + 2] |= 3; + hdr_buf[rt_len + 2] |= data_rate[pattrib->data_rate] << 4; + } else if (pattrib->data_rate >= 74 && pattrib->data_rate < 84) { + hdr_buf[rt_len + 3] |= 4; + hdr_buf[rt_len + 3] |= data_rate[pattrib->data_rate] << 4; + } + rt_len += 4; + + /* coding */ + hdr_buf[rt_len] = 0; + rt_len += 1; + + /* group_id */ + hdr_buf[rt_len] = 0; + rt_len += 1; + + /* partial_aid */ + tmp_16bit = 0; + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 2; + } + + /* push to skb */ + pskb = (_pkt *)buf; + if (skb_headroom(pskb) < rt_len) { + RTW_INFO("%s:%d %s headroom is too small.\n", __FILE__, __LINE__, __func__); + ret = _FAIL; + return ret; + } + + ptr = skb_push(pskb, rt_len); + if (ptr) { + rtap_hdr->it_len = cpu_to_le16(rt_len); + memcpy(ptr, rtap_hdr, rt_len); + } else + ret = _FAIL; + + return ret; + +} +int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe) +{ + int ret = _SUCCESS; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + _pkt *pskb = NULL; + + /* read skb information from recv frame */ + pskb = rframe->u.hdr.pkt; + pskb->len = rframe->u.hdr.len; + pskb->data = rframe->u.hdr.rx_data; + skb_set_tail_pointer(pskb, rframe->u.hdr.len); + + /* fill radiotap header */ + if (fill_radiotap_hdr(padapter, rframe, (u8 *)pskb) == _FAIL) { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */ + goto exit; + } + + /* write skb information to recv frame */ + skb_reset_mac_header(pskb); + rframe->u.hdr.len = pskb->len; + rframe->u.hdr.rx_data = pskb->data; + rframe->u.hdr.rx_head = pskb->head; + rframe->u.hdr.rx_tail = skb_tail_pointer(pskb); + rframe->u.hdr.rx_end = skb_end_pointer(pskb); + + if (!RTW_CANNOT_RUN(padapter)) { + /* indicate this recv_frame */ + ret = rtw_recv_monitor(padapter, rframe); + if (ret != _SUCCESS) { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */ + goto exit; + } + } else { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */ + goto exit; + } + +exit: + return ret; +} +int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) +{ + int ret = _SUCCESS; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + + if (padapter->registrypriv.mp_mode == 1 || padapter->mppriv.bRTWSmbCfg == _TRUE) { + mp_recv_frame(padapter, rframe); + ret = _FAIL; + goto exit; + } else + { + /* check the frame crtl field and decache */ + ret = validate_recv_frame(padapter, rframe); + if (ret != _SUCCESS) { + rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + goto exit; + } + } +exit: + return ret; +} + +/*#define DBG_RX_BMC_FRAME*/ +int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) +{ + int ret = _SUCCESS; + union recv_frame *orig_prframe = prframe; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + + DBG_COUNTER(padapter->rx_logs.core_rx_post); + + /* DATA FRAME */ + rtw_led_control(padapter, LED_CTL_RX); + + prframe = decryptor(padapter, prframe); + if (prframe == NULL) { + ret = _FAIL; + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err); + goto _recv_data_drop; + } + +#ifdef DBG_RX_BMC_FRAME + if (IS_MCAST(pattrib->ra)) { + u8 *pbuf = prframe->u.hdr.rx_data; + u8 *sa_addr = get_sa(pbuf); + + RTW_INFO("%s =>"ADPT_FMT" Rx BC/MC from MAC: "MAC_FMT"\n", __func__, ADPT_ARG(padapter), MAC_ARG(sa_addr)); + } +#endif + + prframe = recvframe_chk_defrag(padapter, prframe); + if (prframe == NULL) { + DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err); + goto _recv_data_drop; + } + + prframe = portctrl(padapter, prframe); + if (prframe == NULL) { + ret = _FAIL; + DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err); + goto _recv_data_drop; + } + + count_rx_stats(padapter, prframe, NULL); + + ret = process_recv_indicatepkts(padapter, prframe); + if (ret != _SUCCESS) { + rtw_free_recvframe(orig_prframe, pfree_recv_queue);/* free this recv_frame */ + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_err); + goto _recv_data_drop; + } + + return ret; + +_recv_data_drop: + precvpriv->rx_drop++; + return ret; +} + +int recv_func(_adapter *padapter, union recv_frame *rframe) +{ + int ret; + struct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib; + struct recv_priv *recvpriv = &padapter->recvpriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + + if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE)) { + /* monitor mode */ + recv_frame_monitor(padapter, rframe); + ret = _SUCCESS; + goto exit; + } else + + /* check if need to handle uc_swdec_pending_queue*/ + if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) { + union recv_frame *pending_frame; + int cnt = 0; + + while ((pending_frame = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) { + cnt++; + DBG_COUNTER(padapter->rx_logs.core_rx_dequeue); + recv_func_posthandle(padapter, pending_frame); + } + + if (cnt) + RTW_INFO(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n", + FUNC_ADPT_ARG(padapter), cnt); + } + + DBG_COUNTER(padapter->rx_logs.core_rx); + ret = recv_func_prehandle(padapter, rframe); + + if (ret == _SUCCESS) { + + /* check if need to enqueue into uc_swdec_pending_queue*/ + if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && + !IS_MCAST(prxattrib->ra) && prxattrib->encrypt > 0 && + (prxattrib->bdecrypted == 0 || psecuritypriv->sw_decrypt == _TRUE) && + psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK && + !psecuritypriv->busetkipkey) { + DBG_COUNTER(padapter->rx_logs.core_rx_enqueue); + rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue); + /* RTW_INFO("%s: no key, enqueue uc_swdec_pending_queue\n", __func__); */ + + if (recvpriv->free_recvframe_cnt < NR_RECVFRAME / 4) { + /* to prevent from recvframe starvation, get recvframe from uc_swdec_pending_queue to free_recvframe_cnt */ + rframe = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue); + if (rframe) + goto do_posthandle; + } + goto exit; + } + +do_posthandle: + ret = recv_func_posthandle(padapter, rframe); + } + +exit: + return ret; +} + +s32 rtw_recv_entry(union recv_frame *precvframe) +{ + _adapter *padapter; + struct recv_priv *precvpriv; + s32 ret = _SUCCESS; + + padapter = precvframe->u.hdr.adapter; + + precvpriv = &padapter->recvpriv; + + ret = recv_func(padapter, precvframe); + if (ret == _FAIL) { + goto _recv_entry_drop; + } + + precvpriv->rx_pkts++; + + return ret; + +_recv_entry_drop: + + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.rx_pktloss = precvpriv->rx_drop; + + return ret; +} + +static void rtw_signal_stat_timer_hdl(void *ctx) +{ + _adapter *adapter = (_adapter *)ctx; + struct recv_priv *recvpriv = &adapter->recvpriv; + + u32 tmp_s, tmp_q; + u8 avg_signal_strength = 0; + u8 avg_signal_qual = 0; + u32 num_signal_strength = 0; + u32 num_signal_qual = 0; + u8 ratio_pre_stat = 0, ratio_curr_stat = 0, ratio_total = 0, ratio_profile = SIGNAL_STAT_CALC_PROFILE_0; + + if (adapter->recvpriv.is_signal_dbg) { + /* update the user specific value, signal_strength_dbg, to signal_strength, rssi */ + adapter->recvpriv.signal_strength = adapter->recvpriv.signal_strength_dbg; + adapter->recvpriv.rssi = (s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg); + } else { + + if (recvpriv->signal_strength_data.update_req == 0) { /* update_req is clear, means we got rx */ + avg_signal_strength = recvpriv->signal_strength_data.avg_val; + num_signal_strength = recvpriv->signal_strength_data.total_num; + /* after avg_vals are accquired, we can re-stat the signal values */ + recvpriv->signal_strength_data.update_req = 1; + } + + if (recvpriv->signal_qual_data.update_req == 0) { /* update_req is clear, means we got rx */ + avg_signal_qual = recvpriv->signal_qual_data.avg_val; + num_signal_qual = recvpriv->signal_qual_data.total_num; + /* after avg_vals are accquired, we can re-stat the signal values */ + recvpriv->signal_qual_data.update_req = 1; + } + + if (num_signal_strength == 0) { + if (rtw_get_on_cur_ch_time(adapter) == 0 + || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval + ) + goto set_timer; + } + + if (check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE + || check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _FALSE + ) + goto set_timer; + + + if (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX) + ratio_profile = RTW_SIGNAL_STATE_CALC_PROFILE; + + ratio_pre_stat = signal_stat_calc_profile[ratio_profile][0]; + ratio_curr_stat = signal_stat_calc_profile[ratio_profile][1]; + ratio_total = ratio_pre_stat + ratio_curr_stat; + + /* update value of signal_strength, rssi, signal_qual */ + tmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvpriv->signal_strength); + if (tmp_s % ratio_total) + tmp_s = tmp_s / ratio_total + 1; + else + tmp_s = tmp_s / ratio_total; + if (tmp_s > 100) + tmp_s = 100; + + tmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvpriv->signal_qual); + if (tmp_q % ratio_total) + tmp_q = tmp_q / ratio_total + 1; + else + tmp_q = tmp_q / ratio_total; + if (tmp_q > 100) + tmp_q = 100; + + recvpriv->signal_strength = tmp_s; + recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s); + recvpriv->signal_qual = tmp_q; + + } + +set_timer: + rtw_set_signal_stat_timer(recvpriv); + +} + +static void rx_process_rssi(_adapter *padapter, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct signal_stat *signal_stat = &padapter->recvpriv.signal_strength_data; + + if (signal_stat->update_req) { + signal_stat->total_num = 0; + signal_stat->total_val = 0; + signal_stat->update_req = 0; + } + + signal_stat->total_num++; + signal_stat->total_val += pattrib->phy_info.SignalStrength; + signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; +} + +static void rx_process_link_qual(_adapter *padapter, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib; + struct signal_stat *signal_stat; + + if (prframe == NULL || padapter == NULL) + return; + + pattrib = &prframe->u.hdr.attrib; + signal_stat = &padapter->recvpriv.signal_qual_data; + + /* RTW_INFO("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); */ + + if (signal_stat->update_req) { + signal_stat->total_num = 0; + signal_stat->total_val = 0; + signal_stat->update_req = 0; + } + + signal_stat->total_num++; + signal_stat->total_val += pattrib->phy_info.SignalQuality; + signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; + +} + +void rx_process_phy_info(_adapter *padapter, union recv_frame *rframe) +{ + /* Check RSSI */ + rx_process_rssi(padapter, rframe); + + /* Check PWDB */ + /* process_PWDB(padapter, rframe); */ + + /* UpdateRxSignalStatistics8192C(Adapter, pRfd); */ + + /* Check EVM */ + rx_process_link_qual(padapter, rframe); + rtw_store_phy_info(padapter, rframe); +} + +void rx_query_phy_status( + union recv_frame *precvframe, + u8 *pphy_status) +{ + PADAPTER padapter = precvframe->u.hdr.adapter; + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct _odm_phy_status_info_ *pPHYInfo = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); + u8 *wlanhdr; + struct _odm_per_pkt_info_ pkt_info; + u8 *sa; + struct sta_priv *pstapriv; + struct sta_info *psta = NULL; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + /* _irqL irqL; */ + + pkt_info.is_packet_match_bssid = _FALSE; + pkt_info.is_packet_to_self = _FALSE; + pkt_info.is_packet_beacon = _FALSE; + pkt_info.ppdu_cnt = pattrib->ppdu_cnt; + + wlanhdr = get_recvframe_data(precvframe); + + pkt_info.is_packet_match_bssid = (!IsFrameTypeCtrl(wlanhdr)) + && (!pattrib->icv_err) && (!pattrib->crc_err) + && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN); + + pkt_info.is_to_self = (!pattrib->icv_err) && (!pattrib->crc_err) + && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.is_packet_to_self = pkt_info.is_packet_match_bssid + && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.is_packet_beacon = pkt_info.is_packet_match_bssid + && (get_frame_sub_type(wlanhdr) == WIFI_BEACON); + + sa = get_ta(wlanhdr); + + pkt_info.station_id = 0xFF; + + if (_rtw_memcmp(adapter_mac_addr(padapter), sa, ETH_ALEN) == _TRUE) { + static u32 start_time = 0; + + if ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) { + RTW_PRINT("Warning!!! %s: Confilc mac addr!!\n", __func__); + start_time = rtw_get_current_time(); + } + pdbgpriv->dbg_rx_conflic_mac_addr_cnt++; + } else { + pstapriv = &padapter->stapriv; + psta = rtw_get_stainfo(pstapriv, sa); + if (psta) + pkt_info.station_id = psta->mac_id; + } + + pkt_info.data_rate = pattrib->data_rate; + + /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + odm_phy_status_query(&pHalData->odmpriv, pPHYInfo, pphy_status, &pkt_info); + if (psta) + psta->rssi = pattrib->phy_info.RecvSignalPower; + /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + + { + precvframe->u.hdr.psta = NULL; + if (pkt_info.is_packet_match_bssid + && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + ) { + if (psta) { + precvframe->u.hdr.psta = psta; + rx_process_phy_info(padapter, precvframe); + } + } else if (pkt_info.is_packet_to_self || pkt_info.is_packet_beacon) { + + if (psta) + precvframe->u.hdr.psta = psta; + rx_process_phy_info(padapter, precvframe); + } + } + + rtw_odm_parse_rx_phy_status_chinfo(precvframe, pphy_status); +} +/* +* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT +* @return _TRUE: +* @return _FALSE: +*/ +int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index) +{ + + int ret = _FALSE; + int value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]); + + if (value >= MAX_CONTINUAL_NORXPACKET_COUNT) + ret = _TRUE; + + return ret; +} + +/* +* Set the continual_no_rx_packet of this @param pmlmepriv to 0 +*/ +void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index) +{ + ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0); +} diff --git a/drivers/staging/rtl8821ce/core/rtw_rf.c b/drivers/staging/rtl8821ce/core/rtw_rf.c new file mode 100644 index 000000000000..697cb6e8c3a7 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_rf.c @@ -0,0 +1,937 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_RF_C_ + +#include <drv_types.h> +#include <hal_data.h> + +u8 center_ch_2g[CENTER_CH_2G_NUM] = { +/* G00 */1, 2, +/* G01 */3, 4, 5, +/* G02 */6, 7, 8, +/* G03 */9, 10, 11, +/* G04 */12, 13, +/* G05 */14 +}; + +u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM] = { + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, +}; + +u8 op_chs_of_cch_2g_40m[CENTER_CH_2G_40M_NUM][2] = { + {1, 5}, /* 3 */ + {2, 6}, /* 4 */ + {3, 7}, /* 5 */ + {4, 8}, /* 6 */ + {5, 9}, /* 7 */ + {6, 10}, /* 8 */ + {7, 11}, /* 9 */ + {8, 12}, /* 10 */ + {9, 13}, /* 11 */ +}; + +u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = { +/* G00 */36, 38, 40, + 42, +/* G01 */44, 46, 48, + /* 50, */ +/* G02 */52, 54, 56, + 58, +/* G03 */60, 62, 64, +/* G04 */100, 102, 104, + 106, +/* G05 */108, 110, 112, + /* 114, */ +/* G06 */116, 118, 120, + 122, +/* G07 */124, 126, 128, +/* G08 */132, 134, 136, + 138, +/* G09 */140, 142, 144, +/* G10 */149, 151, 153, + 155, +/* G11 */157, 159, 161, + /* 163, */ +/* G12 */165, 167, 169, + 171, +/* G13 */173, 175, 177 +}; + +u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = { +/* G00 */36, 40, +/* G01 */44, 48, +/* G02 */52, 56, +/* G03 */60, 64, +/* G04 */100, 104, +/* G05 */108, 112, +/* G06 */116, 120, +/* G07 */124, 128, +/* G08 */132, 136, +/* G09 */140, 144, +/* G10 */149, 153, +/* G11 */157, 161, +/* G12 */165, 169, +/* G13 */173, 177 +}; + +u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = { +/* G00 */38, +/* G01 */46, +/* G02 */54, +/* G03 */62, +/* G04 */102, +/* G05 */110, +/* G06 */118, +/* G07 */126, +/* G08 */134, +/* G09 */142, +/* G10 */151, +/* G11 */159, +/* G12 */167, +/* G13 */175 +}; + +u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM] = { +/* G00 */36, 38, 40, +/* G01 */44, 46, 48, +/* G02 */52, 54, 56, +/* G03 */60, 62, 64, +/* G04 */100, 102, 104, +/* G05 */108, 110, 112, +/* G06 */116, 118, 120, +/* G07 */124, 126, 128, +/* G08 */132, 134, 136, +/* G09 */140, 142, 144, +/* G10 */149, 151, 153, +/* G11 */157, 159, 161, +/* G12 */165, 167, 169, +/* G13 */173, 175, 177 +}; + +u8 op_chs_of_cch_5g_40m[CENTER_CH_5G_40M_NUM][2] = { + {36, 40}, /* 38 */ + {44, 48}, /* 46 */ + {52, 56}, /* 54 */ + {60, 64}, /* 62 */ + {100, 104}, /* 102 */ + {108, 112}, /* 110 */ + {116, 120}, /* 118 */ + {124, 128}, /* 126 */ + {132, 136}, /* 134 */ + {140, 144}, /* 142 */ + {149, 153}, /* 151 */ + {157, 161}, /* 159 */ + {165, 169}, /* 167 */ + {173, 177}, /* 175 */ +}; + +u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = { +/* G00 ~ G01*/42, +/* G02 ~ G03*/58, +/* G04 ~ G05*/106, +/* G06 ~ G07*/122, +/* G08 ~ G09*/138, +/* G10 ~ G11*/155, +/* G12 ~ G13*/171 +}; + +u8 op_chs_of_cch_5g_80m[CENTER_CH_5G_80M_NUM][4] = { + {36, 40, 44, 48}, /* 42 */ + {52, 56, 60, 64}, /* 58 */ + {100, 104, 108, 112}, /* 106 */ + {116, 120, 124, 128}, /* 122 */ + {132, 136, 140, 144}, /* 138 */ + {149, 153, 157, 161}, /* 155 */ + {165, 169, 173, 177}, /* 171 */ +}; + +u8 center_ch_5g_160m[CENTER_CH_5G_160M_NUM] = { +/* G00 ~ G03*/50, +/* G04 ~ G07*/114, +/* G10 ~ G13*/163 +}; + +u8 op_chs_of_cch_5g_160m[CENTER_CH_5G_160M_NUM][8] = { + {36, 40, 44, 48, 52, 56, 60, 64}, /* 50 */ + {100, 104, 108, 112, 116, 120, 124, 128}, /* 114 */ + {149, 153, 157, 161, 165, 169, 173, 177}, /* 163 */ +}; + +struct center_chs_ent_t { + u8 ch_num; + u8 *chs; +}; + +struct center_chs_ent_t center_chs_2g_by_bw[] = { + {CENTER_CH_2G_NUM, center_ch_2g}, + {CENTER_CH_2G_40M_NUM, center_ch_2g_40m}, +}; + +struct center_chs_ent_t center_chs_5g_by_bw[] = { + {CENTER_CH_5G_20M_NUM, center_ch_5g_20m}, + {CENTER_CH_5G_40M_NUM, center_ch_5g_40m}, + {CENTER_CH_5G_80M_NUM, center_ch_5g_80m}, + {CENTER_CH_5G_160M_NUM, center_ch_5g_160m}, +}; + +/* + * Get center channel of smaller bandwidth by @param cch, @param bw, @param offset + * @cch: the given center channel + * @bw: the given bandwidth + * @offset: the given primary SC offset of the given bandwidth + * + * return center channel of smaller bandiwdth if valid, or 0 + */ +u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset) +{ + u8 t_cch = 0; + + if (bw == CHANNEL_WIDTH_20) { + t_cch = cch; + goto exit; + } + + if (offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + rtw_warn_on(1); + goto exit; + } + + /* 2.4G, 40MHz */ + if (cch >= 3 && cch <= 11 && bw == CHANNEL_WIDTH_40) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; + goto exit; + } + + /* 5G, 160MHz */ + if (cch >= 50 && cch <= 163 && bw == CHANNEL_WIDTH_160) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 8 : cch - 8; + goto exit; + + /* 5G, 80MHz */ + } else if (cch >= 42 && cch <= 171 && bw == CHANNEL_WIDTH_80) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 4 : cch - 4; + goto exit; + + /* 5G, 40MHz */ + } else if (cch >= 38 && cch <= 175 && bw == CHANNEL_WIDTH_40) { + t_cch = (offset == HAL_PRIME_CHNL_OFFSET_UPPER) ? cch + 2 : cch - 2; + goto exit; + + } else { + rtw_warn_on(1); + goto exit; + } + +exit: + return t_cch; +} + +struct op_chs_ent_t { + u8 ch_num; + u8 *chs; +}; + +struct op_chs_ent_t op_chs_of_cch_2g_by_bw[] = { + {1, center_ch_2g}, + {2, (u8 *)op_chs_of_cch_2g_40m}, +}; + +struct op_chs_ent_t op_chs_of_cch_5g_by_bw[] = { + {1, center_ch_5g_20m}, + {2, (u8 *)op_chs_of_cch_5g_40m}, + {4, (u8 *)op_chs_of_cch_5g_80m}, + {8, (u8 *)op_chs_of_cch_5g_160m}, +}; + +inline u8 center_chs_2g_num(u8 bw) +{ + if (bw > CHANNEL_WIDTH_40) + return 0; + + return center_chs_2g_by_bw[bw].ch_num; +} + +inline u8 center_chs_5g_num(u8 bw) +{ + if (bw > CHANNEL_WIDTH_80) + return 0; + + return center_chs_5g_by_bw[bw].ch_num; +} + +inline u8 center_chs_5g(u8 bw, u8 id) +{ + if (bw > CHANNEL_WIDTH_80) + return 0; + + if (id >= center_chs_5g_num(bw)) + return 0; + + return center_chs_5g_by_bw[bw].chs[id]; +} + +/* + * Get available op channels by @param cch, @param bw + * @cch: the given center channel + * @bw: the given bandwidth + * @op_chs: the pointer to return pointer of op channel array + * @op_ch_num: the pointer to return pointer of op channel number + * + * return valid (1) or not (0) + */ +u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num) +{ + int i; + struct center_chs_ent_t *c_chs_ent = NULL; + struct op_chs_ent_t *op_chs_ent = NULL; + u8 valid = 1; + + if (cch <= 14 + && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_40 + ) { + c_chs_ent = ¢er_chs_2g_by_bw[bw]; + op_chs_ent = &op_chs_of_cch_2g_by_bw[bw]; + } else if (cch >= 36 && cch <= 177 + && bw >= CHANNEL_WIDTH_20 && bw <= CHANNEL_WIDTH_160 + ) { + c_chs_ent = ¢er_chs_5g_by_bw[bw]; + op_chs_ent = &op_chs_of_cch_5g_by_bw[bw]; + } else { + valid = 0; + goto exit; + } + + for (i = 0; i < c_chs_ent->ch_num; i++) + if (cch == *(c_chs_ent->chs + i)) + break; + + if (i == c_chs_ent->ch_num) { + valid = 0; + goto exit; + } + + *op_chs = op_chs_ent->chs + op_chs_ent->ch_num * i; + *op_ch_num = op_chs_ent->ch_num; + +exit: + return valid; +} + +u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group) +{ + BAND_TYPE band = BAND_MAX; + s8 gp = -1, cck_gp = -1; + + if (ch <= 14) { + band = BAND_ON_2_4G; + + if (1 <= ch && ch <= 2) + gp = 0; + else if (3 <= ch && ch <= 5) + gp = 1; + else if (6 <= ch && ch <= 8) + gp = 2; + else if (9 <= ch && ch <= 11) + gp = 3; + else if (12 <= ch && ch <= 14) + gp = 4; + else + band = BAND_MAX; + + if (ch == 14) + cck_gp = 5; + else + cck_gp = gp; + } else { + band = BAND_ON_5G; + + if (36 <= ch && ch <= 42) + gp = 0; + else if (44 <= ch && ch <= 48) + gp = 1; + else if (50 <= ch && ch <= 58) + gp = 2; + else if (60 <= ch && ch <= 64) + gp = 3; + else if (100 <= ch && ch <= 106) + gp = 4; + else if (108 <= ch && ch <= 114) + gp = 5; + else if (116 <= ch && ch <= 122) + gp = 6; + else if (124 <= ch && ch <= 130) + gp = 7; + else if (132 <= ch && ch <= 138) + gp = 8; + else if (140 <= ch && ch <= 144) + gp = 9; + else if (149 <= ch && ch <= 155) + gp = 10; + else if (157 <= ch && ch <= 161) + gp = 11; + else if (165 <= ch && ch <= 171) + gp = 12; + else if (173 <= ch && ch <= 177) + gp = 13; + else + band = BAND_MAX; + } + + if (band == BAND_MAX + || (band == BAND_ON_2_4G && cck_gp == -1) + || gp == -1 + ) { + RTW_WARN("%s invalid channel:%u", __func__, ch); + rtw_warn_on(1); + goto exit; + } + + if (group) + *group = gp; + if (cck_group && band == BAND_ON_2_4G) + *cck_group = cck_gp; + +exit: + return band; +} + +int rtw_ch2freq(int chan) +{ + /* see 802.11 17.3.8.3.2 and Annex J + * there are overlapping channel numbers in 5GHz and 2GHz bands */ + + /* + * RTK: don't consider the overlapping channel numbers: 5G channel <= 14, + * because we don't support it. simply judge from channel number + */ + + if (chan >= 1 && chan <= 14) { + if (chan == 14) + return 2484; + else if (chan < 14) + return 2407 + chan * 5; + } else if (chan >= 36 && chan <= 177) + return 5000 + chan * 5; + + return 0; /* not supported */ +} + +int rtw_freq2ch(int freq) +{ + /* see 802.11 17.3.8.3.2 and Annex J */ + if (freq == 2484) + return 14; + else if (freq < 2484) + return (freq - 2407) / 5; + else if (freq >= 4910 && freq <= 4980) + return (freq - 4000) / 5; + else if (freq <= 45000) /* DMG band lower limit */ + return (freq - 5000) / 5; + else if (freq >= 58320 && freq <= 64800) + return (freq - 56160) / 2160; + else + return 0; +} + +bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) +{ + u8 c_ch; + u32 freq; + u32 hi_ret = 0, lo_ret = 0; + bool valid = _FALSE; + + if (hi) + *hi = 0; + if (lo) + *lo = 0; + + c_ch = rtw_get_center_ch(ch, bw, offset); + freq = rtw_ch2freq(c_ch); + + if (!freq) { + rtw_warn_on(1); + goto exit; + } + + if (bw == CHANNEL_WIDTH_80) { + hi_ret = freq + 40; + lo_ret = freq - 40; + } else if (bw == CHANNEL_WIDTH_40) { + hi_ret = freq + 20; + lo_ret = freq - 20; + } else if (bw == CHANNEL_WIDTH_20) { + hi_ret = freq + 10; + lo_ret = freq - 10; + } else + rtw_warn_on(1); + + if (hi) + *hi = hi_ret; + if (lo) + *lo = lo_ret; + + valid = _TRUE; + +exit: + return valid; +} + +const char *const _ch_width_str[] = { + "20MHz", + "40MHz", + "80MHz", + "160MHz", + "80_80MHz", + "CHANNEL_WIDTH_MAX", +}; + +const u8 _ch_width_to_bw_cap[] = { + BW_CAP_20M, + BW_CAP_40M, + BW_CAP_80M, + BW_CAP_160M, + BW_CAP_80_80M, + 0, +}; + +const char *const _band_str[] = { + "2.4G", + "5G", + "BOTH", + "BAND_MAX", +}; + +const u8 _band_to_band_cap[] = { + BAND_CAP_2G, + BAND_CAP_5G, + 0, + 0, +}; + +const u8 _rf_type_to_rf_tx_cnt[] = { + 1, + 2, + 2, + 1, + 2, + 2, + 3, + 3, + 4, +}; + +const u8 _rf_type_to_rf_rx_cnt[] = { + 2, + 4, + 2, + 1, + 2, + 3, + 3, + 4, + 4, +}; + +#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val) + +#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) + +/* has def_module_flags specified, used by common map and HAL dfference map */ +#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \ + {.alpha2 = (_alpha2), .chplan = (_chplan) \ + COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \ + COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \ + } + + +static const struct country_chplan country_chplan_map[] = { + COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x000), /* Andorra */ + COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0x1FB), /* United Arab Emirates */ + COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x000), /* Afghanistan */ + COUNTRY_CHPLAN_ENT("AG", 0x30, 1, 0x000), /* Antigua & Barbuda */ + COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x000), /* Anguilla(UK) */ + COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0x1F1), /* Albania */ + COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0x0B0), /* Armenia */ + COUNTRY_CHPLAN_ENT("AO", 0x26, 1, 0x0E0), /* Angola */ + COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x000), /* Antarctica */ + COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0x1F3), /* Argentina */ + COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x000), /* American Samoa */ + COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0x1FB), /* Austria */ + COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0x1FB), /* Australia */ + COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0x0B0), /* Aruba */ + COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0x1F1), /* Azerbaijan */ + COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0x1F1), /* Bosnia & Herzegovina */ + COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x050), /* Barbados */ + COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0x1F1), /* Bangladesh */ + COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0x1FB), /* Belgium */ + COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0x0B0), /* Burkina Faso */ + COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0x1F1), /* Bulgaria */ + COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0x1F1), /* Bahrain */ + COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0x0B0), /* Burundi */ + COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0x0B0), /* Benin */ + COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x010), /* Brunei */ + COUNTRY_CHPLAN_ENT("BO", 0x30, 1, 0x1F1), /* Bolivia */ + COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0x1F1), /* Brazil */ + COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x020), /* Bahamas */ + COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0x0F1), /* Botswana */ + COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0x1F1), /* Belarus */ + COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x000), /* Belize */ + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0x1FB), /* Canada */ + COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x000), /* Cocos (Keeling) Islands (Australia) */ + COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0x0B0), /* Congo, Republic of the */ + COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0x0B0), /* Central African Republic */ + COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0x0B0), /* Congo, Democratic Republic of the. Zaire */ + COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0x1FB), /* Switzerland */ + COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0x1F1), /* Cote d'Ivoire */ + COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x000), /* Cook Islands */ + COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0x1F1), /* Chile */ + COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0x0B0), /* Cameroon */ + COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0x1FB), /* China */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0x1F1), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0x1F1), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0x0B0), /* Cape Verde */ + COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x000), /* Christmas Island (Australia) */ + COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0x1FB), /* Cyprus */ + COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0x1FB), /* Czech Republic */ + COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0x1FB), /* Germany */ + COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x080), /* Djibouti */ + COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0x1FB), /* Denmark */ + COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x000), /* Dominica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0x1F1), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0x1F1), /* Algeria */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0x1F1), /* Ecuador */ + COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0x1FB), /* Estonia */ + COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0x1F1), /* Egypt */ + COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x080), /* Western Sahara */ + COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x000), /* Eritrea */ + COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0x1FB), /* Spain, Canary Islands, Ceuta, Melilla */ + COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0x0B0), /* Ethiopia */ + COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0x1FB), /* Finland */ + COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x000), /* Fiji */ + COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x000), /* Falkland Islands (Islas Malvinas) (UK) */ + COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x000), /* Micronesia, Federated States of (USA) */ + COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x000), /* Faroe Islands (Denmark) */ + COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0x1FB), /* France */ + COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0x0B0), /* Gabon */ + COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0x1FB), /* Great Britain (United Kingdom; England) */ + COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0x0B0), /* Grenada */ + COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x000), /* Georgia */ + COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x080), /* French Guiana */ + COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x000), /* Guernsey (UK) */ + COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0x1F1), /* Ghana */ + COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x000), /* Gibraltar (UK) */ + COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x000), /* Greenland (Denmark) */ + COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0x0B0), /* Gambia */ + COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x010), /* Guinea */ + COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x000), /* Guadeloupe (France) */ + COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0x0B0), /* Equatorial Guinea */ + COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0x1FB), /* Greece */ + COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x000), /* South Georgia and the Sandwich Islands (UK) */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0x1F1), /* Guatemala */ + COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x000), /* Guam (USA) */ + COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0x0B0), /* Guinea-Bissau */ + COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x000), /* Guyana */ + COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0x1FB), /* Hong Kong */ + COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x000), /* Heard and McDonald Islands (Australia) */ + COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0x1F1), /* Honduras */ + COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0x1F9), /* Croatia */ + COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x050), /* Haiti */ + COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0x1FB), /* Hungary */ + COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0x1F3), /* Indonesia */ + COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0x1FB), /* Ireland */ + COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0x1F1), /* Israel */ + COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x000), /* Isle of Man (UK) */ + COUNTRY_CHPLAN_ENT("IN", 0x47, 1, 0x1F1), /* India */ + COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x000), /* Iraq */ + COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x000), /* Iran */ + COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0x1FB), /* Iceland */ + COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0x1FB), /* Italy */ + COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x000), /* Jersey (UK) */ + COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0x1F1), /* Jamaica */ + COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0x1FB), /* Jordan */ + COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0x1FF), /* Japan- Telec */ + COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0x1F9), /* Kenya */ + COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0x1F1), /* Kyrgyzstan */ + COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0x1F1), /* Cambodia */ + COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x000), /* Kiribati */ + COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x000), /* Saint Kitts and Nevis */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0x1FB), /* South Korea */ + COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0x1FB), /* Kuwait */ + COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x000), /* Cayman Islands (UK) */ + COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x100), /* Kazakhstan */ + COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x000), /* Laos */ + COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0x1F1), /* Lebanon */ + COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x000), /* Saint Lucia */ + COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0x1FB), /* Liechtenstein */ + COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0x1F1), /* Sri Lanka */ + COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0x0B0), /* Liberia */ + COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0x1F1), /* Lesotho */ + COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0x1FB), /* Lithuania */ + COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0x1FB), /* Luxembourg */ + COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0x1FB), /* Latvia */ + COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x000), /* Libya */ + COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0x1F1), /* Morocco */ + COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0x1FB), /* Monaco */ + COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0x1F1), /* Moldova */ + COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0x1F1), /* Montenegro */ + COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x000), /* Saint Martin */ + COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x020), /* Madagascar */ + COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x000), /* Marshall Islands (USA) */ + COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0x1F1), /* Republic of Macedonia (FYROM) */ + COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0x0B0), /* Mali */ + COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x000), /* Burma (Myanmar) */ + COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x000), /* Mongolia */ + COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x000), /* Macau */ + COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x000), /* Northern Mariana Islands (USA) */ + COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x040), /* Martinique (France) */ + COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0x0A0), /* Mauritania */ + COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x000), /* Montserrat (UK) */ + COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0x1FB), /* Malta */ + COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0x0B0), /* Mauritius */ + COUNTRY_CHPLAN_ENT("MV", 0x26, 1, 0x000), /* Maldives */ + COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0x0B0), /* Malawi */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0x1F1), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x63, 1, 0x1F1), /* Malaysia */ + COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0x1F1), /* Mozambique */ + COUNTRY_CHPLAN_ENT("NA", 0x26, 1, 0x100), /* Namibia */ + COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x000), /* New Caledonia */ + COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0x0B0), /* Niger */ + COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x000), /* Norfolk Island (Australia) */ + COUNTRY_CHPLAN_ENT("NG", 0x50, 1, 0x1F9), /* Nigeria */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0x1F1), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0x1FB), /* Netherlands */ + COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0x1FB), /* Norway */ + COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0x0F0), /* Nepal */ + COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x000), /* Nauru */ + COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x000), /* Niue */ + COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0x1FB), /* New Zealand */ + COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0x1F9), /* Oman */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0x1F1), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0x1F1), /* Peru */ + COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x000), /* French Polynesia (France) */ + COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0x1F1), /* Papua New Guinea */ + COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0x1F1), /* Philippines */ + COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0x1F1), /* Pakistan */ + COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0x1FB), /* Poland */ + COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x000), /* Saint Pierre and Miquelon (France) */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0x1F1), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0x1FB), /* Portugal */ + COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x000), /* Palau */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0x1F1), /* Paraguay */ + COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0x1F9), /* Qatar */ + COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x000), /* Reunion (France) */ + COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0x1F1), /* Romania */ + COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0x1F1), /* Serbia, Kosovo */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0x1FB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0x0B0), /* Rwanda */ + COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0x1FB), /* Saudi Arabia */ + COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x000), /* Solomon Islands */ + COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x090), /* Seychelles */ + COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0x1FB), /* Sweden */ + COUNTRY_CHPLAN_ENT("SG", 0x26, 1, 0x1FB), /* Singapore */ + COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x000), /* Saint Helena (UK) */ + COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0x1FB), /* Slovenia */ + COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x000), /* Svalbard (Norway) */ + COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0x1FB), /* Slovakia */ + COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0x0B0), /* Sierra Leone */ + COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x000), /* San Marino */ + COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0x1F1), /* Senegal */ + COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x000), /* Somalia */ + COUNTRY_CHPLAN_ENT("SR", 0x34, 1, 0x000), /* Suriname */ + COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x080), /* Sao Tome and Principe */ + COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0x1F1), /* El Salvador */ + COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x000), /* Sint Marteen */ + COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x020), /* Swaziland */ + COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x000), /* Turks and Caicos Islands (UK) */ + COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0x0B0), /* Chad */ + COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x080), /* French Southern and Antarctic Lands (FR Southern Territories) */ + COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0x0B0), /* Togo */ + COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0x1F1), /* Thailand */ + COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x040), /* Tajikistan */ + COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x000), /* Tokelau */ + COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x000), /* Turkmenistan */ + COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0x1F1), /* Tunisia */ + COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x000), /* Tonga */ + COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0x1F1), /* Turkey, Northern Cyprus */ + COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0x1F1), /* Trinidad & Tobago */ + COUNTRY_CHPLAN_ENT("TW", 0x62, 1, 0x1FF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0x0F0), /* Tanzania */ + COUNTRY_CHPLAN_ENT("UA", 0x36, 1, 0x1FB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0x0F1), /* Uganda */ + COUNTRY_CHPLAN_ENT("US", 0x62, 1, 0x1FF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("UY", 0x34, 1, 0x1F1), /* Uruguay */ + COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0x0F0), /* Uzbekistan */ + COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x000), /* Holy See (Vatican City) */ + COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x010), /* Saint Vincent and the Grenadines */ + COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0x1F1), /* Venezuela */ + COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x000), /* United States Virgin Islands (USA) */ + COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0x1F1), /* Vietnam */ + COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x000), /* Vanuatu */ + COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x000), /* Wallis and Futuna (France) */ + COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x000), /* Samoa */ + COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x040), /* Yemen */ + COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x080), /* Mayotte (France) */ + COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0x1F1), /* South Africa */ + COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0x0B0), /* Zambia */ + COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0x1F1), /* Zimbabwe */ +}; + +/* +* rtw_get_chplan_from_country - +* @country_code: string of country code +* +* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given +*/ +const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) +{ + const struct country_chplan *ent = NULL; + const struct country_chplan *map = NULL; + u16 map_sz = 0; + char code[2]; + int i; + + code[0] = alpha_to_upper(country_code[0]); + code[1] = alpha_to_upper(country_code[1]); + + + map = country_chplan_map; + map_sz = sizeof(country_chplan_map) / sizeof(struct country_chplan); + + for (i = 0; i < map_sz; i++) { + if (strncmp(code, map[i].alpha2, 2) == 0) { + ent = &map[i]; + break; + } + } + + return ent; +} + +s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) +{ + s8 kfree_offset = 0; + + return kfree_offset; +} + +void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) +{ + u8 target_path = 0; + u32 val32 = 0; + + if (IS_HARDWARE_TYPE_8723D(adapter)) { + target_path = RF_PATH_A; /*in 8723D case path means S0/S1*/ + if (path == PPG_8723D_S1) + RTW_INFO("kfree gain_offset 0x55:0x%x ", + rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff)); + else if (path == PPG_8723D_S0) + RTW_INFO("kfree gain_offset 0x65:0x%x ", + rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff)); + } else { + target_path = path; + RTW_INFO("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff)); + } + + switch (rtw_get_chip_type(adapter)) { + + case RTL8814A: + case RTL8822B: + case RTL8821C: + RTW_INFO("\nkfree by PhyDM on the sw CH. path %d\n", path); + break; + + default: + rtw_warn_on(1); + break; + } + + if (IS_HARDWARE_TYPE_8723D(adapter)) { + if (path == PPG_8723D_S1) + val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff); + else if (path == PPG_8723D_S0) + val32 = rtw_hal_read_rfreg(adapter, target_path, 0x65, 0xffffffff); + } else { + val32 = rtw_hal_read_rfreg(adapter, target_path, 0x55, 0xffffffff); + } + RTW_INFO(" after :0x%x\n", val32); +} + +inline u8 rtw_is_5g_band1(u8 ch) +{ + if (ch >= 36 && ch <= 48) + return 1; + return 0; +} + +inline u8 rtw_is_5g_band4(u8 ch) +{ + if (ch >= 149 && ch <= 177) + return 1; + return 0; +} + +inline u8 rtw_is_dfs_range(u32 hi, u32 lo) +{ + return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10); +} + +u8 rtw_is_dfs_ch(u8 ch) +{ + u32 hi, lo; + + if (!rtw_chbw_to_freq_range(ch, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, &hi, &lo)) + return 0; + + return rtw_is_dfs_range(hi, lo); +} + +u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset) +{ + u32 hi, lo; + + if (!rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo)) + return 0; + + return rtw_is_dfs_range(hi, lo); +} + +bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region) +{ + return (dfs_region == PHYDM_DFS_DOMAIN_ETSI && rtw_is_range_overlap(hi, lo, 5660 + 10, 5600 - 10)) ? _TRUE : _FALSE; +} + +bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region) +{ + u32 hi, lo; + + if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) + return _FALSE; + + return rtw_is_long_cac_range(hi, lo, dfs_region) ? _TRUE : _FALSE; +} diff --git a/drivers/staging/rtl8821ce/core/rtw_security.c b/drivers/staging/rtl8821ce/core/rtw_security.c new file mode 100644 index 000000000000..84142c7c4123 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_security.c @@ -0,0 +1,2038 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_SECURITY_C_ + +#include <drv_types.h> + +static const char *_security_type_str[] = { + "N/A", + "WEP40", + "TKIP", + "TKIP_WM", + "AES", + "WEP104", + "SMS4", + "WEP_WPA", + "BIP", +}; + +const char *security_type_str(u8 value) +{ + if (value <= _WEP_WPA_MIXED_) + return _security_type_str[value]; + return NULL; +} + +#define WEP_SW_ENC_CNT_INC(sec, ra) +#define WEP_SW_DEC_CNT_INC(sec, ra) +#define TKIP_SW_ENC_CNT_INC(sec, ra) +#define TKIP_SW_DEC_CNT_INC(sec, ra) +#define AES_SW_ENC_CNT_INC(sec, ra) +#define AES_SW_DEC_CNT_INC(sec, ra) + +/* *****WEP related***** */ + +#define CRC32_POLY 0x04c11db7 + +struct arc4context { + u32 x; + u32 y; + u8 state[256]; +}; + +static void arcfour_init(struct arc4context *parc4ctx, u8 *key, u32 key_len) +{ + u32 t, u; + u32 keyindex; + u32 stateindex; + u8 *state; + u32 counter; + state = parc4ctx->state; + parc4ctx->x = 0; + parc4ctx->y = 0; + for (counter = 0; counter < 256; counter++) + state[counter] = (u8)counter; + keyindex = 0; + stateindex = 0; + for (counter = 0; counter < 256; counter++) { + t = state[counter]; + stateindex = (stateindex + key[keyindex] + t) & 0xff; + u = state[stateindex]; + state[stateindex] = (u8)t; + state[counter] = (u8)u; + if (++keyindex >= key_len) + keyindex = 0; + } +} +static u32 arcfour_byte(struct arc4context *parc4ctx) +{ + u32 x; + u32 y; + u32 sx, sy; + u8 *state; + state = parc4ctx->state; + x = (parc4ctx->x + 1) & 0xff; + sx = state[x]; + y = (sx + parc4ctx->y) & 0xff; + sy = state[y]; + parc4ctx->x = x; + parc4ctx->y = y; + state[y] = (u8)sx; + state[x] = (u8)sy; + return state[(sx + sy) & 0xff]; +} + +static void arcfour_encrypt(struct arc4context *parc4ctx, + u8 *dest, + u8 *src, + u32 len) +{ + u32 i; + for (i = 0; i < len; i++) + dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx); +} + +static sint bcrc32initialized = 0; +static u32 crc32_table[256]; + +static u8 crc32_reverseBit(u8 data) +{ + return (u8)((data << 7) & 0x80) | ((data << 5) & 0x40) | ((data << 3) & 0x20) | ((data << 1) & 0x10) | ((data >> 1) & 0x08) | ((data >> 3) & 0x04) | ((data >> 5) & 0x02) | (( + data >> 7) & 0x01) ; +} + +static void crc32_init(void) +{ + if (bcrc32initialized == 1) + goto exit; + else { + sint i, j; + u32 c; + u8 *p = (u8 *)&c, *p1; + u8 k; + + c = 0x12340000; + + for (i = 0; i < 256; ++i) { + k = crc32_reverseBit((u8)i); + for (c = ((u32)k) << 24, j = 8; j > 0; --j) + c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1); + p1 = (u8 *)&crc32_table[i]; + + p1[0] = crc32_reverseBit(p[3]); + p1[1] = crc32_reverseBit(p[2]); + p1[2] = crc32_reverseBit(p[1]); + p1[3] = crc32_reverseBit(p[0]); + } + bcrc32initialized = 1; + } +exit: + return; +} + +static u32 getcrc32(u8 *buf, sint len) +{ + u8 *p; + u32 crc; + if (bcrc32initialized == 0) + crc32_init(); + + crc = 0xffffffff; /* preload shift register, per CRC-32 spec */ + + for (p = buf; len > 0; ++p, --len) + crc = crc32_table[(crc ^ *p) & 0xff] ^ (crc >> 8); + return ~crc; /* transmit complement, per CRC-32 spec */ +} + +/* + Need to consider the fragment situation +*/ +void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe) +{ + /* exclude ICV */ + + unsigned char crc[4]; + struct arc4context mycontext; + + sint curfragnum, length; + u32 keylength; + + u8 *pframe, *payload, *iv; /* ,*wepkey */ + u8 wepkey[16]; + u8 hw_hdr_offset = 0; + struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) + return; + + hw_hdr_offset = TXDESC_OFFSET; + + pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; + + /* start to encrypt each fragment */ + if ((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) { + keylength = psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex]; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + iv = pframe + pattrib->hdrlen; + _rtw_memcpy(&wepkey[0], iv, 3); + _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0], keylength); + payload = pframe + pattrib->iv_len + pattrib->hdrlen; + + if ((curfragnum + 1) == pattrib->nr_frags) { + /* the last fragment */ + + length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; + + *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); + + arcfour_init(&mycontext, wepkey, 3 + keylength); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload + length, crc, 4); + + } else { + length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ; + *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); + arcfour_init(&mycontext, wepkey, 3 + keylength); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload + length, crc, 4); + + pframe += pxmitpriv->frag_len; + pframe = (u8 *)RND4((SIZE_PTR)(pframe)); + + } + + } + + WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + } + +} + +void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe) +{ + /* exclude ICV */ + u8 crc[4]; + struct arc4context mycontext; + sint length; + u32 keylength; + u8 *pframe, *payload, *iv, wepkey[16]; + u8 keyindex; + struct rx_pkt_attrib *prxattrib = &(((union recv_frame *)precvframe)->u.hdr.attrib); + struct security_priv *psecuritypriv = &padapter->securitypriv; + + pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; + + /* start to decrypt recvframe */ + if ((prxattrib->encrypt == _WEP40_) || (prxattrib->encrypt == _WEP104_)) { + iv = pframe + prxattrib->hdrlen; + /* keyindex=(iv[3]&0x3); */ + keyindex = prxattrib->key_index; + keylength = psecuritypriv->dot11DefKeylen[keyindex]; + _rtw_memcpy(&wepkey[0], iv, 3); + /* _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); */ + _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0], keylength); + length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len; + + payload = pframe + prxattrib->iv_len + prxattrib->hdrlen; + + /* decrypt payload include icv */ + arcfour_init(&mycontext, wepkey, 3 + keylength); + arcfour_encrypt(&mycontext, payload, payload, length); + + /* calculate icv and compare the icv */ + *((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4)); + + WEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); + } + + return; + +} + +/* 3 =====TKIP related===== */ + +static u32 secmicgetuint32(u8 *p) +/* Convert from Byte[] to Us4Byte32 in a portable way */ +{ + s32 i; + u32 res = 0; + for (i = 0; i < 4; i++) + res |= ((u32)(*p++)) << (8 * i); + return res; +} + +static void secmicputuint32(u8 *p, u32 val) +/* Convert from Us4Byte32 to Byte[] in a portable way */ +{ + long i; + for (i = 0; i < 4; i++) { + *p++ = (u8)(val & 0xff); + val >>= 8; + } +} + +static void secmicclear(struct mic_data *pmicdata) +{ + /* Reset the state to the empty message. */ + pmicdata->L = pmicdata->K0; + pmicdata->R = pmicdata->K1; + pmicdata->nBytesInM = 0; + pmicdata->M = 0; +} + +void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key) +{ + /* Set the key */ + pmicdata->K0 = secmicgetuint32(key); + pmicdata->K1 = secmicgetuint32(key + 4); + /* and reset the message */ + secmicclear(pmicdata); +} + +void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b) +{ + /* Append the byte to our word-sized buffer */ + pmicdata->M |= ((unsigned long)b) << (8 * pmicdata->nBytesInM); + pmicdata->nBytesInM++; + /* Process the word if it is full. */ + if (pmicdata->nBytesInM >= 4) { + pmicdata->L ^= pmicdata->M; + pmicdata->R ^= ROL32(pmicdata->L, 17); + pmicdata->L += pmicdata->R; + pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8); + pmicdata->L += pmicdata->R; + pmicdata->R ^= ROL32(pmicdata->L, 3); + pmicdata->L += pmicdata->R; + pmicdata->R ^= ROR32(pmicdata->L, 2); + pmicdata->L += pmicdata->R; + /* Clear the buffer */ + pmicdata->M = 0; + pmicdata->nBytesInM = 0; + } +} + +void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nbytes) +{ + /* This is simple */ + while (nbytes > 0) { + rtw_secmicappendbyte(pmicdata, *src++); + nbytes--; + } +} + +void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst) +{ + /* Append the minimum padding */ + rtw_secmicappendbyte(pmicdata, 0x5a); + rtw_secmicappendbyte(pmicdata, 0); + rtw_secmicappendbyte(pmicdata, 0); + rtw_secmicappendbyte(pmicdata, 0); + rtw_secmicappendbyte(pmicdata, 0); + /* and then zeroes until the length is a multiple of 4 */ + while (pmicdata->nBytesInM != 0) + rtw_secmicappendbyte(pmicdata, 0); + /* The appendByte function has already computed the result. */ + secmicputuint32(dst, pmicdata->L); + secmicputuint32(dst + 4, pmicdata->R); + /* Reset to the empty message. */ + secmicclear(pmicdata); +} + +void rtw_seccalctkipmic(u8 *key, u8 *header, u8 *data, u32 data_len, u8 *mic_code, u8 pri) +{ + + struct mic_data micdata; + u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; + rtw_secmicsetkey(&micdata, key); + priority[0] = pri; + + /* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */ + if (header[1] & 1) { /* ToDS==1 */ + rtw_secmicappend(&micdata, &header[16], 6); /* DA */ + if (header[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &header[24], 6); + else + rtw_secmicappend(&micdata, &header[10], 6); + } else { /* ToDS==0 */ + rtw_secmicappend(&micdata, &header[4], 6); /* DA */ + if (header[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &header[16], 6); + else + rtw_secmicappend(&micdata, &header[10], 6); + + } + rtw_secmicappend(&micdata, &priority[0], 4); + + rtw_secmicappend(&micdata, data, data_len); + + rtw_secgetmic(&micdata, mic_code); +} + +/* macros for extraction/creation of unsigned char/unsigned short values */ +#define RotR1(v16) ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15)) +#define Lo8(v16) ((u8)((v16) & 0x00FF)) +#define Hi8(v16) ((u8)(((v16) >> 8) & 0x00FF)) +#define Lo16(v32) ((u16)((v32) & 0xFFFF)) +#define Hi16(v32) ((u16)(((v32) >> 16) & 0xFFFF)) +#define Mk16(hi, lo) ((lo) ^ (((u16)(hi)) << 8)) + +/* select the Nth 16-bit word of the temporal key unsigned char array TK[] */ +#define TK16(N) Mk16(tk[2*(N)+1], tk[2*(N)]) + +/* S-box lookup: 16 bits --> 16 bits */ +#define _S_(v16) (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)]) + +/* fixed algorithm "parameters" */ +#define PHASE1_LOOP_CNT 8 /* this needs to be "big enough" */ +#define TA_SIZE 6 /* 48-bit transmitter address */ +#define TK_SIZE 16 /* 128-bit temporal key */ +#define P1K_SIZE 10 /* 80-bit Phase1 key */ +#define RC4_KEY_SIZE 16 /* 128-bit RC4KEY (104 bits unknown) */ + +/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */ +static const unsigned short Sbox1[2][256] = /* Sbox for hash (can be in ROM) */ +{ { + 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154, + 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A, + 0x8F45, 0x1F9D, 0x8940, 0xFA87, 0xEF15, 0xB2EB, 0x8EC9, 0xFB0B, + 0x41EC, 0xB367, 0x5FFD, 0x45EA, 0x23BF, 0x53F7, 0xE496, 0x9B5B, + 0x75C2, 0xE11C, 0x3DAE, 0x4C6A, 0x6C5A, 0x7E41, 0xF502, 0x834F, + 0x685C, 0x51F4, 0xD134, 0xF908, 0xE293, 0xAB73, 0x6253, 0x2A3F, + 0x080C, 0x9552, 0x4665, 0x9D5E, 0x3028, 0x37A1, 0x0A0F, 0x2FB5, + 0x0E09, 0x2436, 0x1B9B, 0xDF3D, 0xCD26, 0x4E69, 0x7FCD, 0xEA9F, + 0x121B, 0x1D9E, 0x5874, 0x342E, 0x362D, 0xDCB2, 0xB4EE, 0x5BFB, + 0xA4F6, 0x764D, 0xB761, 0x7DCE, 0x527B, 0xDD3E, 0x5E71, 0x1397, + 0xA6F5, 0xB968, 0x0000, 0xC12C, 0x4060, 0xE31F, 0x79C8, 0xB6ED, + 0xD4BE, 0x8D46, 0x67D9, 0x724B, 0x94DE, 0x98D4, 0xB0E8, 0x854A, + 0xBB6B, 0xC52A, 0x4FE5, 0xED16, 0x86C5, 0x9AD7, 0x6655, 0x1194, + 0x8ACF, 0xE910, 0x0406, 0xFE81, 0xA0F0, 0x7844, 0x25BA, 0x4BE3, + 0xA2F3, 0x5DFE, 0x80C0, 0x058A, 0x3FAD, 0x21BC, 0x7048, 0xF104, + 0x63DF, 0x77C1, 0xAF75, 0x4263, 0x2030, 0xE51A, 0xFD0E, 0xBF6D, + 0x814C, 0x1814, 0x2635, 0xC32F, 0xBEE1, 0x35A2, 0x88CC, 0x2E39, + 0x9357, 0x55F2, 0xFC82, 0x7A47, 0xC8AC, 0xBAE7, 0x322B, 0xE695, + 0xC0A0, 0x1998, 0x9ED1, 0xA37F, 0x4466, 0x547E, 0x3BAB, 0x0B83, + 0x8CCA, 0xC729, 0x6BD3, 0x283C, 0xA779, 0xBCE2, 0x161D, 0xAD76, + 0xDB3B, 0x6456, 0x744E, 0x141E, 0x92DB, 0x0C0A, 0x486C, 0xB8E4, + 0x9F5D, 0xBD6E, 0x43EF, 0xC4A6, 0x39A8, 0x31A4, 0xD337, 0xF28B, + 0xD532, 0x8B43, 0x6E59, 0xDAB7, 0x018C, 0xB164, 0x9CD2, 0x49E0, + 0xD8B4, 0xACFA, 0xF307, 0xCF25, 0xCAAF, 0xF48E, 0x47E9, 0x1018, + 0x6FD5, 0xF088, 0x4A6F, 0x5C72, 0x3824, 0x57F1, 0x73C7, 0x9751, + 0xCB23, 0xA17C, 0xE89C, 0x3E21, 0x96DD, 0x61DC, 0x0D86, 0x0F85, + 0xE090, 0x7C42, 0x71C4, 0xCCAA, 0x90D8, 0x0605, 0xF701, 0x1C12, + 0xC2A3, 0x6A5F, 0xAEF9, 0x69D0, 0x1791, 0x9958, 0x3A27, 0x27B9, + 0xD938, 0xEB13, 0x2BB3, 0x2233, 0xD2BB, 0xA970, 0x0789, 0x33A7, + 0x2DB6, 0x3C22, 0x1592, 0xC920, 0x8749, 0xAAFF, 0x5078, 0xA57A, + 0x038F, 0x59F8, 0x0980, 0x1A17, 0x65DA, 0xD731, 0x84C6, 0xD0B8, + 0x82C3, 0x29B0, 0x5A77, 0x1E11, 0x7BCB, 0xA8FC, 0x6DD6, 0x2C3A, + }, + + { /* second half of table is unsigned char-reversed version of first! */ + 0xA5C6, 0x84F8, 0x99EE, 0x8DF6, 0x0DFF, 0xBDD6, 0xB1DE, 0x5491, + 0x5060, 0x0302, 0xA9CE, 0x7D56, 0x19E7, 0x62B5, 0xE64D, 0x9AEC, + 0x458F, 0x9D1F, 0x4089, 0x87FA, 0x15EF, 0xEBB2, 0xC98E, 0x0BFB, + 0xEC41, 0x67B3, 0xFD5F, 0xEA45, 0xBF23, 0xF753, 0x96E4, 0x5B9B, + 0xC275, 0x1CE1, 0xAE3D, 0x6A4C, 0x5A6C, 0x417E, 0x02F5, 0x4F83, + 0x5C68, 0xF451, 0x34D1, 0x08F9, 0x93E2, 0x73AB, 0x5362, 0x3F2A, + 0x0C08, 0x5295, 0x6546, 0x5E9D, 0x2830, 0xA137, 0x0F0A, 0xB52F, + 0x090E, 0x3624, 0x9B1B, 0x3DDF, 0x26CD, 0x694E, 0xCD7F, 0x9FEA, + 0x1B12, 0x9E1D, 0x7458, 0x2E34, 0x2D36, 0xB2DC, 0xEEB4, 0xFB5B, + 0xF6A4, 0x4D76, 0x61B7, 0xCE7D, 0x7B52, 0x3EDD, 0x715E, 0x9713, + 0xF5A6, 0x68B9, 0x0000, 0x2CC1, 0x6040, 0x1FE3, 0xC879, 0xEDB6, + 0xBED4, 0x468D, 0xD967, 0x4B72, 0xDE94, 0xD498, 0xE8B0, 0x4A85, + 0x6BBB, 0x2AC5, 0xE54F, 0x16ED, 0xC586, 0xD79A, 0x5566, 0x9411, + 0xCF8A, 0x10E9, 0x0604, 0x81FE, 0xF0A0, 0x4478, 0xBA25, 0xE34B, + 0xF3A2, 0xFE5D, 0xC080, 0x8A05, 0xAD3F, 0xBC21, 0x4870, 0x04F1, + 0xDF63, 0xC177, 0x75AF, 0x6342, 0x3020, 0x1AE5, 0x0EFD, 0x6DBF, + 0x4C81, 0x1418, 0x3526, 0x2FC3, 0xE1BE, 0xA235, 0xCC88, 0x392E, + 0x5793, 0xF255, 0x82FC, 0x477A, 0xACC8, 0xE7BA, 0x2B32, 0x95E6, + 0xA0C0, 0x9819, 0xD19E, 0x7FA3, 0x6644, 0x7E54, 0xAB3B, 0x830B, + 0xCA8C, 0x29C7, 0xD36B, 0x3C28, 0x79A7, 0xE2BC, 0x1D16, 0x76AD, + 0x3BDB, 0x5664, 0x4E74, 0x1E14, 0xDB92, 0x0A0C, 0x6C48, 0xE4B8, + 0x5D9F, 0x6EBD, 0xEF43, 0xA6C4, 0xA839, 0xA431, 0x37D3, 0x8BF2, + 0x32D5, 0x438B, 0x596E, 0xB7DA, 0x8C01, 0x64B1, 0xD29C, 0xE049, + 0xB4D8, 0xFAAC, 0x07F3, 0x25CF, 0xAFCA, 0x8EF4, 0xE947, 0x1810, + 0xD56F, 0x88F0, 0x6F4A, 0x725C, 0x2438, 0xF157, 0xC773, 0x5197, + 0x23CB, 0x7CA1, 0x9CE8, 0x213E, 0xDD96, 0xDC61, 0x860D, 0x850F, + 0x90E0, 0x427C, 0xC471, 0xAACC, 0xD890, 0x0506, 0x01F7, 0x121C, + 0xA3C2, 0x5F6A, 0xF9AE, 0xD069, 0x9117, 0x5899, 0x273A, 0xB927, + 0x38D9, 0x13EB, 0xB32B, 0x3322, 0xBBD2, 0x70A9, 0x8907, 0xA733, + 0xB62D, 0x223C, 0x9215, 0x20C9, 0x4987, 0xFFAA, 0x7850, 0x7AA5, + 0x8F03, 0xF859, 0x8009, 0x171A, 0xDA65, 0x31D7, 0xC684, 0xB8D0, + 0xC382, 0xB029, 0x775A, 0x111E, 0xCB7B, 0xFCA8, 0xD66D, 0x3A2C, + } +}; + +/* +********************************************************************** +* Routine: Phase 1 -- generate P1K, given TA, TK, IV32 +* +* Inputs: +* tk[] = temporal key [128 bits] +* ta[] = transmitter's MAC address [ 48 bits] +* iv32 = upper 32 bits of IV [ 32 bits] +* Output: +* p1k[] = Phase 1 key [ 80 bits] +* +* Note: +* This function only needs to be called every 2**16 packets, +* although in theory it could be called every packet. +* +********************************************************************** +*/ +static void phase1(u16 *p1k, const u8 *tk, const u8 *ta, u32 iv32) +{ + sint i; + /* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */ + p1k[0] = Lo16(iv32); + p1k[1] = Hi16(iv32); + p1k[2] = Mk16(ta[1], ta[0]); /* use TA[] as little-endian */ + p1k[3] = Mk16(ta[3], ta[2]); + p1k[4] = Mk16(ta[5], ta[4]); + + /* Now compute an unbalanced Feistel cipher with 80-bit block */ + /* size on the 80-bit block P1K[], using the 128-bit key TK[] */ + for (i = 0; i < PHASE1_LOOP_CNT ; i++) { + /* Each add operation here is mod 2**16 */ + p1k[0] += _S_(p1k[4] ^ TK16((i & 1) + 0)); + p1k[1] += _S_(p1k[0] ^ TK16((i & 1) + 2)); + p1k[2] += _S_(p1k[1] ^ TK16((i & 1) + 4)); + p1k[3] += _S_(p1k[2] ^ TK16((i & 1) + 6)); + p1k[4] += _S_(p1k[3] ^ TK16((i & 1) + 0)); + p1k[4] += (unsigned short)i; /* avoid "slide attacks" */ + } +} + +/* +********************************************************************** +* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16 +* +* Inputs: +* tk[] = Temporal key [128 bits] +* p1k[] = Phase 1 output key [ 80 bits] +* iv16 = low 16 bits of IV counter [ 16 bits] +* Output: +* rc4key[] = the key used to encrypt the packet [128 bits] +* +* Note: +* The value {TA,IV32,IV16} for Phase1/Phase2 must be unique +* across all packets using the same key TK value. Then, for a +* given value of TK[], this TKIP48 construction guarantees that +* the final RC4KEY value is unique across all packets. +* +* Suggested implementation optimization: if PPK[] is "overlaid" +* appropriately on RC4KEY[], there is no need for the final +* for loop below that copies the PPK[] result into RC4KEY[]. +* +********************************************************************** +*/ +static void phase2(u8 *rc4key, const u8 *tk, const u16 *p1k, u16 iv16) +{ + sint i; + u16 PPK[6]; /* temporary key for mixing */ + /* Note: all adds in the PPK[] equations below are mod 2**16 */ + for (i = 0; i < 5; i++) + PPK[i] = p1k[i]; /* first, copy P1K to PPK */ + PPK[5] = p1k[4] + iv16; /* next, add in IV16 */ + + /* Bijective non-linear mixing of the 96 bits of PPK[0..5] */ + PPK[0] += _S_(PPK[5] ^ TK16(0)); /* Mix key in each "round" */ + PPK[1] += _S_(PPK[0] ^ TK16(1)); + PPK[2] += _S_(PPK[1] ^ TK16(2)); + PPK[3] += _S_(PPK[2] ^ TK16(3)); + PPK[4] += _S_(PPK[3] ^ TK16(4)); + PPK[5] += _S_(PPK[4] ^ TK16(5)); /* Total # S-box lookups == 6 */ + + /* Final sweep: bijective, "linear". Rotates kill LSB correlations */ + PPK[0] += RotR1(PPK[5] ^ TK16(6)); + PPK[1] += RotR1(PPK[0] ^ TK16(7)); /* Use all of TK[] in Phase2 */ + PPK[2] += RotR1(PPK[1]); + PPK[3] += RotR1(PPK[2]); + PPK[4] += RotR1(PPK[3]); + PPK[5] += RotR1(PPK[4]); + /* Note: At this point, for a given key TK[0..15], the 96-bit output */ + /* value PPK[0..5] is guaranteed to be unique, as a function */ + /* of the 96-bit "input" value {TA,IV32,IV16}. That is, P1K */ + /* is now a keyed permutation of {TA,IV32,IV16}. */ + + /* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key */ + rc4key[0] = Hi8(iv16); /* RC4KEY[0..2] is the WEP IV */ + rc4key[1] = (Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */ + rc4key[2] = Lo8(iv16); + rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1); + + /* Copy 96 bits of PPK[0..5] to RC4KEY[4..15] (little-endian) */ + for (i = 0; i < 6; i++) { + rc4key[4 + 2 * i] = Lo8(PPK[i]); + rc4key[5 + 2 * i] = Hi8(PPK[i]); + } +} + +/* The hlen isn't include the IV */ +u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) +{ + /* exclude ICV */ + u16 pnl; + u32 pnh; + u8 rc4key[16]; + u8 ttkey[16]; + u8 crc[4]; + u8 hw_hdr_offset = 0; + struct arc4context mycontext; + sint curfragnum, length; + u32 prwskeylen; + + u8 *pframe, *payload, *iv, *prwskey; + union pn48 dot11txpn; + /* struct sta_info *stainfo; */ + struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + u32 res = _SUCCESS; + + if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) + return _FAIL; + + hw_hdr_offset = TXDESC_OFFSET; + + pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; + /* 4 start to encrypt each fragment */ + if (pattrib->encrypt == _TKIP_) { + + /* + if(pattrib->psta) + { + stainfo = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); + } + */ + /* if (stainfo!=NULL) */ + { + /* + if(!(stainfo->state &_FW_LINKED)) + { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); + return _FAIL; + } + */ + + if (IS_MCAST(pattrib->ra)) + prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + else { + /* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */ + prwskey = pattrib->dot118021x_UncstKey.skey; + } + + prwskeylen = 16; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + iv = pframe + pattrib->hdrlen; + payload = pframe + pattrib->iv_len + pattrib->hdrlen; + + GET_TKIP_PN(iv, dot11txpn); + + pnl = (u16)(dot11txpn.val); + pnh = (u32)(dot11txpn.val >> 16); + + phase1((u16 *)&ttkey[0], prwskey, &pattrib->ta[0], pnh); + + phase2(&rc4key[0], prwskey, (u16 *)&ttkey[0], pnl); + + if ((curfragnum + 1) == pattrib->nr_frags) { /* 4 the last fragment */ + length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; + *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/ + + arcfour_init(&mycontext, rc4key, 16); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload + length, crc, 4); + + } else { + length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ; + *((u32 *)crc) = cpu_to_le32(getcrc32(payload, length)); /* modified by Amy*/ + arcfour_init(&mycontext, rc4key, 16); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload + length, crc, 4); + + pframe += pxmitpriv->frag_len; + pframe = (u8 *)RND4((SIZE_PTR)(pframe)); + + } + } + + TKIP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + } + /* + else{ + RTW_INFO("%s, psta==NUL\n", __func__); + res=_FAIL; + } + */ + + } + return res; + +} + +/* The hlen isn't include the IV */ +u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) +{ + /* exclude ICV */ + u16 pnl; + u32 pnh; + u8 rc4key[16]; + u8 ttkey[16]; + u8 crc[4]; + struct arc4context mycontext; + sint length; + u32 prwskeylen; + + u8 *pframe, *payload, *iv, *prwskey; + union pn48 dot11txpn; + struct sta_info *stainfo; + struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + /* struct recv_priv *precvpriv=&padapter->recvpriv; */ + u32 res = _SUCCESS; + + pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; + + /* 4 start to decrypt recvframe */ + if (prxattrib->encrypt == _TKIP_) { + + stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]); + if (stainfo != NULL) { + + if (IS_MCAST(prxattrib->ra)) { + static u32 start = 0; + static u32 no_gkey_bc_cnt = 0; + static u32 no_gkey_mc_cnt = 0; + + if (psecuritypriv->binstallGrpkey == _FALSE) { + res = _FAIL; + + if (start == 0) + start = rtw_get_current_time(); + + if (is_broadcast_mac_addr(prxattrib->ra)) + no_gkey_bc_cnt++; + else + no_gkey_mc_cnt++; + + if (rtw_get_passing_time_ms(start) > 1000) { + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = rtw_get_current_time(); + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + } + goto exit; + } + + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = 0; + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + + /* RTW_INFO("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n"); */ + /* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */ + prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; + prwskeylen = 16; + } else { + prwskey = &stainfo->dot118021x_UncstKey.skey[0]; + prwskeylen = 16; + } + + iv = pframe + prxattrib->hdrlen; + payload = pframe + prxattrib->iv_len + prxattrib->hdrlen; + length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len; + + GET_TKIP_PN(iv, dot11txpn); + + pnl = (u16)(dot11txpn.val); + pnh = (u32)(dot11txpn.val >> 16); + + phase1((u16 *)&ttkey[0], prwskey, &prxattrib->ta[0], pnh); + phase2(&rc4key[0], prwskey, (unsigned short *)&ttkey[0], pnl); + + /* 4 decrypt payload include icv */ + + arcfour_init(&mycontext, rc4key, 16); + arcfour_encrypt(&mycontext, payload, payload, length); + + *((u32 *)crc) = le32_to_cpu(getcrc32(payload, length - 4)); + + if (crc[3] != payload[length - 1] || crc[2] != payload[length - 2] || crc[1] != payload[length - 3] || crc[0] != payload[length - 4]) { + res = _FAIL; + } + + TKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); + } else { + res = _FAIL; + } + + } +exit: + return res; + +} + +/* 3 =====AES related===== */ + +#define MAX_MSG_SIZE 2048 +/*****************************/ +/******** SBOX Table *********/ +/*****************************/ + +static u8 sbox_table[256] = { + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, + 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, + 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, + 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, + 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, + 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, + 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, + 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, + 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, + 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, + 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, + 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, + 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, + 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, + 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, + 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, + 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, + 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, + 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, + 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, + 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, + 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, + 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, + 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, + 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, + 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 +}; + +/*****************************/ +/**** Function Prototypes ****/ +/*****************************/ + +static void bitwise_xor(u8 *ina, u8 *inb, u8 *out); +static void construct_mic_iv( + u8 *mic_header1, + sint qc_exists, + sint a4_exists, + u8 *mpdu, + uint payload_length, + u8 *pn_vector, + uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */ +static void construct_mic_header1( + u8 *mic_header1, + sint header_length, + u8 *mpdu, + uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */ +static void construct_mic_header2( + u8 *mic_header2, + u8 *mpdu, + sint a4_exists, + sint qc_exists); +static void construct_ctr_preload( + u8 *ctr_preload, + sint a4_exists, + sint qc_exists, + u8 *mpdu, + u8 *pn_vector, + sint c, + uint frtype);/* add for CONFIG_IEEE80211W, none 11w also can use */ +static void xor_128(u8 *a, u8 *b, u8 *out); +static void xor_32(u8 *a, u8 *b, u8 *out); +static u8 sbox(u8 a); +static void next_key(u8 *key, sint round); +static void byte_sub(u8 *in, u8 *out); +static void shift_row(u8 *in, u8 *out); +static void mix_column(u8 *in, u8 *out); +static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext); + +/****************************************/ +/* aes128k128d() */ +/* Performs a 128 bit AES encrypt with */ +/* 128 bit data. */ +/****************************************/ +static void xor_128(u8 *a, u8 *b, u8 *out) +{ + sint i; + for (i = 0; i < 16; i++) + out[i] = a[i] ^ b[i]; +} + +static void xor_32(u8 *a, u8 *b, u8 *out) +{ + sint i; + for (i = 0; i < 4; i++) + out[i] = a[i] ^ b[i]; +} + +static u8 sbox(u8 a) +{ + return sbox_table[(sint)a]; +} + +static void next_key(u8 *key, sint round) +{ + u8 rcon; + u8 sbox_key[4]; + u8 rcon_table[12] = { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, + 0x1b, 0x36, 0x36, 0x36 + }; + sbox_key[0] = sbox(key[13]); + sbox_key[1] = sbox(key[14]); + sbox_key[2] = sbox(key[15]); + sbox_key[3] = sbox(key[12]); + + rcon = rcon_table[round]; + + xor_32(&key[0], sbox_key, &key[0]); + key[0] = key[0] ^ rcon; + + xor_32(&key[4], &key[0], &key[4]); + xor_32(&key[8], &key[4], &key[8]); + xor_32(&key[12], &key[8], &key[12]); +} + +static void byte_sub(u8 *in, u8 *out) +{ + sint i; + for (i = 0; i < 16; i++) + out[i] = sbox(in[i]); +} + +static void shift_row(u8 *in, u8 *out) +{ + out[0] = in[0]; + out[1] = in[5]; + out[2] = in[10]; + out[3] = in[15]; + out[4] = in[4]; + out[5] = in[9]; + out[6] = in[14]; + out[7] = in[3]; + out[8] = in[8]; + out[9] = in[13]; + out[10] = in[2]; + out[11] = in[7]; + out[12] = in[12]; + out[13] = in[1]; + out[14] = in[6]; + out[15] = in[11]; +} + +static void mix_column(u8 *in, u8 *out) +{ + sint i; + u8 add1b[4]; + u8 add1bf7[4]; + u8 rotl[4]; + u8 swap_halfs[4]; + u8 andf7[4]; + u8 rotr[4]; + u8 temp[4]; + u8 tempb[4]; + for (i = 0 ; i < 4; i++) { + if ((in[i] & 0x80) == 0x80) + add1b[i] = 0x1b; + else + add1b[i] = 0x00; + } + + swap_halfs[0] = in[2]; /* Swap halfs */ + swap_halfs[1] = in[3]; + swap_halfs[2] = in[0]; + swap_halfs[3] = in[1]; + + rotl[0] = in[3]; /* Rotate left 8 bits */ + rotl[1] = in[0]; + rotl[2] = in[1]; + rotl[3] = in[2]; + + andf7[0] = in[0] & 0x7f; + andf7[1] = in[1] & 0x7f; + andf7[2] = in[2] & 0x7f; + andf7[3] = in[3] & 0x7f; + + for (i = 3; i > 0; i--) { /* logical shift left 1 bit */ + andf7[i] = andf7[i] << 1; + if ((andf7[i - 1] & 0x80) == 0x80) + andf7[i] = (andf7[i] | 0x01); + } + andf7[0] = andf7[0] << 1; + andf7[0] = andf7[0] & 0xfe; + + xor_32(add1b, andf7, add1bf7); + + xor_32(in, add1bf7, rotr); + + temp[0] = rotr[0]; /* Rotate right 8 bits */ + rotr[0] = rotr[1]; + rotr[1] = rotr[2]; + rotr[2] = rotr[3]; + rotr[3] = temp[0]; + + xor_32(add1bf7, rotr, temp); + xor_32(swap_halfs, rotl, tempb); + xor_32(temp, tempb, out); +} + +static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext) +{ + sint round; + sint i; + u8 intermediatea[16]; + u8 intermediateb[16]; + u8 round_key[16]; + for (i = 0; i < 16; i++) + round_key[i] = key[i]; + + for (round = 0; round < 11; round++) { + if (round == 0) { + xor_128(round_key, data, ciphertext); + next_key(round_key, round); + } else if (round == 10) { + byte_sub(ciphertext, intermediatea); + shift_row(intermediatea, intermediateb); + xor_128(intermediateb, round_key, ciphertext); + } else { /* 1 - 9 */ + byte_sub(ciphertext, intermediatea); + shift_row(intermediatea, intermediateb); + mix_column(&intermediateb[0], &intermediatea[0]); + mix_column(&intermediateb[4], &intermediatea[4]); + mix_column(&intermediateb[8], &intermediatea[8]); + mix_column(&intermediateb[12], &intermediatea[12]); + xor_128(intermediatea, round_key, ciphertext); + next_key(round_key, round); + } + } +} + +/************************************************/ +/* construct_mic_iv() */ +/* Builds the MIC IV from header fields and PN */ +/* Baron think the function is construct CCM */ +/* nonce */ +/************************************************/ +static void construct_mic_iv( + u8 *mic_iv, + sint qc_exists, + sint a4_exists, + u8 *mpdu, + uint payload_length, + u8 *pn_vector, + uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */ +) +{ + sint i; + mic_iv[0] = 0x59; + if (qc_exists && a4_exists) + mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */ + if (qc_exists && !a4_exists) + mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */ + if (!qc_exists) + mic_iv[1] = 0x00; + for (i = 2; i < 8; i++) + mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */ + for (i = 8; i < 14; i++) + mic_iv[i] = pn_vector[13 - i]; /* mic_iv[8:13] = PN[5:0] */ + mic_iv[14] = (unsigned char)(payload_length / 256); + mic_iv[15] = (unsigned char)(payload_length % 256); +} + +/************************************************/ +/* construct_mic_header1() */ +/* Builds the first MIC header block from */ +/* header fields. */ +/* Build AAD SC,A1,A2 */ +/************************************************/ +static void construct_mic_header1( + u8 *mic_header1, + sint header_length, + u8 *mpdu, + uint frtype/* add for CONFIG_IEEE80211W, none 11w also can use */ +) +{ + mic_header1[0] = (u8)((header_length - 2) / 256); + mic_header1[1] = (u8)((header_length - 2) % 256); + mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */ + + mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */ + mic_header1[4] = mpdu[4]; /* A1 */ + mic_header1[5] = mpdu[5]; + mic_header1[6] = mpdu[6]; + mic_header1[7] = mpdu[7]; + mic_header1[8] = mpdu[8]; + mic_header1[9] = mpdu[9]; + mic_header1[10] = mpdu[10]; /* A2 */ + mic_header1[11] = mpdu[11]; + mic_header1[12] = mpdu[12]; + mic_header1[13] = mpdu[13]; + mic_header1[14] = mpdu[14]; + mic_header1[15] = mpdu[15]; +} + +/************************************************/ +/* construct_mic_header2() */ +/* Builds the last MIC header block from */ +/* header fields. */ +/************************************************/ +static void construct_mic_header2( + u8 *mic_header2, + u8 *mpdu, + sint a4_exists, + sint qc_exists +) +{ + sint i; + for (i = 0; i < 16; i++) + mic_header2[i] = 0x00; + + mic_header2[0] = mpdu[16]; /* A3 */ + mic_header2[1] = mpdu[17]; + mic_header2[2] = mpdu[18]; + mic_header2[3] = mpdu[19]; + mic_header2[4] = mpdu[20]; + mic_header2[5] = mpdu[21]; + + /* mic_header2[6] = mpdu[22] & 0xf0; SC */ + mic_header2[6] = 0x00; + mic_header2[7] = 0x00; /* mpdu[23]; */ + + if (!qc_exists && a4_exists) { + for (i = 0; i < 6; i++) + mic_header2[8 + i] = mpdu[24 + i]; /* A4 */ + + } + + if (qc_exists && !a4_exists) { + mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */ + mic_header2[9] = mpdu[25] & 0x00; + } + + if (qc_exists && a4_exists) { + for (i = 0; i < 6; i++) + mic_header2[8 + i] = mpdu[24 + i]; /* A4 */ + + mic_header2[14] = mpdu[30] & 0x0f; + mic_header2[15] = mpdu[31] & 0x00; + } + +} + +/************************************************/ +/* construct_mic_header2() */ +/* Builds the last MIC header block from */ +/* header fields. */ +/* Baron think the function is construct CCM */ +/* nonce */ +/************************************************/ +static void construct_ctr_preload( + u8 *ctr_preload, + sint a4_exists, + sint qc_exists, + u8 *mpdu, + u8 *pn_vector, + sint c, + uint frtype /* add for CONFIG_IEEE80211W, none 11w also can use */ +) +{ + sint i = 0; + for (i = 0; i < 16; i++) + ctr_preload[i] = 0x00; + i = 0; + + ctr_preload[0] = 0x01; /* flag */ + if (qc_exists && a4_exists) + ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */ + if (qc_exists && !a4_exists) + ctr_preload[1] = mpdu[24] & 0x0f; + for (i = 2; i < 8; i++) + ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */ + for (i = 8; i < 14; i++) + ctr_preload[i] = pn_vector[13 - i]; /* ctr_preload[8:13] = PN[5:0] */ + ctr_preload[14] = (unsigned char)(c / 256); /* Ctr */ + ctr_preload[15] = (unsigned char)(c % 256); +} + +/************************************/ +/* bitwise_xor() */ +/* A 128 bit, bitwise exclusive or */ +/************************************/ +static void bitwise_xor(u8 *ina, u8 *inb, u8 *out) +{ + sint i; + for (i = 0; i < 16; i++) + out[i] = ina[i] ^ inb[i]; +} + +static sint aes_cipher(u8 *key, uint hdrlen, + u8 *pframe, uint plen) +{ + /* static unsigned char message[MAX_MSG_SIZE]; */ + uint qc_exists, a4_exists, i, j, payload_remainder, + num_blocks, payload_index; + + u8 pn_vector[6]; + u8 mic_iv[16]; + u8 mic_header1[16]; + u8 mic_header2[16]; + u8 ctr_preload[16]; + + /* Intermediate Buffers */ + u8 chain_buffer[16]; + u8 aes_out[16]; + u8 padded_buffer[16]; + u8 mic[8]; + /* uint offset = 0; */ + uint frtype = GetFrameType(pframe); + uint frsubtype = get_frame_sub_type(pframe); + + frsubtype = frsubtype >> 4; + + _rtw_memset((void *)mic_iv, 0, 16); + _rtw_memset((void *)mic_header1, 0, 16); + _rtw_memset((void *)mic_header2, 0, 16); + _rtw_memset((void *)ctr_preload, 0, 16); + _rtw_memset((void *)chain_buffer, 0, 16); + _rtw_memset((void *)aes_out, 0, 16); + _rtw_memset((void *)padded_buffer, 0, 16); + + if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen == WLAN_HDR_A3_QOS_LEN)) + a4_exists = 0; + else + a4_exists = 1; + + if ( + ((frtype | frsubtype) == WIFI_DATA_CFACK) || + ((frtype | frsubtype) == WIFI_DATA_CFPOLL) || + ((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) { + qc_exists = 1; + if (hdrlen != WLAN_HDR_A3_QOS_LEN) + + hdrlen += 2; + } + /* add for CONFIG_IEEE80211W, none 11w also can use */ + else if ((frtype == WIFI_DATA) && + ((frsubtype == 0x08) || + (frsubtype == 0x09) || + (frsubtype == 0x0a) || + (frsubtype == 0x0b))) { + if (hdrlen != WLAN_HDR_A3_QOS_LEN) + + hdrlen += 2; + qc_exists = 1; + } else + qc_exists = 0; + + pn_vector[0] = pframe[hdrlen]; + pn_vector[1] = pframe[hdrlen + 1]; + pn_vector[2] = pframe[hdrlen + 4]; + pn_vector[3] = pframe[hdrlen + 5]; + pn_vector[4] = pframe[hdrlen + 6]; + pn_vector[5] = pframe[hdrlen + 7]; + + construct_mic_iv( + mic_iv, + qc_exists, + a4_exists, + pframe, /* message, */ + plen, + pn_vector, + frtype /* add for CONFIG_IEEE80211W, none 11w also can use */ + ); + + construct_mic_header1( + mic_header1, + hdrlen, + pframe, /* message */ + frtype /* add for CONFIG_IEEE80211W, none 11w also can use */ + ); + construct_mic_header2( + mic_header2, + pframe, /* message, */ + a4_exists, + qc_exists + ); + + payload_remainder = plen % 16; + num_blocks = plen / 16; + + /* Find start of payload */ + payload_index = (hdrlen + 8); + + /* Calculate MIC */ + aes128k128d(key, mic_iv, aes_out); + bitwise_xor(aes_out, mic_header1, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + bitwise_xor(aes_out, mic_header2, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + + for (i = 0; i < num_blocks; i++) { + bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */ + + payload_index += 16; + aes128k128d(key, chain_buffer, aes_out); + } + + /* Add on the final payload block if it needs padding */ + if (payload_remainder > 0) { + for (j = 0; j < 16; j++) + padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) { + padded_buffer[j] = pframe[payload_index++];/* padded_buffer[j] = message[payload_index++]; */ + } + bitwise_xor(aes_out, padded_buffer, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + + } + + for (j = 0 ; j < 8; j++) + mic[j] = aes_out[j]; + + /* Insert MIC into payload */ + for (j = 0; j < 8; j++) + pframe[payload_index + j] = mic[j]; /* message[payload_index+j] = mic[j]; */ + + payload_index = hdrlen + 8; + for (i = 0; i < num_blocks; i++) { + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, /* message, */ + pn_vector, + i + 1, + frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */ + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);/* bitwise_xor(aes_out, &message[payload_index], chain_buffer); */ + for (j = 0; j < 16; j++) + pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; */ + } + + if (payload_remainder > 0) { /* If there is a short final block, then pad it,*/ + /* encrypt it and copy the unpadded part back */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, /* message, */ + pn_vector, + num_blocks + 1, + frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */ + + for (j = 0; j < 16; j++) + padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) { + padded_buffer[j] = pframe[payload_index + j]; /* padded_buffer[j] = message[payload_index+j]; */ + } + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j = 0; j < payload_remainder; j++) + pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<payload_remainder;j++) message[payload_index++] = chain_buffer[j]; */ + } + + /* Encrypt the MIC */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, /* message, */ + pn_vector, + 0, + frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */ + + for (j = 0; j < 16; j++) + padded_buffer[j] = 0x00; + for (j = 0; j < 8; j++) { + padded_buffer[j] = pframe[j + hdrlen + 8 + plen]; /* padded_buffer[j] = message[j+hdrlen+8+plen]; */ + } + + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j = 0; j < 8; j++) + pframe[payload_index++] = chain_buffer[j];/* for (j=0; j<8;j++) message[payload_index++] = chain_buffer[j]; */ + return _SUCCESS; +} + +u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe) +{ + /* exclude ICV */ + + /*static*/ + /* unsigned char message[MAX_MSG_SIZE]; */ + + /* Intermediate Buffers */ + sint curfragnum, length; + u32 prwskeylen; + u8 *pframe, *prwskey; /* , *payload,*iv */ + u8 hw_hdr_offset = 0; + /* struct sta_info *stainfo=NULL; */ + struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + /* uint offset = 0; */ + u32 res = _SUCCESS; + + if (((struct xmit_frame *)pxmitframe)->buf_addr == NULL) + return _FAIL; + + hw_hdr_offset = TXDESC_OFFSET; + + pframe = ((struct xmit_frame *)pxmitframe)->buf_addr + hw_hdr_offset; + + /* 4 start to encrypt each fragment */ + if ((pattrib->encrypt == _AES_)) { + /* + if(pattrib->psta) + { + stainfo = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); + } + */ + /* if (stainfo!=NULL) */ + { + /* + if(!(stainfo->state &_FW_LINKED)) + { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); + return _FAIL; + } + */ + + if (IS_MCAST(pattrib->ra)) + prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + else { + /* prwskey=&stainfo->dot118021x_UncstKey.skey[0]; */ + prwskey = pattrib->dot118021x_UncstKey.skey; + } + + prwskeylen = 16; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + + if ((curfragnum + 1) == pattrib->nr_frags) { /* 4 the last fragment */ + length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; + + aes_cipher(prwskey, pattrib->hdrlen, pframe, length); + } else { + length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len ; + + aes_cipher(prwskey, pattrib->hdrlen, pframe, length); + pframe += pxmitpriv->frag_len; + pframe = (u8 *)RND4((SIZE_PTR)(pframe)); + + } + } + + AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + } + /* + else{ + RTW_INFO("%s, psta==NUL\n", __func__); + res=_FAIL; + } + */ + } + + return res; +} + +static sint aes_decipher(u8 *key, uint hdrlen, + u8 *pframe, uint plen) +{ + static u8 message[MAX_MSG_SIZE]; + uint qc_exists, a4_exists, i, j, payload_remainder, + num_blocks, payload_index; + sint res = _SUCCESS; + u8 pn_vector[6]; + u8 mic_iv[16]; + u8 mic_header1[16]; + u8 mic_header2[16]; + u8 ctr_preload[16]; + + /* Intermediate Buffers */ + u8 chain_buffer[16]; + u8 aes_out[16]; + u8 padded_buffer[16]; + u8 mic[8]; + + /* uint offset = 0; */ + uint frtype = GetFrameType(pframe); + uint frsubtype = get_frame_sub_type(pframe); + frsubtype = frsubtype >> 4; + + _rtw_memset((void *)mic_iv, 0, 16); + _rtw_memset((void *)mic_header1, 0, 16); + _rtw_memset((void *)mic_header2, 0, 16); + _rtw_memset((void *)ctr_preload, 0, 16); + _rtw_memset((void *)chain_buffer, 0, 16); + _rtw_memset((void *)aes_out, 0, 16); + _rtw_memset((void *)padded_buffer, 0, 16); + + /* start to decrypt the payload */ + + num_blocks = (plen - 8) / 16; /* (plen including LLC, payload_length and mic ) */ + + payload_remainder = (plen - 8) % 16; + + pn_vector[0] = pframe[hdrlen]; + pn_vector[1] = pframe[hdrlen + 1]; + pn_vector[2] = pframe[hdrlen + 4]; + pn_vector[3] = pframe[hdrlen + 5]; + pn_vector[4] = pframe[hdrlen + 6]; + pn_vector[5] = pframe[hdrlen + 7]; + + if ((hdrlen == WLAN_HDR_A3_LEN) || (hdrlen == WLAN_HDR_A3_QOS_LEN)) + a4_exists = 0; + else + a4_exists = 1; + + if ( + ((frtype | frsubtype) == WIFI_DATA_CFACK) || + ((frtype | frsubtype) == WIFI_DATA_CFPOLL) || + ((frtype | frsubtype) == WIFI_DATA_CFACKPOLL)) { + qc_exists = 1; + if (hdrlen != WLAN_HDR_A3_QOS_LEN) + + hdrlen += 2; + } /* only for data packet . add for CONFIG_IEEE80211W, none 11w also can use */ + else if ((frtype == WIFI_DATA) && + ((frsubtype == 0x08) || + (frsubtype == 0x09) || + (frsubtype == 0x0a) || + (frsubtype == 0x0b))) { + if (hdrlen != WLAN_HDR_A3_QOS_LEN) + + hdrlen += 2; + qc_exists = 1; + } else + qc_exists = 0; + + /* now, decrypt pframe with hdrlen offset and plen long */ + + payload_index = hdrlen + 8; /* 8 is for extiv */ + + for (i = 0; i < num_blocks; i++) { + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, + pn_vector, + i + 1, + frtype /* add for CONFIG_IEEE80211W, none 11w also can use */ + ); + + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, &pframe[payload_index], chain_buffer); + + for (j = 0; j < 16; j++) + pframe[payload_index++] = chain_buffer[j]; + } + + if (payload_remainder > 0) { /* If there is a short final block, then pad it,*/ + /* encrypt it and copy the unpadded part back */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, + pn_vector, + num_blocks + 1, + frtype /* add for CONFIG_IEEE80211W, none 11w also can use */ + ); + + for (j = 0; j < 16; j++) + padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + padded_buffer[j] = pframe[payload_index + j]; + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j = 0; j < payload_remainder; j++) + pframe[payload_index++] = chain_buffer[j]; + } + + /* start to calculate the mic */ + if ((hdrlen + plen + 8) <= MAX_MSG_SIZE) + _rtw_memcpy((void *)message, pframe, (hdrlen + plen + 8)); /* 8 is for ext iv len */ + + pn_vector[0] = pframe[hdrlen]; + pn_vector[1] = pframe[hdrlen + 1]; + pn_vector[2] = pframe[hdrlen + 4]; + pn_vector[3] = pframe[hdrlen + 5]; + pn_vector[4] = pframe[hdrlen + 6]; + pn_vector[5] = pframe[hdrlen + 7]; + + construct_mic_iv( + mic_iv, + qc_exists, + a4_exists, + message, + plen - 8, + pn_vector, + frtype /* add for CONFIG_IEEE80211W, none 11w also can use */ + ); + + construct_mic_header1( + mic_header1, + hdrlen, + message, + frtype /* add for CONFIG_IEEE80211W, none 11w also can use */ + ); + construct_mic_header2( + mic_header2, + message, + a4_exists, + qc_exists + ); + + payload_remainder = (plen - 8) % 16; + num_blocks = (plen - 8) / 16; + + /* Find start of payload */ + payload_index = (hdrlen + 8); + + /* Calculate MIC */ + aes128k128d(key, mic_iv, aes_out); + bitwise_xor(aes_out, mic_header1, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + bitwise_xor(aes_out, mic_header2, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + + for (i = 0; i < num_blocks; i++) { + bitwise_xor(aes_out, &message[payload_index], chain_buffer); + + payload_index += 16; + aes128k128d(key, chain_buffer, aes_out); + } + + /* Add on the final payload block if it needs padding */ + if (payload_remainder > 0) { + for (j = 0; j < 16; j++) + padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + padded_buffer[j] = message[payload_index++]; + bitwise_xor(aes_out, padded_buffer, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + + } + + for (j = 0 ; j < 8; j++) + mic[j] = aes_out[j]; + + /* Insert MIC into payload */ + for (j = 0; j < 8; j++) + message[payload_index + j] = mic[j]; + + payload_index = hdrlen + 8; + for (i = 0; i < num_blocks; i++) { + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + message, + pn_vector, + i + 1, + frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */ + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, &message[payload_index], chain_buffer); + for (j = 0; j < 16; j++) + message[payload_index++] = chain_buffer[j]; + } + + if (payload_remainder > 0) { /* If there is a short final block, then pad it,*/ + /* encrypt it and copy the unpadded part back */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + message, + pn_vector, + num_blocks + 1, + frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */ + + for (j = 0; j < 16; j++) + padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + padded_buffer[j] = message[payload_index + j]; + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j = 0; j < payload_remainder; j++) + message[payload_index++] = chain_buffer[j]; + } + + /* Encrypt the MIC */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + message, + pn_vector, + 0, + frtype); /* add for CONFIG_IEEE80211W, none 11w also can use */ + + for (j = 0; j < 16; j++) + padded_buffer[j] = 0x00; + for (j = 0; j < 8; j++) + padded_buffer[j] = message[j + hdrlen + 8 + plen - 8]; + + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j = 0; j < 8; j++) + message[payload_index++] = chain_buffer[j]; + + /* compare the mic */ + for (i = 0; i < 8; i++) { + if (pframe[hdrlen + 8 + plen - 8 + i] != message[hdrlen + 8 + plen - 8 + i]) { + RTW_INFO("aes_decipher:mic check error mic[%d]: pframe(%x) != message(%x)\n", + i, pframe[hdrlen + 8 + plen - 8 + i], message[hdrlen + 8 + plen - 8 + i]); + res = _FAIL; + } + } + return res; +} + +u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe) +{ + /* exclude ICV */ + + /*static*/ + /* unsigned char message[MAX_MSG_SIZE]; */ + + /* Intermediate Buffers */ + + sint length; + u8 *pframe, *prwskey; /* , *payload,*iv */ + struct sta_info *stainfo; + struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + /* struct recv_priv *precvpriv=&padapter->recvpriv; */ + u32 res = _SUCCESS; + pframe = (unsigned char *)((union recv_frame *)precvframe)->u.hdr.rx_data; + /* 4 start to encrypt each fragment */ + if ((prxattrib->encrypt == _AES_)) { + + stainfo = rtw_get_stainfo(&padapter->stapriv , &prxattrib->ta[0]); + if (stainfo != NULL) { + + if (IS_MCAST(prxattrib->ra)) { + static u32 start = 0; + static u32 no_gkey_bc_cnt = 0; + static u32 no_gkey_mc_cnt = 0; + + /* RTW_INFO("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); */ + /* prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; */ + if (psecuritypriv->binstallGrpkey == _FALSE) { + res = _FAIL; + + if (start == 0) + start = rtw_get_current_time(); + + if (is_broadcast_mac_addr(prxattrib->ra)) + no_gkey_bc_cnt++; + else + no_gkey_mc_cnt++; + + if (rtw_get_passing_time_ms(start) > 1000) { + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + RTW_PRINT(FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = rtw_get_current_time(); + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + } + + goto exit; + } + + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + RTW_PRINT(FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = 0; + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + + prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; + if (psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) { + RTW_DBG("not match packet_index=%d, install_index=%d\n" + , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); + res = _FAIL; + goto exit; + } + } else + prwskey = &stainfo->dot118021x_UncstKey.skey[0]; + + length = ((union recv_frame *)precvframe)->u.hdr.len - prxattrib->hdrlen - prxattrib->iv_len; + + res = aes_decipher(prwskey, prxattrib->hdrlen, pframe, length); + + AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); + } else { + res = _FAIL; + } + + } +exit: + return res; +} + + +/* AES tables*/ +const u32 Te0[256] = { + 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, + 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, + 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU, + 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU, + 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U, + 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, + 0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, + 0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU, + 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU, + 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU, + 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, + 0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU, + 0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU, + 0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U, + 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU, + 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, + 0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, + 0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU, + 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU, + 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U, + 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, + 0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, + 0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU, + 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU, + 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U, + 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, + 0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, + 0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U, + 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU, + 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U, + 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, + 0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, + 0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU, + 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U, + 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U, + 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, + 0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, + 0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U, + 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU, + 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U, + 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, + 0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, + 0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U, + 0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU, + 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U, + 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, + 0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, + 0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U, + 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U, + 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U, + 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, + 0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, + 0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU, + 0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U, + 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U, + 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, + 0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U, + 0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U, + 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U, + 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU, + 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, + 0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U, + 0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U, + 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU, +}; +const u32 Td0[256] = { + 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, + 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, + 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U, + 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU, + 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U, + 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, + 0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU, + 0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U, + 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU, + 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U, + 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, + 0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, + 0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U, + 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU, + 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U, + 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, + 0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, + 0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU, + 0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U, + 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U, + 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, + 0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU, + 0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U, + 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU, + 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U, + 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, + 0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U, + 0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU, + 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU, + 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U, + 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, + 0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, + 0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU, + 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U, + 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U, + 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, + 0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, + 0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U, + 0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U, + 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU, + 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, + 0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, + 0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U, + 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U, + 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U, + 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, + 0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, + 0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U, + 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U, + 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U, + 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, + 0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, + 0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU, + 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU, + 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU, + 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, + 0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, + 0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU, + 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU, + 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U, + 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, + 0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U, + 0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U, + 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U, +}; +const u8 Td4s[256] = { + 0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, + 0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, + 0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U, + 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU, + 0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, + 0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU, + 0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U, + 0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U, + 0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U, + 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U, + 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU, + 0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, + 0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU, + 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U, + 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, + 0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, + 0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU, + 0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U, + 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U, + 0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, + 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U, + 0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU, + 0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U, + 0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U, + 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U, + 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, + 0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, + 0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU, + 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U, + 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, + 0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, + 0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU, +}; +const u8 rcons[] = { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36 + /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */ +}; + +/* Restore HW wep key setting according to key_mask */ +void rtw_sec_restore_wep_key(_adapter *adapter) +{ + struct security_priv *securitypriv = &(adapter->securitypriv); + sint keyid; + + if ((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) || (_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) { + for (keyid = 0; keyid < 4; keyid++) { + if (securitypriv->key_mask & BIT(keyid)) { + if (keyid == securitypriv->dot11PrivacyKeyIndex) + rtw_set_key(adapter, securitypriv, keyid, 1, _FALSE); + else + rtw_set_key(adapter, securitypriv, keyid, 0, _FALSE); + } + } + } +} + +u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller) +{ + struct security_priv *securitypriv = &(adapter->securitypriv); + u8 status = _SUCCESS; + + if (securitypriv->btkip_countermeasure == _TRUE) { + u32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time); + if (passing_ms > 60 * 1000) { + RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds > 60s\n", + caller, ADPT_ARG(adapter), passing_ms / 1000); + securitypriv->btkip_countermeasure = _FALSE; + securitypriv->btkip_countermeasure_time = 0; + } else { + RTW_PRINT("%s("ADPT_FMT") countermeasure time:%ds < 60s\n", + caller, ADPT_ARG(adapter), passing_ms / 1000); + status = _FAIL; + } + } + + return status; +} diff --git a/drivers/staging/rtl8821ce/core/rtw_sreset.c b/drivers/staging/rtl8821ce/core/rtw_sreset.c new file mode 100644 index 000000000000..35feb41ebf12 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_sreset.c @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <hal_data.h> +#include <rtw_sreset.h> + +void sreset_init_value(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + + _rtw_mutex_init(&psrtpriv->silentreset_mutex); + psrtpriv->silent_reset_inprogress = _FALSE; + psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; + psrtpriv->last_tx_time = 0; + psrtpriv->last_tx_complete_time = 0; +} +void sreset_reset_value(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + + psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; + psrtpriv->last_tx_time = 0; + psrtpriv->last_tx_complete_time = 0; +} + +u8 sreset_get_wifi_status(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + + u8 status = WIFI_STATUS_SUCCESS; + u32 val32 = 0; + _irqL irqL; + if (psrtpriv->silent_reset_inprogress == _TRUE) + return status; + val32 = rtw_read32(padapter, REG_TXDMA_STATUS); + if (val32 == 0xeaeaeaea) + psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST; + else if (val32 != 0) { + RTW_INFO("txdmastatu(%x)\n", val32); + psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR; + } + + if (WIFI_STATUS_SUCCESS != psrtpriv->Wifi_Error_Status) { + RTW_INFO("==>%s error_status(0x%x)\n", __FUNCTION__, psrtpriv->Wifi_Error_Status); + status = (psrtpriv->Wifi_Error_Status & (~(USB_READ_PORT_FAIL | USB_WRITE_PORT_FAIL))); + } + RTW_INFO("==> %s wifi_status(0x%x)\n", __FUNCTION__, status); + + /* status restore */ + psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; + + return status; +} + +bool sreset_inprogress(_adapter *padapter) +{ + return _FALSE; +} + +void sreset_restore_security_station(_adapter *padapter) +{ + u8 EntryId = 0; + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; + + { + u8 val8; + + if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) { + val8 = 0xcc; + } else + val8 = 0xcf; + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + } + + if ((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { + psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv)); + if (psta == NULL) { + /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ + } else { + /* pairwise key */ + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _FALSE); + /* group key */ + rtw_set_key(padapter, &padapter->securitypriv, padapter->securitypriv.dot118021XGrpKeyid, 0, _FALSE); + } + } +} + +void sreset_restore_network_station(_adapter *padapter) +{ + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 doiqk = _FALSE; + + rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure, _FALSE); + + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk); + + set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + /* disable dynamic functions, such as high power, DIG */ + /*rtw_phydm_func_disable_all(padapter);*/ + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); + + { + u8 join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + } + + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + + mlmeext_joinbss_event_callback(padapter, 1); + /* restore Sequence No. */ + rtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0); + + sreset_restore_security_station(padapter); +} + +void sreset_restore_network_status(_adapter *padapter) +{ + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + sreset_restore_network_station(padapter); + } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) { + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + rtw_ap_restore_network(padapter); + } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + else + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); +} + +void sreset_stop_adapter(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (padapter == NULL) + return; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + rtw_netif_stop_queue(padapter->pnetdev); + + rtw_cancel_all_timer(padapter); + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) + rtw_scan_abort(padapter); + + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) { + rtw_set_to_roam(padapter, 0); + rtw_join_timeout_handler(padapter); + } + +} + +void sreset_start_adapter(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (padapter == NULL) + return; + + RTW_INFO(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + if (check_fwstate(pmlmepriv, _FW_LINKED)) + sreset_restore_network_status(padapter); + + if (is_primary_adapter(padapter)) + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); + + rtw_netif_wake_queue(padapter->pnetdev); +} + +void sreset_reset(_adapter *padapter) +{ +} diff --git a/drivers/staging/rtl8821ce/core/rtw_sta_mgt.c b/drivers/staging/rtl8821ce/core/rtw_sta_mgt.c new file mode 100644 index 000000000000..76d9d306cae2 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_sta_mgt.c @@ -0,0 +1,872 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_STA_MGT_C_ + +#include <drv_types.h> + +bool test_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + if (ntohs(*((u16 *)local_port)) == 5001 || ntohs(*((u16 *)remote_port)) == 5001) + return _TRUE; + return _FALSE; +} + +struct st_register test_st_reg = { + .s_proto = 0x06, + .rule = test_st_match_rule, +}; + +inline void rtw_st_ctl_init(struct st_ctl_t *st_ctl) +{ + _rtw_memset(st_ctl->reg, 0 , sizeof(struct st_register) * SESSION_TRACKER_REG_ID_NUM); + _rtw_init_queue(&st_ctl->tracker_q); +} + +inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl) +{ + _irqL irqL; + _list *plist, *phead; + struct session_tracker *st; + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + phead = &st_ctl->tracker_q.queue; + plist = get_next(phead); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + plist = get_next(plist); + rtw_list_delete(&st->list); + rtw_mfree((u8 *)st, sizeof(struct session_tracker)); + } + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); +} + +inline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl) +{ + rtw_st_ctl_clear_tracker_q(st_ctl); + _rtw_deinit_queue(&st_ctl->tracker_q); +} + +inline void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg) +{ + if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) { + rtw_warn_on(1); + return; + } + + st_ctl->reg[st_reg_id].s_proto = reg->s_proto; + st_ctl->reg[st_reg_id].rule = reg->rule; +} + +inline void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id) +{ + int i; + + if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) { + rtw_warn_on(1); + return; + } + + st_ctl->reg[st_reg_id].s_proto = 0; + st_ctl->reg[st_reg_id].rule = NULL; + + /* clear tracker queue if no session trecker registered */ + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) + if (st_ctl->reg[i].s_proto != 0) + break; + if (i >= SESSION_TRACKER_REG_ID_NUM) + rtw_st_ctl_clear_tracker_q(st_ctl); +} + +inline bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto) +{ + bool ret = _FALSE; + int i; + + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) { + if (st_ctl->reg[i].s_proto == s_proto) { + ret = _TRUE; + break; + } + } + + return ret; +} + +inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + bool ret = _FALSE; + int i; + st_match_rule rule; + + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) { + rule = st_ctl->reg[i].rule; + if (rule && rule(adapter, local_naddr, local_port, remote_naddr, remote_port) == _TRUE) { + ret = _TRUE; + break; + } + } + + return ret; +} + +#define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d" +#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time) + +void _rtw_init_stainfo(struct sta_info *psta); +void _rtw_init_stainfo(struct sta_info *psta) +{ + + _rtw_memset((u8 *)psta, 0, sizeof(struct sta_info)); + + _rtw_spinlock_init(&psta->lock); + _rtw_init_listhead(&psta->list); + _rtw_init_listhead(&psta->hash_list); + /* _rtw_init_listhead(&psta->asoc_list); */ + /* _rtw_init_listhead(&psta->sleep_list); */ + /* _rtw_init_listhead(&psta->wakeup_list); */ + + _rtw_init_queue(&psta->sleep_q); + psta->sleepq_len = 0; + + _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); + _rtw_init_sta_recv_priv(&psta->sta_recvpriv); + + + _rtw_init_listhead(&psta->asoc_list); + + _rtw_init_listhead(&psta->auth_list); + + psta->expire_to = 0; + + psta->flags = 0; + + psta->capability = 0; + + psta->bpairwise_key_installed = _FALSE; + + + psta->nonerp_set = 0; + psta->no_short_slot_time_set = 0; + psta->no_short_preamble_set = 0; + psta->no_ht_gf_set = 0; + psta->no_ht_set = 0; + psta->ht_20mhz_set = 0; + psta->ht_40mhz_intolerant = 0; + + psta->under_exist_checking = 0; + + psta->keep_alive_trycnt = 0; + + + rtw_st_ctl_init(&psta->st_ctl); + +} + +u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) +{ + struct sta_info *psta; + s32 i; + + pstapriv->pallocated_stainfo_buf = rtw_zvmalloc(sizeof(struct sta_info) * NUM_STA + 4); + + if (!pstapriv->pallocated_stainfo_buf) + return _FAIL; + + pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 - + ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf) & 3); + + _rtw_init_queue(&pstapriv->free_sta_queue); + + _rtw_spinlock_init(&pstapriv->sta_hash_lock); + + /* _rtw_init_queue(&pstapriv->asoc_q); */ + pstapriv->asoc_sta_count = 0; + _rtw_init_queue(&pstapriv->sleep_q); + _rtw_init_queue(&pstapriv->wakeup_q); + + psta = (struct sta_info *)(pstapriv->pstainfo_buf); + + for (i = 0; i < NUM_STA; i++) { + _rtw_init_stainfo(psta); + + _rtw_init_listhead(&(pstapriv->sta_hash[i])); + + rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue)); + + psta++; + } + + pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */ + + + pstapriv->sta_dz_bitmap = 0; + pstapriv->tim_bitmap = 0; + + _rtw_init_listhead(&pstapriv->asoc_list); + _rtw_init_listhead(&pstapriv->auth_list); + _rtw_spinlock_init(&pstapriv->asoc_list_lock); + _rtw_spinlock_init(&pstapriv->auth_list_lock); + pstapriv->asoc_list_cnt = 0; + pstapriv->auth_list_cnt = 0; + + pstapriv->auth_to = 3; /* 3*2 = 6 sec */ + pstapriv->assoc_to = 3; + /* pstapriv->expire_to = 900; */ /* 900*2 = 1800 sec = 30 min, expire after no any traffic. */ + /* pstapriv->expire_to = 30; */ /* 30*2 = 60 sec = 1 min, expire after no any traffic. */ + pstapriv->expire_to = 3; /* 3*2 = 6 sec */ + pstapriv->max_num_sta = NUM_STA; + + + _rtw_init_queue(&(pstapriv->acl_list.acl_node_q)); + + + return _SUCCESS; + +} + +inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta) +{ + int offset = (((u8 *)sta) - stapriv->pstainfo_buf) / sizeof(struct sta_info); + + if (!stainfo_offset_valid(offset)) + RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset); + + return offset; +} + +inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset) +{ + if (!stainfo_offset_valid(offset)) + RTW_INFO("%s invalid offset(%d), out of range!!!", __func__, offset); + + return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info)); +} + +void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv); +void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv) +{ + + _rtw_spinlock_free(&psta_xmitpriv->lock); + + _rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock)); + _rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock)); + _rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock)); + _rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock)); +} + +static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv) +{ + + _rtw_spinlock_free(&psta_recvpriv->lock); + + _rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock)); + +} + +void rtw_mfree_stainfo(struct sta_info *psta); +void rtw_mfree_stainfo(struct sta_info *psta) +{ + + if (&psta->lock != NULL) + _rtw_spinlock_free(&psta->lock); + + _rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv); + _rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv); + +} + +/* this function is used to free the memory of lock || sema for all stainfos */ +void rtw_mfree_all_stainfo(struct sta_priv *pstapriv); +void rtw_mfree_all_stainfo(struct sta_priv *pstapriv) +{ + _irqL irqL; + _list *plist, *phead; + struct sta_info *psta = NULL; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + phead = get_list_head(&pstapriv->free_sta_queue); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info , list); + plist = get_next(plist); + + rtw_mfree_stainfo(psta); + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + +} + +void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv); +void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv) +{ + rtw_mfree_all_stainfo(pstapriv); /* be done before free sta_hash_lock */ + + _rtw_spinlock_free(&pstapriv->free_sta_queue.lock); + + _rtw_spinlock_free(&pstapriv->sta_hash_lock); + _rtw_spinlock_free(&pstapriv->wakeup_q.lock); + _rtw_spinlock_free(&pstapriv->sleep_q.lock); + + _rtw_spinlock_free(&pstapriv->asoc_list_lock); + _rtw_spinlock_free(&pstapriv->auth_list_lock); + +} + +u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) +{ + _irqL irqL; + _list *phead, *plist; + struct sta_info *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl; + int index; + + if (pstapriv) { + + /* delete all reordering_ctrl_timer */ + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (index = 0; index < NUM_STA; index++) { + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int i; + psta = LIST_CONTAINOR(plist, struct sta_info , hash_list); + plist = get_next(plist); + + for (i = 0; i < 16 ; i++) { + preorder_ctrl = &psta->recvreorder_ctrl[i]; + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); + } + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + /*===============================*/ + + rtw_mfree_sta_priv_lock(pstapriv); + + _rtw_deinit_queue(&(pstapriv->acl_list.acl_node_q)); + + + if (pstapriv->pallocated_stainfo_buf) + rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info) * NUM_STA + 4); + } + + return _SUCCESS; +} + +static void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) +{ + _adapter *padapter = preorder_ctrl->padapter; + + rtw_init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter, rtw_reordering_ctrl_timeout_handler, preorder_ctrl); + +} + +/* struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) */ +struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) +{ + _irqL irqL, irqL2; + uint tmp_aid; + s32 index; + _list *phash_list; + struct sta_info *psta; + _queue *pfree_sta_queue; + struct recv_reorder_ctrl *preorder_ctrl; + int i = 0; + u16 wRxSeqInitialValue = 0xffff; + + pfree_sta_queue = &pstapriv->free_sta_queue; + + /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL); */ + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) { + /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */ + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + psta = NULL; + } else { + psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list); + + rtw_list_delete(&(psta->list)); + + /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); */ + + tmp_aid = psta->aid; + + _rtw_init_stainfo(psta); + + psta->padapter = pstapriv->padapter; + + _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN); + + index = wifi_mac_hash(hwaddr); + + if (index >= NUM_STA) { + psta = NULL; + goto exit; + } + phash_list = &(pstapriv->sta_hash[index]); + + /* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + + rtw_list_insert_tail(&psta->hash_list, phash_list); + + pstapriv->asoc_sta_count++; + + /* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); */ + + /* Commented by Albert 2009/08/13 + * For the SMC router, the sequence number of first packet of WPS handshake will be 0. + * In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. + * So, we initialize the tid_rxseq variable as the 0xffff. */ + + for (i = 0; i < 16; i++) { + _rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2); + _rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i])); + } + + rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta); + + /* for A-MPDU Rx reordering buffer control */ + for (i = 0; i < 16 ; i++) { + preorder_ctrl = &psta->recvreorder_ctrl[i]; + + preorder_ctrl->padapter = pstapriv->padapter; + + preorder_ctrl->enable = _FALSE; + + preorder_ctrl->indicate_seq = 0xffff; + preorder_ctrl->wend_b = 0xffff; + /* preorder_ctrl->wsize_b = (NR_RECVBUFF-2); */ + preorder_ctrl->wsize_b = 64;/* 64; */ + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + + _rtw_init_queue(&preorder_ctrl->pending_recvframe_queue); + + rtw_init_recv_timer(preorder_ctrl); + } + + /* init for DM */ + psta->rssi_stat.undecorated_smoothed_pwdb = (-1); + psta->rssi_stat.undecorated_smoothed_cck = (-1); + /* init for the sequence number of received management frame */ + psta->RxMgmtFrameSeqNum = 0xffff; + psta->ra_rpt_linked = _FALSE; + + rtw_alloc_macid(pstapriv->padapter, psta); + + } + +exit: + + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + + if (psta) + rtw_mi_update_iface_status(&(pstapriv->padapter->mlmepriv), 0); + + return psta; +} + +/* using pstapriv->sta_hash_lock to protect */ +u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) +{ + int i; + _irqL irqL0; + _queue *pfree_sta_queue; + struct recv_reorder_ctrl *preorder_ctrl; + struct sta_xmit_priv *pstaxmitpriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct hw_xmit *phwxmit; + int pending_qcnt[4]; + u8 is_pre_link_sta = _FALSE; + + if (psta == NULL) + goto exit; + + is_pre_link_sta = rtw_is_pre_link_sta(pstapriv, psta->hwaddr); + + if (is_pre_link_sta == _FALSE) { + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_list_delete(&psta->hash_list); + pstapriv->asoc_sta_count--; + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_mi_update_iface_status(&(padapter->mlmepriv), 0); + } else { + _enter_critical_bh(&psta->lock, &irqL0); + psta->state = WIFI_FW_PRE_LINK; + _exit_critical_bh(&psta->lock, &irqL0); + } + + _enter_critical_bh(&psta->lock, &irqL0); + psta->state &= ~_FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL0); + + pfree_sta_queue = &pstapriv->free_sta_queue; + + pstaxmitpriv = &psta->sta_xmitpriv; + + /* rtw_list_delete(&psta->sleep_list); */ + + /* rtw_list_delete(&psta->wakeup_list); */ + + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + + rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q); + psta->sleepq_len = 0; + + /* vo */ + /* _enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */ + rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vo_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits; + phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt; + pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt; + pstaxmitpriv->vo_q.qcnt = 0; + /* _exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); */ + + /* vi */ + /* _enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */ + rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->vi_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits + 1; + phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt; + pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt; + pstaxmitpriv->vi_q.qcnt = 0; + /* _exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); */ + + /* be */ + /* _enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */ + rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->be_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits + 2; + phwxmit->accnt -= pstaxmitpriv->be_q.qcnt; + pending_qcnt[2] = pstaxmitpriv->be_q.qcnt; + pstaxmitpriv->be_q.qcnt = 0; + /* _exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); */ + + /* bk */ + /* _enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */ + rtw_free_xmitframe_queue(pxmitpriv, &pstaxmitpriv->bk_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits + 3; + phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt; + pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt; + pstaxmitpriv->bk_q.qcnt = 0; + /* _exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); */ + + rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt); + + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + + /* re-init sta_info; 20061114 */ /* will be init in alloc_stainfo */ + /* _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); */ + /* _rtw_init_sta_recv_priv(&psta->sta_recvpriv); */ + _cancel_timer_ex(&psta->addba_retry_timer); + + /* for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer */ + for (i = 0; i < 16 ; i++) { + _irqL irqL; + _list *phead, *plist; + union recv_frame *prframe; + _queue *ppending_recvframe_queue; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + + preorder_ctrl = &psta->recvreorder_ctrl[i]; + + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); + + ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + + _enter_critical_bh(&ppending_recvframe_queue->lock, &irqL); + + phead = get_list_head(ppending_recvframe_queue); + plist = get_next(phead); + + while (!rtw_is_list_empty(phead)) { + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + + plist = get_next(plist); + + rtw_list_delete(&(prframe->u.hdr.list)); + + rtw_free_recvframe(prframe, pfree_recv_queue); + } + + _exit_critical_bh(&ppending_recvframe_queue->lock, &irqL); + + } + + if (!((psta->state & WIFI_AP_STATE) || MacAddr_isBcst(psta->hwaddr)) && is_pre_link_sta == _FALSE) + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE); + + /* release mac id for non-bc/mc station, */ + if (is_pre_link_sta == _FALSE) + rtw_release_macid(pstapriv->padapter, psta); + + + /* + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0); + rtw_list_delete(&psta->asoc_list); + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0); + */ + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL0); + if (!rtw_is_list_empty(&psta->auth_list)) { + rtw_list_delete(&psta->auth_list); + pstapriv->auth_list_cnt--; + } + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL0); + + psta->expire_to = 0; + psta->sleepq_ac_len = 0; + psta->qos_info = 0; + + psta->max_sp_len = 0; + psta->uapsd_bk = 0; + psta->uapsd_be = 0; + psta->uapsd_vi = 0; + psta->uapsd_vo = 0; + + psta->has_legacy_ac = 0; + + + pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + /* rtw_indicate_sta_disassoc_event(padapter, psta); */ + + if ((psta->aid > 0) && (pstapriv->sta_aid[psta->aid - 1] == psta)) { + pstapriv->sta_aid[psta->aid - 1] = NULL; + psta->aid = 0; + } + + + psta->under_exist_checking = 0; + + + rtw_st_ctl_deinit(&psta->st_ctl); + + if (is_pre_link_sta == _FALSE) { + _rtw_spinlock_free(&psta->lock); + + /* _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue)); + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + /* _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); */ + } + +exit: + return _SUCCESS; +} + +/* free all stainfo which in sta_hash[all] */ +void rtw_free_all_stainfo(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + s32 index; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter); + u8 free_sta_num = 0; + char free_sta_list[NUM_STA]; + int stainfo_offset; + + if (pstapriv->asoc_sta_count == 1) + goto exit; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (index = 0; index < NUM_STA; index++) { + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info , hash_list); + + plist = get_next(plist); + + if (pbcmc_stainfo != psta) { + if (rtw_is_pre_link_sta(pstapriv, psta->hwaddr) == _FALSE) + rtw_list_delete(&psta->hash_list); + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) + free_sta_list[free_sta_num++] = stainfo_offset; + } + + } + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (index = 0; index < free_sta_num; index++) { + psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]); + rtw_free_stainfo(padapter , psta); + } + +exit: + return; +} + +/* any station allocated can be searched by hash list */ +struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) +{ + + _irqL irqL; + + _list *plist, *phead; + + struct sta_info *psta = NULL; + + u32 index; + + u8 *addr; + + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + if (hwaddr == NULL) + return NULL; + + if (IS_MCAST(hwaddr)) + addr = bc_addr; + else + addr = hwaddr; + + index = wifi_mac_hash(addr); + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN)) == _TRUE) { + /* if found the matched address */ + break; + } + psta = NULL; + plist = get_next(plist); + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + return psta; + +} + +u32 rtw_init_bcmc_stainfo(_adapter *padapter) +{ + + struct sta_info *psta; + struct tx_servq *ptxservq; + u32 res = _SUCCESS; + NDIS_802_11_MAC_ADDRESS bcast_addr = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + struct sta_priv *pstapriv = &padapter->stapriv; + /* _queue *pstapending = &padapter->xmitpriv.bm_pending; */ + + psta = rtw_alloc_stainfo(pstapriv, bcast_addr); + + if (psta == NULL) { + res = _FAIL; + goto exit; + } + ptxservq = &(psta->sta_xmitpriv.be_q); + + /* + _enter_critical(&pstapending->lock, &irqL0); + + if (rtw_is_list_empty(&ptxservq->tx_pending)) + rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending)); + + _exit_critical(&pstapending->lock, &irqL0); + */ + +exit: + return _SUCCESS; + +} + +struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter) +{ + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + psta = rtw_get_stainfo(pstapriv, bc_addr); + return psta; + +} + +const char *const _acl_mode_str[] = { + "DISABLED", + "ACCEPT_UNLESS_LISTED", + "DENY_UNLESS_LISTED", +}; + +u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr) +{ + u8 res = _TRUE; + _irqL irqL; + _list *list, *head; + struct rtw_wlan_acl_node *acl_node; + u8 match = _FALSE; + struct sta_priv *stapriv = &adapter->stapriv; + struct wlan_acl_pool *acl = &stapriv->acl_list; + _queue *acl_node_q = &acl->acl_node_q; + + _enter_critical_bh(&(acl_node_q->lock), &irqL); + head = get_list_head(acl_node_q); + list = get_next(head); + while (rtw_end_of_queue_search(head, list) == _FALSE) { + acl_node = LIST_CONTAINOR(list, struct rtw_wlan_acl_node, list); + list = get_next(list); + + if (_rtw_memcmp(acl_node->addr, mac_addr, ETH_ALEN)) { + if (acl_node->valid == _TRUE) { + match = _TRUE; + break; + } + } + } + _exit_critical_bh(&(acl_node_q->lock), &irqL); + + if (acl->mode == RTW_ACL_MODE_ACCEPT_UNLESS_LISTED) + res = (match == _TRUE) ? _FALSE : _TRUE; + else if (acl->mode == RTW_ACL_MODE_DENY_UNLESS_LISTED) + res = (match == _TRUE) ? _TRUE : _FALSE; + else + res = _TRUE; + + return res; +} + +bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr) +{ + return _FALSE; +} + + diff --git a/drivers/staging/rtl8821ce/core/rtw_vht.c b/drivers/staging/rtl8821ce/core/rtw_vht.c new file mode 100644 index 000000000000..2be8a4775f61 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_vht.c @@ -0,0 +1,670 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_VHT_C + +#include <drv_types.h> +#include <hal_data.h> + +/* 20/40/80, ShortGI, MCS Rate */ +const u16 VHT_MCS_DATA_RATE[3][2][30] = { + { { + 13, 26, 39, 52, 78, 104, 117, 130, 156, 156, + 26, 52, 78, 104, 156, 208, 234, 260, 312, 312, + 39, 78, 117, 156, 234, 312, 351, 390, 468, 520 + }, /* Long GI, 20MHz */ + { + 14, 29, 43, 58, 87, 116, 130, 144, 173, 173, + 29, 58, 87, 116, 173, 231, 260, 289, 347, 347, + 43, 87, 130, 173, 260, 347, 390, 433, 520, 578 + } + }, /* Short GI, 20MHz */ + { { + 27, 54, 81, 108, 162, 216, 243, 270, 324, 360, + 54, 108, 162, 216, 324, 432, 486, 540, 648, 720, + 81, 162, 243, 324, 486, 648, 729, 810, 972, 1080 + }, /* Long GI, 40MHz */ + { + 30, 60, 90, 120, 180, 240, 270, 300, 360, 400, + 60, 120, 180, 240, 360, 480, 540, 600, 720, 800, + 90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200 + } + }, /* Short GI, 40MHz */ + { { + 59, 117, 176, 234, 351, 468, 527, 585, 702, 780, + 117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560, + 176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340 + }, /* Long GI, 80MHz */ + { + 65, 130, 195, 260, 390, 520, 585, 650, 780, 867, + 130, 260, 390, 520, 780, 1040, 1170, 1300, 1560, 1734, + 195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600 + } + } /* Short GI, 80MHz */ +}; + +u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map) +{ + u8 i, j; + u8 bit_map; + u8 vht_mcs_rate = 0; + + for (i = 0; i < 2; i++) { + if (pvht_mcs_map[i] != 0xff) { + for (j = 0; j < 8; j += 2) { + bit_map = (pvht_mcs_map[i] >> j) & 3; + + if (bit_map != 3) + vht_mcs_rate = MGN_VHT1SS_MCS7 + 10 * j / 2 + i * 40 + bit_map; /* VHT rate indications begin from 0x90 */ + } + } + } + + /* RTW_INFO("HighestVHTMCSRate is %x\n", vht_mcs_rate); */ + return vht_mcs_rate; +} + +u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map) +{ + u8 i, j; + u8 bit_map; + u8 nss = 0; + + for (i = 0; i < 2; i++) { + if (pvht_mcs_map[i] != 0xff) { + for (j = 0; j < 8; j += 2) { + bit_map = (pvht_mcs_map[i] >> j) & 3; + + if (bit_map != 3) + nss++; + } + } + } + + /* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */ + return nss; +} + +void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map) +{ + u8 i, j; + u8 cur_rate, target_rate; + + for (i = 0; i < 2; i++) { + target_mcs_map[i] = 0; + for (j = 0; j < 8; j += 2) { + cur_rate = (cur_mcs_map[i] >> j) & 3; + if (cur_rate == 3) /* 0x3 indicates not supported that num of SS */ + target_rate = 3; + else if (nss <= ((j / 2) + i * 4)) + target_rate = 3; + else + target_rate = cur_rate; + + target_mcs_map[i] |= (target_rate << j); + } + } + + /* RTW_INFO("%s : %dSS\n", __FUNCTION__, nss); */ +} + +u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate) +{ + if (vht_mcs_rate > MGN_VHT3SS_MCS9) + vht_mcs_rate = MGN_VHT3SS_MCS9; + /* RTW_INFO("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */ + return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0) & 0x3f)]; +} + +void rtw_vht_use_default_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + u8 rf_type = 0; + u8 tx_nss, rx_nss; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE; + + /* LDPC support */ + rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport); + CLEAR_FLAGS(pvhtpriv->ldpc_cap); + if (bHwLDPCSupport) { + if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT0)) + SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport); + if (bHwLDPCSupport) { + if (TEST_FLAG(pregistrypriv->ldpc_cap, BIT1)) + SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX); + } + if (pvhtpriv->ldpc_cap) + RTW_INFO("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap); + + /* STBC */ + rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport); + CLEAR_FLAGS(pvhtpriv->stbc_cap); + if (bHwSTBCSupport) { + if (TEST_FLAG(pregistrypriv->stbc_cap, BIT1)) + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport); + if (bHwSTBCSupport) { + if (TEST_FLAG(pregistrypriv->stbc_cap, BIT0)) + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX); + } + if (pvhtpriv->stbc_cap) + RTW_INFO("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap); + + /* Beamforming setting */ + CLEAR_FLAGS(pvhtpriv->beamform_cap); + + pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + rx_nss = rtw_min(rf_type_to_rf_rx_cnt(rf_type), hal_spec->rx_nss_num); + + /* for now, vhtpriv.vht_mcs_map comes from RX NSS */ + rtw_vht_nss_to_mcsmap(rx_nss, pvhtpriv->vht_mcs_map, pregistrypriv->vht_rx_mcs_map); + pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); +} + +u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss) +{ + u8 i, j, tmp; + u64 bitmap = 0; + u8 bits_nss = nss * 2; + + for (i = j = 0; i < bits_nss; i += 2, j += 10) { + /* every two bits means single sptial stream */ + tmp = (mcs_map[i / 8] >> i) & 3; + + switch (tmp) { + case 2: + bitmap = bitmap | (0x03ff << j); + break; + case 1: + bitmap = bitmap | (0x01ff << j); + break; + case 0: + bitmap = bitmap | (0x00ff << j); + break; + default: + break; + } + } + + RTW_INFO("vht_mcs_map=%02x %02x, nss=%u => bitmap=%016llx\n" + , mcs_map[0], mcs_map[1], nss, bitmap); + + return bitmap; +} + +void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) +{ + struct sta_info *psta = (struct sta_info *)sta; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; + struct vht_priv *pvhtpriv_sta = &psta->vhtpriv; + struct ht_priv *phtpriv_sta = &psta->htpriv; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, bw_mode = 0; + u16 cur_beamform_cap = 0; + u8 *pcap_mcs; + + if (pvhtpriv_sta->vht_option == _FALSE) + return; + + bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify); + + /* if (bw_mode > psta->bw_mode) */ + psta->bw_mode = bw_mode; + + /* B4 Rx LDPC */ + if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) { + SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); + RTW_INFO("Current STA(%d) VHT LDPC = %02X\n", psta->aid, cur_ldpc_cap); + } + pvhtpriv_sta->ldpc_cap = cur_ldpc_cap; + + if (psta->bw_mode > pmlmeext->cur_bwmode) + psta->bw_mode = pmlmeext->cur_bwmode; + + if (psta->bw_mode == CHANNEL_WIDTH_80) { + /* B5 Short GI for 80 MHz */ + pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; + /* RTW_INFO("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); */ + } else if (psta->bw_mode >= CHANNEL_WIDTH_160) { + /* B5 Short GI for 80 MHz */ + pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; + /* RTW_INFO("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); */ + } + + /* B8 B9 B10 Rx STBC */ + if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) { + SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); + RTW_INFO("Current STA(%d) VHT STBC = %02X\n", psta->aid, cur_stbc_cap); + } + pvhtpriv_sta->stbc_cap = cur_stbc_cap; + + + /* B23 B24 B25 Maximum A-MPDU Length Exponent */ + pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap); + _rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2); + pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map); +} + +void update_hw_vht_param(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ht_AMPDU_len; + + ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + if (pvhtpriv->ampdu_len > ht_AMPDU_len) + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len)); +} + +void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R, tx_nss = 0; + u16 cur_beamform_cap = 0; + u8 *pcap_mcs; + + if (pIE == NULL) + return; + + if (pvhtpriv->vht_option == _FALSE) + return; + + pmlmeinfo->VHT_enable = 1; + + /* B4 Rx LDPC */ + if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) { + SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); + RTW_INFO("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap); + } + pvhtpriv->ldpc_cap = cur_ldpc_cap; + + /* B5 Short GI for 80 MHz */ + pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE; + /* RTW_INFO("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m); */ + + /* B8 B9 B10 Rx STBC */ + if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) { + SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); + RTW_INFO("Current VHT STBC Setting = %02X\n", cur_stbc_cap); + } + pvhtpriv->stbc_cap = cur_stbc_cap; + /* B23 B24 B25 Maximum A-MPDU Length Exponent */ + pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data); + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + rtw_vht_nss_to_mcsmap(tx_nss, pvhtpriv->vht_mcs_map, pcap_mcs); + pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); +} + +void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + + if (pIE == NULL) + return; + + if (pvhtpriv->vht_option == _FALSE) + return; +} + +void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) +{ + struct sta_info *psta = (struct sta_info *)sta; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 target_bw; + u8 target_rxss, current_rxss; + u8 update_ra = _FALSE; + + if (pvhtpriv->vht_option == _FALSE) + return; + + target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe); + target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe) + 1); + + if (target_bw != psta->bw_mode) { + if (hal_is_bw_support(padapter, target_bw) + && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) + ) { + update_ra = _TRUE; + psta->bw_mode = target_bw; + } + } + + current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map); + if (target_rxss != current_rxss) { + u8 vht_mcs_map[2] = {}; + + update_ra = _TRUE; + + rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map); + _rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2); + + rtw_hal_update_sta_rate_mask(padapter, psta); + } + + if (update_ra) + rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); +} + +u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + /* struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; */ + u8 ChnlWidth, center_freq, bw_mode; + u32 len = 0; + u8 operation[5]; + + _rtw_memset(operation, 0, 5); + + bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */ + + if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M) + && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80 + ) { + center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER); + ChnlWidth = 1; + } else { + center_freq = 0; + ChnlWidth = 0; + } + + SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth); + /* center frequency */ + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);/* Todo: need to set correct center channel */ + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation, 0); + + _rtw_memcpy(operation + 3, pvhtpriv->vht_mcs_map, 2); + + rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len); + + return len; +} + +u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw) +{ + /* struct registry_priv *pregistrypriv = &padapter->registrypriv; */ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + u32 len = 0; + u8 opmode = 0; + u8 chnl_width, rx_nss; + + chnl_width = bw; + rx_nss = rtw_vht_mcsmap_to_nss(pvhtpriv->vht_mcs_map); + + SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width); + SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss - 1)); + SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); /* Todo */ + + pvhtpriv->vht_op_mode_notify = opmode; + + pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len); + + return len; +} + +u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) +{ + u8 bw, rf_type, rf_num, rx_stbc_nss = 0; + u16 HighestRate; + u8 *pcap, *pcap_mcs; + u32 len = 0; + u32 rx_packet_offset, max_recvbuf_sz; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + + pcap = pvhtpriv->vht_cap; + _rtw_memset(pcap, 0, 32); + + /* B0 B1 Maximum MPDU Length */ + rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); + rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); + + RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n.", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset); + + if ((max_recvbuf_sz - rx_packet_offset) >= 11454) { + SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2); + RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n.", __FUNCTION__, __LINE__); + } else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) { + SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1); + RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n.", __FUNCTION__, __LINE__); + } else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) { + SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0); + RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n.", __FUNCTION__, __LINE__); + } else + RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n.", __FUNCTION__, __LINE__); + + /* B2 B3 Supported Channel Width Set */ + if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) { + if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80)) + SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2); + else + SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1); + } else + SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0); + + /* B4 Rx LDPC */ + if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) { + SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1); + RTW_INFO("[VHT] Declare supporting RX LDPC\n"); + } + + /* B5 ShortGI for 80MHz */ + SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m ? 1 : 0); /* We can receive Short GI of 80M */ + if (pvhtpriv->sgi_80m) + RTW_INFO("[VHT] Declare supporting SGI 80MHz\n"); + + /* B6 ShortGI for 160MHz */ + /* SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); */ + + /* B7 Tx STBC */ + if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) { + SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1); + RTW_INFO("[VHT] Declare supporting TX STBC\n"); + } + + /* B8 B9 B10 Rx STBC */ + if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) { + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss)); + + SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss); + RTW_INFO("[VHT] Declare supporting RX STBC = %d\n", rx_stbc_nss); + } + + /* B11 SU Beamformer Capable */ + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1); + RTW_INFO("[VHT] Declare supporting SU Bfer\n"); + /* B16 17 18 Number of Sounding Dimensions */ + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); + SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num); + /* B19 MU Beamformer Capable */ + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 1); + RTW_INFO("[VHT] Declare supporting MU Bfer\n"); + } + } + + /* B12 SU Beamformee Capable */ + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { + SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1); + RTW_INFO("[VHT] Declare supporting SU Bfee\n"); + /* B13 14 15 Compressed Steering Number of Beamformer Antennas Supported */ + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num); + /* B20 SU Beamformee Capable */ + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE)) { + SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 1); + RTW_INFO("[VHT] Declare supporting MU Bfee\n"); + } + } + + /* B21 VHT TXOP PS */ + SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0); + /* B22 +HTC-VHT Capable */ + SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1); + /* B23 24 25 Maximum A-MPDU Length Exponent */ + if (pregistrypriv->ampdu_factor != 0xFE) + SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor); + else + SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7); + /* B26 27 VHT Link Adaptation Capable */ + SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap); + _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap); + _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2); + + /* find the largest bw supported by both registry and hal */ + bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + + HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0) & 0x3f)]; + HighestRate = (HighestRate + 1) >> 1; + + SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest rx rate is 600Mbps. */ + SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); /* indicate we support highest tx rate is 600Mbps. */ + + pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len); + + return len; +} + +u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len) +{ + u32 ielen = 0, out_len = 0; + u8 cap_len = 0, notify_len = 0, notify_bw = 0, operation_bw = 0, supported_chnl_width = 0; + u8 *p, *pframe; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + + rtw_vht_use_default_setting(padapter); + + p = rtw_get_ie(in_ie + 12, EID_VHTCapability, &ielen, in_len - 12); + if (p && ielen > 0) { + supported_chnl_width = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); + + /* VHT Capabilities element */ + cap_len = rtw_build_vht_cap_ie(padapter, out_ie + *pout_len); + *pout_len += cap_len; + + /* Get HT BW */ + p = rtw_get_ie(in_ie + 12, _HT_EXTRA_INFO_IE_, &ielen, in_len - 12); + if (p && ielen > 0) { + struct HT_info_element *pht_info = (struct HT_info_element *)(p + 2); + if (pht_info->infos[0] & BIT(2)) + operation_bw = CHANNEL_WIDTH_40; + else + operation_bw = CHANNEL_WIDTH_20; + } + + /* VHT Operation element */ + p = rtw_get_ie(in_ie + 12, EID_VHTOperation, &ielen, in_len - 12); + if (p && ielen > 0) { + out_len = *pout_len; + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(p + 2) >= 1) { + if (supported_chnl_width == 2) + operation_bw = CHANNEL_WIDTH_80_80; + else if (supported_chnl_width == 1) + operation_bw = CHANNEL_WIDTH_160; + else + operation_bw = CHANNEL_WIDTH_80; + } + pframe = rtw_set_ie(out_ie + out_len, EID_VHTOperation, ielen, p + 2 , pout_len); + } + + /* find the largest bw supported by both registry and hal */ + notify_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + + if (notify_bw > operation_bw) + notify_bw = operation_bw; + + /* Operating Mode Notification element */ + notify_len = rtw_build_vht_op_mode_notify_ie(padapter, out_ie + *pout_len, notify_bw); + *pout_len += notify_len; + + pvhtpriv->vht_option = _TRUE; + } + + return pvhtpriv->vht_option; + +} + +void VHTOnAssocRsp(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ht_AMPDU_len; + + RTW_INFO("%s\n", __FUNCTION__); + + if (!pmlmeinfo->HT_enable) + return; + + if (!pmlmeinfo->VHT_enable) + return; + + ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + if (pvhtpriv->ampdu_len > ht_AMPDU_len) + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len)); + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate)); +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_wlan_util.c b/drivers/staging/rtl8821ce/core/rtw_wlan_util.c new file mode 100644 index 000000000000..bec6d78b31d8 --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_wlan_util.c @@ -0,0 +1,2935 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_WLAN_UTIL_C_ + +#include <drv_types.h> +#include <hal_data.h> + + +unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f}; +unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74}; + +unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18}; +unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7}; +unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5}; + +unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96}; +unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43}; +unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43}; +unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c}; +unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5}; + +unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20}; + +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WPA_TKIP_CIPHER[4]; +extern unsigned char RSN_TKIP_CIPHER[4]; + +#define R2T_PHY_DELAY (0) + +/* #define WAIT_FOR_BCN_TO_MIN (3000) */ +#define WAIT_FOR_BCN_TO_MIN (6000) +#define WAIT_FOR_BCN_TO_MAX (20000) + +#define DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS 1000 +#define DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD 3 + +static u8 rtw_basic_rate_cck[4] = { + IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK, + IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK +}; + +static u8 rtw_basic_rate_ofdm[3] = { + IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK, + IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK +}; + +static u8 rtw_basic_rate_mix[7] = { + IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK, + IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK, + IEEE80211_OFDM_RATE_6MB | IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB | IEEE80211_BASIC_RATE_MASK, + IEEE80211_OFDM_RATE_24MB | IEEE80211_BASIC_RATE_MASK +}; + +int new_bcn_max = 3; + +int cckrates_included(unsigned char *rate, int ratelen) +{ + int i; + + for (i = 0; i < ratelen; i++) { + if ((((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || + (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22)) + return _TRUE; + } + + return _FALSE; + +} + +int cckratesonly_included(unsigned char *rate, int ratelen) +{ + int i; + + for (i = 0; i < ratelen; i++) { + if ((((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && + (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22)) + return _FALSE; + } + + return _TRUE; +} + +#ifdef CONFIG_GET_RAID_BY_DRV +s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 rf_type = RF_1T1R, custom_rf_type; + s8 nss = 1; + + if (!psta) + return nss; + + custom_rf_type = adapter->registrypriv.rf_config; + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if (RF_TYPE_VALID(custom_rf_type)) + rf_type = custom_rf_type; + + if (psta->vhtpriv.vht_option) { + nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + nss = rtw_min(nss, rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map)); + } else + if (psta->htpriv.ht_option) { + nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + nss = rtw_min(nss, rtw_ht_mcsset_to_nss(psta->htpriv.ht_cap.supp_mcs_set)); + } + + RTW_INFO("%s: %d SS\n", __func__, nss); + return nss; +} + +u8 networktype_to_raid(_adapter *adapter, struct sta_info *psta) +{ + unsigned char raid; + switch (psta->wireless_mode) { + case WIRELESS_11B: + raid = RATR_INX_WIRELESS_B; + break; + case WIRELESS_11A: + case WIRELESS_11G: + raid = RATR_INX_WIRELESS_G; + break; + case WIRELESS_11BG: + raid = RATR_INX_WIRELESS_GB; + break; + case WIRELESS_11_24N: + case WIRELESS_11_5N: + raid = RATR_INX_WIRELESS_N; + break; + case WIRELESS_11A_5N: + case WIRELESS_11G_24N: + raid = RATR_INX_WIRELESS_NG; + break; + case WIRELESS_11BG_24N: + raid = RATR_INX_WIRELESS_NGB; + break; + default: + raid = RATR_INX_WIRELESS_GB; + break; + + } + return raid; + +} + +u8 networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 raid = RATEID_IDX_BGN_40M_1SS, cur_rf_type, rf_type, custom_rf_type; + s8 tx_nss; + + tx_nss = rtw_get_tx_nss(adapter, psta); + + switch (psta->wireless_mode) { + case WIRELESS_11B: + raid = RATEID_IDX_B; + break; + case WIRELESS_11A: + case WIRELESS_11G: + raid = RATEID_IDX_G; + break; + case WIRELESS_11BG: + raid = RATEID_IDX_BG; + break; + case WIRELESS_11_24N: + case WIRELESS_11_5N: + case WIRELESS_11A_5N: + case WIRELESS_11G_24N: + if (tx_nss == 1) + raid = RATEID_IDX_GN_N1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_GN_N2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_BGN_3SS; + else + RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); + break; + case WIRELESS_11B_24N: + case WIRELESS_11BG_24N: + if (psta->bw_mode == CHANNEL_WIDTH_20) { + if (tx_nss == 1) + raid = RATEID_IDX_BGN_20M_1SS_BN; + else if (tx_nss == 2) + raid = RATEID_IDX_BGN_20M_2SS_BN; + else if (tx_nss == 3) + raid = RATEID_IDX_BGN_3SS; + else + RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); + } else { + if (tx_nss == 1) + raid = RATEID_IDX_BGN_40M_1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_BGN_40M_2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_BGN_3SS; + else + RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); + } + break; + case WIRELESS_11_5AC: + if (tx_nss == 1) + raid = RATEID_IDX_VHT_1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_VHT_2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_VHT_3SS; + else + RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); + break; + case WIRELESS_11_24AC: + if (psta->bw_mode >= CHANNEL_WIDTH_80) { + if (tx_nss == 1) + raid = RATEID_IDX_VHT_1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_VHT_2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_VHT_3SS; + else + RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); + } else { + if (tx_nss == 1) + raid = RATEID_IDX_MIX1; + else if (tx_nss == 2) + raid = RATEID_IDX_MIX2; + else if (tx_nss == 3) + raid = RATEID_IDX_VHT_3SS; + else + RTW_INFO("tx_nss error!(tx_nss=%d)\n", tx_nss); + } + break; + default: + RTW_INFO("unexpected wireless mode!(psta->wireless_mode=%x)\n", psta->wireless_mode); + break; + + } + + /* RTW_INFO("psta->wireless_mode=%x, tx_nss=%d\n", psta->wireless_mode, tx_nss); */ + + return raid; + +} +#endif + +unsigned char ratetbl_val_2wifirate(unsigned char rate); +unsigned char ratetbl_val_2wifirate(unsigned char rate) +{ + unsigned char val = 0; + + switch (rate & 0x7f) { + case 0: + val = IEEE80211_CCK_RATE_1MB; + break; + + case 1: + val = IEEE80211_CCK_RATE_2MB; + break; + + case 2: + val = IEEE80211_CCK_RATE_5MB; + break; + + case 3: + val = IEEE80211_CCK_RATE_11MB; + break; + + case 4: + val = IEEE80211_OFDM_RATE_6MB; + break; + + case 5: + val = IEEE80211_OFDM_RATE_9MB; + break; + + case 6: + val = IEEE80211_OFDM_RATE_12MB; + break; + + case 7: + val = IEEE80211_OFDM_RATE_18MB; + break; + + case 8: + val = IEEE80211_OFDM_RATE_24MB; + break; + + case 9: + val = IEEE80211_OFDM_RATE_36MB; + break; + + case 10: + val = IEEE80211_OFDM_RATE_48MB; + break; + + case 11: + val = IEEE80211_OFDM_RATE_54MB; + break; + + } + + return val; + +} + +int is_basicrate(_adapter *padapter, unsigned char rate); +int is_basicrate(_adapter *padapter, unsigned char rate) +{ + int i; + unsigned char val; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + for (i = 0; i < NumRates; i++) { + val = pmlmeext->basicrate[i]; + + if ((val != 0xff) && (val != 0xfe)) { + if (rate == ratetbl_val_2wifirate(val)) + return _TRUE; + } + } + + return _FALSE; +} + +unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset); +unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset) +{ + int i; + unsigned char rate; + unsigned int len = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + for (i = 0; i < NumRates; i++) { + rate = pmlmeext->datarate[i]; + + if (rtw_get_oper_ch(padapter) > 14 && rate < _6M_RATE_) /*5G no support CCK rate*/ + continue; + + switch (rate) { + case 0xff: + return len; + + case 0xfe: + continue; + + default: + rate = ratetbl_val_2wifirate(rate); + + if (is_basicrate(padapter, rate) == _TRUE) + rate |= IEEE80211_BASIC_RATE_MASK; + + rateset[len] = rate; + len++; + break; + } + } + return len; +} + +void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len) +{ + unsigned char supportedrates[NumRates]; + + _rtw_memset(supportedrates, 0, NumRates); + *bssrate_len = ratetbl2rateset(padapter, supportedrates); + _rtw_memcpy(pbssrate, supportedrates, *bssrate_len); +} + +void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask) +{ + u8 mcs_rate_1r = (u8)(mask & 0xff); + u8 mcs_rate_2r = (u8)((mask >> 8) & 0xff); + u8 mcs_rate_3r = (u8)((mask >> 16) & 0xff); + u8 mcs_rate_4r = (u8)((mask >> 24) & 0xff); + + mcs_set[0] &= mcs_rate_1r; + mcs_set[1] &= mcs_rate_2r; + mcs_set[2] &= mcs_rate_3r; + mcs_set[3] &= mcs_rate_4r; +} + +void UpdateBrateTbl( + IN PADAPTER Adapter, + IN u8 *mBratesOS +) +{ + u8 i; + u8 rate; + + /* 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. */ + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + rate = mBratesOS[i] & 0x7f; + switch (rate) { + case IEEE80211_CCK_RATE_1MB: + case IEEE80211_CCK_RATE_2MB: + case IEEE80211_CCK_RATE_5MB: + case IEEE80211_CCK_RATE_11MB: + case IEEE80211_OFDM_RATE_6MB: + case IEEE80211_OFDM_RATE_12MB: + case IEEE80211_OFDM_RATE_24MB: + mBratesOS[i] |= IEEE80211_BASIC_RATE_MASK; + break; + } + } + +} + +void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen) +{ + u8 i; + u8 rate; + + for (i = 0; i < bssratelen; i++) { + rate = bssrateset[i] & 0x7f; + switch (rate) { + case IEEE80211_CCK_RATE_1MB: + case IEEE80211_CCK_RATE_2MB: + case IEEE80211_CCK_RATE_5MB: + case IEEE80211_CCK_RATE_11MB: + bssrateset[i] |= IEEE80211_BASIC_RATE_MASK; + break; + } + } + +} +void Set_MSR(_adapter *padapter, u8 type) +{ + rtw_hal_set_hwreg(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type)); +} + +inline u8 rtw_get_oper_ch(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->oper_channel; +} + +inline void rtw_set_oper_ch(_adapter *adapter, u8 ch) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + if (dvobj->oper_channel != ch) { + dvobj->on_oper_ch_time = rtw_get_current_time(); + + } + + dvobj->oper_channel = ch; +} + +inline u8 rtw_get_oper_bw(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->oper_bwmode; +} + +inline void rtw_set_oper_bw(_adapter *adapter, u8 bw) +{ + adapter_to_dvobj(adapter)->oper_bwmode = bw; +} + +inline u8 rtw_get_oper_choffset(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->oper_ch_offset; +} + +inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset) +{ + adapter_to_dvobj(adapter)->oper_ch_offset = offset; +} + +u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset) +{ + u8 valid = 1; + u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if (bw == CHANNEL_WIDTH_20) + goto exit; + + if (bw >= CHANNEL_WIDTH_80 && ch <= 14) { + valid = 0; + goto exit; + } + + if (ch >= 1 && ch <= 4) + offset = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (ch >= 5 && ch <= 9) { + if (*r_offset == HAL_PRIME_CHNL_OFFSET_LOWER || *r_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + offset = *r_offset; /* both lower and upper is valid, obey input value */ + else + offset = HAL_PRIME_CHNL_OFFSET_UPPER; /* default use upper */ + } else if (ch >= 10 && ch <= 13) + offset = HAL_PRIME_CHNL_OFFSET_UPPER; + else if (ch == 14) { + valid = 0; /* ch14 doesn't support 40MHz bandwidth */ + goto exit; + } else if (ch >= 36 && ch <= 177) { + switch (ch) { + case 36: + case 44: + case 52: + case 60: + case 100: + case 108: + case 116: + case 124: + case 132: + case 140: + case 149: + case 157: + case 165: + case 173: + offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case 40: + case 48: + case 56: + case 64: + case 104: + case 112: + case 120: + case 128: + case 136: + case 144: + case 153: + case 161: + case 169: + case 177: + offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + default: + valid = 0; + break; + } + } else + valid = 0; + +exit: + if (valid && r_offset) + *r_offset = offset; + return valid; +} + +u8 rtw_get_offset_by_ch(u8 channel) +{ + u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if (channel >= 1 && channel <= 4) + offset = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (channel >= 5 && channel <= 14) + offset = HAL_PRIME_CHNL_OFFSET_UPPER; + else { + switch (channel) { + case 36: + case 44: + case 52: + case 60: + case 100: + case 108: + case 116: + case 124: + case 132: + case 149: + case 157: + offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case 40: + case 48: + case 56: + case 64: + case 104: + case 112: + case 120: + case 128: + case 136: + case 153: + case 161: + offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + default: + offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + + } + + return offset; + +} + +u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset) +{ + u8 center_ch = channel; + + if (chnl_bw == CHANNEL_WIDTH_80) { + if (channel == 36 || channel == 40 || channel == 44 || channel == 48) + center_ch = 42; + else if (channel == 52 || channel == 56 || channel == 60 || channel == 64) + center_ch = 58; + else if (channel == 100 || channel == 104 || channel == 108 || channel == 112) + center_ch = 106; + else if (channel == 116 || channel == 120 || channel == 124 || channel == 128) + center_ch = 122; + else if (channel == 132 || channel == 136 || channel == 140 || channel == 144) + center_ch = 138; + else if (channel == 149 || channel == 153 || channel == 157 || channel == 161) + center_ch = 155; + else if (channel == 165 || channel == 169 || channel == 173 || channel == 177) + center_ch = 171; + else if (channel <= 14) + center_ch = 7; + } else if (chnl_bw == CHANNEL_WIDTH_40) { + if (chnl_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + center_ch = channel + 2; + else + center_ch = channel - 2; + } else if (chnl_bw == CHANNEL_WIDTH_20) + center_ch = channel; + else + rtw_warn_on(1); + + return center_ch; +} + +inline u32 rtw_get_on_cur_ch_time(_adapter *adapter) +{ + if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel) + return adapter_to_dvobj(adapter)->on_oper_ch_time; + else + return 0; +} + +void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode) +{ + u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (padapter->bNotifyChannelChange) + RTW_INFO("[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode); + + center_ch = rtw_get_center_ch(channel, bwmode, channel_offset); + + if (bwmode == CHANNEL_WIDTH_80) { + if (center_ch > channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (center_ch < channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + else + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + + + /* set Channel */ + /* saved channel/bw info */ + rtw_set_oper_ch(padapter, channel); + rtw_set_oper_bw(padapter, bwmode); + rtw_set_oper_choffset(padapter, channel_offset); + + rtw_hal_set_chnl_bw(padapter, center_ch, bwmode, channel_offset, chnl_offset80); /* set center channel */ + + + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); +} + +__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork) +{ + return pnetwork->MacAddress; +} + +u16 get_beacon_interval(WLAN_BSSID_EX *bss) +{ + unsigned short val; + _rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2); + + return le16_to_cpu(val); + +} + +int is_client_associated_to_ap(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + + if (!padapter) + return _FAIL; + + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE)) + return _TRUE; + else + return _FAIL; +} + +int is_client_associated_to_ibss(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) + return _TRUE; + else + return _FAIL; +} + +int is_IBSS_empty(_adapter *padapter) +{ + int i; + struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl; + + for (i = 0; i < macid_ctl->num; i++) { + if (!rtw_macid_is_used(macid_ctl, i)) + continue; + if (rtw_macid_get_if_g(macid_ctl, i) != padapter->iface_id) + continue; + if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i])) + continue; + if (GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]) == H2C_MSR_ROLE_ADHOC) + return _FAIL; + } + + return _TRUE; +} + +unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval) +{ + if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN) + return WAIT_FOR_BCN_TO_MIN; + else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX) + return WAIT_FOR_BCN_TO_MAX; + else + return bcn_interval << 2; +} + +void invalidate_cam_all(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + u8 val8 = 0; + + rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8); + + _enter_critical_bh(&cam_ctl->lock, &irqL); + rtw_sec_cam_map_clr_all(&cam_ctl->used); + _rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT); + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +void _clear_cam_entry(_adapter *padapter, u8 entry) +{ + unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + rtw_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key); +} + +inline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ +#ifdef CONFIG_WRITE_CACHE_ONLY + write_cam_cache(adapter, id , ctrl, mac, key); +#else + rtw_sec_write_cam_ent(adapter, id, ctrl, mac, key); + write_cam_cache(adapter, id , ctrl, mac, key); +#endif +} + +inline void clear_cam_entry(_adapter *adapter, u8 id) +{ + _clear_cam_entry(adapter, id); + clear_cam_cache(adapter, id); +} + +void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + dvobj->cam_cache[id].ctrl = ctrl; + _rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN); + _rtw_memcpy(dvobj->cam_cache[id].key, key, 16); + + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +void clear_cam_cache(_adapter *adapter, u8 id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + _rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent)); + + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +inline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + if (cam_ctl->sec_cap & cap) + return _TRUE; + return _FALSE; +} + +inline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + cam_ctl->flags |= flags; +} + +inline void rtw_camctl_set_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + _rtw_camctl_set_flags(adapter, flags); + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +inline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + cam_ctl->flags &= ~flags; +} + +inline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + if (cam_ctl->flags & flags) + return _TRUE; + return _FALSE; +} + +inline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + return map->m0 & BIT(id); + else + rtw_warn_on(1); + + return 0; +} + +inline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + map->m0 |= BIT(id); + else + rtw_warn_on(1); +} + +inline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + map->m0 &= ~BIT(id); + else + rtw_warn_on(1); +} + +inline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map) +{ + map->m0 = 0; +} + +bool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) +{ + bool ret = _FALSE; + + if (id >= cam_ctl->num) { + rtw_warn_on(1); + goto exit; + } + + ret = rtw_sec_camid_is_set(&cam_ctl->used, id); + +exit: + return ret; +} + +inline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) +{ + _irqL irqL; + bool ret; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + ret = _rtw_sec_camid_is_used(cam_ctl, id); + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return ret; +} + +inline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + bool ret = _FALSE; + + if (cam_id >= cam_ctl->num) { + rtw_warn_on(1); + goto exit; + } + + if (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE) + goto exit; + + ret = (dvobj->cam_cache[cam_id].ctrl & BIT6) ? _TRUE : _FALSE; + +exit: + return ret; +} + +inline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + bool ret; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + ret = _rtw_camid_is_gk(adapter, cam_id); + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return ret; +} + +bool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + bool ret = _FALSE; + + if (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE) + goto exit; + if (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl & 0x03)) + goto exit; + if (gk != -1 && (gk ? _TRUE : _FALSE) != _rtw_camid_is_gk(adapter, id)) + goto exit; + + ret = _TRUE; + +exit: + return ret; +} + +s16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; + s16 cam_id = -1; + + for (i = 0; i < cam_ctl->num; i++) { + if (cam_cache_chk(adapter, i, addr, kid, gk)) { + cam_id = i; + break; + } + } + + if (0) { + if (addr) + RTW_INFO(FUNC_ADPT_FMT" addr:"MAC_FMT" kid:%d, gk:%d, return cam_id:%d\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id); + else + RTW_INFO(FUNC_ADPT_FMT" addr:%p kid:%d, gk:%d, return cam_id:%d\n" + , FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id); + } + + return cam_id; +} + +s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + s16 cam_id = -1; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + cam_id = _rtw_camid_search(adapter, addr, kid, gk); + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return cam_id; +} + +s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, u8 *addr, s16 kid) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; + u8 start_id = 0; + s16 cam_id = -1; + + if (addr == NULL) { + RTW_PRINT(FUNC_ADPT_FMT" mac_address is NULL\n" + , FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + goto _exit; + } + + /* find cam entry which has the same addr, kid (, gk bit) */ + if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE) + i = _rtw_camid_search(adapter, addr, kid, sta ? _FALSE : _TRUE); + else + i = _rtw_camid_search(adapter, addr, kid, -1); + + if (i >= 0) { + cam_id = i; + goto _exit; + } + + for (i = 0; i < cam_ctl->num; i++) { + /* bypass default key which is allocated statically */ + if (((i + start_id) % cam_ctl->num) < 4) + continue; + if (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE) + break; + } + + if (i == cam_ctl->num) { + if (sta) + RTW_PRINT(FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u no room\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); + else + RTW_PRINT(FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u no room\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); + rtw_warn_on(1); + goto _exit; + } + + cam_id = ((i + start_id) % cam_ctl->num); + start_id = ((i + start_id + 1) % cam_ctl->num); + +_exit: + return cam_id; +} + +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) +{ + struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + s16 cam_id = -1; + + *used = _FALSE; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + if ((((mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE)) + && !sta) { + /* AP/Ad-hoc mode group key static alloction to default key by key ID on Non-concurrent*/ + if (kid > 3) { + RTW_PRINT(FUNC_ADPT_FMT" group key with invalid key id:%u\n" + , FUNC_ADPT_ARG(adapter), kid); + rtw_warn_on(1); + goto bitmap_handle; + } + cam_id = kid; + } else { + u8 *addr = sta ? sta->hwaddr : NULL; + + if (!sta) { + if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { + /* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */ + goto bitmap_handle; + } + addr = get_bssid(&adapter->mlmepriv);/*A2*/ + } + cam_id = rtw_get_camid(adapter, sta, addr, kid); + } + +bitmap_handle: + if (cam_id >= 0) { + *used = _rtw_sec_camid_is_used(cam_ctl, cam_id); + rtw_sec_cam_map_set(&cam_ctl->used, cam_id); + } + + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return cam_id; +} + +void rtw_camid_set(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + if (cam_id < cam_ctl->num) + rtw_sec_cam_map_set(&cam_ctl->used, cam_id); + + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +void rtw_camid_free(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + if (cam_id < cam_ctl->num) + rtw_sec_cam_map_clr(&cam_ctl->used, cam_id); + + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +/*Must pause TX/RX before use this API*/ +inline void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + struct sec_cam_ent cache_a, cache_b; + _irqL irqL; + bool cam_a_used, cam_b_used; + + if (1) + RTW_INFO(ADPT_FMT" - sec_cam %d,%d swap\n", ADPT_ARG(adapter), cam_id_a, cam_id_b); + + if (cam_id_a == cam_id_b) + return; + + + /*setp-1. backup org cam_info*/ + _enter_critical_bh(&cam_ctl->lock, &irqL); + + cam_a_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_a); + cam_b_used = _rtw_sec_camid_is_used(cam_ctl, cam_id_b); + + if (cam_a_used) + _rtw_memcpy(&cache_a, &dvobj->cam_cache[cam_id_a], sizeof(struct sec_cam_ent)); + + if (cam_b_used) + _rtw_memcpy(&cache_b, &dvobj->cam_cache[cam_id_b], sizeof(struct sec_cam_ent)); + + _exit_critical_bh(&cam_ctl->lock, &irqL); + + /*setp-2. clean cam_info*/ + if (cam_a_used) { + rtw_camid_free(adapter, cam_id_a); + clear_cam_entry(adapter, cam_id_a); + } + if (cam_b_used) { + rtw_camid_free(adapter, cam_id_b); + clear_cam_entry(adapter, cam_id_b); + } + + /*setp-3. set cam_info*/ + if (cam_a_used) { + write_cam(adapter, cam_id_b, cache_a.ctrl, cache_a.mac, cache_a.key); + rtw_camid_set(adapter, cam_id_b); + } + + if (cam_b_used) { + write_cam(adapter, cam_id_a, cache_b.ctrl, cache_b.mac, cache_b.key); + rtw_camid_set(adapter, cam_id_a); + } +} + +s16 rtw_get_empty_cam_entry(_adapter *adapter, u8 start_camid) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + int i; + s16 cam_id = -1; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + for (i = start_camid; i < cam_ctl->num; i++) { + if (_FALSE == _rtw_sec_camid_is_used(cam_ctl, i)) { + cam_id = i; + break; + } + } + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return cam_id; +} + +void flush_all_cam_entry(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv *psecpriv = &padapter->securitypriv; + + + invalidate_cam_all(padapter); + /* clear default key related key search setting */ + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8 *)_FALSE); +} + +void rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + + u8 *attr_content; + u32 attr_contentlen = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + return; + + RTW_INFO("[%s] Found WFD IE\n", tag); + attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen); + if (attr_content && attr_contentlen) { + wdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2); + RTW_INFO("[%s] Peer PORT NUM = %d\n", tag, wdinfo->wfd_info->peer_rtsp_ctrlport); + } +} + +void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag) +{ + u8 *wfd_ie; + u32 wfd_ielen; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + return; + + wfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen); + while (wfd_ie) { + rtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag); + wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen); + } +} + +int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + /* struct registry_priv *pregpriv = &padapter->registrypriv; */ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pmlmepriv->qospriv.qos_option == 0) { + pmlmeinfo->WMM_enable = 0; + return _FALSE; + } + + if (_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element))) + return _FALSE; + else + _rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); + pmlmeinfo->WMM_enable = 1; + return _TRUE; +} + +void WMMOnAssocRsp(_adapter *padapter) +{ + u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; + u8 acm_mask; + u16 TXOP; + u32 acParm, i; + u32 edca[4], inx[4]; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + + acm_mask = 0; + + if (is_supported_5g(pmlmeext->cur_wireless_mode) || + (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) + aSifsTime = 16; + else + aSifsTime = 10; + + if (pmlmeinfo->WMM_enable == 0) { + padapter->mlmepriv.acm_mask = 0; + + AIFS = aSifsTime + (2 * pmlmeinfo->slotTime); + + if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) { + ECWMin = 4; + ECWMax = 10; + } else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) { + ECWMin = 5; + ECWMax = 10; + } else { + ECWMin = 4; + ECWMax = 10; + } + + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + + ECWMin = 2; + ECWMax = 3; + TXOP = 0x2f; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + } else { + edca[0] = edca[1] = edca[2] = edca[3] = 0; + + for (i = 0; i < 4; i++) { + ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03; + ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01; + + /* AIFS = AIFSN * slot time + SIFS - r2t phy delay */ + AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime; + + ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f); + ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4; + TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit); + + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + + switch (ACI) { + case 0x0: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + acm_mask |= (ACM ? BIT(1) : 0); + edca[XMIT_BE_QUEUE] = acParm; + break; + + case 0x1: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + /* acm_mask |= (ACM? BIT(0):0); */ + edca[XMIT_BK_QUEUE] = acParm; + break; + + case 0x2: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + acm_mask |= (ACM ? BIT(2) : 0); + edca[XMIT_VI_QUEUE] = acParm; + break; + + case 0x3: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + acm_mask |= (ACM ? BIT(3) : 0); + edca[XMIT_VO_QUEUE] = acParm; + break; + } + + RTW_INFO("WMM(%x): %x, %x\n", ACI, ACM, acParm); + } + + if (padapter->registrypriv.acm_method == 1) + rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); + else + padapter->mlmepriv.acm_mask = acm_mask; + + inx[0] = 0; + inx[1] = 1; + inx[2] = 2; + inx[3] = 3; + + if (pregpriv->wifi_spec == 1) { + u32 j, tmp, change_inx = _FALSE; + + /* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */ + for (i = 0; i < 4; i++) { + for (j = i + 1; j < 4; j++) { + /* compare CW and AIFS */ + if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF)) + change_inx = _TRUE; + else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) { + /* compare TXOP */ + if ((edca[j] >> 16) > (edca[i] >> 16)) + change_inx = _TRUE; + } + + if (change_inx) { + tmp = edca[i]; + edca[i] = edca[j]; + edca[j] = tmp; + + tmp = inx[i]; + inx[i] = inx[j]; + inx[j] = tmp; + + change_inx = _FALSE; + } + } + } + } + + for (i = 0; i < 4; i++) { + pxmitpriv->wmm_para_seq[i] = inx[i]; + RTW_INFO("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); + } + } +} + +static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + unsigned char new_bwmode; + unsigned char new_ch_offset; + struct HT_info_element *pHT_info; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + u8 cbw40_enable = 0; + + if (!pIE) + return; + + if (phtpriv->ht_option == _FALSE) + return; + + if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80) + return; + + if (pIE->Length > sizeof(struct HT_info_element)) + return; + + pHT_info = (struct HT_info_element *)pIE->data; + + if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { + if (pmlmeext->cur_channel > 14) { + if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } else { + if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } + } + + if ((pHT_info->infos[0] & BIT(2)) && cbw40_enable) { + new_bwmode = CHANNEL_WIDTH_40; + + switch (pHT_info->infos[0] & 0x3) { + case 1: + new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + + case 3: + new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + + default: + new_bwmode = CHANNEL_WIDTH_20; + new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + } else { + new_bwmode = CHANNEL_WIDTH_20; + new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + if ((new_bwmode != pmlmeext->cur_bwmode || new_ch_offset != pmlmeext->cur_ch_offset) + && new_bwmode < pmlmeext->cur_bwmode + ) { + pmlmeinfo->bwmode_updated = _TRUE; + + pmlmeext->cur_bwmode = new_bwmode; + pmlmeext->cur_ch_offset = new_ch_offset; + + /* update HT info also */ + HT_info_handler(padapter, pIE); + } else + pmlmeinfo->bwmode_updated = _FALSE; + + if (_TRUE == pmlmeinfo->bwmode_updated) { + struct sta_info *psta; + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + + /* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */ + + /* update ap's stainfo */ + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) { + struct ht_priv *phtpriv_sta = &psta->htpriv; + + if (phtpriv_sta->ht_option) { + /* bwmode */ + psta->bw_mode = pmlmeext->cur_bwmode; + phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; + } else { + psta->bw_mode = CHANNEL_WIDTH_20; + phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); + } + + /* pmlmeinfo->bwmode_updated = _FALSE; */ /* bwmode_updated done, reset it! */ + } +} + +void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + unsigned int i; + u8 rf_type = RF_1T1R; + u8 max_AMPDU_len, min_MPDU_spacing; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, tx_nss = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + + if (pIE == NULL) + return; + + if (phtpriv->ht_option == _FALSE) + return; + + pmlmeinfo->HT_caps_enable = 1; + + for (i = 0; i < (pIE->Length); i++) { + if (i != 2) { + /* Commented by Albert 2010/07/12 */ + /* Got the endian issue here. */ + pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]); + } else { + /* AMPDU Parameters field */ + + /* Get MIN of MAX AMPDU Length Exp */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3)) + max_AMPDU_len = (pIE->data[i] & 0x3); + else + max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3); + + /* Get MAX of MIN MPDU Start Spacing */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c)) + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c); + else + min_MPDU_spacing = (pIE->data[i] & 0x1c); + + pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing; + } + } + + /* Commented by Albert 2010/07/12 */ + /* Have to handle the endian issue after copying. */ + /* HT_ext_caps didn't be used yet. */ + pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); + pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu(pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps); + + /* update the MCS set */ + for (i = 0; i < 16; i++) + pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + + switch (tx_nss) { + case 1: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); + break; + case 2: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); + break; + case 3: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); + break; + case 4: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_4R); + break; + default: + RTW_WARN("rf_type:%d or tx_nss:%u is not expected\n", rf_type, hal_spec->tx_nss_num); + } + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + /* Config STBC setting */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) { + SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX); + RTW_INFO("Enable HT Tx STBC !\n"); + } + phtpriv->stbc_cap = cur_stbc_cap; + + } else { + /*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/ + /* Config LDPC Coding Capability */ + if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) { + SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); + RTW_INFO("Enable HT Tx LDPC!\n"); + } + phtpriv->ldpc_cap = cur_ldpc_cap; + + /* Config STBC setting */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) { + SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); + RTW_INFO("Enable HT Tx STBC!\n"); + } + phtpriv->stbc_cap = cur_stbc_cap; + + } + +} + +void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + + if (pIE == NULL) + return; + + if (phtpriv->ht_option == _FALSE) + return; + + if (pIE->Length > sizeof(struct HT_info_element)) + return; + + pmlmeinfo->HT_info_enable = 1; + _rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length); + return; +} + +void HTOnAssocRsp(_adapter *padapter) +{ + unsigned char max_AMPDU_len; + unsigned char min_MPDU_spacing; + /* struct registry_priv *pregpriv = &padapter->registrypriv; */ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + RTW_INFO("%s\n", __FUNCTION__); + + if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) + pmlmeinfo->HT_enable = 1; + else { + pmlmeinfo->HT_enable = 0; + /* set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); */ + return; + } + + /* handle A-MPDU parameter field */ + /* + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k + AMPDU_para [4:2]:Min MPDU Start Spacing + */ + max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); +} + +void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pIE->Length > 1) + return; + + pmlmeinfo->ERP_enable = 1; + _rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length); +} + +void VCS_update(_adapter *padapter, struct sta_info *psta) +{ + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + switch (pregpriv->vrtl_carrier_sense) { /* 0:off 1:on 2:auto */ + case 0: /* off */ + psta->rtsen = 0; + psta->cts2self = 0; + break; + + case 1: /* on */ + if (pregpriv->vcs_type == 1) { /* 1:RTS/CTS 2:CTS to self */ + psta->rtsen = 1; + psta->cts2self = 0; + } else { + psta->rtsen = 0; + psta->cts2self = 1; + } + break; + + case 2: /* auto */ + default: + if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) + /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/ + ) { + if (pregpriv->vcs_type == 1) { + psta->rtsen = 1; + psta->cts2self = 0; + } else { + psta->rtsen = 0; + psta->cts2self = 1; + } + } else { + psta->rtsen = 0; + psta->cts2self = 0; + } + break; + } +} + +void update_ldpc_stbc_cap(struct sta_info *psta) +{ + + if (psta->vhtpriv.vht_option) { + if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX)) + psta->ldpc = 1; + + if (TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX)) + psta->stbc = 1; + } else + if (psta->htpriv.ht_option) { + if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX)) + psta->ldpc = 1; + + if (TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) + psta->stbc = 1; + } else { + psta->ldpc = 0; + psta->stbc = 0; + } + +} + +int check_ielen(u8 *start, uint len) +{ + int left = len; + u8 *pos = start; + int unknown = 0; + u8 id, elen; + + while (left >= 2) { + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) { + RTW_INFO("IEEE 802.11 element parse failed (id=%d elen=%d left=%lu)\n", + id, elen, (unsigned long) left); + return _FALSE; + } + if ((id == WLAN_EID_VENDOR_SPECIFIC) && (elen < 4)) + return _FALSE; + + left -= elen; + pos += elen; + } + if (left) + return _FALSE; + + return _TRUE; +} + +int validate_beacon_len(u8 *pframe, u32 len) +{ + u8 ie_offset = _BEACON_IE_OFFSET_ + sizeof(struct rtw_ieee80211_hdr_3addr); + + if (len < ie_offset) { + RTW_INFO("%s: incorrect beacon length(%d)\n", __func__, len); + return _FALSE; + } + + if (check_ielen(pframe + ie_offset, len - ie_offset) == _FALSE) + return _FALSE; + + return _TRUE; +} + +/* + * rtw_get_bcn_keys: get beacon keys from recv frame + * + * TODO: + * WLAN_EID_COUNTRY + * WLAN_EID_ERP_INFO + * WLAN_EID_CHANNEL_SWITCH + * WLAN_EID_PWR_CONSTRAINT + */ +int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, + struct beacon_keys *recv_beacon) +{ + int left; + u16 capability; + unsigned char *pos; + struct rtw_ieee802_11_elems elems; + struct rtw_ieee80211_ht_cap *pht_cap = NULL; + struct HT_info_element *pht_info = NULL; + + _rtw_memset(recv_beacon, 0, sizeof(*recv_beacon)); + + /* checking capabilities */ + capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 10)); + + /* checking IEs */ + left = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_; + pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_; + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) + return _FALSE; + + /* check bw and channel offset */ + if (elems.ht_capabilities) { + if (elems.ht_capabilities_len != sizeof(*pht_cap)) + return _FALSE; + + pht_cap = (struct rtw_ieee80211_ht_cap *) elems.ht_capabilities; + recv_beacon->ht_cap_info = pht_cap->cap_info; + } + + if (elems.ht_operation) { + if (elems.ht_operation_len != sizeof(*pht_info)) + return _FALSE; + + pht_info = (struct HT_info_element *) elems.ht_operation; + recv_beacon->ht_info_infos_0_sco = pht_info->infos[0] & 0x03; + } + + /* Checking for channel */ + if (elems.ds_params && elems.ds_params_len == sizeof(recv_beacon->bcn_channel)) + _rtw_memcpy(&recv_beacon->bcn_channel, elems.ds_params, + sizeof(recv_beacon->bcn_channel)); + else if (pht_info) + /* In 5G, some ap do not have DSSET IE checking HT info for channel */ + recv_beacon->bcn_channel = pht_info->primary_channel; + else { + /* we don't find channel IE, so don't check it */ + /* RTW_INFO("Oops: %s we don't find channel IE, so don't check it\n", __func__); */ + recv_beacon->bcn_channel = Adapter->mlmeextpriv.cur_channel; + } + + /* checking SSID */ + if (elems.ssid) { + if (elems.ssid_len > sizeof(recv_beacon->ssid)) + return _FALSE; + + _rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len); + recv_beacon->ssid_len = elems.ssid_len; + } else + ; /* means hidden ssid */ + + /* checking RSN first */ + if (elems.rsn_ie && elems.rsn_ie_len) { + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2; + rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2, + &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, + &recv_beacon->is_8021x); + } + /* checking WPA secon */ + else if (elems.wpa_ie && elems.wpa_ie_len) { + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA; + rtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2, + &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, + &recv_beacon->is_8021x); + } else if (capability & BIT(4)) + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP; + + return _TRUE; +} + +void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon) +{ + int i; + char *p; + u8 ssid[IW_ESSID_MAX_SIZE + 1]; + + _rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len); + ssid[recv_beacon->ssid_len] = '\0'; + + RTW_INFO("%s: ssid = %s\n", __func__, ssid); + RTW_INFO("%s: channel = %x\n", __func__, recv_beacon->bcn_channel); + RTW_INFO("%s: ht_cap = %x\n", __func__, recv_beacon->ht_cap_info); + RTW_INFO("%s: ht_info_infos_0_sco = %x\n", __func__, recv_beacon->ht_info_infos_0_sco); + RTW_INFO("%s: sec=%d, group = %x, pair = %x, 8021X = %x\n", __func__, + recv_beacon->encryp_protocol, recv_beacon->group_cipher, + recv_beacon->pairwise_cipher, recv_beacon->is_8021x); +} + +int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) +{ + unsigned int len; + u8 *pbssid = GetAddr3Ptr(pframe); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network); + struct beacon_keys recv_beacon; + + if (is_client_associated_to_ap(Adapter) == _FALSE) + return _TRUE; + + len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); + + if (len > MAX_IE_SZ) { + RTW_WARN("%s IE too long for survey event\n", __func__); + return _FAIL; + } + + if (_rtw_memcmp(cur_network->network.MacAddress, pbssid, 6) == _FALSE) { + RTW_WARN("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT, + MAC_ARG(pbssid), MAC_ARG(cur_network->network.MacAddress)); + return _TRUE; + } + + if (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE) + return _TRUE; /* parsing failed => broken IE */ + + /* don't care hidden ssid, use current beacon ssid directly */ + if (recv_beacon.ssid_len == 0) { + _rtw_memcpy(recv_beacon.ssid, pmlmepriv->cur_beacon_keys.ssid, + pmlmepriv->cur_beacon_keys.ssid_len); + recv_beacon.ssid_len = pmlmepriv->cur_beacon_keys.ssid_len; + } + + if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, sizeof(recv_beacon)) == _TRUE) + pmlmepriv->new_beacon_cnts = 0; + else if ((pmlmepriv->new_beacon_cnts == 0) || + _rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) { + RTW_DBG("%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe)); + + if (pmlmepriv->new_beacon_cnts == 0) { + RTW_ERR("%s: cur beacon key\n", __func__); + RTW_DBG_EXPR(rtw_dump_bcn_keys(&pmlmepriv->cur_beacon_keys)); + } + + RTW_DBG("%s: new beacon key\n", __func__); + RTW_DBG_EXPR(rtw_dump_bcn_keys(&recv_beacon)); + + memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 1; + } else { + RTW_DBG("%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe)); + pmlmepriv->new_beacon_cnts++; + } + + /* if counter >= max, it means beacon is changed really */ + if (pmlmepriv->new_beacon_cnts >= new_bcn_max) { + /* check bw mode change only? */ + pmlmepriv->cur_beacon_keys.ht_cap_info = recv_beacon.ht_cap_info; + pmlmepriv->cur_beacon_keys.ht_info_infos_0_sco = recv_beacon.ht_info_infos_0_sco; + if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, + sizeof(recv_beacon)) == _FALSE) { + /* beacon is changed, have to do disconnect/connect */ + RTW_WARN("%s: new beacon occur!!\n", __func__); + return _FAIL; + } + + RTW_INFO("%s bw mode change\n", __func__); + RTW_INFO("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, + cur_network->BcnInfo.ht_cap_info, + cur_network->BcnInfo.ht_info_infos_0); + + cur_network->BcnInfo.ht_cap_info = recv_beacon.ht_cap_info; + cur_network->BcnInfo.ht_info_infos_0 = + (cur_network->BcnInfo.ht_info_infos_0 & (~0x03)) | + recv_beacon.ht_info_infos_0_sco; + + RTW_INFO("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, + cur_network->BcnInfo.ht_cap_info, + cur_network->BcnInfo.ht_info_infos_0); + + memcpy(&pmlmepriv->cur_beacon_keys, &recv_beacon, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } + + return _SUCCESS; +} + +void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta) +{ + unsigned int i; + unsigned int len; + PNDIS_802_11_VARIABLE_IEs pIE; + + len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); + + for (i = 0; i < len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + /* to update WMM paramter set while receiving beacon */ + if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN) /* WMM */ + (WMM_param_handler(padapter, pIE)) ? report_wmm_edca_update(padapter) : 0; + + break; + + case _HT_EXTRA_INFO_IE_: /* HT info */ + /* HT_info_handler(padapter, pIE); */ + bwmode_update_check(padapter, pIE); + break; + case EID_OpModeNotification: + rtw_process_vht_op_mode_notify(padapter, pIE->data, psta); + break; + case _ERPINFO_IE_: + ERP_IE_handler(padapter, pIE); + VCS_update(padapter, psta); + break; + + default: + break; + } + + i += (pIE->Length + 2); + } +} + + +unsigned int is_ap_in_tkip(_adapter *padapter) +{ + u32 i; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + + if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) { + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4))) + return _TRUE; + break; + + case _RSN_IE_2_: + if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4)) + return _TRUE; + + default: + break; + } + + i += (pIE->Length + 2); + } + + return _FALSE; + } else + return _FALSE; + +} + +int wifirate2_ratetbl_inx(unsigned char rate); +int wifirate2_ratetbl_inx(unsigned char rate) +{ + int inx = 0; + rate = rate & 0x7f; + + switch (rate) { + case 54*2: + inx = 11; + break; + + case 48*2: + inx = 10; + break; + + case 36*2: + inx = 9; + break; + + case 24*2: + inx = 8; + break; + + case 18*2: + inx = 7; + break; + + case 12*2: + inx = 6; + break; + + case 9*2: + inx = 5; + break; + + case 6*2: + inx = 4; + break; + + case 11*2: + inx = 3; + break; + case 11: + inx = 2; + break; + + case 2*2: + inx = 1; + break; + + case 1*2: + inx = 0; + break; + + } + return inx; +} + +int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode) +{ + unsigned char bit_offset; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (!(pmlmeinfo->HT_enable)) + return _FAIL; + + bit_offset = (bwmode & CHANNEL_WIDTH_40) ? 6 : 5; + + if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset)) + return _SUCCESS; + else + return _FAIL; +} + +unsigned char get_highest_rate_idx(u32 mask) +{ + int i; + unsigned char rate_idx = 0; + + for (i = 31; i >= 0; i--) { + if (mask & BIT(i)) { + rate_idx = i; + break; + } + } + + return rate_idx; +} + +void Update_RA_Entry(_adapter *padapter, struct sta_info *psta) +{ + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); +} + +void set_sta_rate(_adapter *padapter, struct sta_info *psta) +{ + /* rate adaptive */ + rtw_hal_update_ra_mask(psta, psta->rssi_level, _TRUE); +} + +/* Update RRSR and Rate for USERATE */ +void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode) +{ + NDIS_802_11_RATES_EX supported_rates; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + /* Added by Albert 2011/03/22 */ + /* In the P2P mode, the driver should not support the b mode. */ + /* So, the Tx packet shouldn't use the CCK rate */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + _rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX); + + /* clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. */ + if (pmlmeext->cur_channel > 14) + wirelessmode &= ~(WIRELESS_11B); + + if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B)) + _rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4); + else if (wirelessmode & WIRELESS_11B) + _rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7); + else + _rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3); + + if (wirelessmode & WIRELESS_11B) + update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); + else + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); + + rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates); +} + +unsigned char check_assoc_AP(u8 *pframe, uint len) +{ + unsigned int i; + PNDIS_802_11_VARIABLE_IEs pIE; + + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); + + switch (pIE->ElementID) { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) { + RTW_INFO("link to Artheros AP\n"); + return HT_IOT_PEER_ATHEROS; + } else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3)) + || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3)) + || (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) { + RTW_INFO("link to Broadcom AP\n"); + return HT_IOT_PEER_BROADCOM; + } else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) { + RTW_INFO("link to Marvell AP\n"); + return HT_IOT_PEER_MARVELL; + } else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) { + RTW_INFO("link to Ralink AP\n"); + return HT_IOT_PEER_RALINK; + } else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) { + RTW_INFO("link to Cisco AP\n"); + return HT_IOT_PEER_CISCO; + } else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) { + u32 Vender = HT_IOT_PEER_REALTEK; + + if (pIE->Length >= 5) { + if (pIE->data[4] == 1) { + /* if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) */ + /* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; */ + + if (pIE->data[5] & RT_HT_CAP_USE_92SE) { + /* bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; */ + Vender = HT_IOT_PEER_REALTEK_92SE; + } + } + + if (pIE->data[5] & RT_HT_CAP_USE_SOFTAP) + Vender = HT_IOT_PEER_REALTEK_SOFTAP; + + if (pIE->data[4] == 2) { + if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_BCUT) { + Vender = HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP; + RTW_INFO("link to Realtek JAGUAR_BCUTAP\n"); + } + if (pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCUT) { + Vender = HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP; + RTW_INFO("link to Realtek JAGUAR_CCUTAP\n"); + } + } + } + + RTW_INFO("link to Realtek AP\n"); + return Vender; + } else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI, 3)) { + RTW_INFO("link to Airgo Cap\n"); + return HT_IOT_PEER_AIRGO; + } else + break; + + default: + break; + } + + i += (pIE->Length + 2); + } + + RTW_INFO("link to new AP\n"); + return HT_IOT_PEER_UNKNOWN; +} + +void update_capinfo(PADAPTER Adapter, u16 updateCap) +{ + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + BOOLEAN ShortPreamble; + + /* Check preamble mode, 2005.01.06, by rcnjko. */ + /* Mark to update preamble value forever, 2008.03.18 by lanhsin */ + /* if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) */ + { + + if (updateCap & cShortPreamble) { + /* Short Preamble */ + if (pmlmeinfo->preamble_mode != PREAMBLE_SHORT) { /* PREAMBLE_LONG or PREAMBLE_AUTO */ + ShortPreamble = _TRUE; + pmlmeinfo->preamble_mode = PREAMBLE_SHORT; + rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble); + } + } else { + /* Long Preamble */ + if (pmlmeinfo->preamble_mode != PREAMBLE_LONG) { /* PREAMBLE_SHORT or PREAMBLE_AUTO */ + ShortPreamble = _FALSE; + pmlmeinfo->preamble_mode = PREAMBLE_LONG; + rtw_hal_set_hwreg(Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble); + } + } + } + + if (updateCap & cIBSS) { + /* Filen: See 802.11-2007 p.91 */ + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + } else { + /* Filen: See 802.11-2007 p.90 */ + if (pmlmeext->cur_wireless_mode & (WIRELESS_11_24N | WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC)) + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + else if (pmlmeext->cur_wireless_mode & (WIRELESS_11G)) { + if ((updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) { + /* Short Slot Time */ + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + } else { + /* Long Slot Time */ + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + } + } else { + /* B Mode */ + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + } + } + + rtw_hal_set_hwreg(Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime); + +} + +/* +* set adapter.mlmeextpriv.mlmext_info.HT_enable +* set adapter.mlmeextpriv.cur_wireless_mode +* set SIFS register +* set mgmt tx rate +*/ +void update_wireless_mode(_adapter *padapter) +{ + int ratelen, network_type = 0; + u32 SIFS_Timer; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + unsigned char *rate = cur_network->SupportedRates; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + ratelen = rtw_get_rateset_len(cur_network->SupportedRates); + + if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) + pmlmeinfo->HT_enable = 1; + + if (pmlmeext->cur_channel > 14) { + if (pmlmeinfo->VHT_enable) + network_type = WIRELESS_11AC; + else if (pmlmeinfo->HT_enable) + network_type = WIRELESS_11_5N; + + network_type |= WIRELESS_11A; + } else { + if (pmlmeinfo->VHT_enable) + network_type = WIRELESS_11AC; + else if (pmlmeinfo->HT_enable) + network_type = WIRELESS_11_24N; + + if ((cckratesonly_included(rate, ratelen)) == _TRUE) + network_type |= WIRELESS_11B; + else if ((cckrates_included(rate, ratelen)) == _TRUE) + network_type |= WIRELESS_11BG; + else + network_type |= WIRELESS_11G; + } + + pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode; + /* RTW_INFO("network_type=%02x, padapter->registrypriv.wireless_mode=%02x\n", network_type, padapter->registrypriv.wireless_mode); */ + + SIFS_Timer = 0x0a0a0808; /* 0x0808->for CCK, 0x0a0a->for OFDM + * change this value if having IOT issues. */ + + rtw_hal_set_hwreg(padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer); + + rtw_hal_set_hwreg(padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode)); + + if ((pmlmeext->cur_wireless_mode & WIRELESS_11B) + && (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + ) + ) + update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); + else + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); +} + + +void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode) +{ + if (IsSupportedTxCCK(wireless_mode)) { + /* Only B, B/G, and B/G/N AP could use CCK rate */ + _rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4); + psta->bssratelen = 4; + } else { + _rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3); + psta->bssratelen = 3; + } +} + +int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num) +{ + u8 *ie; + unsigned int ie_len; + + if (!rate_set || !rate_num) + return _FALSE; + + *rate_num = 0; + + ie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len); + if (ie == NULL) + goto ext_rate; + + _rtw_memcpy(rate_set, ie + 2, ie_len); + *rate_num = ie_len; + +ext_rate: + ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len); + if (ie) { + _rtw_memcpy(rate_set + *rate_num, ie + 2, ie_len); + *rate_num += ie_len; + } + + if (*rate_num == 0) + return _FAIL; + + if (0) { + int i; + + for (i = 0; i < *rate_num; i++) + RTW_INFO("rate:0x%02x\n", *(rate_set + i)); + } + + return _SUCCESS; +} + +void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) +{ + struct sta_info *psta; + u16 tid, start_seq, param; + struct sta_priv *pstapriv = &padapter->stapriv; + struct ADDBA_request *preq = (struct ADDBA_request *)paddba_req; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 size, accept = _FALSE; + + psta = rtw_get_stainfo(pstapriv, addr); + if (!psta) + goto exit; + + start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4; + + param = le16_to_cpu(preq->BA_para_set); + tid = (param >> 2) & 0x0f; + + accept = rtw_rx_ampdu_is_accept(padapter); + if (padapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) + size = padapter->fix_rx_ampdu_size; + else { + size = rtw_rx_ampdu_size(padapter); + size = rtw_min(size, rx_ampdu_size_sta_limit(padapter, psta)); + } + + if (accept == _TRUE) + rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq); + else + rtw_addbarsp_cmd(padapter, addr, tid, 37, size, start_seq); /* reject ADDBA Req */ + +exit: + return; +} + +void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) +{ + u8 *pIE; + u32 *pbuf; + + pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pbuf = (u32 *)pIE; + + pmlmeext->TSFValue = le32_to_cpu(*(pbuf + 1)); + + pmlmeext->TSFValue = pmlmeext->TSFValue << 32; + + pmlmeext->TSFValue |= le32_to_cpu(*pbuf); +} + +void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext) +{ + rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, 0); +} + +void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) +{ + int i; + u8 *pIE; + u32 *pbuf; + u64 tsf = 0; + u32 delay_ms; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + pmlmeext->bcn_cnt++; + + pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pbuf = (u32 *)pIE; + + tsf = le32_to_cpu(*(pbuf + 1)); + tsf = tsf << 32; + tsf |= le32_to_cpu(*pbuf); + + /* RTW_INFO("%s(): tsf_upper= 0x%08x, tsf_lower=0x%08x\n", __func__, (u32)(tsf>>32), (u32)tsf); */ + + /* delay = (timestamp mod 1024*100)/1000 (unit: ms) */ + /* delay_ms = do_div(tsf, (pmlmeinfo->bcn_interval*1024))/1000; */ + delay_ms = rtw_modular64(tsf, (pmlmeinfo->bcn_interval * 1024)); + delay_ms = delay_ms / 1000; + + if (delay_ms >= 8) { + pmlmeext->bcn_delay_cnt[8]++; + /* pmlmeext->bcn_delay_ratio[8] = (pmlmeext->bcn_delay_cnt[8] * 100) /pmlmeext->bcn_cnt; */ + } else { + pmlmeext->bcn_delay_cnt[delay_ms]++; + /* pmlmeext->bcn_delay_ratio[delay_ms] = (pmlmeext->bcn_delay_cnt[delay_ms] * 100) /pmlmeext->bcn_cnt; */ + } + + /* + RTW_INFO("%s(): (a)bcn_cnt = %d\n", __func__, pmlmeext->bcn_cnt); + + for(i=0; i<9; i++) + { + RTW_INFO("%s():bcn_delay_cnt[%d]=%d, bcn_delay_ratio[%d]=%d\n", __func__, i, + pmlmeext->bcn_delay_cnt[i] , i, pmlmeext->bcn_delay_ratio[i]); + } + */ + + /* dump for adaptive_early_32k */ + if (pmlmeext->bcn_cnt > 100 && (pmlmeext->adaptive_tsf_done == _TRUE)) { + u8 ratio_20_delay, ratio_80_delay; + u8 DrvBcnEarly, DrvBcnTimeOut; + + ratio_20_delay = 0; + ratio_80_delay = 0; + DrvBcnEarly = 0xff; + DrvBcnTimeOut = 0xff; + + RTW_INFO("%s(): bcn_cnt = %d\n", __func__, pmlmeext->bcn_cnt); + + for (i = 0; i < 9; i++) { + pmlmeext->bcn_delay_ratio[i] = (pmlmeext->bcn_delay_cnt[i] * 100) / pmlmeext->bcn_cnt; + + /* RTW_INFO("%s():bcn_delay_cnt[%d]=%d, bcn_delay_ratio[%d]=%d\n", __func__, i, */ + /* pmlmeext->bcn_delay_cnt[i] , i, pmlmeext->bcn_delay_ratio[i]); */ + + ratio_20_delay += pmlmeext->bcn_delay_ratio[i]; + ratio_80_delay += pmlmeext->bcn_delay_ratio[i]; + + if (ratio_20_delay > 20 && DrvBcnEarly == 0xff) { + DrvBcnEarly = i; + /* RTW_INFO("%s(): DrvBcnEarly = %d\n", __func__, DrvBcnEarly); */ + } + + if (ratio_80_delay > 80 && DrvBcnTimeOut == 0xff) { + DrvBcnTimeOut = i; + /* RTW_INFO("%s(): DrvBcnTimeOut = %d\n", __func__, DrvBcnTimeOut); */ + } + + /* reset adaptive_early_32k cnt */ + pmlmeext->bcn_delay_cnt[i] = 0; + pmlmeext->bcn_delay_ratio[i] = 0; + } + + pmlmeext->DrvBcnEarly = DrvBcnEarly; + pmlmeext->DrvBcnTimeOut = DrvBcnTimeOut; + + pmlmeext->bcn_cnt = 0; + } + +} + +void beacon_timing_control(_adapter *padapter) +{ + rtw_hal_bcn_related_reg_setting(padapter); +} + +#define CONFIG_SHARED_BMC_MACID + +inline bool rtw_macid_is_set(struct macid_bmp *map, u8 id) +{ + if (id < 32) + return map->m0 & BIT(id); +#if (MACID_NUM_SW_LIMIT > 32) + else if (id < 64) + return map->m1 & BIT(id - 32); +#endif +#if (MACID_NUM_SW_LIMIT > 64) + else if (id < 96) + return map->m2 & BIT(id - 64); +#endif +#if (MACID_NUM_SW_LIMIT > 96) + else if (id < 128) + return map->m3 & BIT(id - 96); +#endif + else + rtw_warn_on(1); + + return 0; +} + +inline void rtw_macid_map_set(struct macid_bmp *map, u8 id) +{ + if (id < 32) + map->m0 |= BIT(id); +#if (MACID_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 |= BIT(id - 32); +#endif +#if (MACID_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 |= BIT(id - 64); +#endif +#if (MACID_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 |= BIT(id - 96); +#endif + else + rtw_warn_on(1); +} + +/*Record bc's mac-id and sec-cam-id*/ +inline void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + macid_ctl->iface_bmc[padapter->iface_id] = mac_id; +} +inline u8 rtw_iface_bcmc_id_get(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + return macid_ctl->iface_bmc[padapter->iface_id]; +} + +inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id) +{ + if (id < 32) + map->m0 &= ~BIT(id); +#if (MACID_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 &= ~BIT(id - 32); +#endif +#if (MACID_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 &= ~BIT(id - 64); +#endif +#if (MACID_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 &= ~BIT(id - 96); +#endif + else + rtw_warn_on(1); +} + +inline bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id) +{ + return rtw_macid_is_set(&macid_ctl->used, id); +} + +inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id) +{ + return rtw_macid_is_set(&macid_ctl->bmc, id); +} + +inline s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id) +{ + int i; + + if (rtw_macid_is_bmc(macid_ctl, id)) { + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) + if (macid_ctl->iface_bmc[i] == id) + return i; + return -1; + } + + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) { + if (rtw_macid_is_set(&macid_ctl->if_g[i], id)) + return i; + } + return -1; +} + +void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) +{ + int i; + _irqL irqL; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct macid_bmp *used_map = &macid_ctl->used; + /* static u8 last_id = 0; for testing */ + u8 last_id = 0; + u8 is_bc_sta = _FALSE; + + if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) { + psta->mac_id = macid_ctl->num; + return; + } + + if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) { + is_bc_sta = _TRUE; + rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/ + } + + if (is_bc_sta + ) { + /* use shared broadcast & multicast macid 1 for all ifaces which configure to station mode*/ + _enter_critical_bh(&macid_ctl->lock, &irqL); + rtw_macid_map_set(used_map, 1); + rtw_macid_map_set(&macid_ctl->bmc, 1); + rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], 1); + macid_ctl->sta[1] = psta; + /* TODO ch_g? */ + _exit_critical_bh(&macid_ctl->lock, &irqL); + i = 1; + goto assigned; + } + + _enter_critical_bh(&macid_ctl->lock, &irqL); + + for (i = last_id; i < macid_ctl->num; i++) { + if (i == 1) + continue; + + if (is_bc_sta) {/*for SoftAP's Broadcast sta-info*/ + /*TODO:non-security AP may allociated macid = 1*/ + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + + if ((!rtw_macid_is_used(macid_ctl, i)) && (!rtw_sec_camid_is_used(cam_ctl, i))) + break; + } else { + if (!rtw_macid_is_used(macid_ctl, i)) + break; + } + } + + if (i < macid_ctl->num) { + + rtw_macid_map_set(used_map, i); + + if (is_bc_sta) { + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + + rtw_macid_map_set(&macid_ctl->bmc, i); + rtw_iface_bcmc_id_set(padapter, i); + rtw_sec_cam_map_set(&cam_ctl->used, i); + } + + rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], i); + macid_ctl->sta[i] = psta; + + /* TODO ch_g? */ + + last_id++; + last_id %= macid_ctl->num; + } + + _exit_critical_bh(&macid_ctl->lock, &irqL); + + if (i >= macid_ctl->num) { + psta->mac_id = macid_ctl->num; + RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" no available macid\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr)); + rtw_warn_on(1); + goto exit; + } else + goto assigned; + +assigned: + psta->mac_id = i; + RTW_INFO(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); + +exit: + return; +} + +void rtw_release_macid(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 is_bc_sta = _FALSE; + + if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) + return; + + if (_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) + is_bc_sta = _TRUE; + + if (is_bc_sta + ) + return; + + if (psta->mac_id == 1) { + RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" with macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) || check_fwstate(&padapter->mlmepriv, WIFI_NULL_STATE)) + rtw_warn_on(1); + return; + } + + _enter_critical_bh(&macid_ctl->lock, &irqL); + + if (psta->mac_id < macid_ctl->num) { + int i; + + if (!rtw_macid_is_used(macid_ctl, psta->mac_id)) { + RTW_ERR(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u not used\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id + 1, MAC_ARG(psta->hwaddr), psta->mac_id); + rtw_warn_on(1); + } + + rtw_macid_map_clr(&macid_ctl->used, psta->mac_id); + rtw_macid_map_clr(&macid_ctl->bmc, psta->mac_id); + + if (is_bc_sta) { + struct cam_ctl_t *cam_ctl = dvobj_to_sec_camctl(dvobj); + u8 id = rtw_iface_bcmc_id_get(padapter); + + if ((id != INVALID_SEC_MAC_CAM_ID) && (id < cam_ctl->num)) + rtw_sec_cam_map_clr(&cam_ctl->used, id); + + rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); + } + + for (i = 0; i < CONFIG_IFACE_NUMBER; i++) + rtw_macid_map_clr(&macid_ctl->if_g[i], psta->mac_id); + for (i = 0; i < 2; i++) + rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->mac_id); + macid_ctl->sta[psta->mac_id] = NULL; + } + + _exit_critical_bh(&macid_ctl->lock, &irqL); + + psta->mac_id = macid_ctl->num; +} + +inline void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->h2c_msr[id] = h2c_msr; + if (0) + RTW_INFO("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id])); +} + +inline void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->bw[id] = bw; + if (0) + RTW_INFO("macid:%u, bw:%s\n", id, ch_width_str(macid_ctl->bw[id])); +} + +inline void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->vht_en[id] = en; + if (0) + RTW_INFO("macid:%u, vht_en:%u\n", id, macid_ctl->vht_en[id]); +} + +inline void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->rate_bmp0[id] = bmp; + if (0) + RTW_INFO("macid:%u, rate_bmp0:0x%08X\n", id, macid_ctl->rate_bmp0[id]); +} + +inline void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->rate_bmp1[id] = bmp; + if (0) + RTW_INFO("macid:%u, rate_bmp1:0x%08X\n", id, macid_ctl->rate_bmp1[id]); +} + +inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl) +{ + _rtw_spinlock_init(&macid_ctl->lock); +} + +inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl) +{ + _rtw_spinlock_free(&macid_ctl->lock); +} + +_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj) +{ + _adapter *port0_iface = NULL; + int i; + for (i = 0; i < dvobj->iface_nums; i++) { + if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) + break; + } + + if (i < 0 || i >= dvobj->iface_nums) + rtw_warn_on(1); + else + port0_iface = dvobj->padapters[i]; + + return port0_iface; +} + diff --git a/drivers/staging/rtl8821ce/core/rtw_xmit.c b/drivers/staging/rtl8821ce/core/rtw_xmit.c new file mode 100644 index 000000000000..f49140f1c22c --- /dev/null +++ b/drivers/staging/rtl8821ce/core/rtw_xmit.c @@ -0,0 +1,3570 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_XMIT_C_ + +#include <drv_types.h> +#include <hal_data.h> + +static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 }; +static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; + +static void _init_txservq(struct tx_servq *ptxservq) +{ + _rtw_init_listhead(&ptxservq->tx_pending); + _rtw_init_queue(&ptxservq->sta_pending); + ptxservq->qcnt = 0; +} + +void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) +{ + + _rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof(struct sta_xmit_priv)); + + _rtw_spinlock_init(&psta_xmitpriv->lock); + + /* for(i = 0 ; i < MAX_NUMBLKS; i++) */ + /* _init_txservq(&(psta_xmitpriv->blk_q[i])); */ + + _init_txservq(&psta_xmitpriv->be_q); + _init_txservq(&psta_xmitpriv->bk_q); + _init_txservq(&psta_xmitpriv->vi_q); + _init_txservq(&psta_xmitpriv->vo_q); + _rtw_init_listhead(&psta_xmitpriv->legacy_dz); + _rtw_init_listhead(&psta_xmitpriv->apsd); + +} + +void rtw_init_xmit_block(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + _rtw_spinlock_init(&dvobj->xmit_block_lock); + dvobj->xmit_block = XMIT_BLOCK_NONE; + +} +void rtw_free_xmit_block(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + _rtw_spinlock_free(&dvobj->xmit_block_lock); +} + +s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) +{ + int i; + struct xmit_buf *pxmitbuf; + struct xmit_frame *pxframe; + sint res = _SUCCESS; + + /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ + /* _rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); */ + + _rtw_spinlock_init(&pxmitpriv->lock); + _rtw_spinlock_init(&pxmitpriv->lock_sctx); + _rtw_init_sema(&pxmitpriv->xmit_sema, 0); + /*_rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0);*/ + _rtw_init_completion(&pxmitpriv->xmitthread_comp); + + /* + Please insert all the queue initializaiton using _rtw_init_queue below + */ + + pxmitpriv->adapter = padapter; + + /* for(i = 0 ; i < MAX_NUMBLKS; i++) */ + /* _rtw_init_queue(&pxmitpriv->blk_strms[i]); */ + + _rtw_init_queue(&pxmitpriv->be_pending); + _rtw_init_queue(&pxmitpriv->bk_pending); + _rtw_init_queue(&pxmitpriv->vi_pending); + _rtw_init_queue(&pxmitpriv->vo_pending); + _rtw_init_queue(&pxmitpriv->bm_pending); + + /* _rtw_init_queue(&pxmitpriv->legacy_dz_queue); */ + /* _rtw_init_queue(&pxmitpriv->apsd_queue); */ + + _rtw_init_queue(&pxmitpriv->free_xmit_queue); + + /* + Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME, + and initialize free_xmit_frame below. + Please also apply free_txobj to link_up all the xmit_frames... + */ + + pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4); + + if (pxmitpriv->pallocated_frame_buf == NULL) { + pxmitpriv->pxmit_frame_buf = NULL; + res = _FAIL; + goto exit; + } + pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4); + /* pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - */ + /* ((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); */ + + pxframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf; + + for (i = 0; i < NR_XMITFRAME; i++) { + _rtw_init_listhead(&(pxframe->list)); + + pxframe->padapter = padapter; + pxframe->frame_tag = NULL_FRAMETAG; + + pxframe->pkt = NULL; + + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue)); + + pxframe++; + } + + pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME; + + pxmitpriv->frag_len = MAX_FRAG_THRESHOLD; + + /* init xmit_buf */ + _rtw_init_queue(&pxmitpriv->free_xmitbuf_queue); + _rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue); + + pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4); + + if (pxmitpriv->pallocated_xmitbuf == NULL) { + res = _FAIL; + goto exit; + } + + pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4); + /* pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - */ + /* ((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); */ + + pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; + + for (i = 0; i < NR_XMITBUFF; i++) { + _rtw_init_listhead(&pxmitbuf->list); + + pxmitbuf->priv_data = NULL; + pxmitbuf->padapter = padapter; + pxmitbuf->buf_tag = XMITBUF_DATA; + + /* Tx buf allocation may fail sometimes, so sleep and retry. */ + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + if (res == _FAIL) { + rtw_msleep_os(10); + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + if (res == _FAIL) + goto exit; + } + + pxmitbuf->flags = XMIT_VO_QUEUE; + + rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue)); + + pxmitbuf++; + + } + + pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF; + + /* init xframe_ext queue, the same count as extbuf */ + _rtw_init_queue(&pxmitpriv->free_xframe_ext_queue); + + pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4); + + if (pxmitpriv->xframe_ext_alloc_addr == NULL) { + pxmitpriv->xframe_ext = NULL; + res = _FAIL; + goto exit; + } + pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4); + pxframe = (struct xmit_frame *)pxmitpriv->xframe_ext; + + for (i = 0; i < NR_XMIT_EXTBUFF; i++) { + _rtw_init_listhead(&(pxframe->list)); + + pxframe->padapter = padapter; + pxframe->frame_tag = NULL_FRAMETAG; + + pxframe->pkt = NULL; + + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + pxframe->ext_tag = 1; + + rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue)); + + pxframe++; + } + pxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF; + + /* Init xmit extension buff */ + _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); + + pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); + + if (pxmitpriv->pallocated_xmit_extbuf == NULL) { + res = _FAIL; + goto exit; + } + + pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4); + + pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; + + for (i = 0; i < NR_XMIT_EXTBUFF; i++) { + _rtw_init_listhead(&pxmitbuf->list); + + pxmitbuf->priv_data = NULL; + pxmitbuf->padapter = padapter; + pxmitbuf->buf_tag = XMITBUF_MGNT; + + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE); + if (res == _FAIL) { + res = _FAIL; + goto exit; + } + + rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue)); + pxmitbuf++; + + } + + pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF; + + for (i = 0; i < CMDBUF_MAX; i++) { + pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i]; + if (pxmitbuf) { + _rtw_init_listhead(&pxmitbuf->list); + + pxmitbuf->priv_data = NULL; + pxmitbuf->padapter = padapter; + pxmitbuf->buf_tag = XMITBUF_CMD; + + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE); + if (res == _FAIL) { + res = _FAIL; + goto exit; + } + + pxmitbuf->alloc_sz = MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ; + } + } + + rtw_alloc_hwxmits(padapter); + rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); + + for (i = 0; i < 4; i++) + pxmitpriv->wmm_para_seq[i] = i; + + pxmitpriv->ack_tx = _FALSE; + _rtw_mutex_init(&pxmitpriv->ack_tx_mutex); + rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0); + + rtw_init_xmit_block(padapter); + rtw_hal_init_xmit_priv(padapter); + +exit: + + return res; +} + +void rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv); +void rtw_mfree_xmit_priv_lock(struct xmit_priv *pxmitpriv) +{ + _rtw_spinlock_free(&pxmitpriv->lock); + _rtw_free_sema(&pxmitpriv->xmit_sema); + /*_rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema);*/ + + _rtw_spinlock_free(&pxmitpriv->be_pending.lock); + _rtw_spinlock_free(&pxmitpriv->bk_pending.lock); + _rtw_spinlock_free(&pxmitpriv->vi_pending.lock); + _rtw_spinlock_free(&pxmitpriv->vo_pending.lock); + _rtw_spinlock_free(&pxmitpriv->bm_pending.lock); + + /* _rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); */ + /* _rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); */ + + _rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock); + _rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock); + _rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock); +} + +void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv) +{ + int i; + _adapter *padapter = pxmitpriv->adapter; + struct xmit_frame *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf; + struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; + + rtw_hal_free_xmit_priv(padapter); + + rtw_mfree_xmit_priv_lock(pxmitpriv); + + if (pxmitpriv->pxmit_frame_buf == NULL) + goto out; + + for (i = 0; i < NR_XMITFRAME; i++) { + rtw_os_xmit_complete(padapter, pxmitframe); + + pxmitframe++; + } + + for (i = 0; i < NR_XMITBUFF; i++) { + rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + + pxmitbuf++; + } + + if (pxmitpriv->pallocated_frame_buf) + rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4); + + if (pxmitpriv->pallocated_xmitbuf) + rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4); + + /* free xframe_ext queue, the same count as extbuf */ + if ((pxmitframe = (struct xmit_frame *)pxmitpriv->xframe_ext)) { + for (i = 0; i < NR_XMIT_EXTBUFF; i++) { + rtw_os_xmit_complete(padapter, pxmitframe); + pxmitframe++; + } + } + if (pxmitpriv->xframe_ext_alloc_addr) + rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4); + _rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock); + + /* free xmit extension buff */ + _rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock); + + pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; + for (i = 0; i < NR_XMIT_EXTBUFF; i++) { + rtw_os_xmit_resource_free(padapter, pxmitbuf, (MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + + pxmitbuf++; + } + + if (pxmitpriv->pallocated_xmit_extbuf) + rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); + + for (i = 0; i < CMDBUF_MAX; i++) { + pxmitbuf = &pxmitpriv->pcmd_xmitbuf[i]; + if (pxmitbuf != NULL) + rtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ + XMITBUF_ALIGN_SZ , _TRUE); + } + + rtw_free_hwxmits(padapter); + + _rtw_mutex_free(&pxmitpriv->ack_tx_mutex); + rtw_free_xmit_block(padapter); +out: + return; +} + +u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta) +{ + u8 bw; + + bw = sta->bw_mode; + if (MLME_STATE(adapter) & WIFI_ASOC_STATE) { + if (adapter->mlmeextpriv.cur_channel <= 14) + bw = rtw_min(bw, ADAPTER_TX_BW_2G(adapter)); + else + bw = rtw_min(bw, ADAPTER_TX_BW_5G(adapter)); + } + + return bw; +} + +void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + u8 fix_bw = 0xFF; + u16 bmp_cck_ofdm = 0; + u32 bmp_ht = 0; + u32 bmp_vht = 0; + int i; + + if (adapter->fix_rate != 0xFF && adapter->fix_bw != 0xFF) + fix_bw = adapter->fix_bw; + + for (i = 0; i < macid_ctl->num; i++) { + if (!rtw_macid_is_used(macid_ctl, i)) + continue; + if (rtw_macid_get_if_g(macid_ctl, i) != adapter->iface_id) + continue; + + if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ + bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF; + + /* bypass mismatch bandwidth for HT, VHT */ + if ((fix_bw != 0xFF && fix_bw != bw) || (fix_bw == 0xFF && macid_ctl->bw[i] != bw)) + continue; + + if (macid_ctl->vht_en[i]) + bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + else + bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + } + + if (r_bmp_cck_ofdm) + *r_bmp_cck_ofdm = bmp_cck_ofdm; + if (r_bmp_ht) + *r_bmp_ht = bmp_ht; + if (r_bmp_vht) + *r_bmp_vht = bmp_vht; +} + +void rtw_get_shared_macid_tx_rate_bmp_by_bw(struct dvobj_priv *dvobj, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht) +{ + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u16 bmp_cck_ofdm = 0; + u32 bmp_ht = 0; + u32 bmp_vht = 0; + int i; + + for (i = 0; i < macid_ctl->num; i++) { + if (!rtw_macid_is_used(macid_ctl, i)) + continue; + if (rtw_macid_get_if_g(macid_ctl, i) != -1) + continue; + + if (bw == CHANNEL_WIDTH_20) /* CCK, OFDM always 20MHz */ + bmp_cck_ofdm |= macid_ctl->rate_bmp0[i] & 0x00000FFF; + + /* bypass mismatch bandwidth for HT, VHT */ + if (macid_ctl->bw[i] != bw) + continue; + + if (macid_ctl->vht_en[i]) + bmp_vht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + else + bmp_ht |= (macid_ctl->rate_bmp0[i] >> 12) | (macid_ctl->rate_bmp1[i] << 20); + } + + if (r_bmp_cck_ofdm) + *r_bmp_cck_ofdm = bmp_cck_ofdm; + if (r_bmp_ht) + *r_bmp_ht = bmp_ht; + if (r_bmp_vht) + *r_bmp_vht = bmp_vht; +} + +void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + _adapter *adapter = dvobj_get_primary_adapter(dvobj); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bw; + u16 bmp_cck_ofdm, tmp_cck_ofdm; + u32 bmp_ht, tmp_ht, ori_bmp_ht[2]; + u8 ori_highest_ht_rate_bw_bmp; + u32 bmp_vht, tmp_vht, ori_bmp_vht[4]; + u8 ori_highest_vht_rate_bw_bmp; + int i; + + /* backup the original ht & vht highest bw bmp */ + ori_highest_ht_rate_bw_bmp = rf_ctl->highest_ht_rate_bw_bmp; + ori_highest_vht_rate_bw_bmp = rf_ctl->highest_vht_rate_bw_bmp; + + for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) { + /* backup the original ht & vht bmp */ + if (bw <= CHANNEL_WIDTH_40) + ori_bmp_ht[bw] = rf_ctl->rate_bmp_ht_by_bw[bw]; + if (bw <= CHANNEL_WIDTH_160) + ori_bmp_vht[bw] = rf_ctl->rate_bmp_vht_by_bw[bw]; + + bmp_cck_ofdm = bmp_ht = bmp_vht = 0; + if (hal_is_bw_support(dvobj_get_primary_adapter(dvobj), bw)) { + for (i = 0; i < dvobj->iface_nums; i++) { + if (!dvobj->padapters[i]) + continue; + rtw_get_adapter_tx_rate_bmp_by_bw(dvobj->padapters[i], bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht); + bmp_cck_ofdm |= tmp_cck_ofdm; + bmp_ht |= tmp_ht; + bmp_vht |= tmp_vht; + } + rtw_get_shared_macid_tx_rate_bmp_by_bw(dvobj, bw, &tmp_cck_ofdm, &tmp_ht, &tmp_vht); + bmp_cck_ofdm |= tmp_cck_ofdm; + bmp_ht |= tmp_ht; + bmp_vht |= tmp_vht; + } + if (bw == CHANNEL_WIDTH_20) + rf_ctl->rate_bmp_cck_ofdm = bmp_cck_ofdm; + if (bw <= CHANNEL_WIDTH_40) + rf_ctl->rate_bmp_ht_by_bw[bw] = bmp_ht; + if (bw <= CHANNEL_WIDTH_160) + rf_ctl->rate_bmp_vht_by_bw[bw] = bmp_vht; + } + +#ifndef DBG_HIGHEST_RATE_BMP_BW_CHANGE +#define DBG_HIGHEST_RATE_BMP_BW_CHANGE 0 +#endif + + { + u8 highest_rate_bw; + u8 highest_rate_bw_bmp; + u8 update_ht_rs = _FALSE; + u8 update_vht_rs = _FALSE; + + highest_rate_bw_bmp = BW_CAP_20M; + highest_rate_bw = CHANNEL_WIDTH_20; + for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_40; bw++) { + if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_ht_by_bw[bw]) { + highest_rate_bw_bmp = ch_width_to_bw_cap(bw); + highest_rate_bw = bw; + } else if (rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_ht_by_bw[bw]) + highest_rate_bw_bmp |= ch_width_to_bw_cap(bw); + } + rf_ctl->highest_ht_rate_bw_bmp = highest_rate_bw_bmp; + + if (ori_highest_ht_rate_bw_bmp != rf_ctl->highest_ht_rate_bw_bmp + || largest_bit(ori_bmp_ht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]) + ) { + if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) { + RTW_INFO("highest_ht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_ht_rate_bw_bmp, rf_ctl->highest_ht_rate_bw_bmp); + RTW_INFO("rate_bmp_ht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_ht[highest_rate_bw], rf_ctl->rate_bmp_ht_by_bw[highest_rate_bw]); + } + update_ht_rs = _TRUE; + } + + highest_rate_bw_bmp = BW_CAP_20M; + highest_rate_bw = CHANNEL_WIDTH_20; + for (bw = CHANNEL_WIDTH_20; bw <= CHANNEL_WIDTH_160; bw++) { + if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] < rf_ctl->rate_bmp_vht_by_bw[bw]) { + highest_rate_bw_bmp = ch_width_to_bw_cap(bw); + highest_rate_bw = bw; + } else if (rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw] == rf_ctl->rate_bmp_vht_by_bw[bw]) + highest_rate_bw_bmp |= ch_width_to_bw_cap(bw); + } + rf_ctl->highest_vht_rate_bw_bmp = highest_rate_bw_bmp; + + if (ori_highest_vht_rate_bw_bmp != rf_ctl->highest_vht_rate_bw_bmp + || largest_bit(ori_bmp_vht[highest_rate_bw]) != largest_bit(rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]) + ) { + if (DBG_HIGHEST_RATE_BMP_BW_CHANGE) { + RTW_INFO("highest_vht_rate_bw_bmp:0x%02x=>0x%02x\n", ori_highest_vht_rate_bw_bmp, rf_ctl->highest_vht_rate_bw_bmp); + RTW_INFO("rate_bmp_vht_by_bw[%u]:0x%08x=>0x%08x\n", highest_rate_bw, ori_bmp_vht[highest_rate_bw], rf_ctl->rate_bmp_vht_by_bw[highest_rate_bw]); + } + update_vht_rs = _TRUE; + } + + /* TODO: per rfpath and rate section handling? */ + if (update_ht_rs == _TRUE || update_vht_rs == _TRUE) + rtw_hal_set_tx_power_level(dvobj_get_primary_adapter(dvobj), hal_data->current_channel); + } +} + +inline u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + + return rf_ctl->rate_bmp_cck_ofdm; +} + +inline u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + + return rf_ctl->rate_bmp_ht_by_bw[bw]; +} + +inline u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + + return rf_ctl->rate_bmp_vht_by_bw[bw]; +} + +u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + u8 bw; + u8 bw_bmp = 0; + u32 rate_bmp; + + if (!IS_HT_RATE(rate)) { + rtw_warn_on(1); + goto exit; + } + + rate_bmp = 1 << (rate - MGN_MCS0); + + if (max_bw > CHANNEL_WIDTH_40) + max_bw = CHANNEL_WIDTH_40; + + for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) { + /* RA may use lower rate for retry */ + if (rf_ctl->rate_bmp_ht_by_bw[bw] >= rate_bmp) + bw_bmp |= ch_width_to_bw_cap(bw); + } + +exit: + return bw_bmp; +} + +u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw) +{ + struct rf_ctl_t *rf_ctl = dvobj_to_rfctl(dvobj); + u8 bw; + u8 bw_bmp = 0; + u32 rate_bmp; + + if (!IS_VHT_RATE(rate)) { + rtw_warn_on(1); + goto exit; + } + + rate_bmp = 1 << (rate - MGN_VHT1SS_MCS0); + + if (max_bw > CHANNEL_WIDTH_160) + max_bw = CHANNEL_WIDTH_160; + + for (bw = CHANNEL_WIDTH_20; bw <= max_bw; bw++) { + /* RA may use lower rate for retry */ + if (rf_ctl->rate_bmp_vht_by_bw[bw] >= rate_bmp) + bw_bmp |= ch_width_to_bw_cap(bw); + } + +exit: + return bw_bmp; +} + +u8 query_ra_short_GI(struct sta_info *psta, u8 bw) +{ + u8 sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE; + + if (psta->vhtpriv.vht_option) + sgi_80m = psta->vhtpriv.sgi_80m; + sgi_20m = psta->htpriv.sgi_20m; + sgi_40m = psta->htpriv.sgi_40m; + + switch (bw) { + case CHANNEL_WIDTH_80: + sgi = sgi_80m; + break; + case CHANNEL_WIDTH_40: + sgi = sgi_40m; + break; + case CHANNEL_WIDTH_20: + default: + sgi = sgi_20m; + break; + } + + return sgi; +} + +static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + u32 sz; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + /* struct sta_info *psta = pattrib->psta; */ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* + if(pattrib->psta) + { + psta = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); + } + + if(psta==NULL) + { + RTW_INFO("%s, psta==NUL\n", __func__); + return; + } + + if(!(psta->state &_FW_LINKED)) + { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return; + } + */ + + if (pattrib->nr_frags != 1) + sz = padapter->xmitpriv.frag_len; + else /* no frag */ + sz = pattrib->last_txcmdsz; + + /* (1) RTS_Threshold is compared to the MPDU, not MSDU. */ + /* (2) If there are more than one frag in this MSDU, only the first frag uses protection frame. */ + /* Other fragments are protected by previous fragment. */ + /* So we only need to check the length of first fragment. */ + if (pmlmeext->cur_wireless_mode < WIRELESS_11_24N || padapter->registrypriv.wifi_spec) { + if (sz > padapter->registrypriv.rts_thresh) + pattrib->vcs_mode = RTS_CTS; + else { + if (pattrib->rtsen) + pattrib->vcs_mode = RTS_CTS; + else if (pattrib->cts2self) + pattrib->vcs_mode = CTS_TO_SELF; + else + pattrib->vcs_mode = NONE_VCS; + } + } else { + while (_TRUE) { + /* IOT action */ + if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en == _TRUE) && + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) { + pattrib->vcs_mode = CTS_TO_SELF; + break; + } + + /* check ERP protection */ + if (pattrib->rtsen || pattrib->cts2self) { + if (pattrib->rtsen) + pattrib->vcs_mode = RTS_CTS; + else if (pattrib->cts2self) + pattrib->vcs_mode = CTS_TO_SELF; + + break; + } + + /* check HT op mode */ + if (pattrib->ht_en) { + u8 HTOpMode = pmlmeinfo->HT_protection; + if ((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) || + (!pmlmeext->cur_bwmode && HTOpMode == 3)) { + pattrib->vcs_mode = RTS_CTS; + break; + } + } + + /* check rts */ + if (sz > padapter->registrypriv.rts_thresh) { + pattrib->vcs_mode = RTS_CTS; + break; + } + + /* to do list: check MIMO power save condition. */ + + /* check AMPDU aggregation for TXOP */ + if ((pattrib->ampdu_en == _TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) { + pattrib->vcs_mode = RTS_CTS; + break; + } + + pattrib->vcs_mode = NONE_VCS; + break; + } + } + + /* for debug : force driver control vrtl_carrier_sense. */ + if (padapter->driver_vcs_en == 1) { + /* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ + /* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ + pattrib->vcs_mode = padapter->driver_vcs_type; + } + +} + +static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) +{ + struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + u8 bw; + + pattrib->rtsen = psta->rtsen; + pattrib->cts2self = psta->cts2self; + + pattrib->mdata = 0; + pattrib->eosp = 0; + pattrib->triggered = 0; + pattrib->ampdu_spacing = 0; + + /* qos_en, ht_en, init rate, ,bw, ch_offset, sgi */ + pattrib->qos_en = psta->qos_option; + + pattrib->raid = psta->raid; + + bw = rtw_get_tx_bw_mode(padapter, psta); + pattrib->bwmode = rtw_min(bw, mlmeext->cur_bwmode); + pattrib->sgi = query_ra_short_GI(psta, pattrib->bwmode); + + pattrib->ldpc = psta->ldpc; + pattrib->stbc = psta->stbc; + + pattrib->ht_en = psta->htpriv.ht_option; + pattrib->ch_offset = psta->htpriv.ch_offset; + pattrib->ampdu_en = _FALSE; + + if (padapter->driver_ampdu_spacing != 0xFF) /* driver control AMPDU Density for peer sta's rx */ + pattrib->ampdu_spacing = padapter->driver_ampdu_spacing; + else + pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing; + + /* check if enable ampdu */ + if (pattrib->ht_en && psta->htpriv.ampdu_enable) { + if (psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) { + pattrib->ampdu_en = _TRUE; + if (psta->htpriv.tx_amsdu_enable == _TRUE) + pattrib->amsdu_ampdu_en = _TRUE; + else + pattrib->amsdu_ampdu_en = _FALSE; + } + } + /* if(pattrib->ht_en && psta->htpriv.ampdu_enable) */ + /* { */ + /* if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) */ + /* pattrib->ampdu_en = _TRUE; */ + /* } */ + + pattrib->retry_ctrl = _FALSE; + + +} + +static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) +{ + sint res = _SUCCESS; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + sint bmcast = IS_MCAST(pattrib->ra); + + _rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16); + _rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16); + pattrib->mac_id = psta->mac_id; + + if (psta->ieee8021x_blocked == _TRUE) { + + pattrib->encrypt = 0; + + if ((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) { + res = _FAIL; + goto exit; + } + } else { + GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast); + + switch (psecuritypriv->dot11AuthAlgrthm) { + case dot11AuthAlgrthm_Open: + case dot11AuthAlgrthm_Shared: + case dot11AuthAlgrthm_Auto: + pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex; + break; + case dot11AuthAlgrthm_8021X: + if (bmcast) + pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid; + else + pattrib->key_idx = 0; + break; + default: + pattrib->key_idx = 0; + break; + } + + /* For WPS 1.0 WEP, driver should not encrypt EAPOL Packet for WPS handshake. */ + if (((pattrib->encrypt == _WEP40_) || (pattrib->encrypt == _WEP104_)) && (pattrib->ether_type == 0x888e)) + pattrib->encrypt = _NO_PRIVACY_; + + } + + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + pattrib->iv_len = 4; + pattrib->icv_len = 4; + WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + break; + + case _TKIP_: + pattrib->iv_len = 8; + pattrib->icv_len = 4; + + if (psecuritypriv->busetkipkey == _FAIL) { + res = _FAIL; + goto exit; + } + + if (bmcast) + TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + TKIP_IV(pattrib->iv, psta->dot11txpn, 0); + + _rtw_memcpy(pattrib->dot11tkiptxmickey.skey, psta->dot11tkiptxmickey.skey, 16); + + break; + + case _AES_: + + pattrib->iv_len = 8; + pattrib->icv_len = 8; + + if (bmcast) + AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + AES_IV(pattrib->iv, psta->dot11txpn, 0); + + break; + + default: + pattrib->iv_len = 0; + pattrib->icv_len = 0; + break; + } + + if (pattrib->encrypt > 0) + _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); + + if (pattrib->encrypt && + ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) { + pattrib->bswenc = _TRUE; + } else { + pattrib->bswenc = _FALSE; + } + + + if (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH)) + pattrib->bswenc = _TRUE; + +exit: + + return res; + +} + +u8 qos_acm(u8 acm_mask, u8 priority) +{ + u8 change_priority = priority; + + switch (priority) { + case 0: + case 3: + if (acm_mask & BIT(1)) + change_priority = 1; + break; + case 1: + case 2: + break; + case 4: + case 5: + if (acm_mask & BIT(2)) + change_priority = 0; + break; + case 6: + case 7: + if (acm_mask & BIT(3)) + change_priority = 5; + break; + default: + RTW_INFO("qos_acm(): invalid pattrib->priority: %d!!!\n", priority); + break; + } + + return change_priority; +} + +static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib) +{ + struct ethhdr etherhdr; + struct iphdr ip_hdr; + s32 UserPriority = 0; + + _rtw_open_pktfile(ppktfile->pkt, ppktfile); + _rtw_pktfile_read(ppktfile, (unsigned char *)ðerhdr, ETH_HLEN); + + /* get UserPriority from IP hdr */ + if (pattrib->ether_type == 0x0800) { + _rtw_pktfile_read(ppktfile, (u8 *)&ip_hdr, sizeof(ip_hdr)); + /* UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; */ + UserPriority = ip_hdr.tos >> 5; + } + /* + else if (pattrib->ether_type == 0x888e) { + + UserPriority = 7; + } + */ + pattrib->priority = UserPriority; + pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; + pattrib->subtype = WIFI_QOS_DATA_TYPE; +} + +/*get non-qos hw_ssn control register,mapping to REG_HW_SEQ0,1,2,3*/ +inline u8 rtw_get_hwseq_no(_adapter *padapter) +{ + u8 hwseq_num = 0; + return hwseq_num; +} +static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib) +{ + uint i; + struct pkt_file pktfile; + struct sta_info *psta = NULL; + struct ethhdr etherhdr; + + sint bmcast; + struct sta_priv *pstapriv = &padapter->stapriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + sint res = _SUCCESS; + + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib); + + _rtw_open_pktfile(pkt, &pktfile); + i = _rtw_pktfile_read(&pktfile, (u8 *)ðerhdr, ETH_HLEN); + + pattrib->ether_type = ntohs(etherhdr.h_proto); + + _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); + _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc); + } else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_bssid(pmlmepriv), ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_ap); + } else + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown); + + bmcast = IS_MCAST(pattrib->ra); + if (bmcast) { + psta = rtw_get_bcmc_stainfo(padapter); + if (psta == NULL) { /* if we cannot get psta => drop the pkt */ + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta); + res = _FAIL; + goto exit; + } + } else { + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + if (psta == NULL) { /* if we cannot get psta => drop the pkt */ + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta); + res = _FAIL; + goto exit; + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link); + res = _FAIL; + goto exit; + } + } + + if (!(psta->state & _FW_LINKED)) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link); + RTW_INFO("%s-"ADPT_FMT" psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", __func__, ADPT_ARG(padapter), MAC_ARG(psta->hwaddr), psta->state); + res = _FAIL; + goto exit; + } + + pattrib->pktlen = pktfile.pkt_len; + + /* TODO: 802.1Q VLAN header */ + /* TODO: IPV6 */ + + if (ETH_P_IP == pattrib->ether_type) { + u8 ip[20]; + + _rtw_pktfile_read(&pktfile, ip, 20); + + if (GET_IPV4_IHL(ip) * 4 > 20) + _rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20); + + pattrib->icmp_pkt = 0; + pattrib->dhcp_pkt = 0; + + if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */ + pattrib->icmp_pkt = 1; + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp); + + } else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */ + u8 udp[8]; + + _rtw_pktfile_read(&pktfile, udp, 8); + + if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67) + || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68) + ) { + /* 67 : UDP BOOTP server, 68 : UDP BOOTP client */ + if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */ + pattrib->dhcp_pkt = 1; + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp); + if (0) + RTW_INFO("send DHCP packet\n"); + } + } + + } else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ + && rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE + ) { + u8 tcp[20]; + + _rtw_pktfile_read(&pktfile, tcp, 20); + + if (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) { + if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { + session_tracker_add_cmd(padapter, psta + , IPV4_SRC(ip), TCP_SRC(tcp) + , IPV4_SRC(ip), TCP_DST(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))); + } + if (GET_TCP_FIN(tcp)) { + session_tracker_del_cmd(padapter, psta + , IPV4_SRC(ip), TCP_SRC(tcp) + , IPV4_SRC(ip), TCP_DST(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))); + } + } + } + + } else if (0x888e == pattrib->ether_type) + RTW_PRINT("send eapol packet\n"); + + if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) + rtw_mi_set_scan_deny(padapter, 3000); + + /* If EAPOL , ARP , OR DHCP packet, driver must be in active mode. */ + /* if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) */ + if (pattrib->icmp_pkt == 1) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); + else if (pattrib->dhcp_pkt == 1) + { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active); + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 1); + } + + /* TODO:_lock */ + if (update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec); + res = _FAIL; + goto exit; + } + + update_attrib_phy_info(padapter, pattrib, psta); + + /* RTW_INFO("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); */ + + pattrib->psta = psta; + /* TODO:_unlock */ + + pattrib->pctrl = 0; + + pattrib->ack_policy = 0; + /* get ether_hdr_len */ + pattrib->pkt_hdrlen = ETH_HLEN;/* (pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; */ /* vlan tag */ + + pattrib->hdrlen = WLAN_HDR_A3_LEN; + pattrib->subtype = WIFI_DATA_TYPE; + pattrib->priority = 0; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { + if (pattrib->qos_en) + set_qos(&pktfile, pattrib); + } else { + { + if (pqospriv->qos_option) { + set_qos(&pktfile, pattrib); + + if (pmlmepriv->acm_mask != 0) + pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority); + } + } + } + + /* pattrib->priority = 5; */ /* force to used VI queue, for testing */ + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; + rtw_set_tx_chksum_offload(pkt, pattrib); + +exit: + + return res; +} + +static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + sint curfragnum, length; + u8 *pframe, *payload, mic[8]; + struct mic_data micdata; + /* struct sta_info *stainfo; */ + struct qos_priv *pqospriv = &(padapter->mlmepriv.qospriv); + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + u8 priority[4] = {0x0, 0x0, 0x0, 0x0}; + u8 hw_hdr_offset = 0; + sint bmcst = IS_MCAST(pattrib->ra); + + /* + if(pattrib->psta) + { + stainfo = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); + } + + if(stainfo==NULL) + { + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(stainfo->state &_FW_LINKED)) + { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); + return _FAIL; + } + */ + + hw_hdr_offset = TXDESC_OFFSET; + + if (pattrib->encrypt == _TKIP_) { /* if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) */ + /* encode mic code */ + /* if(stainfo!= NULL) */ + { + u8 null_key[16] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + + pframe = pxmitframe->buf_addr + hw_hdr_offset; + + if (bmcst) { + if (_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16) == _TRUE) { + /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ + /* rtw_msleep_os(10); */ + return _FAIL; + } + /* start to calculate the mic code */ + rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); + } else { + if (_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0], null_key, 16) == _TRUE) { + /* DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); */ + /* rtw_msleep_os(10); */ + return _FAIL; + } + /* start to calculate the mic code */ + rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]); + } + + if (pframe[1] & 1) { /* ToDS==1 */ + rtw_secmicappend(&micdata, &pframe[16], 6); /* DA */ + if (pframe[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &pframe[24], 6); + else + rtw_secmicappend(&micdata, &pframe[10], 6); + } else { /* ToDS==0 */ + rtw_secmicappend(&micdata, &pframe[4], 6); /* DA */ + if (pframe[1] & 2) /* From Ds==1 */ + rtw_secmicappend(&micdata, &pframe[16], 6); + else + rtw_secmicappend(&micdata, &pframe[10], 6); + + } + + /* if(pqospriv->qos_option==1) */ + if (pattrib->qos_en) + priority[0] = (u8)pxmitframe->attrib.priority; + + rtw_secmicappend(&micdata, &priority[0], 4); + + payload = pframe; + + for (curfragnum = 0; curfragnum < pattrib->nr_frags; curfragnum++) { + payload = (u8 *)RND4((SIZE_PTR)(payload)); + + payload = payload + pattrib->hdrlen + pattrib->iv_len; + if ((curfragnum + 1) == pattrib->nr_frags) { + length = pattrib->last_txcmdsz - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); + rtw_secmicappend(&micdata, payload, length); + payload = payload + length; + } else { + length = pxmitpriv->frag_len - pattrib->hdrlen - pattrib->iv_len - ((pattrib->bswenc) ? pattrib->icv_len : 0); + rtw_secmicappend(&micdata, payload, length); + payload = payload + length + pattrib->icv_len; + } + } + rtw_secgetmic(&micdata, &(mic[0])); + /* add mic code and add the mic code length in last_txcmdsz */ + + _rtw_memcpy(payload, &(mic[0]), 8); + pattrib->last_txcmdsz += 8; + + payload = payload - pattrib->last_txcmdsz + 8; + } + } + + return _SUCCESS; +} + +/*#define DBG_TX_SW_ENCRYPTOR*/ + +static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + /* struct security_priv *psecuritypriv=&padapter->securitypriv; */ + + /* if((psecuritypriv->sw_encrypt)||(pattrib->bswenc)) */ + if (pattrib->bswenc) { +#ifdef DBG_TX_SW_ENCRYPTOR + RTW_INFO(ADPT_FMT" - sec_type:%s DO SW encryption\n", + ADPT_ARG(padapter), security_type_str(pattrib->encrypt)); +#endif + + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + rtw_wep_encrypt(padapter, (u8 *)pxmitframe); + break; + case _TKIP_: + rtw_tkip_encrypt(padapter, (u8 *)pxmitframe); + break; + case _AES_: + rtw_aes_encrypt(padapter, (u8 *)pxmitframe); + break; + default: + break; + } + + } + + return _SUCCESS; +} + +s32 rtw_make_wlanhdr(_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) +{ + u16 *qc; + + struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + u8 qos_option = _FALSE; + sint res = _SUCCESS; + u16 *fctrl = &pwlanhdr->frame_ctl; + + /* struct sta_info *psta; */ + + /* sint bmcst = IS_MCAST(pattrib->ra); */ + + /* + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return; + } + + if(psta==NULL) + { + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(psta->state &_FW_LINKED)) + { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } + */ + + _rtw_memset(hdr, 0, WLANHDR_OFFSET); + + set_frame_sub_type(fctrl, pattrib->subtype); + + if (pattrib->subtype & WIFI_DATA_TYPE) { + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { + { + /* to_ds = 1, fr_ds = 0; */ + /* 1.Data transfer to AP */ + /* 2.Arp pkt will relayed by AP */ + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + + if (pqospriv->qos_option) + qos_option = _TRUE; + } + } else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)) { + /* to_ds = 0, fr_ds = 1; */ + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); + + if (pattrib->qos_en) + qos_option = _TRUE; + } else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + + if (pattrib->qos_en) + qos_option = _TRUE; + } else { + res = _FAIL; + goto exit; + } + + if (pattrib->mdata) + SetMData(fctrl); + + if (pattrib->encrypt) + SetPrivacy(fctrl); + + if (qos_option) { + qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + + if (pattrib->priority) + SetPriority(qc, pattrib->priority); + + SetEOSP(qc, pattrib->eosp); + + SetAckpolicy(qc, pattrib->ack_policy); + + if(pattrib->amsdu) + SetAMsdu(qc, pattrib->amsdu); + } + + /* TODO: fill HT Control Field */ + + /* Update Seq Num will be handled by f/w */ + { + struct sta_info *psta; + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FAIL; + } + + if (psta == NULL) { + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if (!(psta->state & _FW_LINKED)) { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } + + if (psta) { + psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; + + SetSeqNum(hdr, pattrib->seqnum); + + /* re-check if enable ampdu by BA_starting_seqctrl */ + if (pattrib->ampdu_en == _TRUE) { + u16 tx_seq; + + tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; + + /* check BA_starting_seqctrl */ + if (SN_LESS(pattrib->seqnum, tx_seq)) { + /* RTW_INFO("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); */ + pattrib->ampdu_en = _FALSE;/* AGG BK */ + } else if (SN_EQUAL(pattrib->seqnum, tx_seq)) { + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq + 1) & 0xfff; + + pattrib->ampdu_en = _TRUE;/* AGG EN */ + } else { + /* RTW_INFO("tx ampdu over run\n"); */ + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum + 1) & 0xfff; + pattrib->ampdu_en = _TRUE;/* AGG EN */ + } + + } + } + } + + } else { + + } + +exit: + + return res; +} + +s32 rtw_txframes_pending(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE)); +} + +s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) +{ + struct sta_info *psta; + struct tx_servq *ptxservq; + int priority = pattrib->priority; + /* + if(pattrib->psta) + { + psta = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); + } + */ + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return 0; + } + + if (psta == NULL) { + RTW_INFO("%s, psta==NUL\n", __func__); + return 0; + } + + if (!(psta->state & _FW_LINKED)) { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return 0; + } + + switch (priority) { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + break; + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + break; + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + break; + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + break; + + } + + return ptxservq->qcnt; +} + +/* + +This sub-routine will perform all the following: + +1. remove 802.3 header. +2. create wlan_header, based on the info in pxmitframe +3. append sta's iv/ext-iv +4. append LLC +5. move frag chunk from pframe to pxmitframe->mem +6. apply sw-encrypt, if necessary. + +*/ +s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) +{ + struct pkt_file pktfile; + + s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; + + SIZE_PTR addr; + + u8 *pframe, *mem_start; + u8 hw_hdr_offset; + + /* struct sta_info *psta; */ + /* struct sta_priv *pstapriv = &padapter->stapriv; */ + /* struct mlme_priv *pmlmepriv = &padapter->mlmepriv; */ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + u8 *pbuf_start; + + s32 bmcst = IS_MCAST(pattrib->ra); + s32 res = _SUCCESS; + + /* + if (pattrib->psta) + { + psta = pattrib->psta; + } else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + } + + if(psta==NULL) + { + + RTW_INFO("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(psta->state &_FW_LINKED)) + { + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } + */ + if (pxmitframe->buf_addr == NULL) { + RTW_INFO("==> %s buf_addr==NULL\n", __FUNCTION__); + return _FAIL; + } + + pbuf_start = pxmitframe->buf_addr; + + hw_hdr_offset = TXDESC_OFFSET; + + mem_start = pbuf_start + hw_hdr_offset; + + if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { + RTW_INFO("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); + res = _FAIL; + goto exit; + } + + _rtw_open_pktfile(pkt, &pktfile); + _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); + + frg_inx = 0; + frg_len = pxmitpriv->frag_len - 4;/* 2346-4 = 2342 */ + + while (1) { + llc_sz = 0; + + mpdu_len = frg_len; + + pframe = mem_start; + + SetMFrag(mem_start); + + pframe += pattrib->hdrlen; + mpdu_len -= pattrib->hdrlen; + + /* adding icv, if necessary... */ + if (pattrib->iv_len) { + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + pframe += pattrib->iv_len; + mpdu_len -= pattrib->iv_len; + } + + if (frg_inx == 0) { + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); + pframe += llc_sz; + mpdu_len -= llc_sz; + } + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) + mpdu_len -= pattrib->icv_len; + + if (bmcst) { + /* don't do fragment to broadcat/multicast packets */ + mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); + } else + mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len); + + pframe += mem_sz; + + if ((pattrib->icv_len > 0) && (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + + frg_inx++; + + if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) { + pattrib->nr_frags = frg_inx; + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags == 1) ? llc_sz : 0) + + ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; + + ClearMFrag(mem_start); + + break; + } + + addr = (SIZE_PTR)(pframe); + + mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset; + _rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen); + + } + + if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) { + RTW_INFO("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); + res = _FAIL; + goto exit; + } + + xmitframe_swencrypt(padapter, pxmitframe); + + if (bmcst == _FALSE) + update_attrib_vcs_info(padapter, pxmitframe); + else + pattrib->vcs_mode = NONE_VCS; + +exit: + + return res; +} + +/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header + * IEEE LLC/SNAP header contains 8 octets + * First 3 octets comprise the LLC portion + * SNAP portion, 5 octets, is divided into two fields: + * Organizationally Unique Identifier(OUI), 3 octets, + * type, defined by that organization, 2 octets. + */ +s32 rtw_put_snap(u8 *data, u16 h_proto) +{ + struct ieee80211_snap_hdr *snap; + u8 *oui; + + snap = (struct ieee80211_snap_hdr *)data; + snap->dsap = 0xaa; + snap->ssap = 0xaa; + snap->ctrl = 0x03; + + if (h_proto == 0x8137 || h_proto == 0x80f3) + oui = P802_1H_OUI; + else + oui = RFC1042_OUI; + + snap->oui[0] = oui[0]; + snap->oui[1] = oui[1]; + snap->oui[2] = oui[2]; + + *(u16 *)(data + SNAP_SIZE) = htons(h_proto); + + return SNAP_SIZE + sizeof(u16); +} + +void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) +{ + + uint protection; + u8 *perp; + sint erp_len; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + switch (pxmitpriv->vcs_setting) { + case DISABLE_VCS: + pxmitpriv->vcs = NONE_VCS; + break; + + case ENABLE_VCS: + break; + + case AUTO_VCS: + default: + perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len); + if (perp == NULL) + pxmitpriv->vcs = NONE_VCS; + else { + protection = (*(perp + 2)) & BIT(1); + if (protection) { + if (pregistrypriv->vcs_type == RTS_CTS) + pxmitpriv->vcs = RTS_CTS; + else + pxmitpriv->vcs = CTS_TO_SELF; + } else + pxmitpriv->vcs = NONE_VCS; + } + + break; + + } + +} + +void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz) +{ + struct sta_info *psta = NULL; + struct stainfo_stats *pstats = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 pkt_num = 1; + + if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) { + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pkt_num; + + pxmitpriv->tx_pkts += pkt_num; + + pxmitpriv->tx_bytes += sz; + + psta = pxmitframe->attrib.psta; + if (psta) { + pstats = &psta->sta_stats; + + pstats->tx_pkts += pkt_num; + + pstats->tx_bytes += sz; + } + + + } +} + +static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type) +{ + struct xmit_buf *pxmitbuf = NULL; + + pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type]; + if (pxmitbuf != NULL) { + pxmitbuf->priv_data = NULL; + + pxmitbuf->len = 0; + /*pxmitbuf->buf_desc = NULL;*/ + + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } + } else + RTW_INFO("%s fail, no xmitbuf available !!!\n", __func__); + + return pxmitbuf; +} + +struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type) +{ + struct xmit_frame *pcmdframe; + struct xmit_buf *pxmitbuf; + + pcmdframe = rtw_alloc_xmitframe(pxmitpriv); + if (pcmdframe == NULL) { + RTW_INFO("%s, alloc xmitframe fail\n", __FUNCTION__); + return NULL; + } + + pxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type); + if (pxmitbuf == NULL) { + RTW_INFO("%s, alloc xmitbuf fail\n", __FUNCTION__); + rtw_free_xmitframe(pxmitpriv, pcmdframe); + return NULL; + } + + pcmdframe->frame_tag = MGNT_FRAMETAG; + + pcmdframe->pxmitbuf = pxmitbuf; + + pcmdframe->buf_addr = pxmitbuf->pbuf; + + /* initial memory to zero */ + _rtw_memset(pcmdframe->buf_addr, 0, pxmitbuf->alloc_sz); + + pxmitbuf->priv_data = pcmdframe; + + return pcmdframe; + +} + +struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) +{ + _irqL irqL; + struct xmit_buf *pxmitbuf = NULL; + _list *plist, *phead; + _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; + + _enter_critical(&pfree_queue->lock, &irqL); + + if (_rtw_queue_empty(pfree_queue) == _TRUE) + pxmitbuf = NULL; + else { + + phead = get_list_head(pfree_queue); + + plist = get_next(phead); + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + + rtw_list_delete(&(pxmitbuf->list)); + } + + if (pxmitbuf != NULL) { + pxmitpriv->free_xmit_extbuf_cnt--; + + pxmitbuf->priv_data = NULL; + + pxmitbuf->len = 0; + /*pxmitbuf->buf_desc = NULL;*/ + + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } + + } + + _exit_critical(&pfree_queue->lock, &irqL); + + return pxmitbuf; +} + +s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + _irqL irqL; + _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; + + if (pxmitbuf == NULL) + return _FAIL; + + _enter_critical(&pfree_queue->lock, &irqL); + + rtw_list_delete(&pxmitbuf->list); + + rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue)); + pxmitpriv->free_xmit_extbuf_cnt++; + + _exit_critical(&pfree_queue->lock, &irqL); + + return _SUCCESS; +} + +struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) +{ + _irqL irqL; + struct xmit_buf *pxmitbuf = NULL; + _list *plist, *phead; + _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; + + /* RTW_INFO("+rtw_alloc_xmitbuf\n"); */ + + _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); + + if (_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE) + pxmitbuf = NULL; + else { + + phead = get_list_head(pfree_xmitbuf_queue); + + plist = get_next(phead); + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + + rtw_list_delete(&(pxmitbuf->list)); + } + + if (pxmitbuf != NULL) { + pxmitpriv->free_xmitbuf_cnt--; + /* RTW_INFO("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */ + + pxmitbuf->priv_data = NULL; + + pxmitbuf->len = 0; + /*pxmitbuf->buf_desc = NULL;*/ + + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } + } + + _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); + + return pxmitbuf; +} + +s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + _irqL irqL; + _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; + + /* RTW_INFO("+rtw_free_xmitbuf\n"); */ + + if (pxmitbuf == NULL) + return _FAIL; + + if (pxmitbuf->sctx) { + RTW_INFO("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE); + } + + if (pxmitbuf->buf_tag == XMITBUF_CMD) { + } else if (pxmitbuf->buf_tag == XMITBUF_MGNT) + rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf); + else { + _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); + + rtw_list_delete(&pxmitbuf->list); + + rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue)); + + pxmitpriv->free_xmitbuf_cnt++; + /* RTW_INFO("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); */ + _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); + } + + return _SUCCESS; +} + +void rtw_init_xmitframe(struct xmit_frame *pxframe) +{ + if (pxframe != NULL) { /* default value setting */ + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); + /* pxframe->attrib.psta = NULL; */ + + pxframe->frame_tag = DATA_FRAMETAG; + + pxframe->ack_report = 0; + + } +} + +/* +Calling context: +1. OS_TXENTRY +2. RXENTRY (rx_thread or RX_ISR/RX_CallBack) + +If we turn on USE_RXTHREAD, then, no need for critical section. +Otherwise, we must use _enter/_exit critical to protect free_xmit_queue... + +Must be very very cautious... + +*/ +struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)/* (_queue *pfree_xmit_queue) */ +{ + /* + Please remember to use all the osdep_service api, + and lock/unlock or _enter/_exit critical to protect + pfree_xmit_queue + */ + + _irqL irqL; + struct xmit_frame *pxframe = NULL; + _list *plist, *phead; + _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; + + _enter_critical_bh(&pfree_xmit_queue->lock, &irqL); + + if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { + pxframe = NULL; + } else { + phead = get_list_head(pfree_xmit_queue); + + plist = get_next(phead); + + pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + rtw_list_delete(&(pxframe->list)); + pxmitpriv->free_xmitframe_cnt--; + } + + _exit_critical_bh(&pfree_xmit_queue->lock, &irqL); + + rtw_init_xmitframe(pxframe); + + return pxframe; +} + +struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv) +{ + _irqL irqL; + struct xmit_frame *pxframe = NULL; + _list *plist, *phead; + _queue *queue = &pxmitpriv->free_xframe_ext_queue; + + _enter_critical_bh(&queue->lock, &irqL); + + if (_rtw_queue_empty(queue) == _TRUE) { + pxframe = NULL; + } else { + phead = get_list_head(queue); + plist = get_next(phead); + pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + rtw_list_delete(&(pxframe->list)); + pxmitpriv->free_xframe_ext_cnt--; + } + + _exit_critical_bh(&queue->lock, &irqL); + + rtw_init_xmitframe(pxframe); + + return pxframe; +} + +struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv) +{ + struct xmit_frame *pxframe = NULL; + u8 *alloc_addr; + + alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4); + + if (alloc_addr == NULL) + goto exit; + + pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4); + pxframe->alloc_addr = alloc_addr; + + pxframe->padapter = pxmitpriv->adapter; + pxframe->frame_tag = NULL_FRAMETAG; + + pxframe->pkt = NULL; + + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + rtw_init_xmitframe(pxframe); + + RTW_INFO("################## %s ##################\n", __func__); + +exit: + return pxframe; +} + +s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe) +{ + _irqL irqL; + _queue *queue = NULL; + _adapter *padapter = pxmitpriv->adapter; + _pkt *pndis_pkt = NULL; + + if (pxmitframe == NULL) { + goto exit; + } + + if (pxmitframe->pkt) { + pndis_pkt = pxmitframe->pkt; + pxmitframe->pkt = NULL; + } + + if (pxmitframe->alloc_addr) { + RTW_INFO("################## %s with alloc_addr ##################\n", __func__); + rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4); + goto check_pkt_complete; + } + + if (pxmitframe->ext_tag == 0) + queue = &pxmitpriv->free_xmit_queue; + else if (pxmitframe->ext_tag == 1) + queue = &pxmitpriv->free_xframe_ext_queue; + else + rtw_warn_on(1); + + _enter_critical_bh(&queue->lock, &irqL); + + rtw_list_delete(&pxmitframe->list); + rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue)); + if (pxmitframe->ext_tag == 0) { + pxmitpriv->free_xmitframe_cnt++; + } else if (pxmitframe->ext_tag == 1) { + pxmitpriv->free_xframe_ext_cnt++; + } else { + } + + _exit_critical_bh(&queue->lock, &irqL); + +check_pkt_complete: + + if (pndis_pkt) + rtw_os_pkt_complete(padapter, pndis_pkt); + +exit: + + return _SUCCESS; +} + +void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) +{ + _irqL irqL; + _list *plist, *phead; + struct xmit_frame *pxmitframe; + + _enter_critical_bh(&(pframequeue->lock), &irqL); + + phead = get_list_head(pframequeue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + + pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + plist = get_next(plist); + + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + } + _exit_critical_bh(&(pframequeue->lock), &irqL); + +} + +s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue); + if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) { + /* pxmitframe->pkt = NULL; */ + return _FAIL; + } + + return _SUCCESS; +} + +static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) +{ + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + + xmitframe_phead = get_list_head(pframe_queue); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + rtw_list_delete(&pxmitframe->list); + + ptxservq->qcnt--; + + break; + } + + return pxmitframe; +} + +struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry) +{ + _irqL irqL0; + _list *sta_plist, *sta_phead; + struct hw_xmit *phwxmit; + struct tx_servq *ptxservq = NULL; + _queue *pframe_queue = NULL; + struct xmit_frame *pxmitframe = NULL; + _adapter *padapter = pxmitpriv->adapter; + struct registry_priv *pregpriv = &padapter->registrypriv; + int i, inx[4]; + + inx[0] = 0; + inx[1] = 1; + inx[2] = 2; + inx[3] = 3; + + if (pregpriv->wifi_spec == 1) { + int j, tmp, acirp_cnt[4]; + + for (j = 0; j < 4; j++) + inx[j] = pxmitpriv->wmm_para_seq[j]; + } + + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + + for (i = 0; i < entry; i++) { + phwxmit = phwxmit_i + inx[i]; + + /* _enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */ + + sta_phead = get_list_head(phwxmit->sta_queue); + sta_plist = get_next(sta_phead); + + while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) { + + ptxservq = LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); + + pframe_queue = &ptxservq->sta_pending; + + pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); + + if (pxmitframe) { + phwxmit->accnt--; + + /* Remove sta node when there is no pending packets. */ + if (_rtw_queue_empty(pframe_queue)) /* must be done after get_next and before break */ + rtw_list_delete(&ptxservq->tx_pending); + + /* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */ + + goto exit; + } + + sta_plist = get_next(sta_plist); + + } + + /* _exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); */ + + } + +exit: + + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + + return pxmitframe; +} + +struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac) +{ + struct tx_servq *ptxservq = NULL; + + switch (up) { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + *(ac) = 3; + break; + + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + *(ac) = 1; + break; + + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + *(ac) = 0; + break; + + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + *(ac) = 2; + break; + + } + + return ptxservq; +} + +/* + * Will enqueue pxmitframe to the proper queue, + * and indicate it to xx_pending list..... + */ +s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + /* _irqL irqL0; */ + u8 ac_index; + struct sta_info *psta; + struct tx_servq *ptxservq; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; + sint res = _SUCCESS; + + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class); + + /* + if (pattrib->psta) { + psta = pattrib->psta; + } else { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + } + */ + + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta); + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FAIL; + } + + if (psta == NULL) { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta); + res = _FAIL; + RTW_INFO("rtw_xmit_classifier: psta == NULL\n"); + goto exit; + } + + if (!(psta->state & _FW_LINKED)) { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink); + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } + + ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); + + /* _enter_critical(&pstapending->lock, &irqL0); */ + + if (rtw_is_list_empty(&ptxservq->tx_pending)) + rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue)); + + /* _enter_critical(&ptxservq->sta_pending.lock, &irqL1); */ + + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); + ptxservq->qcnt++; + phwxmits[ac_index].accnt++; + + /* _exit_critical(&ptxservq->sta_pending.lock, &irqL1); */ + + /* _exit_critical(&pstapending->lock, &irqL0); */ + +exit: + + return res; +} + +void rtw_alloc_hwxmits(_adapter *padapter) +{ + struct hw_xmit *hwxmits; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + pxmitpriv->hwxmit_entry = HWXMIT_ENTRY; + + pxmitpriv->hwxmits = NULL; + + pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry); + + if (pxmitpriv->hwxmits == NULL) { + RTW_INFO("alloc hwxmits fail!...\n"); + return; + } + + hwxmits = pxmitpriv->hwxmits; + + if (pxmitpriv->hwxmit_entry == 5) { + /* pxmitpriv->bmc_txqueue.head = 0; */ + /* hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; */ + hwxmits[0] .sta_queue = &pxmitpriv->bm_pending; + + /* pxmitpriv->vo_txqueue.head = 0; */ + /* hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; */ + hwxmits[1] .sta_queue = &pxmitpriv->vo_pending; + + /* pxmitpriv->vi_txqueue.head = 0; */ + /* hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; */ + hwxmits[2] .sta_queue = &pxmitpriv->vi_pending; + + /* pxmitpriv->bk_txqueue.head = 0; */ + /* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */ + hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; + + /* pxmitpriv->be_txqueue.head = 0; */ + /* hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; */ + hwxmits[4] .sta_queue = &pxmitpriv->be_pending; + + } else if (pxmitpriv->hwxmit_entry == 4) { + + /* pxmitpriv->vo_txqueue.head = 0; */ + /* hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; */ + hwxmits[0] .sta_queue = &pxmitpriv->vo_pending; + + /* pxmitpriv->vi_txqueue.head = 0; */ + /* hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; */ + hwxmits[1] .sta_queue = &pxmitpriv->vi_pending; + + /* pxmitpriv->be_txqueue.head = 0; */ + /* hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; */ + hwxmits[2] .sta_queue = &pxmitpriv->be_pending; + + /* pxmitpriv->bk_txqueue.head = 0; */ + /* hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; */ + hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; + } else { + + } + +} + +void rtw_free_hwxmits(_adapter *padapter) +{ + struct hw_xmit *hwxmits; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + hwxmits = pxmitpriv->hwxmits; + if (hwxmits) + rtw_mfree((u8 *)hwxmits, (sizeof(struct hw_xmit) * pxmitpriv->hwxmit_entry)); +} + +void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) +{ + sint i; + for (i = 0; i < entry; i++, phwxmit++) { + /* _rtw_spinlock_init(&phwxmit->xmit_lock); */ + /* _rtw_init_listhead(&phwxmit->pending); */ + /* phwxmit->txcmdcnt = 0; */ + phwxmit->accnt = 0; + } +} + +int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb) +{ + struct sk_buff *skb = *pskb; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _irqL irqL; + /* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */ + { + void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb); + int res, is_vlan_tag = 0, i, do_nat25 = 1; + unsigned short vlan_hdr = 0; + void *br_port = NULL; + + /* mac_clone_handle_frame(priv, skb); */ + + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + _enter_critical_bh(&padapter->br_ext_lock, &irqL); + if (!(skb->data[0] & 1) && + br_port && + memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) && + *((unsigned short *)(skb->data + MACADDRLEN * 2)) != __constant_htons(ETH_P_8021Q) && + *((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP) && + !memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) { + memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + padapter->scdb_entry->ageing_timer = jiffies; + _exit_critical_bh(&padapter->br_ext_lock, &irqL); + } else + /* if (!priv->pmib->ethBrExtInfo.nat25_disable) */ + { + /* if (priv->dev->br_port && + * !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { */ + if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_8021Q)) { + is_vlan_tag = 1; + vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2)); + skb_pull(skb, 4); + } + /* if SA == br_mac && skb== IP => copy SIP to br_ip ?? why */ + if (!memcmp(skb->data + MACADDRLEN, padapter->br_mac, MACADDRLEN) && + (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP))) + memcpy(padapter->br_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4); + + if (*((unsigned short *)(skb->data + MACADDRLEN * 2)) == __constant_htons(ETH_P_IP)) { + if (memcmp(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN)) { + void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr); + + padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter, + skb->data + MACADDRLEN, skb->data + WLAN_ETHHDR_LEN + 12); + if (padapter->scdb_entry != NULL) { + memcpy(padapter->scdb_mac, skb->data + MACADDRLEN, MACADDRLEN); + memcpy(padapter->scdb_ip, skb->data + WLAN_ETHHDR_LEN + 12, 4); + padapter->scdb_entry->ageing_timer = jiffies; + do_nat25 = 0; + } + } else { + if (padapter->scdb_entry) { + padapter->scdb_entry->ageing_timer = jiffies; + do_nat25 = 0; + } else { + memset(padapter->scdb_mac, 0, MACADDRLEN); + memset(padapter->scdb_ip, 0, 4); + } + } + } + _exit_critical_bh(&padapter->br_ext_lock, &irqL); + if (do_nat25) { + int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method); + if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) { + struct sk_buff *newskb; + + if (is_vlan_tag) { + skb_push(skb, 4); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2)); + *((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr; + } + + newskb = rtw_skb_copy(skb); + if (newskb == NULL) { + /* priv->ext_stats.tx_drops++; */ + DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n"); + /* goto stop_proc; */ + return -1; + } + rtw_skb_free(skb); + + *pskb = skb = newskb; + if (is_vlan_tag) { + vlan_hdr = *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2 - i * 2)) = *((unsigned short *)(skb->data + MACADDRLEN * 2 - 2 - i * 2)); + skb_pull(skb, 4); + } + } + + if (skb_is_nonlinear(skb)) + DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__); + + res = skb_linearize(skb); + if (res < 0) { + DEBUG_ERR("TX DROP: skb_linearize fail!\n"); + /* goto free_and_stop; */ + return -1; + } + + res = nat25_db_handle(padapter, skb, NAT25_INSERT); + if (res < 0) { + if (res == -2) { + /* priv->ext_stats.tx_drops++; */ + DEBUG_ERR("TX DROP: nat25_db_handle fail!\n"); + /* goto free_and_stop; */ + return -1; + + } + /* we just print warning message and let it go */ + /* DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); */ + /* return -1; */ /* return -1 will cause system crash on 2011/08/30! */ + return 0; + } + } + + memcpy(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + + dhcp_flag_bcast(padapter, skb); + + if (is_vlan_tag) { + skb_push(skb, 4); + for (i = 0; i < 6; i++) + *((unsigned short *)(skb->data + i * 2)) = *((unsigned short *)(skb->data + 4 + i * 2)); + *((unsigned short *)(skb->data + MACADDRLEN * 2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data + MACADDRLEN * 2 + 2)) = vlan_hdr; + } + } + + /* check if SA is equal to our MAC */ + if (memcmp(skb->data + MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) { + /* priv->ext_stats.tx_drops++; */ + DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n", + skb->data[6], skb->data[7], skb->data[8], skb->data[9], skb->data[10], skb->data[11]); + /* goto free_and_stop; */ + return -1; + } + } + return 0; +} + +u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe) +{ + u32 addr; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + switch (pattrib->qsel) { + case 0: + case 3: + addr = BE_QUEUE_INX; + break; + case 1: + case 2: + addr = BK_QUEUE_INX; + break; + case 4: + case 5: + addr = VI_QUEUE_INX; + break; + case 6: + case 7: + addr = VO_QUEUE_INX; + break; + case 0x10: + addr = BCN_QUEUE_INX; + break; + case 0x11: /* BC/MC in PS (HIQ) */ + addr = HIGH_QUEUE_INX; + break; + case 0x13: + addr = TXCMD_QUEUE_INX; + break; + case 0x12: + default: + addr = MGT_QUEUE_INX; + break; + + } + + return addr; + +} + +static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u8 qsel; + + qsel = pattrib->priority; + + + pattrib->qsel = qsel; +} + +/* + * The main transmit(tx) entry + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) +{ + int ret = 0; + int rtap_len; + int qos_len = 0; + int dot11_hdr_len = 24; + int snap_len = 6; + unsigned char *pdata; + u16 frame_ctl; + unsigned char src_mac_addr[6]; + unsigned char dst_mac_addr[6]; + struct rtw_ieee80211_hdr *dot11_hdr; + struct ieee80211_radiotap_header *rtap_hdr; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + + if (skb) + rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); + + if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) + goto fail; + + rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; + if (unlikely(rtap_hdr->it_version)) + goto fail; + + rtap_len = ieee80211_get_radiotap_len(skb->data); + if (unlikely(skb->len < rtap_len)) + goto fail; + + if (rtap_len != 12) { + RTW_INFO("radiotap len (should be 14): %d\n", rtap_len); + goto fail; + } + + /* Skip the ratio tap header */ + skb_pull(skb, rtap_len); + + dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data; + frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl); + /* Check if the QoS bit is set */ + + if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 *buf = skb->data; + u32 len = skb->len; + u8 category, action; + int type = -1; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + rtw_udelay_os(500); + goto fail; + } + pattrib = &pmgntframe->attrib; + + update_monitor_frame_attrib(padapter, pattrib); + + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pframe, (void *)buf, len); + + pattrib->pktlen = len; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1)) + pattrib->rate = MGN_24M; + + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + } else { + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 *buf = skb->data; + u32 len = skb->len; + u8 category, action; + int type = -1; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto fail; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pframe, (void *)buf, len); + + pattrib->pktlen = len; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + } + +fail: + + rtw_skb_free(skb); + + return 0; +} +/* + * The main transmit(tx) entry + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) +{ + static u32 start = 0; + static u32 drop_cnt = 0; + _irqL irqL0; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pxmitframe = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + void *br_port = NULL; + + s32 res; + + DBG_COUNTER(padapter->tx_logs.core_tx); + + if (start == 0) + start = rtw_get_current_time(); + + pxmitframe = rtw_alloc_xmitframe(pxmitpriv); + + if (rtw_get_passing_time_ms(start) > 2000) { + if (drop_cnt) + RTW_INFO("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt); + start = rtw_get_current_time(); + drop_cnt = 0; + } + + if (pxmitframe == NULL) { + drop_cnt++; + /*RTW_INFO("%s-"ADPT_FMT" no more xmitframe\n", __func__, ADPT_ARG(padapter));*/ + DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe); + return -1; + } + + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + + if (br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE) { + res = rtw_br_client_tx(padapter, ppkt); + if (res == -1) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); + return -1; + } + } + + res = update_attrib(padapter, *ppkt, &pxmitframe->attrib); + + if (res == _FAIL) { + /*RTW_INFO("%s-"ADPT_FMT" update attrib fail\n", __func__, ADPT_ARG(padapter));*/ + rtw_free_xmitframe(pxmitpriv, pxmitframe); + return -1; + } + pxmitframe->pkt = *ppkt; + + rtw_led_control(padapter, LED_CTL_TX); + + do_queue_select(padapter, &pxmitframe->attrib); + + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + if (xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) { + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); + return 1; + } + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + + /* pre_xmitframe */ + if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) + return 1; + + return 0; +} + +#define RTW_HIQ_FILTER_ALLOW_ALL 0 +#define RTW_HIQ_FILTER_ALLOW_SPECIAL 1 +#define RTW_HIQ_FILTER_DENY_ALL 2 + +inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe) +{ + bool allow = _FALSE; + _adapter *adapter = xmitframe->padapter; + struct registry_priv *registry = &adapter->registrypriv; + + if (rtw_get_intf_type(adapter) != RTW_PCIE) { + + if (adapter->registrypriv.wifi_spec == 1) + allow = _TRUE; + else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) { + + struct pkt_attrib *attrib = &xmitframe->attrib; + + if (attrib->ether_type == 0x0806 + || attrib->ether_type == 0x888e + || attrib->dhcp_pkt + ) { + if (0) + RTW_INFO(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter) + , attrib->ether_type, attrib->dhcp_pkt ? " DHCP" : ""); + allow = _TRUE; + } + } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL) + allow = _TRUE; + else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL) { + } else + rtw_warn_on(1); + } + return allow; +} + + +sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + _irqL irqL; + sint ret = _FALSE; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + sint bmcst = IS_MCAST(pattrib->ra); + bool update_tim = _FALSE; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate); + return ret; + } + /* + if(pattrib->psta) + { + psta = pattrib->psta; + } + else + { + RTW_INFO("%s, call rtw_get_stainfo()\n", __func__); + psta=rtw_get_stainfo(pstapriv, pattrib->ra); + } + */ + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if (pattrib->psta != psta) { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_sta); + RTW_INFO("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FALSE; + } + + if (psta == NULL) { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_nosta); + RTW_INFO("%s, psta==NUL\n", __func__); + return _FALSE; + } + + if (!(psta->state & _FW_LINKED)) { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link); + RTW_INFO("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FALSE; + } + + if (pattrib->triggered == 1) { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_trigger); + /* RTW_INFO("directly xmit pspoll_triggered packet\n"); */ + + /* pattrib->triggered=0; */ + if (bmcst && xmitframe_hiq_filter(pxmitframe) == _TRUE) + pattrib->qsel = QSLT_HIGH;/* HIQ */ + + return ret; + } + + if (bmcst) { + _enter_critical_bh(&psta->sleep_q.lock, &irqL); + + if (pstapriv->sta_dz_bitmap) { /* if anyone sta is in ps mode */ + /* pattrib->qsel = QSLT_HIGH; */ /* HIQ */ + + rtw_list_delete(&pxmitframe->list); + + /*_enter_critical_bh(&psta->sleep_q.lock, &irqL);*/ + + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); + + psta->sleepq_len++; + + if (!(pstapriv->tim_bitmap & BIT(0))) + update_tim = _TRUE; + + pstapriv->tim_bitmap |= BIT(0); + pstapriv->sta_dz_bitmap |= BIT(0); + + /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + if (update_tim == _TRUE) { + if (is_broadcast_mac_addr(pattrib->ra)) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC"); + else + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer MC"); + } else + chk_bmc_sleepq_cmd(padapter); + + /*_exit_critical_bh(&psta->sleep_q.lock, &irqL);*/ + + ret = _TRUE; + + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast); + + } + + _exit_critical_bh(&psta->sleep_q.lock, &irqL); + + return ret; + + } + + _enter_critical_bh(&psta->sleep_q.lock, &irqL); + + if (psta->state & WIFI_SLEEP_STATE) { + u8 wmmps_ac = 0; + + if (pstapriv->sta_dz_bitmap & BIT(psta->aid)) { + rtw_list_delete(&pxmitframe->list); + + /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ + + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); + + psta->sleepq_len++; + + switch (pattrib->priority) { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk & BIT(0); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi & BIT(0); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo & BIT(0); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be & BIT(0); + break; + } + + if (wmmps_ac) + psta->sleepq_ac_len++; + + if (((psta->has_legacy_ac) && (!wmmps_ac)) || ((!psta->has_legacy_ac) && (wmmps_ac))) { + if (!(pstapriv->tim_bitmap & BIT(psta->aid))) + update_tim = _TRUE; + + pstapriv->tim_bitmap |= BIT(psta->aid); + + /* RTW_INFO("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); */ + + if (update_tim == _TRUE) { + /* RTW_INFO("sleepq_len==1, update BCNTIM\n"); */ + /* upate BCN for TIM IE */ + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer UC"); + } + } + + /* _exit_critical_bh(&psta->sleep_q.lock, &irqL); */ + + /* if(psta->sleepq_len > (NR_XMITFRAME>>3)) */ + /* { */ + /* wakeup_sta_to_xmit(padapter, psta); */ + /* } */ + + ret = _TRUE; + + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast); + } + + } + + _exit_critical_bh(&psta->sleep_q.lock, &irqL); + + return ret; + +} + +static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue) +{ + sint ret; + _list *plist, *phead; + u8 ac_index; + struct tx_servq *ptxservq; + struct pkt_attrib *pattrib; + struct xmit_frame *pxmitframe; + struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; + + phead = get_list_head(pframequeue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + plist = get_next(plist); + + pattrib = &pxmitframe->attrib; + + pattrib->triggered = 0; + + ret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe); + + if (_TRUE == ret) { + ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); + + ptxservq->qcnt--; + phwxmits[ac_index].accnt--; + } else { + /* RTW_INFO("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); */ + } + + } + +} + +void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL0; + struct sta_info *psta_bmc; + struct sta_xmit_priv *pstaxmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + pstaxmitpriv = &psta->sta_xmitpriv; + + /* for BC/MC Frames */ + psta_bmc = rtw_get_bcmc_stainfo(padapter); + + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + + psta->state |= WIFI_SLEEP_STATE; + + pstapriv->sta_dz_bitmap |= BIT(psta->aid); + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); + + /* for BC/MC Frames */ + pstaxmitpriv = &psta_bmc->sta_xmitpriv; + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); + + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + +} + +void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + u8 update_mask = 0, wmmps_ac = 0; + struct sta_info *psta_bmc; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + psta_bmc = rtw_get_bcmc_stainfo(padapter); + + /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + switch (pxmitframe->attrib.priority) { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk & BIT(1); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi & BIT(1); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo & BIT(1); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be & BIT(1); + break; + } + + psta->sleepq_len--; + if (psta->sleepq_len > 0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + if (wmmps_ac) { + psta->sleepq_ac_len--; + if (psta->sleepq_ac_len > 0) { + pxmitframe->attrib.mdata = 1; + pxmitframe->attrib.eosp = 0; + } else { + pxmitframe->attrib.mdata = 0; + pxmitframe->attrib.eosp = 1; + } + } + + pxmitframe->attrib.triggered = 1; + + /* + _exit_critical_bh(&psta->sleep_q.lock, &irqL); + if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + { + rtw_os_xmit_complete(padapter, pxmitframe); + } + _enter_critical_bh(&psta->sleep_q.lock, &irqL); + */ + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + } + + if (psta->sleepq_len == 0) { + + if (pstapriv->tim_bitmap & BIT(psta->aid)) { + /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + /* upate BCN for TIM IE */ + /* update_BCNTIM(padapter); */ + update_mask = BIT(0); + } + + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + if (psta->state & WIFI_SLEEP_STATE) + psta->state ^= WIFI_SLEEP_STATE; + + if (psta->state & WIFI_STA_ALIVE_CHK_STATE) { + RTW_INFO("%s alive check\n", __func__); + psta->expire_to = pstapriv->expire_to; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + } + + pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); + } + + /* for BC/MC Frames */ + if (!psta_bmc) + goto _exit; + + if ((pstapriv->sta_dz_bitmap & 0xfffe) == 0x0) { /* no any sta in ps mode */ + xmitframe_phead = get_list_head(&psta_bmc->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + psta_bmc->sleepq_len--; + if (psta_bmc->sleepq_len > 0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + pxmitframe->attrib.triggered = 1; + /* + _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + { + rtw_os_xmit_complete(padapter, pxmitframe); + } + _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + + */ + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + } + + if (psta_bmc->sleepq_len == 0) { + if (pstapriv->tim_bitmap & BIT(0)) { + /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + /* upate BCN for TIM IE */ + /* update_BCNTIM(padapter); */ + update_mask |= BIT(1); + } + pstapriv->tim_bitmap &= ~BIT(0); + pstapriv->sta_dz_bitmap &= ~BIT(0); + } + + } + +_exit: + + /* _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); */ + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + if (update_mask) { + /* update_BCNTIM(padapter); */ + if ((update_mask & (BIT(0) | BIT(1))) == (BIT(0) | BIT(1))) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear UC&BMC"); + else if ((update_mask & BIT(1)) == BIT(1)) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear BMC"); + else + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear UC"); + } + +} + +void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + u8 wmmps_ac = 0; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + /* _enter_critical_bh(&psta->sleep_q.lock, &irqL); */ + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + switch (pxmitframe->attrib.priority) { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk & BIT(1); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi & BIT(1); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo & BIT(1); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be & BIT(1); + break; + } + + if (!wmmps_ac) + continue; + + rtw_list_delete(&pxmitframe->list); + + psta->sleepq_len--; + psta->sleepq_ac_len--; + + if (psta->sleepq_ac_len > 0) { + pxmitframe->attrib.mdata = 1; + pxmitframe->attrib.eosp = 0; + } else { + pxmitframe->attrib.mdata = 0; + pxmitframe->attrib.eosp = 1; + } + + pxmitframe->attrib.triggered = 1; + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + if ((psta->sleepq_ac_len == 0) && (!psta->has_legacy_ac) && (wmmps_ac)) { + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + /* RTW_INFO("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); */ + /* upate BCN for TIM IE */ + /* update_BCNTIM(padapter); */ + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + /* update_mask = BIT(0); */ + } + + } + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + return; +} + +bool rtw_xmit_ac_blocked(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_ext_priv *mlmeext; + struct mlme_ext_info *mlmeextinfo; + bool blocked = _FALSE; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlmeext = &iface->mlmeextpriv; + + /* check scan state */ + if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE + && mlmeext_scan_state(mlmeext) != SCAN_BACK_OP + ) { + blocked = _TRUE; + goto exit; + } + + if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP + && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME) + ) { + blocked = _TRUE; + goto exit; + } + } + +exit: + return blocked; +} + +void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms) +{ + sctx->timeout_ms = timeout_ms; + sctx->submit_time = rtw_get_current_time(); + init_completion(&sctx->done); + sctx->status = RTW_SCTX_SUBMITTED; +} + +int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg) +{ + int ret = _FAIL; + unsigned long expire; + int status = 0; + + expire = sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT; + if (!wait_for_completion_timeout(&sctx->done, expire)) { + /* timeout, do something?? */ + status = RTW_SCTX_DONE_TIMEOUT; + RTW_INFO("%s timeout: %s\n", __func__, msg); + } else + status = sctx->status; + + if (status == RTW_SCTX_DONE_SUCCESS) + ret = _SUCCESS; + + return ret; +} + +bool rtw_sctx_chk_waring_status(int status) +{ + switch (status) { + case RTW_SCTX_DONE_UNKNOWN: + case RTW_SCTX_DONE_BUF_ALLOC: + case RTW_SCTX_DONE_BUF_FREE: + + case RTW_SCTX_DONE_DRV_STOP: + case RTW_SCTX_DONE_DEV_REMOVE: + return _TRUE; + default: + return _FALSE; + } +} + +void rtw_sctx_done_err(struct submit_ctx **sctx, int status) +{ + if (*sctx) { + if (rtw_sctx_chk_waring_status(status)) + RTW_INFO("%s status:%d\n", __func__, status); + (*sctx)->status = status; + complete(&((*sctx)->done)); + *sctx = NULL; + } +} + +void rtw_sctx_done(struct submit_ctx **sctx) +{ + rtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS); +} + +void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status) +{ + struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; + + if (pxmitpriv->ack_tx) + rtw_sctx_done_err(&pack_tx_ops, status); + else + RTW_INFO("%s ack_tx not set\n", __func__); +} diff --git a/drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.c b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.c new file mode 100644 index 000000000000..1c05a2f592eb --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.c @@ -0,0 +1,5148 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* ************************************************************ + * Description: + * + * This file is for RTL8821C Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + + +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8821c_1ant glcoex_dm_8821c_1ant; +static struct coex_dm_8821c_1ant *coex_dm = &glcoex_dm_8821c_1ant; +static struct coex_sta_8821c_1ant glcoex_sta_8821c_1ant; +static struct coex_sta_8821c_1ant *coex_sta = &glcoex_sta_8821c_1ant; +static struct psdscan_sta_8821c_1ant gl_psd_scan_8821c_1ant; +static struct psdscan_sta_8821c_1ant *psd_scan = &gl_psd_scan_8821c_1ant; +static struct rfe_type_8821c_1ant gl_rfe_type_8821c_1ant; +static struct rfe_type_8821c_1ant *rfe_type = &gl_rfe_type_8821c_1ant; + +const char *const glbt_info_src_8821c_1ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8821c_1ant = 20170310; +u32 glcoex_ver_8821c_1ant = 0x12; +u32 glcoex_ver_btdesired_8821c_1ant = 0x11; + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8821c1ant_ + * ************************************************************ */ +u8 halbtc8821c1ant_bt_rssi_state(u8 level_num, u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = coex_sta->pre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_bt_rssi_state; + } + + if ((coex_sta->pre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_bt_rssi_state == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8821c1ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 index, IN u8 level_num, IN u8 rssi_thresh, IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = coex_sta->pre_wifi_rssi_state[index]; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return coex_sta->pre_wifi_rssi_state[index]; + } + + if ((coex_sta->pre_wifi_rssi_state[index] == BTC_RSSI_STATE_LOW) + || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_MEDIUM) || + (coex_sta->pre_wifi_rssi_state[index] == + BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + coex_sta->pre_wifi_rssi_state[index] = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8821c1ant_update_ra_mask(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 dis_rate_mask) +{ + coex_dm->cur_ra_mask = dis_rate_mask; + + if (force_exec || (coex_dm->pre_ra_mask != coex_dm->cur_ra_mask)) + btcoexist->btc_set(btcoexist, BTC_SET_ACT_UPDATE_RAMASK, + &coex_dm->cur_ra_mask); + coex_dm->pre_ra_mask = coex_dm->cur_ra_mask; +} + +void halbtc8821c1ant_auto_rate_fallback_retry(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + boolean wifi_under_b_mode = FALSE; + + coex_dm->cur_arfr_type = type; + + if (force_exec || (coex_dm->pre_arfr_type != coex_dm->cur_arfr_type)) { + switch (coex_dm->cur_arfr_type) { + case 0: /* normal mode */ + btcoexist->btc_write_4byte(btcoexist, 0x430, + coex_dm->backup_arfr_cnt1); + btcoexist->btc_write_4byte(btcoexist, 0x434, + coex_dm->backup_arfr_cnt2); + break; + case 1: + btcoexist->btc_get(btcoexist, + BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + if (wifi_under_b_mode) { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x01010101); + } else { + btcoexist->btc_write_4byte(btcoexist, + 0x430, 0x0); + btcoexist->btc_write_4byte(btcoexist, + 0x434, 0x04030201); + } + break; + default: + break; + } + } + + coex_dm->pre_arfr_type = coex_dm->cur_arfr_type; +} + +void halbtc8821c1ant_retry_limit(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_retry_limit_type = type; + + if (force_exec || + (coex_dm->pre_retry_limit_type != + coex_dm->cur_retry_limit_type)) { + switch (coex_dm->cur_retry_limit_type) { + case 0: /* normal mode */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + coex_dm->backup_retry_limit); + break; + case 1: /* retry limit=8 */ + btcoexist->btc_write_2byte(btcoexist, 0x42a, + 0x0808); + break; + default: + break; + } + } + + coex_dm->pre_retry_limit_type = coex_dm->cur_retry_limit_type; +} + +void halbtc8821c1ant_ampdu_max_time(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + coex_dm->cur_ampdu_time_type = type; + + if (force_exec || + (coex_dm->pre_ampdu_time_type != coex_dm->cur_ampdu_time_type)) { + switch (coex_dm->cur_ampdu_time_type) { + case 0: /* normal mode */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + coex_dm->backup_ampdu_max_time); + break; + case 1: /* AMPDU timw = 0x38 * 32us */ + btcoexist->btc_write_1byte(btcoexist, 0x456, + 0x38); + break; + default: + break; + } + } + + coex_dm->pre_ampdu_time_type = coex_dm->cur_ampdu_time_type; +} + +void halbtc8821c1ant_limited_tx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ra_mask_type, IN u8 arfr_type, + IN u8 retry_limit_type, IN u8 ampdu_time_type) +{ + switch (ra_mask_type) { + case 0: /* normal mode */ + halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, + 0x0); + break; + case 1: /* disable cck 1/2 */ + halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, + 0x00000003); + break; + case 2: /* disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 */ + halbtc8821c1ant_update_ra_mask(btcoexist, force_exec, + 0x0001f1f7); + break; + default: + break; + } + + halbtc8821c1ant_auto_rate_fallback_retry(btcoexist, force_exec, + arfr_type); + halbtc8821c1ant_retry_limit(btcoexist, force_exec, retry_limit_type); + halbtc8821c1ant_ampdu_max_time(btcoexist, force_exec, ampdu_time_type); +} + +void halbtc8821c1ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + +} + +void halbtc8821c1ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No query BT info because BT is disabled!\n"); + BTC_TRACE(trace_buf); + return; + } + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WL query BT info!!\n"); + BTC_TRACE(trace_buf); +} + +void halbtc8821c1ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, + cnt_autoslot_hang = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + /* to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS */ + /* if (! (btcoexist->btc_read_1byte(btcoexist, 0x76e) & 0x8) ) */ + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + + BTC_TRACE(trace_buf); + + if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->high_priority_rx >= 15) { + if (cnt_overhead < 3) + cnt_overhead++; + + if (cnt_overhead == 3) + coex_sta->is_hiPri_rx_overhead = TRUE; + + } else { + if (cnt_overhead > 0) + cnt_overhead--; + + if (cnt_overhead == 0) + coex_sta->is_hiPri_rx_overhead = FALSE; + } + } else + coex_sta->is_hiPri_rx_overhead = FALSE; + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 1150) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) + && (!coex_sta->c2h_bt_inquiry_page) + && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { + if (cnt_slave >= 2) { + bt_link_info->slave_role = TRUE; + cnt_slave = 2; + } else + cnt_slave++; + } else { + if (cnt_slave == 0) { + bt_link_info->slave_role = FALSE; + cnt_slave = 0; + } else + cnt_slave--; + } + + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = TRUE; + cnt_autoslot_hang = 2; + } else + cnt_autoslot_hang++; + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = FALSE; + cnt_autoslot_hang = 0; + } else + cnt_autoslot_hang--; + } + } + + if (bt_link_info->hid_only) { + if (coex_sta->low_priority_rx > 50) + coex_sta->is_hid_low_pri_tx_overhead = true; + else + coex_sta->is_hid_low_pri_tx_overhead = false; + } + + if (!coex_sta->bt_disabled) { + + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8821c1ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } + } + +} + +void halbtc8821c1ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ + s32 wifi_rssi = 0; + boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, + wifi_scan = FALSE; + boolean bt_idle = FALSE, wl_idle = FALSE; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, reg_val1, reg_val2, cck_cnt; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_VHT); + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; + + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + coex_sta->crc_ok_11n_vht; + + if ((coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) + || + (coex_dm->bt_status == BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = TRUE; + else + coex_sta->cck_lock = FALSE; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = FALSE; + else + coex_sta->cck_lock = TRUE; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = TRUE; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + +} + +void halbtc8821c1ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + boolean bt_busy = FALSE; + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = FALSE; + coex_sta->pan_exist = FALSE; + coex_sta->a2dp_exist = FALSE; + coex_sta->hid_exist = FALSE; + coex_sta->sco_exist = FALSE; + } else { /* connection exists */ + coex_sta->bt_link_exist = TRUE; + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { + coex_sta->pan_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { + coex_sta->a2dp_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { + coex_sta->hid_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = FALSE; + + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = TRUE; + bt_link_info->bt_link_exist = TRUE; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = TRUE; + else + bt_link_info->sco_only = FALSE; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = TRUE; + else + bt_link_info->a2dp_only = FALSE; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = TRUE; + else + bt_link_info->pan_only = FALSE; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = TRUE; + else + bt_link_info->hid_only = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8821C_1ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8821C_1ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = TRUE; + else + bt_busy = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); +} + +void halbtc8821c1ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = + 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ + /* h2c_parameter[0] = 0x0; */ + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + +} + +u8 halbtc8821c1ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u8 algorithm = BT_8821C_1ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP ==> SCO\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_HID; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_1ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +void halbtc8821c1ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8821c1ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8821c1ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8821c1ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == + coex_dm->cur_low_penalty_ra) + return; + } + + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + + +} + +void halbtc8821c1ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002, preval = 0x0; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + if (originalval != preval) { + + preval = originalval; + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_write_score_board: return for nochange\n"); + BTC_TRACE(trace_buf); + } +} + +void halbtc8821c1ant_read_score_board( + IN struct btc_coexist *btcoexist, + IN u16 *score_board_val +) +{ + + *score_board_val = (btcoexist->btc_read_2byte(btcoexist, + 0xaa)) & 0x7fff; +} + +void halbtc8821c1ant_post_state_to_bt( + IN struct btc_coexist *btcoexist, + IN u16 type, + IN boolean state +) +{ + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_post_state_to_bt: type = %d, state =%d\n", + type, state); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_write_score_board(btcoexist, (u16) type, state); +} + +boolean halbtc8821c1ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) +{ + static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE, + pre_bt_hs_on = FALSE, pre_bt_off = FALSE, + pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE, + pre_wifi_under_lps = FALSE; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0, + pre_bt_setup_link = FALSE; + boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE; + boolean wifi_connected = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + return TRUE; + } + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + + if (wifi_busy) + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, TRUE); + else + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, FALSE); + return TRUE; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return TRUE; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return TRUE; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return TRUE; + } + if (coex_sta->under_lps != pre_wifi_under_lps) { + pre_wifi_under_lps = coex_sta->under_lps; + if (coex_sta->under_lps == TRUE) + return TRUE; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return TRUE; + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return TRUE; + } + + if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) { + pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead; + return TRUE; + } + + if (pre_bt_setup_link != coex_sta->is_setupLink) { + pre_bt_setup_link = coex_sta->is_setupLink; + return TRUE; + } + } + + return FALSE; +} + +void halbtc8821c1ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE; + u16 u16tmp; + + /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ + halbtc8821c1ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 2) { + bt_disabled = TRUE; + bt_disable_cnt = 2; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) || (bt_disabled)) + halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + else + halbtc8821c1ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE); + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + } + +} + +void halbtc8821c1ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, + boolean isenable) +{ +#if BT_8821C_1ANT_COEX_DBG + static u8 bitVal[5] = {0, 0, 0, 0, 0}; + static boolean state = FALSE; + /* + if (state ==isenable) + return; + else + state = isenable; + */ + if (isenable) { + + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + + /* store original value */ + bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, + 0x66) & BIT(4)) >> 4; /*0x66[4] */ + bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, + 0x67) & BIT(0)); /*0x66[8] */ + bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, + 0x42) & BIT(3)) >> 3; /*0x40[19] */ + bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, + 0x65) & BIT(7)) >> 7; /*0x64[15] */ + bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, + 0x72) & BIT(2)) >> 2; /*0x70[18] */ + + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + 0x0); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + 0x0); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + 0x0); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + 0x0); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + 0x0); /*0x70[18] = 0 */ + + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + bitVal[0]); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + bitVal[1]); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + bitVal[2]); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + bitVal[3]); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + bitVal[4]); /*0x70[18] = 0 */ + } + +#endif +} + +u32 halbtc8821c1ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, + IN u16 reg_addr) +{ + u32 j = 0, delay_count = 0; + + /* wait for ready bit before access 0x1700 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else + break; + } + + btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); + + return btcoexist->btc_read_4byte(btcoexist, + 0x1708); /* get read data */ +} + +void halbtc8821c1ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, + IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +{ + u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0; + + if (bit_mask == 0x0) + return; + + if (bit_mask == 0xffffffff) { + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else + break; + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + reg_value); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /* read back register value before write */ + val = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else + break; + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + val); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + + } + +} + +void halbtc8821c1ant_ltecoex_enable(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 val; + + val = (enable) ? 1 : 0; + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, + val); /* 0x38[7] */ + +} + +void halbtc8821c1ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, + IN boolean wifi_control) +{ + u8 val; + + val = (wifi_control) ? 1 : 0; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, + val); /* 0x70[26] */ + +} + +void halbtc8821c1ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); + break; + case BT_8821C_1ANT_GNT_BLOCK_RFC: + val = (val << 14) | (val_orig & 0xffff3fff); + break; + case BT_8821C_1ANT_GNT_BLOCK_BB: + val = (val << 10) | (val_orig & 0xfffff3ff); + break; + } + + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c1ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_1ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); + break; + case BT_8821C_1ANT_GNT_BLOCK_RFC: + val = (val << 12) | (val_orig & 0xffffcfff); + break; + case BT_8821C_1ANT_GNT_BLOCK_BB: + val = (val << 8) | (val_orig & 0xfffffcff); + break; + } + + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c1ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_1ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8821C_1ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ + +} + +void halbtc8821c1ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u8 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_1ANT_LBTT_WL_BREAK_LTE: + reg_addr = 0xa8; + break; + case BT_8821C_1ANT_LBTT_BT_BREAK_LTE: + reg_addr = 0xac; + break; + case BT_8821C_1ANT_LBTT_LTE_BREAK_WL: + reg_addr = 0xb0; + break; + case BT_8821C_1ANT_LBTT_LTE_BREAK_BT: + reg_addr = 0xb4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c1ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ + +} + +void halbtc8821c1ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + +void halbtc8821c1ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8821c1ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + + halbtc8821c1ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8821c1ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + u32 break_table; + u8 select_table; + + coex_sta->coex_table_type = type; + + if (coex_sta->concurrent_rx_mode_on == TRUE) { + break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ + select_table = + 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + } else { + break_table = 0xffffff; + select_table = 0x3; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Table-%d **********\n", + coex_sta->coex_table_type); + BTC_TRACE(trace_buf); + + switch (type) { + case 0: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, + select_table); + break; + case 1: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 2: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xaa5a5a5a, 0xaa5a5a5a, break_table, + select_table); + break; + case 3: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 4: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 5: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, + select_table); + break; + case 6: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, + select_table); + break; + case 7: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xaa555555, 0xaa555555, break_table, + select_table); + break; + case 8: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaaaa5aaa, break_table, + select_table); + break; + case 9: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, + select_table); + break; + case 10: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0xaaaaaaaa, 0xaaaaaaaa, break_table, + select_table); + break; + case 11: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55a55555, 0x5aaa5a5a, break_table, + select_table); + break; + case 12: + halbtc8821c1ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5aaa5a5a, break_table, + select_table); + break; + default: + break; + } +} + +void halbtc8821c1ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) + h2c_parameter[0] |= BIT(0); /* function enable */ + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8821c1ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8821c1ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8821c1ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8821c1ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8821c1ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8821c1ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0x8, 0, 0, 0, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + /*halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8);*/ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +boolean halbtc8821c1ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = FALSE, result = TRUE; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + /* recover to original 32k low power setting */ + coex_sta->force_lps_ctrl = FALSE; + low_pwr_disable = FALSE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + + break; + case BTC_PS_LPS_ON: + coex_sta->force_lps_ctrl = TRUE; + halbtc8821c1ant_ps_tdma_check_for_power_save_state( + btcoexist, TRUE); + halbtc8821c1ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = TRUE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + + break; + case BTC_PS_LPS_OFF: + coex_sta->force_lps_ctrl = TRUE; + halbtc8821c1ant_ps_tdma_check_for_power_save_state( + btcoexist, FALSE); + result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + + break; + default: + break; + } + + return result; +} + +void halbtc8821c1ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = FALSE, result = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = TRUE; + else + coex_sta->is_tdma_btautoslot = FALSE; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_set_fw_pstdma == FW for 1Ant AP mode\n"); + BTC_TRACE(trace_buf); + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8821c1ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, + 0x0); + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_set_fw_pstdma == Force LPS Leave (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + + if (!halbtc8821c1ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + result = TRUE; + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_set_fw_pstdma == native power save (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, + 0x0); + } + + coex_sta->is_set_ps_state_fail = result; + + if (!coex_sta->is_set_ps_state_fail) { + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + + } else { + coex_sta->cnt_set_ps_state_fail++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c1ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n", + coex_sta->cnt_set_ps_state_fail); + BTC_TRACE(trace_buf); + } +} + +void halbtc8821c1ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = FALSE; + static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; + static boolean pre_wifi_busy = FALSE; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (wifi_busy != pre_wifi_busy) { + force_exec = TRUE; + pre_wifi_busy = wifi_busy; + } + + /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + if (bt_link_info->slave_role) + psTdmaByte4Modify = 0x1; + else + psTdmaByte4Modify = 0x0; + + if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + force_exec = TRUE; + pre_psTdmaByte4Modify = psTdmaByte4Modify; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + (coex_dm->cur_ps_tdma_on ? "on" : "off"), + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + return; + } + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + if (turn_on) { + switch (type) { + default: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x11); + break; + + case 3: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50); + break; + case 4: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x21, 0x03, 0x10, 0x50); + break; + case 5: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x15, 0x03, 0x11, 0x11); + break; + case 6: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x20, 0x03, 0x11, 0x10); + break; + case 7: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 8: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 9: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 10: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 11: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x25, 0x03, 0x11, 0x10 | + psTdmaByte4Modify); + break; + case 12: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 13: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x07, 0x10, 0x54 | + psTdmaByte4Modify); + break; + case 14: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x15, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 15: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x20, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 16: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15 | + psTdmaByte4Modify); + break; + case 17: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x14 | + psTdmaByte4Modify); + break; + case 18: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x30, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 19: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x15, 0x03, 0x11, 0x10); + break; + case 20: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x30, 0x03, 0x11, 0x10); + break; + case 22: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10); + break; + case 27: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x15); + break; + case 32: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x11); + break; + case 33: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x35, 0x03, 0x11, 0x10); + break; + case 57: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 58: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x51, 0x10, 0x03, 0x10, 0x50 | + psTdmaByte4Modify); + break; + case 67: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0x61, 0x10, 0x03, 0x11, 0x10 | + psTdmaByte4Modify); + break; + + /* 1-Ant to 2-Ant TDMA case */ + case 103: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x3a, 0x03, 0x70, 0x10); + break; + case 104: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x21, 0x03, 0x70, 0x10); + break; + case 105: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x15, 0x03, 0x71, 0x11); + break; + case 106: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x20, 0x03, 0x71, 0x11); + break; + case 107: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x10, 0x03, 0x70, 0x14 | + psTdmaByte4Modify); + break; + case 108: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x10, 0x03, 0x70, 0x14 | + psTdmaByte4Modify); + break; + case 113: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x25, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); + break; + case 114: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x15, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); + break; + case 115: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xd3, 0x20, 0x03, 0x70, 0x10 | + psTdmaByte4Modify); + break; + case 117: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x10, 0x03, 0x71, 0x14 | + psTdmaByte4Modify); + break; + case 119: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x15, 0x03, 0x71, 0x10); + break; + case 120: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x30, 0x03, 0x71, 0x10); + break; + case 121: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x30, 0x03, 0x71, 0x10); + break; + case 122: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x25, 0x03, 0x71, 0x10); + break; + case 132: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x35, 0x03, 0x71, 0x11); + break; + case 133: + halbtc8821c1ant_set_fw_pstdma(btcoexist, + 0xe3, 0x35, 0x03, 0x71, 0x10); + break; + + } + } else { + + /* disable PS tdma */ + switch (type) { + case 8: /* PTA Control */ + halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x8, + 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: /* Software control, Antenna at BT side */ + halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x0, 0x0); + break; + case 1: /* 2-Ant, 0x778=3, antenna control by antenna diversity */ + halbtc8821c1ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + } + } + + if (!coex_sta->is_set_ps_state_fail) { + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; + } +} + +void halbtc8821c1ant_set_int_block(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ +} + +void halbtc8821c1ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ +} + +void halbtc8821c1ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + boolean switch_polatiry_inverse = FALSE; + u8 regval_0xcb7 = 0, regval_0x64; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + + if (!rfe_type->ext_ant_switch_exist) + return; + + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_ant_switch_status == + coex_dm->cur_ext_ant_switch_status) + return; + } + + coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + + /* swap control polarity if use different switch control polarity*/ + /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ + /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + if (rfe_type->ext_ant_switch_ctrl_polarity) + switch_polatiry_inverse = !switch_polatiry_inverse; + + /* swap control polarity if 1-Ant at Aux */ + if (rfe_type->ant_at_main_port == FALSE) + switch_polatiry_inverse = !switch_polatiry_inverse; + + switch (pos_type) { + default: + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT: + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE: + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA: + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG: + if (!rfe_type->wlg_Locate_at_btg) + switch_polatiry_inverse = !switch_polatiry_inverse; + break; + } + + if (board_info->ant_div_cfg) + ctrl_type = BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + + switch (ctrl_type) { + default: + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == FALSE ? + 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == FALSE ? + 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x88); /* */ + + /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ + + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x1); /* 0x4c[23] = 1 */ + + regval_0x64 = (switch_polatiry_inverse == FALSE ? 0x0 : + 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, + regval_0x64); + break; + case BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x0); /* 0x4c[24] = 0 */ + + /* no setup required, because antenna switch control value by BT vendor 0xac[1:0] */ + break; + } + + /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ + if (ctrl_type == BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x0); /* PAPE 0x64[29] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x0); /* LNA_ON 0x64[28] = 0 */ + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x1); /* PAPE 0x64[29] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x1); /* LNA_ON 0x64[28] = 1 */ + } + +#if BT_8821C_1ANT_COEX_DBG + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", + u32tmp1, u32tmp2, u32tmp3); + BTC_TRACE(trace_buf); +#endif + +} + +void halbtc8821c1ant_set_rfe_type(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 1: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, WLG */ + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 2: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, BTG */ + rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ant_at_main_port = TRUE; + break; + case 3: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, WLG */ + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = FALSE; + break; + case 4: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, BTG */ + rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ant_at_main_port = FALSE; + break; + case 5: + rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 6: + rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 7: + rfe_type->ext_ant_switch_exist = TRUE; /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT; + rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ant_at_main_port = TRUE; + break; + } +} + +void halbtc8821c1ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 cnt_bt_cal_chk = 0; + boolean is_in_mp_mode = FALSE; + u8 u8tmp = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u16 u16tmp1 = 0; + + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = TRUE; + coex_sta->gnt_error_cnt++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Ant Setup) 0x38= 0x%x\n", + u32tmp1); + BTC_TRACE(trace_buf); + } + +#if BT_8821C_1ANT_COEX_DBG + + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + + coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Ant Setup) pre_ant_pos_type = 0x%x, cur_ant_pos_type = 0x%x\n", + coex_dm->pre_ant_pos_type, + coex_dm->cur_ant_pos_type); + BTC_TRACE(trace_buf); + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) + return; + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + + switch (phase) { + case BT_8821C_1ANT_PHASE_COEX_POWERON: + + /* set Path control owner to WL at initial step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_1ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = FALSE; + + break; + case BT_8821C_1ANT_PHASE_COEX_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + while (cnt_bt_cal_chk <= 20) { + u8tmp = btcoexist->btc_read_1byte( + btcoexist, + 0x49c); + cnt_bt_cal_chk++; + if (u8tmp & BIT(1)) { + BTC_SPRINTF( + trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE( + trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF( + trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE( + trace_buf); + break; + } + } + + /* set Path control owner to WL at initial step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW low */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = FALSE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + break; + case BT_8821C_1ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c1ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_1ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set Path control owner to WL at initial step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Low */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = FALSE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_WIFI; + + break; + case BT_8821C_1ANT_PHASE_WLAN_OFF: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to BT */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_BTSIDE); + + /* Set Ext Ant Switch to BT control at wifi off step */ + halbtc8821c1ant_set_ext_ant_switch(btcoexist, + FORCE_EXEC, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); + + coex_sta->run_time_state = FALSE; + break; + case BT_8821C_1ANT_PHASE_2G_RUNTIME: + + while (cnt_bt_cal_chk <= 20) { + /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ + u8tmp = btcoexist->btc_read_1byte( + btcoexist, + 0x49c); + + cnt_bt_cal_chk++; + if (u8tmp & BIT(0)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else if (u8tmp & BIT(1)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* set Path control owner to WL at runtime step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to PTA */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_SIG_STA_SET_BY_HW); + + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_SIG_STA_SET_BY_HW); + + coex_sta->run_time_state = TRUE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (rfe_type->wlg_Locate_at_btg) + ant_pos_type = + BTC_ANT_PATH_WIFI; + else + ant_pos_type = BTC_ANT_PATH_PTA; + } + + if (rfe_type->wlg_Locate_at_btg) + halbtc8821c1ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); + else + halbtc8821c1ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); + + break; + case BT_8821C_1ANT_PHASE_5G_RUNTIME: + + /* set Path control owner to WL at runtime step */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_1ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to SW Hi */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = TRUE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + /* if (rfe_type->ext_band_switch_exist) + ant_pos_type = BTC_ANT_PATH_PTA; + else */ + ant_pos_type = + BTC_ANT_PATH_WIFI5G; + } + + halbtc8821c1ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); + + break; + case BT_8821C_1ANT_PHASE_BTMPMODE: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c1ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to WL */ + halbtc8821c1ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Lo */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = FALSE; + + /* Set Ext Ant Switch to BT side at BT MP mode */ + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + break; + case BT_8821C_1ANT_PHASE_ANTENNA_DET: + halbtc8821c1ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_1ANT_PCO_WLSIDE); + + /* set GNT_BT to high */ + halbtc8821c1ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to high */ + halbtc8821c1ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_1ANT_GNT_BLOCK_RFC_BB, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) + ant_pos_type = BTC_ANT_PATH_BT; + + coex_sta->run_time_state = FALSE; + + break; + } + + if (phase != BT_8821C_1ANT_PHASE_WLAN_OFF) { + switch (ant_pos_type) { + case BTC_ANT_PATH_WIFI: + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG); + break; + case BTC_ANT_PATH_WIFI5G + : + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA); + break; + case BTC_ANT_PATH_BT: + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT); + break; + default: + case BTC_ANT_PATH_PTA: + halbtc8821c1ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE); + break; + } + + } + +#if BT_8821C_1ANT_COEX_DBG + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); + + BTC_TRACE(trace_buf); +#endif +} + +boolean halbtc8821c1ant_is_common_action(IN struct btc_coexist *btcoexist) +{ + boolean common = FALSE, wifi_connected = FALSE, wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_connected && + BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = TRUE; + } else if (wifi_connected && + (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT non connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = TRUE; + } else if (!wifi_connected && + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = TRUE; + } else if (wifi_connected && + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi connected + BT connected-idle!!\n"); + BTC_TRACE(trace_buf); + + common = TRUE; + } else if (!wifi_connected && + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE != + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi non connected-idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + + common = TRUE; + } else { + if (wifi_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Busy + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi Connected-Idle + BT Busy!!\n"); + BTC_TRACE(trace_buf); + } + + common = FALSE; + } + + return common; +} + +/* ********************************************* + * + * Software Coex Mechanism start + * + * ********************************************* */ + +/* ********************************************* + * + * Non-Software Coex Mechanism start + * + * ********************************************* */ +void halbtc8821c1ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c1ant_action_bt_hs(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 5); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8821c1ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + if (coex_sta->is_bt_multi_link == TRUE) + return; + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c1ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + boolean wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 3); + + } else { /* if wl busy */ + + if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 33); + } else { + + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 32); + + } + + } + +} + +void halbtc8821c1ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = FALSE, wifi_busy = FALSE, + bt_busy = FALSE; + boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 17); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); + } else if ((!wifi_connected) && (!wifi_scan)) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (bt_link_info->pan_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } +} + +void halbtc8821c1ant_action_bt_sco_hid_only_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = FALSE, wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (bt_link_info->sco_exist) { + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 5); + } else { + + if (coex_sta->is_hid_low_pri_tx_overhead) { + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 18); + } else if (wifi_bw == 0) { /* if 11bg mode */ + + if (coex_sta->is_bt_multi_link) { + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 11); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11); + } else { + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11); + } + } else { + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11); + } + } +} + +void halbtc8821c1ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +{ + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_1ANT_PHASE_5G_RUNTIME); +} + +void halbtc8821c1ant_action_wifi_only(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 10); +} + +void halbtc8821c1ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 5); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); +} + +void halbtc8821c1ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + if ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 7); + else if (!bt_link_info->pan_exist) + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 2); +} + +void halbtc8821c1ant_action_wifi_linkscan_process(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (bt_link_info->pan_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 27); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } else { + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } + +} + +void halbtc8821c1ant_action_wifi_connected_bt_acl_busy(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy_level = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (!bt_link_info->pan_exist) && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 12); + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + } else if (bt_link_info->a2dp_only) { /* A2DP */ + + halbtc8821c1ant_ps_tdma(btcoexist, + NORMAL_EXEC, TRUE, 7); + + if (wifi_turbo) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (((bt_link_info->a2dp_exist) && + (bt_link_info->pan_exist)) || + (bt_link_info->hid_exist && bt_link_info->a2dp_exist && + bt_link_info->pan_exist)) { /* A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) */ + + if (wifi_busy) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 13); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 14); + + if (bt_link_info->hid_exist) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { /* HID+A2DP */ + + if (wifi_bw == 0) {/* if 11bg mode */ + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 12); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 8); + } else { + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, + 8); + } + + } else if ((bt_link_info->pan_only) + || (bt_link_info->hid_exist && bt_link_info->pan_exist)) { + /* PAN(OPP,FTP), HID+PAN(OPP,FTP) */ + + if (!wifi_busy) + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 4); + else + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 3); + + if (bt_link_info->hid_exist) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 1); + else if (wifi_turbo) + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + else + halbtc8821c1ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + } else { + /* BT no-profile busy (0x9) */ + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 33); + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + } + +} + +void halbtc8821c1ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + /* tdma and coex table */ + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c1ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_busy = FALSE; + boolean wifi_under_5g = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CoexForWifiConnect()===>\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + if (BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) { + + if (bt_link_info->hid_only) /* HID only */ + halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); + else + halbtc8821c1ant_action_wifi_connected_bt_acl_busy( + btcoexist); + + } else if ((BT_8821C_1ANT_BT_STATUS_SCO_BUSY == + coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == + coex_dm->bt_status)) + halbtc8821c1ant_action_bt_sco_hid_only_busy(btcoexist); + else + halbtc8821c1ant_action_bt_idle(btcoexist); + +} + +void halbtc8821c1ant_run_sw_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + + algorithm = halbtc8821c1ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + + if (!halbtc8821c1ant_is_common_action(btcoexist)) { + switch (coex_dm->cur_algorithm) { + case BT_8821C_1ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_sco(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_hid(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_a2dp(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_a2dp_pan_hs(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_edr(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HS mode.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_hs(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_edr_a2dp(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_pan_edr_hid(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_hid_a2dp_pan_edr(btcoexist); */ + break; + case BT_8821C_1ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_action_hid_a2dp(btcoexist); */ + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + /* halbtc8821c1ant_coex_all_off(btcoexist); */ + break; + } + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + } +} + +void halbtc8821c1ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean wifi_connected = FALSE, bt_hs_on = FALSE; + boolean increase_scan_dev_num = FALSE; + boolean bt_ctrl_agg_buf_size = FALSE; + boolean miracast_plus_bt = FALSE, wifi_under_5g = FALSE; + u8 agg_buf_size = 5; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0, wifi_bw; + u8 iot_peer = BTC_IOT_PEER_UNKNOWN; + boolean scan = FALSE, link = FALSE, roam = FALSE, under_4way = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if ((coex_sta->under_lps) && + (coex_dm->bt_status != BT_8821C_1ANT_BT_STATUS_ACL_BUSY)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_wifi_native_lps(btcoexist); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = FALSE !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + } + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_whql_test(btcoexist); + return; + } + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_wifi_only(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_inquiry(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_relink(btcoexist); + return; + } + + if ((BT_8821C_1ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + increase_scan_dev_num = TRUE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, + &increase_scan_dev_num); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = TRUE; + else + miracast_plus_bt = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); + } else + halbtc8821c1ant_action_wifi_multi_port(btcoexist); + + return; + } else { + + miracast_plus_bt = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + } + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if ((bt_link_info->bt_link_exist) && (wifi_connected)) { + + btcoexist->btc_get(btcoexist, BTC_GET_U1_IOT_PEER, &iot_peer); + + if (BTC_IOT_PEER_CISCO == iot_peer) { + + if (BTC_WIFI_BW_HT40 == wifi_bw) + halbtc8821c1ant_limited_rx(btcoexist, + NORMAL_EXEC, FALSE, TRUE, 0x10); + else + halbtc8821c1ant_limited_rx(btcoexist, + NORMAL_EXEC, FALSE, TRUE, 0x8); + } + } + + halbtc8821c1ant_run_sw_coexist_mechanism( + btcoexist); /* just print debug message */ + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_hs(btcoexist); + return; + } + + if ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is idle\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_action_bt_idle(btcoexist); + return; + } + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_connected(btcoexist); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under not-connected!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_not_connected(btcoexist); + } +} + +void halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + /* force to reset coex mechanism */ + halbtc8821c1ant_low_penalty_ra(btcoexist, FORCE_EXEC, FALSE); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + coex_sta->cnt_RoleSwitch = 0; + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; + + halbtc8821c1ant_query_bt_info(btcoexist); +} + +void halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean back_up, IN boolean wifi_only) +{ + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u16 u16tmp1 = 0; + u8 i; + struct btc_board_info *board_info = &btcoexist->board_info; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 1Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex],(Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->isolation_btween_wb = BT_8821C_1ANT_DEFAULT_ISOLATION; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + coex_sta->is_set_ps_state_fail = FALSE; + coex_sta->cnt_set_ps_state_fail = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; + + /* Setup RF front end type */ + halbtc8821c1ant_set_rfe_type(btcoexist); + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* BT report packet sample rate */ + btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + + /* Init 0x778 = 0x1 for 1-Ant */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* Enable PTA (3-wire function form BT side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + + /* Enable PTA (tx/rx signal form WiFi side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + + /* set GNT_BT=1 for coex table select both */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + + halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, TRUE); + + /* PTA parameter */ + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 8); + + halbtc8821c1ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + psd_scan->ant_det_is_ant_det_available = TRUE; + + /* Antenna config */ + if (coex_sta->is_rf_state_off) { + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + + btcoexist->stop_coex_dm = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** halbtc8821c1ant_init_hw_config (RF Off)**********\n"); + BTC_TRACE(trace_buf); + } else if (wifi_only) { + coex_sta->concurrent_rx_mode_on = FALSE; + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_WIFI, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLANONLY_INIT); + + btcoexist->stop_coex_dm = TRUE; + } else { + /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + + coex_sta->concurrent_rx_mode_on = TRUE; + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ + + /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_COEX_INIT); + + btcoexist->stop_coex_dm = FALSE; + } + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); + +} + +/* ************************************************************ + * work around function start with wa_halbtc8821c1ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8821c1ant_ + * ************************************************************ */ +void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + u32 value = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8821c 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + (board_info->btdm_ant_det_finish ? "Yes" : "No"), + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = FALSE; + psd_scan->ant_det_is_ant_det_available = FALSE; + + /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + + /* Set Antenna Path to BT side */ + /* Check efuse 0xc3[6] for Single Antenna Path */ + if (board_info->single_ant_path == 0) { + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + u8tmp = 1; + } else if (board_info->single_ant_path == 1) { + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + u8tmp = 0; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", + board_info->single_ant_path , board_info->btdm_ant_pos); + BTC_TRACE(trace_buf); + + /* Setup RF front end type */ + halbtc8821c1ant_set_rfe_type(btcoexist); + + /* Set Antenna Path to BT side */ + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_COEX_POWERON); + + /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + halbtc8821c1ant_enable_gnt_to_gpio(btcoexist, TRUE); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x\n", + halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_4byte(btcoexist, 0xcb4)); + BTC_TRACE(trace_buf); + +} + +void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ +} + +void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8821c1ant_init_hw_config(btcoexist, TRUE, wifi_only); +} + +void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + halbtc8821c1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_stack_info *stack_info = &btcoexist->stack_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, bt_info_ext, ps_tdma_case = 0; + u16 u16tmp[4]; + u32 u32tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + static u8 cnt = 0; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + if (btcoexist->stop_coex_dm) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + if (board_info->btdm_ant_det_finish) { + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); + CL_PRINTF(cli_buf); + } + } + + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = ((coex_sta->bt_coex_supported_version & 0xff00) >> 8); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821c_1ant, glcoex_ver_8821c_1ant, + glcoex_ver_btdesired_8821c_1ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8821c_1ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "AFH Map to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : + "A2DP,") : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", "Profiles"); + + CL_PRINTF(cli_buf); + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_RoleSwitch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8821c1ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + + for (i = 0; i < BT_INFO_SRC_8821C_1ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8821c_1ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanisms] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Mechanisms]============"); + + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s)", + "TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off")); + + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_ctrl) ? "On" : "Off"), + ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), + coex_sta->cnt_set_ps_state_fail); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE; + + if (lte_coex_on) { + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8821c1ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off") , + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), + (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", + "0xcb0/0xcb4/0xcb8[23:16]", + u32tmp[0], u32tmp[1], u8tmp[0], + ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "4c[24:23]/64[0]/4c6[4]/40[5]", + (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", + "0x550/0x522/4-RxAGC/0xc50", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11ac", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_Err CCK/11g/11n/11ac", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + +void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = TRUE; + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + FALSE); + + halbtc8821c1ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + + halbtc8821c1ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_init_hw_config(btcoexist, FALSE, FALSE); + halbtc8821c1ant_init_coex_dm(btcoexist); + + coex_sta->under_ips = FALSE; + } +} + +void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + static boolean pre_force_lps_on = FALSE; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = TRUE; + + if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + pre_force_lps_on = TRUE; + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, TRUE); + } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + pre_force_lps_on = FALSE; + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, FALSE); + } + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = FALSE; + + /* Write WL "Active" in Score-board for LPS off */ + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, TRUE); + + if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl)) + halbtc8821c1ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = FALSE; + boolean wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + coex_sta->freeze_coexrun_by_btinfo = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (wifi_connected) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL connected before SCAN\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL is not connected before SCAN\n"); + + BTC_TRACE(trace_buf); + + halbtc8821c1ant_query_bt_info(btcoexist); + + if (BTC_SCAN_START == type) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + TRUE); + + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (5g)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (2g)\n"); + BTC_TRACE(trace_buf); + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + return; + } + + if (BTC_SCAN_START_2G == type) { + + if (!wifi_connected) + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + TRUE); + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + } else { + + coex_sta->wifi_is_high_pri_task = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + boolean wifi_connected = FALSE, bt_hs_on = FALSE; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = FALSE; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + coex_sta->switch_band_notify_to = type; + + if (type == BTC_SWITCH_TO_5G) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 5G\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + + } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 2G\n"); + BTC_TRACE(trace_buf); + + ex_halbtc8821c1ant_scan_notify(btcoexist, + BTC_SCAN_START_2G); + } + + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; +} + +void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + TRUE); + + if ((BTC_ASSOCIATE_5G_START == type) || + (BTC_ASSOCIATE_5G_FINISH == type)) { + + if (BTC_ASSOCIATE_5G_START == type) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G start\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G finish\n"); + + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) { + + coex_sta->wifi_is_high_pri_task = TRUE; + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify (2G)\n"); + BTC_TRACE(trace_buf); + + coex_dm->arp_cnt = 0; + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + + /* To keep TDMA case during connect process, + to avoid changed by Btinfo and runcoexmechanism */ + coex_sta->freeze_coexrun_by_btinfo = TRUE; + } else { + + coex_sta->wifi_is_high_pri_task = FALSE; + coex_sta->freeze_coexrun_by_btinfo = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_under_b_mode = FALSE, wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (BTC_MEDIA_CONNECT == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF, + TRUE); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + /* Force antenna setup for no scan result issue */ + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + /* btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x10); */ /*CCK Tx */ + /* btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x10); */ /*CCK Rx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + coex_dm->backup_arfr_cnt1 = btcoexist->btc_read_4byte(btcoexist, + 0x430); + coex_dm->backup_arfr_cnt2 = btcoexist->btc_read_4byte(btcoexist, + 0x434); + coex_dm->backup_retry_limit = btcoexist->btc_read_2byte( + btcoexist, 0x42a); + coex_dm->backup_ampdu_max_time = btcoexist->btc_read_1byte( + btcoexist, 0x456); + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE, FALSE); + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + coex_sta->cck_ever_lock = FALSE; + } + + halbtc8821c1ant_update_wifi_channel_info(btcoexist, type); + +} + +void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean under_4way = FALSE, wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_action_wifi_under5g(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ---- under_4way!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + } else if (BTC_PACKET_ARP == type) { + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + } + + if (coex_sta->wifi_is_high_pri_task) { + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, TRUE); + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i, rsp_source = 0; + boolean wifi_connected = FALSE; + boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE, + wifi_busy = FALSE; + static boolean is_scoreboard_scan = FALSE; + + if (psd_scan->is_AntDet_running == TRUE) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], bt_info_notify return for AntDet is running\n"); + BTC_TRACE(trace_buf); + return; + } + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8821C_1ANT_MAX) + rsp_source = BT_INFO_SRC_8821C_1ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + + if (BT_INFO_SRC_8821C_1ANT_WIFI_FW != rsp_source) { + + /* if 0xff, it means BT is under WHCK test */ + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE : + FALSE); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE : + FALSE); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE : + FALSE); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? TRUE : FALSE); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? TRUE : FALSE); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + TRUE : FALSE); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8821C_1ANT_B_INQ_PAGE) ? TRUE : FALSE); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0); + + coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? + TRUE : FALSE; + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; + + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; + + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = TRUE; + coex_sta->bt_relink_downcount = 2; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link start in BT info!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->is_setupLink = FALSE; + coex_sta->bt_relink_downcount = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop in BT info!!\n"); + BTC_TRACE(trace_buf); + } + + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_info_ext & BIT(6)) + coex_sta->cnt_RoleSwitch++; + + if (coex_sta->bt_info_ext & BIT(7)) + coex_sta->is_bt_multi_link = TRUE; + else + coex_sta->is_bt_multi_link = FALSE; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + + is_scoreboard_scan = TRUE; + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, TRUE); + + } else + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, FALSE); + + } else { + if (is_scoreboard_scan) { + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_SCAN, FALSE); + is_scoreboard_scan = FALSE; + } + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + halbtc8821c1ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); + else + halbtc8821c1ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); + } + + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c1ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, FALSE); + } + } + + } + + if ((coex_sta->bt_info_ext & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + + } + + halbtc8821c1ant_update_bt_link_info(btcoexist); + + halbtc8821c1ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = FALSE; + coex_sta->is_rf_state_off = FALSE; + } else if (BTC_RF_OFF == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + FALSE); + + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + + btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = TRUE; + } +} + +void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + FALSE); + + halbtc8821c1ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + + halbtc8821c1ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + + halbtc8821c1ant_ignore_wlan_act(btcoexist, FORCE_EXEC, TRUE); + + ex_halbtc8821c1ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + btcoexist->stop_coex_dm = TRUE; +} + +void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + boolean wifi_under_5g = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_post_state_to_bt(btcoexist, + BT_8821C_1ANT_SCOREBOARD_ACTIVE | + BT_8821C_1ANT_SCOREBOARD_ONOFF | + BT_8821C_1ANT_SCOREBOARD_SCAN | + BT_8821C_1ANT_SCOREBOARD_UNDERTEST, + FALSE); + + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + + if (wifi_under_5g) + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_5G_RUNTIME); + else + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_1ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8821c1ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_1ANT_PHASE_WLAN_OFF); + } + + btcoexist->stop_coex_dm = TRUE; + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + btcoexist->stop_coex_dm = FALSE; + } +} + +void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], *****************Coex DM Reset*****************\n"); + BTC_TRACE(trace_buf); + + halbtc8821c1ant_init_hw_config(btcoexist, FALSE, FALSE); + halbtc8821c1ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist) +{ + + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = FALSE; + u16 bt_scoreboard_val = 0; + boolean bt_relink_finish = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* Periodical *************\n"); + BTC_TRACE(trace_buf); + +#if (BT_AUTO_REPORT_ONLY_8821C_1ANT == 0) + halbtc8821c1ant_query_bt_info(btcoexist); + +#endif + + halbtc8821c1ant_monitor_bt_ctr(btcoexist); + halbtc8821c1ant_monitor_wifi_ctr(btcoexist); + + halbtc8821c1ant_monitor_bt_enable_disable(btcoexist); + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) { + coex_sta->is_setupLink = FALSE; + bt_relink_finish = TRUE; + } + } + + /* for 4-way, DHCP, EAPOL packet */ + if (coex_sta->specific_pkt_period_cnt > 0) { + + coex_sta->specific_pkt_period_cnt--; + + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) + coex_sta->wifi_is_high_pri_task = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ***************** Hi-Pri Task = %s\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); + BTC_TRACE(trace_buf); + + } + + if (halbtc8821c1ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish) + || (coex_sta->is_set_ps_state_fail)) + halbtc8821c1ant_run_coexist_mechanism(btcoexist); + +} + +/*#pragma optimize( "", off )*/ +void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + +} + +void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ + +} + +void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + +} + +void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + +} + + + diff --git a/drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.h b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.h new file mode 100644 index 000000000000..d9906b722600 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c1ant.h @@ -0,0 +1,461 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + + + +/* ******************************************* + * The following is for 8821C 1ANT BT Co-exist definition + * ******************************************* */ +#define BT_8821C_1ANT_COEX_DBG 0 +#define BT_AUTO_REPORT_ONLY_8821C_1ANT 1 + +#define BT_INFO_8821C_1ANT_B_FTP BIT(7) +#define BT_INFO_8821C_1ANT_B_A2DP BIT(6) +#define BT_INFO_8821C_1ANT_B_HID BIT(5) +#define BT_INFO_8821C_1ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8821C_1ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8821C_1ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8821C_1ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8821C_1ANT_B_CONNECTION BIT(0) + +#define BT_INFO_8821C_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT(0))) ? TRUE : FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8821C_1ANT 2 + +#define BT_8821C_1ANT_WIFI_NOISY_THRESH 30 /* max: 255 */ +#define BT_8821C_1ANT_DEFAULT_ISOLATION 15 /* unit: dB */ + +/* for Antenna detection */ +#define BT_8821C_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8821C_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 +#define BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT 35 +#define BT_8821C_1ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8821C_1ANT_ANTDET_SWEEPPOINT_DELAY 60000 +#define BT_8821C_1ANT_ANTDET_ENABLE 0 +#define BT_8821C_1ANT_ANTDET_BTTXTIME 100 +#define BT_8821C_1ANT_ANTDET_BTTXCHANNEL 39 +#define BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT 50 + +#define BT_8821C_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + +enum bt_8821c_1ant_signal_state { + BT_8821C_1ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8821C_1ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8821C_1ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8821C_1ANT_SIG_STA_MAX +}; + +enum bt_8821c_1ant_path_ctrl_owner { + BT_8821C_1ANT_PCO_BTSIDE = 0x0, + BT_8821C_1ANT_PCO_WLSIDE = 0x1, + BT_8821C_1ANT_PCO_MAX +}; + +enum bt_8821c_1ant_gnt_ctrl_type { + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8821C_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8821C_1ANT_GNT_TYPE_MAX +}; + +enum bt_8821c_1ant_gnt_ctrl_block { + BT_8821C_1ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8821C_1ANT_GNT_BLOCK_RFC = 0x1, + BT_8821C_1ANT_GNT_BLOCK_BB = 0x2, + BT_8821C_1ANT_GNT_BLOCK_MAX +}; + +enum bt_8821c_1ant_lte_coex_table_type { + BT_8821C_1ANT_CTT_WL_VS_LTE = 0x0, + BT_8821C_1ANT_CTT_BT_VS_LTE = 0x1, + BT_8821C_1ANT_CTT_MAX +}; + +enum bt_8821c_1ant_lte_break_table_type { + BT_8821C_1ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8821C_1ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8821C_1ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8821C_1ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8821C_1ANT_LBTT_MAX +}; + +enum bt_info_src_8821c_1ant { + BT_INFO_SRC_8821C_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821C_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821C_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821C_1ANT_MAX +}; + +enum bt_8821c_1ant_bt_status { + BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821C_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821C_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821C_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821C_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821C_1ANT_BT_STATUS_MAX +}; + +enum bt_8821c_1ant_wifi_status { + BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821C_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_SPECIFIC_PKT = 0x3, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8821C_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8821C_1ANT_WIFI_STATUS_MAX +}; + +enum bt_8821c_1ant_coex_algo { + BT_8821C_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821C_1ANT_COEX_ALGO_SCO = 0x1, + BT_8821C_1ANT_COEX_ALGO_HID = 0x2, + BT_8821C_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8821C_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821C_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821C_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8821C_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821C_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821C_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821C_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821C_1ANT_COEX_ALGO_MAX = 0xb, +}; + +enum bt_8821c_1ant_ext_ant_switch_type { + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, + BT_8821C_1ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, + BT_8821C_1ANT_EXT_ANT_SWITCH_NONE = 0x2, + BT_8821C_1ANT_EXT_ANT_SWITCH_MAX +}; + +enum bt_8821c_1ant_ext_ant_switch_ctrl_type { + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8821C_1ANT_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8821c_1ant_ext_ant_switch_pos_type { + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_BT = 0x0, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLG = 0x1, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_WLA = 0x2, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_NOCARE = 0x3, + BT_8821C_1ANT_EXT_ANT_SWITCH_TO_MAX +}; + +enum bt_8821c_1ant_ext_band_switch_pos_type { + BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, + BT_8821C_1ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, + BT_8821C_1ANT_EXT_BAND_SWITCH_TO_MAX +}; + +enum bt_8821c_1ant_int_block { + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, + BT_8821C_1ANT_INT_BLOCK_SWITCH_TO_MAX +}; + +enum bt_8821c_1ant_phase { + BT_8821C_1ANT_PHASE_COEX_INIT = 0x0, + BT_8821C_1ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8821C_1ANT_PHASE_WLAN_OFF = 0x2, + BT_8821C_1ANT_PHASE_2G_RUNTIME = 0x3, + BT_8821C_1ANT_PHASE_5G_RUNTIME = 0x4, + BT_8821C_1ANT_PHASE_BTMPMODE = 0x5, + BT_8821C_1ANT_PHASE_ANTENNA_DET = 0x6, + BT_8821C_1ANT_PHASE_COEX_POWERON = 0x7, + BT_8821C_1ANT_PHASE_MAX +}; + +enum bt_8821c_1ant_Scoreboard { + BT_8821C_1ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8821C_1ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8821C_1ANT_SCOREBOARD_SCAN = BIT(2), + BT_8821C_1ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8821C_1ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + +struct coex_dm_8821c_1ant { + /* hw setting */ + u32 pre_ant_pos_type; + u32 cur_ant_pos_type; + /* fw mechanism */ + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + /* sw mechanism */ + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + u32 backup_arfr_cnt1; /* Auto Rate Fallback Retry cnt */ + u32 backup_arfr_cnt2; /* Auto Rate Fallback Retry cnt */ + u16 backup_retry_limit; + u8 backup_ampdu_max_time; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + u32 pre_ra_mask; + u32 cur_ra_mask; + u8 pre_arfr_type; + u8 cur_arfr_type; + u8 pre_retry_limit_type; + u8 cur_retry_limit_type; + u8 pre_ampdu_time_type; + u8 cur_ampdu_time_type; + u32 arp_cnt; + + u32 pre_ext_ant_switch_status; + u32 cur_ext_ant_switch_status; + + u8 pre_ext_band_switch_status; + u8 cur_ext_band_switch_status; + + u8 pre_int_block_status; + u8 cur_int_block_status; + + u8 error_condition; +}; + +struct coex_sta_8821c_1ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + u8 num_of_profile; + + boolean under_lps; + boolean under_ips; + u32 specific_pkt_period_cnt; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hiPri_rx_overhead; + s8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_INFO_SRC_8821C_1ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_1ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + boolean c2h_bt_page; /* Add for win8.1 page out issue */ + boolean wifi_is_high_pri_task; /* Add for win8.1 page out issue */ + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + u8 coex_table_type; + + boolean force_lps_ctrl; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + + u8 a2dp_bit_pool; + u8 cut_version; + boolean acl_busy; + boolean bt_create_connection; + + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; + + u8 switch_band_notify_to; + boolean is_rf_state_off; + + boolean is_hid_low_pri_tx_overhead; + boolean is_bt_multi_link; + boolean is_bt_a2dp_sink; + boolean is_set_ps_state_fail; + u8 cnt_set_ps_state_fail; +}; + +#define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_DPDT 0 +#define BT_8821C_1ANT_EXT_BAND_SWITCH_USE_SPDT 1 + +struct rfe_type_8821c_1ant { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + + boolean ext_band_switch_exist; + u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_band_switch_ctrl_polarity; + + boolean ant_at_main_port; + + boolean wlg_Locate_at_btg; /* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */ + + boolean ext_ant_switch_diversity; /* If diversity on */ +}; + +#define BT_8821C_1ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8821C_1ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8821C_1ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8821c_1ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8821C_1ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8821C_1ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_max_value2; + u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ + u32 psd_loop_max_value[BT_8821C_1ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_AntDet_running; + boolean is_psd_show_max_only; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8821c1ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8821c1ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8821c1ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c1ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8821c1ant_coex_dm_reset(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c1ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8821c1ant_antenna_isolation(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); + +void ex_halbtc8821c1ant_psd_scan(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8821c1ant_display_ant_detection(IN struct btc_coexist *btcoexist); + + + diff --git a/drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.c b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.c new file mode 100644 index 000000000000..7c780958c618 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.c @@ -0,0 +1,5773 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* ************************************************************ + * Description: + * + * This file is for RTL8821C Co-exist mechanism + * + * History + * 2012/11/15 Cosa first check in. + * + * ************************************************************ */ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" + + +/* ************************************************************ + * Global variables, these are static variables + * ************************************************************ */ +static u8 *trace_buf = &gl_btc_trace_buf[0]; +static struct coex_dm_8821c_2ant glcoex_dm_8821c_2ant; +static struct coex_dm_8821c_2ant *coex_dm = &glcoex_dm_8821c_2ant; +static struct coex_sta_8821c_2ant glcoex_sta_8821c_2ant; +static struct coex_sta_8821c_2ant *coex_sta = &glcoex_sta_8821c_2ant; +static struct psdscan_sta_8821c_2ant gl_psd_scan_8821c_2ant; +static struct psdscan_sta_8821c_2ant *psd_scan = &gl_psd_scan_8821c_2ant; +static struct rfe_type_8821c_2ant gl_rfe_type_8821c_2ant; +static struct rfe_type_8821c_2ant *rfe_type = &gl_rfe_type_8821c_2ant; + +const char *const glbt_info_src_8821c_2ant[] = { + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u32 glcoex_ver_date_8821c_2ant = 20170310; +u32 glcoex_ver_8821c_2ant = 0x12; +u32 glcoex_ver_btdesired_8821c_2ant = 0x11; + +/* ************************************************************ + * local function proto type if needed + * ************************************************************ + * ************************************************************ + * local function start with halbtc8821c2ant_ + * ************************************************************ */ +u8 halbtc8821c2ant_bt_rssi_state(IN struct btc_coexist *btcoexist, + u8 *ppre_bt_rssi_state, u8 level_num, + u8 rssi_thresh, u8 rssi_thresh1) +{ + s32 bt_rssi = 0; + u8 bt_rssi_state = *ppre_bt_rssi_state; + + bt_rssi = coex_sta->bt_rssi; + + if (level_num == 2) { + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT Rssi thresh error!!\n"); + BTC_TRACE(trace_buf); + return *ppre_bt_rssi_state; + } + + if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_LOW) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (bt_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*ppre_bt_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*ppre_bt_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (bt_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + bt_rssi_state = BTC_RSSI_STATE_HIGH; + else if (bt_rssi < rssi_thresh) + bt_rssi_state = BTC_RSSI_STATE_LOW; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (bt_rssi < rssi_thresh1) + bt_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + bt_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *ppre_bt_rssi_state = bt_rssi_state; + + return bt_rssi_state; +} + +u8 halbtc8821c2ant_wifi_rssi_state(IN struct btc_coexist *btcoexist, + IN u8 *pprewifi_rssi_state, IN u8 level_num, IN u8 rssi_thresh, + IN u8 rssi_thresh1) +{ + s32 wifi_rssi = 0; + u8 wifi_rssi_state = *pprewifi_rssi_state; + + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + + if (level_num == 2) { + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else { + if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } else if (level_num == 3) { + if (rssi_thresh > rssi_thresh1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi RSSI thresh error!!\n"); + BTC_TRACE(trace_buf); + return *pprewifi_rssi_state; + } + + if ((*pprewifi_rssi_state == BTC_RSSI_STATE_LOW) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_LOW)) { + if (wifi_rssi >= (rssi_thresh + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_LOW; + } else if ((*pprewifi_rssi_state == BTC_RSSI_STATE_MEDIUM) || + (*pprewifi_rssi_state == BTC_RSSI_STATE_STAY_MEDIUM)) { + if (wifi_rssi >= (rssi_thresh1 + + BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT)) + wifi_rssi_state = BTC_RSSI_STATE_HIGH; + else if (wifi_rssi < rssi_thresh) + wifi_rssi_state = BTC_RSSI_STATE_LOW; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_MEDIUM; + } else { + if (wifi_rssi < rssi_thresh1) + wifi_rssi_state = BTC_RSSI_STATE_MEDIUM; + else + wifi_rssi_state = BTC_RSSI_STATE_STAY_HIGH; + } + } + + *pprewifi_rssi_state = wifi_rssi_state; + + return wifi_rssi_state; +} + +void halbtc8821c2ant_coex_switch_threshold(IN struct btc_coexist *btcoexist, + IN u8 isolation_measuared) +{ + s8 interference_wl_tx = 0, interference_bt_tx = 0; + + interference_wl_tx = BT_8821C_2ANT_WIFI_MAX_TX_POWER - + isolation_measuared; + interference_bt_tx = BT_8821C_2ANT_BT_MAX_TX_POWER - + isolation_measuared; + + coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + coex_sta->wifi_coex_thres2 = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2; + + coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; + coex_sta->bt_coex_thres2 = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2; + + /* + coex_sta->wifi_coex_thres = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES1; + coex_sta->wifi_coex_thres2 = interference_wl_tx + BT_8821C_2ANT_WIFI_SIR_THRES2; + + coex_sta->bt_coex_thres = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES1; + coex_sta->bt_coex_thres2 = interference_bt_tx + BT_8821C_2ANT_BT_SIR_THRES2; + */ + + /* + if ( BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION) ) + coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1; + else + coex_sta->wifi_coex_thres = BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION); + + if ( BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 < (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION) ) + coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1; + else + coex_sta->bt_coex_thres = BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 - (isolation_measuared - + BT_8821C_2ANT_DEFAULT_ISOLATION); + + */ +} + +void halbtc8821c2ant_limited_rx(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean rej_ap_agg_pkt, + IN boolean bt_ctrl_agg_buf_size, IN u8 agg_buf_size) +{ + boolean reject_rx_agg = rej_ap_agg_pkt; + boolean bt_ctrl_rx_agg_size = bt_ctrl_agg_buf_size; + u8 rx_agg_size = agg_buf_size; + + /* ============================================ */ + /* Rx Aggregation related setting */ + /* ============================================ */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, + &reject_rx_agg); + /* decide BT control aggregation buf size or not */ + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, + &bt_ctrl_rx_agg_size); + /* aggregation buf size, only work when BT control Rx aggregation size. */ + btcoexist->btc_set(btcoexist, BTC_SET_U1_AGG_BUF_SIZE, &rx_agg_size); + /* real update aggregation setting */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +void halbtc8821c2ant_query_bt_info(IN struct btc_coexist *btcoexist) +{ + u8 h2c_parameter[1] = {0}; + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No query BT info because BT is disabled!\n"); + BTC_TRACE(trace_buf); + return; + } + + h2c_parameter[0] |= BIT(0); /* trigger */ + + btcoexist->btc_fill_h2c(btcoexist, 0x61, 1, h2c_parameter); +} + +void halbtc8821c2ant_monitor_bt_ctr(IN struct btc_coexist *btcoexist) +{ + u32 reg_hp_txrx, reg_lp_txrx, u32tmp; + u32 reg_hp_tx = 0, reg_hp_rx = 0, reg_lp_tx = 0, reg_lp_rx = 0; + static u8 num_of_bt_counter_chk = 0, cnt_slave = 0, cnt_overhead = 0, + cnt_autoslot_hang = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + reg_hp_txrx = 0x770; + reg_lp_txrx = 0x774; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_hp_txrx); + reg_hp_tx = u32tmp & MASKLWORD; + reg_hp_rx = (u32tmp & MASKHWORD) >> 16; + + u32tmp = btcoexist->btc_read_4byte(btcoexist, reg_lp_txrx); + reg_lp_tx = u32tmp & MASKLWORD; + reg_lp_rx = (u32tmp & MASKHWORD) >> 16; + + coex_sta->high_priority_tx = reg_hp_tx; + coex_sta->high_priority_rx = reg_hp_rx; + coex_sta->low_priority_tx = reg_lp_tx; + coex_sta->low_priority_rx = reg_lp_rx; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + reg_hp_rx, reg_hp_tx, reg_lp_rx, reg_lp_tx); + + BTC_TRACE(trace_buf); + + if (BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + if (coex_sta->high_priority_rx >= 15) { + if (cnt_overhead < 3) + cnt_overhead++; + + if (cnt_overhead == 3) + coex_sta->is_hiPri_rx_overhead = TRUE; + + } else { + if (cnt_overhead > 0) + cnt_overhead--; + + if (cnt_overhead == 0) + coex_sta->is_hiPri_rx_overhead = FALSE; + } + } else + coex_sta->is_hiPri_rx_overhead = FALSE; + + /* reset counter */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, 0xc); + + if ((coex_sta->low_priority_tx > 1150) && + (!coex_sta->c2h_bt_inquiry_page)) + coex_sta->pop_event_cnt++; + + if ((coex_sta->low_priority_rx >= 1150) && + (coex_sta->low_priority_rx >= coex_sta->low_priority_tx) + && (!coex_sta->under_ips) + && (!coex_sta->c2h_bt_inquiry_page) + && ((bt_link_info->a2dp_exist) || (bt_link_info->pan_exist))) { + if (cnt_slave >= 2) { + bt_link_info->slave_role = TRUE; + cnt_slave = 2; + } else + cnt_slave++; + } else { + if (cnt_slave == 0) { + bt_link_info->slave_role = FALSE; + cnt_slave = 0; + } else + cnt_slave--; + } + + if (coex_sta->is_tdma_btautoslot) { + if ((coex_sta->low_priority_tx >= 1300) && + (coex_sta->low_priority_rx <= 150)) { + if (cnt_autoslot_hang >= 2) { + coex_sta->is_tdma_btautoslot_hang = TRUE; + cnt_autoslot_hang = 2; + } else + cnt_autoslot_hang++; + } else { + if (cnt_autoslot_hang == 0) { + coex_sta->is_tdma_btautoslot_hang = FALSE; + cnt_autoslot_hang = 0; + } else + cnt_autoslot_hang--; + } + } + + if (coex_sta->sco_exist) { + if ((coex_sta->high_priority_tx >= 400) && + (coex_sta->high_priority_rx >= 400)) + coex_sta->is_eSCO_mode = FALSE; + else + coex_sta->is_eSCO_mode = TRUE; + } + + if (bt_link_info->hid_only) { + if (coex_sta->low_priority_rx > 50) + coex_sta->is_hid_low_pri_tx_overhead = true; + else + coex_sta->is_hid_low_pri_tx_overhead = false; + } + + if (!coex_sta->bt_disabled) { + + if ((coex_sta->high_priority_tx == 0) && + (coex_sta->high_priority_rx == 0) && + (coex_sta->low_priority_tx == 0) && + (coex_sta->low_priority_rx == 0)) { + num_of_bt_counter_chk++; + if (num_of_bt_counter_chk >= 3) { + halbtc8821c2ant_query_bt_info(btcoexist); + num_of_bt_counter_chk = 0; + } + } + } + +} + +void halbtc8821c2ant_monitor_wifi_ctr(IN struct btc_coexist *btcoexist) +{ + s32 wifi_rssi = 0; + boolean wifi_busy = FALSE, wifi_under_b_mode = FALSE, + wifi_scan = FALSE; + boolean bt_idle = FALSE, wl_idle = FALSE; + static u8 cck_lock_counter = 0, wl_noisy_count0 = 0, + wl_noisy_count1 = 3, wl_noisy_count2 = 0; + u32 total_cnt, reg_val1, reg_val2, cck_cnt; + u32 cnt_crcok = 0, cnt_crcerr = 0; + static u8 cnt = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_S4_WIFI_RSSI, &wifi_rssi); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + + coex_sta->crc_ok_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_CCK); + coex_sta->crc_ok_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_LEGACY); + coex_sta->crc_ok_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_HT); + coex_sta->crc_ok_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_OK_VHT); + + coex_sta->crc_err_cck = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_CCK); + coex_sta->crc_err_11g = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_LEGACY); + coex_sta->crc_err_11n = btcoexist->btc_phydm_query_PHY_counter( + btcoexist, PHYDM_INFO_CRC32_ERROR_HT); + coex_sta->crc_err_11n_vht = + btcoexist->btc_phydm_query_PHY_counter( + btcoexist, + PHYDM_INFO_CRC32_ERROR_VHT); + + cnt_crcok = coex_sta->crc_ok_cck + coex_sta->crc_ok_11g + + coex_sta->crc_ok_11n + + coex_sta->crc_ok_11n_vht; + + cnt_crcerr = coex_sta->crc_err_cck + coex_sta->crc_err_11g + + coex_sta->crc_err_11n + + coex_sta->crc_err_11n_vht; + + if ((wifi_busy) && (cnt_crcerr != 0)) { + + coex_sta->now_crc_ratio = cnt_crcok/cnt_crcerr; + + if (cnt == 0) + coex_sta->acc_crc_ratio = coex_sta->now_crc_ratio; + else + coex_sta->acc_crc_ratio = (coex_sta->acc_crc_ratio * 7 + + coex_sta->now_crc_ratio * 3)/10; + + if (cnt >= 10) + cnt = 0; + else + cnt++; + } + + cck_cnt = coex_sta->crc_ok_cck + coex_sta->crc_err_cck; + + if ((coex_dm->bt_status == + BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE) || + (coex_dm->bt_status == + BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE) || + (coex_sta->bt_disabled)) + bt_idle = TRUE; + + if (cck_cnt > 250) { + if (wl_noisy_count2 < 3) + wl_noisy_count2++; + + if (wl_noisy_count2 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count1 = 0; + } + + } else if (cck_cnt < 50) { + if (wl_noisy_count0 < 3) + wl_noisy_count0++; + + if (wl_noisy_count0 == 3) { + wl_noisy_count1 = 0; + wl_noisy_count2 = 0; + } + + } else { + if (wl_noisy_count1 < 3) + wl_noisy_count1++; + + if (wl_noisy_count1 == 3) { + wl_noisy_count0 = 0; + wl_noisy_count2 = 0; + } + } + + if (wl_noisy_count2 == 3) + coex_sta->wl_noisy_level = 2; + else if (wl_noisy_count1 == 3) + coex_sta->wl_noisy_level = 1; + else + coex_sta->wl_noisy_level = 0; + + if ((wifi_busy) && (wifi_rssi >= 30) && (!wifi_under_b_mode)) { + total_cnt = cnt_crcok; + + if ((coex_dm->bt_status == + BT_8821C_1ANT_BT_STATUS_ACL_BUSY) || + (coex_dm->bt_status == + BT_8821C_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (coex_dm->bt_status == + BT_8821C_1ANT_BT_STATUS_SCO_BUSY)) { + if (coex_sta->crc_ok_cck > (total_cnt - + coex_sta->crc_ok_cck)) { + if (cck_lock_counter < 3) + cck_lock_counter++; + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + } else { + if (cck_lock_counter > 0) + cck_lock_counter--; + } + + if (!coex_sta->pre_ccklock) { + + if (cck_lock_counter >= 3) + coex_sta->cck_lock = TRUE; + else + coex_sta->cck_lock = FALSE; + } else { + if (cck_lock_counter == 0) + coex_sta->cck_lock = FALSE; + else + coex_sta->cck_lock = TRUE; + } + + if (coex_sta->cck_lock) + coex_sta->cck_ever_lock = TRUE; + + coex_sta->pre_ccklock = coex_sta->cck_lock; + +} + +void halbtc8821c2ant_update_bt_link_info(IN struct btc_coexist *btcoexist) +{ + + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + boolean bt_busy = FALSE; + + coex_sta->num_of_profile = 0; + + /* set link exist status */ + if (!(coex_sta->bt_info & BT_INFO_8821C_1ANT_B_CONNECTION)) { + coex_sta->bt_link_exist = FALSE; + coex_sta->pan_exist = FALSE; + coex_sta->a2dp_exist = FALSE; + coex_sta->hid_exist = FALSE; + coex_sta->sco_exist = FALSE; + } else { /* connection exists */ + coex_sta->bt_link_exist = TRUE; + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_FTP) { + coex_sta->pan_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->pan_exist = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_A2DP) { + coex_sta->a2dp_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->a2dp_exist = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_HID) { + coex_sta->hid_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->hid_exist = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_1ANT_B_SCO_ESCO) { + coex_sta->sco_exist = TRUE; + coex_sta->num_of_profile++; + } else + coex_sta->sco_exist = FALSE; + + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + bt_link_info->bt_link_exist = coex_sta->bt_link_exist; + bt_link_info->sco_exist = coex_sta->sco_exist; + bt_link_info->a2dp_exist = coex_sta->a2dp_exist; + bt_link_info->pan_exist = coex_sta->pan_exist; + bt_link_info->hid_exist = coex_sta->hid_exist; + bt_link_info->acl_busy = coex_sta->acl_busy; + + /* work around for HS mode. */ + if (bt_hs_on) { + bt_link_info->pan_exist = TRUE; + bt_link_info->bt_link_exist = TRUE; + } + + /* check if Sco only */ + if (bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->sco_only = TRUE; + else + bt_link_info->sco_only = FALSE; + + /* check if A2dp only */ + if (!bt_link_info->sco_exist && + bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->a2dp_only = TRUE; + else + bt_link_info->a2dp_only = FALSE; + + /* check if Pan only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + bt_link_info->pan_exist && + !bt_link_info->hid_exist) + bt_link_info->pan_only = TRUE; + else + bt_link_info->pan_only = FALSE; + + /* check if Hid only */ + if (!bt_link_info->sco_exist && + !bt_link_info->a2dp_exist && + !bt_link_info->pan_exist && + bt_link_info->hid_exist) + bt_link_info->hid_only = TRUE; + else + bt_link_info->hid_only = FALSE; + + if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_INQ_PAGE) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_INQ_PAGE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Inq/page!!!\n"); + } else if (!(coex_sta->bt_info & BT_INFO_8821C_2ANT_B_CONNECTION)) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n"); + } else if (coex_sta->bt_info == BT_INFO_8821C_2ANT_B_CONNECTION) { + /* connection exists but no busy */ + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n"); + } else if (((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) && + (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY)) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL SCO busy!!!\n"); + } else if ((coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_ESCO) || + (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_SCO_BUSY)) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_SCO_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT SCO busy!!!\n"); + } else if (coex_sta->bt_info & BT_INFO_8821C_2ANT_B_ACL_BUSY) { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_ACL_BUSY; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT ACL busy!!!\n"); + } else { + coex_dm->bt_status = BT_8821C_2ANT_BT_STATUS_MAX; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n"); + } + + BTC_TRACE(trace_buf); + + if ((BT_8821C_2ANT_BT_STATUS_ACL_BUSY == coex_dm->bt_status) || + (BT_8821C_2ANT_BT_STATUS_SCO_BUSY == coex_dm->bt_status) || + (BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY == coex_dm->bt_status)) + bt_busy = TRUE; + else + bt_busy = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bt_busy); +} + +void halbtc8821c2ant_update_wifi_channel_info(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + + /* only 2.4G we need to inform bt the chnl mask */ + btcoexist->btc_get(btcoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, + &wifi_central_chnl); + if ((BTC_MEDIA_CONNECT == type) && + (wifi_central_chnl <= 14)) { + h2c_parameter[0] = + 0x1; /* enable BT AFH skip WL channel for 8821c because BT Rx LO interference */ + /* h2c_parameter[0] = 0x0; */ + h2c_parameter[1] = wifi_central_chnl; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + if (BTC_WIFI_BW_HT40 == wifi_bw) + h2c_parameter[2] = 0x30; + else + h2c_parameter[2] = 0x20; + } + + coex_dm->wifi_chnl_info[0] = h2c_parameter[0]; + coex_dm->wifi_chnl_info[1] = h2c_parameter[1]; + coex_dm->wifi_chnl_info[2] = h2c_parameter[2]; + + btcoexist->btc_fill_h2c(btcoexist, 0x66, 3, h2c_parameter); + +} + +void halbtc8821c2ant_set_fw_dac_swing_level(IN struct btc_coexist *btcoexist, + IN u8 dac_swing_lvl) +{ + u8 h2c_parameter[1] = {0}; + + /* There are several type of dacswing */ + /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ + h2c_parameter[0] = dac_swing_lvl; + + btcoexist->btc_fill_h2c(btcoexist, 0x64, 1, h2c_parameter); +} + +void halbtc8821c2ant_fw_dac_swing_lvl(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 fw_dac_swing_lvl) +{ + coex_dm->cur_fw_dac_swing_lvl = fw_dac_swing_lvl; + + if (!force_exec) { + if (coex_dm->pre_fw_dac_swing_lvl == + coex_dm->cur_fw_dac_swing_lvl) + return; + } + + halbtc8821c2ant_set_fw_dac_swing_level(btcoexist, + coex_dm->cur_fw_dac_swing_lvl); + + coex_dm->pre_fw_dac_swing_lvl = coex_dm->cur_fw_dac_swing_lvl; +} + +void halbtc8821c2ant_set_fw_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN u8 dec_bt_pwr_lvl) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = dec_bt_pwr_lvl; +} + +void halbtc8821c2ant_dec_bt_pwr(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 dec_bt_pwr_lvl) +{ + coex_dm->cur_bt_dec_pwr_lvl = dec_bt_pwr_lvl; + + if (!force_exec) { + if (coex_dm->pre_bt_dec_pwr_lvl == coex_dm->cur_bt_dec_pwr_lvl) + return; + } + halbtc8821c2ant_set_fw_dec_bt_pwr(btcoexist, + coex_dm->cur_bt_dec_pwr_lvl); + + coex_dm->pre_bt_dec_pwr_lvl = coex_dm->cur_bt_dec_pwr_lvl; +} + +void halbtc8821c2ant_low_penalty_ra(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean low_penalty_ra) +{ + + coex_dm->cur_low_penalty_ra = low_penalty_ra; + + if (!force_exec) { + if (coex_dm->pre_low_penalty_ra == + coex_dm->cur_low_penalty_ra) + return; + } + + if (low_penalty_ra) + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 15); + else + btcoexist->btc_phydm_modify_RA_PCR_threshold(btcoexist, 0, 0); + + coex_dm->pre_low_penalty_ra = coex_dm->cur_low_penalty_ra; + + +} + +void halbtc8821c2ant_set_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean enable_auto_report) +{ + u8 h2c_parameter[1] = {0}; + + h2c_parameter[0] = 0; + + if (enable_auto_report) + h2c_parameter[0] |= BIT(0); + + btcoexist->btc_fill_h2c(btcoexist, 0x68, 1, h2c_parameter); +} + +void halbtc8821c2ant_bt_auto_report(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable_auto_report) +{ + coex_dm->cur_bt_auto_report = enable_auto_report; + + if (!force_exec) { + if (coex_dm->pre_bt_auto_report == coex_dm->cur_bt_auto_report) + return; + } + halbtc8821c2ant_set_bt_auto_report(btcoexist, + coex_dm->cur_bt_auto_report); + + coex_dm->pre_bt_auto_report = coex_dm->cur_bt_auto_report; +} + +void halbtc8821c2ant_write_score_board( + IN struct btc_coexist *btcoexist, + IN u16 bitpos, + IN boolean state +) +{ + + static u16 originalval = 0x8002; + + if (state) + originalval = originalval | bitpos; + else + originalval = originalval & (~bitpos); + + btcoexist->btc_write_2byte(btcoexist, 0xaa, originalval); + +} + +void halbtc8821c2ant_read_score_board( + IN struct btc_coexist *btcoexist, + IN u16 *score_board_val +) +{ + + *score_board_val = (btcoexist->btc_read_2byte(btcoexist, + 0xaa)) & 0x7fff; +} + +void halbtc8821c2ant_post_state_to_bt( + IN struct btc_coexist *btcoexist, + IN u16 type, + IN boolean state +) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_post_state_to_bt: type = %d, state =%d\n", + type, state); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_write_score_board(btcoexist, (u16) type, state); +} + +boolean halbtc8821c2ant_is_wifibt_status_changed(IN struct btc_coexist + *btcoexist) +{ + static boolean pre_wifi_busy = FALSE, pre_under_4way = FALSE, + pre_bt_hs_on = FALSE, pre_bt_off = FALSE, + pre_bt_slave = FALSE, pre_hid_low_pri_tx_overhead = FALSE, + pre_wifi_under_lps = FALSE; + static u8 pre_hid_busy_num = 0, pre_wl_noisy_level = 0, + pre_bt_setup_link = FALSE; + boolean wifi_busy = FALSE, under_4way = FALSE, bt_hs_on = FALSE; + boolean wifi_connected = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (coex_sta->bt_disabled != pre_bt_off) { + pre_bt_off = coex_sta->bt_disabled; + + if (coex_sta->bt_disabled) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled !!\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is enabled !!\n"); + + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + return TRUE; + } + + if (wifi_connected) { + if (wifi_busy != pre_wifi_busy) { + pre_wifi_busy = wifi_busy; + + if (wifi_busy) + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, TRUE); + else + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, FALSE); + return TRUE; + } + if (under_4way != pre_under_4way) { + pre_under_4way = under_4way; + return TRUE; + } + if (bt_hs_on != pre_bt_hs_on) { + pre_bt_hs_on = bt_hs_on; + return TRUE; + } + if (coex_sta->wl_noisy_level != pre_wl_noisy_level) { + pre_wl_noisy_level = coex_sta->wl_noisy_level; + return TRUE; + } + if (coex_sta->under_lps != pre_wifi_under_lps) { + pre_wifi_under_lps = coex_sta->under_lps; + if (coex_sta->under_lps == TRUE) + return TRUE; + } + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->hid_busy_num != pre_hid_busy_num) { + pre_hid_busy_num = coex_sta->hid_busy_num; + return TRUE; + } + + if (bt_link_info->slave_role != pre_bt_slave) { + pre_bt_slave = bt_link_info->slave_role; + return TRUE; + } + + if (pre_hid_low_pri_tx_overhead != coex_sta->is_hid_low_pri_tx_overhead) { + pre_hid_low_pri_tx_overhead = coex_sta->is_hid_low_pri_tx_overhead; + return TRUE; + } + + if (pre_bt_setup_link != coex_sta->is_setupLink) { + pre_bt_setup_link = coex_sta->is_setupLink; + return TRUE; + } + } + + return FALSE; +} + +void halbtc8821c2ant_monitor_bt_enable_disable(IN struct btc_coexist *btcoexist) +{ + static u32 bt_disable_cnt = 0; + boolean bt_active = TRUE, bt_disabled = FALSE, wifi_under_5g = FALSE; + u16 u16tmp; + + /* Read BT on/off status from scoreboard[1], enable this only if BT patch support this feature */ + halbtc8821c2ant_read_score_board(btcoexist, &u16tmp); + + bt_active = u16tmp & BIT(1); + + if (bt_active) { + bt_disable_cnt = 0; + bt_disabled = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } else { + + bt_disable_cnt++; + if (bt_disable_cnt >= 2) { + bt_disabled = TRUE; + bt_disable_cnt = 2; + } + + btcoexist->btc_set(btcoexist, BTC_SET_BL_BT_DISABLE, + &bt_disabled); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) || (bt_disabled)) + halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + else + halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, TRUE); + + if (coex_sta->bt_disabled != bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is from %s to %s!!\n", + (coex_sta->bt_disabled ? "disabled" : "enabled"), + (bt_disabled ? "disabled" : "enabled")); + BTC_TRACE(trace_buf); + coex_sta->bt_disabled = bt_disabled; + } + +} + +void halbtc8821c2ant_enable_gnt_to_gpio(IN struct btc_coexist *btcoexist, + boolean isenable) +{ +#if BT_8821C_2ANT_COEX_DBG + static u8 bitVal[5] = {0, 0, 0, 0, 0}; + static boolean state = FALSE; + /* + if (state ==isenable) + return; + else + state = isenable; + */ + if (isenable) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], enable_gnt_to_gpio!!\n"); + BTC_TRACE(trace_buf); + + /* enable GNT_WL, GNT_BT to GPIO for debug */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x1); + + /* store original value */ + bitVal[0] = (btcoexist->btc_read_1byte(btcoexist, + 0x66) & BIT(4)) >> 4; /*0x66[4] */ + bitVal[1] = (btcoexist->btc_read_1byte(btcoexist, + 0x67) & BIT(0)); /*0x66[8] */ + bitVal[2] = (btcoexist->btc_read_1byte(btcoexist, + 0x42) & BIT(3)) >> 3; /*0x40[19] */ + bitVal[3] = (btcoexist->btc_read_1byte(btcoexist, + 0x65) & BIT(7)) >> 7; /*0x64[15] */ + bitVal[4] = (btcoexist->btc_read_1byte(btcoexist, + 0x72) & BIT(2)) >> 2; /*0x70[18] */ + + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + 0x0); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + 0x0); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + 0x0); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + 0x0); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + 0x0); /*0x70[18] = 0 */ + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], disable_gnt_to_gpio!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x8, 0x0); + + /* Restore original value */ + /* switch GPIO Mux */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x66, BIT(4), + bitVal[0]); /*0x66[4] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, BIT(0), + bitVal[1]); /*0x66[8] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x42, BIT(3), + bitVal[2]); /*0x40[19] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x65, BIT(7), + bitVal[3]); /*0x64[15] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x72, BIT(2), + bitVal[4]); /*0x70[18] = 0 */ + } + +#endif +} + +u32 halbtc8821c2ant_ltecoex_indirect_read_reg(IN struct btc_coexist *btcoexist, + IN u16 reg_addr) +{ + u32 j = 0, delay_count = 0; + + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else + break; + } + + /* wait for ready bit before access 0x1700 */ + btcoexist->btc_write_4byte(btcoexist, 0x1700, 0x800F0000 | reg_addr); + + return btcoexist->btc_read_4byte(btcoexist, + 0x1708); /* get read data */ + +} + +void halbtc8821c2ant_ltecoex_indirect_write_reg(IN struct btc_coexist + *btcoexist, + IN u16 reg_addr, IN u32 bit_mask, IN u32 reg_value) +{ + u32 val, i = 0, j = 0, bitpos = 0, delay_count = 0; + + if (bit_mask == 0x0) + return; + if (bit_mask == 0xffffffff) { + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else + break; + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + reg_value); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /* read back register value before write */ + val = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + /* wait for ready bit before access 0x1700/0x1704 */ + while (1) { + if ((btcoexist->btc_read_1byte(btcoexist, 0x1703)&BIT(5)) == 0) { + delay_ms(50); + delay_count++; + if (delay_count >= 10) { + delay_count = 0; + break; + } + } else + break; + } + + btcoexist->btc_write_4byte(btcoexist, 0x1704, + val); /* put write data */ + + btcoexist->btc_write_4byte(btcoexist, 0x1700, + 0xc00F0000 | reg_addr); + } + +} + +void halbtc8821c2ant_ltecoex_enable(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 val; + + val = (enable) ? 1 : 0; + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, 0x38, 0x80, + val); /* 0x38[7] */ + +} + +void halbtc8821c2ant_ltecoex_pathcontrol_owner(IN struct btc_coexist *btcoexist, + IN boolean wifi_control) +{ + u8 val; + + val = (wifi_control) ? 1 : 0; + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x73, 0x4, + val); /* 0x70[26] */ + +} + +void halbtc8821c2ant_ltecoex_set_gnt_bt(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 14) | (val << 10)) | (val_orig & 0xffff33ff); + break; + case BT_8821C_2ANT_GNT_BLOCK_RFC: + val = (val << 14) | (val_orig & 0xffff3fff); + break; + case BT_8821C_2ANT_GNT_BLOCK_BB: + val = (val << 10) | (val_orig & 0xfffff3ff); + break; + } + + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c2ant_ltecoex_set_gnt_wl(IN struct btc_coexist *btcoexist, + IN u8 control_block, IN boolean sw_control, IN u8 state) +{ + u32 val = 0, val_orig = 0; + + if (!sw_control) + val = 0x0; + else if (state & 0x1) + val = 0x3; + else + val = 0x1; + + val_orig = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + switch (control_block) { + case BT_8821C_2ANT_GNT_BLOCK_RFC_BB: + default: + val = ((val << 12) | (val << 8)) | (val_orig & 0xffffccff); + break; + case BT_8821C_2ANT_GNT_BLOCK_RFC: + val = (val << 12) | (val_orig & 0xffffcfff); + break; + case BT_8821C_2ANT_GNT_BLOCK_BB: + val = (val << 8) | (val_orig & 0xfffffcff); + break; + } + + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, + 0x38, 0xffffffff, val); +} + +void halbtc8821c2ant_ltecoex_set_coex_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u16 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_2ANT_CTT_WL_VS_LTE: + reg_addr = 0xa0; + break; + case BT_8821C_2ANT_CTT_BT_VS_LTE: + reg_addr = 0xa4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xffff, table_content); /* 0xa0[15:0] or 0xa4[15:0] */ + +} + +void halbtc8821c2ant_ltecoex_set_break_table(IN struct btc_coexist *btcoexist, + IN u8 table_type, IN u8 table_content) +{ + u16 reg_addr = 0x0000; + + switch (table_type) { + case BT_8821C_2ANT_LBTT_WL_BREAK_LTE: + reg_addr = 0xa8; + break; + case BT_8821C_2ANT_LBTT_BT_BREAK_LTE: + reg_addr = 0xac; + break; + case BT_8821C_2ANT_LBTT_LTE_BREAK_WL: + reg_addr = 0xb0; + break; + case BT_8821C_2ANT_LBTT_LTE_BREAK_BT: + reg_addr = 0xb4; + break; + } + + if (reg_addr != 0x0000) + halbtc8821c2ant_ltecoex_indirect_write_reg(btcoexist, reg_addr, + 0xff, table_content); /* 0xa8[15:0] or 0xb4[15:0] */ + +} + +void halbtc8821c2ant_set_wltoggle_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 interval, + IN u8 val0x6c4_b0, IN u8 val0x6c4_b1, IN u8 val0x6c4_b2, + IN u8 val0x6c4_b3) +{ + static u8 pre_h2c_parameter[6] = {0}; + u8 cur_h2c_parameter[6] = {0}; + u8 i, match_cnt = 0; + + cur_h2c_parameter[0] = 0x7; /* op_code, 0x7= wlan toggle slot*/ + + cur_h2c_parameter[1] = interval; + cur_h2c_parameter[2] = val0x6c4_b0; + cur_h2c_parameter[3] = val0x6c4_b1; + cur_h2c_parameter[4] = val0x6c4_b2; + cur_h2c_parameter[5] = val0x6c4_b3; + + if (!force_exec) { + for (i = 1; i <= 5; i++) { + if (cur_h2c_parameter[i] != pre_h2c_parameter[i]) + break; + + match_cnt++; + } + + if (match_cnt == 5) + return; + } + + for (i = 1; i <= 5; i++) + pre_h2c_parameter[i] = cur_h2c_parameter[i]; + + btcoexist->btc_fill_h2c(btcoexist, 0x69, 6, cur_h2c_parameter); +} + +void halbtc8821c2ant_set_coex_table(IN struct btc_coexist *btcoexist, + IN u32 val0x6c0, IN u32 val0x6c4, IN u32 val0x6c8, IN u8 val0x6cc) +{ + btcoexist->btc_write_4byte(btcoexist, 0x6c0, val0x6c0); + + btcoexist->btc_write_4byte(btcoexist, 0x6c4, val0x6c4); + + btcoexist->btc_write_4byte(btcoexist, 0x6c8, val0x6c8); + + btcoexist->btc_write_1byte(btcoexist, 0x6cc, val0x6cc); +} + +void halbtc8821c2ant_coex_table(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u32 val0x6c0, IN u32 val0x6c4, + IN u32 val0x6c8, IN u8 val0x6cc) +{ + coex_dm->cur_val0x6c0 = val0x6c0; + coex_dm->cur_val0x6c4 = val0x6c4; + coex_dm->cur_val0x6c8 = val0x6c8; + coex_dm->cur_val0x6cc = val0x6cc; + + if (!force_exec) { + if ((coex_dm->pre_val0x6c0 == coex_dm->cur_val0x6c0) && + (coex_dm->pre_val0x6c4 == coex_dm->cur_val0x6c4) && + (coex_dm->pre_val0x6c8 == coex_dm->cur_val0x6c8) && + (coex_dm->pre_val0x6cc == coex_dm->cur_val0x6cc)) + return; + } + halbtc8821c2ant_set_coex_table(btcoexist, val0x6c0, val0x6c4, val0x6c8, + val0x6cc); + + coex_dm->pre_val0x6c0 = coex_dm->cur_val0x6c0; + coex_dm->pre_val0x6c4 = coex_dm->cur_val0x6c4; + coex_dm->pre_val0x6c8 = coex_dm->cur_val0x6c8; + coex_dm->pre_val0x6cc = coex_dm->cur_val0x6cc; +} + +void halbtc8821c2ant_coex_table_with_type(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 type) +{ + u32 break_table; + u8 select_table; + + coex_sta->coex_table_type = type; + + if (coex_sta->concurrent_rx_mode_on == TRUE) { + break_table = 0xf0ffffff; /* set WL hi-pri can break BT */ + select_table = + 0xb; /* set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) */ + } else { + break_table = 0xffffff; + select_table = 0x3; + } + + switch (type) { + case 0: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0xffffffff, 0xffffffff, break_table, select_table); + break; + case 1: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 2: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0x5a5a5a5a, break_table, select_table); + break; + case 3: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 4: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x5a5a5a5a, break_table, select_table); + break; + case 5: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0x55555555, break_table, select_table); + break; + case 6: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xfafafafa, break_table, select_table); + break; + case 7: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0xa5555555, 0xaa5a5a5a, break_table, select_table); + break; + case 8: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x55555555, 0xfafa5afa, break_table, select_table); + break; + case 9: + halbtc8821c2ant_coex_table(btcoexist, force_exec, + 0x5a5a5a5a, 0xaaaa5aaa, break_table, select_table); + break; + default: + break; + } +} + +void halbtc8821c2ant_set_fw_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean enable) +{ + u8 h2c_parameter[1] = {0}; + + if (enable) { + h2c_parameter[0] |= BIT(0); /* function enable */ + } + + btcoexist->btc_fill_h2c(btcoexist, 0x63, 1, h2c_parameter); +} + +void halbtc8821c2ant_ignore_wlan_act(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean enable) +{ + coex_dm->cur_ignore_wlan_act = enable; + + if (!force_exec) { + if (coex_dm->pre_ignore_wlan_act == + coex_dm->cur_ignore_wlan_act) + return; + } + halbtc8821c2ant_set_fw_ignore_wlan_act(btcoexist, enable); + + coex_dm->pre_ignore_wlan_act = coex_dm->cur_ignore_wlan_act; +} + +void halbtc8821c2ant_set_lps_rpwm(IN struct btc_coexist *btcoexist, + IN u8 lps_val, IN u8 rpwm_val) +{ + u8 lps = lps_val; + u8 rpwm = rpwm_val; + + btcoexist->btc_set(btcoexist, BTC_SET_U1_LPS_VAL, &lps); + btcoexist->btc_set(btcoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +void halbtc8821c2ant_lps_rpwm(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 lps_val, IN u8 rpwm_val) +{ + coex_dm->cur_lps = lps_val; + coex_dm->cur_rpwm = rpwm_val; + + if (!force_exec) { + if ((coex_dm->pre_lps == coex_dm->cur_lps) && + (coex_dm->pre_rpwm == coex_dm->cur_rpwm)) + return; + } + halbtc8821c2ant_set_lps_rpwm(btcoexist, lps_val, rpwm_val); + + coex_dm->pre_lps = coex_dm->cur_lps; + coex_dm->pre_rpwm = coex_dm->cur_rpwm; +} + +void halbtc8821c2ant_ps_tdma_check_for_power_save_state( + IN struct btc_coexist *btcoexist, IN boolean new_ps_state) +{ + u8 lps_mode = 0x0; + u8 h2c_parameter[5] = {0, 0, 0, 0x40, 0}; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_LPS_MODE, &lps_mode); + + if (lps_mode) { /* already under LPS state */ + if (new_ps_state) { + /* keep state under LPS, do nothing. */ + } else { + /* will leave LPS state, turn off psTdma first */ + /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8); */ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } + } else { /* NO PS state */ + if (new_ps_state) { + /* will enter LPS state, turn off psTdma first */ + /*halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, + 8);*/ + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, + h2c_parameter); + } else { + /* keep state under NO PS state, do nothing. */ + } + } +} + +boolean halbtc8821c2ant_power_save_state(IN struct btc_coexist *btcoexist, + IN u8 ps_type, IN u8 lps_val, IN u8 rpwm_val) +{ + boolean low_pwr_disable = FALSE, result = TRUE; + + switch (ps_type) { + case BTC_PS_WIFI_NATIVE: + coex_sta->force_lps_ctrl = FALSE; + /* recover to original 32k low power setting */ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_power_save_state == BTC_PS_WIFI_NATIVE\n"); + BTC_TRACE(trace_buf); + + low_pwr_disable = FALSE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + btcoexist->btc_set(btcoexist, BTC_SET_ACT_NORMAL_LPS, + NULL); + break; + case BTC_PS_LPS_ON: + coex_sta->force_lps_ctrl = TRUE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_power_save_state == BTC_PS_LPS_ON\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_ps_tdma_check_for_power_save_state( + btcoexist, TRUE); + halbtc8821c2ant_lps_rpwm(btcoexist, NORMAL_EXEC, + lps_val, rpwm_val); + /* when coex force to enter LPS, do not enter 32k low power. */ + low_pwr_disable = TRUE; + btcoexist->btc_set(btcoexist, + BTC_SET_ACT_DISABLE_LOW_POWER, + &low_pwr_disable); + /* power save must executed before psTdma. */ + btcoexist->btc_set(btcoexist, BTC_SET_ACT_ENTER_LPS, + NULL); + break; + case BTC_PS_LPS_OFF: + coex_sta->force_lps_ctrl = TRUE; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_power_save_state == BTC_PS_LPS_OFF\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_ps_tdma_check_for_power_save_state( + btcoexist, FALSE); + result = btcoexist->btc_set(btcoexist, BTC_SET_ACT_LEAVE_LPS, + NULL); + break; + default: + break; + } + + return result; +} + +void halbtc8821c2ant_set_fw_pstdma(IN struct btc_coexist *btcoexist, + IN u8 byte1, IN u8 byte2, IN u8 byte3, IN u8 byte4, IN u8 byte5) +{ + u8 h2c_parameter[5] = {0}; + u8 real_byte1 = byte1, real_byte5 = byte5; + boolean ap_enable = FALSE, result = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + if (byte5 & BIT(2)) + coex_sta->is_tdma_btautoslot = TRUE; + else + coex_sta->is_tdma_btautoslot = FALSE; + + /* release bt-auto slot for auto-slot hang is detected!! */ + if (coex_sta->is_tdma_btautoslot) + if ((coex_sta->is_tdma_btautoslot_hang) || + (bt_link_info->slave_role)) + byte5 = byte5 & 0xfb; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, + &ap_enable); + + if ((ap_enable) && (byte1 & BIT(4) && !(byte1 & BIT(5)))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_set_fw_pstdma == FW for AP mode\n"); + BTC_TRACE(trace_buf); + + real_byte1 &= ~BIT(4); + real_byte1 |= BIT(5); + + real_byte5 |= BIT(5); + real_byte5 &= ~BIT(6); + + halbtc8821c2ant_power_save_state(btcoexist, + BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } else if (byte1 & BIT(4) && !(byte1 & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_set_fw_pstdma == Force LPS Leave (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + + if (!halbtc8821c2ant_power_save_state(btcoexist, BTC_PS_LPS_OFF, 0x50, 0x4)) + result = TRUE; + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_set_fw_pstdma == Native LPS (byte1 = 0x%x)\n", byte1); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_power_save_state(btcoexist, BTC_PS_WIFI_NATIVE, + 0x0, + 0x0); + } + + coex_sta->is_set_ps_state_fail = result; + + if (!coex_sta->is_set_ps_state_fail) { + h2c_parameter[0] = real_byte1; + h2c_parameter[1] = byte2; + h2c_parameter[2] = byte3; + h2c_parameter[3] = byte4; + h2c_parameter[4] = real_byte5; + + coex_dm->ps_tdma_para[0] = real_byte1; + coex_dm->ps_tdma_para[1] = byte2; + coex_dm->ps_tdma_para[2] = byte3; + coex_dm->ps_tdma_para[3] = byte4; + coex_dm->ps_tdma_para[4] = real_byte5; + + btcoexist->btc_fill_h2c(btcoexist, 0x60, 5, h2c_parameter); + } else { + coex_sta->cnt_set_ps_state_fail++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], halbtc8821c2ant_set_fw_pstdma == Force Leave LPS Fail (cnt = %d)\n", + coex_sta->cnt_set_ps_state_fail); + BTC_TRACE(trace_buf); + } +} + +void halbtc8821c2ant_ps_tdma(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN boolean turn_on, IN u8 type) +{ + static u8 psTdmaByte4Modify = 0x0, pre_psTdmaByte4Modify = 0x0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + coex_dm->cur_ps_tdma_on = turn_on; + coex_dm->cur_ps_tdma = type; + + /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */ + if (bt_link_info->slave_role) + psTdmaByte4Modify = 0x1; + else + psTdmaByte4Modify = 0x0; + + if (pre_psTdmaByte4Modify != psTdmaByte4Modify) { + force_exec = TRUE; + pre_psTdmaByte4Modify = psTdmaByte4Modify; + } + + if (!force_exec) { + if ((coex_dm->pre_ps_tdma_on == coex_dm->cur_ps_tdma_on) && + (coex_dm->pre_ps_tdma == coex_dm->cur_ps_tdma)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Skip TDMA because no change TDMA(%s, %d)\n", + (coex_dm->cur_ps_tdma_on ? "on" : "off"), + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + return; + } + } + + if (coex_dm->cur_ps_tdma_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(on, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** TDMA(off, %d) **********\n", + coex_dm->cur_ps_tdma); + BTC_TRACE(trace_buf); + } + + if (turn_on) { + switch (type) { + case 1: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x54 | psTdmaByte4Modify); + break; + case 2: + default: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 3: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 4: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x21, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 5: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 6: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 7: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x3, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 8: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x15, 0x03, 0x11, + 0x11); + break; + case 10: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); + break; + case 11: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); + break; + case 12: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, 0x11); + break; + case 13: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x1c, 0x03, 0x11, + 0x10 | psTdmaByte4Modify); + break; + case 14: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x20, 0x03, 0x11, + 0x11); + break; + case 15: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x14); + break; + case 16: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x15); + break; + case 21: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x30, 0x03, 0x11, + 0x10); + break; + case 22: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, + 0x10); + break; + case 23: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x11, + 0x10); + break; + case 51: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x10, 0x03, 0x91, + 0x10 | psTdmaByte4Modify); + break; + case 101: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 102: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x35, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 103: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 104: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x21, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 105: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 106: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 107: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x7, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 108: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x3, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 109: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x54 | psTdmaByte4Modify); + break; + case 110: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x30, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); + break; + case 111: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x61, + 0x25, 0x03, 0x11, + 0x11 | psTdmaByte4Modify); + break; + case 151: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x51, + 0x10, 0x03, 0x10, + 0x50 | psTdmaByte4Modify); + break; + } + } else { + /* disable PS tdma */ + switch (type) { + case 0: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8821c2ant_set_fw_pstdma(btcoexist, 0x0, + 0x0, 0x0, 0x40, 0x0); + break; + } + } + + if (!coex_sta->is_set_ps_state_fail) { + /* update pre state */ + coex_dm->pre_ps_tdma_on = coex_dm->cur_ps_tdma_on; + coex_dm->pre_ps_tdma = coex_dm->cur_ps_tdma; + } +} + +void halbtc8821c2ant_set_int_block(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ +} + +void halbtc8821c2ant_set_ext_band_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 pos_type) +{ + +} + +void halbtc8821c2ant_set_ext_ant_switch(IN struct btc_coexist *btcoexist, + IN boolean force_exec, IN u8 ctrl_type, IN u8 pos_type) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + boolean switch_polatiry_inverse = FALSE; + u8 regval_0xcb7 = 0, regval_0x64; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + + if (!rfe_type->ext_ant_switch_exist) + return; + + coex_dm->cur_ext_ant_switch_status = (ctrl_type << 8) + pos_type; + + if (!force_exec) { + if (coex_dm->pre_ext_ant_switch_status == + coex_dm->cur_ext_ant_switch_status) + return; + } + + coex_dm->pre_ext_ant_switch_status = coex_dm->cur_ext_ant_switch_status; + + /* swap control polarity if use different switch control polarity*/ + /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ + /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + if (rfe_type->ext_ant_switch_ctrl_polarity) + switch_polatiry_inverse = !switch_polatiry_inverse; + + /* swap control polarity if 1-Ant at Aux */ + if (rfe_type->ant_at_main_port == FALSE) + switch_polatiry_inverse = !switch_polatiry_inverse; + + switch (pos_type) { + default: + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT: + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE: + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA: + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG: + if (!rfe_type->wlg_Locate_at_btg) + switch_polatiry_inverse = !switch_polatiry_inverse; + + break; + } + + if (board_info->ant_div_cfg) + ctrl_type = BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + + switch (ctrl_type) { + default: + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x77); /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == FALSE ? + 0x1 : 0x2); /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x66); /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + + regval_0xcb7 = (switch_polatiry_inverse == FALSE ? + 0x2 : 0x1); /* 0xcb4[29:28] = 2b'10 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 @ GNT_BT=1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb7, + 0x30, regval_0xcb7); + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x1); /* 0x4c[24] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0xcb4, + 0xff, 0x88); /* */ + + /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ + + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x1); /* 0x4c[23] = 1 */ + + regval_0x64 = (switch_polatiry_inverse == FALSE ? 0x0 : + 0x1); /* 0x64[0] = 1b'0 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x64, 0x1, + regval_0x64); + break; + case BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT: + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4e, + 0x80, 0x0); /* 0x4c[23] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4f, + 0x01, 0x0); /* 0x4c[24] = 0 */ + + /* no setup required, because antenna switch control value by BT vendor 0x1c[1:0] */ + break; + } + + /* PAPE, LNA_ON control by BT while WLAN off for current leakage issue */ + if (ctrl_type == BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT) { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x0); /* PAPE 0x64[29] = 0 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x0); /* LNA_ON 0x64[28] = 0 */ + } else { + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x20, + 0x1); /* PAPE 0x64[29] = 1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x67, 0x10, + 0x1); /* LNA_ON 0x64[28] = 1 */ + } + +#if BT_8821C_2ANT_COEX_DBG + + u32tmp1 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp2 = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0x64) & 0xff; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ext Ant switch setup) 0xcb4 = 0x%08x, 0x4c = 0x%08x, 0x64= 0x%02x\n", + u32tmp1, u32tmp2, u32tmp3); + BTC_TRACE(trace_buf); +#endif + +} + +void halbtc8821c2ant_set_rfe_type(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = board_info->rfe_type & 0x1f; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 1: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, WLG */ + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 2: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, BTG */ + rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ant_at_main_port = TRUE; + break; + case 3: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = FALSE; + break; + case 4: + rfe_type->ext_ant_switch_exist = TRUE; + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ + rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ant_at_main_port = FALSE; + break; + case 5: + rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 6: + rfe_type->ext_ant_switch_exist = FALSE; /*2-Ant, no switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = FALSE; + rfe_type->ant_at_main_port = TRUE; + break; + case 7: + rfe_type->ext_ant_switch_exist = TRUE; /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT; + rfe_type->wlg_Locate_at_btg = TRUE; + rfe_type->ant_at_main_port = TRUE; + break; + } +} + +void halbtc8821c2ant_set_ant_path(IN struct btc_coexist *btcoexist, + IN u8 ant_pos_type, IN boolean force_exec, + IN u8 phase) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u32 cnt_bt_cal_chk = 0; + boolean is_in_mp_mode = FALSE; + u8 u8tmp = 0; + u32 u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u16 u16tmp1 = 0; + + u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x38); + + /* To avoid indirect access fail */ + if (((u32tmp1 & 0xf000) >> 12) != ((u32tmp1 & 0x0f00) >> 8)) { + force_exec = TRUE; + coex_sta->gnt_error_cnt++; + } + +#if BT_8821C_2ANT_COEX_DBG + + u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0x54); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Ant Setup) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u8tmp, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf); +#endif + + coex_dm->cur_ant_pos_type = (ant_pos_type << 8) + phase; + + if (!force_exec) { + if (coex_dm->cur_ant_pos_type == coex_dm->pre_ant_pos_type) + return; + } + + coex_dm->pre_ant_pos_type = coex_dm->cur_ant_pos_type; + + switch (phase) { + case BT_8821C_2ANT_PHASE_COEX_POWERON: + + /* set Path control owner to WL at initial step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_2ANT_PCO_BTSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + coex_sta->run_time_state = FALSE; + + break; + case BT_8821C_2ANT_PHASE_COEX_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) */ + while (cnt_bt_cal_chk <= 20) { + u8tmp = btcoexist->btc_read_1byte( + btcoexist, 0x49c); + cnt_bt_cal_chk++; + + if (u8tmp & BIT(1)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* set Path control owner to WL at initial step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = FALSE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_WLANONLY_INIT: + /* Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* GNT_WL_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_WL_VS_LTE, + 0xffff); + + /* GNT_BT_LTE always = 1 (this should be config if LTE coex is required) */ + halbtc8821c2ant_ltecoex_set_coex_table( + btcoexist, + BT_8821C_2ANT_CTT_BT_VS_LTE, + 0xffff); + + /* set Path control owner to WL at initial step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Low */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_LOW); + /* Set GNT_WL to SW high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = FALSE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_WLAN_OFF: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to BT */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_BTSIDE); + + /* Set Ext Ant Switch to BT control at wifi off step */ + halbtc8821c2ant_set_ext_ant_switch(btcoexist, + FORCE_EXEC, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); + coex_sta->run_time_state = FALSE; + break; + case BT_8821C_2ANT_PHASE_2G_RUNTIME: + case BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT: + + while (cnt_bt_cal_chk <= 20) { + /* 0x49c[0]=1 WL IQK, 0x49c[1]=1 BT IQK*/ + u8tmp = btcoexist->btc_read_1byte(btcoexist, + 0x49c); + + cnt_bt_cal_chk++; + if (u8tmp & BIT(0)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### WL is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else if (u8tmp & BIT(1)) { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ########### BT is IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + delay_ms(50); + } else { + BTC_SPRINTF(trace_buf, + BT_TMP_BUF_SIZE, + "[BTCoex], ********** WL and BT is NOT IQK (wait cnt=%d)\n", + cnt_bt_cal_chk); + BTC_TRACE(trace_buf); + break; + } + } + + /* set Path control owner to WL at runtime step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + if (phase == + BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT) { + /* set GNT_BT to PTA */ + halbtc8821c2ant_ltecoex_set_gnt_bt( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to SW High */ + halbtc8821c2ant_ltecoex_set_gnt_wl( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + } else { + /* set GNT_BT to PTA */ + halbtc8821c2ant_ltecoex_set_gnt_bt( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to PTA */ + halbtc8821c2ant_ltecoex_set_gnt_wl( + btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + } + coex_sta->run_time_state = TRUE; + + if (rfe_type->wlg_Locate_at_btg) + halbtc8821c2ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG); + else + halbtc8821c2ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_5G_RUNTIME: + + /* set Path control owner to WL at runtime step */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA, + BT_8821C_2ANT_SIG_STA_SET_BY_HW); + + /* Set GNT_WL to SW Hi */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + coex_sta->run_time_state = TRUE; + + halbtc8821c2ant_set_int_block(btcoexist, + NORMAL_EXEC, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_BTMPMODE: + /* Disable LTE Coex Function in WiFi side */ + halbtc8821c2ant_ltecoex_enable(btcoexist, 0x0); + + /* set Path control owner to WL */ + halbtc8821c2ant_ltecoex_pathcontrol_owner( + btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to SW Hi */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + /* Set GNT_WL to SW Lo */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_LOW); + + coex_sta->run_time_state = FALSE; + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + break; + case BT_8821C_2ANT_PHASE_ANTENNA_DET: + halbtc8821c2ant_ltecoex_pathcontrol_owner(btcoexist, + BT_8821C_2ANT_PCO_WLSIDE); + + /* set GNT_BT to high */ + halbtc8821c2ant_ltecoex_set_gnt_bt(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + /* Set GNT_WL to high */ + halbtc8821c2ant_ltecoex_set_gnt_wl(btcoexist, + BT_8821C_2ANT_GNT_BLOCK_RFC_BB, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH); + + if (BTC_ANT_PATH_AUTO == ant_pos_type) { + if (board_info->btdm_ant_pos == + BTC_ANTENNA_AT_MAIN_PORT) + ant_pos_type = + BTC_ANT_WIFI_AT_MAIN; + else + ant_pos_type = + BTC_ANT_WIFI_AT_AUX; + } + + coex_sta->run_time_state = FALSE; + + break; + } + + if (phase != BT_8821C_2ANT_PHASE_WLAN_OFF) { + switch (ant_pos_type) { + default: + case BTC_ANT_WIFI_AT_MAIN + : + halbtc8821c2ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG); + break; + case BTC_ANT_WIFI_AT_AUX + : + halbtc8821c2ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT); + break; + case BTC_ANT_WIFI_AT_DIVERSITY + : + halbtc8821c2ant_set_ext_ant_switch( + btcoexist, + force_exec, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE); + break; + } + + } + +#if BT_8821C_2ANT_COEX_DBG + u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp = btcoexist->btc_read_1byte(btcoexist, 0x73); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (After Ant-Setup phase---%d) 0xcb4 = 0x%x, 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + phase, u32tmp3, u8tmp, u32tmp1, u32tmp2); + + BTC_TRACE(trace_buf); +#endif + +} + +u8 halbtc8821c2ant_action_algorithm(IN struct btc_coexist *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean bt_hs_on = FALSE; + u8 algorithm = BT_8821C_2ANT_COEX_ALGO_UNDEFINED; + u8 num_of_diff_profile = 0; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (!bt_link_info->bt_link_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No BT link exists!!!\n"); + BTC_TRACE(trace_buf); + return algorithm; + } + + if (bt_link_info->sco_exist) + num_of_diff_profile++; + if (bt_link_info->hid_exist) + num_of_diff_profile++; + if (bt_link_info->pan_exist) + num_of_diff_profile++; + if (bt_link_info->a2dp_exist) + num_of_diff_profile++; + + if (num_of_diff_profile == 0) { + + if (bt_link_info->acl_busy) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], No-Profile busy\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY; + } + } else if ((bt_link_info->a2dp_exist) && (coex_sta->is_bt_a2dp_sink)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP Sink\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_A2DPSINK; + } else if (num_of_diff_profile == 1) { + if (bt_link_info->sco_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; + } else { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_HID; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP only\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(HS) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], PAN(EDR) only\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR; + } + } + } + } else if (num_of_diff_profile == 2) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; + } else if (bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP ==> A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_A2DP; + } else if (bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_SCO; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP; + } + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } else if (num_of_diff_profile == 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->a2dp_exist) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP ==> HID + A2DP\n"); + BTC_TRACE(trace_buf); + algorithm = BT_8821C_2ANT_COEX_ALGO_HID_A2DP; + } else if (bt_link_info->hid_exist && + bt_link_info->pan_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID; + } + } else if (bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } else { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], HID + A2DP + PAN(EDR)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } else if (num_of_diff_profile >= 3) { + if (bt_link_info->sco_exist) { + if (bt_link_info->hid_exist && + bt_link_info->pan_exist && + bt_link_info->a2dp_exist) { + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n"); + BTC_TRACE(trace_buf); + algorithm = + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + + return algorithm; +} + +void halbtc8821c2ant_action_coex_all_off(IN struct btc_coexist *btcoexist) +{ + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + +} + +void halbtc8821c2ant_action_bt_whql_test(IN struct btc_coexist *btcoexist) +{ + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); +} + +void halbtc8821c2ant_action_bt_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } + +} + +void halbtc8821c2ant_action_bt_inquiry(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_connected = FALSE; + boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE; + boolean wifi_busy = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((coex_sta->bt_create_connection) && ((wifi_link) || (wifi_roam) + || (wifi_scan) || (wifi_busy) || (coex_sta->wifi_is_high_pri_task))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi link/roam/Scan/busy/hi-pri-task + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, + 8); + + if ((bt_link_info->a2dp_exist) && (!bt_link_info->pan_exist)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 15); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 11); + } else if ((!wifi_connected) && (!wifi_scan)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Wifi no-link + no-scan + BT Inq/Page!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (bt_link_info->pan_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } else { + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || (wifi_busy) + || (coex_sta->wifi_is_high_pri_task)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 23); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c2ant_action_bt_relink(IN struct btc_coexist *btcoexist) +{ + if (coex_sta->is_bt_multi_link == TRUE) + return; + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); +} + +void halbtc8821c2ant_action_bt_idle(IN struct btc_coexist *btcoexist) +{ + + boolean wifi_busy = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + if (!wifi_busy) { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 14); + } else { /* if wl busy */ + + if (BT_8821C_1ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 8); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 12); + } + } + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + +} + +/* SCO only or SCO+PAN(HS) */ +void halbtc8821c2ant_action_sco(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + if (coex_sta->is_eSCO_mode) + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 1); + else /* 2-Ant free run if SCO mode */ + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 8); + } + +} + +void halbtc8821c2ant_action_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, &wifi_bw); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + if (coex_sta->is_hid_low_pri_tx_overhead) { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 4); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 108); + } else if (wifi_bw == 0) { /* if 11bg mode */ + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 111); + } else { + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 111); + } + } + +} + +void halbtc8821c2ant_action_a2dpsink(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 1); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 16); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + } else { + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 105); + } + + } + +} + +/* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ +void halbtc8821c2ant_action_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 1); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 16); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + + } else { + + if (wifi_turbo) + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 7); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 101); + } + } + +} + +void halbtc8821c2ant_action_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 3); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 4); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 103); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 104); + } +} + +void halbtc8821c2ant_action_hid_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 1); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 16); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if ((coex_sta->bt_relink_downcount != 0) + && (wifi_busy)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Re-Link + A2DP + WL busy\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 5); + } else { + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 8); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 109); + } + } + +} + +void halbtc8821c2ant_action_a2dp_pan_hs(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 7); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + if (wifi_turbo) + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 6); + else + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 7); + + if (wifi_busy) { + + if ((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 107); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 105); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 106); + + } + +} + +/* PAN(EDR)+A2DP */ +void halbtc8821c2ant_action_pan_edr_a2dp(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE, wifi_turbo = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], scan_ap_num = %d, wl_noisy = %d\n", + coex_sta->scan_ap_num, coex_sta->wl_noisy_level); + BTC_TRACE(trace_buf); + + if ((wifi_busy) && (coex_sta->wl_noisy_level == 0)) + wifi_turbo = TRUE; + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 7); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, + 8); + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 107); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 106); + } + +} + +void halbtc8821c2ant_action_pan_edr_hid(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 3); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 4); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 103); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 104); + } + +} + +/* HID+A2DP+PAN(EDR) */ +void halbtc8821c2ant_action_hid_a2dp_pan_edr(IN struct btc_coexist *btcoexist) +{ + static u8 prewifi_rssi_state = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state, bt_rssi_state; + + static u8 prewifi_rssi_state2 = BTC_RSSI_STATE_LOW; + static u8 pre_bt_rssi_state2 = BTC_RSSI_STATE_LOW; + u8 wifi_rssi_state2, bt_rssi_state2; + boolean wifi_busy = FALSE; + u32 wifi_bw = 1; + + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_BW, + &wifi_bw); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, &wifi_busy); + + wifi_rssi_state = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state, 2, + coex_sta->wifi_coex_thres, 0); + + wifi_rssi_state2 = halbtc8821c2ant_wifi_rssi_state(btcoexist, + &prewifi_rssi_state2, 2, + coex_sta->wifi_coex_thres2, 0); + + bt_rssi_state = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state, 2, + coex_sta->bt_coex_thres, 0); + + bt_rssi_state2 = halbtc8821c2ant_bt_rssi_state(btcoexist, + &pre_bt_rssi_state2, 2, + coex_sta->bt_coex_thres2, 0); + + if (BTC_RSSI_HIGH(wifi_rssi_state) && + BTC_RSSI_HIGH(bt_rssi_state)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + } else if (BTC_RSSI_HIGH(wifi_rssi_state2) && + BTC_RSSI_HIGH(bt_rssi_state2)) { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xc8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 2); + + coex_dm->is_switch_to_1dot5_ant = FALSE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 4); + + if (wifi_busy) { + + if (((coex_sta->a2dp_bit_pool > 40) && + (coex_sta->a2dp_bit_pool < 255)) || + (!coex_sta->is_A2DP_3M)) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 7); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, + TRUE, 5); + } else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 6); + } else { + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_dm->is_switch_to_1dot5_ant = TRUE; + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + if (wifi_busy) + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 107); + else + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, + 106); + } + } + +void halbtc8821c2ant_action_wifi_under5g(IN struct btc_coexist *btcoexist) +{ + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, NORMAL_EXEC, + BT_8821C_2ANT_PHASE_5G_RUNTIME); +} + +void halbtc8821c2ant_action_wifi_native_lps(IN struct btc_coexist *btcoexist) +{ + halbtc8821c2ant_coex_table_with_type(btcoexist, + NORMAL_EXEC, 2); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); +} + +void halbtc8821c2ant_action_wifi_multi_port(IN struct btc_coexist *btcoexist) +{ + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + /* hw all off */ + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); +} +void halbtc8821c2ant_action_wifi_linkscan_process(IN struct btc_coexist + *btcoexist) +{ + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, FORCE_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + if (bt_link_info->pan_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 22); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + + } else if (bt_link_info->a2dp_exist) { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 16); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } else { + + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, TRUE, 21); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 8); + } + +} + +void halbtc8821c2ant_action_wifi_not_connected(IN struct btc_coexist *btcoexist) +{ + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); +} + +void halbtc8821c2ant_action_wifi_connected(IN struct btc_coexist *btcoexist) +{ + switch (coex_dm->cur_algorithm) { + + case BT_8821C_2ANT_COEX_ALGO_SCO: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = SCO.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_sco(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_hid(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_a2dp(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_A2DPSINK: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP Sink.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_a2dpsink(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_a2dp_pan_hs(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_pan_edr(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_pan_edr_a2dp(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_PANEDR_HID: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_pan_edr_hid(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_hid_a2dp_pan_edr( + btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_HID_A2DP: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_hid_a2dp(btcoexist); + break; + case BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = No-Profile busy.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_idle(btcoexist); + break; + default: + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_coex_all_off(btcoexist); + break; + } + + coex_dm->pre_algorithm = coex_dm->cur_algorithm; + +} + +void halbtc8821c2ant_run_coexist_mechanism(IN struct btc_coexist *btcoexist) +{ + u8 algorithm = 0; + u32 num_of_wifi_link = 0; + u32 wifi_link_status = 0; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + boolean miracast_plus_bt = FALSE; + boolean scan = FALSE, link = FALSE, roam = FALSE, + under_4way = FALSE, + wifi_connected = FALSE, wifi_under_5g = + FALSE, + bt_hs_on = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &roam); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism()===>\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (btcoexist->stop_coex_dm) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->under_ips) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under IPS !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if ((coex_sta->under_lps) && + (coex_dm->bt_status != BT_8821C_2ANT_BT_STATUS_ACL_BUSY)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RunCoexistMechanism(), wifi is under LPS !!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_native_lps(btcoexist); + return; + } + + if (!coex_sta->run_time_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], return for run_time_state = FALSE !!!\n"); + BTC_TRACE(trace_buf); + return; + } + + if (coex_sta->freeze_coexrun_by_btinfo) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BtInfoNotify(), return for freeze_coexrun_by_btinfo\n"); + BTC_TRACE(trace_buf); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((wifi_under_5g) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G) && + (coex_sta->switch_band_notify_to != BTC_SWITCH_TO_24G_NOFORSCAN)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 2G!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + NORMAL_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + } + + if (coex_sta->bt_whck_test) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under WHCK TEST!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_whql_test(btcoexist); + return; + } + + if (coex_sta->bt_disabled) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is disabled!!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_coex_all_off(btcoexist); + return; + } + + if (coex_sta->c2h_bt_inquiry_page) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is under inquiry/page scan !!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_inquiry(btcoexist); + return; + } + + if (coex_sta->is_setupLink) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT is re-link !!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_relink(btcoexist); + return; + } + + /* for P2P */ + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_LINK_STATUS, + &wifi_link_status); + num_of_wifi_link = wifi_link_status >> 16; + + if ((num_of_wifi_link >= 2) || + (wifi_link_status & WIFI_P2P_GO_CONNECTED)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], Multi-Port num_of_wifi_link = %d, wifi_link_status = 0x%x\n", + num_of_wifi_link, wifi_link_status); + BTC_TRACE(trace_buf); + + if (bt_link_info->bt_link_exist) + miracast_plus_bt = TRUE; + else + miracast_plus_bt = FALSE; + + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], scan = %d, link = %d, roam = %d 4way = %d!!!\n", + scan, link, roam, under_4way); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], wifi is under linkscan process + Multi-Port !!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); + } else + halbtc8821c2ant_action_wifi_multi_port(btcoexist); + + return; + } else { + miracast_plus_bt = FALSE; + btcoexist->btc_set(btcoexist, BTC_SET_BL_MIRACAST_PLUS_BT, + &miracast_plus_bt); + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_HS_OPERATION, &bt_hs_on); + + if (bt_hs_on) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "############# [BTCoex], BT Is hs\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_bt_hs(btcoexist); + return; + } + + if ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) || + (BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == + coex_dm->bt_status)) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, bt idle!!.\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_bt_idle(btcoexist); + return; + } + + algorithm = halbtc8821c2ant_action_algorithm(btcoexist); + coex_dm->cur_algorithm = algorithm; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Algorithm = %d\n", + coex_dm->cur_algorithm); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + if (scan || link || roam || under_4way) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under Link Process !!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_linkscan_process(btcoexist); + } else if (wifi_connected) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, wifi connected!!.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_connected(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Action 2-Ant, wifi not-connected!!.\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_action_wifi_not_connected(btcoexist); + } +} + +void halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Coex Mechanism Init!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_low_penalty_ra(btcoexist, NORMAL_EXEC, FALSE); + + halbtc8821c2ant_coex_table_with_type(btcoexist, NORMAL_EXEC, 0); + + /* fw all off */ + halbtc8821c2ant_ps_tdma(btcoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8821c2ant_fw_dac_swing_lvl(btcoexist, NORMAL_EXEC, 0xd8); + halbtc8821c2ant_dec_bt_pwr(btcoexist, NORMAL_EXEC, 0); + + coex_sta->pop_event_cnt = 0; + coex_sta->cnt_RemoteNameReq = 0; + coex_sta->cnt_ReInit = 0; + coex_sta->cnt_setupLink = 0; + coex_sta->cnt_IgnWlanAct = 0; + coex_sta->cnt_Page = 0; + coex_sta->cnt_RoleSwitch = 0; + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; + + halbtc8821c2ant_query_bt_info(btcoexist); +} + +void halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + u8 u8tmp = 0; + u32 vendor; + u32 u32tmp0 = 0, u32tmp1 = 0, u32tmp2 = 0, u32tmp3 = 0; + u8 i; + + u32tmp3 = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u32tmp1 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp2 = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], (Before Init HW config) 0xcb4 = 0x%x, 0x38= 0x%x, 0x54= 0x%x\n", + u32tmp3, u32tmp1, u32tmp2); + BTC_TRACE(trace_buf);; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], 2Ant Init HW Config!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->bt_coex_supported_feature = 0; + coex_sta->bt_coex_supported_version = 0; + coex_sta->bt_ble_scan_type = 0; + coex_sta->bt_ble_scan_para[0] = 0; + coex_sta->bt_ble_scan_para[1] = 0; + coex_sta->bt_ble_scan_para[2] = 0; + coex_sta->bt_reg_vendor_ac = 0xffff; + coex_sta->bt_reg_vendor_ae = 0xffff; + coex_sta->isolation_btween_wb = BT_8821C_2ANT_DEFAULT_ISOLATION; + coex_sta->gnt_error_cnt = 0; + coex_sta->bt_relink_downcount = 0; + coex_sta->is_set_ps_state_fail = FALSE; + coex_sta->cnt_set_ps_state_fail = 0; + + for (i = 0; i <= 9; i++) + coex_sta->bt_afh_map[i] = 0; + + /* 0xf0[15:12] --> Chip Cut information */ + coex_sta->cut_version = (btcoexist->btc_read_1byte(btcoexist, + 0xf1) & 0xf0) >> 4; + + coex_sta->dis_ver_info_cnt = 0; + + halbtc8821c2ant_coex_switch_threshold(btcoexist, + coex_sta->isolation_btween_wb); + + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x550, 0x8, + 0x1); /* enable TBTT nterrupt */ + + /* BT report packet sample rate */ + btcoexist->btc_write_1byte(btcoexist, 0x790, 0x5); + + /* Init 0x778 = 0x1 for 2-Ant */ + btcoexist->btc_write_1byte(btcoexist, 0x778, 0x1); + + /* Enable PTA (3-wire function form BT side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x40, 0x20, 0x1); + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x41, 0x02, 0x1); + + /* Enable PTA (tx/rx signal form WiFi side) */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x4c6, 0x10, 0x1); + + /* set GNT_BT=1 for coex table select both */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x763, 0x10, 0x1); + + halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, TRUE); + + /* Enable counter statistics */ + btcoexist->btc_write_1byte(btcoexist, 0x76e, + 0x4); /* 0x76e[3] =1, WLAN_Act control by PTA */ + + /* WLAN_Tx by GNT_WL 0x950[29] = 0 */ + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x20, 0x0); */ + + halbtc8821c2ant_coex_table_with_type(btcoexist, FORCE_EXEC, 0); + + halbtc8821c2ant_ps_tdma(btcoexist, FORCE_EXEC, FALSE, 0); + + psd_scan->ant_det_is_ant_det_available = TRUE; + + if (coex_sta->is_rf_state_off) { + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + + btcoexist->stop_coex_dm = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** halbtc8821c2ant_init_hw_config (RF Off)**********\n"); + BTC_TRACE(trace_buf); + } else if (wifi_only) { + coex_sta->concurrent_rx_mode_on = FALSE; + /* Path config */ + /* Set Antenna Path */ + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLANONLY_INIT); + + btcoexist->stop_coex_dm = TRUE; + } else { + /*Set BT polluted packet on for Tx rate adaptive not including Tx retry break by PTA, 0x45c[19] =1 */ + btcoexist->btc_write_1byte_bitmask(btcoexist, 0x45e, 0x8, 0x1); + + coex_sta->concurrent_rx_mode_on = TRUE; + /* btcoexist->btc_write_1byte_bitmask(btcoexist, 0x953, 0x2, 0x1); */ + + /* RF 0x1[1] = 0->Set GNT_WL_RF_Rx always = 1 for con-current Rx, mask Tx only */ + btcoexist->btc_set_rf_reg(btcoexist, BTC_RF_A, 0x1, 0x2, 0x0); + + /* Set Antenna Path */ + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_COEX_INIT); + + btcoexist->stop_coex_dm = FALSE; + } + +} + +/* ************************************************************ + * work around function start with wa_halbtc8821c2ant_ + * ************************************************************ + * ************************************************************ + * extern function start with ex_halbtc8821c2ant_ + * ************************************************************ */ +void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x0; + u16 u16tmp = 0x0; + u32 value = 0; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "xxxxxxxxxxxxxxxx Execute 8821c 2-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n"); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "Ant Det Finish = %s, Ant Det Number = %d\n", + (board_info->btdm_ant_det_finish ? "Yes" : "No"), + board_info->btdm_ant_num_by_ant_det); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = FALSE; + psd_scan->ant_det_is_ant_det_available = FALSE; + + /* enable BB, REG_SYS_FUNC_EN such that we can write BB Register correctly. */ + u16tmp = btcoexist->btc_read_2byte(btcoexist, 0x2); + btcoexist->btc_write_2byte(btcoexist, 0x2, u16tmp | BIT(0) | BIT(1)); + + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + + /* Check efuse 0xc3[6] for Single Antenna Path */ + if (board_info->single_ant_path == 0) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Aux Port\n"); + BTC_TRACE(trace_buf); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_AUX_PORT; + + u8tmp = 7; + } else if (board_info->single_ant_path == 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** Single Antenna, Antenna at Main Port\n"); + BTC_TRACE(trace_buf); + + board_info->btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + + u8tmp = 6; + } + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** (Power On) single_ant_path = %d, btdm_ant_pos = %d\n", + board_info->single_ant_path , board_info->btdm_ant_pos); + BTC_TRACE(trace_buf); + + /* Setup RF front end type */ + halbtc8821c2ant_set_rfe_type(btcoexist); + + /* Set Antenna Path to BT side */ + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_COEX_POWERON); + + /* Save"single antenna position" info in Local register setting for FW reading, because FW may not ready at power on */ + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_USB) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, u8tmp); + + /* enable GNT_WL/GNT_BT debug signal to GPIO14/15 */ + halbtc8821c2ant_enable_gnt_to_gpio(btcoexist, TRUE); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", + halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38)); + BTC_TRACE(trace_buf); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** MAC Reg 0x70/ BB Reg 0xcb4 (Power-On) = 0x%x / 0x%x\n", + btcoexist->btc_read_4byte(btcoexist, 0x70), + btcoexist->btc_read_4byte(btcoexist, 0xcb4)); + BTC_TRACE(trace_buf); + +} + +void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + u8 u8tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ + + /* */ + /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ + /* Local setting bit define */ + /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ + /* BIT1: "0" for internal switch; "1" for external switch */ + /* BIT2: "0" for one antenna; "1" for two antenna */ + /* NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 */ + if (btcoexist->chip_interface == BTC_INTF_USB) { + /* fixed at S0 for USB interface */ + u8tmp |= 0x1; /* antenna inverse */ + btcoexist->btc_write_local_reg_1byte(btcoexist, 0xfe08, u8tmp); + } else { + /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ + if (board_info->single_ant_path == 0) { + } else if (board_info->single_ant_path == 1) { + /* set to S0 */ + u8tmp |= 0x1; /* antenna inverse */ + } + + if (btcoexist->chip_interface == BTC_INTF_PCI) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x3e0, + u8tmp); + else if (btcoexist->chip_interface == BTC_INTF_SDIO) + btcoexist->btc_write_local_reg_1byte(btcoexist, 0x60, + u8tmp); + } +} + +void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only) +{ + halbtc8821c2ant_init_hw_config(btcoexist, wifi_only); +} + +void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist) +{ + + halbtc8821c2ant_init_coex_dm(btcoexist); +} + +void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + struct btc_bt_link_info *bt_link_info = &btcoexist->bt_link_info; + + u8 *cli_buf = btcoexist->cli_buf; + u8 u8tmp[4], i, ps_tdma_case = 0; + u32 u32tmp[4]; + u16 u16tmp[4]; + u32 fa_ofdm, fa_cck, cca_ofdm, cca_cck, ratio_ofdm; + u32 fw_ver = 0, bt_patch_ver = 0, bt_coex_ver = 0; + static u8 pop_report_in_10s = 0; + u32 phyver = 0; + boolean lte_coex_on = FALSE; + static u8 cnt = 0; + u32 ratio_crc, cnt_ok, cnt_err; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cli_buf); + + if (btcoexist->manual_control) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cli_buf); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n =========================================="); + CL_PRINTF(cli_buf); + } + + if (!coex_sta->bt_disabled) { + if (coex_sta->bt_coex_supported_feature == 0) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_FEATURE, + &coex_sta->bt_coex_supported_feature); + + if ((coex_sta->bt_coex_supported_version == 0) || + (coex_sta->bt_coex_supported_version == 0xffff)) + btcoexist->btc_get(btcoexist, BTC_GET_U4_SUPPORTED_VERSION, + &coex_sta->bt_coex_supported_version); + + if (coex_sta->bt_reg_vendor_ac == 0xffff) + coex_sta->bt_reg_vendor_ac = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xac) & 0xffff); + + if (coex_sta->bt_reg_vendor_ae == 0xffff) + coex_sta->bt_reg_vendor_ae = (u16)( + btcoexist->btc_get_bt_reg(btcoexist, 3, + 0xae) & 0xffff); + + btcoexist->btc_get(btcoexist, BTC_GET_U4_BT_PATCH_VER, + &bt_patch_ver); + btcoexist->bt_info.bt_get_fw_ver = bt_patch_ver; + + if (coex_sta->num_of_profile > 0) { + cnt++; + + if (cnt >= 3) { + btcoexist->btc_get_bt_afh_map_from_bt(btcoexist, 0, + &coex_sta->bt_afh_map[0]); + cnt = 0; + } + } + } + + if (psd_scan->ant_det_try_count == 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s / %d", + "Ant PG Num/ Mech/ Pos/ RFE", + board_info->pg_ant_num, board_info->btdm_ant_num, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type); + CL_PRINTF(cli_buf); + } else { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %s/ %d (%d/%d/%d)", + "Ant PG Num/ Mech(Ant_Det)/ Pos/ RFE", + board_info->pg_ant_num, + board_info->btdm_ant_num_by_ant_det, + (board_info->btdm_ant_pos == BTC_ANTENNA_AT_MAIN_PORT + ? "Main" : "Aux"), + rfe_type->rfe_module_type, + psd_scan->ant_det_try_count, + psd_scan->ant_det_fail_count, + psd_scan->ant_det_result); + CL_PRINTF(cli_buf); + + if (board_info->btdm_ant_det_finish) { + + if (psd_scan->ant_det_result != 12) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s", + "Ant Det PSD Value", + psd_scan->ant_det_peak_val); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d", + "Ant Det PSD Value", + psd_scan->ant_det_psd_scan_peak_val + / 100); + CL_PRINTF(cli_buf); + } + } + + bt_patch_ver = btcoexist->bt_info.bt_get_fw_ver; + btcoexist->btc_get(btcoexist, BTC_GET_U4_WIFI_FW_VER, &fw_ver); + phyver = btcoexist->btc_get_bt_phydm_version(btcoexist); + + bt_coex_ver = (coex_sta->bt_coex_supported_version & 0xff); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d_%02x/ 0x%02x/ 0x%02x (%s)", + "CoexVer WL/ BT_Desired/ BT_Report", + glcoex_ver_date_8821c_2ant, glcoex_ver_8821c_2ant, + glcoex_ver_btdesired_8821c_2ant, + bt_coex_ver, + (bt_coex_ver == 0xff ? "Unknown" : + (coex_sta->bt_disabled ? "BT-disable" : + (bt_coex_ver >= glcoex_ver_btdesired_8821c_2ant ? + "Match" : "Mis-Match")))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ v%d/ %c", + "W_FW/ B_FW/ Phy/ Kt", + fw_ver, bt_patch_ver, phyver, + coex_sta->cut_version + 65); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", + "AFH Map to BT", + coex_dm->wifi_chnl_info[0], coex_dm->wifi_chnl_info[1], + coex_dm->wifi_chnl_info[2]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d ", + "Isolation/WL_Thres/BT_Thres", + coex_sta->isolation_btween_wb, + coex_sta->wifi_coex_thres, + coex_sta->bt_coex_thres); + CL_PRINTF(cli_buf); + + /* wifi status */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Wifi Status]============"); + CL_PRINTF(cli_buf); + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[BT Status]============"); + CL_PRINTF(cli_buf); + + pop_report_in_10s++; + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = [%s/ %d dBm/ %d/ %d] ", + "BT [status/ rssi/ retryCnt/ popCnt]", + ((coex_sta->bt_disabled) ? ("disabled") : (( + coex_sta->c2h_bt_inquiry_page) ? ("inquiry/page") + : ((BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE == + coex_dm->bt_status) ? "non-connected idle" : + ((BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE == coex_dm->bt_status) + ? "connected-idle" : "busy")))), + coex_sta->bt_rssi - 100, coex_sta->bt_retry_cnt, + coex_sta->pop_event_cnt); + CL_PRINTF(cli_buf); + + if (pop_report_in_10s >= 5) { + coex_sta->pop_event_cnt = 0; + pop_report_in_10s = 0; + } + + if (coex_sta->num_of_profile != 0) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s%s%s%s%s", + "Profiles", + ((bt_link_info->a2dp_exist) ? + ((coex_sta->is_bt_a2dp_sink) ? "A2DP sink," : + "A2DP,") : ""), + ((bt_link_info->sco_exist) ? "HFP," : ""), + ((bt_link_info->hid_exist) ? + ((coex_sta->hid_busy_num >= 2) ? "HID(4/18)," : + "HID(2/18),") : ""), + ((bt_link_info->pan_exist) ? "PAN," : ""), + ((coex_sta->voice_over_HOGP) ? "Voice" : "")); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = None", "Profiles"); + + CL_PRINTF(cli_buf); + + if (bt_link_info->a2dp_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s", + "A2DP Rate/Bitpool/Auto_Slot", + ((coex_sta->is_A2DP_3M) ? "3M" : "No_3M"), + coex_sta->a2dp_bit_pool, + ((coex_sta->is_autoslot) ? "On" : "Off") + ); + CL_PRINTF(cli_buf); + } + + if (bt_link_info->hid_exist) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "HID PairNum/Forbid_Slot", + coex_sta->hid_pair_cnt, + coex_sta->forbidden_slot + ); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d/ %s/ 0x%x", + "Role/RoleSwCnt/IgnWlact/Feature", + ((bt_link_info->slave_role) ? "Slave" : "Master"), + coex_sta->cnt_RoleSwitch, + ((coex_dm->cur_ignore_wlan_act) ? "Yes" : "No"), + coex_sta->bt_coex_supported_feature); + CL_PRINTF(cli_buf); + + if ((coex_sta->bt_ble_scan_type & 0x7) != 0x0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "BLEScan Type/TV/Init/Ble", + coex_sta->bt_ble_scan_type, + (coex_sta->bt_ble_scan_type & 0x1 ? + coex_sta->bt_ble_scan_para[0] : 0x0), + (coex_sta->bt_ble_scan_type & 0x2 ? + coex_sta->bt_ble_scan_para[1] : 0x0), + (coex_sta->bt_ble_scan_type & 0x4 ? + coex_sta->bt_ble_scan_para[2] : 0x0)); + CL_PRINTF(cli_buf); + } + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", + "ReInit/ReLink/IgnWlact/Page/NameReq", + coex_sta->cnt_ReInit, + coex_sta->cnt_setupLink, + coex_sta->cnt_IgnWlanAct, + coex_sta->cnt_Page, + coex_sta->cnt_RemoteNameReq + ); + CL_PRINTF(cli_buf); + + halbtc8821c2ant_read_score_board(btcoexist, &u16tmp[0]); + + if ((coex_sta->bt_reg_vendor_ae == 0xffff) || + (coex_sta->bt_reg_vendor_ac == 0xffff)) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = x/ x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", u16tmp[0]); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %04x", + "0xae[4]/0xac[1:0]/Scoreboard", + ((coex_sta->bt_reg_vendor_ae & BIT(4)) >> 4), + coex_sta->bt_reg_vendor_ac & 0x3, u16tmp[0]); + CL_PRINTF(cli_buf); + + if (coex_sta->num_of_profile > 0) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x", + "AFH MAP", + coex_sta->bt_afh_map[0], + coex_sta->bt_afh_map[1], + coex_sta->bt_afh_map[2], + coex_sta->bt_afh_map[3], + coex_sta->bt_afh_map[4], + coex_sta->bt_afh_map[5], + coex_sta->bt_afh_map[6], + coex_sta->bt_afh_map[7], + coex_sta->bt_afh_map[8], + coex_sta->bt_afh_map[9] + ); + CL_PRINTF(cli_buf); + } + + for (i = 0; i < BT_INFO_SRC_8821C_2ANT_MAX; i++) { + if (coex_sta->bt_info_c2h_cnt[i]) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", + glbt_info_src_8821c_2ant[i], + coex_sta->bt_info_c2h[i][0], + coex_sta->bt_info_c2h[i][1], + coex_sta->bt_info_c2h[i][2], + coex_sta->bt_info_c2h[i][3], + coex_sta->bt_info_c2h[i][4], + coex_sta->bt_info_c2h[i][5], + coex_sta->bt_info_c2h[i][6], + coex_sta->bt_info_c2h_cnt[i]); + CL_PRINTF(cli_buf); + } + } + + /* Sw mechanism */ + if (btcoexist->manual_control) + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[mechanism] (before Manual)============"); + else + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Mechanism]============"); + + CL_PRINTF(cli_buf); + + ps_tdma_case = coex_dm->cur_ps_tdma; + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %02x %02x %02x %02x %02x (case-%d, %s, %s)", + "TDMA", + coex_dm->ps_tdma_para[0], coex_dm->ps_tdma_para[1], + coex_dm->ps_tdma_para[2], coex_dm->ps_tdma_para[3], + coex_dm->ps_tdma_para[4], ps_tdma_case, + (coex_dm->cur_ps_tdma_on ? "TDMA On" : "TDMA Off"), + (coex_dm->is_switch_to_1dot5_ant ? "1.5Ant" : "2Ant")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6c0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0x6c4); + u32tmp[2] = btcoexist->btc_read_4byte(btcoexist, 0x6c8); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ 0x%x/ 0x%x/ 0x%x", + "Table/0x6c0/0x6c4/0x6c8", + coex_sta->coex_table_type, u32tmp[0], u32tmp[1], u32tmp[2]); + CL_PRINTF(cli_buf); + + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x778); + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x6cc); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x", + "0x778/0x6cc", + u8tmp[0], u32tmp[0]); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "AntDiv/BtCtrlLPS/LPRA/PsFail", + ((board_info->ant_div_cfg) ? "On" : "Off"), + ((coex_sta->force_lps_ctrl) ? "On" : "Off"), + ((coex_dm->cur_low_penalty_ra) ? "On" : "Off"), + coex_sta->cnt_set_ps_state_fail); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "WL_DACSwing/ BT_Dec_Pwr", coex_dm->cur_fw_dac_swing_lvl, + coex_dm->cur_bt_dec_pwr_lvl); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + lte_coex_on = ((u32tmp[0] & BIT(7)) >> 7) ? TRUE : FALSE; + + if (lte_coex_on) { + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa0); + u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", + "LTE Coex Table W_L/B_L", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xa8); + u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xac); + u32tmp[2] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb0); + u32tmp[3] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, + 0xb4); + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "LTE Break Table W_L/B_L/L_W/L_B", + u32tmp[0] & 0xffff, u32tmp[1] & 0xffff, + u32tmp[2] & 0xffff, u32tmp[3] & 0xffff); + CL_PRINTF(cli_buf); + + } + + /* Hw setting */ + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s", + "============[Hw setting]============"); + CL_PRINTF(cli_buf); + + u32tmp[0] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x38); + u32tmp[1] = halbtc8821c2ant_ltecoex_indirect_read_reg(btcoexist, 0x54); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x73); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", + "LTE Coex/Path Owner", + ((lte_coex_on) ? "On" : "Off") , + ((u8tmp[0] & BIT(2)) ? "WL" : "BT")); + CL_PRINTF(cli_buf); + + if (lte_coex_on) { + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %d/ %d/ %d/ %d", + "LTE 3Wire/OPMode/UART/UARTMode", + (int)((u32tmp[0] & BIT(6)) >> 6), + (int)((u32tmp[0] & (BIT(5) | BIT(4))) >> 4), + (int)((u32tmp[0] & BIT(3)) >> 3), + (int)(u32tmp[0] & (BIT(2) | BIT(1) | BIT(0)))); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "LTE_Busy/UART_Busy", + (int)((u32tmp[1] & BIT(1)) >> 1), + (int)(u32tmp[1] & BIT(0))); + CL_PRINTF(cli_buf); + } + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = %s (BB:%s)/ %s (BB:%s)/ %s %d", + "GNT_WL_Ctrl/GNT_BT_Ctrl/Dbg", + ((u32tmp[0] & BIT(12)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(8)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(14)) ? "SW" : "HW"), + ((u32tmp[0] & BIT(10)) ? "SW" : "HW"), + ((u8tmp[0] & BIT(3)) ? "On" : "Off"), + coex_sta->gnt_error_cnt); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "GNT_WL/GNT_BT", + (int)((u32tmp[1] & BIT(2)) >> 2), + (int)((u32tmp[1] & BIT(3)) >> 3)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0xcb0); + u32tmp[1] = btcoexist->btc_read_4byte(btcoexist, 0xcb4); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0xcba); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%04x/ 0x%04x/ 0x%02x %s", + "0xcb0/0xcb4/0xcb8[23:16]", + u32tmp[0], u32tmp[1], u8tmp[0], + ((u8tmp[0] & 0x1) == 0x1 ? "(BTG)" : "(WL_A+G)")); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x4c); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0x64); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x4c6); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x40); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", + "4c[24:23]/64[0]/4c6[4]/40[5]", + (u32tmp[0] & (BIT(24) | BIT(23))) >> 23 , u8tmp[2] & 0x1 , + (int)((u8tmp[0] & BIT(4)) >> 4), + (int)((u8tmp[1] & BIT(5)) >> 5)); + CL_PRINTF(cli_buf); + + u32tmp[0] = btcoexist->btc_read_4byte(btcoexist, 0x550); + u8tmp[0] = btcoexist->btc_read_1byte(btcoexist, 0x522); + u8tmp[1] = btcoexist->btc_read_1byte(btcoexist, 0x953); + u8tmp[2] = btcoexist->btc_read_1byte(btcoexist, 0xc50); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ %s/ 0x%x", + "0x550/0x522/4-RxAGC/0xc50", + u32tmp[0], u8tmp[0], (u8tmp[1] & 0x2) ? "On" : "Off", u8tmp[2]); + CL_PRINTF(cli_buf); + + fa_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_OFDM); + fa_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_FA_CCK); + cca_ofdm = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_OFDM); + cca_cck = btcoexist->btc_phydm_query_PHY_counter(btcoexist, + PHYDM_INFO_CCA_CCK); + + ratio_ofdm = (fa_ofdm == 0) ? 1000 : (cca_ofdm/fa_ofdm); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, + "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x (%d)", + "CCK-CCA/CCK-FA/OFDM-CCA/OFDM-FA", + cca_cck, fa_cck, cca_ofdm, fa_ofdm, + ratio_ofdm); + CL_PRINTF(cli_buf); + + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", + "CRC_OK CCK/11g/11n/11ac", + coex_sta->crc_ok_cck, coex_sta->crc_ok_11g, + coex_sta->crc_ok_11n, coex_sta->crc_ok_11n_vht); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d (%d, %d)", + "CRC_Err CCK/11g/11n/11ac", + coex_sta->crc_err_cck, coex_sta->crc_err_11g, + coex_sta->crc_err_11n, coex_sta->crc_err_11n_vht, + coex_sta->now_crc_ratio, coex_sta->acc_crc_ratio); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s/ %d", + "WlHiPri/ Locking/ Locked/ Noisy", + (coex_sta->wifi_is_high_pri_task ? "Yes" : "No"), + (coex_sta->cck_lock ? "Yes" : "No"), + (coex_sta->cck_ever_lock ? "Yes" : "No"), + coex_sta->wl_noisy_level); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", + "0x770(Hi-pri rx/tx)", + coex_sta->high_priority_rx, coex_sta->high_priority_tx); + CL_PRINTF(cli_buf); + + CL_SPRINTF(cli_buf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d %s", + "0x774(Lo-pri rx/tx)", + coex_sta->low_priority_rx, coex_sta->low_priority_tx, + (bt_link_info->slave_role ? "(Slave!!)" : ( + coex_sta->is_tdma_btautoslot_hang ? "(auto-slot hang!!)" : ""))); + CL_PRINTF(cli_buf); + + btcoexist->btc_disp_dbg_msg(btcoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + +void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_IPS_ENTER == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS ENTER notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = TRUE; + coex_sta->under_lps = FALSE; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + FALSE); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + + halbtc8821c2ant_action_coex_all_off(btcoexist); + } else if (BTC_IPS_LEAVE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], IPS LEAVE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_ips = FALSE; + + halbtc8821c2ant_init_hw_config(btcoexist, FALSE); + halbtc8821c2ant_init_coex_dm(btcoexist); + halbtc8821c2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, IN u8 type) +{ + static boolean pre_force_lps_on = FALSE; + + if (btcoexist->manual_control || btcoexist->stop_coex_dm) + return; + + if (BTC_LPS_ENABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS ENABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = TRUE; + coex_sta->under_ips = FALSE; + + if (coex_sta->force_lps_ctrl == TRUE) { /* LPS No-32K */ + /* Write WL "Active" in Score-board for PS-TDMA */ + pre_force_lps_on = TRUE; + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, TRUE); + + } else { /* LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) */ + /* Write WL "Non-Active" in Score-board for Native-PS */ + pre_force_lps_on = FALSE; + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, FALSE); + } + + } else if (BTC_LPS_DISABLE == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], LPS DISABLE notify\n"); + BTC_TRACE(trace_buf); + coex_sta->under_lps = FALSE; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, TRUE); + + if ((!pre_force_lps_on) && (!coex_sta->force_lps_ctrl)) + halbtc8821c2ant_query_bt_info(btcoexist); + } +} + +void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean wifi_connected = FALSE; + boolean wifi_under_5g = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN notify()\n"); + BTC_TRACE(trace_buf); + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* this can't be removed for RF off_on event, or BT would dis-connect */ + halbtc8821c2ant_query_bt_info(btcoexist); + + if (BTC_SCAN_START == type) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, + &wifi_under_5g); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + TRUE); + + if (wifi_under_5g) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (5g)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** SCAN START notify (2g)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + halbtc8821c2ant_run_coexist_mechanism( + btcoexist); + + return; + } + + if (BTC_SCAN_START_2G == type) { + + if (!wifi_connected) + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + TRUE); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + + } else if (BTC_SCAN_FINISH == type) { + + coex_sta->wifi_is_high_pri_task = FALSE; + + btcoexist->btc_get(btcoexist, BTC_GET_U1_AP_NUM, + &coex_sta->scan_ap_num); + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], SCAN FINISH notify (Scan-AP = %d)\n", + coex_sta->scan_ap_num); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + + boolean wifi_connected = FALSE, bt_hs_on = FALSE; + u32 wifi_link_status = 0; + u32 num_of_wifi_link = 0; + boolean bt_ctrl_agg_buf_size = FALSE; + u8 agg_buf_size = 5; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + coex_sta->switch_band_notify_to = type; + + if (type == BTC_SWITCH_TO_5G) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 5G\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + + } else if (type == BTC_SWITCH_TO_24G_NOFORSCAN) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ********** switchband_notify BTC_SWITCH_TO_2G (no for scan)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], switchband_notify --- switch to 2G\n"); + BTC_TRACE(trace_buf); + + ex_halbtc8821c2ant_scan_notify(btcoexist, + BTC_SCAN_START_2G); + } + + coex_sta->switch_band_notify_to = BTC_NOT_SWITCH; +} + +void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + TRUE); + + if ((BTC_ASSOCIATE_5G_START == type) || + (BTC_ASSOCIATE_5G_FINISH == type)) { + + if (BTC_ASSOCIATE_5G_START == type) + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G start\n"); + else + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], connect_notify --- 5G finish\n"); + + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + if (BTC_ASSOCIATE_START == type) { + + coex_sta->wifi_is_high_pri_task = TRUE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT START notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + + /* To keep TDMA case during connect process, + to avoid changed by Btinfo and runcoexmechanism */ + coex_sta->freeze_coexrun_by_btinfo = TRUE; + + coex_dm->arp_cnt = 0; + + } else if (BTC_ASSOCIATE_FINISH == type) { + + coex_sta->wifi_is_high_pri_task = FALSE; + coex_sta->freeze_coexrun_by_btinfo = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], CONNECT FINISH notify (2G)\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + } +} + +void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + u8 h2c_parameter[3] = {0}; + u32 wifi_bw; + u8 wifi_central_chnl; + u8 ap_num = 0; + boolean wifi_under_b_mode = FALSE, wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (BTC_MEDIA_CONNECT == type) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA connect notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF, + TRUE); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, + &wifi_under_b_mode); + + /* Set CCK Tx/Rx high Pri except 11b mode */ + if (wifi_under_b_mode) { + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x00); /* CCK Rx */ + } else { + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, + 0x00); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, + 0x10); /* CCK Rx */ + } + + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], MEDIA disconnect notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_write_1byte(btcoexist, 0x6cd, 0x0); /* CCK Tx */ + btcoexist->btc_write_1byte(btcoexist, 0x6cf, 0x0); /* CCK Rx */ + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE, FALSE); + } + + halbtc8821c2ant_update_wifi_channel_info(btcoexist, type); +} + +void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + boolean under_4way = FALSE, wifi_under_5g = FALSE; + + if (btcoexist->manual_control || + btcoexist->stop_coex_dm) + return; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if (wifi_under_5g) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], WiFi is under 5G!!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_action_wifi_under5g(btcoexist); + return; + } + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, + &under_4way); + + if (under_4way) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ---- under_4way!!\n"); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + + } else if (BTC_PACKET_ARP == type) { + + coex_dm->arp_cnt++; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet ARP notify -cnt = %d\n", + coex_dm->arp_cnt); + BTC_TRACE(trace_buf); + + } else { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], specific Packet DHCP or EAPOL notify [Type = %d]\n", + type); + BTC_TRACE(trace_buf); + + coex_sta->wifi_is_high_pri_task = TRUE; + coex_sta->specific_pkt_period_cnt = 2; + } + + if (coex_sta->wifi_is_high_pri_task) { + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, TRUE); + halbtc8821c2ant_run_coexist_mechanism(btcoexist); + } + +} + +void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length) +{ + u8 i, rsp_source = 0; + boolean wifi_connected = FALSE; + boolean wifi_scan = FALSE, wifi_link = FALSE, wifi_roam = FALSE, + wifi_busy = FALSE; + static boolean is_scoreboard_scan = FALSE; + + rsp_source = tmp_buf[0] & 0xf; + if (rsp_source >= BT_INFO_SRC_8821C_2ANT_MAX) + rsp_source = BT_INFO_SRC_8821C_2ANT_WIFI_FW; + coex_sta->bt_info_c2h_cnt[rsp_source]++; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Bt_info[%d], len=%d, data=[", rsp_source, + length); + BTC_TRACE(trace_buf); + + for (i = 0; i < length; i++) { + coex_sta->bt_info_c2h[rsp_source][i] = tmp_buf[i]; + + if (i == length - 1) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x]\n", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } else { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "0x%02x, ", + tmp_buf[i]); + BTC_TRACE(trace_buf); + } + } + + coex_sta->bt_info = coex_sta->bt_info_c2h[rsp_source][1]; + coex_sta->bt_info_ext = coex_sta->bt_info_c2h[rsp_source][4]; + coex_sta->bt_info_ext2 = coex_sta->bt_info_c2h[rsp_source][5]; + + if (BT_INFO_SRC_8821C_2ANT_WIFI_FW != rsp_source) { + + /* if 0xff, it means BT is under WHCK test */ + coex_sta->bt_whck_test = ((coex_sta->bt_info == 0xff) ? TRUE : + FALSE); + + coex_sta->bt_create_connection = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x80) ? TRUE : + FALSE); + + /* unit: %, value-100 to translate to unit: dBm */ + coex_sta->bt_rssi = coex_sta->bt_info_c2h[rsp_source][3] * 2 + + 10; + + coex_sta->c2h_bt_remote_name_req = (( + coex_sta->bt_info_c2h[rsp_source][2] & 0x20) ? TRUE : + FALSE); + + coex_sta->is_A2DP_3M = ((coex_sta->bt_info_c2h[rsp_source][2] & + 0x10) ? TRUE : FALSE); + + coex_sta->acl_busy = ((coex_sta->bt_info_c2h[rsp_source][1] & + 0x9) ? TRUE : FALSE); + + coex_sta->voice_over_HOGP = ((coex_sta->bt_info_ext & 0x10) ? + TRUE : FALSE); + + coex_sta->c2h_bt_inquiry_page = ((coex_sta->bt_info & + BT_INFO_8821C_2ANT_B_INQ_PAGE) ? TRUE : FALSE); + + coex_sta->a2dp_bit_pool = ((( + coex_sta->bt_info_c2h[rsp_source][1] & 0x49) == 0x49) ? + (coex_sta->bt_info_c2h[rsp_source][6] & 0x7f) : 0); + + coex_sta->is_bt_a2dp_sink = (coex_sta->bt_info_c2h[rsp_source][6] & 0x80) ? + TRUE : FALSE; + + coex_sta->bt_retry_cnt = coex_sta->bt_info_c2h[rsp_source][2] & + 0xf; + + coex_sta->is_autoslot = coex_sta->bt_info_ext2 & 0x8; + + coex_sta->forbidden_slot = coex_sta->bt_info_ext2 & 0x7; + + coex_sta->hid_busy_num = (coex_sta->bt_info_ext2 & 0x30) >> 4; + + coex_sta->hid_pair_cnt = (coex_sta->bt_info_ext2 & 0xc0) >> 6; + + if (coex_sta->bt_retry_cnt >= 1) + coex_sta->pop_event_cnt++; + + if (coex_sta->c2h_bt_remote_name_req) + coex_sta->cnt_RemoteNameReq++; + + if (coex_sta->bt_info_ext & BIT(1)) + coex_sta->cnt_ReInit++; + + if (coex_sta->bt_info_ext & BIT(2)) { + coex_sta->cnt_setupLink++; + coex_sta->is_setupLink = TRUE; + coex_sta->bt_relink_downcount = 2; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link start in BT info!!\n"); + BTC_TRACE(trace_buf); + } else { + coex_sta->is_setupLink = FALSE; + coex_sta->bt_relink_downcount = 0; + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Re-Link stop in BT info!!\n"); + BTC_TRACE(trace_buf); + } + + if (coex_sta->bt_info_ext & BIT(3)) + coex_sta->cnt_IgnWlanAct++; + + if (coex_sta->bt_info_ext & BIT(6)) + coex_sta->cnt_RoleSwitch++; + + if (coex_sta->bt_info_ext & BIT(7)) + coex_sta->is_bt_multi_link = TRUE; + else + coex_sta->is_bt_multi_link = FALSE; + + if (coex_sta->bt_create_connection) { + coex_sta->cnt_Page++; + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_BUSY, + &wifi_busy); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_SCAN, &wifi_scan); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_LINK, &wifi_link); + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_ROAM, &wifi_roam); + + if ((wifi_link) || (wifi_roam) || (wifi_scan) || + (coex_sta->wifi_is_high_pri_task) || (wifi_busy)) { + + is_scoreboard_scan = TRUE; + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, TRUE); + + } else + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, FALSE); + + } else { + if (is_scoreboard_scan) { + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_SCAN, FALSE); + is_scoreboard_scan = FALSE; + } + } + + /* Here we need to resend some wifi info to BT */ + /* because bt is reset and loss of the info. */ + + if ((!btcoexist->manual_control) && + (!btcoexist->stop_coex_dm)) { + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_CONNECTED, + &wifi_connected); + + /* Re-Init */ + if ((coex_sta->bt_info_ext & BIT(1))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n"); + BTC_TRACE(trace_buf); + if (wifi_connected) + halbtc8821c2ant_update_wifi_channel_info( + btcoexist, BTC_MEDIA_CONNECT); + else + halbtc8821c2ant_update_wifi_channel_info( + btcoexist, + BTC_MEDIA_DISCONNECT); + } + + /* If Ignore_WLanAct && not SetUp_Link */ + if ((coex_sta->bt_info_ext & BIT(3)) && + (!(coex_sta->bt_info_ext & BIT(2))) && + (!(coex_sta->bt_info_ext & BIT(6)))) { + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n"); + BTC_TRACE(trace_buf); + halbtc8821c2ant_ignore_wlan_act(btcoexist, + FORCE_EXEC, FALSE); + } else { + if (coex_sta->bt_info_ext & BIT(2)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Re-link!!\n"); + BTC_TRACE(trace_buf); + } else if (coex_sta->bt_info_ext & BIT(6)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ignore Wlan active because Role-Switch!!\n"); + BTC_TRACE(trace_buf); + } + } + } + + } + + if ((coex_sta->bt_info_ext & BIT(5))) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], BT ext info bit4 check, query BLE Scan type!!\n"); + BTC_TRACE(trace_buf); + coex_sta->bt_ble_scan_type = btcoexist->btc_get_ble_scan_type_from_bt( + btcoexist); + + if ((coex_sta->bt_ble_scan_type & 0x1) == 0x1) + coex_sta->bt_ble_scan_para[0] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x1); + if ((coex_sta->bt_ble_scan_type & 0x2) == 0x2) + coex_sta->bt_ble_scan_para[1] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x2); + if ((coex_sta->bt_ble_scan_type & 0x4) == 0x4) + coex_sta->bt_ble_scan_para[2] = + btcoexist->btc_get_ble_scan_para_from_bt(btcoexist, + 0x4); + } + + halbtc8821c2ant_update_bt_link_info(btcoexist); + + halbtc8821c2ant_run_coexist_mechanism(btcoexist); +} + +void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], RF Status notify\n"); + BTC_TRACE(trace_buf); + + if (BTC_RF_ON == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned ON!!\n"); + BTC_TRACE(trace_buf); + + btcoexist->stop_coex_dm = FALSE; + coex_sta->is_rf_state_off = FALSE; + } else if (BTC_RF_OFF == type) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], RF is turned OFF!!\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + + halbtc8821c2ant_action_coex_all_off(btcoexist); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + FALSE); + + btcoexist->stop_coex_dm = TRUE; + coex_sta->is_rf_state_off = TRUE; + } +} + +void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist) +{ + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Halt notify\n"); + BTC_TRACE(trace_buf); + + halbtc8821c2ant_set_ant_path(btcoexist, BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + + ex_halbtc8821c2ant_media_status_notify(btcoexist, BTC_MEDIA_DISCONNECT); + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + FALSE); +} + +void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state) +{ + boolean wifi_under_5g = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, "[BTCoex], Pnp notify\n"); + BTC_TRACE(trace_buf); + + btcoexist->btc_get(btcoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifi_under_5g); + + if ((BTC_WIFI_PNP_SLEEP == pnp_state) || + (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state)) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to SLEEP\n"); + BTC_TRACE(trace_buf); + + /* Sinda 20150819, workaround for driver skip leave IPS/LPS to speed up sleep time. */ + /* Driver do not leave IPS/LPS when driver is going to sleep, so BTCoexistence think wifi is still under IPS/LPS */ + /* BT should clear UnderIPS/UnderLPS state to avoid mismatch state after wakeup. */ + coex_sta->under_ips = FALSE; + coex_sta->under_lps = FALSE; + + halbtc8821c2ant_post_state_to_bt(btcoexist, + BT_8821C_2ANT_SCOREBOARD_ACTIVE | + BT_8821C_2ANT_SCOREBOARD_ONOFF | + BT_8821C_2ANT_SCOREBOARD_SCAN | + BT_8821C_2ANT_SCOREBOARD_UNDERTEST, + FALSE); + + if (BTC_WIFI_PNP_SLEEP_KEEP_ANT == pnp_state) { + + if (wifi_under_5g) + halbtc8821c2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_5G_RUNTIME); + else + halbtc8821c2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, FORCE_EXEC, + BT_8821C_2ANT_PHASE_2G_RUNTIME); + } else { + + halbtc8821c2ant_set_ant_path(btcoexist, + BTC_ANT_PATH_AUTO, + FORCE_EXEC, + BT_8821C_2ANT_PHASE_WLAN_OFF); + } + } else if (BTC_WIFI_PNP_WAKE_UP == pnp_state) { + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], Pnp notify to WAKE UP\n"); + BTC_TRACE(trace_buf); + } +} + +void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist) +{ + struct btc_board_info *board_info = &btcoexist->board_info; + boolean wifi_busy = FALSE; + boolean bt_relink_finish = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ************* Periodical *************\n"); + BTC_TRACE(trace_buf); + +#if (BT_AUTO_REPORT_ONLY_8821C_2ANT == 0) + halbtc8821c2ant_query_bt_info(btcoexist); +#endif + + halbtc8821c2ant_monitor_bt_ctr(btcoexist); + halbtc8821c2ant_monitor_wifi_ctr(btcoexist); + halbtc8821c2ant_monitor_bt_enable_disable(btcoexist); + + if (coex_sta->bt_relink_downcount != 0) { + coex_sta->bt_relink_downcount--; + + if (coex_sta->bt_relink_downcount == 0) { + coex_sta->is_setupLink = FALSE; + bt_relink_finish = TRUE; + } + } + + /* for 4-way, DHCP, EAPOL packet */ + if (coex_sta->specific_pkt_period_cnt > 0) { + + coex_sta->specific_pkt_period_cnt--; + + if ((coex_sta->specific_pkt_period_cnt == 0) && + (coex_sta->wifi_is_high_pri_task)) + coex_sta->wifi_is_high_pri_task = FALSE; + + BTC_SPRINTF(trace_buf, BT_TMP_BUF_SIZE, + "[BTCoex], ***************** Hi-Pri Task = %s\n", + (coex_sta->wifi_is_high_pri_task ? "Yes" : + "No")); + BTC_TRACE(trace_buf); + + } + + if (halbtc8821c2ant_is_wifibt_status_changed(btcoexist) || (bt_relink_finish) + || (coex_sta->is_set_ps_state_fail)) + halbtc8821c2ant_run_coexist_mechanism(btcoexist); +} + +/*#pragma optimize( "", off )*/ +void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds) +{ + +} + +void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist) +{ + +} + + + diff --git a/drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.h b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.h new file mode 100644 index 000000000000..475993c4ab73 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/halbtc8821c2ant.h @@ -0,0 +1,470 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + + + +/* ******************************************* + * The following is for 8821C 2Ant BT Co-exist definition + * ******************************************* */ +#define BT_8821C_2ANT_COEX_DBG 0 +#define BT_AUTO_REPORT_ONLY_8821C_2ANT 1 + +#define BT_INFO_8821C_2ANT_B_FTP BIT(7) +#define BT_INFO_8821C_2ANT_B_A2DP BIT(6) +#define BT_INFO_8821C_2ANT_B_HID BIT(5) +#define BT_INFO_8821C_2ANT_B_SCO_BUSY BIT(4) +#define BT_INFO_8821C_2ANT_B_ACL_BUSY BIT(3) +#define BT_INFO_8821C_2ANT_B_INQ_PAGE BIT(2) +#define BT_INFO_8821C_2ANT_B_SCO_ESCO BIT(1) +#define BT_INFO_8821C_2ANT_B_CONNECTION BIT(0) + +#define BTC_RSSI_COEX_THRESH_TOL_8821C_2ANT 2 + +#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES1 80 /* unit: % WiFi RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 42 */ +#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES1 80 /* unit: % BT RSSI Threshold for 2-Ant free-run/2-Ant TDMA translation, default = 46 */ +#define BT_8821C_2ANT_WIFI_RSSI_COEXSWITCH_THRES2 80 /* unit: % WiFi RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 42 */ +#define BT_8821C_2ANT_BT_RSSI_COEXSWITCH_THRES2 80 /* unit: % BT RSSI Threshold for 1-Ant TDMA/1-Ant PS-TDMA translation, default = 46 */ +#define BT_8821C_2ANT_DEFAULT_ISOLATION 15 /* unit: dB */ +#define BT_8821C_2ANT_WIFI_MAX_TX_POWER 15 /* unit: dBm */ +#define BT_8821C_2ANT_BT_MAX_TX_POWER 3 /* unit: dBm */ +#define BT_8821C_2ANT_WIFI_SIR_THRES1 -15 /* unit: dB */ +#define BT_8821C_2ANT_WIFI_SIR_THRES2 -30 /* unit: dB */ +#define BT_8821C_2ANT_BT_SIR_THRES1 -15 /* unit: dB */ +#define BT_8821C_2ANT_BT_SIR_THRES2 -30 /* unit: dB */ + +/* for Antenna detection */ +#define BT_8821C_2ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8821C_2ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 52 +#define BT_8821C_2ANT_ANTDET_PSDTHRES_1ANT 40 +#define BT_8821C_2ANT_ANTDET_RETRY_INTERVAL 10 /* retry timer if ant det is fail, unit: second */ +#define BT_8821C_2ANT_ANTDET_SWEEPPOINT_DELAY 60000 +#define BT_8821C_2ANT_ANTDET_ENABLE 0 +#define BT_8821C_2ANT_ANTDET_BTTXTIME 100 +#define BT_8821C_2ANT_ANTDET_BTTXCHANNEL 39 +#define BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT 50 + +#define BT_8821C_2ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + +enum bt_8821c_2ant_signal_state { + BT_8821C_2ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8821C_2ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8821C_2ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8821C_2ANT_SIG_STA_MAX +}; + +enum bt_8821c_2ant_path_ctrl_owner { + BT_8821C_2ANT_PCO_BTSIDE = 0x0, + BT_8821C_2ANT_PCO_WLSIDE = 0x1, + BT_8821C_2ANT_PCO_MAX +}; + +enum bt_8821c_2ant_gnt_ctrl_type { + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8821C_2ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8821C_2ANT_GNT_TYPE_MAX +}; + +enum bt_8821c_2ant_gnt_ctrl_block { + BT_8821C_2ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8821C_2ANT_GNT_BLOCK_RFC = 0x1, + BT_8821C_2ANT_GNT_BLOCK_BB = 0x2, + BT_8821C_2ANT_GNT_BLOCK_MAX +}; + +enum bt_8821c_2ant_lte_coex_table_type { + BT_8821C_2ANT_CTT_WL_VS_LTE = 0x0, + BT_8821C_2ANT_CTT_BT_VS_LTE = 0x1, + BT_8821C_2ANT_CTT_MAX +}; + +enum bt_8821c_2ant_lte_break_table_type { + BT_8821C_2ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8821C_2ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8821C_2ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8821C_2ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8821C_2ANT_LBTT_MAX +}; + +enum bt_info_src_8821c_2ant { + BT_INFO_SRC_8821C_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821C_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821C_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821C_2ANT_MAX +}; + +enum bt_8821c_2ant_bt_status { + BT_8821C_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821C_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821C_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821C_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821C_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821C_2ANT_BT_STATUS_MAX +}; + +enum bt_8821c_2ant_coex_algo { + BT_8821C_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821C_2ANT_COEX_ALGO_SCO = 0x1, + BT_8821C_2ANT_COEX_ALGO_HID = 0x2, + BT_8821C_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8821C_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821C_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821C_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8821C_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821C_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821C_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821C_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821C_2ANT_COEX_ALGO_NOPROFILEBUSY = 0xb, + BT_8821C_2ANT_COEX_ALGO_A2DPSINK = 0xc, + BT_8821C_2ANT_COEX_ALGO_MAX +}; + +enum bt_8821c_2ant_ext_ant_switch_type { + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_DPDT = 0x0, + BT_8821C_2ANT_EXT_ANT_SWITCH_USE_SPDT = 0x1, + BT_8821C_2ANT_EXT_ANT_SWITCH_NONE = 0x2, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAX +}; + +enum bt_8821c_2ant_ext_ant_switch_ctrl_type { + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8821C_2ANT_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8821c_2ant_ext_ant_switch_pos_type { + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_BT = 0x0, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLG = 0x1, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_WLA = 0x2, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_NOCARE = 0x3, + BT_8821C_2ANT_EXT_ANT_SWITCH_MAIN_TO_MAX +}; + +enum bt_8821c_2ant_ext_band_switch_pos_type { + BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLG = 0x0, + BT_8821C_2ANT_EXT_BAND_SWITCH_TO_WLA = 0x1, + BT_8821C_2ANT_EXT_BAND_SWITCH_TO_MAX +}; + +enum bt_8821c_2ant_int_block { + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_BTG = 0x0, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLG_OF_WLAG = 0x1, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_WLA_OF_WLAG = 0x2, + BT_8821C_2ANT_INT_BLOCK_SWITCH_TO_MAX +}; + +enum bt_8821c_2ant_phase { + BT_8821C_2ANT_PHASE_COEX_INIT = 0x0, + BT_8821C_2ANT_PHASE_WLANONLY_INIT = 0x1, + BT_8821C_2ANT_PHASE_WLAN_OFF = 0x2, + BT_8821C_2ANT_PHASE_2G_RUNTIME = 0x3, + BT_8821C_2ANT_PHASE_5G_RUNTIME = 0x4, + BT_8821C_2ANT_PHASE_BTMPMODE = 0x5, + BT_8821C_2ANT_PHASE_ANTENNA_DET = 0x6, + BT_8821C_2ANT_PHASE_COEX_POWERON = 0x7, + BT_8821C_2ANT_PHASE_2G_RUNTIME_CONCURRENT = 0x8, + BT_8821C_2ANT_PHASE_MAX +}; + +enum bt_8821c_2ant_Scoreboard { + BT_8821C_2ANT_SCOREBOARD_ACTIVE = BIT(0), + BT_8821C_2ANT_SCOREBOARD_ONOFF = BIT(1), + BT_8821C_2ANT_SCOREBOARD_SCAN = BIT(2), + BT_8821C_2ANT_SCOREBOARD_UNDERTEST = BIT(3), + BT_8821C_2ANT_SCOREBOARD_WLBUSY = BIT(6) +}; + +struct coex_dm_8821c_2ant { + /* hw setting */ + u32 pre_ant_pos_type; + u32 cur_ant_pos_type; + /* fw mechanism */ + u8 pre_bt_dec_pwr_lvl; + u8 cur_bt_dec_pwr_lvl; + u8 pre_fw_dac_swing_lvl; + u8 cur_fw_dac_swing_lvl; + boolean cur_ignore_wlan_act; + boolean pre_ignore_wlan_act; + u8 pre_ps_tdma; + u8 cur_ps_tdma; + u8 ps_tdma_para[5]; + u8 ps_tdma_du_adj_type; + boolean reset_tdma_adjust; + boolean pre_ps_tdma_on; + boolean cur_ps_tdma_on; + boolean pre_bt_auto_report; + boolean cur_bt_auto_report; + + /* sw mechanism */ + boolean pre_rf_rx_lpf_shrink; + boolean cur_rf_rx_lpf_shrink; + u32 bt_rf_0x1e_backup; + boolean pre_low_penalty_ra; + boolean cur_low_penalty_ra; + boolean pre_dac_swing_on; + u32 pre_dac_swing_lvl; + boolean cur_dac_swing_on; + u32 cur_dac_swing_lvl; + boolean pre_adc_back_off; + boolean cur_adc_back_off; + boolean pre_agc_table_en; + boolean cur_agc_table_en; + u32 pre_val0x6c0; + u32 cur_val0x6c0; + u32 pre_val0x6c4; + u32 cur_val0x6c4; + u32 pre_val0x6c8; + u32 cur_val0x6c8; + u8 pre_val0x6cc; + u8 cur_val0x6cc; + boolean limited_dig; + + /* algorithm related */ + u8 pre_algorithm; + u8 cur_algorithm; + u8 bt_status; + u8 wifi_chnl_info[3]; + + boolean need_recover0x948; + u32 backup0x948; + + u8 pre_lps; + u8 cur_lps; + u8 pre_rpwm; + u8 cur_rpwm; + + boolean is_switch_to_1dot5_ant; + u8 switch_thres_offset; + u32 arp_cnt; + + u32 pre_ext_ant_switch_status; + u32 cur_ext_ant_switch_status; + + u8 pre_ext_band_switch_status; + u8 cur_ext_band_switch_status; + + u8 pre_int_block_status; + u8 cur_int_block_status; +}; + +struct coex_sta_8821c_2ant { + boolean bt_disabled; + boolean bt_link_exist; + boolean sco_exist; + boolean a2dp_exist; + boolean hid_exist; + boolean pan_exist; + + boolean under_lps; + boolean under_ips; + u32 high_priority_tx; + u32 high_priority_rx; + u32 low_priority_tx; + u32 low_priority_rx; + boolean is_hiPri_rx_overhead; + u8 bt_rssi; + u8 pre_bt_rssi_state; + u8 pre_wifi_rssi_state[4]; + u8 bt_info_c2h[BT_INFO_SRC_8821C_2ANT_MAX][10]; + u32 bt_info_c2h_cnt[BT_INFO_SRC_8821C_2ANT_MAX]; + boolean bt_whck_test; + boolean c2h_bt_inquiry_page; + boolean c2h_bt_remote_name_req; + + u8 bt_info_ext; + u8 bt_info_ext2; + u32 pop_event_cnt; + u8 scan_ap_num; + u8 bt_retry_cnt; + + u32 crc_ok_cck; + u32 crc_ok_11g; + u32 crc_ok_11n; + u32 crc_ok_11n_vht; + + u32 crc_err_cck; + u32 crc_err_11g; + u32 crc_err_11n; + u32 crc_err_11n_vht; + + u32 acc_crc_ratio; + u32 now_crc_ratio; + + boolean cck_lock; + boolean pre_ccklock; + boolean cck_ever_lock; + + u8 coex_table_type; + boolean force_lps_ctrl; + + u8 dis_ver_info_cnt; + + u8 a2dp_bit_pool; + u8 cut_version; + + boolean concurrent_rx_mode_on; + + u16 score_board; + u8 isolation_btween_wb; /* 0~ 50 */ + u8 wifi_coex_thres; + u8 bt_coex_thres; + u8 wifi_coex_thres2; + u8 bt_coex_thres2; + + u8 num_of_profile; + boolean acl_busy; + boolean bt_create_connection; + boolean wifi_is_high_pri_task; + u32 specific_pkt_period_cnt; + u32 bt_coex_supported_feature; + u32 bt_coex_supported_version; + + u8 bt_ble_scan_type; + u32 bt_ble_scan_para[3]; + + boolean run_time_state; + boolean freeze_coexrun_by_btinfo; + + boolean is_A2DP_3M; + boolean voice_over_HOGP; + u8 bt_info; + boolean is_autoslot; + u8 forbidden_slot; + u8 hid_busy_num; + u8 hid_pair_cnt; + + u32 cnt_RemoteNameReq; + u32 cnt_setupLink; + u32 cnt_ReInit; + u32 cnt_IgnWlanAct; + u32 cnt_Page; + u32 cnt_RoleSwitch; + + u16 bt_reg_vendor_ac; + u16 bt_reg_vendor_ae; + + boolean is_setupLink; + u8 wl_noisy_level; + u32 gnt_error_cnt; + + u8 bt_afh_map[10]; + u8 bt_relink_downcount; + boolean is_tdma_btautoslot; + boolean is_tdma_btautoslot_hang; + + boolean is_eSCO_mode; + u8 switch_band_notify_to; + boolean is_rf_state_off; + + boolean is_hid_low_pri_tx_overhead; + boolean is_bt_multi_link; + boolean is_bt_a2dp_sink; + boolean is_set_ps_state_fail; + u8 cnt_set_ps_state_fail; +}; + +#define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_DPDT 0 +#define BT_8821C_2ANT_EXT_BAND_SWITCH_USE_SPDT 1 + +struct rfe_type_8821c_2ant { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + + boolean ext_band_switch_exist; + u8 ext_band_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_band_switch_ctrl_polarity; + + boolean ant_at_main_port; + + boolean wlg_Locate_at_btg; /* If TRUE: WLG at BTG, If FALSE: WLG at WLAG */ + + boolean ext_ant_switch_diversity; /* If diversity on */ +}; + +#define BT_8821C_2ANT_ANTDET_PSD_POINTS 256 /* MAX:1024 */ +#define BT_8821C_2ANT_ANTDET_PSD_AVGNUM 1 /* MAX:3 */ +#define BT_8821C_2ANT_ANTDET_BUF_LEN 16 + +struct psdscan_sta_8821c_2ant { + + u32 ant_det_bt_le_channel; /* BT LE Channel ex:2412 */ + u32 ant_det_bt_tx_time; + u32 ant_det_pre_psdscan_peak_val; + boolean ant_det_is_ant_det_available; + u32 ant_det_psd_scan_peak_val; + boolean ant_det_is_btreply_available; + u32 ant_det_psd_scan_peak_freq; + + u8 ant_det_result; + u8 ant_det_peak_val[BT_8821C_2ANT_ANTDET_BUF_LEN]; + u8 ant_det_peak_freq[BT_8821C_2ANT_ANTDET_BUF_LEN]; + u32 ant_det_try_count; + u32 ant_det_fail_count; + u32 ant_det_inteval_count; + u32 ant_det_thres_offset; + + u32 real_cent_freq; + s32 real_offset; + u32 real_span; + + u32 psd_band_width; /* unit: Hz */ + u32 psd_point; /* 128/256/512/1024 */ + u32 psd_report[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_report_max_hold[1024]; /* unit:dB (20logx), 0~255 */ + u32 psd_start_point; + u32 psd_stop_point; + u32 psd_max_value_point; + u32 psd_max_value; + u32 psd_max_value2; + u32 psd_avg_value; /* filter loop_max_value that below BT_8821C_1ANT_ANTDET_PSDTHRES_1ANT, and average the rest*/ + u32 psd_loop_max_value[BT_8821C_2ANT_ANTDET_PSD_SWWEEPCOUNT]; /*max value in each loop */ + u32 psd_start_base; + u32 psd_avg_num; /* 1/8/16/32 */ + u32 psd_gen_count; + boolean is_AntDet_running; + boolean is_psd_show_max_only; +}; + +/* ******************************************* + * The following is interface which will notify coex module. + * ******************************************* */ +void ex_halbtc8821c2ant_power_on_setting(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_pre_load_firmware(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_init_hw_config(IN struct btc_coexist *btcoexist, + IN boolean wifi_only); +void ex_halbtc8821c2ant_init_coex_dm(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_ips_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_lps_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_scan_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_switchband_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_connect_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_media_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_specific_packet_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_bt_info_notify(IN struct btc_coexist *btcoexist, + IN u8 *tmp_buf, IN u8 length); +void ex_halbtc8821c2ant_rf_status_notify(IN struct btc_coexist *btcoexist, + IN u8 type); +void ex_halbtc8821c2ant_halt_notify(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_pnp_notify(IN struct btc_coexist *btcoexist, + IN u8 pnp_state); +void ex_halbtc8821c2ant_periodical(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_display_coex_info(IN struct btc_coexist *btcoexist); +void ex_halbtc8821c2ant_antenna_detection(IN struct btc_coexist *btcoexist, + IN u32 cent_freq, IN u32 offset, IN u32 span, IN u32 seconds); +void ex_halbtc8821c2ant_display_ant_detection(IN struct btc_coexist *btcoexist); + + + diff --git a/drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.c b/drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.c new file mode 100644 index 000000000000..b27f591810b6 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "mp_precomp.h" + +static struct rfe_type_8821c_wifi_only gl_rfe_type_8821c_1ant; +static struct rfe_type_8821c_wifi_only *rfe_type = &gl_rfe_type_8821c_1ant; + +VOID hal8821c_wifi_only_switch_antenna( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + boolean switch_polatiry_inverse = false; + u8 regval_0xcb7 = 0; + u8 pos_type, ctrl_type; + + if (!rfe_type->ext_ant_switch_exist) + return; + + /* swap control polarity if use different switch control polarity*/ + /* Normal switch polarity for DPDT, 0xcb4[29:28] = 2b'01 => BTG to Main, WLG to Aux, 0xcb4[29:28] = 2b'10 => BTG to Aux, WLG to Main */ + /* Normal switch polarity for SPDT, 0xcb4[29:28] = 2b'01 => Ant to BTG, 0xcb4[29:28] = 2b'10 => Ant to WLG */ + if (rfe_type->ext_ant_switch_ctrl_polarity) + switch_polatiry_inverse = !switch_polatiry_inverse; + + /* swap control polarity if 1-Ant at Aux */ + if (rfe_type->ant_at_main_port == false) + switch_polatiry_inverse = !switch_polatiry_inverse; + + if (is_5g) + pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA; + else + pos_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG; + + switch (pos_type) { + default: + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA: + + break; + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG: + if (!rfe_type->wlg_Locate_at_btg) + switch_polatiry_inverse = !switch_polatiry_inverse; + break; + } + + if (pwifionlycfg->haldata_info.ant_div_cfg) + ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV; + else + ctrl_type = BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW; + + switch (ctrl_type) { + default: + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW: + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); + + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff, 0x77); + + regval_0xcb7 = (switch_polatiry_inverse == false ? 0x1 : 0x2); + + /* 0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0 */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x30000000, regval_0xcb7); + break; + + case BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV: + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x4c, 0x01800000, 0x2); + + /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as control pin */ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0xcb4, 0x000000ff, 0x88); + + /* no regval_0xcb7 setup required, because antenna switch control value by antenna diversity */ + + break; + + } + +} + +VOID halbtc8821c_wifi_only_set_rfe_type( + IN struct wifi_only_cfg *pwifionlycfg + ) +{ + + /* the following setup should be got from Efuse in the future */ + rfe_type->rfe_module_type = (pwifionlycfg->haldata_info.rfe_type) & 0x1f; + + rfe_type->ext_ant_switch_ctrl_polarity = 0; + + switch (rfe_type->rfe_module_type) { + case 0: + default: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*2-Ant, DPDT, WLG*/ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 1: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 2: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT; /*1-Ant, Main, DPDT or SPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + case 3: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, WLG */ + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = false; + break; + case 4: + rfe_type->ext_ant_switch_exist = true; + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; /*1-Ant, Aux, DPDT, BTG */ + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = false; + break; + case 5: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 6: + rfe_type->ext_ant_switch_exist = false; /*2-Ant, no antenna switch, WLG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE; + rfe_type->wlg_Locate_at_btg = false; + rfe_type->ant_at_main_port = true; + break; + case 7: + rfe_type->ext_ant_switch_exist = true; /*2-Ant, DPDT, BTG*/ + rfe_type->ext_ant_switch_type = + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT; + rfe_type->wlg_Locate_at_btg = true; + rfe_type->ant_at_main_port = true; + break; + } + +} + +VOID +ex_hal8821c_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ) +{ + halbtc8821c_wifi_only_set_rfe_type(pwifionlycfg); + + /* set gnt_wl, gnt_bt control owner to WL*/ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x70, 0x400000, 0x1); + + /*gnt_wl=1 , gnt_bt=0*/ + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1704, 0xffffffff, 0x7700); + halwifionly_phy_set_bb_reg(pwifionlycfg, 0x1700, 0xffffffff, 0xc00f0038); +} + +VOID +ex_hal8821c_wifi_only_scannotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); +} + +VOID +ex_hal8821c_wifi_only_switchbandnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ) +{ + hal8821c_wifi_only_switch_antenna(pwifionlycfg, is_5g); +} + diff --git a/drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.h b/drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.h new file mode 100644 index 000000000000..efb41db8dc87 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/halbtc8821cwifionly.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_HAL8821CWIFIONLYHWCFG_H +#define __INC_HAL8821CWIFIONLYHWCFG_H + +struct rfe_type_8821c_wifi_only { + + u8 rfe_module_type; + boolean ext_ant_switch_exist; + u8 ext_ant_switch_type; /* 0:DPDT, 1:SPDT */ + u8 ext_ant_switch_ctrl_polarity; /* iF 0: DPDT_P=0, DPDT_N=1 => BTG to Main, WL_A+G to Aux */ + + boolean ant_at_main_port; + + boolean wlg_Locate_at_btg; /* If true: WLG at BTG, If false: WLG at WLAG */ + + boolean ext_ant_switch_diversity; /* If diversity on */ +}; + +enum bt_8821c_wifi_only_ext_ant_switch_type { + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_DPDT = 0x0, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_USE_SPDT = 0x1, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_NONE = 0x2, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_MAX +}; + +enum bt_8821c_wifi_only_ext_ant_switch_ctrl_type { + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BBSW = 0x0, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_PTA = 0x1, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_ANTDIV = 0x2, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_MAC = 0x3, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_BY_BT = 0x4, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_CTRL_MAX +}; + +enum bt_8821c_wifi_only_ext_ant_switch_pos_type { + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_BT = 0x0, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLG = 0x1, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_WLA = 0x2, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_NOCARE = 0x3, + BT_8821C_WIFI_ONLY_EXT_ANT_SWITCH_TO_MAX +}; + +VOID +hal8821c_wifi_only_switch_antenna( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); + +VOID +halbtc8821c_wifi_only_set_rfe_type( + IN struct wifi_only_cfg *pwifionlycfg + ); + +VOID +ex_hal8821c_wifi_only_hw_config( + IN struct wifi_only_cfg *pwifionlycfg + ); +VOID +ex_hal8821c_wifi_only_scannotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +VOID +ex_hal8821c_wifi_only_switchbandnotify( + IN struct wifi_only_cfg *pwifionlycfg, + IN u1Byte is_5g + ); +#endif diff --git a/drivers/staging/rtl8821ce/hal/btc/halbtcoutsrc.h b/drivers/staging/rtl8821ce/hal/btc/halbtcoutsrc.h new file mode 100644 index 000000000000..9e9e736b8c68 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/halbtcoutsrc.h @@ -0,0 +1,987 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HALBTC_OUT_SRC_H__ +#define __HALBTC_OUT_SRC_H__ + +#define BTC_COEX_OFFLOAD 0 +#define BTC_TMP_BUF_SHORT 20 + +extern u1Byte gl_btc_trace_buf[]; +#define BTC_SPRINTF rsprintf +#define BTC_TRACE(_MSG_)\ +do {\ + if (GLBtcDbgType[COMP_COEX] & BIT(DBG_LOUD)) {\ + RTW_INFO("%s", _MSG_);\ + } \ +} while (0) +#define BT_PrintData(adapter, _MSG_, len, data) RTW_DBG_DUMP((_MSG_), data, len) + +#define NORMAL_EXEC FALSE +#define FORCE_EXEC TRUE + +#define BTC_RF_OFF 0x0 +#define BTC_RF_ON 0x1 + +#define BTC_RF_A 0x0 +#define BTC_RF_B 0x1 +#define BTC_RF_C 0x2 +#define BTC_RF_D 0x3 + +#define BTC_SMSP SINGLEMAC_SINGLEPHY +#define BTC_DMDP DUALMAC_DUALPHY +#define BTC_DMSP DUALMAC_SINGLEPHY +#define BTC_MP_UNKNOWN 0xff + +#define BT_COEX_ANT_TYPE_PG 0 +#define BT_COEX_ANT_TYPE_ANTDIV 1 +#define BT_COEX_ANT_TYPE_DETECTED 2 + +#define BTC_MIMO_PS_STATIC 0 /* 1ss */ +#define BTC_MIMO_PS_DYNAMIC 1 /* 2ss */ + +#define BTC_RATE_DISABLE 0 +#define BTC_RATE_ENABLE 1 + +/* single Antenna definition */ +#define BTC_ANT_PATH_WIFI 0 +#define BTC_ANT_PATH_BT 1 +#define BTC_ANT_PATH_PTA 2 +#define BTC_ANT_PATH_WIFI5G 3 +#define BTC_ANT_PATH_AUTO 4 +/* dual Antenna definition */ +#define BTC_ANT_WIFI_AT_MAIN 0 +#define BTC_ANT_WIFI_AT_AUX 1 +#define BTC_ANT_WIFI_AT_DIVERSITY 2 +/* coupler Antenna definition */ +#define BTC_ANT_WIFI_AT_CPL_MAIN 0 +#define BTC_ANT_WIFI_AT_CPL_AUX 1 + +typedef enum _BTC_POWERSAVE_TYPE { + BTC_PS_WIFI_NATIVE = 0, /* wifi original power save behavior */ + BTC_PS_LPS_ON = 1, + BTC_PS_LPS_OFF = 2, + BTC_PS_MAX +} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE; + +typedef enum _BTC_BT_REG_TYPE { + BTC_BT_REG_RF = 0, + BTC_BT_REG_MODEM = 1, + BTC_BT_REG_BLUEWIZE = 2, + BTC_BT_REG_VENDOR = 3, + BTC_BT_REG_LE = 4, + BTC_BT_REG_MAX +} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE; + +typedef enum _BTC_CHIP_INTERFACE { + BTC_INTF_UNKNOWN = 0, + BTC_INTF_PCI = 1, + BTC_INTF_USB = 2, + BTC_INTF_SDIO = 3, + BTC_INTF_MAX +} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE; + +typedef enum _BTC_CHIP_TYPE { + BTC_CHIP_UNDEF = 0, + BTC_CHIP_CSR_BC4 = 1, + BTC_CHIP_CSR_BC8 = 2, + BTC_CHIP_RTL8723A = 3, + BTC_CHIP_RTL8821 = 4, + BTC_CHIP_RTL8723B = 5, + BTC_CHIP_MAX +} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE; + +/* following is for wifi link status */ +#define WIFI_STA_CONNECTED BIT0 +#define WIFI_AP_CONNECTED BIT1 +#define WIFI_HS_CONNECTED BIT2 +#define WIFI_P2P_GO_CONNECTED BIT3 +#define WIFI_P2P_GC_CONNECTED BIT4 + +/* following is for command line utility */ +#define CL_SPRINTF rsprintf +#define CL_PRINTF DCMD_Printf + +struct btc_board_info { + /* The following is some board information */ + u8 bt_chip_type; + u8 pg_ant_num; /* pg ant number */ + u8 btdm_ant_num; /* ant number for btdm */ + u8 btdm_ant_num_by_ant_det; /* ant number for btdm after antenna detection */ + u8 btdm_ant_pos; /* Bryant Add to indicate Antenna Position for (pg_ant_num = 2) && (btdm_ant_num =1) (DPDT+1Ant case) */ + u8 single_ant_path; /* current used for 8723b only, 1=>s0, 0=>s1 */ + boolean tfbga_package; /* for Antenna detect threshold */ + boolean btdm_ant_det_finish; + boolean btdm_ant_det_already_init_phydm; + u8 ant_type; + u8 rfe_type; + u8 ant_div_cfg; + boolean btdm_ant_det_complete_fail; + u8 ant_det_result; + boolean ant_det_result_five_complete; + u32 antdetval; +}; + +typedef enum _BTC_DBG_OPCODE { + BTC_DBG_SET_COEX_NORMAL = 0x0, + BTC_DBG_SET_COEX_WIFI_ONLY = 0x1, + BTC_DBG_SET_COEX_BT_ONLY = 0x2, + BTC_DBG_SET_COEX_DEC_BT_PWR = 0x3, + BTC_DBG_SET_COEX_BT_AFH_MAP = 0x4, + BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT = 0x5, + BTC_DBG_SET_COEX_MANUAL_CTRL = 0x6, + BTC_DBG_MAX +} BTC_DBG_OPCODE, *PBTC_DBG_OPCODE; + +typedef enum _BTC_RSSI_STATE { + BTC_RSSI_STATE_HIGH = 0x0, + BTC_RSSI_STATE_MEDIUM = 0x1, + BTC_RSSI_STATE_LOW = 0x2, + BTC_RSSI_STATE_STAY_HIGH = 0x3, + BTC_RSSI_STATE_STAY_MEDIUM = 0x4, + BTC_RSSI_STATE_STAY_LOW = 0x5, + BTC_RSSI_MAX +} BTC_RSSI_STATE, *PBTC_RSSI_STATE; +#define BTC_RSSI_HIGH(_rssi_) ((_rssi_ == BTC_RSSI_STATE_HIGH || _rssi_ == BTC_RSSI_STATE_STAY_HIGH) ? TRUE:FALSE) +#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_ == BTC_RSSI_STATE_MEDIUM || _rssi_ == BTC_RSSI_STATE_STAY_MEDIUM) ? TRUE:FALSE) +#define BTC_RSSI_LOW(_rssi_) ((_rssi_ == BTC_RSSI_STATE_LOW || _rssi_ == BTC_RSSI_STATE_STAY_LOW) ? TRUE:FALSE) + +typedef enum _BTC_WIFI_ROLE { + BTC_ROLE_STATION = 0x0, + BTC_ROLE_AP = 0x1, + BTC_ROLE_IBSS = 0x2, + BTC_ROLE_HS_MODE = 0x3, + BTC_ROLE_MAX +} BTC_WIFI_ROLE, *PBTC_WIFI_ROLE; + +typedef enum _BTC_WIRELESS_FREQ { + BTC_FREQ_2_4G = 0x0, + BTC_FREQ_5G = 0x1, + BTC_FREQ_MAX +} BTC_WIRELESS_FREQ, *PBTC_WIRELESS_FREQ; + +typedef enum _BTC_WIFI_BW_MODE { + BTC_WIFI_BW_LEGACY = 0x0, + BTC_WIFI_BW_HT20 = 0x1, + BTC_WIFI_BW_HT40 = 0x2, + BTC_WIFI_BW_HT80 = 0x3, + BTC_WIFI_BW_HT160 = 0x4, + BTC_WIFI_BW_MAX +} BTC_WIFI_BW_MODE, *PBTC_WIFI_BW_MODE; + +typedef enum _BTC_WIFI_TRAFFIC_DIR { + BTC_WIFI_TRAFFIC_TX = 0x0, + BTC_WIFI_TRAFFIC_RX = 0x1, + BTC_WIFI_TRAFFIC_MAX +} BTC_WIFI_TRAFFIC_DIR, *PBTC_WIFI_TRAFFIC_DIR; + +typedef enum _BTC_WIFI_PNP { + BTC_WIFI_PNP_WAKE_UP = 0x0, + BTC_WIFI_PNP_SLEEP = 0x1, + BTC_WIFI_PNP_SLEEP_KEEP_ANT = 0x2, + BTC_WIFI_PNP_MAX +} BTC_WIFI_PNP, *PBTC_WIFI_PNP; + +typedef enum _BTC_IOT_PEER { + BTC_IOT_PEER_UNKNOWN = 0, + BTC_IOT_PEER_REALTEK = 1, + BTC_IOT_PEER_REALTEK_92SE = 2, + BTC_IOT_PEER_BROADCOM = 3, + BTC_IOT_PEER_RALINK = 4, + BTC_IOT_PEER_ATHEROS = 5, + BTC_IOT_PEER_CISCO = 6, + BTC_IOT_PEER_MERU = 7, + BTC_IOT_PEER_MARVELL = 8, + BTC_IOT_PEER_REALTEK_SOFTAP = 9, /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */ + BTC_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */ + BTC_IOT_PEER_AIRGO = 11, + BTC_IOT_PEER_INTEL = 12, + BTC_IOT_PEER_RTK_APCLIENT = 13, + BTC_IOT_PEER_REALTEK_81XX = 14, + BTC_IOT_PEER_REALTEK_WOW = 15, + BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16, + BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17, + BTC_IOT_PEER_MAX, +} BTC_IOT_PEER, *PBTC_IOT_PEER; + +/* for 8723b-d cut large current issue */ +typedef enum _BTC_WIFI_COEX_STATE { + BTC_WIFI_STAT_INIT, + BTC_WIFI_STAT_IQK, + BTC_WIFI_STAT_NORMAL_OFF, + BTC_WIFI_STAT_MP_OFF, + BTC_WIFI_STAT_NORMAL, + BTC_WIFI_STAT_ANT_DIV, + BTC_WIFI_STAT_MAX +} BTC_WIFI_COEX_STATE, *PBTC_WIFI_COEX_STATE; + +typedef enum _BTC_ANT_TYPE { + BTC_ANT_TYPE_0, + BTC_ANT_TYPE_1, + BTC_ANT_TYPE_2, + BTC_ANT_TYPE_3, + BTC_ANT_TYPE_4, + BTC_ANT_TYPE_MAX +} BTC_ANT_TYPE, *PBTC_ANT_TYPE; + +typedef enum _BTC_VENDOR { + BTC_VENDOR_LENOVO, + BTC_VENDOR_ASUS, + BTC_VENDOR_OTHER +} BTC_VENDOR, *PBTC_VENDOR; + +/* defined for BFP_BTC_GET */ +typedef enum _BTC_GET_TYPE { + /* type BOOLEAN */ + BTC_GET_BL_HS_OPERATION, + BTC_GET_BL_HS_CONNECTING, + BTC_GET_BL_WIFI_FW_READY, + BTC_GET_BL_WIFI_CONNECTED, + BTC_GET_BL_WIFI_BUSY, + BTC_GET_BL_WIFI_SCAN, + BTC_GET_BL_WIFI_LINK, + BTC_GET_BL_WIFI_ROAM, + BTC_GET_BL_WIFI_4_WAY_PROGRESS, + BTC_GET_BL_WIFI_UNDER_5G, + BTC_GET_BL_WIFI_AP_MODE_ENABLE, + BTC_GET_BL_WIFI_ENABLE_ENCRYPTION, + BTC_GET_BL_WIFI_UNDER_B_MODE, + BTC_GET_BL_EXT_SWITCH, + BTC_GET_BL_WIFI_IS_IN_MP_MODE, + BTC_GET_BL_IS_ASUS_8723B, + BTC_GET_BL_RF4CE_CONNECTED, + + /* type s4Byte */ + BTC_GET_S4_WIFI_RSSI, + BTC_GET_S4_HS_RSSI, + + /* type u4Byte */ + BTC_GET_U4_WIFI_BW, + BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, + BTC_GET_U4_WIFI_FW_VER, + BTC_GET_U4_WIFI_LINK_STATUS, + BTC_GET_U4_BT_PATCH_VER, + BTC_GET_U4_VENDOR, + BTC_GET_U4_SUPPORTED_VERSION, + BTC_GET_U4_SUPPORTED_FEATURE, + BTC_GET_U4_WIFI_IQK_TOTAL, + BTC_GET_U4_WIFI_IQK_OK, + BTC_GET_U4_WIFI_IQK_FAIL, + + /* type u1Byte */ + BTC_GET_U1_WIFI_DOT11_CHNL, + BTC_GET_U1_WIFI_CENTRAL_CHNL, + BTC_GET_U1_WIFI_HS_CHNL, + BTC_GET_U1_WIFI_P2P_CHNL, + BTC_GET_U1_MAC_PHY_MODE, + BTC_GET_U1_AP_NUM, + BTC_GET_U1_ANT_TYPE, + BTC_GET_U1_IOT_PEER, + + /*===== for 1Ant ======*/ + BTC_GET_U1_LPS_MODE, + + BTC_GET_MAX +} BTC_GET_TYPE, *PBTC_GET_TYPE; + +/* defined for BFP_BTC_SET */ +typedef enum _BTC_SET_TYPE { + /* type BOOLEAN */ + BTC_SET_BL_BT_DISABLE, + BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE, + BTC_SET_BL_BT_TRAFFIC_BUSY, + BTC_SET_BL_BT_LIMITED_DIG, + BTC_SET_BL_FORCE_TO_ROAM, + BTC_SET_BL_TO_REJ_AP_AGG_PKT, + BTC_SET_BL_BT_CTRL_AGG_SIZE, + BTC_SET_BL_INC_SCAN_DEV_NUM, + BTC_SET_BL_BT_TX_RX_MASK, + BTC_SET_BL_MIRACAST_PLUS_BT, + + /* type u1Byte */ + BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, + BTC_SET_U1_AGG_BUF_SIZE, + + /* type trigger some action */ + BTC_SET_ACT_GET_BT_RSSI, + BTC_SET_ACT_AGGREGATE_CTRL, + BTC_SET_ACT_ANTPOSREGRISTRY_CTRL, + /*===== for 1Ant ======*/ + /* type BOOLEAN */ + + /* type u1Byte */ + BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, + BTC_SET_U1_LPS_VAL, + BTC_SET_U1_RPWM_VAL, + /* type trigger some action */ + BTC_SET_ACT_LEAVE_LPS, + BTC_SET_ACT_ENTER_LPS, + BTC_SET_ACT_NORMAL_LPS, + BTC_SET_ACT_DISABLE_LOW_POWER, + BTC_SET_ACT_UPDATE_RAMASK, + BTC_SET_ACT_SEND_MIMO_PS, + /* BT Coex related */ + BTC_SET_ACT_CTRL_BT_INFO, + BTC_SET_ACT_CTRL_BT_COEX, + BTC_SET_ACT_CTRL_8723B_ANT, + /*=================*/ + BTC_SET_MAX +} BTC_SET_TYPE, *PBTC_SET_TYPE; + +typedef enum _BTC_DBG_DISP_TYPE { + BTC_DBG_DISP_COEX_STATISTICS = 0x0, + BTC_DBG_DISP_BT_LINK_INFO = 0x1, + BTC_DBG_DISP_WIFI_STATUS = 0x2, + BTC_DBG_DISP_MAX +} BTC_DBG_DISP_TYPE, *PBTC_DBG_DISP_TYPE; + +typedef enum _BTC_NOTIFY_TYPE_IPS { + BTC_IPS_LEAVE = 0x0, + BTC_IPS_ENTER = 0x1, + BTC_IPS_MAX +} BTC_NOTIFY_TYPE_IPS, *PBTC_NOTIFY_TYPE_IPS; +typedef enum _BTC_NOTIFY_TYPE_LPS { + BTC_LPS_DISABLE = 0x0, + BTC_LPS_ENABLE = 0x1, + BTC_LPS_MAX +} BTC_NOTIFY_TYPE_LPS, *PBTC_NOTIFY_TYPE_LPS; +typedef enum _BTC_NOTIFY_TYPE_SCAN { + BTC_SCAN_FINISH = 0x0, + BTC_SCAN_START = 0x1, + BTC_SCAN_START_2G = 0x2, + BTC_SCAN_MAX +} BTC_NOTIFY_TYPE_SCAN, *PBTC_NOTIFY_TYPE_SCAN; +typedef enum _BTC_NOTIFY_TYPE_SWITCHBAND { + BTC_NOT_SWITCH = 0x0, + BTC_SWITCH_TO_24G = 0x1, + BTC_SWITCH_TO_5G = 0x2, + BTC_SWITCH_TO_24G_NOFORSCAN = 0x3, + BTC_SWITCH_MAX +} BTC_NOTIFY_TYPE_SWITCHBAND, *PBTC_NOTIFY_TYPE_SWITCHBAND; +typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE { + BTC_ASSOCIATE_FINISH = 0x0, + BTC_ASSOCIATE_START = 0x1, + BTC_ASSOCIATE_5G_FINISH = 0x2, + BTC_ASSOCIATE_5G_START = 0x3, + BTC_ASSOCIATE_MAX +} BTC_NOTIFY_TYPE_ASSOCIATE, *PBTC_NOTIFY_TYPE_ASSOCIATE; +typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS { + BTC_MEDIA_DISCONNECT = 0x0, + BTC_MEDIA_CONNECT = 0x1, + BTC_MEDIA_MAX +} BTC_NOTIFY_TYPE_MEDIA_STATUS, *PBTC_NOTIFY_TYPE_MEDIA_STATUS; +typedef enum _BTC_NOTIFY_TYPE_SPECIFIC_PACKET { + BTC_PACKET_UNKNOWN = 0x0, + BTC_PACKET_DHCP = 0x1, + BTC_PACKET_ARP = 0x2, + BTC_PACKET_EAPOL = 0x3, + BTC_PACKET_MAX +} BTC_NOTIFY_TYPE_SPECIFIC_PACKET, *PBTC_NOTIFY_TYPE_SPECIFIC_PACKET; +typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION { + BTC_STACK_OP_NONE = 0x0, + BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1, + BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2, + BTC_STACK_OP_MAX +} BTC_NOTIFY_TYPE_STACK_OPERATION, *PBTC_NOTIFY_TYPE_STACK_OPERATION; + +/* Bryant Add */ +typedef enum _BTC_ANTENNA_POS { + BTC_ANTENNA_AT_MAIN_PORT = 0x1, + BTC_ANTENNA_AT_AUX_PORT = 0x2, +} BTC_ANTENNA_POS, *PBTC_ANTENNA_POS; + +/* Bryant Add */ +typedef enum _BTC_BT_OFFON { + BTC_BT_OFF = 0x0, + BTC_BT_ON = 0x1, +} BTC_BTOFFON, *PBTC_BT_OFFON; + +/*================================================== +For following block is for coex offload +==================================================*/ +typedef struct _COL_H2C { + u1Byte opcode; + u1Byte opcode_ver:4; + u1Byte req_num:4; + u1Byte buf[1]; +} COL_H2C, *PCOL_H2C; + +#define COL_C2H_ACK_HDR_LEN 3 +typedef struct _COL_C2H_ACK { + u1Byte status; + u1Byte opcode_ver:4; + u1Byte req_num:4; + u1Byte ret_len; + u1Byte buf[1]; +} COL_C2H_ACK, *PCOL_C2H_ACK; + +#define COL_C2H_IND_HDR_LEN 3 +typedef struct _COL_C2H_IND { + u1Byte type; + u1Byte version; + u1Byte length; + u1Byte data[1]; +} COL_C2H_IND, *PCOL_C2H_IND; + +/*============================================ +NOTE: for debug message, the following define should match +the strings in coexH2cResultString. +============================================*/ +typedef enum _COL_H2C_STATUS { + /* c2h status */ + COL_STATUS_C2H_OK = 0x00, /* Wifi received H2C request and check content ok. */ + COL_STATUS_C2H_UNKNOWN = 0x01, /* Not handled routine */ + COL_STATUS_C2H_UNKNOWN_OPCODE = 0x02, /* Invalid OP code, It means that wifi firmware received an undefiend OP code. */ + COL_STATUS_C2H_OPCODE_VER_MISMATCH = 0x03, /* Wifi firmware and wifi driver mismatch, need to update wifi driver or wifi or. */ + COL_STATUS_C2H_PARAMETER_ERROR = 0x04, /* Error paraneter.(ex: parameters = NULL but it should have values) */ + COL_STATUS_C2H_PARAMETER_OUT_OF_RANGE = 0x05, /* Wifi firmware needs to check the parameters from H2C request and return the status.(ex: ch = 500, it's wrong) */ + /* other COL status start from here */ + COL_STATUS_C2H_REQ_NUM_MISMATCH , /* c2h req_num mismatch, means this c2h is not we expected. */ + COL_STATUS_H2C_HALMAC_FAIL , /* HALMAC return fail. */ + COL_STATUS_H2C_TIMTOUT , /* not received the c2h response from fw */ + COL_STATUS_INVALID_C2H_LEN , /* invalid coex offload c2h ack length, must >= 3 */ + COL_STATUS_COEX_DATA_OVERFLOW , /* coex returned length over the c2h ack length. */ + COL_STATUS_MAX +} COL_H2C_STATUS, *PCOL_H2C_STATUS; + +#define COL_MAX_H2C_REQ_NUM 16 + +#define COL_H2C_BUF_LEN 20 +typedef enum _COL_OPCODE { + COL_OP_WIFI_STATUS_NOTIFY = 0x0, + COL_OP_WIFI_PROGRESS_NOTIFY = 0x1, + COL_OP_WIFI_INFO_NOTIFY = 0x2, + COL_OP_WIFI_POWER_STATE_NOTIFY = 0x3, + COL_OP_SET_CONTROL = 0x4, + COL_OP_GET_CONTROL = 0x5, + COL_OP_WIFI_OPCODE_MAX +} COL_OPCODE, *PCOL_OPCODE; + +typedef enum _COL_IND_TYPE { + COL_IND_BT_INFO = 0x0, + COL_IND_PSTDMA = 0x1, + COL_IND_LIMITED_TX_RX = 0x2, + COL_IND_COEX_TABLE = 0x3, + COL_IND_REQ = 0x4, + COL_IND_MAX +} COL_IND_TYPE, *PCOL_IND_TYPE; + +typedef struct _COL_SINGLE_H2C_RECORD { + u1Byte h2c_buf[COL_H2C_BUF_LEN]; /* the latest sent h2c buffer */ + u4Byte h2c_len; + u1Byte c2h_ack_buf[COL_H2C_BUF_LEN]; /* the latest received c2h buffer */ + u4Byte c2h_ack_len; + u4Byte count; /* the total number of the sent h2c command */ + u4Byte status[COL_STATUS_MAX]; /* the c2h status for the sent h2c command */ +} COL_SINGLE_H2C_RECORD, *PCOL_SINGLE_H2C_RECORD; + +typedef struct _COL_SINGLE_C2H_IND_RECORD { + u1Byte ind_buf[COL_H2C_BUF_LEN]; /* the latest received c2h indication buffer */ + u4Byte ind_len; + u4Byte count; /* the total number of the rcvd c2h indication */ + u4Byte status[COL_STATUS_MAX]; /* the c2h indication verified status */ +} COL_SINGLE_C2H_IND_RECORD, *PCOL_SINGLE_C2H_IND_RECORD; + +typedef struct _BTC_OFFLOAD { + /* H2C command related */ + u1Byte h2c_req_num; + u4Byte cnt_h2c_sent; + COL_SINGLE_H2C_RECORD h2c_record[COL_OP_WIFI_OPCODE_MAX]; + + /* C2H Ack related */ + u4Byte cnt_c2h_ack; + u4Byte status[COL_STATUS_MAX]; + struct completion c2h_event[COL_MAX_H2C_REQ_NUM]; /* for req_num = 1~COL_MAX_H2C_REQ_NUM */ + u1Byte c2h_ack_buf[COL_MAX_H2C_REQ_NUM][COL_H2C_BUF_LEN]; + u1Byte c2h_ack_len[COL_MAX_H2C_REQ_NUM]; + + /* C2H Indication related */ + u4Byte cnt_c2h_ind; + COL_SINGLE_C2H_IND_RECORD c2h_ind_record[COL_IND_MAX]; + u4Byte c2h_ind_status[COL_STATUS_MAX]; + u1Byte c2h_ind_buf[COL_H2C_BUF_LEN]; + u1Byte c2h_ind_len; +} BTC_OFFLOAD, *PBTC_OFFLOAD; +extern BTC_OFFLOAD gl_coex_offload; +/*==================================================*/ + +typedef u1Byte +(*BFP_BTC_R1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef u2Byte +(*BFP_BTC_R2)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef u4Byte +(*BFP_BTC_R4)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef VOID +(*BFP_BTC_W1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u1Byte Data + ); +typedef VOID +(*BFP_BTC_W1_BIT_MASK)( + IN PVOID pBtcContext, + IN u4Byte regAddr, + IN u1Byte bitMask, + IN u1Byte data1b + ); +typedef VOID +(*BFP_BTC_W2)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u2Byte Data + ); +typedef VOID +(*BFP_BTC_W4)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte Data + ); +typedef VOID +(*BFP_BTC_LOCAL_REG_W1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u1Byte Data + ); +typedef VOID +(*BFP_BTC_SET_BB_REG)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); +typedef u4Byte +(*BFP_BTC_GET_BB_REG)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); +typedef VOID +(*BFP_BTC_SET_RF_REG)( + IN PVOID pBtcContext, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); +typedef u4Byte +(*BFP_BTC_GET_RF_REG)( + IN PVOID pBtcContext, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); +typedef VOID +(*BFP_BTC_FILL_H2C)( + IN PVOID pBtcContext, + IN u1Byte elementId, + IN u4Byte cmdLen, + IN pu1Byte pCmdBuffer + ); + +typedef BOOLEAN +(*BFP_BTC_GET)( + IN PVOID pBtCoexist, + IN u1Byte getType, + OUT PVOID pOutBuf + ); + +typedef BOOLEAN +(*BFP_BTC_SET)( + IN PVOID pBtCoexist, + IN u1Byte setType, + OUT PVOID pInBuf + ); +typedef u2Byte +(*BFP_BTC_SET_BT_REG)( + IN PVOID pBtcContext, + IN u1Byte regType, + IN u4Byte offset, + IN u4Byte value + ); +typedef BOOLEAN +(*BFP_BTC_SET_BT_ANT_DETECTION)( + IN PVOID pBtcContext, + IN u1Byte txTime, + IN u1Byte btChnl + ); + +typedef BOOLEAN +(*BFP_BTC_SET_BT_TRX_MASK)( + IN PVOID pBtcContext, + IN u1Byte bt_trx_mask + ); + +typedef u4Byte +(*BFP_BTC_GET_BT_REG)( + IN PVOID pBtcContext, + IN u1Byte regType, + IN u4Byte offset + ); +typedef VOID +(*BFP_BTC_DISP_DBG_MSG)( + IN PVOID pBtCoexist, + IN u1Byte dispType + ); + +typedef COL_H2C_STATUS +(*BFP_BTC_COEX_H2C_PROCESS)( + IN PVOID pBtCoexist, + IN u1Byte opcode, + IN u1Byte opcode_ver, + IN pu1Byte ph2c_par, + IN u1Byte h2c_par_len + ); + +typedef u4Byte +(*BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE)( + IN PVOID pBtcContext + ); + +typedef u4Byte +(*BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION)( + IN PVOID pBtcContext + ); + +typedef u4Byte +(*BFP_BTC_GET_PHYDM_VERSION)( + IN PVOID pBtcContext + ); + +typedef VOID +(*BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD)( + IN PVOID pDM_Odm, + IN u1Byte RA_offset_direction, + IN u1Byte RA_threshold_offset + ); + +typedef u4Byte +(*BTC_PHYDM_CMNINFOQUERY)( + IN PVOID pDM_Odm, + IN u1Byte info_type + ); + +typedef u1Byte +(*BFP_BTC_GET_ANT_DET_VAL_FROM_BT)( + + IN PVOID pBtcContext + ); + +typedef u1Byte +(*BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT)( + IN PVOID pBtcContext + ); + +typedef u4Byte +(*BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT)( + IN PVOID pBtcContext, + IN u1Byte scanType + ); + +typedef BOOLEAN +(*BFP_BTC_GET_BT_AFH_MAP_FROM_BT)( + IN PVOID pBtcContext, + IN u1Byte mapType, + OUT pu1Byte afhMap + ); + +struct btc_bt_info { + boolean bt_disabled; + boolean bt_enable_disable_change; + u8 rssi_adjust_for_agc_table_on; + u8 rssi_adjust_for_1ant_coex_type; + boolean pre_bt_ctrl_agg_buf_size; + boolean bt_ctrl_agg_buf_size; + boolean pre_reject_agg_pkt; + boolean reject_agg_pkt; + boolean increase_scan_dev_num; + boolean bt_tx_rx_mask; + u8 pre_agg_buf_size; + u8 agg_buf_size; + boolean bt_busy; + boolean limited_dig; + u16 bt_hci_ver; + u16 bt_real_fw_ver; + u8 bt_fw_ver; + u32 get_bt_fw_ver_cnt; + u32 bt_get_fw_ver; + boolean miracast_plus_bt; + + boolean bt_disable_low_pwr; + + boolean bt_ctrl_lps; + boolean bt_lps_on; + boolean force_to_roam; /* for 1Ant solution */ + u8 lps_val; + u8 rpwm_val; + u32 ra_mask; +}; + +struct btc_stack_info { + boolean profile_notified; + u16 hci_version; /* stack hci version */ + u8 num_of_link; + boolean bt_link_exist; + boolean sco_exist; + boolean acl_exist; + boolean a2dp_exist; + boolean hid_exist; + u8 num_of_hid; + boolean pan_exist; + boolean unknown_acl_exist; + s8 min_bt_rssi; +}; + +struct btc_bt_link_info { + boolean bt_link_exist; + boolean bt_hi_pri_link_exist; + boolean sco_exist; + boolean sco_only; + boolean a2dp_exist; + boolean a2dp_only; + boolean hid_exist; + boolean hid_only; + boolean pan_exist; + boolean pan_only; + boolean slave_role; + boolean acl_busy; +}; + +struct btc_statistics { + u32 cnt_bind; + u32 cnt_power_on; + u32 cnt_pre_load_firmware; + u32 cnt_init_hw_config; + u32 cnt_init_coex_dm; + u32 cnt_ips_notify; + u32 cnt_lps_notify; + u32 cnt_scan_notify; + u32 cnt_connect_notify; + u32 cnt_media_status_notify; + u32 cnt_specific_packet_notify; + u32 cnt_bt_info_notify; + u32 cnt_rf_status_notify; + u32 cnt_periodical; + u32 cnt_coex_dm_switch; + u32 cnt_stack_operation_notify; + u32 cnt_dbg_ctrl; +}; + +struct btc_coexist { + BOOLEAN bBinded; /*make sure only one adapter can bind the data context*/ + PVOID Adapter; /*default adapter*/ + struct btc_board_info board_info; + struct btc_bt_info bt_info; /*some bt info referenced by non-bt module*/ + struct btc_stack_info stack_info; + struct btc_bt_link_info bt_link_info; + + BTC_CHIP_INTERFACE chip_interface; + PVOID odm_priv; + + BOOLEAN initilized; + BOOLEAN stop_coex_dm; + BOOLEAN manual_control; + BOOLEAN bdontenterLPS; + pu1Byte cli_buf; + struct btc_statistics statistics; + u1Byte pwrModeVal[10]; + + /* function pointers */ + /* io related */ + BFP_BTC_R1 btc_read_1byte; + BFP_BTC_W1 btc_write_1byte; + BFP_BTC_W1_BIT_MASK btc_write_1byte_bitmask; + BFP_BTC_R2 btc_read_2byte; + BFP_BTC_W2 btc_write_2byte; + BFP_BTC_R4 btc_read_4byte; + BFP_BTC_W4 btc_write_4byte; + BFP_BTC_LOCAL_REG_W1 btc_write_local_reg_1byte; + /* read/write bb related */ + BFP_BTC_SET_BB_REG btc_set_bb_reg; + BFP_BTC_GET_BB_REG btc_get_bb_reg; + + /* read/write rf related */ + BFP_BTC_SET_RF_REG btc_set_rf_reg; + BFP_BTC_GET_RF_REG btc_get_rf_reg; + + /* fill h2c related */ + BFP_BTC_FILL_H2C btc_fill_h2c; + /* other */ + BFP_BTC_DISP_DBG_MSG btc_disp_dbg_msg; + /* normal get/set related */ + BFP_BTC_GET btc_get; + BFP_BTC_SET btc_set; + + BFP_BTC_GET_BT_REG btc_get_bt_reg; + BFP_BTC_SET_BT_REG btc_set_bt_reg; + + BFP_BTC_SET_BT_ANT_DETECTION btc_set_bt_ant_detection; + + BFP_BTC_COEX_H2C_PROCESS btc_coex_h2c_process; + BFP_BTC_SET_BT_TRX_MASK btc_set_bt_trx_mask; + BFP_BTC_GET_BT_COEX_SUPPORTED_FEATURE btc_get_bt_coex_supported_feature; + BFP_BTC_GET_BT_COEX_SUPPORTED_VERSION btc_get_bt_coex_supported_version; + BFP_BTC_GET_PHYDM_VERSION btc_get_bt_phydm_version; + BTC_PHYDM_MODIFY_RA_PCR_THRESHLOD btc_phydm_modify_RA_PCR_threshold; + BTC_PHYDM_CMNINFOQUERY btc_phydm_query_PHY_counter; + BFP_BTC_GET_ANT_DET_VAL_FROM_BT btc_get_ant_det_val_from_bt; + BFP_BTC_GET_BLE_SCAN_TYPE_FROM_BT btc_get_ble_scan_type_from_bt; + BFP_BTC_GET_BLE_SCAN_PARA_FROM_BT btc_get_ble_scan_para_from_bt; + BFP_BTC_GET_BT_AFH_MAP_FROM_BT btc_get_bt_afh_map_from_bt; +}; +typedef struct btc_coexist *PBTC_COEXIST; + +extern struct btc_coexist GLBtCoexist; + +BOOLEAN +EXhalbtcoutsrc_InitlizeVariables( + IN PVOID Adapter + ); +VOID +EXhalbtcoutsrc_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtcoutsrc_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte action + ); +VOID +EXhalbtcoutsrc_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN RT_MEDIA_STATUS mediaStatus + ); +VOID +EXhalbtcoutsrc_SpecificPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pktType + ); +VOID +EXhalbtcoutsrc_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtcoutsrc_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtcoutsrc_CoexDmSwitch( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ); +VOID +EXhalbtcoutsrc_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); +VOID +EXhalbtcoutsrc_StackUpdateProfileInfo( + VOID + ); +VOID +EXhalbtcoutsrc_SetHciVersion( + IN u2Byte hciVersion + ); +VOID +EXhalbtcoutsrc_SetBtPatchVersion( + IN u2Byte btHciVersion, + IN u2Byte btPatchVersion + ); +VOID +EXhalbtcoutsrc_UpdateMinBtRssi( + IN s1Byte btRssi + ); +VOID +EXhalbtcoutsrc_SetChipType( + IN u1Byte chipType + ); +VOID +EXhalbtcoutsrc_SetAntNum( + IN u1Byte type, + IN u1Byte antNum + ); +VOID +EXhalbtcoutsrc_SetSingleAntPath( + IN u1Byte singleAntPath + ); +VOID +EXhalbtcoutsrc_DisplayBtCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ); + +#define MASKBYTE0 0xff +#define MASKBYTE1 0xff00 +#define MASKBYTE2 0xff0000 +#define MASKBYTE3 0xff000000 +#define MASKHWORD 0xffff0000 +#define MASKLWORD 0x0000ffff +#define MASKDWORD 0xffffffff +#define MASK12BITS 0xfff +#define MASKH4BITS 0xf0000000 +#define MASKOFDM_D 0xffc00000 +#define MASKCCK 0x3f3f3f3f + +#endif diff --git a/drivers/staging/rtl8821ce/hal/btc/mp_precomp.h b/drivers/staging/rtl8821ce/hal/btc/mp_precomp.h new file mode 100644 index 000000000000..dd19104a51e9 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/btc/mp_precomp.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __MP_PRECOMP_H__ +#define __MP_PRECOMP_H__ + +#include <drv_types.h> +#include <hal_data.h> + +#define BT_TMP_BUF_SIZE 100 + +#define rsprintf snprintf + +#define DCMD_Printf DBG_BT_INFO + +#define delay_ms(ms) rtw_mdelay_os(ms) + +#ifdef bEnable +#undef bEnable +#endif + +#define WPP_SOFTWARE_TRACE 0 + +typedef enum _BTC_MSG_COMP_TYPE { + COMP_COEX = 0, + COMP_MAX +} BTC_MSG_COMP_TYPE; +extern u4Byte GLBtcDbgType[]; + +#define DBG_OFF 0 +#define DBG_SEC 1 +#define DBG_SERIOUS 2 +#define DBG_WARNING 3 +#define DBG_LOUD 4 +#define DBG_TRACE 5 + +#define HS_SUPPORT 1 + +#include "halbtcoutsrc.h" +#include "halbtc8821c1ant.h" +#include "halbtc8821c2ant.h" + +/* for wifi only mode */ +#include "hal_btcoex_wifionly.h" +#include "halbtc8821cwifionly.h" + +#endif /* __MP_PRECOMP_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/efuse/efuse_mask.h b/drivers/staging/rtl8821ce/hal/efuse/efuse_mask.h new file mode 100644 index 000000000000..bab9bb2a83c0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/efuse/efuse_mask.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + + #include "rtl8821c/HalEfuseMask8821C_USB.h" + +#elif DEV_BUS_TYPE == RT_PCI_INTERFACE + + #include "rtl8821c/HalEfuseMask8821C_PCIE.h" + +#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE + + #include "rtl8821c/HalEfuseMask8821C_SDIO.h" + +#endif diff --git a/drivers/staging/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c b/drivers/staging/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c new file mode 100644 index 000000000000..5c9326c6f3c9 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.c @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/* #include "Mp_Precomp.h" */ +/* #include "../odm_precomp.h" */ + +#include <drv_types.h> +#include "HalEfuseMask8821C_PCIE.h" + +/****************************************************************************** +* MPCIE.TXT +******************************************************************************/ + +u1Byte Array_MP_8821C_MPCIE[] = { + 0xFF, + 0xF3, + 0xEF, + 0x9E, + 0x70, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x03, + 0xF7, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0xF1, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + +}; + +u2Byte +EFUSE_GetArrayLen_MP_8821C_MPCIE(VOID) +{ + return sizeof(Array_MP_8821C_MPCIE) / sizeof(u1Byte); +} + +VOID +EFUSE_GetMaskArray_MP_8821C_MPCIE( + IN OUT pu1Byte Array +) +{ + u2Byte len = EFUSE_GetArrayLen_MP_8821C_MPCIE(), i = 0; + + for (i = 0; i < len; ++i) + Array[i] = Array_MP_8821C_MPCIE[i]; +} +BOOLEAN +EFUSE_IsAddressMasked_MP_8821C_MPCIE( + IN u2Byte Offset +) +{ + int r = Offset / 16; + int c = (Offset % 16) / 2; + int result = 0; + + if (c < 4) /* Upper double word */ + result = (Array_MP_8821C_MPCIE[r] & (0x10 << c)); + else + result = (Array_MP_8821C_MPCIE[r] & (0x01 << (c - 4))); + + return (result > 0) ? 0 : 1; +} diff --git a/drivers/staging/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h b/drivers/staging/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h new file mode 100644 index 000000000000..68f74bc7c009 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/efuse/rtl8821c/HalEfuseMask8821C_PCIE.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/****************************************************************************** +* MPCIE.TXT +******************************************************************************/ + +u2Byte +EFUSE_GetArrayLen_MP_8821C_MPCIE(VOID); + +VOID +EFUSE_GetMaskArray_MP_8821C_MPCIE( + IN OUT pu1Byte Array +); + +BOOLEAN +EFUSE_IsAddressMasked_MP_8821C_MPCIE(/* TC: Test Chip, MP: MP Chip */ + IN u2Byte Offset +); diff --git a/drivers/staging/rtl8821ce/hal/hal_btcoex.c b/drivers/staging/rtl8821ce/hal/hal_btcoex.c new file mode 100644 index 000000000000..4db458d00f08 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_btcoex.c @@ -0,0 +1,2741 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define __HAL_BTCOEX_C__ + +#include <hal_data.h> +#include <hal_btcoex.h> +#include "btc/mp_precomp.h" + +/* ************************************ + * Global variables + * ************************************ */ +const char *const BtProfileString[] = { + "NONE", + "A2DP", + "PAN", + "HID", + "SCO", +}; + +const char *const BtSpecString[] = { + "1.0b", + "1.1", + "1.2", + "2.0+EDR", + "2.1+EDR", + "3.0+HS", + "4.0", +}; + +const char *const BtLinkRoleString[] = { + "Master", + "Slave", +}; + +const char *const h2cStaString[] = { + "successful", + "h2c busy", + "rf off", + "fw not read", +}; + +const char *const ioStaString[] = { + "success", + "can not IO", + "rf off", + "fw not read", + "wait io timeout", + "invalid len", + "idle Q empty", + "insert waitQ fail", + "unknown fail", + "wrong level", + "h2c stopped", +}; + +const char *const GLBtcWifiBwString[] = { + "11bg", + "HT20", + "HT40", + "HT80", + "HT160" +}; + +const char *const GLBtcWifiFreqString[] = { + "2.4G", + "5G" +}; + +const char *const GLBtcIotPeerString[] = { + "UNKNOWN", + "REALTEK", + "REALTEK_92SE", + "BROADCOM", + "RALINK", + "ATHEROS", + "CISCO", + "MERU", + "MARVELL", + "REALTEK_SOFTAP", /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */ + "SELF_SOFTAP", /* Self is SoftAP */ + "AIRGO", + "INTEL", + "RTK_APCLIENT", + "REALTEK_81XX", + "REALTEK_WOW", + "REALTEK_JAGUAR_BCUTAP", + "REALTEK_JAGUAR_CCUTAP" +}; + +const char *const coexOpcodeString[] = { + "Wifi status notify", + "Wifi progress", + "Wifi info", + "Power state", + "Set Control", + "Get Control" +}; + +const char *const coexIndTypeString[] = { + "bt info", + "pstdma", + "limited tx/rx", + "coex table", + "request" +}; + +const char *const coexH2cResultString[] = { + "ok", + "unknown", + "un opcode", + "opVer MM", + "par Err", + "par OoR", + "reqNum MM", + "halMac Fail", + "h2c TimeOut", + "Invalid c2h Len", + "data overflow" +}; + +#define HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS 8000 + +struct btc_coexist GLBtCoexist; +BTC_OFFLOAD gl_coex_offload; +u8 GLBtcWiFiInScanState; +u8 GLBtcWiFiInIQKState; +u8 GLBtcWiFiInIPS; +u8 GLBtcWiFiInLPS; +u8 GLBtcBtCoexAliveRegistered; + +/* + * BT control H2C/C2H + */ +/* EXT_EID */ +typedef enum _bt_ext_eid { + C2H_WIFI_FW_ACTIVE_RSP = 0, + C2H_TRIG_BY_BT_FW +} BT_EXT_EID; + +/* C2H_STATUS */ +typedef enum _bt_c2h_status { + BT_STATUS_OK = 0, + BT_STATUS_VERSION_MISMATCH, + BT_STATUS_UNKNOWN_OPCODE, + BT_STATUS_ERROR_PARAMETER +} BT_C2H_STATUS; + +/* C2H BT OP CODES */ +typedef enum _bt_op_code { + BT_OP_GET_BT_VERSION = 0x00, + BT_OP_WRITE_REG_ADDR = 0x0c, + BT_OP_WRITE_REG_VALUE = 0x0d, + + BT_OP_READ_REG = 0x11, + + BT_LO_OP_GET_AFH_MAP_L = 0x1e, + BT_LO_OP_GET_AFH_MAP_M = 0x1f, + BT_LO_OP_GET_AFH_MAP_H = 0x20, + + BT_OP_GET_BT_COEX_SUPPORTED_FEATURE = 0x2a, + BT_OP_GET_BT_COEX_SUPPORTED_VERSION = 0x2b, + BT_OP_GET_BT_ANT_DET_VAL = 0x2c, + BT_OP_GET_BT_BLE_SCAN_PARA = 0x2d, + BT_OP_GET_BT_BLE_SCAN_TYPE = 0x2e, + BT_OP_MAX +} BT_OP_CODE; + +#define BTC_MPOPER_TIMEOUT 50 /* unit: ms */ + +#define C2H_MAX_SIZE 16 +u8 GLBtcBtMpOperSeq; +_mutex GLBtcBtMpOperLock; +_timer GLBtcBtMpOperTimer; +_sema GLBtcBtMpRptSema; +u8 GLBtcBtMpRptSeq; +u8 GLBtcBtMpRptStatus; +u8 GLBtcBtMpRptRsp[C2H_MAX_SIZE]; +u8 GLBtcBtMpRptRspSize; +u8 GLBtcBtMpRptWait; +u8 GLBtcBtMpRptWiFiOK; +u8 GLBtcBtMpRptBTOK; + +/* + * Debug + */ +u32 GLBtcDbgType[COMP_MAX]; +u8 GLBtcDbgBuf[BT_TMP_BUF_SIZE]; +u1Byte gl_btc_trace_buf[BT_TMP_BUF_SIZE]; + +typedef struct _btcoexdbginfo { + u8 *info; + u32 size; /* buffer total size */ + u32 len; /* now used length */ +} BTCDBGINFO, *PBTCDBGINFO; + +BTCDBGINFO GLBtcDbgInfo; + +#define BT_Operation(Adapter) _FALSE + +void DBG_BT_INFO(u8 *dbgmsg) +{ + PBTCDBGINFO pinfo; + u32 msglen, buflen; + u8 *pbuf; + + pinfo = &GLBtcDbgInfo; + + if (NULL == pinfo->info) + return; + + msglen = strlen(dbgmsg); + if (pinfo->len + msglen > pinfo->size) + return; + + pbuf = pinfo->info + pinfo->len; + _rtw_memcpy(pbuf, dbgmsg, msglen); + pinfo->len += msglen; +} + +/* ************************************ + * Debug related function + * ************************************ */ +static u8 halbtcoutsrc_IsBtCoexistAvailable(PBTC_COEXIST pBtCoexist) +{ + if (!pBtCoexist->bBinded || + NULL == pBtCoexist->Adapter) + return _FALSE; + return _TRUE; +} + +static void halbtcoutsrc_DbgInit(void) +{ + u8 i; + + for (i = 0; i < COMP_MAX; i++) + GLBtcDbgType[i] = 0; +} + +static void halbtcoutsrc_EnterPwrLock(PBTC_COEXIST pBtCoexist) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + _enter_pwrlock(&pwrpriv->lock); +} + +static void halbtcoutsrc_ExitPwrLock(PBTC_COEXIST pBtCoexist) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj((PADAPTER)pBtCoexist->Adapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + _exit_pwrlock(&pwrpriv->lock); +} + +static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist) +{ + if (pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC4 + || pBtCoexist->board_info.bt_chip_type == BTC_CHIP_CSR_BC8 + ) + return _FALSE; + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + return _FALSE; + else + return _TRUE; +} + +static u8 halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + padapter = pBtCoexist->Adapter; + + pBtCoexist->bt_info.bt_ctrl_lps = _TRUE; + pBtCoexist->bt_info.bt_lps_on = _FALSE; + + return rtw_btcoex_LPS_Leave(padapter); +} + +void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + padapter = pBtCoexist->Adapter; + + if (pBtCoexist->bdontenterLPS == _FALSE) { + pBtCoexist->bt_info.bt_ctrl_lps = _TRUE; + pBtCoexist->bt_info.bt_lps_on = _TRUE; + + rtw_btcoex_LPS_Enter(padapter); + } +} + +void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + padapter = pBtCoexist->Adapter; + + if (pBtCoexist->bt_info.bt_ctrl_lps) { + pBtCoexist->bt_info.bt_lps_on = _FALSE; + rtw_btcoex_LPS_Leave(padapter); + pBtCoexist->bt_info.bt_ctrl_lps = _FALSE; + } +} + +/* + * Constraint: + * 1. this function will request pwrctrl->lock + */ +void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist) +{ +} + +/* + * Constraint: + * 1. this function will request pwrctrl->lock + */ +void halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist) +{ +} + +void halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable) +{ + pBtCoexist->bt_info.bt_disable_low_pwr = bLowPwrDisable; + if (bLowPwrDisable) + halbtcoutsrc_LeaveLowPower(pBtCoexist); /* leave 32k low power. */ + else + halbtcoutsrc_NormalLowPower(pBtCoexist); /* original 32k low power behavior. */ +} + +void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + BOOLEAN bNeedToAct = _FALSE; + static u32 preTime = 0; + u32 curTime = 0; + + padapter = pBtCoexist->Adapter; + + /* ===================================== */ + /* To void continuous deleteBA=>addBA=>deleteBA=>addBA */ + /* This function is not allowed to continuous called. */ + /* It can only be called after 8 seconds. */ + /* ===================================== */ + + curTime = rtw_systime_to_ms(rtw_get_current_time()); + if ((curTime - preTime) < HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS) /* over 8 seconds you can execute this function again. */ + return; + else + preTime = curTime; + + if (pBtCoexist->bt_info.reject_agg_pkt) { + bNeedToAct = _TRUE; + pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt; + } else { + if (pBtCoexist->bt_info.pre_reject_agg_pkt) { + bNeedToAct = _TRUE; + pBtCoexist->bt_info.pre_reject_agg_pkt = pBtCoexist->bt_info.reject_agg_pkt; + } + + if (pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size != + pBtCoexist->bt_info.bt_ctrl_agg_buf_size) { + bNeedToAct = _TRUE; + pBtCoexist->bt_info.pre_bt_ctrl_agg_buf_size = pBtCoexist->bt_info.bt_ctrl_agg_buf_size; + } + + if (pBtCoexist->bt_info.bt_ctrl_agg_buf_size) { + if (pBtCoexist->bt_info.pre_agg_buf_size != + pBtCoexist->bt_info.agg_buf_size) + bNeedToAct = _TRUE; + pBtCoexist->bt_info.pre_agg_buf_size = pBtCoexist->bt_info.agg_buf_size; + } + } + + if (bNeedToAct) + rtw_btcoex_rx_ampdu_apply(padapter); +} + +u8 halbtcoutsrc_is_autoload_fail(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + + padapter = pBtCoexist->Adapter; + pHalData = GET_HAL_DATA(padapter); + + return pHalData->bautoload_fail_flag; +} + +u8 halbtcoutsrc_is_fw_ready(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + padapter = pBtCoexist->Adapter; + + return padapter->bFWReady; +} + +u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter) +{ + if (rtw_mi_check_status(padapter, MI_AP_MODE)) + return _TRUE; + if (rtw_mi_busy_traffic_check(padapter, _FALSE)) + return _TRUE; + + return _FALSE; +} + +static u32 _halbtcoutsrc_GetWifiLinkStatus(PADAPTER padapter) +{ + struct mlme_priv *pmlmepriv; + u8 bp2p; + u32 portConnectedStatus; + + pmlmepriv = &padapter->mlmepriv; + bp2p = _FALSE; + portConnectedStatus = 0; + + if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) + bp2p = _TRUE; + + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) { + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + if (_TRUE == bp2p) + portConnectedStatus |= WIFI_P2P_GO_CONNECTED; + else + portConnectedStatus |= WIFI_AP_CONNECTED; + } else { + if (_TRUE == bp2p) + portConnectedStatus |= WIFI_P2P_GC_CONNECTED; + else + portConnectedStatus |= WIFI_STA_CONNECTED; + } + } + + return portConnectedStatus; +} + +u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist) +{ + /* ================================= */ + /* return value: */ + /* [31:16]=> connected port number */ + /* [15:0]=> port connected bit define */ + /* ================================ */ + + PADAPTER padapter; + u32 retVal; + u32 portConnectedStatus, numOfConnectedPort; + struct dvobj_priv *dvobj; + _adapter *iface; + int i; + + padapter = pBtCoexist->Adapter; + retVal = 0; + portConnectedStatus = 0; + numOfConnectedPort = 0; + dvobj = adapter_to_dvobj(padapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + retVal = _halbtcoutsrc_GetWifiLinkStatus(iface); + if (retVal) { + portConnectedStatus |= retVal; + numOfConnectedPort++; + } + } + } + retVal = (numOfConnectedPort << 16) | portConnectedStatus; + + return retVal; +} + +static void _btmpoper_timer_hdl(void *p) +{ + if (GLBtcBtMpRptWait) { + GLBtcBtMpRptWait = 0; + _rtw_up_sema(&GLBtcBtMpRptSema); + } +} + +/* + * !IMPORTANT! + * Before call this function, caller should acquire "GLBtcBtMpOperLock"! + * Othrewise there will be racing problem and something may go wrong. + */ +static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cmd, u8 size) +{ + PADAPTER padapter; + u8 buf[H2C_BTMP_OPER_LEN] = {0}; + u8 buflen; + u8 seq; + s32 ret; + + if (!cmd && size) + size = 0; + if ((size + 2) > H2C_BTMP_OPER_LEN) + return BT_STATUS_H2C_LENGTH_EXCEEDED; + buflen = size + 2; + + seq = GLBtcBtMpOperSeq & 0xF; + GLBtcBtMpOperSeq++; + + buf[0] = (opcodever & 0xF) | (seq << 4); + buf[1] = opcode; + if (cmd && size) + _rtw_memcpy(buf + 2, cmd, size); + + GLBtcBtMpRptWait = 1; + GLBtcBtMpRptWiFiOK = 0; + GLBtcBtMpRptBTOK = 0; + GLBtcBtMpRptStatus = 0; + padapter = pBtCoexist->Adapter; + _set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT); + if (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) { + _cancel_timer_ex(&GLBtcBtMpOperTimer); + ret = BT_STATUS_H2C_FAIL; + goto exit; + } + + _rtw_down_sema(&GLBtcBtMpRptSema); + /* GLBtcBtMpRptWait should be 0 here*/ + + if (!GLBtcBtMpRptWiFiOK) { + RTW_ERR("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__); + ret = BT_STATUS_H2C_TIMTOUT; + goto exit; + } + if (!GLBtcBtMpRptBTOK) { + RTW_DBG("%s: Didn't get BT response!\n", __FUNCTION__); + ret = BT_STATUS_H2C_BT_NO_RSP; + goto exit; + } + if (seq != GLBtcBtMpRptSeq) { + RTW_ERR("%s: Sequence number not match!(%d!=%d)!\n", + __FUNCTION__, seq, GLBtcBtMpRptSeq); + ret = BT_STATUS_C2H_REQNUM_MISMATCH; + goto exit; + } + + switch (GLBtcBtMpRptStatus) { + /* Examine the status reported from C2H */ + case BT_STATUS_OK: + ret = BT_STATUS_BT_OP_SUCCESS; + RTW_DBG("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__); + break; + case BT_STATUS_VERSION_MISMATCH: + ret = BT_STATUS_OPCODE_L_VERSION_MISMATCH; + RTW_DBG("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__); + break; + case BT_STATUS_UNKNOWN_OPCODE: + ret = BT_STATUS_UNKNOWN_OPCODE_L; + RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__); + break; + case BT_STATUS_ERROR_PARAMETER: + ret = BT_STATUS_PARAMETER_FORMAT_ERROR_L; + RTW_DBG("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__); + break; + default: + ret = BT_STATUS_UNKNOWN_STATUS_L; + RTW_DBG("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__); + break; + } + +exit: + return ret; +} + +u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist) +{ + if (pBtCoexist->bt_info.get_bt_fw_ver_cnt <= 5) { + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + _irqL irqL; + u8 ret; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0); + if (BT_STATUS_BT_OP_SUCCESS == ret) { + pBtCoexist->bt_info.bt_real_fw_ver = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + pBtCoexist->bt_info.bt_fw_ver = *(GLBtcBtMpRptRsp + 2); + pBtCoexist->bt_info.get_bt_fw_ver_cnt++; + } + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + } + } + + return pBtCoexist->bt_info.bt_real_fw_ver; +} + +s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + s32 undecorated_smoothed_pwdb = 0; + + pHalData = GET_HAL_DATA(padapter); + + undecorated_smoothed_pwdb = pHalData->entry_min_undecorated_smoothed_pwdb; + + return undecorated_smoothed_pwdb; +} + +u32 halbtcoutsrc_GetBtCoexSupportedFeature(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 data = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_COEX_SUPPORTED_FEATURE; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; +} + +u32 halbtcoutsrc_GetBtCoexSupportedVersion(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 data = 0xFFFF; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_COEX_SUPPORTED_VERSION; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; +} + +static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter) +{ + struct mlme_priv *pmlmepriv; + struct mlme_ext_priv *pmlmeext; + static u8 scan_AP_num = 0; + + pmlmepriv = &padapter->mlmepriv; + pmlmeext = &padapter->mlmeextpriv; + + if (GLBtcWiFiInScanState == _FALSE) { + if (pmlmepriv->num_of_scanned > 0xFF) + scan_AP_num = 0xFF; + else + scan_AP_num = (u8)pmlmepriv->num_of_scanned; + } + + return scan_AP_num; +} + +u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + struct mlme_ext_priv *mlmeext; + u8 bSoftApExist, bVwifiExist; + u8 *pu8; + s32 *pS4Tmp; + u32 *pU4Tmp; + u8 *pU1Tmp; + u8 ret; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return _FALSE; + + padapter = pBtCoexist->Adapter; + pHalData = GET_HAL_DATA(padapter); + mlmeext = &padapter->mlmeextpriv; + bSoftApExist = _FALSE; + bVwifiExist = _FALSE; + pu8 = (u8 *)pOutBuf; + pS4Tmp = (s32 *)pOutBuf; + pU4Tmp = (u32 *)pOutBuf; + pU1Tmp = (u8 *)pOutBuf; + ret = _TRUE; + + switch (getType) { + case BTC_GET_BL_HS_OPERATION: + *pu8 = _FALSE; + ret = _FALSE; + break; + + case BTC_GET_BL_HS_CONNECTING: + *pu8 = _FALSE; + ret = _FALSE; + break; + + case BTC_GET_BL_WIFI_FW_READY: + *pu8 = halbtcoutsrc_is_fw_ready(pBtCoexist); + break; + + case BTC_GET_BL_WIFI_CONNECTED: + *pu8 = (rtw_mi_check_status(padapter, MI_LINKED)) ? _TRUE : _FALSE; + break; + + case BTC_GET_BL_WIFI_BUSY: + *pu8 = halbtcoutsrc_IsWifiBusy(padapter); + break; + + case BTC_GET_BL_WIFI_SCAN: + /* Use the value of the new variable GLBtcWiFiInScanState to judge whether WiFi is in scan state or not, since the originally used flag + WIFI_SITE_MONITOR in fwstate may not be cleared in time */ + *pu8 = GLBtcWiFiInScanState; + break; + + case BTC_GET_BL_WIFI_LINK: + *pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE; + break; + + case BTC_GET_BL_WIFI_ROAM: + *pu8 = (rtw_mi_check_status(padapter, MI_STA_LINKING)) ? _TRUE : _FALSE; + break; + + case BTC_GET_BL_WIFI_4_WAY_PROGRESS: + *pu8 = _FALSE; + break; + + case BTC_GET_BL_WIFI_UNDER_5G: + *pu8 = (pHalData->current_band_type == 1) ? _TRUE : _FALSE; + break; + + case BTC_GET_BL_WIFI_AP_MODE_ENABLE: + *pu8 = (rtw_mi_check_status(padapter, MI_AP_MODE)) ? _TRUE : _FALSE; + break; + + case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION: + *pu8 = padapter->securitypriv.dot11PrivacyAlgrthm == 0 ? _FALSE : _TRUE; + break; + + case BTC_GET_BL_WIFI_UNDER_B_MODE: + if (mlmeext->cur_wireless_mode == WIRELESS_11B) + *pu8 = _TRUE; + else + *pu8 = _FALSE; + break; + + case BTC_GET_BL_WIFI_IS_IN_MP_MODE: + if (padapter->registrypriv.mp_mode == 0) + *pu8 = _FALSE; + else + *pu8 = _TRUE; + break; + + case BTC_GET_BL_EXT_SWITCH: + *pu8 = _FALSE; + break; + case BTC_GET_BL_IS_ASUS_8723B: + /* Always return FALSE in linux driver since this case is added only for windows driver */ + *pu8 = _FALSE; + break; + + case BTC_GET_BL_RF4CE_CONNECTED: + *pu8 = FALSE; + break; + + case BTC_GET_S4_WIFI_RSSI: + *pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter); + break; + + case BTC_GET_S4_HS_RSSI: + *pS4Tmp = 0; + ret = _FALSE; + break; + + case BTC_GET_U4_WIFI_BW: + if (IsLegacyOnly(mlmeext->cur_wireless_mode)) + *pU4Tmp = BTC_WIFI_BW_LEGACY; + else { + switch (pHalData->current_channel_bw) { + case CHANNEL_WIDTH_20: + *pU4Tmp = BTC_WIFI_BW_HT20; + break; + case CHANNEL_WIDTH_40: + *pU4Tmp = BTC_WIFI_BW_HT40; + break; + case CHANNEL_WIDTH_80: + *pU4Tmp = BTC_WIFI_BW_HT80; + break; + case CHANNEL_WIDTH_160: + *pU4Tmp = BTC_WIFI_BW_HT160; + break; + default: + RTW_INFO("[BTCOEX] unknown bandwidth(%d)\n", pHalData->current_channel_bw); + *pU4Tmp = BTC_WIFI_BW_HT40; + break; + } + + } + break; + + case BTC_GET_U4_WIFI_TRAFFIC_DIRECTION: { + PRT_LINK_DETECT_T plinkinfo; + plinkinfo = &padapter->mlmepriv.LinkDetectInfo; + + if (plinkinfo->NumTxOkInPeriod > plinkinfo->NumRxOkInPeriod) + *pU4Tmp = BTC_WIFI_TRAFFIC_TX; + else + *pU4Tmp = BTC_WIFI_TRAFFIC_RX; + } + break; + + case BTC_GET_U4_WIFI_FW_VER: + *pU4Tmp = pHalData->firmware_version << 16; + *pU4Tmp |= pHalData->firmware_sub_version; + break; + + case BTC_GET_U4_WIFI_LINK_STATUS: + *pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist); + break; + + case BTC_GET_U4_BT_PATCH_VER: + *pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist); + break; + + case BTC_GET_U4_VENDOR: + *pU4Tmp = BTC_VENDOR_OTHER; + break; + + case BTC_GET_U4_SUPPORTED_VERSION: + *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedVersion(pBtCoexist); + break; + case BTC_GET_U4_SUPPORTED_FEATURE: + *pU4Tmp = halbtcoutsrc_GetBtCoexSupportedFeature(pBtCoexist); + break; + + case BTC_GET_U4_WIFI_IQK_TOTAL: + *pU4Tmp = pHalData->odmpriv.n_iqk_cnt; + break; + + case BTC_GET_U4_WIFI_IQK_OK: + *pU4Tmp = pHalData->odmpriv.n_iqk_ok_cnt; + break; + + case BTC_GET_U4_WIFI_IQK_FAIL: + *pU4Tmp = pHalData->odmpriv.n_iqk_fail_cnt; + break; + + case BTC_GET_U1_WIFI_DOT11_CHNL: + *pU1Tmp = padapter->mlmeextpriv.cur_channel; + break; + + case BTC_GET_U1_WIFI_CENTRAL_CHNL: + *pU1Tmp = pHalData->current_channel; + break; + + case BTC_GET_U1_WIFI_HS_CHNL: + *pU1Tmp = 0; + ret = _FALSE; + break; + + case BTC_GET_U1_WIFI_P2P_CHNL: + { + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + *pU1Tmp = pwdinfo->operating_channel; + } + break; + + case BTC_GET_U1_MAC_PHY_MODE: + /* *pU1Tmp = BTC_SMSP; + * *pU1Tmp = BTC_DMSP; + * *pU1Tmp = BTC_DMDP; + * *pU1Tmp = BTC_MP_UNKNOWN; */ + break; + + case BTC_GET_U1_AP_NUM: + *pU1Tmp = halbtcoutsrc_GetWifiScanAPNum(padapter); + break; + case BTC_GET_U1_ANT_TYPE: + switch (pHalData->bt_coexist.btAntisolation) { + case 0: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_0; + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_0; + break; + case 1: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_1; + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_1; + break; + case 2: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_2; + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_2; + break; + case 3: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_3; + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_3; + break; + case 4: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_4; + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_4; + break; + } + break; + case BTC_GET_U1_IOT_PEER: + *pU1Tmp = mlmeext->mlmext_info.assoc_AP_vendor; + break; + + /* =======1Ant=========== */ + case BTC_GET_U1_LPS_MODE: + *pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode; + break; + + default: + ret = _FALSE; + break; + } + + return ret; +} + +u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + u8 *pu8; + u8 *pU1Tmp; + u32 *pU4Tmp; + u8 ret; + u8 result = _TRUE; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + pHalData = GET_HAL_DATA(padapter); + pu8 = (u8 *)pInBuf; + pU1Tmp = (u8 *)pInBuf; + pU4Tmp = (u32 *)pInBuf; + ret = _TRUE; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return _FALSE; + + switch (setType) { + /* set some u8 type variables. */ + case BTC_SET_BL_BT_DISABLE: + pBtCoexist->bt_info.bt_disabled = *pu8; + break; + + case BTC_SET_BL_BT_ENABLE_DISABLE_CHANGE: + pBtCoexist->bt_info.bt_enable_disable_change = *pu8; + break; + + case BTC_SET_BL_BT_TRAFFIC_BUSY: + pBtCoexist->bt_info.bt_busy = *pu8; + break; + + case BTC_SET_BL_BT_LIMITED_DIG: + pBtCoexist->bt_info.limited_dig = *pu8; + break; + + case BTC_SET_BL_FORCE_TO_ROAM: + pBtCoexist->bt_info.force_to_roam = *pu8; + break; + + case BTC_SET_BL_TO_REJ_AP_AGG_PKT: + pBtCoexist->bt_info.reject_agg_pkt = *pu8; + break; + + case BTC_SET_BL_BT_CTRL_AGG_SIZE: + pBtCoexist->bt_info.bt_ctrl_agg_buf_size = *pu8; + break; + + case BTC_SET_BL_INC_SCAN_DEV_NUM: + pBtCoexist->bt_info.increase_scan_dev_num = *pu8; + break; + + case BTC_SET_BL_BT_TX_RX_MASK: + pBtCoexist->bt_info.bt_tx_rx_mask = *pu8; + break; + + case BTC_SET_BL_MIRACAST_PLUS_BT: + pBtCoexist->bt_info.miracast_plus_bt = *pu8; + break; + + /* set some u8 type variables. */ + case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON: + pBtCoexist->bt_info.rssi_adjust_for_agc_table_on = *pU1Tmp; + break; + + case BTC_SET_U1_AGG_BUF_SIZE: + pBtCoexist->bt_info.agg_buf_size = *pU1Tmp; + break; + + /* the following are some action which will be triggered */ + case BTC_SET_ACT_GET_BT_RSSI: + ret = _FALSE; + break; + + case BTC_SET_ACT_AGGREGATE_CTRL: + halbtcoutsrc_AggregationCheck(pBtCoexist); + break; + + /* =======1Ant=========== */ + /* set some u8 type variables. */ + case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE: + pBtCoexist->bt_info.rssi_adjust_for_1ant_coex_type = *pU1Tmp; + break; + + case BTC_SET_U1_LPS_VAL: + pBtCoexist->bt_info.lps_val = *pU1Tmp; + break; + + case BTC_SET_U1_RPWM_VAL: + pBtCoexist->bt_info.rpwm_val = *pU1Tmp; + break; + + /* the following are some action which will be triggered */ + case BTC_SET_ACT_LEAVE_LPS: + result = halbtcoutsrc_LeaveLps(pBtCoexist); + break; + + case BTC_SET_ACT_ENTER_LPS: + halbtcoutsrc_EnterLps(pBtCoexist); + break; + + case BTC_SET_ACT_NORMAL_LPS: + halbtcoutsrc_NormalLps(pBtCoexist); + break; + + case BTC_SET_ACT_DISABLE_LOW_POWER: + halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8); + break; + + case BTC_SET_ACT_UPDATE_RAMASK: + pBtCoexist->bt_info.ra_mask = *pU4Tmp; + + if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) { + struct sta_info *psta; + PWLAN_BSSID_EX cur_network; + + cur_network = &padapter->mlmeextpriv.mlmext_info.network; + psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress); + rtw_hal_update_ra_mask(psta, psta->rssi_level, _FALSE); + } + break; + + case BTC_SET_ACT_SEND_MIMO_PS: { + u8 newMimoPsMode = 3; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* *pU1Tmp = 0 use SM_PS static type */ + /* *pU1Tmp = 1 disable SM_PS */ + if (*pU1Tmp == 0) + newMimoPsMode = WLAN_HT_CAP_SM_PS_STATIC; + else if (*pU1Tmp == 1) + newMimoPsMode = WLAN_HT_CAP_SM_PS_DISABLED; + + if (check_fwstate(&padapter->mlmepriv , WIFI_ASOC_STATE) == _TRUE) { + /* issue_action_SM_PS(padapter, get_my_bssid(&(pmlmeinfo->network)), newMimoPsMode); */ + issue_action_SM_PS_wait_ack(padapter , get_my_bssid(&(pmlmeinfo->network)) , newMimoPsMode, 3 , 1); + } + } + break; + + case BTC_SET_ACT_CTRL_BT_INFO: + ret = _FALSE; + break; + + case BTC_SET_ACT_CTRL_BT_COEX: + ret = _FALSE; + break; + case BTC_SET_ACT_CTRL_8723B_ANT: + ret = _FALSE; + break; + /* ===================== */ + default: + ret = _FALSE; + break; + } + + return result; +} + +u8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + struct pwrctrl_priv *pwrpriv; + u8 bMacPwrCtrlOn; + + padapter = pBtCoexist->Adapter; + pwrpriv = &padapter->dvobj->pwrctl_priv; + bMacPwrCtrlOn = _FALSE; + + if ((_TRUE == pwrpriv->bips_processing) + && (IPS_NONE != pwrpriv->ips_mode_req) + ) + return _TRUE; + + if (rf_off == pwrpriv->rf_pwrstate) + return _TRUE; + + rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if (_FALSE == bMacPwrCtrlOn) + return _TRUE; + + return _FALSE; +} + +u8 halbtcoutsrc_UnderLps(PBTC_COEXIST pBtCoexist) +{ + return GLBtcWiFiInLPS; +} + +u8 halbtcoutsrc_Under32K(PBTC_COEXIST pBtCoexist) +{ + /* todo: the method to check whether wifi is under 32K or not */ + return _FALSE; +} + +void halbtcoutsrc_DisplayCoexStatistics(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter = pBtCoexist->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 *cliBuf = pBtCoexist->cli_buf; + + if (pHalData->EEPROMBluetoothCoexist == 1) { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Coex Status]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtDisabled", rtw_btcoex_IsBtDisabled(padapter)); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IsBtControlLps", rtw_btcoex_IsBtControlLps(padapter)); + CL_PRINTF(cliBuf); + } +} + +void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter = pBtCoexist->Adapter; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 *cliBuf = pBtCoexist->cli_buf; + s32 wifiRssi = 0, btHsRssi = 0; + BOOLEAN bScan = _FALSE, bLink = _FALSE, bRoam = _FALSE, bWifiBusy = _FALSE, bWifiUnderBMode = _FALSE; + u32 wifiBw = BTC_WIFI_BW_HT20, wifiTrafficDir = BTC_WIFI_TRAFFIC_TX, wifiFreq = BTC_FREQ_2_4G; + u32 wifiLinkStatus = 0x0; + BOOLEAN bBtHsOn = _FALSE, bLowPower = _FALSE; + u8 wifiChnl = 0, wifiP2PChnl = 0, nScanAPNum = 0, FwPSState; + u32 iqk_cnt_total = 0, iqk_cnt_ok = 0, iqk_cnt_fail = 0; + + wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc", \ + ((wifiLinkStatus & WIFI_STA_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_AP_CONNECTED) ? 1 : 0), + ((wifiLinkStatus & WIFI_HS_CONNECTED) ? 1 : 0), ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) ? 1 : 0), + ((wifiLinkStatus & WIFI_P2P_GC_CONNECTED) ? 1 : 0)); + CL_PRINTF(cliBuf); + + pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Link/ Roam/ Scan", \ + bLink, bRoam, bScan); + CL_PRINTF(cliBuf); + + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_TOTAL, &iqk_cnt_total); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_OK, &iqk_cnt_ok); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_IQK_FAIL, &iqk_cnt_fail); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d %s %s", + "IQK All/ OK/ Fail/AutoLoad/FWDL", iqk_cnt_total, iqk_cnt_ok, iqk_cnt_fail, + ((halbtcoutsrc_is_autoload_fail(pBtCoexist) == _TRUE) ? "fail":"ok"), ((halbtcoutsrc_is_fw_ready(pBtCoexist) == _TRUE) ? "ok":"fail")); + CL_PRINTF(cliBuf); + + if (wifiLinkStatus & WIFI_STA_CONNECTED) { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "IOT Peer", GLBtcIotPeerString[padapter->mlmeextpriv.mlmext_info.assoc_AP_vendor]); + CL_PRINTF(cliBuf); + } + + pBtCoexist->btc_get(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiChnl); + if ((wifiLinkStatus & WIFI_P2P_GO_CONNECTED) || (wifiLinkStatus & WIFI_P2P_GC_CONNECTED)) + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_WIFI_P2P_CHNL, &wifiP2PChnl); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dBm/ %d/ %d", "RSSI/ STA_Chnl/ P2P_Chnl", \ + wifiRssi -100, wifiChnl, wifiP2PChnl); + CL_PRINTF(cliBuf); + + pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifiFreq); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + pBtCoexist->btc_get(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ %d ", "Band/ BW/ Traffic/ APCnt", \ + GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode) ? "11b" : GLBtcWifiBwString[wifiBw]), + ((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")), + nScanAPNum); + CL_PRINTF(cliBuf); + + /* power status */ + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s%s%s", "Power Status", \ + ((halbtcoutsrc_UnderIps(pBtCoexist) == _TRUE) ? "IPS ON" : "IPS OFF"), + ((halbtcoutsrc_UnderLps(pBtCoexist) == _TRUE) ? ", LPS ON" : ", LPS OFF"), + ((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE) ? ", 32k" : "")); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)", \ + pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1], + pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3], + pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5], + pBtCoexist->bt_info.lps_val, + pBtCoexist->bt_info.rpwm_val); + CL_PRINTF(cliBuf); +} + +void halbtcoutsrc_DisplayDbgMsg(void *pBtcContext, u8 dispType) +{ + PBTC_COEXIST pBtCoexist; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + switch (dispType) { + case BTC_DBG_DISP_COEX_STATISTICS: + halbtcoutsrc_DisplayCoexStatistics(pBtCoexist); + break; + case BTC_DBG_DISP_WIFI_STATUS: + halbtcoutsrc_DisplayWifiStatus(pBtCoexist); + break; + default: + break; + } +} + +/* ************************************ + * IO related function + * ************************************ */ +u8 halbtcoutsrc_Read1Byte(void *pBtcContext, u32 RegAddr) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return rtw_read8(padapter, RegAddr); +} + +u16 halbtcoutsrc_Read2Byte(void *pBtcContext, u32 RegAddr) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return rtw_read16(padapter, RegAddr); +} + +u32 halbtcoutsrc_Read4Byte(void *pBtcContext, u32 RegAddr) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return rtw_read32(padapter, RegAddr); +} + +void halbtcoutsrc_Write1Byte(void *pBtcContext, u32 RegAddr, u8 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_write8(padapter, RegAddr, Data); +} + +void halbtcoutsrc_BitMaskWrite1Byte(void *pBtcContext, u32 regAddr, u8 bitMask, u8 data1b) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + u8 originalValue, bitShift; + u8 i; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + originalValue = 0; + bitShift = 0; + + if (bitMask != 0xff) { + originalValue = rtw_read8(padapter, regAddr); + + for (i = 0; i <= 7; i++) { + if ((bitMask >> i) & 0x1) + break; + } + bitShift = i; + + data1b = (originalValue & ~bitMask) | ((data1b << bitShift) & bitMask); + } + + rtw_write8(padapter, regAddr, data1b); +} + +void halbtcoutsrc_Write2Byte(void *pBtcContext, u32 RegAddr, u16 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_write16(padapter, RegAddr, Data); +} + +void halbtcoutsrc_Write4Byte(void *pBtcContext, u32 RegAddr, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_write32(padapter, RegAddr, Data); +} + +void halbtcoutsrc_WriteLocalReg1Byte(void *pBtcContext, u32 RegAddr, u8 Data) +{ + PBTC_COEXIST pBtCoexist = (PBTC_COEXIST)pBtcContext; + PADAPTER Adapter = pBtCoexist->Adapter; + + if (BTC_INTF_SDIO == pBtCoexist->chip_interface) + rtw_write8(Adapter, SDIO_LOCAL_BASE | RegAddr, Data); + else + rtw_write8(Adapter, RegAddr, Data); +} + +void halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + phy_set_bb_reg(padapter, RegAddr, BitMask, Data); +} + +u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return phy_query_bb_reg(padapter, RegAddr, BitMask); +} + +void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + phy_set_rf_reg(padapter, eRFPath, RegAddr, BitMask, Data); +} + +u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return phy_query_rf_reg(padapter, eRFPath, RegAddr, BitMask); +} + +u16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + u16 ret = BT_STATUS_BT_OP_SUCCESS; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + Data = cpu_to_le32(Data); + op_code = BT_OP_WRITE_REG_VALUE; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Data, 3); + if (status != BT_STATUS_BT_OP_SUCCESS) + ret = SET_BT_MP_OPER_RET(op_code, status); + else { + buf[0] = RegType; + *(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr); + op_code = BT_OP_WRITE_REG_ADDR; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3); + if (status != BT_STATUS_BT_OP_SUCCESS) + ret = SET_BT_MP_OPER_RET(op_code, status); + } + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return ret; +} + +u8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl) +{ + /* Always return _FALSE since we don't implement this yet */ + return _FALSE; +} + +BOOLEAN +halbtcoutsrc_SetBtTRXMASK( + IN PVOID pBtcContext, + IN u1Byte bt_trx_mask + ) +{ + return _FALSE; +} + +u16 halbtcoutsrc_GetBtReg_with_status(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data) +{ + PBTC_COEXIST pBtCoexist; + u16 ret = BT_STATUS_BT_OP_SUCCESS; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + buf[0] = RegType; + *(u16 *)(buf + 1) = cpu_to_le16((u16)RegAddr); + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_READ_REG; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3); + if (status == BT_STATUS_BT_OP_SUCCESS) + *data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return ret; +} + +u32 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr) +{ + u32 regVal; + + return (BT_STATUS_BT_OP_SUCCESS == halbtcoutsrc_GetBtReg_with_status(pBtcContext, RegType, RegAddr, ®Val)) ? regVal : 0xffffffff; +} + +void halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_hal_fill_h2c_cmd(padapter, elementId, cmdLen, pCmdBuffer); +} + +static void halbtcoutsrc_coex_offload_init(void) +{ + u1Byte i; + + gl_coex_offload.h2c_req_num = 0; + gl_coex_offload.cnt_h2c_sent = 0; + gl_coex_offload.cnt_c2h_ack = 0; + gl_coex_offload.cnt_c2h_ind = 0; + + for (i = 0; i < COL_MAX_H2C_REQ_NUM; i++) + init_completion(&gl_coex_offload.c2h_event[i]); +} + +static COL_H2C_STATUS halbtcoutsrc_send_h2c(PADAPTER Adapter, PCOL_H2C pcol_h2c, u16 h2c_cmd_len) +{ + COL_H2C_STATUS h2c_status = COL_STATUS_C2H_OK; + u8 i; + + reinit_completion(&gl_coex_offload.c2h_event[pcol_h2c->req_num]); /* set event to un signaled state */ + + return h2c_status; +} + +static COL_H2C_STATUS halbtcoutsrc_check_c2h_ack(PADAPTER Adapter, PCOL_SINGLE_H2C_RECORD pH2cRecord) +{ + COL_H2C_STATUS c2h_status = COL_STATUS_C2H_OK; + PCOL_H2C p_h2c_cmd = (PCOL_H2C)&pH2cRecord->h2c_buf[0]; + u8 req_num = p_h2c_cmd->req_num; + PCOL_C2H_ACK p_c2h_ack = (PCOL_C2H_ACK)&gl_coex_offload.c2h_ack_buf[req_num]; + + if ((COL_C2H_ACK_HDR_LEN + p_c2h_ack->ret_len) > gl_coex_offload.c2h_ack_len[req_num]) { + c2h_status = COL_STATUS_COEX_DATA_OVERFLOW; + return c2h_status; + } + /* else */ + { + _rtw_memmove(&pH2cRecord->c2h_ack_buf[0], &gl_coex_offload.c2h_ack_buf[req_num], gl_coex_offload.c2h_ack_len[req_num]); + pH2cRecord->c2h_ack_len = gl_coex_offload.c2h_ack_len[req_num]; + } + + if (p_c2h_ack->req_num != p_h2c_cmd->req_num) { + c2h_status = COL_STATUS_C2H_REQ_NUM_MISMATCH; + } else if (p_c2h_ack->opcode_ver != p_h2c_cmd->opcode_ver) { + c2h_status = COL_STATUS_C2H_OPCODE_VER_MISMATCH; + } else { + c2h_status = p_c2h_ack->status; + } + + return c2h_status; +} + +COL_H2C_STATUS halbtcoutsrc_CoexH2cProcess(void *pBtCoexist, + u8 opcode, u8 opcode_ver, u8 *ph2c_par, u8 h2c_par_len) +{ + PADAPTER Adapter = ((struct btc_coexist *)pBtCoexist)->Adapter; + u8 H2C_Parameter[BTC_TMP_BUF_SHORT] = {0}; + PCOL_H2C pcol_h2c = (PCOL_H2C)&H2C_Parameter[0]; + u16 paraLen = 0; + COL_H2C_STATUS h2c_status = COL_STATUS_C2H_OK, c2h_status = COL_STATUS_C2H_OK; + COL_H2C_STATUS ret_status = COL_STATUS_C2H_OK; + u16 i, col_h2c_len = 0; + + pcol_h2c->opcode = opcode; + pcol_h2c->opcode_ver = opcode_ver; + pcol_h2c->req_num = gl_coex_offload.h2c_req_num; + gl_coex_offload.h2c_req_num++; + gl_coex_offload.h2c_req_num %= 16; + + _rtw_memmove(&pcol_h2c->buf[0], ph2c_par, h2c_par_len); + + col_h2c_len = h2c_par_len + 2; /* 2=sizeof(OPCode, OPCode_version and Request number) */ + BT_PrintData(Adapter, "[COL], H2C cmd: ", col_h2c_len, H2C_Parameter); + + gl_coex_offload.cnt_h2c_sent++; + + gl_coex_offload.h2c_record[opcode].count++; + gl_coex_offload.h2c_record[opcode].h2c_len = col_h2c_len; + _rtw_memmove((PVOID)&gl_coex_offload.h2c_record[opcode].h2c_buf[0], (PVOID)pcol_h2c, col_h2c_len); + + h2c_status = halbtcoutsrc_send_h2c(Adapter, pcol_h2c, col_h2c_len); + + gl_coex_offload.h2c_record[opcode].c2h_ack_len = 0; + + if (COL_STATUS_C2H_OK == h2c_status) { + /* if reach here, it means H2C get the correct c2h response, */ + c2h_status = halbtcoutsrc_check_c2h_ack(Adapter, &gl_coex_offload.h2c_record[opcode]); + ret_status = c2h_status; + } else { + /* check h2c status error, return error status code to upper layer. */ + ret_status = h2c_status; + } + gl_coex_offload.h2c_record[opcode].status[ret_status]++; + gl_coex_offload.status[ret_status]++; + + return ret_status; +} + +u8 halbtcoutsrc_GetAntDetValFromBt(void *pBtcContext) +{ + /* Always return 0 since we don't implement this yet */ + return 0; +} + +u8 halbtcoutsrc_GetBleScanTypeFromBt(void *pBtcContext) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u8 data = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_BLE_SCAN_TYPE; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = *(u8 *)GLBtcBtMpRptRsp; + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; +} + +u32 halbtcoutsrc_GetBleScanParaFromBt(void *pBtcContext, u8 scanType) +{ + PBTC_COEXIST pBtCoexist; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + u32 data = 0; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_GET_BT_BLE_SCAN_PARA; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + data = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return data; +} + +u8 halbtcoutsrc_GetBtAFHMapFromBt(void *pBtcContext, u8 mapType, u8 *afhMap) +{ + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + u8 buf[2] = {0}; + _irqL irqL; + u8 op_code; + u32 *AfhMapL = (u32 *)&(afhMap[0]); + u32 *AfhMapM = (u32 *)&(afhMap[4]); + u16 *AfhMapH = (u16 *)&(afhMap[8]); + u8 status; + u32 ret = BT_STATUS_BT_OP_SUCCESS; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _FALSE) + return _FALSE; + + buf[0] = 0; + buf[1] = mapType; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_LO_OP_GET_AFH_MAP_L; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + *AfhMapL = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else { + ret = SET_BT_MP_OPER_RET(op_code, status); + goto exit; + } + + op_code = BT_LO_OP_GET_AFH_MAP_M; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + *AfhMapM = le32_to_cpu(*(u32 *)GLBtcBtMpRptRsp); + else { + ret = SET_BT_MP_OPER_RET(op_code, status); + goto exit; + } + + op_code = BT_LO_OP_GET_AFH_MAP_H; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 0); + if (status == BT_STATUS_BT_OP_SUCCESS) + *AfhMapH = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else { + ret = SET_BT_MP_OPER_RET(op_code, status); + goto exit; + } + +exit: + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + return (ret == BT_STATUS_BT_OP_SUCCESS) ? _TRUE : _FALSE; +} + +u32 halbtcoutsrc_GetPhydmVersion(void *pBtcContext) +{ + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + PADAPTER Adapter = pBtCoexist->Adapter; + + return RELEASE_VERSION_8821C; +} + +void halbtcoutsrc_phydm_modify_RA_PCR_threshold(void *pBtcContext, u8 RA_offset_direction, u8 RA_threshold_offset) +{ + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + +/* switch to #if 0 in case the phydm version does not provide the function */ + phydm_modify_RA_PCR_threshold(pBtCoexist->odm_priv, RA_offset_direction, RA_threshold_offset); +} + +u32 halbtcoutsrc_phydm_query_PHY_counter(void *pBtcContext, u8 info_type) +{ + struct btc_coexist *pBtCoexist = (struct btc_coexist *)pBtcContext; + +/* switch to #if 0 in case the phydm version does not provide the function */ + return phydm_cmn_info_query((struct PHY_DM_STRUCT *)pBtCoexist->odm_priv, (enum phydm_info_query_e)info_type); +} + +/* ************************************ + * Extern functions called by other module + * ************************************ */ +u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + u8 antNum = 1, chipType = 0, singleAntPath = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA((PADAPTER)padapter); + + if (pBtCoexist->bBinded) + return _FALSE; + else + pBtCoexist->bBinded = _TRUE; + + pBtCoexist->statistics.cnt_bind++; + + pBtCoexist->Adapter = padapter; + pBtCoexist->odm_priv = (PVOID)&(pHalData->odmpriv); + + pBtCoexist->stack_info.profile_notified = _FALSE; + + pBtCoexist->bt_info.bt_ctrl_agg_buf_size = _FALSE; + pBtCoexist->bt_info.agg_buf_size = 5; + + pBtCoexist->bt_info.increase_scan_dev_num = _FALSE; + pBtCoexist->bt_info.miracast_plus_bt = _FALSE; + + antNum = rtw_btcoex_get_pg_ant_num((PADAPTER)padapter); + EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum); + + if (antNum == 1) { + singleAntPath = rtw_btcoex_get_pg_single_ant_path((PADAPTER)padapter); + EXhalbtcoutsrc_SetSingleAntPath(singleAntPath); + } + + /* set default antenna position to main port */ + pBtCoexist->board_info.btdm_ant_pos = BTC_ANTENNA_AT_MAIN_PORT; + + pBtCoexist->board_info.btdm_ant_det_finish = _FALSE; + pBtCoexist->board_info.btdm_ant_num_by_ant_det = 1; + + pBtCoexist->board_info.tfbga_package = rtw_btcoex_is_tfbga_package_type((PADAPTER)padapter); + + pBtCoexist->board_info.rfe_type = rtw_btcoex_get_pg_rfe_type((PADAPTER)padapter); + + pBtCoexist->board_info.ant_div_cfg = rtw_btcoex_get_ant_div_cfg((PADAPTER)padapter); + + return _TRUE; +} + +u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + /* pBtCoexist->statistics.cntBind++; */ + + halbtcoutsrc_DbgInit(); + + halbtcoutsrc_coex_offload_init(); + + pBtCoexist->chip_interface = BTC_INTF_PCI; + + EXhalbtcoutsrc_BindBtCoexWithAdapter(padapter); + + pBtCoexist->btc_read_1byte = halbtcoutsrc_Read1Byte; + pBtCoexist->btc_write_1byte = halbtcoutsrc_Write1Byte; + pBtCoexist->btc_write_1byte_bitmask = halbtcoutsrc_BitMaskWrite1Byte; + pBtCoexist->btc_read_2byte = halbtcoutsrc_Read2Byte; + pBtCoexist->btc_write_2byte = halbtcoutsrc_Write2Byte; + pBtCoexist->btc_read_4byte = halbtcoutsrc_Read4Byte; + pBtCoexist->btc_write_4byte = halbtcoutsrc_Write4Byte; + pBtCoexist->btc_write_local_reg_1byte = halbtcoutsrc_WriteLocalReg1Byte; + + pBtCoexist->btc_set_bb_reg = halbtcoutsrc_SetBbReg; + pBtCoexist->btc_get_bb_reg = halbtcoutsrc_GetBbReg; + + pBtCoexist->btc_set_rf_reg = halbtcoutsrc_SetRfReg; + pBtCoexist->btc_get_rf_reg = halbtcoutsrc_GetRfReg; + + pBtCoexist->btc_fill_h2c = halbtcoutsrc_FillH2cCmd; + pBtCoexist->btc_disp_dbg_msg = halbtcoutsrc_DisplayDbgMsg; + + pBtCoexist->btc_get = halbtcoutsrc_Get; + pBtCoexist->btc_set = halbtcoutsrc_Set; + pBtCoexist->btc_get_bt_reg = halbtcoutsrc_GetBtReg; + pBtCoexist->btc_set_bt_reg = halbtcoutsrc_SetBtReg; + pBtCoexist->btc_set_bt_ant_detection = halbtcoutsrc_SetBtAntDetection; + pBtCoexist->btc_set_bt_trx_mask = halbtcoutsrc_SetBtTRXMASK; + pBtCoexist->btc_coex_h2c_process = halbtcoutsrc_CoexH2cProcess; + pBtCoexist->btc_get_bt_coex_supported_feature = halbtcoutsrc_GetBtCoexSupportedFeature; + pBtCoexist->btc_get_bt_coex_supported_version= halbtcoutsrc_GetBtCoexSupportedVersion; + pBtCoexist->btc_get_ant_det_val_from_bt = halbtcoutsrc_GetAntDetValFromBt; + pBtCoexist->btc_get_ble_scan_type_from_bt = halbtcoutsrc_GetBleScanTypeFromBt; + pBtCoexist->btc_get_ble_scan_para_from_bt = halbtcoutsrc_GetBleScanParaFromBt; + pBtCoexist->btc_get_bt_afh_map_from_bt = halbtcoutsrc_GetBtAFHMapFromBt; + pBtCoexist->btc_get_bt_phydm_version = halbtcoutsrc_GetPhydmVersion; + pBtCoexist->btc_phydm_modify_RA_PCR_threshold = halbtcoutsrc_phydm_modify_RA_PCR_threshold; + pBtCoexist->btc_phydm_query_PHY_counter = halbtcoutsrc_phydm_query_PHY_counter; + + pBtCoexist->cli_buf = &GLBtcDbgBuf[0]; + + GLBtcWiFiInScanState = _FALSE; + + GLBtcWiFiInIQKState = _FALSE; + + GLBtcWiFiInIPS = _FALSE; + + GLBtcWiFiInLPS = _FALSE; + + GLBtcBtCoexAliveRegistered = _FALSE; + + /* BT Control H2C/C2H*/ + GLBtcBtMpOperSeq = 0; + _rtw_mutex_init(&GLBtcBtMpOperLock); + rtw_init_timer(&GLBtcBtMpOperTimer, padapter, _btmpoper_timer_hdl, pBtCoexist); + _rtw_init_sema(&GLBtcBtMpRptSema, 0); + GLBtcBtMpRptSeq = 0; + GLBtcBtMpRptStatus = 0; + _rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE); + GLBtcBtMpRptRspSize = 0; + GLBtcBtMpRptWait = 0; + GLBtcBtMpRptWiFiOK = 0; + GLBtcBtMpRptBTOK = 0; + + return _TRUE; +} + +void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist) +{ + HAL_DATA_TYPE *pHalData = NULL; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pHalData = GET_HAL_DATA((PADAPTER)pBtCoexist->Adapter); + + /* Power on setting function is only added in 8723B currently */ + if ((pHalData->EEPROMBluetoothCoexist == _TRUE)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_power_on_setting(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_power_on_setting(pBtCoexist); + } +} + +void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_pre_load_firmware++; + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_pre_load_firmware(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_pre_load_firmware(pBtCoexist); +} + +void EXhalbtcoutsrc_init_hw_config(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_init_hw_config++; + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_init_hw_config(pBtCoexist, bWifiOnly); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_init_hw_config(pBtCoexist, bWifiOnly); +} + +void EXhalbtcoutsrc_init_coex_dm(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_init_coex_dm++; + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_init_coex_dm(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_init_coex_dm(pBtCoexist); + + pBtCoexist->initilized = _TRUE; +} + +void EXhalbtcoutsrc_ips_notify(PBTC_COEXIST pBtCoexist, u8 type) +{ + u8 ipsType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_ips_notify++; + if (pBtCoexist->manual_control) + return; + + if (IPS_NONE == type) { + ipsType = BTC_IPS_LEAVE; + GLBtcWiFiInIPS = _FALSE; + } else { + ipsType = BTC_IPS_ENTER; + GLBtcWiFiInIPS = _TRUE; + } + + /* All notify is called in cmd thread, don't need to leave low power again + * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_ips_notify(pBtCoexist, ipsType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_ips_notify(pBtCoexist, ipsType); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +void EXhalbtcoutsrc_lps_notify(PBTC_COEXIST pBtCoexist, u8 type) +{ + u8 lpsType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_lps_notify++; + if (pBtCoexist->manual_control) + return; + + if (PS_MODE_ACTIVE == type) { + lpsType = BTC_LPS_DISABLE; + GLBtcWiFiInLPS = _FALSE; + } else { + lpsType = BTC_LPS_ENABLE; + GLBtcWiFiInLPS = _TRUE; + } + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_lps_notify(pBtCoexist, lpsType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_lps_notify(pBtCoexist, lpsType); +} + +void EXhalbtcoutsrc_scan_notify(PBTC_COEXIST pBtCoexist, u8 type) +{ + u8 scanType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cnt_scan_notify++; + if (pBtCoexist->manual_control) + return; + + if (type) { + scanType = BTC_SCAN_START; + GLBtcWiFiInScanState = _TRUE; + } else { + scanType = BTC_SCAN_FINISH; + GLBtcWiFiInScanState = _FALSE; + } + + /* All notify is called in cmd thread, don't need to leave low power again + * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_scan_notify(pBtCoexist, scanType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_scan_notify(pBtCoexist, scanType); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +void EXhalbtcoutsrc_connect_notify(PBTC_COEXIST pBtCoexist, u8 action) +{ + u8 assoType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cnt_connect_notify++; + if (pBtCoexist->manual_control) + return; + + if (action) + assoType = BTC_ASSOCIATE_START; + else + assoType = BTC_ASSOCIATE_FINISH; + + /* All notify is called in cmd thread, don't need to leave low power again + * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_connect_notify(pBtCoexist, assoType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_connect_notify(pBtCoexist, assoType); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +void EXhalbtcoutsrc_media_status_notify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus) +{ + u8 mStatus; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_media_status_notify++; + if (pBtCoexist->manual_control) + return; + + if (RT_MEDIA_CONNECT == mediaStatus) + mStatus = BTC_MEDIA_CONNECT; + else + mStatus = BTC_MEDIA_DISCONNECT; + + /* All notify is called in cmd thread, don't need to leave low power again + * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_media_status_notify(pBtCoexist, mStatus); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_media_status_notify(pBtCoexist, mStatus); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +void EXhalbtcoutsrc_specific_packet_notify(PBTC_COEXIST pBtCoexist, u8 pktType) +{ + u8 packetType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cnt_specific_packet_notify++; + if (pBtCoexist->manual_control) + return; + + if (PACKET_DHCP == pktType) + packetType = BTC_PACKET_DHCP; + else if (PACKET_EAPOL == pktType) + packetType = BTC_PACKET_EAPOL; + else if (PACKET_ARP == pktType) + packetType = BTC_PACKET_ARP; + else { + packetType = BTC_PACKET_UNKNOWN; + return; + } + + /* All notify is called in cmd thread, don't need to leave low power again + * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_specific_packet_notify(pBtCoexist, packetType); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_specific_packet_notify(pBtCoexist, packetType); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +void EXhalbtcoutsrc_bt_info_notify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cnt_bt_info_notify++; + + /* All notify is called in cmd thread, don't need to leave low power again + * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_bt_info_notify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_bt_info_notify(pBtCoexist, tmpBuf, length); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +void EXhalbtcoutsrc_halt_notify(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_halt_notify(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_halt_notify(pBtCoexist); +} + +void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist) +{ + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) { + if (pBtCoexist->board_info.btdm_ant_num == 2) { + halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x01); /* BT goto standby while GNT_BT 1-->0 */ + } else if (pBtCoexist->board_info.btdm_ant_num == 1) { + halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x15); /* BT goto standby while GNT_BT 1-->0 */ + } + } +} + +void EXhalbtcoutsrc_pnp_notify(PBTC_COEXIST pBtCoexist, u8 pnpState) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + /* */ + /* currently only 1ant we have to do the notification, */ + /* once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. */ + /* */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_pnp_notify(pBtCoexist, pnpState); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_pnp_notify(pBtCoexist, pnpState); +} + +void EXhalbtcoutsrc_periodical(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cnt_periodical++; + + /* Periodical should be called in cmd thread, */ + /* don't need to leave low power again + * halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_periodical(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_periodical(pBtCoexist); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +void EXhalbtcoutsrc_StackUpdateProfileInfo(void) +{ +} + +void EXhalbtcoutsrc_SetHciVersion(u16 hciVersion) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->stack_info.hci_version = hciVersion; +} + +void EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->bt_info.bt_real_fw_ver = btPatchVersion; + pBtCoexist->bt_info.bt_hci_ver = btHciVersion; +} + +void EXhalbtcoutsrc_SetAntNum(u8 type, u8 antNum) +{ + if (BT_COEX_ANT_TYPE_PG == type) { + GLBtCoexist.board_info.pg_ant_num = antNum; + GLBtCoexist.board_info.btdm_ant_num = antNum; + } else if (BT_COEX_ANT_TYPE_ANTDIV == type) { + GLBtCoexist.board_info.btdm_ant_num = antNum; + /* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; */ + } else if (BT_COEX_ANT_TYPE_DETECTED == type) { + GLBtCoexist.board_info.btdm_ant_num = antNum; + /* GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; */ + } +} + +/* + * Currently used by 8723b only, S0 or S1 + * */ +void EXhalbtcoutsrc_SetSingleAntPath(u8 singleAntPath) +{ + GLBtCoexist.board_info.single_ant_path = singleAntPath; +} + +void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + halbtcoutsrc_LeaveLowPower(pBtCoexist); + + /* To prevent the racing with IPS enter */ + halbtcoutsrc_EnterPwrLock(pBtCoexist); + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_display_coex_info(pBtCoexist); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_display_coex_info(pBtCoexist); + + halbtcoutsrc_ExitPwrLock(pBtCoexist); + + halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void ex_halbtcoutsrc_pta_off_on_notify(PBTC_COEXIST pBtCoexist, u8 bBTON) +{ +} + +void EXhalbtcoutsrc_set_rfe_type(u8 type) +{ + GLBtCoexist.board_info.rfe_type= type; +} + +void EXhalbtcoutsrc_switchband_notify(struct btc_coexist *pBtCoexist, u8 type) +{ + if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + if(pBtCoexist->manual_control) + return; + + /* Driver should guarantee that the HW status isn't in low power mode */ + /* halbtcoutsrc_LeaveLowPower(pBtCoexist); */ + + if (pBtCoexist->board_info.btdm_ant_num == 2) + ex_halbtc8821c2ant_switchband_notify(pBtCoexist, type); + else if (pBtCoexist->board_info.btdm_ant_num == 1) + ex_halbtc8821c1ant_switchband_notify(pBtCoexist, type); + + /* halbtcoutsrc_NormalLowPower(pBtCoexist); */ +} + +/* + * Description: + * Run BT-Coexist mechansim or not + * + */ +void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + pHalData->bt_coexist.bBtExist = bBtExist; +} + +/* + * Dewcription: + * Check is co-exist mechanism enabled or not + * + * Return: + * _TRUE Enable BT co-exist mechanism + * _FALSE Disable BT co-exist mechanism + */ +u8 hal_btcoex_IsBtExist(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + return pHalData->bt_coexist.bBtExist; +} + +u8 hal_btcoex_IsBtDisabled(PADAPTER padapter) +{ + if (!hal_btcoex_IsBtExist(padapter)) + return _TRUE; + + if (GLBtCoexist.bt_info.bt_disabled) + return _TRUE; + else + return _FALSE; +} + +void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + pHalData->bt_coexist.btChipType = chipType; +} + +void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + + pHalData->bt_coexist.btTotalAntNum = antNum; +} + +u8 hal_btcoex_Initialize(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 ret; + + _rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist)); + + hal_btcoex_SetBTCoexist(padapter, rtw_btcoex_get_bt_coexist(padapter)); + hal_btcoex_SetChipType(padapter, rtw_btcoex_get_chip_type(padapter)); + hal_btcoex_SetPgAntNum(padapter, rtw_btcoex_get_pg_ant_num(padapter)); + + ret = EXhalbtcoutsrc_InitlizeVariables((void *)padapter); + + return ret; +} + +void hal_btcoex_PowerOnSetting(PADAPTER padapter) +{ + EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist); +} + +void hal_btcoex_PowerOffSetting(PADAPTER padapter) +{ + /* Clear the WiFi on/off bit in scoreboard reg. if necessary */ + rtw_write16(padapter, 0xaa, 0x8000); +} + +void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly) +{ + if (!hal_btcoex_IsBtExist(padapter)) + return; + + EXhalbtcoutsrc_init_hw_config(&GLBtCoexist, bWifiOnly); + EXhalbtcoutsrc_init_coex_dm(&GLBtCoexist); +} + +void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type) +{ + EXhalbtcoutsrc_ips_notify(&GLBtCoexist, type); +} + +void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type) +{ + EXhalbtcoutsrc_lps_notify(&GLBtCoexist, type); +} + +void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type) +{ + EXhalbtcoutsrc_scan_notify(&GLBtCoexist, type); +} + +void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action) +{ + EXhalbtcoutsrc_connect_notify(&GLBtCoexist, action); +} + +void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus) +{ + EXhalbtcoutsrc_media_status_notify(&GLBtCoexist, mediaStatus); +} + +void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType) +{ + EXhalbtcoutsrc_specific_packet_notify(&GLBtCoexist, pktType); +} + +void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + if (GLBtcWiFiInIQKState == _TRUE) + return; + + EXhalbtcoutsrc_bt_info_notify(&GLBtCoexist, tmpBuf, length); +} + +void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + u8 extid, status, len, seq; + + if (!GLBtcBtMpRptWait) + return; + + if ((length < 3) || (!tmpBuf)) + return; + + extid = tmpBuf[0]; + /* not response from BT FW then exit*/ + switch (extid) { + case C2H_WIFI_FW_ACTIVE_RSP: + GLBtcBtMpRptWiFiOK = 1; + return; + + case C2H_TRIG_BY_BT_FW: + _cancel_timer_ex(&GLBtcBtMpOperTimer); + GLBtcBtMpRptWait = 0; + GLBtcBtMpRptBTOK = 1; + break; + + default: + return; + } + + status = tmpBuf[1] & 0xF; + len = length - 3; + seq = tmpBuf[2] >> 4; + + GLBtcBtMpRptSeq = seq; + GLBtcBtMpRptStatus = status; + _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf + 3, len); + GLBtcBtMpRptRspSize = len; + _rtw_up_sema(&GLBtcBtMpRptSema); +} + +void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state) +{ + switch (state) { + case BTCOEX_SUSPEND_STATE_SUSPEND: + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP); + break; + case BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT: + /* should switch to "#if 1" once all ICs' coex. revision are upgraded to support the KEEP_ANT case */ + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP); + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_SLEEP_KEEP_ANT); + break; + case BTCOEX_SUSPEND_STATE_RESUME: + EXhalbtcoutsrc_pnp_notify(&GLBtCoexist, BTC_WIFI_PNP_WAKE_UP); + break; + } +} + +void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt) +{ + if (do_halt == 1) + EXhalbtcoutsrc_halt_notify(&GLBtCoexist); + + GLBtCoexist.bBinded = _FALSE; + GLBtCoexist.Adapter = NULL; +} + +void hal_btcoex_Hanlder(PADAPTER padapter) +{ + u32 bt_patch_ver; + + EXhalbtcoutsrc_periodical(&GLBtCoexist); + + if (GLBtCoexist.bt_info.bt_get_fw_ver == 0) { + GLBtCoexist.btc_get(&GLBtCoexist, BTC_GET_U4_BT_PATCH_VER, &bt_patch_ver); + GLBtCoexist.bt_info.bt_get_fw_ver = bt_patch_ver; + } +} + +s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter) +{ + return (s32)GLBtCoexist.bt_info.reject_agg_pkt; +} + +s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter) +{ + return (s32)GLBtCoexist.bt_info.bt_ctrl_agg_buf_size; +} + +u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter) +{ + return (u32)GLBtCoexist.bt_info.agg_buf_size; +} + +void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual) +{ + GLBtCoexist.manual_control = bmanual; +} + +u8 hal_btcoex_IsBtControlLps(PADAPTER padapter) +{ + if (GLBtCoexist.bdontenterLPS == _TRUE) + return _TRUE; + + if (hal_btcoex_IsBtExist(padapter) == _FALSE) + return _FALSE; + + if (GLBtCoexist.bt_info.bt_disabled) + return _FALSE; + + if (GLBtCoexist.bt_info.bt_ctrl_lps) + return _TRUE; + + return _FALSE; +} + +u8 hal_btcoex_IsLpsOn(PADAPTER padapter) +{ + if (GLBtCoexist.bdontenterLPS == _TRUE) + return _FALSE; + + if (hal_btcoex_IsBtExist(padapter) == _FALSE) + return _FALSE; + + if (GLBtCoexist.bt_info.bt_disabled) + return _FALSE; + + if (GLBtCoexist.bt_info.bt_lps_on) + return _TRUE; + + return _FALSE; +} + +u8 hal_btcoex_RpwmVal(PADAPTER padapter) +{ + return GLBtCoexist.bt_info.rpwm_val; +} + +u8 hal_btcoex_LpsVal(PADAPTER padapter) +{ + return GLBtCoexist.bt_info.lps_val; +} + +u32 hal_btcoex_GetRaMask(PADAPTER padapter) +{ + if (!hal_btcoex_IsBtExist(padapter)) + return 0; + + if (GLBtCoexist.bt_info.bt_disabled) + return 0; + + /* Modify by YiWei , suggest by Cosa and Jenyu + * Remove the limit antenna number , because 2 antenna case (ex: 8192eu)also want to get BT coex report rate mask. + */ + /*if (GLBtCoexist.board_info.btdm_ant_num != 1) + return 0;*/ + + return GLBtCoexist.bt_info.ra_mask; +} + +void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen) +{ + + _rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen); +} + +void hal_btcoex_SetBtPatchVersion(PADAPTER padapter, u16 btHciVer, u16 btPatchVer) +{ + EXhalbtcoutsrc_SetBtPatchVersion(btHciVer, btPatchVer); +} + +/* + * Description: + * Setting BT coex antenna isolation type . + * coex mechanisn/ spital stream/ best throughput + * anttype = 0 , PSTDMA / 2SS / 0.5T , bad isolation , WiFi/BT ANT Distance<15cm , (<20dB) for 2,3 antenna + * anttype = 1 , PSTDMA / 1SS / 0.5T , normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 2 antenna + * anttype = 2 , TDMA / 2SS / T , normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 3 antenna + * anttype = 3 , no TDMA / 1SS / 0.5T , good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 2 antenna + * anttype = 4 , no TDMA / 2SS / T , good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 3 antenna + * wifi only throughput ~ T + * wifi/BT share one antenna with SPDT + */ +void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype) +{ + PHAL_DATA_TYPE pHalData; + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + /*RTW_INFO("####%s , anttype = %d , %d\n" , __func__ , anttype , __LINE__); */ + pHalData = GET_HAL_DATA(padapter); + + pHalData->bt_coexist.btAntisolation = anttype; + + switch (pHalData->bt_coexist.btAntisolation) { + case 0: + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_0; + break; + case 1: + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_1; + break; + case 2: + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_2; + break; + case 3: + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_3; + break; + case 4: + pBtCoexist->board_info.ant_type = (u1Byte)BTC_ANT_TYPE_4; + break; + } + +} + +int +hal_btcoex_ParseAntIsolationConfigFile( + PADAPTER Adapter, + char *buffer +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u32 i = 0 , j = 0; + char *szLine , *ptmp; + int rtStatus = _SUCCESS; + char param_value_string[10]; + u8 param_value; + u8 anttype = 4; + + u8 ant_num = 3 , ant_distance = 50 , rfe_type = 1; + + typedef struct ant_isolation { + char *param_name; /* antenna isolation config parameter name */ + u8 *value; /* antenna isolation config parameter value */ + } ANT_ISOLATION; + + ANT_ISOLATION ant_isolation_param[] = { + {"ANT_NUMBER" , &ant_num}, + {"ANT_DISTANCE" , &ant_distance}, + {"RFE_TYPE" , &rfe_type}, + {NULL , 0} + }; + + /* RTW_INFO("===>Hal_ParseAntIsolationConfigFile()\n" ); */ + + ptmp = buffer; + for (szLine = GetLineFromBuffer(ptmp) ; szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + /* skip comment */ + if (IsCommentString(szLine)) + continue; + + /* RTW_INFO("%s : szLine = %s , strlen(szLine) = %d\n" , __func__ , szLine , strlen(szLine));*/ + for (j = 0 ; ant_isolation_param[j].param_name != NULL ; j++) { + if (strstr(szLine , ant_isolation_param[j].param_name) != NULL) { + i = 0; + while (i < strlen(szLine)) { + if (szLine[i] != '"') + ++i; + else { + /* skip only has one " */ + if (strpbrk(szLine , "\"") == strrchr(szLine , '"')) { + RTW_INFO("Fail to parse parameters , format error!\n"); + break; + } + _rtw_memset((PVOID)param_value_string , 0 , 10); + if (!ParseQualifiedString(szLine , &i , param_value_string , '"' , '"')) { + RTW_INFO("Fail to parse parameters\n"); + return _FAIL; + } else if (!GetU1ByteIntegerFromStringInDecimal(param_value_string , ant_isolation_param[j].value)) + RTW_INFO("Fail to GetU1ByteIntegerFromStringInDecimal\n"); + + break; + } + } + } + } + } + + /* YiWei 20140716 , for BT coex antenna isolation control */ + /* rfe_type = 0 was SPDT , rfe_type = 1 was coupler */ + if (ant_num == 3 && ant_distance >= 50) + anttype = 3; + else if (ant_num == 2 && ant_distance >= 50 && rfe_type == 1) + anttype = 2; + else if (ant_num == 3 && ant_distance >= 15 && ant_distance < 50) + anttype = 2; + else if (ant_num == 2 && ant_distance >= 15 && ant_distance < 50 && rfe_type == 1) + anttype = 2; + else if ((ant_num == 2 && ant_distance < 15 && rfe_type == 1) || (ant_num == 3 && ant_distance < 15)) + anttype = 1; + else if (ant_num == 2 && rfe_type == 0) + anttype = 0; + else + anttype = 0; + + hal_btcoex_SetAntIsolationType(Adapter, anttype); + + RTW_INFO("%s : ant_num = %d\n" , __func__ , ant_num); + RTW_INFO("%s : ant_distance = %d\n" , __func__ , ant_distance); + RTW_INFO("%s : rfe_type = %d\n" , __func__ , rfe_type); + /* RTW_INFO("<===Hal_ParseAntIsolationConfigFile()\n"); */ + return rtStatus; +} + +void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type) +{ + switch (band_type) { + case BAND_ON_2_4G: + if (under_scan) + EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G); + else + EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_24G_NOFORSCAN); + break; + case BAND_ON_5G: + EXhalbtcoutsrc_switchband_notify(&GLBtCoexist, BTC_SWITCH_TO_5G); + break; + default: + RTW_INFO("[BTCOEX] unkown switch band type\n"); + break; + } +} diff --git a/drivers/staging/rtl8821ce/hal/hal_btcoex_wifionly.c b/drivers/staging/rtl8821ce/hal/hal_btcoex_wifionly.c new file mode 100644 index 000000000000..9ca13316d6d6 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_btcoex_wifionly.c @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "btc/mp_precomp.h" +#include <hal_btcoex_wifionly.h> + +struct wifi_only_cfg GLBtCoexistWifiOnly; + +void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + rtw_write8(Adapter, RegAddr, Data); +} + +void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data) +{ + struct wifi_only_cfg *pwifionlycfg = (struct wifi_only_cfg *)pwifionlyContext; + PADAPTER Adapter = pwifionlycfg->Adapter; + + phy_set_bb_reg(Adapter, RegAddr, BitMask, Data); +} + +void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 is_5g = _FALSE; + + if (pHalData->current_band_type == BAND_ON_5G) + is_5g = _TRUE; + + ex_hal8821c_wifi_only_switchbandnotify(&GLBtCoexistWifiOnly, is_5g); +} + +void hal_btcoex_wifionly_scan_notify(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 is_5g = _FALSE; + + if (pHalData->current_band_type == BAND_ON_5G) + is_5g = _TRUE; + + ex_hal8821c_wifi_only_scannotify(&GLBtCoexistWifiOnly, is_5g); +} + +void hal_btcoex_wifionly_hw_config(PADAPTER padapter) +{ + struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; + + ex_hal8821c_wifi_only_hw_config(pwifionlycfg); +} + +void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter) +{ + struct wifi_only_cfg *pwifionlycfg = &GLBtCoexistWifiOnly; + struct wifi_only_haldata *pwifionly_haldata = &pwifionlycfg->haldata_info; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + _rtw_memset(&GLBtCoexistWifiOnly, 0, sizeof(GLBtCoexistWifiOnly)); + + pwifionlycfg->Adapter = padapter; + + pwifionlycfg->chip_interface = WIFIONLY_INTF_PCI; + + pwifionly_haldata->customer_id = CUSTOMER_NORMAL; + pwifionly_haldata->efuse_pg_antnum = pHalData->EEPROMBluetoothAntNum; + pwifionly_haldata->efuse_pg_antpath = pHalData->ant_path; + pwifionly_haldata->rfe_type = pHalData->rfe_type; + pwifionly_haldata->ant_div_cfg = pHalData->AntDivCfg; +} diff --git a/drivers/staging/rtl8821ce/hal/hal_com.c b/drivers/staging/rtl8821ce/hal/hal_com.c new file mode 100644 index 000000000000..28c73bd4972a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_com.c @@ -0,0 +1,3490 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_COM_C_ + +#include <drv_types.h> +#include "hal_com_h2c.h" +#include "hal_data.h" +#include "../../hal/hal_halmac.h" + +char rtw_phy_para_file_path[PATH_LENGTH_MAX]; + +void dump_chip_info(HAL_VERSION ChipVersion) +{ + int cnt = 0; + u8 buf[128] = {0}; + + if (IS_8188E(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188E_"); + else if (IS_8188F(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8188F_"); + else if (IS_8812_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8812_"); + else if (IS_8192E(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8192E_"); + else if (IS_8821_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821_"); + else if (IS_8723B_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723B_"); + else if (IS_8703B_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8703B_"); + else if (IS_8723D_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8723D_"); + else if (IS_8814A_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8814A_"); + else if (IS_8822B_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8822B_"); + else if (IS_8821C_SERIES(ChipVersion)) + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_8821C_"); + else + cnt += sprintf((buf + cnt), "Chip Version Info: CHIP_UNKNOWN_"); + + cnt += sprintf((buf + cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip"); + if (IS_CHIP_VENDOR_TSMC(ChipVersion)) + cnt += sprintf((buf + cnt), "%s_", "TSMC"); + else if (IS_CHIP_VENDOR_UMC(ChipVersion)) + cnt += sprintf((buf + cnt), "%s_", "UMC"); + else if (IS_CHIP_VENDOR_SMIC(ChipVersion)) + cnt += sprintf((buf + cnt), "%s_", "SMIC"); + + if (IS_A_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "A_CUT_"); + else if (IS_B_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "B_CUT_"); + else if (IS_C_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "C_CUT_"); + else if (IS_D_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "D_CUT_"); + else if (IS_E_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "E_CUT_"); + else if (IS_F_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "F_CUT_"); + else if (IS_I_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "I_CUT_"); + else if (IS_J_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "J_CUT_"); + else if (IS_K_CUT(ChipVersion)) + cnt += sprintf((buf + cnt), "K_CUT_"); + else + cnt += sprintf((buf + cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion); + + if (IS_1T1R(ChipVersion)) + cnt += sprintf((buf + cnt), "1T1R_"); + else if (IS_1T2R(ChipVersion)) + cnt += sprintf((buf + cnt), "1T2R_"); + else if (IS_2T2R(ChipVersion)) + cnt += sprintf((buf + cnt), "2T2R_"); + else if (IS_3T3R(ChipVersion)) + cnt += sprintf((buf + cnt), "3T3R_"); + else if (IS_3T4R(ChipVersion)) + cnt += sprintf((buf + cnt), "3T4R_"); + else if (IS_4T4R(ChipVersion)) + cnt += sprintf((buf + cnt), "4T4R_"); + else + cnt += sprintf((buf + cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType); + + cnt += sprintf((buf + cnt), "RomVer(%d)\n", ChipVersion.ROMVer); + + RTW_INFO("%s", buf); +} +void rtw_hal_config_rftype(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (IS_1T1R(pHalData->version_id)) { + pHalData->rf_type = RF_1T1R; + pHalData->NumTotalRFPath = 1; + } else if (IS_2T2R(pHalData->version_id)) { + pHalData->rf_type = RF_2T2R; + pHalData->NumTotalRFPath = 2; + } else if (IS_1T2R(pHalData->version_id)) { + pHalData->rf_type = RF_1T2R; + pHalData->NumTotalRFPath = 2; + } else if (IS_3T3R(pHalData->version_id)) { + pHalData->rf_type = RF_3T3R; + pHalData->NumTotalRFPath = 3; + } else if (IS_4T4R(pHalData->version_id)) { + pHalData->rf_type = RF_4T4R; + pHalData->NumTotalRFPath = 4; + } else { + pHalData->rf_type = RF_1T1R; + pHalData->NumTotalRFPath = 1; + } + + RTW_INFO("%s RF_Type is %d TotalTxPath is %d\n", __FUNCTION__, pHalData->rf_type, pHalData->NumTotalRFPath); +} + +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +/* + * Description: + * Use hardware(efuse), driver parameter(registry) and default channel plan + * to decide which one should be used. + * + * Parameters: + * padapter pointer of adapter + * hw_alpha2 country code from HW (efuse/eeprom/mapfile) + * hw_chplan channel plan from HW (efuse/eeprom/mapfile) + * BIT[7] software configure mode; 0:Enable, 1:disable + * BIT[6:0] Channel Plan + * sw_alpha2 country code from HW (registry/module param) + * sw_chplan channel plan from SW (registry/module param) + * def_chplan channel plan used when HW/SW both invalid + * AutoLoadFail efuse autoload fail or not + * + * Return: + * Final channel plan decision + * + */ +u8 hal_com_config_channel_plan( + IN PADAPTER padapter, + IN char *hw_alpha2, + IN u8 hw_chplan, + IN char *sw_alpha2, + IN u8 sw_chplan, + IN u8 def_chplan, + IN BOOLEAN AutoLoadFail +) +{ + PHAL_DATA_TYPE pHalData; + u8 force_hw_chplan = _FALSE; + int chplan = -1; + const struct country_chplan *country_ent = NULL, *ent; + + pHalData = GET_HAL_DATA(padapter); + + /* treat 0xFF as invalid value, bypass hw_chplan & force_hw_chplan parsing */ + if (hw_chplan == 0xFF) + goto chk_hw_country_code; + + if (AutoLoadFail == _TRUE) + goto chk_sw_config; + +#ifndef CONFIG_FORCE_SW_CHANNEL_PLAN + if (hw_chplan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) + force_hw_chplan = _TRUE; +#endif + + hw_chplan &= (~EEPROM_CHANNEL_PLAN_BY_HW_MASK); + +chk_hw_country_code: + if (hw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(hw_alpha2)) { + ent = rtw_get_chplan_from_country(hw_alpha2); + if (ent) { + /* get chplan from hw country code, by pass hw chplan setting */ + country_ent = ent; + chplan = ent->chplan; + goto chk_sw_config; + } else + RTW_PRINT("%s unsupported hw_alpha2:\"%c%c\"\n", __func__, hw_alpha2[0], hw_alpha2[1]); + } + + if (rtw_is_channel_plan_valid(hw_chplan)) + chplan = hw_chplan; + else if (force_hw_chplan == _TRUE) { + RTW_PRINT("%s unsupported hw_chplan:0x%02X\n", __func__, hw_chplan); + /* hw infomaton invalid, refer to sw information */ + force_hw_chplan = _FALSE; + } + +chk_sw_config: + if (force_hw_chplan == _TRUE) + goto done; + + if (sw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(sw_alpha2)) { + ent = rtw_get_chplan_from_country(sw_alpha2); + if (ent) { + /* get chplan from sw country code, by pass sw chplan setting */ + country_ent = ent; + chplan = ent->chplan; + goto done; + } else + RTW_PRINT("%s unsupported sw_alpha2:\"%c%c\"\n", __func__, sw_alpha2[0], sw_alpha2[1]); + } + + if (rtw_is_channel_plan_valid(sw_chplan)) { + /* cancel hw_alpha2 because chplan is specified by sw_chplan*/ + country_ent = NULL; + chplan = sw_chplan; + } else if (sw_chplan != RTW_CHPLAN_MAX) + RTW_PRINT("%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan); + +done: + if (chplan == -1) { + RTW_PRINT("%s use def_chplan:0x%02X\n", __func__, def_chplan); + chplan = def_chplan; + } else if (country_ent) { + RTW_PRINT("%s country code:\"%c%c\" with chplan:0x%02X\n", __func__ + , country_ent->alpha2[0], country_ent->alpha2[1], country_ent->chplan); + } else + RTW_PRINT("%s chplan:0x%02X\n", __func__, chplan); + + padapter->mlmepriv.country_ent = country_ent; + pHalData->bDisableSWChannelPlan = force_hw_chplan; + + return chplan; +} + +BOOLEAN +HAL_IsLegalChannel( + IN PADAPTER Adapter, + IN u32 Channel +) +{ + BOOLEAN bLegalChannel = _TRUE; + + if (Channel > 14) { + if (is_supported_5g(Adapter->registrypriv.wireless_mode) == _FALSE) { + bLegalChannel = _FALSE; + RTW_INFO("Channel > 14 but wireless_mode do not support 5G\n"); + } + } else if ((Channel <= 14) && (Channel >= 1)) { + if (IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) { + bLegalChannel = _FALSE; + RTW_INFO("(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\n"); + } + } else { + bLegalChannel = _FALSE; + RTW_INFO("Channel is Invalid !!!\n"); + } + + return bLegalChannel; +} + +u8 MRateToHwRate(u8 rate) +{ + u8 ret = DESC_RATE1M; + + switch (rate) { + case MGN_1M: + ret = DESC_RATE1M; + break; + case MGN_2M: + ret = DESC_RATE2M; + break; + case MGN_5_5M: + ret = DESC_RATE5_5M; + break; + case MGN_11M: + ret = DESC_RATE11M; + break; + case MGN_6M: + ret = DESC_RATE6M; + break; + case MGN_9M: + ret = DESC_RATE9M; + break; + case MGN_12M: + ret = DESC_RATE12M; + break; + case MGN_18M: + ret = DESC_RATE18M; + break; + case MGN_24M: + ret = DESC_RATE24M; + break; + case MGN_36M: + ret = DESC_RATE36M; + break; + case MGN_48M: + ret = DESC_RATE48M; + break; + case MGN_54M: + ret = DESC_RATE54M; + break; + + case MGN_MCS0: + ret = DESC_RATEMCS0; + break; + case MGN_MCS1: + ret = DESC_RATEMCS1; + break; + case MGN_MCS2: + ret = DESC_RATEMCS2; + break; + case MGN_MCS3: + ret = DESC_RATEMCS3; + break; + case MGN_MCS4: + ret = DESC_RATEMCS4; + break; + case MGN_MCS5: + ret = DESC_RATEMCS5; + break; + case MGN_MCS6: + ret = DESC_RATEMCS6; + break; + case MGN_MCS7: + ret = DESC_RATEMCS7; + break; + case MGN_MCS8: + ret = DESC_RATEMCS8; + break; + case MGN_MCS9: + ret = DESC_RATEMCS9; + break; + case MGN_MCS10: + ret = DESC_RATEMCS10; + break; + case MGN_MCS11: + ret = DESC_RATEMCS11; + break; + case MGN_MCS12: + ret = DESC_RATEMCS12; + break; + case MGN_MCS13: + ret = DESC_RATEMCS13; + break; + case MGN_MCS14: + ret = DESC_RATEMCS14; + break; + case MGN_MCS15: + ret = DESC_RATEMCS15; + break; + case MGN_MCS16: + ret = DESC_RATEMCS16; + break; + case MGN_MCS17: + ret = DESC_RATEMCS17; + break; + case MGN_MCS18: + ret = DESC_RATEMCS18; + break; + case MGN_MCS19: + ret = DESC_RATEMCS19; + break; + case MGN_MCS20: + ret = DESC_RATEMCS20; + break; + case MGN_MCS21: + ret = DESC_RATEMCS21; + break; + case MGN_MCS22: + ret = DESC_RATEMCS22; + break; + case MGN_MCS23: + ret = DESC_RATEMCS23; + break; + case MGN_MCS24: + ret = DESC_RATEMCS24; + break; + case MGN_MCS25: + ret = DESC_RATEMCS25; + break; + case MGN_MCS26: + ret = DESC_RATEMCS26; + break; + case MGN_MCS27: + ret = DESC_RATEMCS27; + break; + case MGN_MCS28: + ret = DESC_RATEMCS28; + break; + case MGN_MCS29: + ret = DESC_RATEMCS29; + break; + case MGN_MCS30: + ret = DESC_RATEMCS30; + break; + case MGN_MCS31: + ret = DESC_RATEMCS31; + break; + + case MGN_VHT1SS_MCS0: + ret = DESC_RATEVHTSS1MCS0; + break; + case MGN_VHT1SS_MCS1: + ret = DESC_RATEVHTSS1MCS1; + break; + case MGN_VHT1SS_MCS2: + ret = DESC_RATEVHTSS1MCS2; + break; + case MGN_VHT1SS_MCS3: + ret = DESC_RATEVHTSS1MCS3; + break; + case MGN_VHT1SS_MCS4: + ret = DESC_RATEVHTSS1MCS4; + break; + case MGN_VHT1SS_MCS5: + ret = DESC_RATEVHTSS1MCS5; + break; + case MGN_VHT1SS_MCS6: + ret = DESC_RATEVHTSS1MCS6; + break; + case MGN_VHT1SS_MCS7: + ret = DESC_RATEVHTSS1MCS7; + break; + case MGN_VHT1SS_MCS8: + ret = DESC_RATEVHTSS1MCS8; + break; + case MGN_VHT1SS_MCS9: + ret = DESC_RATEVHTSS1MCS9; + break; + case MGN_VHT2SS_MCS0: + ret = DESC_RATEVHTSS2MCS0; + break; + case MGN_VHT2SS_MCS1: + ret = DESC_RATEVHTSS2MCS1; + break; + case MGN_VHT2SS_MCS2: + ret = DESC_RATEVHTSS2MCS2; + break; + case MGN_VHT2SS_MCS3: + ret = DESC_RATEVHTSS2MCS3; + break; + case MGN_VHT2SS_MCS4: + ret = DESC_RATEVHTSS2MCS4; + break; + case MGN_VHT2SS_MCS5: + ret = DESC_RATEVHTSS2MCS5; + break; + case MGN_VHT2SS_MCS6: + ret = DESC_RATEVHTSS2MCS6; + break; + case MGN_VHT2SS_MCS7: + ret = DESC_RATEVHTSS2MCS7; + break; + case MGN_VHT2SS_MCS8: + ret = DESC_RATEVHTSS2MCS8; + break; + case MGN_VHT2SS_MCS9: + ret = DESC_RATEVHTSS2MCS9; + break; + case MGN_VHT3SS_MCS0: + ret = DESC_RATEVHTSS3MCS0; + break; + case MGN_VHT3SS_MCS1: + ret = DESC_RATEVHTSS3MCS1; + break; + case MGN_VHT3SS_MCS2: + ret = DESC_RATEVHTSS3MCS2; + break; + case MGN_VHT3SS_MCS3: + ret = DESC_RATEVHTSS3MCS3; + break; + case MGN_VHT3SS_MCS4: + ret = DESC_RATEVHTSS3MCS4; + break; + case MGN_VHT3SS_MCS5: + ret = DESC_RATEVHTSS3MCS5; + break; + case MGN_VHT3SS_MCS6: + ret = DESC_RATEVHTSS3MCS6; + break; + case MGN_VHT3SS_MCS7: + ret = DESC_RATEVHTSS3MCS7; + break; + case MGN_VHT3SS_MCS8: + ret = DESC_RATEVHTSS3MCS8; + break; + case MGN_VHT3SS_MCS9: + ret = DESC_RATEVHTSS3MCS9; + break; + case MGN_VHT4SS_MCS0: + ret = DESC_RATEVHTSS4MCS0; + break; + case MGN_VHT4SS_MCS1: + ret = DESC_RATEVHTSS4MCS1; + break; + case MGN_VHT4SS_MCS2: + ret = DESC_RATEVHTSS4MCS2; + break; + case MGN_VHT4SS_MCS3: + ret = DESC_RATEVHTSS4MCS3; + break; + case MGN_VHT4SS_MCS4: + ret = DESC_RATEVHTSS4MCS4; + break; + case MGN_VHT4SS_MCS5: + ret = DESC_RATEVHTSS4MCS5; + break; + case MGN_VHT4SS_MCS6: + ret = DESC_RATEVHTSS4MCS6; + break; + case MGN_VHT4SS_MCS7: + ret = DESC_RATEVHTSS4MCS7; + break; + case MGN_VHT4SS_MCS8: + ret = DESC_RATEVHTSS4MCS8; + break; + case MGN_VHT4SS_MCS9: + ret = DESC_RATEVHTSS4MCS9; + break; + default: + break; + } + + return ret; +} + +u8 hw_rate_to_m_rate(u8 rate) +{ + u8 ret_rate = MGN_1M; + + switch (rate) { + + case DESC_RATE1M: + ret_rate = MGN_1M; + break; + case DESC_RATE2M: + ret_rate = MGN_2M; + break; + case DESC_RATE5_5M: + ret_rate = MGN_5_5M; + break; + case DESC_RATE11M: + ret_rate = MGN_11M; + break; + case DESC_RATE6M: + ret_rate = MGN_6M; + break; + case DESC_RATE9M: + ret_rate = MGN_9M; + break; + case DESC_RATE12M: + ret_rate = MGN_12M; + break; + case DESC_RATE18M: + ret_rate = MGN_18M; + break; + case DESC_RATE24M: + ret_rate = MGN_24M; + break; + case DESC_RATE36M: + ret_rate = MGN_36M; + break; + case DESC_RATE48M: + ret_rate = MGN_48M; + break; + case DESC_RATE54M: + ret_rate = MGN_54M; + break; + case DESC_RATEMCS0: + ret_rate = MGN_MCS0; + break; + case DESC_RATEMCS1: + ret_rate = MGN_MCS1; + break; + case DESC_RATEMCS2: + ret_rate = MGN_MCS2; + break; + case DESC_RATEMCS3: + ret_rate = MGN_MCS3; + break; + case DESC_RATEMCS4: + ret_rate = MGN_MCS4; + break; + case DESC_RATEMCS5: + ret_rate = MGN_MCS5; + break; + case DESC_RATEMCS6: + ret_rate = MGN_MCS6; + break; + case DESC_RATEMCS7: + ret_rate = MGN_MCS7; + break; + case DESC_RATEMCS8: + ret_rate = MGN_MCS8; + break; + case DESC_RATEMCS9: + ret_rate = MGN_MCS9; + break; + case DESC_RATEMCS10: + ret_rate = MGN_MCS10; + break; + case DESC_RATEMCS11: + ret_rate = MGN_MCS11; + break; + case DESC_RATEMCS12: + ret_rate = MGN_MCS12; + break; + case DESC_RATEMCS13: + ret_rate = MGN_MCS13; + break; + case DESC_RATEMCS14: + ret_rate = MGN_MCS14; + break; + case DESC_RATEMCS15: + ret_rate = MGN_MCS15; + break; + case DESC_RATEMCS16: + ret_rate = MGN_MCS16; + break; + case DESC_RATEMCS17: + ret_rate = MGN_MCS17; + break; + case DESC_RATEMCS18: + ret_rate = MGN_MCS18; + break; + case DESC_RATEMCS19: + ret_rate = MGN_MCS19; + break; + case DESC_RATEMCS20: + ret_rate = MGN_MCS20; + break; + case DESC_RATEMCS21: + ret_rate = MGN_MCS21; + break; + case DESC_RATEMCS22: + ret_rate = MGN_MCS22; + break; + case DESC_RATEMCS23: + ret_rate = MGN_MCS23; + break; + case DESC_RATEMCS24: + ret_rate = MGN_MCS24; + break; + case DESC_RATEMCS25: + ret_rate = MGN_MCS25; + break; + case DESC_RATEMCS26: + ret_rate = MGN_MCS26; + break; + case DESC_RATEMCS27: + ret_rate = MGN_MCS27; + break; + case DESC_RATEMCS28: + ret_rate = MGN_MCS28; + break; + case DESC_RATEMCS29: + ret_rate = MGN_MCS29; + break; + case DESC_RATEMCS30: + ret_rate = MGN_MCS30; + break; + case DESC_RATEMCS31: + ret_rate = MGN_MCS31; + break; + case DESC_RATEVHTSS1MCS0: + ret_rate = MGN_VHT1SS_MCS0; + break; + case DESC_RATEVHTSS1MCS1: + ret_rate = MGN_VHT1SS_MCS1; + break; + case DESC_RATEVHTSS1MCS2: + ret_rate = MGN_VHT1SS_MCS2; + break; + case DESC_RATEVHTSS1MCS3: + ret_rate = MGN_VHT1SS_MCS3; + break; + case DESC_RATEVHTSS1MCS4: + ret_rate = MGN_VHT1SS_MCS4; + break; + case DESC_RATEVHTSS1MCS5: + ret_rate = MGN_VHT1SS_MCS5; + break; + case DESC_RATEVHTSS1MCS6: + ret_rate = MGN_VHT1SS_MCS6; + break; + case DESC_RATEVHTSS1MCS7: + ret_rate = MGN_VHT1SS_MCS7; + break; + case DESC_RATEVHTSS1MCS8: + ret_rate = MGN_VHT1SS_MCS8; + break; + case DESC_RATEVHTSS1MCS9: + ret_rate = MGN_VHT1SS_MCS9; + break; + case DESC_RATEVHTSS2MCS0: + ret_rate = MGN_VHT2SS_MCS0; + break; + case DESC_RATEVHTSS2MCS1: + ret_rate = MGN_VHT2SS_MCS1; + break; + case DESC_RATEVHTSS2MCS2: + ret_rate = MGN_VHT2SS_MCS2; + break; + case DESC_RATEVHTSS2MCS3: + ret_rate = MGN_VHT2SS_MCS3; + break; + case DESC_RATEVHTSS2MCS4: + ret_rate = MGN_VHT2SS_MCS4; + break; + case DESC_RATEVHTSS2MCS5: + ret_rate = MGN_VHT2SS_MCS5; + break; + case DESC_RATEVHTSS2MCS6: + ret_rate = MGN_VHT2SS_MCS6; + break; + case DESC_RATEVHTSS2MCS7: + ret_rate = MGN_VHT2SS_MCS7; + break; + case DESC_RATEVHTSS2MCS8: + ret_rate = MGN_VHT2SS_MCS8; + break; + case DESC_RATEVHTSS2MCS9: + ret_rate = MGN_VHT2SS_MCS9; + break; + case DESC_RATEVHTSS3MCS0: + ret_rate = MGN_VHT3SS_MCS0; + break; + case DESC_RATEVHTSS3MCS1: + ret_rate = MGN_VHT3SS_MCS1; + break; + case DESC_RATEVHTSS3MCS2: + ret_rate = MGN_VHT3SS_MCS2; + break; + case DESC_RATEVHTSS3MCS3: + ret_rate = MGN_VHT3SS_MCS3; + break; + case DESC_RATEVHTSS3MCS4: + ret_rate = MGN_VHT3SS_MCS4; + break; + case DESC_RATEVHTSS3MCS5: + ret_rate = MGN_VHT3SS_MCS5; + break; + case DESC_RATEVHTSS3MCS6: + ret_rate = MGN_VHT3SS_MCS6; + break; + case DESC_RATEVHTSS3MCS7: + ret_rate = MGN_VHT3SS_MCS7; + break; + case DESC_RATEVHTSS3MCS8: + ret_rate = MGN_VHT3SS_MCS8; + break; + case DESC_RATEVHTSS3MCS9: + ret_rate = MGN_VHT3SS_MCS9; + break; + case DESC_RATEVHTSS4MCS0: + ret_rate = MGN_VHT4SS_MCS0; + break; + case DESC_RATEVHTSS4MCS1: + ret_rate = MGN_VHT4SS_MCS1; + break; + case DESC_RATEVHTSS4MCS2: + ret_rate = MGN_VHT4SS_MCS2; + break; + case DESC_RATEVHTSS4MCS3: + ret_rate = MGN_VHT4SS_MCS3; + break; + case DESC_RATEVHTSS4MCS4: + ret_rate = MGN_VHT4SS_MCS4; + break; + case DESC_RATEVHTSS4MCS5: + ret_rate = MGN_VHT4SS_MCS5; + break; + case DESC_RATEVHTSS4MCS6: + ret_rate = MGN_VHT4SS_MCS6; + break; + case DESC_RATEVHTSS4MCS7: + ret_rate = MGN_VHT4SS_MCS7; + break; + case DESC_RATEVHTSS4MCS8: + ret_rate = MGN_VHT4SS_MCS8; + break; + case DESC_RATEVHTSS4MCS9: + ret_rate = MGN_VHT4SS_MCS9; + break; + + default: + RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate); + break; + } + + return ret_rate; +} + +void HalSetBrateCfg( + IN PADAPTER Adapter, + IN u8 *mBratesOS, + OUT u16 *pBrateCfg) +{ + u8 i, is_brate, brate; + + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK; + brate = mBratesOS[i] & 0x7f; + + if (is_brate) { + switch (brate) { + case IEEE80211_CCK_RATE_1MB: + *pBrateCfg |= RATE_1M; + break; + case IEEE80211_CCK_RATE_2MB: + *pBrateCfg |= RATE_2M; + break; + case IEEE80211_CCK_RATE_5MB: + *pBrateCfg |= RATE_5_5M; + break; + case IEEE80211_CCK_RATE_11MB: + *pBrateCfg |= RATE_11M; + break; + case IEEE80211_OFDM_RATE_6MB: + *pBrateCfg |= RATE_6M; + break; + case IEEE80211_OFDM_RATE_9MB: + *pBrateCfg |= RATE_9M; + break; + case IEEE80211_OFDM_RATE_12MB: + *pBrateCfg |= RATE_12M; + break; + case IEEE80211_OFDM_RATE_18MB: + *pBrateCfg |= RATE_18M; + break; + case IEEE80211_OFDM_RATE_24MB: + *pBrateCfg |= RATE_24M; + break; + case IEEE80211_OFDM_RATE_36MB: + *pBrateCfg |= RATE_36M; + break; + case IEEE80211_OFDM_RATE_48MB: + *pBrateCfg |= RATE_48M; + break; + case IEEE80211_OFDM_RATE_54MB: + *pBrateCfg |= RATE_54M; + break; + } + } + } +} + +void rtw_hal_dump_macaddr(void *sel, _adapter *adapter) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 mac_addr[ETH_ALEN]; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + rtw_hal_get_macaddr_port(iface, mac_addr); + RTW_PRINT_SEL(sel, ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", + ADPT_ARG(iface), iface->hw_port, MAC_ARG(mac_addr)); + } + } +} + +void rtw_restore_mac_addr(_adapter *adapter) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) + rtw_hal_set_macaddr_port(iface, adapter_mac_addr(iface)); + } + if (1) + rtw_hal_dump_macaddr(RTW_DBGDUMP, adapter); +} + +void rtw_init_hal_com_default_value(PADAPTER Adapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + struct registry_priv *regsty = adapter_to_regsty(Adapter); + + pHalData->AntDetection = 1; + pHalData->antenna_test = _FALSE; + pHalData->u1ForcedIgiLb = regsty->force_igi_lb; +} + +#ifndef DBG_C2H_PKT_PRE_HDL +#define DBG_C2H_PKT_PRE_HDL 0 +#endif +#ifndef DBG_C2H_PKT_HDL +#define DBG_C2H_PKT_HDL 0 +#endif + +void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len) +{ + adapter->hal_func.hal_mac_c2h_handler(adapter, buf, len); +} + +void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct submit_ctx *iqk_sctx = &hal_data->iqk_sctx; + + RTW_INFO("IQK offload finish in %dms\n", rtw_get_passing_time_ms(iqk_sctx->submit_time)); + if (0) + RTW_INFO_DUMP("C2H_IQK_FINISH: ", data, len); + + rtw_sctx_done(&iqk_sctx); +} + +#define GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8) +#define GET_C2H_MAC_HIDDEN_RPT_UUID_Y(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8) +#define GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5) +#define GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11) +#define GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4) +#define GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3) +#define GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1) +#define GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4) +#define GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4) +#define GET_C2H_MAC_HIDDEN_RPT_BW(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3) +#define GET_C2H_MAC_HIDDEN_RPT_FAB(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 3, 2) +#define GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3) +#define GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2) +#define GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2) + +#ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE +#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0 +#endif + +int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + u32 uuid; + u8 uuid_x; + u8 uuid_y; + u8 uuid_z; + u16 uuid_crc; + + u8 hci_type; + u8 package_type; + u8 tr_switch; + u8 wl_func; + u8 hw_stype; + u8 bw; + u8 fab; + u8 ant_num; + u8 protocol; + u8 nic; + + int i; + + if (len < MAC_HIDDEN_RPT_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_LEN); + goto exit; + } + + uuid_x = GET_C2H_MAC_HIDDEN_RPT_UUID_X(data); + uuid_y = GET_C2H_MAC_HIDDEN_RPT_UUID_Y(data); + uuid_z = GET_C2H_MAC_HIDDEN_RPT_UUID_Z(data); + uuid_crc = GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(data); + + hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data); + package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data); + + tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data); + + wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data); + hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data); + + bw = GET_C2H_MAC_HIDDEN_RPT_BW(data); + fab = GET_C2H_MAC_HIDDEN_RPT_FAB(data); + ant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data); + + protocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data); + nic = GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(data); + + if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) { + for (i = 0; i < len; i++) + RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); + + RTW_PRINT("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc); + RTW_PRINT("hci_type:0x%x\n", hci_type); + RTW_PRINT("package_type:0x%x\n", package_type); + RTW_PRINT("tr_switch:0x%x\n", tr_switch); + RTW_PRINT("wl_func:0x%x\n", wl_func); + RTW_PRINT("hw_stype:0x%x\n", hw_stype); + RTW_PRINT("bw:0x%x\n", bw); + RTW_PRINT("fab:0x%x\n", fab); + RTW_PRINT("ant_num:0x%x\n", ant_num); + RTW_PRINT("protocol:0x%x\n", protocol); + RTW_PRINT("nic:0x%x\n", nic); + } + + /* + * NOTICE: + * for now, the following is common info/format + * if there is any hal difference need to export + * some IC dependent code will need to be implement + */ + hal_data->PackageType = package_type; + hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func); + hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw); + hal_spec->tx_nss_num = rtw_min(hal_spec->tx_nss_num, ant_num); + hal_spec->rx_nss_num = rtw_min(hal_spec->rx_nss_num, ant_num); + hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol); + hal_spec->hci_type = hci_type; + + /* TODO: tr_switch */ + /* TODO: fab */ + + ret = _SUCCESS; + +exit: + return ret; +} + +int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + int i; + + if (len < MAC_HIDDEN_RPT_2_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN); + goto exit; + } + + if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) { + for (i = 0; i < len; i++) + RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); + } + + ret = _SUCCESS; + +exit: + return ret; +} + +int hal_read_mac_hidden_rpt(_adapter *adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + int ret = _FAIL; + int ret_fwdl; + u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0}; + u32 start = rtw_get_current_time(); + u32 cnt = 0; + u32 timeout_ms = 800; + u32 min_cnt = 10; + u8 id = C2H_DEFEATURE_RSVD; + int i; + + u8 hci_type = rtw_get_intf_type(adapter); + + if ((hci_type == RTW_USB || hci_type == RTW_PCIE) + && !rtw_is_hw_init_completed(adapter)) + rtw_hal_power_on(adapter); + + /* inform FW mac hidden rpt from reg is needed */ + rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD); + + /* download FW */ + pHalData->not_xmitframe_fw_dl = 1; + ret_fwdl = rtw_hal_fw_dl(adapter); + pHalData->not_xmitframe_fw_dl = 0; + if (ret_fwdl != _SUCCESS) + goto mac_hidden_rpt_hdl; + + /* polling for data ready */ + start = rtw_get_current_time(); + do { + cnt++; + id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL); + if (id == C2H_MAC_HIDDEN_RPT || RTW_CANNOT_IO(adapter)) + break; + rtw_msleep_os(10); + } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt); + + if (id == C2H_MAC_HIDDEN_RPT) { + /* read data */ + for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++) + mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); + } + + /* inform FW mac hidden rpt has read */ + rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG); + +mac_hidden_rpt_hdl: + c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN); + c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN); + + if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT) + ret = _SUCCESS; + + if ((hci_type == RTW_USB || hci_type == RTW_PCIE) + && !rtw_is_hw_init_completed(adapter)) + rtw_hal_power_off(adapter); + + RTW_INFO("%s %s! (%u, %dms), fwdl:%d, id:0x%02x\n", __func__ + , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), ret_fwdl, id); + + return ret; +} + +int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + int i; + + if (len < DEFEATURE_DBG_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN); + goto exit; + } + + for (i = 0; i < len; i++) + RTW_PRINT("%s: 0x%02X\n", __func__, *(data + i)); + + ret = _SUCCESS; + +exit: + return ret; +} + +#ifndef DBG_CUSTOMER_STR_RPT_HANDLE +#define DBG_CUSTOMER_STR_RPT_HANDLE 0 +#endif + + +u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta) +{ +#ifdef CONFIG_GET_RAID_BY_DRV /*Just for 8188E now*/ + if (IS_NEW_GENERATION_IC(adapter)) + return networktype_to_raid_ex(adapter, psta); + else + return networktype_to_raid(adapter, psta); +#else + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + u8 bw; + + bw = rtw_get_tx_bw_mode(adapter, psta); + + return phydm_rate_id_mapping(&pHalData->odmpriv, psta->wireless_mode, pHalData->rf_type, bw); +#endif +} +u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type) +{ + + u8 raid; + if (IS_NEW_GENERATION_IC(adapter)) { + + raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B + : RATEID_IDX_G; + } else { + raid = (network_type & WIRELESS_11B) ? RATR_INX_WIRELESS_B + : RATR_INX_WIRELESS_G; + } + return raid; +} + +void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + u8 i, rf_type, tx_nss; + u64 tx_ra_bitmap; + + if (psta == NULL) + return; + + tx_ra_bitmap = 0; + + /* b/g mode ra_bitmap */ + for (i = 0; i < sizeof(psta->bssrateset); i++) { + if (psta->bssrateset[i]) + tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i] & 0x7f); + } + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + tx_nss = rtw_min(rf_type_to_rf_tx_cnt(rf_type), hal_spec->tx_nss_num); + if (psta->vhtpriv.vht_option) { + /* AC mode ra_bitmap */ + tx_ra_bitmap |= (rtw_vht_mcs_map_to_bitmap(psta->vhtpriv.vht_mcs_map, tx_nss) << 12); + } else + if (psta->htpriv.ht_option) { + /* n mode ra_bitmap */ + + /* Handling SMPS mode for AP MODE only*/ + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) { + /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/ + tx_nss = rtw_min(tx_nss, 1); + } + } + + tx_ra_bitmap |= (rtw_ht_mcs_set_to_bitmap(psta->htpriv.ht_cap.supp_mcs_set, tx_nss) << 12); + } + psta->ra_mask = tx_ra_bitmap; + psta->init_rate = get_highest_rate_idx(tx_ra_bitmap) & 0x3f; +} + +#ifndef SEC_CAM_ACCESS_TIMEOUT_MS + #define SEC_CAM_ACCESS_TIMEOUT_MS 200 +#endif + +#ifndef DBG_SEC_CAM_ACCESS + #define DBG_SEC_CAM_ACCESS 0 +#endif + +u32 rtw_sec_read_cam(_adapter *adapter, u8 addr) +{ + _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; + u32 rdata; + u32 cnt = 0; + u32 start = 0, end = 0; + u8 timeout = 0; + u8 sr = 0; + + _enter_critical_mutex(mutex, NULL); + + rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr); + + start = rtw_get_current_time(); + while (1) { + if (rtw_is_surprise_removed(adapter)) { + sr = 1; + break; + } + + cnt++; + if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG)) + break; + + if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) { + timeout = 1; + break; + } + } + end = rtw_get_current_time(); + + rdata = rtw_read32(adapter, REG_CAMREAD); + + _exit_critical_mutex(mutex, NULL); + + if (DBG_SEC_CAM_ACCESS || timeout) { + RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n" + , FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end)); + } + + return rdata; +} + +void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata) +{ + _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; + u32 cnt = 0; + u32 start = 0, end = 0; + u8 timeout = 0; + u8 sr = 0; + + _enter_critical_mutex(mutex, NULL); + + rtw_write32(adapter, REG_CAMWRITE, wdata); + rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr); + + start = rtw_get_current_time(); + while (1) { + if (rtw_is_surprise_removed(adapter)) { + sr = 1; + break; + } + + cnt++; + if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG)) + break; + + if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) { + timeout = 1; + break; + } + } + end = rtw_get_current_time(); + + _exit_critical_mutex(mutex, NULL); + + if (DBG_SEC_CAM_ACCESS || timeout) { + RTW_INFO(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n" + , FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end)); + } +} + +void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key) +{ + unsigned int val, addr; + u8 i; + u32 rdata; + u8 begin = 0; + u8 end = 5; /* TODO: consider other key length accordingly */ + + if (!ctrl && !mac && !key) { + rtw_warn_on(1); + goto exit; + } + + /* TODO: check id range */ + + if (!ctrl && !mac) + begin = 2; /* read from key */ + + if (!key && !mac) + end = 0; /* read to ctrl */ + else if (!key) + end = 2; /* read to mac */ + + for (i = begin; i <= end; i++) { + rdata = rtw_sec_read_cam(adapter, (id << 3) | i); + + switch (i) { + case 0: + if (ctrl) + _rtw_memcpy(ctrl, (u8 *)(&rdata), 2); + if (mac) + _rtw_memcpy(mac, ((u8 *)(&rdata)) + 2, 2); + break; + case 1: + if (mac) + _rtw_memcpy(mac + 2, (u8 *)(&rdata), 4); + break; + default: + if (key) + _rtw_memcpy(key + (i - 2) * 4, (u8 *)(&rdata), 4); + break; + } + } + +exit: + return; +} + +void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ + unsigned int i; + int j; + u8 addr; + u32 wdata; + + /* TODO: consider other key length accordingly */ + j = 7; + + for (; j >= 0; j--) { + switch (j) { + case 0: + wdata = (ctrl | (mac[0] << 16) | (mac[1] << 24)); + break; + case 1: + wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24)); + break; + case 6: + case 7: + wdata = 0; + break; + default: + i = (j - 2) << 2; + wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24)); + break; + } + + addr = (id << 3) + j; + + rtw_sec_write_cam(adapter, addr, wdata); + } +} + +void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val) +{ + u8 idx = 0; + u32 reg_macid = 0; + + if (val == NULL) + return; + + RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__, + ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val)); + + switch (adapter->hw_port) { + case HW_PORT0: + default: + reg_macid = REG_MACID; + break; + case HW_PORT1: + reg_macid = REG_MACID1; + break; + } + + for (idx = 0; idx < 6; idx++) + rtw_write8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx), val[idx]); +} +void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr) +{ + u8 idx = 0; + u32 reg_macid = 0; + + if (mac_addr == NULL) + return; + + _rtw_memset(mac_addr, 0, ETH_ALEN); + switch (adapter->hw_port) { + case HW_PORT0: + default: + reg_macid = REG_MACID; + break; + case HW_PORT1: + reg_macid = REG_MACID1; + break; + } + + for (idx = 0; idx < 6; idx++) + mac_addr[idx] = rtw_read8(GET_PRIMARY_ADAPTER(adapter), (reg_macid + idx)); + + RTW_INFO("%s "ADPT_FMT"- hw port(%d) mac_addr ="MAC_FMT"\n", __func__, + ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(mac_addr)); +} + +void rtw_hal_set_bssid(_adapter *adapter, u8 *val) +{ + u8 idx = 0; + u32 reg_bssid = 0; + + switch (adapter->hw_port) { + case HW_PORT0: + default: + reg_bssid = REG_BSSID; + break; + case HW_PORT1: + reg_bssid = REG_BSSID1; + break; + } + + for (idx = 0 ; idx < 6; idx++) + rtw_write8(adapter, (reg_bssid + idx), val[idx]); + + RTW_INFO("%s "ADPT_FMT"- hw port -%d BSSID: "MAC_FMT"\n", __func__, ADPT_ARG(adapter), adapter->hw_port, MAC_ARG(val)); +} + +void rtw_hal_get_msr(_adapter *adapter, u8 *net_type) +{ + switch (adapter->hw_port) { + case HW_PORT0: + /*REG_CR - BIT[17:16]-Network Type for port 1*/ + *net_type = rtw_read8(adapter, MSR) & 0x03; + break; + case HW_PORT1: + /*REG_CR - BIT[19:18]-Network Type for port 1*/ + *net_type = (rtw_read8(adapter, MSR) & 0x0C) >> 2; + break; + default: + RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n", + ADPT_ARG(adapter), adapter->hw_port); + rtw_warn_on(1); + break; + } +} + +void rtw_hal_set_msr(_adapter *adapter, u8 net_type) +{ + u8 val8 = 0; + + switch (adapter->hw_port) { + case HW_PORT0: + /*REG_CR - BIT[17:16]-Network Type for port 0*/ + val8 = rtw_read8(adapter, MSR) & 0x0C; + val8 |= net_type; + rtw_write8(adapter, MSR, val8); + break; + case HW_PORT1: + /*REG_CR - BIT[19:18]-Network Type for port 1*/ + val8 = rtw_read8(adapter, MSR) & 0x03; + val8 |= net_type << 2; + rtw_write8(adapter, MSR, val8); + break; + case HW_PORT2: + /*REG_CR_EXT- BIT[1:0]-Network Type for port 2*/ + val8 = rtw_read8(adapter, MSR1) & 0xFC; + val8 |= net_type; + rtw_write8(adapter, MSR1, val8); + break; + case HW_PORT3: + /*REG_CR_EXT- BIT[3:2]-Network Type for port 3*/ + val8 = rtw_read8(adapter, MSR1) & 0xF3; + val8 |= net_type << 2; + rtw_write8(adapter, MSR1, val8); + break; + case HW_PORT4: + /*REG_CR_EXT- BIT[5:4]-Network Type for port 4*/ + val8 = rtw_read8(adapter, MSR1) & 0xCF; + val8 |= net_type << 4; + rtw_write8(adapter, MSR1, val8); + break; + default: + RTW_INFO("[WARN] "ADPT_FMT"- invalid hw port -%d\n", + ADPT_ARG(adapter), adapter->hw_port); + rtw_warn_on(1); + break; + } +} + +void hw_var_port_switch(_adapter *adapter) +{ +} + +const char *const _h2c_msr_role_str[] = { + "RSVD", + "STA", + "AP", + "GC", + "GO", + "TDLS", + "ADHOC", + "INVALID", +}; + + +void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &adapter->stapriv; + struct sta_info *psta; + HAL_P2P_PS_PARA p2p_ps_para; + int status = -1; + u8 i; + + _rtw_memset(&p2p_ps_para, 0, sizeof(HAL_P2P_PS_PARA)); + _rtw_memcpy((&p2p_ps_para) , &hal->p2p_ps_offload , sizeof(hal->p2p_ps_offload)); + + (&p2p_ps_para)->p2p_port_id = adapter->hw_port; + (&p2p_ps_para)->p2p_group = 0; + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) { + (&p2p_ps_para)->p2p_macid = psta->mac_id; + } else { + if (p2p_ps_state != P2P_PS_DISABLE) { + RTW_ERR("%s , psta was NULL\n", __func__); + return; + } + } + + switch (p2p_ps_state) { + case P2P_PS_DISABLE: + RTW_INFO("P2P_PS_DISABLE\n"); + _rtw_memset(&p2p_ps_para , 0, sizeof(HAL_P2P_PS_PARA)); + break; + + case P2P_PS_ENABLE: + RTW_INFO("P2P_PS_ENABLE\n"); + /* update CTWindow value. */ + if (pwdinfo->ctwindow > 0) { + (&p2p_ps_para)->ctwindow_en = 1; + (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow; + /*RTW_INFO("%s , ctwindow_length = %d\n" , __func__ , (&p2p_ps_para)->ctwindow_length);*/ + } + + if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) { + (&p2p_ps_para)->offload_en = 1; + if (pwdinfo->role == P2P_ROLE_GO) { + (&p2p_ps_para)->role = 1; + (&p2p_ps_para)->all_sta_sleep = 0; + } else + (&p2p_ps_para)->role = 0; + + (&p2p_ps_para)->discovery = 0; + } + /* hw only support 2 set of NoA */ + for (i = 0; i < pwdinfo->noa_num; i++) { + /* To control the register setting for which NOA */ + (&p2p_ps_para)->noa_sel = i; + (&p2p_ps_para)->noa_en = 1; + /* config P2P NoA Descriptor Register */ + /* config NOA duration */ + (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[i]; + /* config NOA interval */ + (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[i]; + /* config NOA start time */ + (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[i]; + /* config NOA count */ + (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[i]; + /*RTW_INFO("%s , noa_duration_para = %d , noa_interval_para = %d , noa_start_time_para = %d , noa_count_para = %d\n" , __func__ , + (&p2p_ps_para)->noa_duration_para , (&p2p_ps_para)->noa_interval_para , + (&p2p_ps_para)->noa_start_time_para , (&p2p_ps_para)->noa_count_para);*/ + status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para)); + if (status == -1) + RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__); + } + + break; + + case P2P_PS_SCAN: + /*This feature FW not ready 20161116 YiWei*/ + return; + RTW_INFO("P2P_PS_SCAN\n"); + (&p2p_ps_para)->discovery = 1; + /* + (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow; + (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0]; + (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0]; + (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0]; + (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0]; + */ + break; + + case P2P_PS_SCAN_DONE: + /*This feature FW not ready 20161116 YiWei*/ + return; + RTW_INFO("P2P_PS_SCAN_DONE\n"); + (&p2p_ps_para)->discovery = 0; + /* + pwdinfo->p2p_ps_state = P2P_PS_ENABLE; + (&p2p_ps_para)->ctwindow_length = pwdinfo->ctwindow; + (&p2p_ps_para)->noa_duration_para = pwdinfo->noa_duration[0]; + (&p2p_ps_para)->noa_interval_para = pwdinfo->noa_interval[0]; + (&p2p_ps_para)->noa_start_time_para = pwdinfo->noa_start_time[0]; + (&p2p_ps_para)->noa_count_para = pwdinfo->noa_count[0]; + */ + break; + + default: + break; + } + + if (p2p_ps_state != P2P_PS_ENABLE || (&p2p_ps_para)->noa_en == 0) { + status = rtw_halmac_p2pps(adapter_to_dvobj(adapter) , (&p2p_ps_para)); + if (status == -1) + RTW_ERR("%s , rtw_halmac_p2pps fail\n", __func__); + } + _rtw_memcpy(&hal->p2p_ps_offload , (&p2p_ps_para) , sizeof(hal->p2p_ps_offload)); + +} + +/* +* rtw_hal_set_FwMediaStatusRpt_cmd - +* +* @adapter: +* @opmode: 0:disconnect, 1:connect +* @miracast: 0:it's not in miracast scenario. 1:it's in miracast scenario +* @miracast_sink: 0:source. 1:sink +* @role: The role of this macid. 0:rsvd. 1:STA. 2:AP. 3:GC. 4:GO. 5:TDLS +* @macid: +* @macid_ind: 0:update Media Status to macid. 1:update Media Status from macid to macid_end +* @macid_end: +*/ +s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + u8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0}; + int i; + s32 ret; + + SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode); + SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind); + SET_H2CCMD_MSRRPT_PARM_MIRACAST(parm, miracast); + SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(parm, miracast_sink); + SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role); + SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid); + SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end); + RTW_DBG_DUMP("MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN); + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm); + if (ret != _SUCCESS) + goto exit; + + SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0); + if (macid_ind == 0) + macid_end = macid; + + for (i = macid; macid <= macid_end; macid++) { + rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]); + if (!opmode) { + rtw_macid_ctl_set_bw(macid_ctl, macid, CHANNEL_WIDTH_20); + rtw_macid_ctl_set_vht_en(macid_ctl, macid, 0); + rtw_macid_ctl_set_rate_bmp0(macid_ctl, macid, 0); + rtw_macid_ctl_set_rate_bmp1(macid_ctl, macid, 0); + } + } + if (!opmode) + rtw_update_tx_rate_bmp(adapter_to_dvobj(adapter)); + +exit: + return ret; +} + +inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid) +{ + return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 0, 0); +} + +void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) +{ + struct hal_ops *pHalFunc = &padapter->hal_func; + u8 u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0}; + u8 ret = 0; + + RTW_INFO("RsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n", + rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll, + rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull, + rsvdpageloc->LocBTQosNull); + + SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp); + SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll); + SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData); + SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull); + SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull); + + ret = rtw_hal_fill_h2c_cmd(padapter, + H2C_RSVD_PAGE, + H2C_RSVDPAGE_LOC_LEN, + u1H2CRsvdPageParm); + +} + +/*#define DBG_GET_RSVD_PAGE*/ +int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, + u32 page_num, u8 *buffer, u32 buffer_size) +{ + u32 addr = 0, size = 0, count = 0; + u32 page_size = 0, data_low = 0, data_high = 0; + u16 txbndy = 0, offset = 0; + u8 i = 0; + bool rst = _FALSE; + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + + addr = page_offset * page_size; + size = page_num * page_size; + + if (buffer_size < size) { + RTW_ERR("%s buffer_size(%d) < get page total size(%d)\n", + __func__, buffer_size, size); + return rst; + } + if (rtw_halmac_dump_fifo(adapter_to_dvobj(adapter), 2, addr, size, buffer) < 0) + rst = _FALSE; + else + rst = _TRUE; + +#ifdef DBG_GET_RSVD_PAGE + RTW_INFO("%s [page_offset:%d , page_num:%d][start_addr:0x%04x , size:%d]\n", + __func__, page_offset, page_num, addr, size); + RTW_INFO_DUMP("\n", buffer, size); + RTW_INFO(" ==================================================\n"); +#endif + return rst; +} + +void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num) +{ + u32 page_size = 0; + u8 *buffer = NULL; + u32 buf_size = 0; + + if (page_num == 0) + return; + + RTW_PRINT_SEL(sel, "======= RSVG PAGE DUMP =======\n"); + RTW_PRINT_SEL(sel, "page_offset:%d, page_num:%d\n", page_offset, page_num); + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, &page_size); + if (page_size) { + buf_size = page_size * page_num; + buffer = rtw_zvmalloc(buf_size); + + if (buffer) { + rtw_hal_get_rsvd_page(adapter, page_offset, page_num, buffer, buf_size); + _RTW_DUMP_SEL(sel, buffer, buf_size); + rtw_vmfree(buffer, buf_size); + } else + RTW_PRINT_SEL(sel, "ERROR - rsvd_buf mem allocate failed\n"); + } else + RTW_PRINT_SEL(sel, "ERROR - Tx page size is zero ??\n"); + + RTW_PRINT_SEL(sel, "==========================\n"); +} + + +static void rtw_hal_construct_beacon(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 rate_len, pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + /* pmlmeext->mgnt_seq++; */ + set_frame_sub_type(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* timestamp will be inserted by hardware */ + pframe += 8; + pktlen += 8; + + /* beacon interval: 2 bytes */ + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + /* capability info: 2 bytes */ + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + /* RTW_INFO("ie len=%d\n", cur_network->IELength); */ + pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); + _rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen); + + goto _ConstructBeacon; + } + + /* below for ad-hoc mode */ + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); + + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + u32 ATIMWindow; + /* IBSS Parameter Set... */ + /* ATIMWindow = cur->Configuration.ATIMWindow; */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); + } + + /* todo: ERP IE */ + + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); + + /* todo:HT for adhoc */ + +_ConstructBeacon: + + if ((pktlen + TXDESC_SIZE) > 512) { + RTW_INFO("beacon frame too large\n"); + return; + } + + *pLength = pktlen; + + /* RTW_INFO("%s bcn_sz=%d\n", __FUNCTION__, pktlen); */ + +} + +static void rtw_hal_construct_PSPoll(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + /* Frame control. */ + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + SetPwrMgt(fctrl); + set_frame_sub_type(pframe, WIFI_PSPOLL); + + /* AID. */ + set_duration(pframe, (pmlmeinfo->aid | 0xc000)); + + /* BSSID. */ + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + /* TA. */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + + *pLength = 16; +} + +void rtw_hal_construct_NullFunctionData( + PADAPTER padapter, + u8 *pframe, + u32 *pLength, + u8 *StaAddr, + u8 bQoS, + u8 AC, + u8 bEosp, + u8 bForcePowerSave) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* RTW_INFO("%s:%d\n", __FUNCTION__, bForcePowerSave); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + if (bForcePowerSave) + SetPwrMgt(fctrl); + + switch (cur_network->network.InfrastructureMode) { + case Ndis802_11Infrastructure: + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); + break; + case Ndis802_11APMode: + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + break; + case Ndis802_11IBSS: + default: + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + break; + } + + SetSeqNum(pwlanhdr, 0); + + if (bQoS == _TRUE) { + struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; + + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); + + pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; + SetPriority(&pwlanqoshdr->qc, AC); + SetEOSP(&pwlanqoshdr->qc, bEosp); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + } else { + set_frame_sub_type(pframe, WIFI_DATA_NULL); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + } + + *pLength = pktlen; +} + +void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, + u8 *StaAddr, BOOLEAN bHideSSID) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u8 *mac, *bssid; + u32 pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + + /*RTW_INFO("%s\n", __FUNCTION__);*/ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + bssid = cur_network->MacAddress; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + set_frame_sub_type(fctrl, WIFI_PROBERSP); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += pktlen; + + if (cur_network->IELength > MAX_IE_SZ) + return; + + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pktlen += cur_network->IELength; + + *pLength = pktlen; +} + + + + +/* + * Description: Fill the reserved packets that FW will use to RSVD page. + * Now we just send 4 types packet to rsvd page. + * (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. + * Input: + * finished - FALSE:At the first time we will send all the packets as a large packet to Hw, + * so we need to set the packet length to total lengh. + * TRUE: At the second time, we should send the first packet (default:beacon) + * to Hw again and set the lengh in descriptor to the real beacon lengh. + * 2009.10.15 by tynli. + * + * Page Size = 128: 8188e, 8723a/b, 8192c/d, + * Page Size = 256: 8192e, 8821a + * Page Size = 512: 8812a + */ + +/*#define DBG_DUMP_SET_RSVD_PAGE*/ +void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished) +{ + PHAL_DATA_TYPE pHalData; + struct xmit_frame *pcmdframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + struct pwrctrl_priv *pwrctl; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct hal_ops *pHalFunc = &adapter->hal_func; + u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0; + u32 NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0; + u32 ProbeReqLength = 0, NullFunctionDataLength = 0; + u8 TxDescLen = TXDESC_SIZE, TxDescOffset = TXDESC_OFFSET; + u8 TotalPageNum = 0 , CurtPktPageNum = 0 , RsvdPageNum = 0; + u8 *ReservedPagePacket; + u16 BufIndex = 0; + u32 TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0; + RSVDPAGE_LOC RsvdPageLoc; + + struct sreset_priv *psrtpriv; + + pHalData = GET_HAL_DATA(adapter); + psrtpriv = &pHalData->srestpriv; + pxmitpriv = &adapter->xmitpriv; + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + pwrctl = adapter_to_pwrctl(adapter); + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize); + + if (PageSize == 0) { + RTW_INFO("[Error]: %s, PageSize is zero!!\n", __func__); + return; + } + + if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE) + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); + else + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); + + RTW_INFO("%s PageSize: %d, RsvdPageNUm: %d\n", __func__, PageSize, RsvdPageNum); + + MaxRsvdPageBufSize = RsvdPageNum * PageSize; + + if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) { + RTW_INFO("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)", + __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ); + rtw_warn_on(1); + return; + } + + pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + + if (pcmdframe == NULL) { + RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); + return; + } + + ReservedPagePacket = pcmdframe->buf_addr; + _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); + + /* beacon * 2 pages */ + BufIndex = TxDescOffset; + rtw_hal_construct_beacon(adapter, + &ReservedPagePacket[BufIndex], &BeaconLength); + + /* + * When we count the first page size, we need to reserve description size for the RSVD + * packet, it will be filled in front of the packet in TXPKTBUF. + */ + CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize); + /* If we don't add 1 more page, ARP offload function will fail at 8723bs.*/ + if (CurtPktPageNum == 1) + CurtPktPageNum += 1; + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum * PageSize); + + if (pwrctl->wowlan_ap_mode == _TRUE) { + /* (4) probe response*/ + RsvdPageLoc.LocProbeRsp = TotalPageNum; + rtw_hal_construct_ProbeRsp( + adapter, &ReservedPagePacket[BufIndex], + &ProbeRspLength, + get_my_bssid(&pmlmeinfo->network), _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + ProbeRspLength, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + ProbeRspLength, PageSize); + TotalPageNum += CurtPktPageNum; + TotalPacketLen = BufIndex + ProbeRspLength; + BufIndex += (CurtPktPageNum * PageSize); + goto download_page; + } + + /* ps-poll * 1 page */ + RsvdPageLoc.LocPsPoll = TotalPageNum; + RTW_INFO("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll); + rtw_hal_construct_PSPoll(adapter, + &ReservedPagePacket[BufIndex], &PSPollLength); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + PSPollLength, _TRUE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize); + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum * PageSize); + + /* BT Qos null data * 1 page */ + RsvdPageLoc.LocBTQosNull = TotalPageNum; + RTW_INFO("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull); + rtw_hal_construct_NullFunctionData( + adapter, + &ReservedPagePacket[BufIndex], + &BTQosNullLength, + get_my_bssid(&pmlmeinfo->network), + _TRUE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + BTQosNullLength, _FALSE, _TRUE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, PageSize); + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum * PageSize); + + /* null data * 1 page */ + RsvdPageLoc.LocNullData = TotalPageNum; + RTW_INFO("LocNullData: %d\n", RsvdPageLoc.LocNullData); + rtw_hal_construct_NullFunctionData( + adapter, + &ReservedPagePacket[BufIndex], + &NullDataLength, + get_my_bssid(&pmlmeinfo->network), + _FALSE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + NullDataLength, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize); + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum * PageSize); + + /* Qos null data * 1 page */ + RsvdPageLoc.LocQosNull = TotalPageNum; + RTW_INFO("LocQosNull: %d\n", RsvdPageLoc.LocQosNull); + rtw_hal_construct_NullFunctionData( + adapter, + &ReservedPagePacket[BufIndex], + &QosNullLength, + get_my_bssid(&pmlmeinfo->network), + _TRUE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex - TxDescLen], + QosNullLength, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, PageSize); + + TotalPageNum += CurtPktPageNum; + + TotalPacketLen = BufIndex + QosNullLength; + + BufIndex += (CurtPktPageNum * PageSize); + + + + +download_page: + /* RTW_INFO("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/ + RTW_INFO("%s PageNum(%d), pktlen(%d)\n", + __func__, TotalPageNum, TotalPacketLen); + + + if (TotalPacketLen > MaxRsvdPageBufSize) { + RTW_ERR("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", + __FUNCTION__, TotalPacketLen, MaxRsvdPageBufSize); + rtw_warn_on(1); + goto error; + } else { + /* update attribute */ + pattrib = &pcmdframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + pattrib->qsel = QSLT_BEACON; + pattrib->pktlen = TotalPacketLen - TxDescOffset; + pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset; + dump_mgntframe(adapter, pcmdframe); + } + + RTW_INFO("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n", + __func__, TotalPacketLen, TotalPageNum); +#ifdef DBG_DUMP_SET_RSVD_PAGE + RTW_INFO(" ==================================================\n"); + RTW_INFO_DUMP("\n", ReservedPagePacket, TotalPacketLen); + RTW_INFO(" ==================================================\n"); +#endif + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc); + } else if (pwrctl->wowlan_pno_enable) { + } + return; +error: + rtw_free_xmitframe(pxmitpriv, pcmdframe); +} +static void rtw_hal_set_hw_update_tsf(PADAPTER padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + + if (!pmlmeext->en_hw_update_tsf) + return; + + /* check REG_RCR bit is set */ + if (!(rtw_read32(padapter, REG_RCR) & RCR_CBSSID_BCN)) + return; + + /* enable hw update tsf function for non-AP */ + if (rtw_linked_check(padapter) && + check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) { + rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) & (~DIS_TSF_UDT)); + } + pmlmeext->en_hw_update_tsf = _FALSE; +} + + + +void SetHwReg(_adapter *adapter, u8 variable, u8 *val) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + switch (variable) { + case HW_VAR_MEDIA_STATUS: { + u8 net_type = *((u8 *)val); + + rtw_hal_set_msr(adapter, net_type); + } + break; + case HW_VAR_MAC_ADDR: + rtw_hal_set_macaddr_port(adapter, val); + break; + case HW_VAR_BSSID: + rtw_hal_set_bssid(adapter, val); + break; + case HW_VAR_PORT_SWITCH: + hw_var_port_switch(adapter); + break; + case HW_VAR_INIT_RTS_RATE: { + u16 brate_cfg = *((u16 *)val); + u8 rate_index = 0; + HAL_VERSION *hal_ver = &hal_data->version_id; + + if (IS_8188E(*hal_ver)) { + + while (brate_cfg > 0x1) { + brate_cfg = (brate_cfg >> 1); + rate_index++; + } + rtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index); + } else + rtw_warn_on(1); + } + break; + case HW_VAR_SEC_CFG: { + u16 reg_scr_ori; + u16 reg_scr; + + reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG); + reg_scr |= (SCR_CHK_KEYID | SCR_RxDecEnable | SCR_TxEncEnable); + + if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC)) + reg_scr |= SCR_CHK_BMC; + + if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH)) + reg_scr |= SCR_NoSKMC; + + if (reg_scr != reg_scr_ori) + rtw_write16(adapter, REG_SECCFG, reg_scr); + } + break; + case HW_VAR_SEC_DK_CFG: { + struct security_priv *sec = &adapter->securitypriv; + u8 reg_scr = rtw_read8(adapter, REG_SECCFG); + + if (val) { /* Enable default key related setting */ + reg_scr |= SCR_TXBCUSEDK; + if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X) + reg_scr |= (SCR_RxUseDK | SCR_TxUseDK); + } else /* Disable default key related setting */ + reg_scr &= ~(SCR_RXBCUSEDK | SCR_TXBCUSEDK | SCR_RxUseDK | SCR_TxUseDK); + + rtw_write8(adapter, REG_SECCFG, reg_scr); + } + break; + + case HW_VAR_ASIX_IOT: + /* enable ASIX IOT function */ + if (*((u8 *)val) == _TRUE) { + /* 0xa2e[0]=0 (disable rake receiver) */ + rtw_write8(adapter, rCCK0_FalseAlarmReport + 2, + rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) & ~(BIT0)); + /* 0xa1c=0xa0 (reset channel estimation if signal quality is bad) */ + rtw_write8(adapter, rCCK0_DSPParameter2, 0xa0); + } else { + /* restore reg:0xa2e, reg:0xa1c */ + rtw_write8(adapter, rCCK0_FalseAlarmReport + 2, + rtw_read8(adapter, rCCK0_FalseAlarmReport + 2) | (BIT0)); + rtw_write8(adapter, rCCK0_DSPParameter2, 0x00); + } + break; + + case HW_VAR_EN_HW_UPDATE_TSF: + rtw_hal_set_hw_update_tsf(adapter); + break; + + case HW_VAR_APFM_ON_MAC: + hal_data->bMacPwrCtrlOn = *val; + RTW_INFO("%s: bMacPwrCtrlOn=%d\n", __func__, hal_data->bMacPwrCtrlOn); + break; + + default: + if (0) + RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n", + FUNC_ADPT_ARG(adapter), variable); + break; + } + +} + +void GetHwReg(_adapter *adapter, u8 variable, u8 *val) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + switch (variable) { + case HW_VAR_BASIC_RATE: + *((u16 *)val) = hal_data->BasicRateSet; + break; + case HW_VAR_RF_TYPE: + *((u8 *)val) = hal_data->rf_type; + break; + case HW_VAR_MEDIA_STATUS: + rtw_hal_get_msr(adapter, val); + break; + case HW_VAR_DO_IQK: + *val = hal_data->bNeedIQK; + break; + case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO: + if (hal_is_band_support(adapter, BAND_ON_5G)) + *val = _TRUE; + else + *val = _FALSE; + break; + case HW_VAR_APFM_ON_MAC: + *val = hal_data->bMacPwrCtrlOn; + break; + default: + if (0) + RTW_PRINT(FUNC_ADPT_FMT" variable(%d) not defined!\n", + FUNC_ADPT_ARG(adapter), variable); + break; + } + +} + +u8 +SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bResult = _SUCCESS; + + switch (variable) { + + case HAL_DEF_DBG_DUMP_RXPKT: + hal_data->bDumpRxPkt = *((u8 *)value); + break; + case HAL_DEF_DBG_DUMP_TXPKT: + hal_data->bDumpTxPkt = *((u8 *)value); + break; + case HAL_DEF_ANT_DETECT: + hal_data->AntDetection = *((u8 *)value); + break; + case HAL_DEF_DBG_DIS_PWT: + hal_data->bDisableTXPowerTraining = *((u8 *)value); + break; + default: + RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); + bResult = _FAIL; + break; + } + + return bResult; +} + + +u8 +GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bResult = _SUCCESS; + + switch (variable) { + case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: { + struct mlme_priv *pmlmepriv; + struct sta_priv *pstapriv; + struct sta_info *psta; + + pmlmepriv = &adapter->mlmepriv; + pstapriv = &adapter->stapriv; + psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); + if (psta) + *((int *)value) = psta->rssi_stat.undecorated_smoothed_pwdb; + } + break; + case HAL_DEF_DBG_DUMP_RXPKT: + *((u8 *)value) = hal_data->bDumpRxPkt; + break; + case HAL_DEF_DBG_DUMP_TXPKT: + *((u8 *)value) = hal_data->bDumpTxPkt; + break; + case HAL_DEF_ANT_DETECT: + *((u8 *)value) = hal_data->AntDetection; + break; + case HAL_DEF_MACID_SLEEP: + *(u8 *)value = _FALSE; + break; + case HAL_DEF_TX_PAGE_SIZE: + *((u32 *)value) = PAGE_SIZE_128; + break; + case HAL_DEF_DBG_DIS_PWT: + *(u8 *)value = hal_data->bDisableTXPowerTraining; + break; + case HAL_DEF_EXPLICIT_BEAMFORMER: + case HAL_DEF_EXPLICIT_BEAMFORMEE: + case HAL_DEF_VHT_MU_BEAMFORMER: + case HAL_DEF_VHT_MU_BEAMFORMEE: + *(u8 *)value = _FALSE; + break; + default: + RTW_PRINT("%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); + bResult = _FAIL; + break; + } + + return bResult; +} + +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; + /* _irqL irqL; */ + switch (eVariable) { + case HAL_ODM_STA_INFO: { + struct sta_info *psta = (struct sta_info *)pValue1; + if (bSet) { + RTW_INFO("### Set STA_(%d) info ###\n", psta->mac_id); + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta); + } else { + RTW_INFO("### Clean STA_(%d) info ###\n", psta->mac_id); + /* _enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + psta->rssi_level = 0; + odm_cmn_info_ptr_array_hook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL); + + /* _exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); */ + } + } + break; + case HAL_ODM_P2P_STATE: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet); + break; + case HAL_ODM_WIFI_DISPLAY_STATE: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet); + break; + case HAL_ODM_REGULATION: + odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); + odm_cmn_info_init(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); + break; + + case HAL_ODM_INITIAL_GAIN: { + u8 rx_gain = *((u8 *)(pValue1)); + /*printk("rx_gain:%x\n",rx_gain);*/ + if (rx_gain == 0xff) {/*restore rx gain*/ + /*odm_write_dig(podmpriv,pDigTable->backup_ig_value);*/ + odm_pause_dig(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); + } else { + /*pDigTable->backup_ig_value = pDigTable->cur_ig_value;*/ + /*odm_write_dig(podmpriv,rx_gain);*/ + odm_pause_dig(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); + } + } + break; + case HAL_ODM_FA_CNT_DUMP: + if (*((u8 *)pValue1)) + podmpriv->debug_components |= (ODM_COMP_DIG | ODM_COMP_FA_CNT); + else + podmpriv->debug_components &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT); + break; + case HAL_ODM_DBG_FLAG: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1)); + break; + case HAL_ODM_DBG_LEVEL: + odm_cmn_info_update(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1)); + break; + case HAL_ODM_RX_INFO_DUMP: { + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(podmpriv , PHYDM_FALSEALMCNT); + struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; + void *sel; + + sel = pValue1; + + _RTW_PRINT_SEL(sel , "============ Rx Info dump ===================\n"); + _RTW_PRINT_SEL(sel , "is_linked = %d, rssi_min = %d(%%), current_igi = 0x%x\n", podmpriv->is_linked, podmpriv->rssi_min, pDM_DigTable->cur_ig_value); + _RTW_PRINT_SEL(sel , "cnt_cck_fail = %d, cnt_ofdm_fail = %d, Total False Alarm = %d\n", false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all); + + if (podmpriv->is_linked) { + _RTW_PRINT_SEL(sel , "rx_rate = %s", HDATA_RATE(podmpriv->rx_rate)); + _RTW_PRINT_SEL(sel , " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B); + rtw_dump_raw_rssi_info(Adapter, sel); + } + } + break; + case HAL_ODM_RX_Dframe_INFO: { + void *sel; + + sel = pValue1; + + /*_RTW_PRINT_SEL(sel , "HAL_ODM_RX_Dframe_INFO\n");*/ + } + break; + + + default: + break; + } +} + +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; + + switch (eVariable) { + case HAL_ODM_DBG_FLAG: + *((u8Byte *)pValue1) = podmpriv->debug_components; + break; + case HAL_ODM_DBG_LEVEL: + *((u4Byte *)pValue1) = podmpriv->debug_level; + break; + + case HAL_ODM_INITIAL_GAIN: { + struct _dynamic_initial_gain_threshold_ *pDM_DigTable = &podmpriv->dm_dig_table; + *((u8 *)pValue1) = pDM_DigTable->cur_ig_value; + } + break; + default: + break; + } +} + +u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *podmpriv = &pHalData->odmpriv; + u32 result = 0; + + switch (ops) { + case HAL_PHYDM_DIS_ALL_FUNC: + podmpriv->support_ability = DYNAMIC_FUNC_DISABLE; + break; + case HAL_PHYDM_FUNC_SET: + podmpriv->support_ability |= ability; + break; + case HAL_PHYDM_FUNC_CLR: + podmpriv->support_ability &= ~(ability); + break; + case HAL_PHYDM_ABILITY_BK: + /* dm flag backup*/ + podmpriv->bk_support_ability = podmpriv->support_ability; + break; + case HAL_PHYDM_ABILITY_RESTORE: + /* restore dm flag */ + podmpriv->support_ability = podmpriv->bk_support_ability; + break; + case HAL_PHYDM_ABILITY_SET: + podmpriv->support_ability = ability; + break; + case HAL_PHYDM_ABILITY_GET: + result = podmpriv->support_ability; + break; + } + return result; +} + +BOOLEAN +eqNByte( + u8 *str1, + u8 *str2, + u32 num +) +{ + if (num == 0) + return _FALSE; + while (num > 0) { + num--; + if (str1[num] != str2[num]) + return _FALSE; + } + return _TRUE; +} + +/* + * Description: + * Translate a character to hex digit. + * */ +u32 +MapCharToHexDigit( + IN char chTmp +) +{ + if (chTmp >= '0' && chTmp <= '9') + return chTmp - '0'; + else if (chTmp >= 'a' && chTmp <= 'f') + return 10 + (chTmp - 'a'); + else if (chTmp >= 'A' && chTmp <= 'F') + return 10 + (chTmp - 'A'); + else + return 0; +} + +/* + * Description: + * Parse hex number from the string pucStr. + * */ +BOOLEAN +GetHexValueFromString( + IN char *szStr, + IN OUT u32 *pu4bVal, + IN OUT u32 *pu4bMove +) +{ + char *szScan = szStr; + + /* Check input parameter. */ + if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) { + RTW_INFO("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove); + return _FALSE; + } + + /* Initialize output. */ + *pu4bMove = 0; + *pu4bVal = 0; + + /* Skip leading space. */ + while (*szScan != '\0' && + (*szScan == ' ' || *szScan == '\t')) { + szScan++; + (*pu4bMove)++; + } + + /* Skip leading '0x' or '0X'. */ + if (*szScan == '0' && (*(szScan + 1) == 'x' || *(szScan + 1) == 'X')) { + szScan += 2; + (*pu4bMove) += 2; + } + + /* Check if szScan is now pointer to a character for hex digit, */ + /* if not, it means this is not a valid hex number. */ + if (!IsHexDigit(*szScan)) + return _FALSE; + + /* Parse each digit. */ + do { + (*pu4bVal) <<= 4; + *pu4bVal += MapCharToHexDigit(*szScan); + + szScan++; + (*pu4bMove)++; + } while (IsHexDigit(*szScan)); + + return _TRUE; +} + +BOOLEAN +GetFractionValueFromString( + IN char *szStr, + IN OUT u8 *pInteger, + IN OUT u8 *pFraction, + IN OUT u32 *pu4bMove +) +{ + char *szScan = szStr; + + /* Initialize output. */ + *pu4bMove = 0; + *pInteger = 0; + *pFraction = 0; + + /* Skip leading space. */ + while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) { + ++szScan; + ++(*pu4bMove); + } + + /* Parse each digit. */ + do { + (*pInteger) *= 10; + *pInteger += (*szScan - '0'); + + ++szScan; + ++(*pu4bMove); + + if (*szScan == '.') { + ++szScan; + ++(*pu4bMove); + + if (*szScan < '0' || *szScan > '9') + return _FALSE; + else { + *pFraction = *szScan - '0'; + ++szScan; + ++(*pu4bMove); + return _TRUE; + } + } + } while (*szScan >= '0' && *szScan <= '9'); + + return _TRUE; +} + +/* + * Description: + * Return TRUE if szStr is comment out with leading " */ /* ". + * */ +BOOLEAN +IsCommentString( + IN char *szStr +) +{ + if (*szStr == '/' && *(szStr + 1) == '/') + return _TRUE; + else + return _FALSE; +} + +BOOLEAN +GetU1ByteIntegerFromStringInDecimal( + IN char *Str, + IN OUT u8 *pInt +) +{ + u16 i = 0; + *pInt = 0; + + while (Str[i] != '\0') { + if (Str[i] >= '0' && Str[i] <= '9') { + *pInt *= 10; + *pInt += (Str[i] - '0'); + } else + return _FALSE; + ++i; + } + + return _TRUE; +} + +/* <20121004, Kordan> For example, + * ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from a string "Hello [Kordan]". + * If RightQualifier does not exist, it will hang on in the while loop */ +BOOLEAN +ParseQualifiedString( + IN char *In, + IN OUT u32 *Start, + OUT char *Out, + IN char LeftQualifier, + IN char RightQualifier +) +{ + u32 i = 0, j = 0; + char c = In[(*Start)++]; + + if (c != LeftQualifier) + return _FALSE; + + i = (*Start); + while ((c = In[(*Start)++]) != RightQualifier) + ; /* find ']' */ + j = (*Start) - 2; + strncpy((char *)Out, (const char *)(In + i), j - i + 1); + + return _TRUE; +} + +BOOLEAN +isAllSpaceOrTab( + u8 *data, + u8 size +) +{ + u8 cnt = 0, NumOfSpaceAndTab = 0; + + while (size > cnt) { + if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0') + ++NumOfSpaceAndTab; + + ++cnt; + } + + return size == NumOfSpaceAndTab; +} + +void linked_info_dump(_adapter *padapter, u8 benable) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (padapter->bLinkInfoDump == benable) + return; + + RTW_INFO("%s %s\n", __FUNCTION__, (benable) ? "enable" : "disable"); + + if (benable) { + pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */ + rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + + pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */ + rtw_pm_set_ips(padapter, IPS_NONE); + } else { + rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode); + + rtw_pm_set_lps(padapter, pwrctrlpriv->org_power_mgnt); + } + padapter->bLinkInfoDump = benable ; +} + +void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel) +{ + u8 isCCKrate, rf_path; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; + _RTW_PRINT_SEL(sel, "============ RAW Rx Info dump ===================\n"); + _RTW_PRINT_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n", HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all); + + isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? TRUE : FALSE; + + if (isCCKrate) + psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball; + + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { + _RTW_PRINT_SEL(sel , "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)" + , rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]); + + if (!isCCKrate) + _RTW_PRINT_SEL(sel , ",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n", psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]); + else + _RTW_PRINT_SEL(sel , "\n"); + + } +} + +void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) +{ + u8 isCCKrate, rf_path , dframe_type; + u8 *ptr; + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct recv_priv *precvpriv = &(padapter->recvpriv); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct sta_info *psta = prframe->u.hdr.psta; + struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)(&pattrib->phy_info); + struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; + psample_pkt_rssi->data_rate = pattrib->data_rate; + ptr = prframe->u.hdr.rx_data; + dframe_type = GetFrameType(ptr); + /*RTW_INFO("=>%s\n", __FUNCTION__);*/ + + if (precvpriv->store_law_data_flag) { + isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? TRUE : FALSE; + + psample_pkt_rssi->pwdball = p_phy_info->rx_pwdb_all; + psample_pkt_rssi->pwr_all = p_phy_info->recv_signal_power; + + for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) { + psample_pkt_rssi->mimo_signal_strength[rf_path] = p_phy_info->rx_mimo_signal_strength[rf_path]; + psample_pkt_rssi->mimo_signal_quality[rf_path] = p_phy_info->rx_mimo_signal_quality[rf_path]; + if (!isCCKrate) { + psample_pkt_rssi->ofdm_pwr[rf_path] = p_phy_info->rx_pwr[rf_path]; + psample_pkt_rssi->ofdm_snr[rf_path] = p_phy_info->rx_snr[rf_path]; + } + } + } + +} + +int check_phy_efuse_tx_power_info_valid(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 *pContent = pHalData->efuse_eeprom_data; + int index = 0; + u16 tx_index_offset = 0x0000; + + switch (rtw_get_chip_type(padapter)) { + case RTL8723B: + tx_index_offset = EEPROM_TX_PWR_INX_8723B; + break; + case RTL8703B: + tx_index_offset = EEPROM_TX_PWR_INX_8703B; + break; + case RTL8723D: + tx_index_offset = EEPROM_TX_PWR_INX_8723D; + break; + case RTL8188E: + tx_index_offset = EEPROM_TX_PWR_INX_88E; + break; + case RTL8188F: + tx_index_offset = EEPROM_TX_PWR_INX_8188F; + break; + case RTL8192E: + tx_index_offset = EEPROM_TX_PWR_INX_8192E; + break; + case RTL8821: + tx_index_offset = EEPROM_TX_PWR_INX_8821; + break; + case RTL8812: + tx_index_offset = EEPROM_TX_PWR_INX_8812; + break; + case RTL8814A: + tx_index_offset = EEPROM_TX_PWR_INX_8814; + break; + case RTL8822B: + tx_index_offset = EEPROM_TX_PWR_INX_8822B; + break; + case RTL8821C: + tx_index_offset = EEPROM_TX_PWR_INX_8821C; + break; + default: + tx_index_offset = 0x0010; + break; + } + + /* TODO: chacking length by ICs */ + for (index = 0 ; index < 11 ; index++) { + if (pContent[tx_index_offset + index] == 0xFF) + return _FALSE; + } + return _TRUE; +} + +int hal_efuse_macaddr_offset(_adapter *adapter) +{ + u8 interface_type = 0; + int addr_offset = -1; + + interface_type = rtw_get_intf_type(adapter); + + switch (rtw_get_chip_type(adapter)) { + + case RTL8821C: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8821CU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8821CS; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_8821CE; + break; + } + + if (addr_offset == -1) { + RTW_ERR("%s: unknown combination - chip_type:%u, interface:%u\n" + , __func__, rtw_get_chip_type(adapter), rtw_get_intf_type(adapter)); + } + + return addr_offset; +} + +int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr) +{ + int ret = _FAIL; + int addr_offset; + + addr_offset = hal_efuse_macaddr_offset(padapter); + if (addr_offset == -1) + goto exit; + + ret = rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr); + +exit: + return ret; +} + +void rtw_dump_cur_efuse(PADAPTER padapter) +{ + int i =0; + int mapsize =0; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapsize, _FALSE); + + if (mapsize <= 0 || mapsize > EEPROM_MAX_SIZE) { + RTW_ERR("wrong map size %d\n", mapsize); + return; + } + + if (hal_data->efuse_file_status == EFUSE_FILE_LOADED) + RTW_INFO("EFUSE FILE\n"); + else + RTW_INFO("HW EFUSE\n"); + + for (i = 0; i < mapsize; i++) { + if (i % 16 == 0) + RTW_PRINT_SEL(RTW_DBGDUMP, "0x%03x: ", i); + + _RTW_PRINT_SEL(RTW_DBGDUMP, "%02X%s" + , hal_data->efuse_eeprom_data[i] + , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") + ); + } + _RTW_PRINT_SEL(RTW_DBGDUMP, "\n"); +} + +int hal_config_macaddr(_adapter *adapter, bool autoload_fail) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 addr[ETH_ALEN]; + int addr_offset = hal_efuse_macaddr_offset(adapter); + u8 *hw_addr = NULL; + int ret = _SUCCESS; + + if (autoload_fail) + goto bypass_hw_pg; + + if (addr_offset != -1) + hw_addr = &hal_data->efuse_eeprom_data[addr_offset]; + + /* if the hw_addr is written by efuse file, set to NULL */ + if (hal_data->efuse_file_status == EFUSE_FILE_LOADED) + hw_addr = NULL; + + if (!hw_addr) { + /* try getting hw pg data */ + if (Hal_GetPhyEfuseMACAddr(adapter, addr) == _SUCCESS) + hw_addr = addr; + } + + /* check hw pg data */ + if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) { + _rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN); + goto exit; + } + +bypass_hw_pg: + + _rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN); + ret = _FAIL; + +exit: + return ret; +} + +/* To avoid RX affect TX throughput */ +void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct registry_priv *registry_par = &padapter->registrypriv; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 cur_wireless_mode = WIRELESS_INVALID; +} + +s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 i; + + for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) { + if ((pHalData->iqk_reg_backup[i].central_chnl != 0)) { + if ((pHalData->iqk_reg_backup[i].central_chnl == central_chnl) + && (pHalData->iqk_reg_backup[i].bw_mode == bw_mode)) + return i; + } + } + + return -1; +} + +void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter) +{ + u32 mac_cck_ok = 0, mac_ofdm_ok = 0, mac_ht_ok = 0, mac_vht_ok = 0; + u32 mac_cck_err = 0, mac_ofdm_err = 0, mac_ht_err = 0, mac_vht_err = 0; + u32 mac_cck_fa = 0, mac_ofdm_fa = 0, mac_ht_fa = 0; + u32 DropPacket = 0; + + if (!rx_counter) { + rtw_warn_on(1); + return; + } + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ + + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x3); + mac_cck_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0); + mac_ofdm_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x6); + mac_ht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + mac_vht_ok = 0; + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x0); + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1); + mac_vht_ok = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ + } + + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x4); + mac_cck_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1); + mac_ofdm_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x7); + mac_ht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + mac_vht_err = 0; + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x1); + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x1); + mac_vht_err = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0]*/ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT26, 0x0);/*clear bit-26*/ + } + + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x5); + mac_cck_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x2); + mac_ofdm_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT28 | BIT29 | BIT30 | BIT31, 0x9); + mac_ht_fa = phy_query_mac_reg(padapter, REG_RXERR_RPT, bMaskLWord);/* [15:0] */ + + /* Mac_DropPacket */ + rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT) & 0x0FFFFFFF) | Mac_DropPacket); + DropPacket = rtw_read32(padapter, REG_RXERR_RPT) & 0x0000FFFF; + + rx_counter->rx_pkt_ok = mac_cck_ok + mac_ofdm_ok + mac_ht_ok + mac_vht_ok; + rx_counter->rx_pkt_crc_error = mac_cck_err + mac_ofdm_err + mac_ht_err + mac_vht_err; + rx_counter->rx_cck_fa = mac_cck_fa; + rx_counter->rx_ofdm_fa = mac_ofdm_fa; + rx_counter->rx_ht_fa = mac_ht_fa; + rx_counter->rx_pkt_drop = DropPacket; +} +void rtw_reset_mac_rx_counters(_adapter *padapter) +{ + + /* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/ + if (IS_HARDWARE_TYPE_8703B(padapter) || + IS_HARDWARE_TYPE_8723D(padapter) || + IS_HARDWARE_TYPE_8188F(padapter)) + phy_set_mac_reg(padapter, REG_RCR, BIT19, 0x1); + + /* reset mac counter */ + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x1); + phy_set_mac_reg(padapter, REG_RXERR_RPT, BIT27, 0x0); +} + +void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter) +{ + u32 cckok = 0, cckcrc = 0, ofdmok = 0, ofdmcrc = 0, htok = 0, htcrc = 0, OFDM_FA = 0, CCK_FA = 0, vht_ok = 0, vht_err = 0; + if (!rx_counter) { + rtw_warn_on(1); + return; + } + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + cckok = phy_query_bb_reg(padapter, 0xF04, 0x3FFF); /* [13:0] */ + ofdmok = phy_query_bb_reg(padapter, 0xF14, 0x3FFF); /* [13:0] */ + htok = phy_query_bb_reg(padapter, 0xF10, 0x3FFF); /* [13:0] */ + vht_ok = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF); /* [13:0] */ + cckcrc = phy_query_bb_reg(padapter, 0xF04, 0x3FFF0000); /* [29:16] */ + ofdmcrc = phy_query_bb_reg(padapter, 0xF14, 0x3FFF0000); /* [29:16] */ + htcrc = phy_query_bb_reg(padapter, 0xF10, 0x3FFF0000); /* [29:16] */ + vht_err = phy_query_bb_reg(padapter, 0xF0C, 0x3FFF0000); /* [29:16] */ + CCK_FA = phy_query_bb_reg(padapter, 0xA5C, bMaskLWord); + OFDM_FA = phy_query_bb_reg(padapter, 0xF48, bMaskLWord); + } else { + cckok = phy_query_bb_reg(padapter, 0xF88, bMaskDWord); + ofdmok = phy_query_bb_reg(padapter, 0xF94, bMaskLWord); + htok = phy_query_bb_reg(padapter, 0xF90, bMaskLWord); + vht_ok = 0; + cckcrc = phy_query_bb_reg(padapter, 0xF84, bMaskDWord); + ofdmcrc = phy_query_bb_reg(padapter, 0xF94, bMaskHWord); + htcrc = phy_query_bb_reg(padapter, 0xF90, bMaskHWord); + vht_err = 0; + OFDM_FA = phy_query_bb_reg(padapter, 0xCF0, bMaskLWord) + phy_query_bb_reg(padapter, 0xCF2, bMaskLWord) + + phy_query_bb_reg(padapter, 0xDA2, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA4, bMaskLWord) + + phy_query_bb_reg(padapter, 0xDA6, bMaskLWord) + phy_query_bb_reg(padapter, 0xDA8, bMaskLWord); + + CCK_FA = (rtw_read8(padapter, 0xA5B) << 8) | (rtw_read8(padapter, 0xA5C)); + } + + rx_counter->rx_pkt_ok = cckok + ofdmok + htok + vht_ok; + rx_counter->rx_pkt_crc_error = cckcrc + ofdmcrc + htcrc + vht_err; + rx_counter->rx_ofdm_fa = OFDM_FA; + rx_counter->rx_cck_fa = CCK_FA; + +} + +void rtw_reset_phy_trx_ok_counters(_adapter *padapter) +{ + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + phy_set_bb_reg(padapter, 0xB58, BIT0, 0x1); + phy_set_bb_reg(padapter, 0xB58, BIT0, 0x0); + } +} +void rtw_reset_phy_rx_counters(_adapter *padapter) +{ + /* reset phy counter */ + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + rtw_reset_phy_trx_ok_counters(padapter); + + phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x1);/* reset OFDA FA counter */ + phy_set_bb_reg(padapter, 0x9A4, BIT17, 0x0); + + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */ + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1); + } else { + phy_set_bb_reg(padapter, 0xF14, BIT16, 0x1); + rtw_msleep_os(10); + phy_set_bb_reg(padapter, 0xF14, BIT16, 0x0); + + phy_set_bb_reg(padapter, 0xD00, BIT27, 0x1);/* reset OFDA FA counter */ + phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x1);/* reset OFDA FA counter */ + phy_set_bb_reg(padapter, 0xD00, BIT27, 0x0); + phy_set_bb_reg(padapter, 0xC0C, BIT31, 0x0); + + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x0);/* reset CCK FA counter */ + phy_set_bb_reg(padapter, 0xA2C, BIT15, 0x1); + } +} +void rtw_get_noise(_adapter *padapter) +{ + +} + +void update_IOT_info(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + switch (pmlmeinfo->assoc_AP_vendor) { + case HT_IOT_PEER_MARVELL: + pmlmeinfo->turboMode_cts2self = 1; + pmlmeinfo->turboMode_rtsen = 0; + break; + + case HT_IOT_PEER_RALINK: + pmlmeinfo->turboMode_cts2self = 0; + pmlmeinfo->turboMode_rtsen = 1; + /* disable high power */ + rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); + break; + case HT_IOT_PEER_REALTEK: + /* rtw_write16(padapter, 0x4cc, 0xffff); */ + /* rtw_write16(padapter, 0x546, 0x01c0); */ + /* disable high power */ + rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); + break; + default: + pmlmeinfo->turboMode_cts2self = 0; + pmlmeinfo->turboMode_rtsen = 1; + break; + } + +} + +/* TODO: merge with phydm, see odm_SetCrystalCap() */ +void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) +{ + crystal_cap = crystal_cap & 0x3F; + + switch (rtw_get_chip_type(adapter)) { + + case RTL8822B: + case RTL8821C: + /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */ + crystal_cap = crystal_cap & 0x3F; + phy_set_bb_reg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap); + phy_set_bb_reg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap); + break; + default: + rtw_warn_on(1); + } +} + +int hal_spec_init(_adapter *adapter) +{ + u8 interface_type = 0; + int ret = _SUCCESS; + + interface_type = rtw_get_intf_type(adapter); + + switch (rtw_get_chip_type(adapter)) { + case RTL8821C: + init_hal_spec_rtl8821c(adapter); + break; + default: + RTW_ERR("%s: unknown chip_type:%u\n" + , __func__, rtw_get_chip_type(adapter)); + ret = _FAIL; + break; + } + + return ret; +} + +static const char *const _band_cap_str[] = { + /* BIT0 */"2G", + /* BIT1 */"5G", +}; + +static const char *const _bw_cap_str[] = { + /* BIT0 */"5M", + /* BIT1 */"10M", + /* BIT2 */"20M", + /* BIT3 */"40M", + /* BIT4 */"80M", + /* BIT5 */"160M", + /* BIT6 */"80_80M", +}; + +static const char *const _proto_cap_str[] = { + /* BIT0 */"b", + /* BIT1 */"g", + /* BIT2 */"n", + /* BIT3 */"ac", +}; + +static const char *const _wl_func_str[] = { + /* BIT0 */"P2P", + /* BIT1 */"MIRACAST", + /* BIT2 */"TDLS", + /* BIT3 */"FTM", +}; + +inline bool hal_chk_band_cap(_adapter *adapter, u8 cap) +{ + return GET_HAL_SPEC(adapter)->band_cap & cap; +} + +inline bool hal_chk_bw_cap(_adapter *adapter, u8 cap) +{ + return GET_HAL_SPEC(adapter)->bw_cap & cap; +} + +inline bool hal_chk_proto_cap(_adapter *adapter, u8 cap) +{ + return GET_HAL_SPEC(adapter)->proto_cap & cap; +} + +inline bool hal_chk_wl_func(_adapter *adapter, u8 func) +{ + return GET_HAL_SPEC(adapter)->wl_func & func; +} + +inline bool hal_is_band_support(_adapter *adapter, u8 band) +{ + return GET_HAL_SPEC(adapter)->band_cap & band_to_band_cap(band); +} + +inline bool hal_is_bw_support(_adapter *adapter, u8 bw) +{ + return GET_HAL_SPEC(adapter)->bw_cap & ch_width_to_bw_cap(bw); +} + +/* +* hal_largest_bw - starting from in_bw, get largest bw supported by HAL +* @adapter: +* @in_bw: starting bw, value of CHANNEL_WIDTH +* +* Returns: value of CHANNEL_WIDTH +*/ +u8 hal_largest_bw(_adapter *adapter, u8 in_bw) +{ + for (; in_bw > CHANNEL_WIDTH_20; in_bw--) { + if (hal_is_bw_support(adapter, in_bw)) + break; + } + + if (!hal_is_bw_support(adapter, in_bw)) + rtw_warn_on(1); + + return in_bw; +} + +void ResumeTxBeacon(_adapter *padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ + /* which should be read from register to a global variable. */ + + pHalData->RegFwHwTxQCtrl |= BIT(6); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff); + pHalData->RegReg542 |= BIT(0); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); +} + +void StopTxBeacon(_adapter *padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ + /* which should be read from register to a global variable. */ + + pHalData->RegFwHwTxQCtrl &= ~BIT(6); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64); + pHalData->RegReg542 &= ~BIT(0); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); + + /*CheckFwRsvdPageContent(padapter);*/ /* 2010.06.23. Added by tynli. */ +} diff --git a/drivers/staging/rtl8821ce/hal/hal_com_c2h.h b/drivers/staging/rtl8821ce/hal/hal_com_c2h.h new file mode 100644 index 000000000000..2eae435d4cf2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_com_c2h.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __COMMON_C2H_H__ +#define __COMMON_C2H_H__ + +#define C2H_TYPE_REG 0 +#define C2H_TYPE_PKT 1 + +/* +* C2H event format: +* Fields TRIGGER PAYLOAD SEQ PLEN ID +* BITS [127:120] [119:16] [15:8] [7:4] [3:0] +*/ +#define C2H_ID(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 4) +#define C2H_PLEN(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 4, 4) +#define C2H_SEQ(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8) +#define C2H_PAYLOAD(_c2h) (((u8*)(_c2h)) + 2) + +#define SET_C2H_ID(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 4, _val) +#define SET_C2H_PLEN(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 4, 4, _val) +#define SET_C2H_SEQ(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1 , 0, 8, _val) + +/* +* C2H event format: +* Fields TRIGGER PLEN PAYLOAD SEQ ID +* BITS [127:120] [119:112] [111:16] [15:8] [7:0] +*/ +#define C2H_ID_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)), 0, 8) +#define C2H_SEQ_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 1, 0, 8) +#define C2H_PAYLOAD_88XX(_c2h) (((u8*)(_c2h)) + 2) +#define C2H_PLEN_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 14, 0, 8) +#define C2H_TRIGGER_88XX(_c2h) LE_BITS_TO_1BYTE(((u8*)(_c2h)) + 15, 0, 8) + +#define SET_C2H_ID_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)), 0, 8, _val) +#define SET_C2H_SEQ_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 1, 0, 8, _val) +#define SET_C2H_PLEN_88XX(_c2h, _val) SET_BITS_TO_LE_1BYTE(((u8*)(_c2h)) + 14, 0, 8, _val) + +typedef enum _C2H_EVT { + C2H_DBG = 0x00, + C2H_LB = 0x01, + C2H_TXBF = 0x02, + C2H_CCX_TX_RPT = 0x03, + C2H_AP_REQ_TXRPT = 0x04, + C2H_FW_SCAN_COMPLETE = 0x7, + C2H_BT_INFO = 0x09, + C2H_BT_MP_INFO = 0x0B, + C2H_RA_RPT = 0x0C, + C2H_SPC_STAT = 0x0D, + C2H_RA_PARA_RPT = 0x0E, + C2H_FW_CHNL_SWITCH_COMPLETE = 0x10, + C2H_IQK_FINISH = 0x11, + C2H_MAILBOX_STATUS = 0x15, + C2H_P2P_RPORT = 0x16, + C2H_MCC = 0x17, + C2H_MAC_HIDDEN_RPT = 0x19, + C2H_MAC_HIDDEN_RPT_2 = 0x1A, + C2H_BCN_EARLY_RPT = 0x1E, + C2H_DEFEATURE_DBG = 0x22, + C2H_CUSTOMER_STR_RPT = 0x24, + C2H_CUSTOMER_STR_RPT_2 = 0x25, + C2H_DEFEATURE_RSVD = 0xFD, + C2H_EXTEND = 0xff, +} C2H_EVT; + +typedef enum _EXTEND_C2H_EVT { + EXTEND_C2H_DBG_PRINT = 0 +} EXTEND_C2H_EVT; + +#define C2H_REG_LEN 16 + +/* C2H_IQK_FINISH, 0x11 */ +#define IQK_OFFLOAD_LEN 1 +void c2h_iqk_offload(_adapter *adapter, u8 *data, u8 len); +int c2h_iqk_offload_wait(_adapter *adapter, u32 timeout_ms); +#define rtl8812_iqk_wait c2h_iqk_offload_wait /* TODO: remove this after phydm call c2h_iqk_offload_wait instead */ + +/* C2H_MAC_HIDDEN_RPT, 0x19 */ +#define MAC_HIDDEN_RPT_LEN 8 +int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len); + +/* C2H_MAC_HIDDEN_RPT_2, 0x1A */ +#define MAC_HIDDEN_RPT_2_LEN 5 +int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); +int hal_read_mac_hidden_rpt(_adapter *adapter); + +/* C2H_DEFEATURE_DBG, 0x22 */ +#define DEFEATURE_DBG_LEN 1 +int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len); + + +#endif /* __COMMON_C2H_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/hal_com_phycfg.c b/drivers/staging/rtl8821ce/hal/hal_com_phycfg.c new file mode 100644 index 000000000000..23697b31203a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_com_phycfg.c @@ -0,0 +1,4226 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_COM_PHYCFG_C_ + +#include <drv_types.h> +#include <hal_data.h> + +#define PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) (((_pg_v) & 0xf0) >> 4) +#define PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) ((_pg_v) & 0x0f) +#define PG_TXPWR_MSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_MSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_MSB_DIFF_S4BIT(_pg_v)) +#define PG_TXPWR_LSB_DIFF_TO_S8BIT(_pg_v) ((PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) & BIT3) ? (PG_TXPWR_LSB_DIFF_S4BIT(_pg_v) | 0xF0) : PG_TXPWR_LSB_DIFF_S4BIT(_pg_v)) +#define IS_PG_TXPWR_BASE_INVALID(_base) ((_base) > 63) +#define IS_PG_TXPWR_DIFF_INVALID(_diff) ((_diff) > 7 || (_diff) < -8) +#define PG_TXPWR_INVALID_BASE 255 +#define PG_TXPWR_INVALID_DIFF 8 + +#define PG_TXPWR_SRC_PG_DATA 0 +#define PG_TXPWR_SRC_IC_DEF 1 +#define PG_TXPWR_SRC_DEF 2 +#define PG_TXPWR_SRC_NUM 3 + +const char *const _pg_txpwr_src_str[] = { + "PG_DATA", + "IC_DEF", + "DEF", + "UNKNOWN" +}; + +#define pg_txpwr_src_str(src) (((src) >= PG_TXPWR_SRC_NUM) ? _pg_txpwr_src_str[PG_TXPWR_SRC_NUM] : _pg_txpwr_src_str[(src)]) + +#ifndef DBG_PG_TXPWR_READ +#define DBG_PG_TXPWR_READ 0 +#endif + +void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) +{ + int path, group, tx_idx; + + RTW_PRINT_SEL(sel, "2.4G\n"); + RTW_PRINT_SEL(sel, "CCK-1T base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) + _RTW_PRINT_SEL(sel, "G%02d ", group); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) + _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexCCK_Base[path][group]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "CCK diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dT ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->CCK_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40-1S base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) + _RTW_PRINT_SEL(sel, "G%02d ", group); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) + _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "OFDM diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dT ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW20 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); +} + +void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt) +{ + int path, group, tx_idx; + + RTW_PRINT_SEL(sel, "5G\n"); + RTW_PRINT_SEL(sel, "BW40-1S base:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + _RTW_PRINT_SEL(sel, "G%02d ", group); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + _RTW_PRINT_SEL(sel, "%3u ", txpwr_info->IndexBW40_Base[path][group]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "OFDM diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dT ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->OFDM_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW20 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW20_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW40 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW40_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW80 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW80_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); + + RTW_PRINT_SEL(sel, "BW160 diff:\n"); + RTW_PRINT_SEL(sel, "%4s ", ""); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) + _RTW_PRINT_SEL(sel, "%dS ", path + 1); + _RTW_PRINT_SEL(sel, "\n"); + for (path = 0; path < MAX_RF_PATH && path < rfpath_num; path++) { + RTW_PRINT_SEL(sel, "[%c]: ", rf_path_char(path)); + for (tx_idx = RF_1TX; tx_idx < MAX_TX_COUNT && tx_idx < max_tx_cnt; tx_idx++) + _RTW_PRINT_SEL(sel, "%2d ", txpwr_info->BW160_Diff[path][tx_idx]); + _RTW_PRINT_SEL(sel, "\n"); + } + RTW_PRINT_SEL(sel, "\n"); +} + +const struct map_t pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 168, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, + 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, + 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x24, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, + 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x2A, 0x04, 0xEE, + 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE) + ); + +static const struct map_t rtl8821c_pg_txpwr_def_info = + MAP_ENT(0xB8, 1, 0xFF + , MAPSEG_ARRAY_ENT(0x10, 54, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, 0x28, + 0x02, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xEC, 0xFF, 0xFF, 0xFF, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, + 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02) + ); + +const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter) +{ + u8 interface_type = 0; + const struct map_t *map = NULL; + + interface_type = rtw_get_intf_type(adapter); + + switch (rtw_get_chip_type(adapter)) { + case RTL8821C: + map = &rtl8821c_pg_txpwr_def_info; + break; + } + + if (map == NULL) { + RTW_ERR("%s: unknown chip_type:%u\n" + , __func__, rtw_get_chip_type(adapter)); + rtw_warn_on(1); + } + + return map; +} + +static u8 hal_chk_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; + + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) + return _SUCCESS; + + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) + continue; + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group]) + || IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])) + return _FAIL; + } + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) + continue; + if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx])) + return _FAIL; + } + } + + return _SUCCESS; +} + +static u8 hal_chk_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; + + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G)) + return _SUCCESS; + + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + continue; + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + if (IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group])) + return _FAIL; + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (!HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) + continue; + if (IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx]) + || IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx])) + return _FAIL; + } + } + return _SUCCESS; +} + +static inline void hal_init_pg_txpwr_info_2g(_adapter *adapter, TxPowerInfo24G *pwr_info) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; + + if (pwr_info == NULL) + return; + + _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo24G)); + + /* init with invalid value */ + for (path = 0; path < MAX_RF_PATH; path++) { + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + pwr_info->IndexCCK_Base[path][group] = PG_TXPWR_INVALID_BASE; + pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE; + } + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + pwr_info->CCK_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + } + } + + /* init for dummy base and diff */ + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) + break; + /* 2.4G BW40 base has 1 less group than CCK base*/ + pwr_info->IndexBW40_Base[path][MAX_CHNL_GROUP_24G - 1] = 0; + + /* dummy diff */ + pwr_info->CCK_Diff[path][0] = 0; /* 2.4G CCK-1TX */ + pwr_info->BW40_Diff[path][0] = 0; /* 2.4G BW40-1S */ + } +} + +static inline void hal_init_pg_txpwr_info_5g(_adapter *adapter, TxPowerInfo5G *pwr_info) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path, group, tx_idx; + + if (pwr_info == NULL) + return; + + _rtw_memset(pwr_info, 0, sizeof(TxPowerInfo5G)); + + /* init with invalid value */ + for (path = 0; path < MAX_RF_PATH; path++) { + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) + pwr_info->IndexBW40_Base[path][group] = PG_TXPWR_INVALID_BASE; + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + pwr_info->OFDM_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW20_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW40_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW80_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + pwr_info->BW160_Diff[path][tx_idx] = PG_TXPWR_INVALID_DIFF; + } + } + + for (path = 0; path < MAX_RF_PATH; path++) { + if (!HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + break; + /* dummy diff */ + pwr_info->BW40_Diff[path][0] = 0; /* 5G BW40-1S */ + } +} + +#if DBG_PG_TXPWR_READ +#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) 1 +#else +#define LOAD_PG_TXPWR_WARN_COND(_txpwr_src) (_txpwr_src > PG_TXPWR_SRC_PG_DATA) +#endif + +u16 hal_load_pg_txpwr_info_path_2g( + _adapter *adapter, + TxPowerInfo24G *pwr_info, + u32 path, + u8 txpwr_src, + const struct map_t *txpwr_map, + u16 pg_offset) +{ +#define PG_TXPWR_1PATH_BYTE_NUM_2G 18 + + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u16 offset = pg_offset; + u8 group, tx_idx; + u8 val; + u8 tmp_base; + s8 tmp_diff; + + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_2G)) { + offset += PG_TXPWR_1PATH_BYTE_NUM_2G; + goto exit; + } + + if (DBG_PG_TXPWR_READ) + RTW_INFO("%s [%c] offset:0x%03x\n", __func__, rf_path_char(path), offset); + + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { + tmp_base = map_read8(txpwr_map, offset); + if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) + && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexCCK_Base[path][group]) + ) { + pwr_info->IndexCCK_Base[path][group] = tmp_base; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G G%02d CCK-1T base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } + + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path)) { + tmp_base = map_read8(txpwr_map, offset); + if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) + && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]) + ) { + pwr_info->IndexBW40_Base[path][group] = tmp_base; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } + + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx == 0) { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + ) { + pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } else { + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]) + ) { + pwr_info->BW40_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + + if (HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + ) { + pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->CCK_Diff[path][tx_idx]) + ) { + pwr_info->CCK_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 2G CCK-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } + } + + if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_2G) { + RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_2G); + rtw_warn_on(1); + } + +exit: + return offset; +} + +u16 hal_load_pg_txpwr_info_path_5g( + _adapter *adapter, + TxPowerInfo5G *pwr_info, + u32 path, + u8 txpwr_src, + const struct map_t *txpwr_map, + u16 pg_offset) +{ +#define PG_TXPWR_1PATH_BYTE_NUM_5G 24 + + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u16 offset = pg_offset; + u8 group, tx_idx; + u8 val; + u8 tmp_base; + s8 tmp_diff; + + if (pwr_info == NULL || !hal_chk_band_cap(adapter, BAND_CAP_5G)) + { + offset += PG_TXPWR_1PATH_BYTE_NUM_5G; + goto exit; + } + + if (DBG_PG_TXPWR_READ) + RTW_INFO("%s[%c] eaddr:0x%03x\n", __func__, rf_path_char(path), offset); + + for (group = 0; group < MAX_CHNL_GROUP_5G; group++) { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) { + tmp_base = map_read8(txpwr_map, offset); + if (!IS_PG_TXPWR_BASE_INVALID(tmp_base) + && IS_PG_TXPWR_BASE_INVALID(pwr_info->IndexBW40_Base[path][group]) + ) { + pwr_info->IndexBW40_Base[path][group] = tmp_base; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G G%02d BW40-1S base:%u from %s\n", rf_path_char(path), group, tmp_base, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } + + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx == 0) { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][tx_idx]) + ) { + pwr_info->OFDM_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } else { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW40_Diff[path][tx_idx]) + ) { + pwr_info->BW40_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW40-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW20_Diff[path][tx_idx]) + ) { + pwr_info->BW20_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW20-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } + } + + /* OFDM diff 2T ~ 3T */ + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 1)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][1]) + ) { + pwr_info->OFDM_Diff[path][1] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 2, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + if (HAL_SPEC_CHK_TX_CNT(hal_spec, 2)) { + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][2]) + ) { + pwr_info->OFDM_Diff[path][2] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 3, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + } + offset++; + + /* OFDM diff 4T */ + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, 3)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->OFDM_Diff[path][3]) + ) { + pwr_info->OFDM_Diff[path][3] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G OFDM-%dT diff:%d from %s\n", rf_path_char(path), 4, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path) && HAL_SPEC_CHK_TX_CNT(hal_spec, tx_idx)) { + val = map_read8(txpwr_map, offset); + tmp_diff = PG_TXPWR_MSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW80_Diff[path][tx_idx]) + ) { + pwr_info->BW80_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW80-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + tmp_diff = PG_TXPWR_LSB_DIFF_TO_S8BIT(val); + if (!IS_PG_TXPWR_DIFF_INVALID(tmp_diff) + && IS_PG_TXPWR_DIFF_INVALID(pwr_info->BW160_Diff[path][tx_idx]) + ) { + pwr_info->BW160_Diff[path][tx_idx] = tmp_diff; + if (LOAD_PG_TXPWR_WARN_COND(txpwr_src)) + RTW_INFO("[%c] 5G BW160-%dS diff:%d from %s\n", rf_path_char(path), tx_idx + 1, tmp_diff, pg_txpwr_src_str(txpwr_src)); + } + } + offset++; + } + + if (offset != pg_offset + PG_TXPWR_1PATH_BYTE_NUM_5G) { + RTW_ERR("%s parse %d bytes != %d\n", __func__, offset - pg_offset, PG_TXPWR_1PATH_BYTE_NUM_5G); + rtw_warn_on(1); + } + + +exit: + return offset; +} + +void hal_load_pg_txpwr_info( + _adapter *adapter, + TxPowerInfo24G *pwr_info_2g, + TxPowerInfo5G *pwr_info_5g, + u8 *pg_data, + BOOLEAN AutoLoadFail +) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 path; + u16 pg_offset; + u8 txpwr_src = PG_TXPWR_SRC_PG_DATA; + struct map_t pg_data_map = MAP_ENT(184, 1, 0xFF, MAPSEG_PTR_ENT(0x00, 184, pg_data)); + const struct map_t *txpwr_map = NULL; + + /* init with invalid value and some dummy base and diff */ + hal_init_pg_txpwr_info_2g(adapter, pwr_info_2g); + hal_init_pg_txpwr_info_5g(adapter, pwr_info_5g); + +select_src: + pg_offset = 0x10; + + switch (txpwr_src) { + case PG_TXPWR_SRC_PG_DATA: + txpwr_map = &pg_data_map; + break; + case PG_TXPWR_SRC_IC_DEF: + txpwr_map = hal_pg_txpwr_def_info(adapter); + break; + case PG_TXPWR_SRC_DEF: + default: + txpwr_map = &pg_txpwr_def_info; + break; + }; + + if (txpwr_map == NULL) + goto end_parse; + + for (path = 0; path < MAX_RF_PATH ; path++) { + if (!HAL_SPEC_CHK_RF_PATH_2G(hal_spec, path) && !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, path)) + break; + pg_offset = hal_load_pg_txpwr_info_path_2g(adapter, pwr_info_2g, path, txpwr_src, txpwr_map, pg_offset); + pg_offset = hal_load_pg_txpwr_info_path_5g(adapter, pwr_info_5g, path, txpwr_src, txpwr_map, pg_offset); + } + + if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) == _SUCCESS + && hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) == _SUCCESS) + goto exit; + +end_parse: + txpwr_src++; + if (txpwr_src < PG_TXPWR_SRC_NUM) + goto select_src; + + if (hal_chk_pg_txpwr_info_2g(adapter, pwr_info_2g) != _SUCCESS + || hal_chk_pg_txpwr_info_5g(adapter, pwr_info_5g) != _SUCCESS) + rtw_warn_on(1); + +exit: + if (DBG_PG_TXPWR_READ) { + if (pwr_info_2g) + dump_pg_txpwr_info_2g(RTW_DBGDUMP, pwr_info_2g, 4, 4); + if (pwr_info_5g) + dump_pg_txpwr_info_5g(RTW_DBGDUMP, pwr_info_5g, 4, 4); + } + + return; +} + +void hal_load_txpwr_info( + _adapter *adapter, + TxPowerInfo24G *pwr_info_2g, + TxPowerInfo5G *pwr_info_5g, + u8 *pg_data +) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 max_tx_cnt = hal_spec->max_tx_cnt; + u8 rfpath, ch_idx, group, tx_idx; + + /* load from pg data (or default value) */ + hal_load_pg_txpwr_info(adapter, pwr_info_2g, pwr_info_5g, pg_data, _FALSE); + + /* transform to hal_data */ + for (rfpath = 0; rfpath < MAX_RF_PATH; rfpath++) { + + if (!pwr_info_2g || !HAL_SPEC_CHK_RF_PATH_2G(hal_spec, rfpath)) + goto bypass_2g; + + /* 2.4G base */ + for (ch_idx = 0; ch_idx < CENTER_CH_2G_NUM; ch_idx++) { + u8 cck_group; + + if (rtw_get_ch_group(ch_idx + 1, &group, &cck_group) != BAND_ON_2_4G) + continue; + + hal_data->Index24G_CCK_Base[rfpath][ch_idx] = pwr_info_2g->IndexCCK_Base[rfpath][cck_group]; + hal_data->Index24G_BW40_Base[rfpath][ch_idx] = pwr_info_2g->IndexBW40_Base[rfpath][group]; + } + + /* 2.4G diff */ + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx >= max_tx_cnt) + break; + + hal_data->CCK_24G_Diff[rfpath][tx_idx] = pwr_info_2g->CCK_Diff[rfpath][tx_idx]; + hal_data->OFDM_24G_Diff[rfpath][tx_idx] = pwr_info_2g->OFDM_Diff[rfpath][tx_idx]; + hal_data->BW20_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW20_Diff[rfpath][tx_idx]; + hal_data->BW40_24G_Diff[rfpath][tx_idx] = pwr_info_2g->BW40_Diff[rfpath][tx_idx]; + } +bypass_2g: + ; + + if (!pwr_info_5g || !HAL_SPEC_CHK_RF_PATH_5G(hal_spec, rfpath)) + goto bypass_5g; + + /* 5G base */ + for (ch_idx = 0; ch_idx < CENTER_CH_5G_ALL_NUM; ch_idx++) { + if (rtw_get_ch_group(center_ch_5g_all[ch_idx], &group, NULL) != BAND_ON_5G) + continue; + hal_data->Index5G_BW40_Base[rfpath][ch_idx] = pwr_info_5g->IndexBW40_Base[rfpath][group]; + } + + for (ch_idx = 0 ; ch_idx < CENTER_CH_5G_80M_NUM; ch_idx++) { + u8 upper, lower; + + if (rtw_get_ch_group(center_ch_5g_80m[ch_idx], &group, NULL) != BAND_ON_5G) + continue; + + upper = pwr_info_5g->IndexBW40_Base[rfpath][group]; + lower = pwr_info_5g->IndexBW40_Base[rfpath][group + 1]; + hal_data->Index5G_BW80_Base[rfpath][ch_idx] = (upper + lower) / 2; + } + + /* 5G diff */ + for (tx_idx = 0; tx_idx < MAX_TX_COUNT; tx_idx++) { + if (tx_idx >= max_tx_cnt) + break; + + hal_data->OFDM_5G_Diff[rfpath][tx_idx] = pwr_info_5g->OFDM_Diff[rfpath][tx_idx]; + hal_data->BW20_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW20_Diff[rfpath][tx_idx]; + hal_data->BW40_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW40_Diff[rfpath][tx_idx]; + hal_data->BW80_5G_Diff[rfpath][tx_idx] = pwr_info_5g->BW80_Diff[rfpath][tx_idx]; + } +bypass_5g: + ; + } +} + +/* +* rtw_regsty_get_target_tx_power - +* +* Return dBm or -1 for undefined +*/ +s8 rtw_regsty_get_target_tx_power( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection +) +{ + struct registry_priv *regsty = adapter_to_regsty(Adapter); + s8 value = 0; + + if (RfPath > RF_PATH_D) { + RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); + return -1; + } + + if (Band != BAND_ON_2_4G + && Band != BAND_ON_5G + ) { + RTW_PRINT("%s invalid Band:%d\n", __func__, Band); + return -1; + } + + if (RateSection >= RATE_SECTION_NUM + || (Band == BAND_ON_5G && RateSection == CCK) + ) { + RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d\n", __func__ + , RateSection, Band, RfPath); + return -1; + } + + if (Band == BAND_ON_2_4G) + value = regsty->target_tx_pwr_2g[RfPath][RateSection]; + else /* BAND_ON_5G */ + value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1]; + + return value; +} + +bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int path, tx_num, band, rs; + s8 target; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + for (path = 0; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + break; + + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->tx_nss_num) + continue; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; + + target = rtw_regsty_get_target_tx_power(adapter, band, path, rs); + if (target == -1) { + RTW_PRINT("%s return _FALSE for band:%d, path:%d, rs:%d, t:%d\n", __func__, band, path, rs, target); + return _FALSE; + } + } + } + } + + return _TRUE; +} + +/* +* PHY_GetTxPowerByRateBase - +* +* Return 2 times of dBm +*/ +u8 +PHY_GetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN u8 TxNum, + IN RATE_SECTION RateSection +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 value = 0; + + if (RfPath > RF_PATH_D) { + RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); + return 0; + } + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_PRINT("%s invalid Band:%d\n", __func__, Band); + return 0; + } + + if (RateSection >= RATE_SECTION_NUM + || (Band == BAND_ON_5G && RateSection == CCK) + ) { + RTW_PRINT("%s invalid RateSection:%d in Band:%d, RfPath:%d, TxNum:%d\n", __func__ + , RateSection, Band, RfPath, TxNum); + return 0; + } + + if (Band == BAND_ON_2_4G) + value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection]; + else /* BAND_ON_5G */ + value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1]; + + return value; +} + +VOID +phy_SetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection, + IN u8 TxNum, + IN u8 Value +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if (RfPath > RF_PATH_D) { + RTW_PRINT("%s invalid RfPath:%d\n", __func__, RfPath); + return; + } + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_PRINT("%s invalid Band:%d\n", __func__, Band); + return; + } + + if (RateSection >= RATE_SECTION_NUM + || (Band == BAND_ON_5G && RateSection == CCK) + ) { + RTW_PRINT("%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__ + , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum); + return; + } + + if (Band == BAND_ON_2_4G) + pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection] = Value; + else /* BAND_ON_5G */ + pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1] = Value; +} + +static inline BOOLEAN phy_is_txpwr_by_rate_undefined_of_band_path(_adapter *adapter, u8 band, u8 path) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 tx_num = 0, rate_idx = 0; + + for (tx_num = 0; tx_num < TX_PWR_BY_RATE_NUM_RF; tx_num++) { + if (tx_num >= hal_spec->max_tx_cnt || tx_num >= hal_spec->tx_nss_num) + goto exit; + for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) { + if (hal_data->TxPwrByRateOffset[band][path][tx_num][rate_idx] != 0) + goto exit; + } + } + +exit: + return (tx_num >= hal_spec->max_tx_cnt || tx_num >= hal_spec->tx_nss_num) ? _TRUE : _FALSE; +} + +static inline void phy_txpwr_by_rate_duplicate_band_path(_adapter *adapter, u8 band, u8 s_path, u8 t_path) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 tx_num = 0, rate_idx = 0; + + for (tx_num = 0; tx_num < TX_PWR_BY_RATE_NUM_RF; tx_num++) + for (rate_idx = 0; rate_idx < TX_PWR_BY_RATE_NUM_RATE; rate_idx++) + hal_data->TxPwrByRateOffset[band][t_path][tx_num][rate_idx] = hal_data->TxPwrByRateOffset[band][s_path][tx_num][rate_idx]; +} + +static void phy_txpwr_by_rate_chk_for_path_dup(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 band, path; + s8 src_path; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) + hal_data->txpwr_by_rate_undefined_band_path[band][path] = 0; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + continue; + + if (phy_is_txpwr_by_rate_undefined_of_band_path(adapter, band, path)) + hal_data->txpwr_by_rate_undefined_band_path[band][path] = 1; + } + } + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + src_path = -1; + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + continue; + + /* find src */ + if (src_path == -1 && hal_data->txpwr_by_rate_undefined_band_path[band][path] == 0) + src_path = path; + } + + if (src_path == -1) { + RTW_ERR("%s all power by rate undefined\n", __func__); + continue; + } + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + continue; + + /* duplicate src to undefined one */ + if (hal_data->txpwr_by_rate_undefined_band_path[band][path] == 1) { + RTW_INFO("%s duplicate %s [%c] to [%c]\n", __func__ + , band_str(band), rf_path_char(src_path), rf_path_char(path)); + phy_txpwr_by_rate_duplicate_band_path(adapter, band, src_path, path); + } + } + } +} + +VOID +phy_StoreTxPowerByRateBase( + IN PADAPTER pAdapter +) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter); + struct registry_priv *regsty = adapter_to_regsty(pAdapter); + + u8 rate_sec_base[RATE_SECTION_NUM] = { + MGN_11M, + MGN_54M, + MGN_MCS7, + MGN_MCS15, + MGN_MCS23, + MGN_MCS31, + MGN_VHT1SS_MCS7, + MGN_VHT2SS_MCS7, + MGN_VHT3SS_MCS7, + MGN_VHT4SS_MCS7, + }; + + u8 band, path, rs, tx_num, base, index; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(pAdapter, band)) + continue; + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, path)) + break; + + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->tx_nss_num) + continue; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) + continue; + + if (regsty->target_tx_pwr_valid == _TRUE) + base = 2 * rtw_regsty_get_target_tx_power(pAdapter, band, path, rs); + else + base = _PHY_GetTxPowerByRate(pAdapter, band, path, tx_num, rate_sec_base[rs]); + phy_SetTxPowerByRateBase(pAdapter, band, path, rs, tx_num, base); + } + } + } +} + +VOID +PHY_GetRateValuesOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Value, + OUT u8 *Rate, + OUT s8 *PwrByRateVal, + OUT u8 *RateNum +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + u8 index = 0, i = 0; + + switch (RegAddr) { + case rTxAGC_A_Rate18_06: + case rTxAGC_B_Rate18_06: + Rate[0] = MGN_6M; + Rate[1] = MGN_9M; + Rate[2] = MGN_12M; + Rate[3] = MGN_18M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case rTxAGC_A_Rate54_24: + case rTxAGC_B_Rate54_24: + Rate[0] = MGN_24M; + Rate[1] = MGN_36M; + Rate[2] = MGN_48M; + Rate[3] = MGN_54M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case rTxAGC_A_CCK1_Mcs32: + Rate[0] = MGN_1M; + PwrByRateVal[0] = (s8)((((Value >> (8 + 4)) & 0xF)) * 10 + + ((Value >> 8) & 0xF)); + *RateNum = 1; + break; + + case rTxAGC_B_CCK11_A_CCK2_11: + if (BitMask == 0xffffff00) { + Rate[0] = MGN_2M; + Rate[1] = MGN_5_5M; + Rate[2] = MGN_11M; + for (i = 1; i < 4; ++i) { + PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 3; + } else if (BitMask == 0x000000ff) { + Rate[0] = MGN_11M; + PwrByRateVal[0] = (s8)((((Value >> 4) & 0xF)) * 10 + + (Value & 0xF)); + *RateNum = 1; + } + break; + + case rTxAGC_A_Mcs03_Mcs00: + case rTxAGC_B_Mcs03_Mcs00: + Rate[0] = MGN_MCS0; + Rate[1] = MGN_MCS1; + Rate[2] = MGN_MCS2; + Rate[3] = MGN_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case rTxAGC_A_Mcs07_Mcs04: + case rTxAGC_B_Mcs07_Mcs04: + Rate[0] = MGN_MCS4; + Rate[1] = MGN_MCS5; + Rate[2] = MGN_MCS6; + Rate[3] = MGN_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case rTxAGC_A_Mcs11_Mcs08: + case rTxAGC_B_Mcs11_Mcs08: + Rate[0] = MGN_MCS8; + Rate[1] = MGN_MCS9; + Rate[2] = MGN_MCS10; + Rate[3] = MGN_MCS11; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case rTxAGC_A_Mcs15_Mcs12: + case rTxAGC_B_Mcs15_Mcs12: + Rate[0] = MGN_MCS12; + Rate[1] = MGN_MCS13; + Rate[2] = MGN_MCS14; + Rate[3] = MGN_MCS15; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + + break; + + case rTxAGC_B_CCK1_55_Mcs32: + Rate[0] = MGN_1M; + Rate[1] = MGN_2M; + Rate[2] = MGN_5_5M; + for (i = 1; i < 4; ++i) { + PwrByRateVal[i - 1] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 3; + break; + + case 0xC20: + case 0xE20: + case 0x1820: + case 0x1a20: + Rate[0] = MGN_1M; + Rate[1] = MGN_2M; + Rate[2] = MGN_5_5M; + Rate[3] = MGN_11M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC24: + case 0xE24: + case 0x1824: + case 0x1a24: + Rate[0] = MGN_6M; + Rate[1] = MGN_9M; + Rate[2] = MGN_12M; + Rate[3] = MGN_18M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC28: + case 0xE28: + case 0x1828: + case 0x1a28: + Rate[0] = MGN_24M; + Rate[1] = MGN_36M; + Rate[2] = MGN_48M; + Rate[3] = MGN_54M; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC2C: + case 0xE2C: + case 0x182C: + case 0x1a2C: + Rate[0] = MGN_MCS0; + Rate[1] = MGN_MCS1; + Rate[2] = MGN_MCS2; + Rate[3] = MGN_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC30: + case 0xE30: + case 0x1830: + case 0x1a30: + Rate[0] = MGN_MCS4; + Rate[1] = MGN_MCS5; + Rate[2] = MGN_MCS6; + Rate[3] = MGN_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC34: + case 0xE34: + case 0x1834: + case 0x1a34: + Rate[0] = MGN_MCS8; + Rate[1] = MGN_MCS9; + Rate[2] = MGN_MCS10; + Rate[3] = MGN_MCS11; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC38: + case 0xE38: + case 0x1838: + case 0x1a38: + Rate[0] = MGN_MCS12; + Rate[1] = MGN_MCS13; + Rate[2] = MGN_MCS14; + Rate[3] = MGN_MCS15; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC3C: + case 0xE3C: + case 0x183C: + case 0x1a3C: + Rate[0] = MGN_VHT1SS_MCS0; + Rate[1] = MGN_VHT1SS_MCS1; + Rate[2] = MGN_VHT1SS_MCS2; + Rate[3] = MGN_VHT1SS_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC40: + case 0xE40: + case 0x1840: + case 0x1a40: + Rate[0] = MGN_VHT1SS_MCS4; + Rate[1] = MGN_VHT1SS_MCS5; + Rate[2] = MGN_VHT1SS_MCS6; + Rate[3] = MGN_VHT1SS_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC44: + case 0xE44: + case 0x1844: + case 0x1a44: + Rate[0] = MGN_VHT1SS_MCS8; + Rate[1] = MGN_VHT1SS_MCS9; + Rate[2] = MGN_VHT2SS_MCS0; + Rate[3] = MGN_VHT2SS_MCS1; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC48: + case 0xE48: + case 0x1848: + case 0x1a48: + Rate[0] = MGN_VHT2SS_MCS2; + Rate[1] = MGN_VHT2SS_MCS3; + Rate[2] = MGN_VHT2SS_MCS4; + Rate[3] = MGN_VHT2SS_MCS5; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xC4C: + case 0xE4C: + case 0x184C: + case 0x1a4C: + Rate[0] = MGN_VHT2SS_MCS6; + Rate[1] = MGN_VHT2SS_MCS7; + Rate[2] = MGN_VHT2SS_MCS8; + Rate[3] = MGN_VHT2SS_MCS9; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xCD8: + case 0xED8: + case 0x18D8: + case 0x1aD8: + Rate[0] = MGN_MCS16; + Rate[1] = MGN_MCS17; + Rate[2] = MGN_MCS18; + Rate[3] = MGN_MCS19; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xCDC: + case 0xEDC: + case 0x18DC: + case 0x1aDC: + Rate[0] = MGN_MCS20; + Rate[1] = MGN_MCS21; + Rate[2] = MGN_MCS22; + Rate[3] = MGN_MCS23; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xCE0: + case 0xEE0: + case 0x18E0: + case 0x1aE0: + Rate[0] = MGN_VHT3SS_MCS0; + Rate[1] = MGN_VHT3SS_MCS1; + Rate[2] = MGN_VHT3SS_MCS2; + Rate[3] = MGN_VHT3SS_MCS3; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xCE4: + case 0xEE4: + case 0x18E4: + case 0x1aE4: + Rate[0] = MGN_VHT3SS_MCS4; + Rate[1] = MGN_VHT3SS_MCS5; + Rate[2] = MGN_VHT3SS_MCS6; + Rate[3] = MGN_VHT3SS_MCS7; + for (i = 0; i < 4; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 4; + break; + + case 0xCE8: + case 0xEE8: + case 0x18E8: + case 0x1aE8: + Rate[0] = MGN_VHT3SS_MCS8; + Rate[1] = MGN_VHT3SS_MCS9; + for (i = 0; i < 2; ++i) { + PwrByRateVal[i] = (s8)((((Value >> (i * 8 + 4)) & 0xF)) * 10 + + ((Value >> (i * 8)) & 0xF)); + } + *RateNum = 2; + break; + + default: + RTW_PRINT("Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__); + break; + }; +} + +void +PHY_StoreTxPowerByRateNew( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 i = 0, rates[4] = {0}, rateNum = 0; + s8 PwrByRateVal[4] = {0}; + + PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum); + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_PRINT("Invalid Band %d\n", Band); + return; + } + + if (RfPath > ODM_RF_PATH_D) { + RTW_PRINT("Invalid RfPath %d\n", RfPath); + return; + } + + if (TxNum > ODM_RF_PATH_D) { + RTW_PRINT("Invalid TxNum %d\n", TxNum); + return; + } + + for (i = 0; i < rateNum; ++i) { + u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]); + + if (IS_1T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_1TX][rate_idx] = PwrByRateVal[i]; + else if (IS_2T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_2TX][rate_idx] = PwrByRateVal[i]; + else if (IS_3T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_3TX][rate_idx] = PwrByRateVal[i]; + else if (IS_4T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_4TX][rate_idx] = PwrByRateVal[i]; + else + rtw_warn_on(1); + } +} + +VOID +PHY_InitTxPowerByRate( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 band = 0, rfPath = 0, TxNum = 0, rate = 0, i = 0, j = 0; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) + for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath) + for (TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum) + for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate) + pHalData->TxPwrByRateOffset[band][rfPath][TxNum][rate] = 0; +} + +VOID +phy_store_tx_power_by_rate( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + + if (pDM_Odm->phy_reg_pg_version > 0) + PHY_StoreTxPowerByRateNew(pAdapter, Band, RfPath, TxNum, RegAddr, BitMask, Data); + else + RTW_INFO("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->phy_reg_pg_version); + +} + +VOID +phy_ConvertTxPowerByRateInDbmToRelativeValues( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 base = 0, i = 0, value = 0, + band = 0, path = 0, txNum = 0, index = 0, + startIndex = 0, endIndex = 0; + u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, + ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}, + mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, + mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, + mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, + vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9}, + vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, + vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9}; + + /* RTW_INFO("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band) { + for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { + for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) { + /* CCK */ + if (band == BAND_ON_2_4G) { + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, CCK); + for (i = 0; i < sizeof(cckRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, cckRates[i], value - base); + } + } + + /* OFDM */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, OFDM); + for (i = 0; i < sizeof(ofdmRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, ofdmRates[i], value - base); + } + + /* HT MCS0~7 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, HT_1SS); + for (i = 0; i < sizeof(mcs0_7Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs0_7Rates[i], value - base); + } + + /* HT MCS8~15 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, HT_2SS); + for (i = 0; i < sizeof(mcs8_15Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs8_15Rates[i], value - base); + } + + /* HT MCS16~23 */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, HT_3SS); + for (i = 0; i < sizeof(mcs16_23Rates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, mcs16_23Rates[i], value - base); + } + + /* VHT 1SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, VHT_1SS); + for (i = 0; i < sizeof(vht1ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht1ssRates[i], value - base); + } + + /* VHT 2SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, VHT_2SS); + for (i = 0; i < sizeof(vht2ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht2ssRates[i], value - base); + } + + /* VHT 3SS */ + base = PHY_GetTxPowerByRateBase(pAdapter, band, path, txNum, VHT_3SS); + for (i = 0; i < sizeof(vht3ssRates); ++i) { + value = PHY_GetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i]); + PHY_SetTxPowerByRate(pAdapter, band, path, txNum, vht3ssRates[i], value - base); + } + } + } + } + + /* RTW_INFO("<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); */ +} + +/* + * This function must be called if the value in the PHY_REG_PG.txt(or header) + * is exact dBm values + */ +VOID +PHY_TxPowerByRateConfiguration( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + phy_txpwr_by_rate_chk_for_path_dup(pAdapter); + phy_StoreTxPowerByRateBase(pAdapter); + phy_ConvertTxPowerByRateInDbmToRelativeValues(pAdapter); +} + +VOID +phy_set_tx_power_index_by_rate_section( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Channel, + IN u8 RateSection +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + if (RateSection >= RATE_SECTION_NUM) { + RTW_INFO("Invalid RateSection %d in %s", RateSection, __func__); + rtw_warn_on(1); + goto exit; + } + + if (RateSection == CCK && pHalData->current_band_type != BAND_ON_2_4G) + goto exit; + + PHY_SetTxPowerIndexByRateArray(pAdapter, RFPath, pHalData->current_channel_bw, Channel, + rates_by_sections[RateSection].rates, rates_by_sections[RateSection].rate_num); + +exit: + return; +} + +BOOLEAN +phy_GetChnlIndex( + IN u8 Channel, + OUT u8 *ChannelIdx +) +{ + u8 i = 0; + BOOLEAN bIn24G = _TRUE; + + if (Channel <= 14) { + bIn24G = _TRUE; + *ChannelIdx = Channel - 1; + } else { + bIn24G = _FALSE; + + for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { + if (center_ch_5g_all[i] == Channel) { + *ChannelIdx = i; + return bIn24G; + } + } + } + + return bIn24G; +} + +u8 +PHY_GetTxPowerIndexBase( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + OUT PBOOLEAN bIn24G +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + u8 i = 0; /* default set to 1S */ + u8 txPower = 0; + u8 chnlIdx = (Channel - 1); + + if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) { + chnlIdx = 0; + RTW_INFO("Illegal channel!!\n"); + } + + *bIn24G = phy_GetChnlIndex(Channel, &chnlIdx); + + /* RTW_INFO("[%s] Channel Index: %d\n", (*bIn24G?"2.4G":"5G"), chnlIdx); */ + + if (*bIn24G) { /* 3 ============================== 2.4 G ============================== */ + if (IS_CCK_RATE(Rate)) + txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx]; + else if (MGN_6M <= Rate) + txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx]; + else + RTW_INFO("PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate); + + /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */ + /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */ + + /* OFDM-1T */ + if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { + txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S]; + /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_24G_Diff[RFPath][TX_1S]); */ + } + /* BW20-1S, BW20-2S */ + if (BandWidth == CHANNEL_WIDTH_20) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_2S]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_3S]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_4S]; + + /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ + /* pHalData->BW20_24G_Diff[RFPath][TX_1S], pHalData->BW20_24G_Diff[RFPath][TX_2S], */ + /* pHalData->BW20_24G_Diff[RFPath][TX_3S], pHalData->BW20_24G_Diff[RFPath][TX_4S]); */ + } + /* BW40-1S, BW40-2S */ + else if (BandWidth == CHANNEL_WIDTH_40) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; + + /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ + /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */ + /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */ + } + /* Willis suggest adopt BW 40M power index while in BW 80 mode */ + else if (BandWidth == CHANNEL_WIDTH_80) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; + + /* RTW_INFO("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4T) = (%d, %d, %d, %d) P.S. Current is in BW 80MHz\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ + /* pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], */ + /* pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); */ + } + } + else { /* 3 ============================== 5 G ============================== */ + if (MGN_6M <= Rate) + txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx]; + else + RTW_INFO("===>PHY_GetTxPowerIndexBase: INVALID Rate(0x%02x).\n", Rate); + + /* RTW_INFO("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", */ + /* ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); */ + + /* OFDM-1T */ + if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) { + txPower += pHalData->OFDM_5G_Diff[RFPath][TX_1S]; + /* RTW_INFO("+PowerDiff 5G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_5G_Diff[RFPath][TX_1S]); */ + } + + /* BW20-1S, BW20-2S */ + if (BandWidth == CHANNEL_WIDTH_20) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_1S]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_2S]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_3S]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_4S]; + + /* RTW_INFO("+PowerDiff 5G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ + /* pHalData->BW20_5G_Diff[RFPath][TX_1S], pHalData->BW20_5G_Diff[RFPath][TX_2S], */ + /* pHalData->BW20_5G_Diff[RFPath][TX_3S], pHalData->BW20_5G_Diff[RFPath][TX_4S]); */ + } + /* BW40-1S, BW40-2S */ + else if (BandWidth == CHANNEL_WIDTH_40) { + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_1S]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_2S]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_3S]; + if ((MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S]; + + /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW40-1S, BW40-2S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ + /* pHalData->BW40_5G_Diff[RFPath][TX_1S], pHalData->BW40_5G_Diff[RFPath][TX_2S], */ + /* pHalData->BW40_5G_Diff[RFPath][TX_3S], pHalData->BW40_5G_Diff[RFPath][TX_4S]); */ + } + /* BW80-1S, BW80-2S */ + else if (BandWidth == CHANNEL_WIDTH_80) { + /* <20121220, Kordan> Get the index of array "Index5G_BW80_Base". */ + for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) + if (center_ch_5g_80m[i] == Channel) + chnlIdx = i; + + txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx]; + + if ((MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S]; + if ((MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S]; + if ((MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S]; + if ((MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S]; + + /* RTW_INFO("+PowerDiff 5G(RF-%c): (BW80-1S, BW80-2S, BW80-3S, BW80-4S) = (%d, %d, %d, %d)\n",((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), */ + /* pHalData->BW80_5G_Diff[RFPath][TX_1S], pHalData->BW80_5G_Diff[RFPath][TX_2S], */ + /* pHalData->BW80_5G_Diff[RFPath][TX_3S], pHalData->BW80_5G_Diff[RFPath][TX_4S]); */ + } + } + + return txPower; +} + +/*The same as MRateToHwRate in hal_com.c*/ +u8 +PHY_GetRateIndexOfTxPowerByRate( + IN u8 Rate +) +{ + u8 index = 0; + switch (Rate) { + case MGN_1M: + index = 0; + break; + case MGN_2M: + index = 1; + break; + case MGN_5_5M: + index = 2; + break; + case MGN_11M: + index = 3; + break; + case MGN_6M: + index = 4; + break; + case MGN_9M: + index = 5; + break; + case MGN_12M: + index = 6; + break; + case MGN_18M: + index = 7; + break; + case MGN_24M: + index = 8; + break; + case MGN_36M: + index = 9; + break; + case MGN_48M: + index = 10; + break; + case MGN_54M: + index = 11; + break; + case MGN_MCS0: + index = 12; + break; + case MGN_MCS1: + index = 13; + break; + case MGN_MCS2: + index = 14; + break; + case MGN_MCS3: + index = 15; + break; + case MGN_MCS4: + index = 16; + break; + case MGN_MCS5: + index = 17; + break; + case MGN_MCS6: + index = 18; + break; + case MGN_MCS7: + index = 19; + break; + case MGN_MCS8: + index = 20; + break; + case MGN_MCS9: + index = 21; + break; + case MGN_MCS10: + index = 22; + break; + case MGN_MCS11: + index = 23; + break; + case MGN_MCS12: + index = 24; + break; + case MGN_MCS13: + index = 25; + break; + case MGN_MCS14: + index = 26; + break; + case MGN_MCS15: + index = 27; + break; + case MGN_MCS16: + index = 28; + break; + case MGN_MCS17: + index = 29; + break; + case MGN_MCS18: + index = 30; + break; + case MGN_MCS19: + index = 31; + break; + case MGN_MCS20: + index = 32; + break; + case MGN_MCS21: + index = 33; + break; + case MGN_MCS22: + index = 34; + break; + case MGN_MCS23: + index = 35; + break; + case MGN_MCS24: + index = 36; + break; + case MGN_MCS25: + index = 37; + break; + case MGN_MCS26: + index = 38; + break; + case MGN_MCS27: + index = 39; + break; + case MGN_MCS28: + index = 40; + break; + case MGN_MCS29: + index = 41; + break; + case MGN_MCS30: + index = 42; + break; + case MGN_MCS31: + index = 43; + break; + case MGN_VHT1SS_MCS0: + index = 44; + break; + case MGN_VHT1SS_MCS1: + index = 45; + break; + case MGN_VHT1SS_MCS2: + index = 46; + break; + case MGN_VHT1SS_MCS3: + index = 47; + break; + case MGN_VHT1SS_MCS4: + index = 48; + break; + case MGN_VHT1SS_MCS5: + index = 49; + break; + case MGN_VHT1SS_MCS6: + index = 50; + break; + case MGN_VHT1SS_MCS7: + index = 51; + break; + case MGN_VHT1SS_MCS8: + index = 52; + break; + case MGN_VHT1SS_MCS9: + index = 53; + break; + case MGN_VHT2SS_MCS0: + index = 54; + break; + case MGN_VHT2SS_MCS1: + index = 55; + break; + case MGN_VHT2SS_MCS2: + index = 56; + break; + case MGN_VHT2SS_MCS3: + index = 57; + break; + case MGN_VHT2SS_MCS4: + index = 58; + break; + case MGN_VHT2SS_MCS5: + index = 59; + break; + case MGN_VHT2SS_MCS6: + index = 60; + break; + case MGN_VHT2SS_MCS7: + index = 61; + break; + case MGN_VHT2SS_MCS8: + index = 62; + break; + case MGN_VHT2SS_MCS9: + index = 63; + break; + case MGN_VHT3SS_MCS0: + index = 64; + break; + case MGN_VHT3SS_MCS1: + index = 65; + break; + case MGN_VHT3SS_MCS2: + index = 66; + break; + case MGN_VHT3SS_MCS3: + index = 67; + break; + case MGN_VHT3SS_MCS4: + index = 68; + break; + case MGN_VHT3SS_MCS5: + index = 69; + break; + case MGN_VHT3SS_MCS6: + index = 70; + break; + case MGN_VHT3SS_MCS7: + index = 71; + break; + case MGN_VHT3SS_MCS8: + index = 72; + break; + case MGN_VHT3SS_MCS9: + index = 73; + break; + case MGN_VHT4SS_MCS0: + index = 74; + break; + case MGN_VHT4SS_MCS1: + index = 75; + break; + case MGN_VHT4SS_MCS2: + index = 76; + break; + case MGN_VHT4SS_MCS3: + index = 77; + break; + case MGN_VHT4SS_MCS4: + index = 78; + break; + case MGN_VHT4SS_MCS5: + index = 79; + break; + case MGN_VHT4SS_MCS6: + index = 80; + break; + case MGN_VHT4SS_MCS7: + index = 81; + break; + case MGN_VHT4SS_MCS8: + index = 82; + break; + case MGN_VHT4SS_MCS9: + index = 83; + break; + default: + RTW_INFO("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__); + break; + }; + + return index; +} + +s8 +_PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s8 value = 0; + u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_INFO("Invalid band %d in %s\n", Band, __func__); + goto exit; + } + if (RFPath > ODM_RF_PATH_D) { + RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __func__); + goto exit; + } + if (TxNum >= RF_MAX_TX_NUM) { + RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __func__); + goto exit; + } + if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { + RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __func__); + goto exit; + } + + value = pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex]; + +exit: + return value; +} + +s8 +PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate +) +{ + if (!phy_is_tx_power_by_rate_needed(pAdapter)) + return 0; + + return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, TxNum, Rate); +} + + +VOID +PHY_SetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate, + IN s8 Value +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_INFO("Invalid band %d in %s\n", Band, __FUNCTION__); + return; + } + if (RFPath > ODM_RF_PATH_D) { + RTW_INFO("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__); + return; + } + if (TxNum >= RF_MAX_TX_NUM) { + RTW_INFO("Invalid TxNum %d in %s\n", TxNum, __FUNCTION__); + return; + } + if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { + RTW_INFO("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__); + return; + } + + pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex] = Value; +} + +#ifndef DBG_TX_POWER_IDX +#define DBG_TX_POWER_IDX 0 +#endif + +VOID +PHY_SetTxPowerIndexByRateArray( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + IN u8 *Rates, + IN u8 RateArraySize +) +{ + u32 powerIndex = 0; + int i = 0; + + for (i = 0; i < RateArraySize; ++i) { +#if DBG_TX_POWER_IDX + struct txpwr_idx_comp tic; + + powerIndex = rtw_hal_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel, &tic); + RTW_INFO("TXPWR: [%c][%s]ch:%u, %s, pwr_idx:%u = %u + (%d=%d:%d) + (%d) + (%d)\n" + , rf_path_char(RFPath), ch_width_str(BandWidth), Channel, MGN_RATE_STR(Rates[i]) + , powerIndex, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); +#else + powerIndex = phy_get_tx_power_index(pAdapter, RFPath, Rates[i], BandWidth, Channel); +#endif + PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]); + } +} + +s8 +phy_GetWorldWideLimit( + s8 *LimitTable +) +{ + s8 min = LimitTable[0]; + u8 i = 0; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) { + if (LimitTable[i] < min) + min = LimitTable[i]; + } + + return min; +} + +s8 +phy_GetChannelIndexOfTxPowerLimit( + IN u8 Band, + IN u8 Channel +) +{ + s8 channelIndex = -1; + u8 i = 0; + + if (Band == BAND_ON_2_4G) + channelIndex = Channel - 1; + else if (Band == BAND_ON_5G) { + for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { + if (center_ch_5g_all[i] == Channel) + channelIndex = i; + } + } else + RTW_PRINT("Invalid Band %d in %s\n", Band, __func__); + + if (channelIndex == -1) + RTW_PRINT("Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__); + + return channelIndex; +} + +static s8 _phy_get_txpwr_lmt( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel, + BOOLEAN no_sc +) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(Adapter); + s8 regulation = -1, bw = -1, rs = -1; + u8 cch = 0; + u8 bw_bmp = 0; + s8 min_lmt = MAX_POWER_INDEX; + s8 tmp_lmt; + u8 final_bw = Bandwidth, final_cch = Channel; + + if ((Adapter->registrypriv.RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory != 1) || + Adapter->registrypriv.RegEnableTxPowerLimit == 0) + goto exit; + + switch (RegPwrTblSel) { + case 1: + regulation = TXPWR_LMT_ETSI; + break; + case 2: + regulation = TXPWR_LMT_MKK; + break; + case 3: + regulation = TXPWR_LMT_FCC; + break; + case 4: + regulation = TXPWR_LMT_WW; + break; + default: + regulation = (Band == BAND_ON_2_4G) ? hal_data->Regulation2_4G : hal_data->Regulation5G; + break; + } + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + RTW_ERR("%s invalid band:%u\n", __func__, Band); + rtw_warn_on(1); + goto exit; + } + + if (IS_CCK_RATE(DataRate)) + rs = CCK; + else if (IS_OFDM_RATE(DataRate)) + rs = OFDM; + else if (IS_HT1SS_RATE(DataRate)) + rs = HT_1SS; + else if (IS_HT2SS_RATE(DataRate)) + rs = HT_2SS; + else if (IS_HT3SS_RATE(DataRate)) + rs = HT_3SS; + else if (IS_HT4SS_RATE(DataRate)) + rs = HT_4SS; + else if (IS_VHT1SS_RATE(DataRate)) + rs = VHT_1SS; + else if (IS_VHT2SS_RATE(DataRate)) + rs = VHT_2SS; + else if (IS_VHT3SS_RATE(DataRate)) + rs = VHT_3SS; + else if (IS_VHT4SS_RATE(DataRate)) + rs = VHT_4SS; + else { + RTW_ERR("%s invalid rate 0x%x\n", __func__, DataRate); + rtw_warn_on(1); + goto exit; + } + + if (Band == BAND_ON_5G && rs == CCK) { + RTW_ERR("Wrong rate No CCK(0x%x) in 5G Band\n", DataRate); + goto exit; + } + + if (no_sc == _TRUE) { + /* use the input center channel and bandwidth directly */ + cch = Channel; + bw_bmp = ch_width_to_bw_cap(Bandwidth); + } else { + /* + * find the possible tx bandwidth bmp for this rate, and then will get center channel for each bandwidth + * if no possible tx bandwidth bmp, select valid bandwidth up to current RF bandwidth into bmp + */ + if (rs == CCK || rs == OFDM) + bw_bmp = BW_CAP_20M; /* CCK, OFDM only BW 20M */ + else if (IS_HT_RATE_SECTION(rs)) { + bw_bmp = rtw_get_tx_bw_bmp_of_ht_rate(dvobj, DataRate, Bandwidth); + if (bw_bmp == 0) + bw_bmp = ch_width_to_bw_cap(Bandwidth > CHANNEL_WIDTH_40 ? CHANNEL_WIDTH_40 : Bandwidth); + } else if (IS_VHT_RATE_SECTION(rs)) { + bw_bmp = rtw_get_tx_bw_bmp_of_vht_rate(dvobj, DataRate, Bandwidth); + if (bw_bmp == 0) + bw_bmp = ch_width_to_bw_cap(Bandwidth > CHANNEL_WIDTH_160 ? CHANNEL_WIDTH_160 : Bandwidth); + } else + rtw_warn_on(1); + } + + if (bw_bmp == 0) + goto exit; + + /* loop for each possible tx bandwidth to find minimum limit */ + for (bw = CHANNEL_WIDTH_20; bw <= Bandwidth; bw++) { + s8 ch_idx; + + if (!(ch_width_to_bw_cap(bw) & bw_bmp)) + continue; + + if (no_sc == _FALSE) { + if (bw == CHANNEL_WIDTH_20) + cch = hal_data->cch_20; + else if (bw == CHANNEL_WIDTH_40) + cch = hal_data->cch_40; + else if (bw == CHANNEL_WIDTH_80) + cch = hal_data->cch_80; + else { + cch = 0; + rtw_warn_on(1); + } + } + + ch_idx = phy_GetChannelIndexOfTxPowerLimit(Band, cch); + if (ch_idx == -1) + continue; + + if (Band == BAND_ON_2_4G) { + s8 limits[MAX_REGULATION_NUM] = {0}; + u8 i = 0; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) + limits[i] = hal_data->TxPwrLimit_2_4G[i][bw][rs][ch_idx][RfPath]; + + tmp_lmt = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : + hal_data->TxPwrLimit_2_4G[regulation][bw][rs][ch_idx][RfPath]; + + } else if (Band == BAND_ON_5G) { + s8 limits[MAX_REGULATION_NUM] = {0}; + u8 i = 0; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) + limits[i] = hal_data->TxPwrLimit_5G[i][bw][rs][ch_idx][RfPath]; + + tmp_lmt = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : + hal_data->TxPwrLimit_5G[regulation][bw][rs][ch_idx][RfPath]; + } else + continue; + + if (min_lmt >= tmp_lmt) { + min_lmt = tmp_lmt; + final_cch = cch; + final_bw = bw; + } + } + +exit: + return min_lmt; +} + +inline s8 +PHY_GetTxPowerLimit( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel +) +{ + BOOLEAN no_sc = _FALSE; + + /* MP mode channel don't use secondary channel */ + if (rtw_mi_mp_mode_check(Adapter) == _TRUE) + no_sc = _TRUE; + + return _phy_get_txpwr_lmt(Adapter, RegPwrTblSel, Band, Bandwidth, RfPath, DataRate, Channel, no_sc); +} + +inline s8 +PHY_GetTxPowerLimit_no_sc( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel +) +{ + return _phy_get_txpwr_lmt(Adapter, RegPwrTblSel, Band, Bandwidth, RfPath, DataRate, Channel, _TRUE); +} + + +VOID +phy_CrossReferenceHTAndVHTTxPowerLimit( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 regulation, bw, channel, rs, ref_rs; + int ht_ref_vht_5g_20_40 = 0; + int vht_ref_ht_5g_20_40 = 0; + int ht_has_ref_5g_20_40 = 0; + int vht_has_ref_5g_20_40 = 0; + + pHalData->tx_pwr_lmt_5g_20_40_ref = 0; + + for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { + + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + + for (rs = 0; rs < MAX_RATE_SECTION_NUM; ++rs) { + + /* 5G 20M 40M VHT and HT can cross reference */ + if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) { + if (rs == HT_1SS) + ref_rs = VHT_1SS; + else if (rs == HT_2SS) + ref_rs = VHT_2SS; + else if (rs == HT_3SS) + ref_rs = VHT_3SS; + else if (rs == HT_4SS) + ref_rs = VHT_4SS; + else if (rs == VHT_1SS) + ref_rs = HT_1SS; + else if (rs == VHT_2SS) + ref_rs = HT_2SS; + else if (rs == VHT_3SS) + ref_rs = HT_3SS; + else if (rs == VHT_4SS) + ref_rs = HT_4SS; + else + continue; + + if (pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A] == MAX_POWER_INDEX) + continue; + + if (IS_HT_RATE_SECTION(rs)) + ht_has_ref_5g_20_40++; + else if (IS_VHT_RATE_SECTION(rs)) + vht_has_ref_5g_20_40++; + else + continue; + + if (pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] != MAX_POWER_INDEX) + continue; + + if (IS_HT_RATE_SECTION(rs) && IS_VHT_RATE_SECTION(ref_rs)) + ht_ref_vht_5g_20_40++; + else if (IS_VHT_RATE_SECTION(rs) && IS_HT_RATE_SECTION(ref_rs)) + vht_ref_ht_5g_20_40++; + + if (0) + RTW_INFO("reg:%u, bw:%u, ch:%u, %s ref %s\n" + , regulation, bw, channel + , rate_section_str(rs), rate_section_str(ref_rs)); + + pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] = + pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A]; + } + + } + } + } + } + + if (0) { + RTW_INFO("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40); + RTW_INFO("vht_ref_hht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40); + } + + /* 5G 20M&40M HT all come from VHT*/ + if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40) + pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_HT_FROM_VHT; + + /* 5G 20M&40M VHT all come from HT*/ + if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40) + pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_VHT_FROM_HT; +} + +VOID +PHY_ConvertTxPowerLimitToPowerIndex( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 base; + u8 regulation, bw, channel, rateSection; + s8 tempValue = 0, tempPwrLmt = 0; + u8 rfPath = 0; + + if (pHalData->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) { + rtw_warn_on(1); + return; + } + + phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter); + + for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + + for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { + + for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + + for (rateSection = CCK; rateSection <= HT_4SS; ++rateSection) { + tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A]; + + if (tempPwrLmt != MAX_POWER_INDEX) { + + for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { + base = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_2_4G, rfPath, rate_section_to_tx_num(rateSection), rateSection); + tempValue = tempPwrLmt - base; + pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue; + } + } + } + } + } + } + + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { + + for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { + + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + + for (rateSection = OFDM; rateSection <= VHT_4SS; ++rateSection) { + tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][RF_PATH_A]; + + if (tempPwrLmt != MAX_POWER_INDEX) { + + for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { + base = PHY_GetTxPowerByRateBase(Adapter, BAND_ON_5G, rfPath, rate_section_to_tx_num(rateSection), rateSection); + tempValue = tempPwrLmt - base; + pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][rfPath] = tempValue; + } + } + } + } + } + } + } +} + +/* +* PHY_InitTxPowerLimit - Set all hal_data.TxPwrLimit_2_4G, TxPwrLimit_5G array to MAX_POWER_INDEX +*/ +VOID +PHY_InitTxPowerLimit( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 i, j, k, l, m; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) + for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) + for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) + for (m = 0; m < CENTER_CH_2G_NUM; ++m) + for (l = 0; l < MAX_RF_PATH; ++l) + pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) + for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) + for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) + for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m) + for (l = 0; l < MAX_RF_PATH; ++l) + pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX; +} + +/* +* phy_set_tx_power_limit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm +*/ +VOID +phy_set_tx_power_limit( + IN struct PHY_DM_STRUCT *pDM_Odm, + IN u8 *Regulation, + IN u8 *Band, + IN u8 *Bandwidth, + IN u8 *RateSection, + IN u8 *RfPath, + IN u8 *Channel, + IN u8 *PowerLimit +) +{ + PADAPTER Adapter = pDM_Odm->adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 regulation = 0, bandwidth = 0, rateSection = 0, channel; + s8 powerLimit = 0, prevPowerLimit, channelIndex; + + if (0) + RTW_INFO("Index of power limit table [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s][val %s]\n" + , Band, Regulation, Bandwidth, RateSection, RfPath, Channel, PowerLimit); + + if (GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel) == _FALSE + || GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit) == _FALSE + ) { + RTW_PRINT("Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit); + return; + } + + powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit; + + if (eqNByte(Regulation, (u8 *)("FCC"), 3)) + regulation = TXPWR_LMT_FCC; + else if (eqNByte(Regulation, (u8 *)("MKK"), 3)) + regulation = TXPWR_LMT_MKK; + else if (eqNByte(Regulation, (u8 *)("ETSI"), 4)) + regulation = TXPWR_LMT_ETSI; + else if (eqNByte(Regulation, (u8 *)("WW13"), 4)) + regulation = TXPWR_LMT_WW; + else { + RTW_PRINT("unknown regulation:%s", Regulation); + return; + } + + if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = CCK; + else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = OFDM; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = HT_1SS; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("2T"), 2)) + rateSection = HT_2SS; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("3T"), 2)) + rateSection = HT_3SS; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("4T"), 2)) + rateSection = HT_4SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = VHT_1SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("2T"), 2)) + rateSection = VHT_2SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("3T"), 2)) + rateSection = VHT_3SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("4T"), 2)) + rateSection = VHT_4SS; + else { + RTW_PRINT("Wrong rate section: (%s,%s)\n", RateSection, RfPath); + return; + } + + if (eqNByte(Bandwidth, (u8 *)("20M"), 3)) + bandwidth = CHANNEL_WIDTH_20; + else if (eqNByte(Bandwidth, (u8 *)("40M"), 3)) + bandwidth = CHANNEL_WIDTH_40; + else if (eqNByte(Bandwidth, (u8 *)("80M"), 3)) + bandwidth = CHANNEL_WIDTH_80; + else { + RTW_PRINT("unknown bandwidth: %s\n", Bandwidth); + return; + } + + if (eqNByte(Band, (u8 *)("2.4G"), 4)) { + channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel); + + if (channelIndex == -1) { + RTW_PRINT("unsupported channel: %d at 2.4G\n", channel); + return; + } + + if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) { + RTW_PRINT("unsupported bandwidth: %s at 2.4G\n", Bandwidth); + return; + } + + prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; + + if (prevPowerLimit != MAX_POWER_INDEX) + RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" + , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); + + if (powerLimit < prevPowerLimit) + pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; + + if (0) + RTW_INFO("2.4G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" + , regulation, bandwidth, rateSection, channelIndex, pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A]); + } else if (eqNByte(Band, (u8 *)("5G"), 2)) { + + channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel); + + if (channelIndex == -1) { + RTW_PRINT("unsupported channel: %d at 5G\n", channel); + return; + } + + prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; + + if (prevPowerLimit != MAX_POWER_INDEX) + RTW_PRINT("duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" + , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); + + if (powerLimit < prevPowerLimit) + pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; + + if (0) + RTW_INFO("5G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" + , regulation, bandwidth, rateSection, channel, pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]); + } else { + RTW_PRINT("Cannot recognize the band info in %s\n", Band); + return; + } +} + +u8 +phy_get_tx_power_index( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel +) +{ + return rtw_hal_get_tx_power_index(pAdapter, RFPath, Rate, BandWidth, Channel, NULL); +} + +VOID +PHY_SetTxPowerIndex( + IN PADAPTER pAdapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate +) +{ + if (IS_HARDWARE_TYPE_8814A(pAdapter)) { + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { + } else if (IS_HARDWARE_TYPE_8822B(pAdapter)) + rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate); + else if (IS_HARDWARE_TYPE_8821C(pAdapter)) + rtw_hal_set_tx_power_index(pAdapter, PowerIndex, RFPath, Rate); +} + +void dump_tx_power_idx_title(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bw = hal_data->current_channel_bw; + + RTW_PRINT_SEL(sel, "%s", ch_width_str(bw)); + if (bw >= CHANNEL_WIDTH_80) + _RTW_PRINT_SEL(sel, ", cch80:%u", hal_data->cch_80); + if (bw >= CHANNEL_WIDTH_40) + _RTW_PRINT_SEL(sel, ", cch40:%u", hal_data->cch_40); + _RTW_PRINT_SEL(sel, ", cch20:%u\n", hal_data->cch_20); + + RTW_PRINT_SEL(sel, "%-4s %-9s %-3s %-4s %-3s %-4s %-4s %-3s %-5s\n" + , "path", "rate", "pwr", "base", "", "(byr", "lmt)", "tpt", "ebias"); +} + +void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 power_idx; + struct txpwr_idx_comp tic; + u8 tx_num, i; + u8 band = hal_data->current_band_type; + u8 cch = hal_data->current_channel; + u8 bw = hal_data->current_channel_bw; + + if (!HAL_SPEC_CHK_RF_PATH(hal_spec, band, rfpath)) + return; + + if (rs >= RATE_SECTION_NUM) + return; + + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->tx_nss_num || tx_num >= hal_spec->max_tx_cnt) + return; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + return; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + return; + + for (i = 0; i < rates_by_sections[rs].rate_num; i++) { + power_idx = rtw_hal_get_tx_power_index(adapter, rfpath, rates_by_sections[rs].rates[i], bw, cch, &tic); + + RTW_PRINT_SEL(sel, "%4c %9s %3u %4u %3d (%3d %3d) %3d %5d\n" + , rf_path_char(rfpath), MGN_RATE_STR(rates_by_sections[rs].rates[i]) + , power_idx, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias); + } +} + +bool phy_is_tx_power_limit_needed(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + + if (regsty->RegEnableTxPowerLimit == 1 + || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1)) + return _TRUE; + return _FALSE; +} + +bool phy_is_tx_power_by_rate_needed(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + + if (regsty->RegEnableTxPowerByRate == 1 + || (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2)) + return _TRUE; + return _FALSE; +} + +int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + int ret = _FAIL; + + hal_data->txpwr_by_rate_loaded = 0; + PHY_InitTxPowerByRate(adapter); + + /* tx power limit is based on tx power by rate */ + hal_data->txpwr_limit_loaded = 0; + + if (chk_file + && phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS + ) { + hal_data->txpwr_by_rate_from_file = 1; + goto post_hdl; + } + + if (HAL_STATUS_SUCCESS == odm_config_bb_with_header_file(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) { + RTW_INFO("default power by rate loaded\n"); + hal_data->txpwr_by_rate_from_file = 0; + goto post_hdl; + } + + RTW_ERR("%s():Read Tx power by rate fail\n", __func__); + goto exit; + +post_hdl: + if (hal_data->odmpriv.phy_reg_pg_value_type != PHY_REG_PG_EXACT_VALUE) { + rtw_warn_on(1); + goto exit; + } + + PHY_TxPowerByRateConfiguration(adapter); + hal_data->txpwr_by_rate_loaded = 1; + + ret = _SUCCESS; + +exit: + return ret; +} + +int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + int ret = _FAIL; + + hal_data->txpwr_limit_loaded = 0; + PHY_InitTxPowerLimit(adapter); + + if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) { + RTW_ERR("%s():Read Tx power limit before target tx power is specify\n", __func__); + goto exit; + } + + if (chk_file + && PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS + ) { + hal_data->txpwr_limit_from_file = 1; + goto post_hdl; + } + + if (HAL_STATUS_SUCCESS == odm_config_rf_with_header_file(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, (enum odm_rf_radio_path_e)0)) { + RTW_INFO("default power limit loaded\n"); + hal_data->txpwr_limit_from_file = 0; + goto post_hdl; + } + + RTW_ERR("%s():Read Tx power limit fail\n", __func__); + goto exit; + +post_hdl: + PHY_ConvertTxPowerLimitToPowerIndex(adapter); + hal_data->txpwr_limit_loaded = 1; + ret = _SUCCESS; + +exit: + return ret; +} + +void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + + /* check registy target tx power */ + regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter); + + /* power by rate and limit */ + if (phy_is_tx_power_by_rate_needed(adapter) + || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE) + ) + phy_load_tx_power_by_rate(adapter, chk_file); + + if (phy_is_tx_power_limit_needed(adapter)) + phy_load_tx_power_limit(adapter, chk_file); +} + +/* + * phy file path is stored in global char array rtw_phy_para_file_path + * need to care about racing + */ +int rtw_get_phy_file_path(_adapter *adapter, const char *file_name) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int len = 0; + + if (file_name) { + len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path); + #if defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER) + len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name); + #endif + len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name); + + return _TRUE; + } + return _FALSE; +} + +int +phy_ConfigMACWithParaFile( + IN PADAPTER Adapter, + IN char *pFileName +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegValue, u4bMove; + + if (!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) { + rtStatus = _SUCCESS; + pHalData->mac_reg = rtw_zvmalloc(rlen); + if (pHalData->mac_reg) { + _rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen); + pHalData->mac_reg_len = rlen; + } else + RTW_INFO("%s mac_reg alloc fail !\n", __FUNCTION__); + } + } + } else { + if ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len); + rtStatus = _SUCCESS; + } else + RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__); + } + + if (rtStatus == _SUCCESS) { + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + if (!IsCommentString(szLine)) { + /* Get 1st hex value as register offset */ + if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) { + if (u4bRegOffset == 0xffff) { + /* Ending. */ + break; + } + + /* Get 2nd hex value as register value. */ + szLine += u4bMove; + if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) + rtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue); + } + } + } + } else + RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + + return rtStatus; +} + +int +phy_ConfigBBWithParaFile( + IN PADAPTER Adapter, + IN char *pFileName, + IN u32 ConfigType +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegValue, u4bMove; + char *pBuf = NULL; + u32 *pBufLen = NULL; + + if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE)) + return rtStatus; + + switch (ConfigType) { + case CONFIG_BB_PHY_REG: + pBuf = pHalData->bb_phy_reg; + pBufLen = &pHalData->bb_phy_reg_len; + break; + case CONFIG_BB_AGC_TAB: + pBuf = pHalData->bb_agc_tab; + pBufLen = &pHalData->bb_agc_tab_len; + break; + default: + RTW_INFO("Unknown ConfigType!! %d\r\n", ConfigType); + break; + } + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) { + rtStatus = _SUCCESS; + pBuf = rtw_zvmalloc(rlen); + if (pBuf) { + _rtw_memcpy(pBuf, pHalData->para_file_buf, rlen); + *pBufLen = rlen; + + switch (ConfigType) { + case CONFIG_BB_PHY_REG: + pHalData->bb_phy_reg = pBuf; + break; + case CONFIG_BB_AGC_TAB: + pHalData->bb_agc_tab = pBuf; + break; + } + } else + RTW_INFO("%s(): ConfigType %d alloc fail !\n", __FUNCTION__, ConfigType); + } + } + } else { + if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen); + rtStatus = _SUCCESS; + } else + RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__); + } + + if (rtStatus == _SUCCESS) { + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + if (!IsCommentString(szLine)) { + /* Get 1st hex value as register offset. */ + if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) { + if (u4bRegOffset == 0xffff) { + /* Ending. */ + break; + } else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) { + rtw_msleep_os(50); + } else if (u4bRegOffset == 0xfd) + rtw_mdelay_os(5); + else if (u4bRegOffset == 0xfc) + rtw_mdelay_os(1); + else if (u4bRegOffset == 0xfb) + rtw_udelay_os(50); + else if (u4bRegOffset == 0xfa) + rtw_udelay_os(5); + else if (u4bRegOffset == 0xf9) + rtw_udelay_os(1); + + /* Get 2nd hex value as register value. */ + szLine += u4bMove; + if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { + /* RTW_INFO("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); */ + phy_set_bb_reg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); + + if (u4bRegOffset == 0xa24) + pHalData->odmpriv.rf_calibrate_info.rega24 = u4bRegValue; + + /* Add 1us delay between BB/RF register setting. */ + rtw_udelay_os(1); + } + } + } + } + } else + RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + + return rtStatus; +} + +VOID +phy_DecryptBBPgParaFile( + PADAPTER Adapter, + char *buffer +) +{ + u32 i = 0, j = 0; + u8 map[95] = {0}; + u8 currentChar; + char *BufOfLines, *ptmp; + + /* RTW_INFO("=====>phy_DecryptBBPgParaFile()\n"); */ + /* 32 the ascii code of the first visable char, 126 the last one */ + for (i = 0; i < 95; ++i) + map[i] = (u8)(94 - i); + + ptmp = buffer; + i = 0; + for (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) { + /* RTW_INFO("Encrypted Line: %s\n", BufOfLines); */ + + for (j = 0; j < strlen(BufOfLines); ++j) { + currentChar = BufOfLines[j]; + + if (currentChar == '\0') + break; + + currentChar -= (u8)((((i + j) * 3) % 128)); + + BufOfLines[j] = map[currentChar - 32] + 32; + } + /* RTW_INFO("Decrypted Line: %s\n", BufOfLines ); */ + if (strlen(BufOfLines) != 0) + i++; + BufOfLines[strlen(BufOfLines)] = '\n'; + } +} + +int +phy_ParseBBPgParaFile( + PADAPTER Adapter, + char *buffer +) +{ + int rtStatus = _SUCCESS; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegMask, u4bRegValue; + u32 u4bMove; + BOOLEAN firstLine = _TRUE; + u8 tx_num = 0; + u8 band = 0, rf_path = 0; + + /* RTW_INFO("=====>phy_ParseBBPgParaFile()\n"); */ + + if (Adapter->registrypriv.RegDecryptCustomFile == 1) + phy_DecryptBBPgParaFile(Adapter, buffer); + + ptmp = buffer; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + if (isAllSpaceOrTab(szLine, sizeof(*szLine))) + continue; + + if (!IsCommentString(szLine)) { + /* Get header info (relative value or exact value) */ + if (firstLine) { + if (eqNByte(szLine, (u8 *)("#[v1]"), 5)) { + + pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0'; + /* RTW_INFO("This is a new format PHY_REG_PG.txt\n"); */ + } else if (eqNByte(szLine, (u8 *)("#[v0]"), 5)) { + pHalData->odmpriv.phy_reg_pg_version = szLine[3] - '0'; + /* RTW_INFO("This is a old format PHY_REG_PG.txt ok\n"); */ + } else { + RTW_INFO("The format in PHY_REG_PG are invalid %s\n", szLine); + return _FAIL; + } + + if (eqNByte(szLine + 5, (u8 *)("[Exact]#"), 8)) { + pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + /* RTW_INFO("The values in PHY_REG_PG are exact values ok\n"); */ + firstLine = _FALSE; + continue; + } else if (eqNByte(szLine + 5, (pu1Byte)("[Relative]#"), 11)) { + pHalData->odmpriv.phy_reg_pg_value_type = PHY_REG_PG_RELATIVE_VALUE; + /* RTW_INFO("The values in PHY_REG_PG are relative values ok\n"); */ + firstLine = _FALSE; + continue; + } else { + RTW_INFO("The values in PHY_REG_PG are invalid %s\n", szLine); + return _FAIL; + } + } + + if (pHalData->odmpriv.phy_reg_pg_version == 0) { + /* Get 1st hex value as register offset. */ + if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) { + szLine += u4bMove; + if (u4bRegOffset == 0xffff) { + /* Ending. */ + break; + } + + /* Get 2nd hex value as register mask. */ + if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) { + /* Get 3rd hex value as register value. */ + if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { + phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, u4bRegValue); + /* RTW_INFO("[ADDR] %03X=%08X Mask=%08x\n", u4bRegOffset, u4bRegValue, u4bRegMask); */ + } else + return _FAIL; + } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) { + u32 combineValue = 0; + u8 integer = 0, fraction = 0; + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue <<= 8; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue <<= 8; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue <<= 8; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + phy_store_tx_power_by_rate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, combineValue); + + /* RTW_INFO("[ADDR] 0x%3x = 0x%4x\n", u4bRegOffset, combineValue ); */ + } + } + } else if (pHalData->odmpriv.phy_reg_pg_version > 0) { + u32 index = 0, cnt = 0; + + if (eqNByte(szLine, "0xffff", 6)) + break; + + if (!eqNByte("#[END]#", szLine, 7)) { + /* load the table label info */ + if (szLine[0] == '#') { + index = 0; + if (eqNByte(szLine, "#[2.4G]" , 7)) { + band = BAND_ON_2_4G; + index += 8; + } else if (eqNByte(szLine, "#[5G]", 5)) { + band = BAND_ON_5G; + index += 6; + } else { + RTW_INFO("Invalid band %s in PHY_REG_PG.txt\n", szLine); + return _FAIL; + } + + rf_path = szLine[index] - 'A'; + /* RTW_INFO(" Table label Band %d, RfPath %d\n", band, rf_path ); */ + } else { /* load rows of tables */ + if (szLine[1] == '1') + tx_num = RF_1TX; + else if (szLine[1] == '2') + tx_num = RF_2TX; + else if (szLine[1] == '3') + tx_num = RF_3TX; + else if (szLine[1] == '4') + tx_num = RF_4TX; + else { + RTW_INFO("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]); + return _FAIL; + } + + while (szLine[index] != ']') + ++index; + ++index;/* skip ] */ + + /* Get 2nd hex value as register offset. */ + szLine += index; + if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + /* Get 2nd hex value as register mask. */ + if (GetHexValueFromString(szLine, &u4bRegMask, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_RELATIVE_VALUE) { + /* Get 3rd hex value as register value. */ + if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { + phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, u4bRegValue); + /* RTW_INFO("[ADDR] %03X (tx_num %d) =%08X Mask=%08x\n", u4bRegOffset, tx_num, u4bRegValue, u4bRegMask); */ + } else + return _FAIL; + } else if (pHalData->odmpriv.phy_reg_pg_value_type == PHY_REG_PG_EXACT_VALUE) { + u32 combineValue = 0; + u8 integer = 0, fraction = 0; + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue <<= 8; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue <<= 8; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + + if (GetFractionValueFromString(szLine, &integer, &fraction, &u4bMove)) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if (fraction == 5) + integer += 1; + combineValue <<= 8; + combineValue |= (((integer / 10) << 4) + (integer % 10)); + /* RTW_INFO(" %d", integer ); */ + phy_store_tx_power_by_rate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue); + + /* RTW_INFO("[ADDR] 0x%3x (tx_num %d) = 0x%4x\n", u4bRegOffset, tx_num, combineValue ); */ + } + } + } + } + } + } + /* RTW_INFO("<=====phy_ParseBBPgParaFile()\n"); */ + return rtStatus; +} + +int +phy_ConfigBBWithPgParaFile( + IN PADAPTER Adapter, + IN const char *pFileName) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + + if (!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if (pHalData->bb_phy_reg_pg == NULL) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) { + rtStatus = _SUCCESS; + pHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen); + if (pHalData->bb_phy_reg_pg) { + _rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen); + pHalData->bb_phy_reg_pg_len = rlen; + } else + RTW_INFO("%s bb_phy_reg_pg alloc fail !\n", __FUNCTION__); + } + } + } else { + if ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len); + rtStatus = _SUCCESS; + } else + RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__); + } + + if (rtStatus == _SUCCESS) { + /* RTW_INFO("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); */ + phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf); + } else + RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + + return rtStatus; +} + +int +PHY_ConfigRFWithParaFile( + IN PADAPTER Adapter, + IN char *pFileName, + IN u8 eRFPath +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegValue, u4bMove; + u16 i; + char *pBuf = NULL; + u32 *pBufLen = NULL; + + if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE)) + return rtStatus; + + switch (eRFPath) { + case ODM_RF_PATH_A: + pBuf = pHalData->rf_radio_a; + pBufLen = &pHalData->rf_radio_a_len; + break; + case ODM_RF_PATH_B: + pBuf = pHalData->rf_radio_b; + pBufLen = &pHalData->rf_radio_b_len; + break; + default: + RTW_INFO("Unknown RF path!! %d\r\n", eRFPath); + break; + } + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) { + rtStatus = _SUCCESS; + pBuf = rtw_zvmalloc(rlen); + if (pBuf) { + _rtw_memcpy(pBuf, pHalData->para_file_buf, rlen); + *pBufLen = rlen; + + switch (eRFPath) { + case ODM_RF_PATH_A: + pHalData->rf_radio_a = pBuf; + break; + case ODM_RF_PATH_B: + pHalData->rf_radio_b = pBuf; + break; + } + } else + RTW_INFO("%s(): eRFPath=%d alloc fail !\n", __FUNCTION__, eRFPath); + } + } + } else { + if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen); + rtStatus = _SUCCESS; + } else + RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__); + } + + if (rtStatus == _SUCCESS) { + /* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */ + + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + if (!IsCommentString(szLine)) { + /* Get 1st hex value as register offset. */ + if (GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) { + if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) { + /* Deay specific ms. Only RF configuration require delay. */ + rtw_msleep_os(50); + } else if (u4bRegOffset == 0xfd) { + /* delay_ms(5); */ + for (i = 0; i < 100; i++) + rtw_udelay_os(MAX_STALL_TIME); + } else if (u4bRegOffset == 0xfc) { + /* delay_ms(1); */ + for (i = 0; i < 20; i++) + rtw_udelay_os(MAX_STALL_TIME); + } else if (u4bRegOffset == 0xfb) + rtw_udelay_os(50); + else if (u4bRegOffset == 0xfa) + rtw_udelay_os(5); + else if (u4bRegOffset == 0xf9) + rtw_udelay_os(1); + else if (u4bRegOffset == 0xffff) + break; + + /* Get 2nd hex value as register value. */ + szLine += u4bMove; + if (GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) { + phy_set_rf_reg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue); + + /* Temp add, for frequency lock, if no delay, that may cause */ + /* frequency shift, ex: 2412MHz => 2417MHz */ + /* If frequency shift, the following action may works. */ + /* Fractional-N table in radio_a.txt */ + /* 0x2a 0x00001 */ /* channel 1 */ + /* 0x2b 0x00808 frequency divider. */ + /* 0x2b 0x53333 */ + /* 0x2c 0x0000c */ + rtw_udelay_os(1); + } + } + } + } + } else + RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + + return rtStatus; +} + +VOID +initDeltaSwingIndexTables( + PADAPTER Adapter, + char *Band, + char *Path, + char *Sign, + char *Channel, + char *Rate, + char *Data +) +{ +#define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \ + ((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\ + (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\ + ) +#define STR_EQUAL_2G(_band, _path, _sign, _rate) \ + ((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\ + (strcmp(Rate, _rate) == 0)\ + ) + +#define STORE_SWING_TABLE(_array, _iteratedIdx) \ + do { \ + for (token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim)) {\ + sscanf(token, "%d", &idx);\ + _array[_iteratedIdx++] = (u8)idx;\ + } } while (0)\ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + u32 j = 0; + char *token; + char delim[] = ","; + u32 idx = 0; + + /* RTW_INFO("===>initDeltaSwingIndexTables(): Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n", */ + /* Band, Path, Sign, Channel, Rate, Data); */ + + if (STR_EQUAL_2G("2G", "A", "+", "CCK")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_p, j); + else if (STR_EQUAL_2G("2G", "A", "-", "CCK")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_a_n, j); + else if (STR_EQUAL_2G("2G", "B", "+", "CCK")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_p, j); + else if (STR_EQUAL_2G("2G", "B", "-", "CCK")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2g_cck_b_n, j); + else if (STR_EQUAL_2G("2G", "A", "+", "ALL")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_p, j); + else if (STR_EQUAL_2G("2G", "A", "-", "ALL")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2ga_n, j); + else if (STR_EQUAL_2G("2G", "B", "+", "ALL")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_p, j); + else if (STR_EQUAL_2G("2G", "B", "-", "ALL")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_2gb_n, j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "0")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[0], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "0")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[0], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "0")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[0], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "0")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[0], j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "1")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[1], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "1")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[1], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "1")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[1], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "1")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[1], j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "2")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[2], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "2")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[2], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "2")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[2], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "2")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[2], j); + else if (STR_EQUAL_5G("5G", "A", "+", "ALL", "3")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_p[3], j); + else if (STR_EQUAL_5G("5G", "A", "-", "ALL", "3")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5ga_n[3], j); + else if (STR_EQUAL_5G("5G", "B", "+", "ALL", "3")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_p[3], j); + else if (STR_EQUAL_5G("5G", "B", "-", "ALL", "3")) + STORE_SWING_TABLE(pRFCalibrateInfo->delta_swing_table_idx_5gb_n[3], j); + else + RTW_INFO("===>initDeltaSwingIndexTables(): The input is invalid!!\n"); +} + +int +PHY_ConfigRFWithTxPwrTrackParaFile( + IN PADAPTER Adapter, + IN char *pFileName +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 i = 0, j = 0; + char c = 0; + + if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) { + rtStatus = _SUCCESS; + pHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen); + if (pHalData->rf_tx_pwr_track) { + _rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen); + pHalData->rf_tx_pwr_track_len = rlen; + } else + RTW_INFO("%s rf_tx_pwr_track alloc fail !\n", __FUNCTION__); + } + } + } else { + if ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len); + rtStatus = _SUCCESS; + } else + RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__); + } + + if (rtStatus == _SUCCESS) { + /* RTW_INFO("%s(): read %s successfully\n", __FUNCTION__, pFileName); */ + + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + if (!IsCommentString(szLine)) { + char band[5] = "", path[5] = "", sign[5] = ""; + char chnl[5] = "", rate[10] = ""; + char data[300] = ""; /* 100 is too small */ + + if (strlen(szLine) < 10 || szLine[0] != '[') + continue; + + strncpy(band, szLine + 1, 2); + strncpy(path, szLine + 5, 1); + strncpy(sign, szLine + 8, 1); + + i = 10; /* szLine+10 */ + if (!ParseQualifiedString(szLine, &i, rate, '[', ']')) { + /* RTW_INFO("Fail to parse rate!\n"); */ + } + if (!ParseQualifiedString(szLine, &i, chnl, '[', ']')) { + /* RTW_INFO("Fail to parse channel group!\n"); */ + } + while (szLine[i] != '{' && i < strlen(szLine)) + i++; + if (!ParseQualifiedString(szLine, &i, data, '{', '}')) { + /* RTW_INFO("Fail to parse data!\n"); */ + } + + initDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data); + } + } + } else + RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + return rtStatus; +} + +int +phy_ParsePowerLimitTableFile( + PADAPTER Adapter, + char *buffer +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + u32 i = 0, forCnt = 0; + u8 loadingStage = 0, limitValue = 0, fraction = 0; + char *szLine, *ptmp; + int rtStatus = _SUCCESS; + char band[10], bandwidth[10], rateSection[10], + regulation[TXPWR_LMT_MAX_REGULATION_NUM][10], rfPath[10], colNumBuf[10]; + u8 colNum = 0; + + RTW_INFO("===>phy_ParsePowerLimitTableFile()\n"); + + if (Adapter->registrypriv.RegDecryptCustomFile == 1) + phy_DecryptBBPgParaFile(Adapter, buffer); + + ptmp = buffer; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + if (isAllSpaceOrTab(szLine, sizeof(*szLine))) + continue; + + /* skip comment */ + if (IsCommentString(szLine)) + continue; + + if (loadingStage == 0) { + for (forCnt = 0; forCnt < TXPWR_LMT_MAX_REGULATION_NUM; ++forCnt) + _rtw_memset((PVOID) regulation[forCnt], 0, 10); + _rtw_memset((PVOID) band, 0, 10); + _rtw_memset((PVOID) bandwidth, 0, 10); + _rtw_memset((PVOID) rateSection, 0, 10); + _rtw_memset((PVOID) rfPath, 0, 10); + _rtw_memset((PVOID) colNumBuf, 0, 10); + + if (szLine[0] != '#' || szLine[1] != '#') + continue; + + /* skip the space */ + i = 2; + while (szLine[i] == ' ' || szLine[i] == '\t') + ++i; + + szLine[--i] = ' '; /* return the space in front of the regulation info */ + + /* Parse the label of the table */ + if (!ParseQualifiedString(szLine, &i, band, ' ', ',')) { + RTW_INFO("Fail to parse band!\n"); + return _FAIL; + } + if (!ParseQualifiedString(szLine, &i, bandwidth, ' ', ',')) { + RTW_INFO("Fail to parse bandwidth!\n"); + return _FAIL; + } + if (!ParseQualifiedString(szLine, &i, rfPath, ' ', ',')) { + RTW_INFO("Fail to parse rf path!\n"); + return _FAIL; + } + if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) { + RTW_INFO("Fail to parse rate!\n"); + return _FAIL; + } + + loadingStage = 1; + } else if (loadingStage == 1) { + if (szLine[0] != '#' || szLine[1] != '#') + continue; + + /* skip the space */ + i = 2; + while (szLine[i] == ' ' || szLine[i] == '\t') + ++i; + + if (!eqNByte((u8 *)(szLine + i), (u8 *)("START"), 5)) { + RTW_INFO("Lost \"## START\" label\n"); + return _FAIL; + } + + loadingStage = 2; + } else if (loadingStage == 2) { + if (szLine[0] != '#' || szLine[1] != '#') + continue; + + /* skip the space */ + i = 2; + while (szLine[i] == ' ' || szLine[i] == '\t') + ++i; + + if (!ParseQualifiedString(szLine, &i, colNumBuf, '#', '#')) { + RTW_INFO("Fail to parse column number!\n"); + return _FAIL; + } + + if (!GetU1ByteIntegerFromStringInDecimal(colNumBuf, &colNum)) + return _FAIL; + + if (colNum > TXPWR_LMT_MAX_REGULATION_NUM) { + RTW_INFO("unvalid col number %d (greater than max %d)\n", + colNum, TXPWR_LMT_MAX_REGULATION_NUM); + return _FAIL; + } + + for (forCnt = 0; forCnt < colNum; ++forCnt) { + u8 regulation_name_cnt = 0; + + /* skip the space */ + while (szLine[i] == ' ' || szLine[i] == '\t') + ++i; + + while (szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0') + regulation[forCnt][regulation_name_cnt++] = szLine[i++]; + /* RTW_INFO("regulation %s!\n", regulation[forCnt]); */ + + if (regulation_name_cnt == 0) { + RTW_INFO("unvalid number of regulation!\n"); + return _FAIL; + } + } + + loadingStage = 3; + } else if (loadingStage == 3) { + char channel[10] = {0}, powerLimit[10] = {0}; + u8 cnt = 0; + + /* the table ends */ + if (szLine[0] == '#' && szLine[1] == '#') { + i = 2; + while (szLine[i] == ' ' || szLine[i] == '\t') + ++i; + + if (eqNByte((u8 *)(szLine + i), (u8 *)("END"), 3)) { + loadingStage = 0; + continue; + } else { + RTW_INFO("Wrong format\n"); + RTW_INFO("<===== phy_ParsePowerLimitTableFile()\n"); + return _FAIL; + } + } + + if ((szLine[0] != 'c' && szLine[0] != 'C') || + (szLine[1] != 'h' && szLine[1] != 'H')) { + RTW_INFO("Meet wrong channel => power limt pair '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]); + continue; + } + i = 2;/* move to the location behind 'h' */ + + /* load the channel number */ + cnt = 0; + while (szLine[i] >= '0' && szLine[i] <= '9') { + channel[cnt] = szLine[i]; + ++cnt; + ++i; + } + /* RTW_INFO("chnl %s!\n", channel); */ + + for (forCnt = 0; forCnt < colNum; ++forCnt) { + /* skip the space between channel number and the power limit value */ + while (szLine[i] == ' ' || szLine[i] == '\t') + ++i; + + /* load the power limit value */ + cnt = 0; + fraction = 0; + _rtw_memset((PVOID) powerLimit, 0, 10); + while ((szLine[i] >= '0' && szLine[i] <= '9') || szLine[i] == '.') { + if (szLine[i] == '.') { + if ((szLine[i + 1] >= '0' && szLine[i + 1] <= '9')) { + fraction = szLine[i + 1]; + i += 2; + } else { + RTW_INFO("Wrong fraction in TXPWR_LMT.txt\n"); + return _FAIL; + } + + break; + } + + powerLimit[cnt] = szLine[i]; + ++cnt; + ++i; + } + + if (powerLimit[0] == '\0') { + powerLimit[0] = '6'; + powerLimit[1] = '3'; + i += 2; + } else { + if (!GetU1ByteIntegerFromStringInDecimal(powerLimit, &limitValue)) + return _FAIL; + + limitValue *= 2; + cnt = 0; + if (fraction == '5') + ++limitValue; + + /* the value is greater or equal to 100 */ + if (limitValue >= 100) { + powerLimit[cnt++] = limitValue / 100 + '0'; + limitValue %= 100; + + if (limitValue >= 10) { + powerLimit[cnt++] = limitValue / 10 + '0'; + limitValue %= 10; + } else + powerLimit[cnt++] = '0'; + + powerLimit[cnt++] = limitValue + '0'; + } + /* the value is greater or equal to 10 */ + else if (limitValue >= 10) { + powerLimit[cnt++] = limitValue / 10 + '0'; + limitValue %= 10; + powerLimit[cnt++] = limitValue + '0'; + } + /* the value is less than 10 */ + else + powerLimit[cnt++] = limitValue + '0'; + + powerLimit[cnt] = '\0'; + } + + /* RTW_INFO("ch%s => %s\n", channel, powerLimit); */ + + /* store the power limit value */ + phy_set_tx_power_limit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band, + (u8 *)bandwidth, (u8 *)rateSection, (u8 *)rfPath, (u8 *)channel, (u8 *)powerLimit); + + } + } else { + RTW_INFO("Abnormal loading stage in phy_ParsePowerLimitTableFile()!\n"); + rtStatus = _FAIL; + break; + } + } + + RTW_INFO("<===phy_ParsePowerLimitTableFile()\n"); + return rtStatus; +} + +int +PHY_ConfigRFWithPowerLimitTableParaFile( + IN PADAPTER Adapter, + IN const char *pFileName +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + + if (!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if (pHalData->rf_tx_pwr_lmt == NULL) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) { + rtStatus = _SUCCESS; + pHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen); + if (pHalData->rf_tx_pwr_lmt) { + _rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen); + pHalData->rf_tx_pwr_lmt_len = rlen; + } else + RTW_INFO("%s rf_tx_pwr_lmt alloc fail !\n", __FUNCTION__); + } + } + } else { + if ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len); + rtStatus = _SUCCESS; + } else + RTW_INFO("%s(): Critical Error !!!\n", __FUNCTION__); + } + + if (rtStatus == _SUCCESS) { + /* RTW_INFO("%s(): read %s ok\n", __FUNCTION__, pFileName); */ + rtStatus = phy_ParsePowerLimitTableFile(Adapter, pHalData->para_file_buf); + } else + RTW_INFO("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + + return rtStatus; +} + +void phy_free_filebuf_mask(_adapter *padapter, u8 mask) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) { + rtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len); + pHalData->mac_reg = NULL; + } + if (mask & LOAD_BB_PARA_FILE) { + if (pHalData->bb_phy_reg) { + rtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len); + pHalData->bb_phy_reg = NULL; + } + if (pHalData->bb_agc_tab) { + rtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len); + pHalData->bb_agc_tab = NULL; + } + } + if (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) { + rtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len); + pHalData->bb_phy_reg_pg = NULL; + } + if (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) { + rtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len); + pHalData->bb_phy_reg_mp = NULL; + } + if (mask & LOAD_RF_PARA_FILE) { + if (pHalData->rf_radio_a) { + rtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len); + pHalData->rf_radio_a = NULL; + } + if (pHalData->rf_radio_b) { + rtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len); + pHalData->rf_radio_b = NULL; + } + } + if (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) { + rtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len); + pHalData->rf_tx_pwr_track = NULL; + } + if (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) { + rtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len); + pHalData->rf_tx_pwr_lmt = NULL; + } +} + +inline void phy_free_filebuf(_adapter *padapter) +{ + phy_free_filebuf_mask(padapter, 0xFF); +} + diff --git a/drivers/staging/rtl8821ce/hal/hal_dm.c b/drivers/staging/rtl8821ce/hal/hal_dm.c new file mode 100644 index 000000000000..b69cd8d2e961 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_dm.c @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2014 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <hal_data.h> + +void Init_ODM_ComInfo(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + int i; + + _rtw_memset(pDM_Odm, 0, sizeof(*pDM_Odm)); + + pDM_Odm->adapter = adapter; + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE); + + rtw_odm_init_ic_type(adapter); + + if (rtw_get_intf_type(adapter) == RTW_GSPI) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO); + else + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter)); + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->version_id)); + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID); + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec); + + if (pHalData->rf_type == RF_1T1R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R); + else if (pHalData->rf_type == RF_1T2R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R); + else if (pHalData->rf_type == RF_2T2R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R); + else if (pHalData->rf_type == RF_2T2R_GREEN) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN); + else if (pHalData->rf_type == RF_2T3R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T3R); + else if (pHalData->rf_type == RF_2T4R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T4R); + else if (pHalData->rf_type == RF_3T3R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T3R); + else if (pHalData->rf_type == RF_3T4R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T4R); + else if (pHalData->rf_type == RF_4T4R) + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_4T4R); + else + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_XTXR); + + { + /* 1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= */ + u8 odm_board_type = ODM_BOARD_DEFAULT; + + if (pHalData->ExternalLNA_2G != 0) { + odm_board_type |= ODM_BOARD_EXT_LNA; + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1); + } + if (pHalData->external_lna_5g != 0) { + odm_board_type |= ODM_BOARD_EXT_LNA_5G; + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1); + } + if (pHalData->ExternalPA_2G != 0) { + odm_board_type |= ODM_BOARD_EXT_PA; + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_PA, 1); + } + if (pHalData->external_pa_5g != 0) { + odm_board_type |= ODM_BOARD_EXT_PA_5G; + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1); + } + if (pHalData->EEPROMBluetoothCoexist) + odm_board_type |= ODM_BOARD_BT; + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type); + /* 1 ============== End of BoardType ============== */ + } + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); + + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA); + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->rfe_type); + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0); + + /*Add by YuChen for kfree init*/ + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_REGRFKFREEENABLE, adapter->registrypriv.RegPwrTrimEnable); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RFKFREEENABLE, pHalData->RfKFreeEnable); + + /*Antenna diversity relative parameters*/ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_DIV, &(pHalData->AntDivCfg)); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_BE_FIX_TX_ANT, pHalData->b_fix_tx_ant); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, pHalData->with_extenal_ant_switch); + + /* (8822B) efuse 0x3D7 & 0x3D8 for TX PA bias */ + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D7, pHalData->efuse0x3d7); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_EFUSE0X3D8, pHalData->efuse0x3d8); + + /*Add by YuChen for adaptivity init*/ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ADAPTIVITY, &(adapter->registrypriv.adaptivity_en)); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE, (adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DCBACKOFF, adapter->registrypriv.adaptivity_dc_backoff); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, (adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_L2H_INI, adapter->registrypriv.adaptivity_th_l2h_ini); + phydm_adaptivity_info_init(pDM_Odm, PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, adapter->registrypriv.adaptivity_th_edcca_hl_diff); + +#ifdef CONFIG_IQK_PA_OFF + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKPAOFF, 1); +#endif + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKFWOFFLOAD, pHalData->RegIQKFWOffload); + + /* Pointer reference */ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->current_band_type)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); + + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->current_channel_bw)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_CHNL, &(pHalData->current_channel)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); + + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving)); + /*Add by Yuchen for phydm beamforming*/ + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp)); + odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_ANT_TEST, &(pHalData->antenna_test)); + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + odm_cmn_info_ptr_array_hook(pDM_Odm, ODM_CMNINFO_STA_STATUS, i, NULL); + + phydm_init_debug_setting(pDM_Odm); + + /* TODO */ + /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_OPERATION, _FALSE); */ + /* odm_cmn_info_hook(pDM_Odm, ODM_CMNINFO_BT_DISABLE_EDCA, _FALSE); */ +} + +static u32 edca_setting_UL[HT_IOT_PEER_MAX] = +/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/ +/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(DownLink/Tx) */ +{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; + +static u32 edca_setting_DL[HT_IOT_PEER_MAX] = +/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/ +/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP(UpLink/Rx)*/ +{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; + +static u32 edca_setting_dl_g_mode[HT_IOT_PEER_MAX] = +/*UNKNOWN, REALTEK_90, REALTEK_92SE, BROADCOM,*/ +/*RALINK, ATHEROS, CISCO, MERU, MARVELL, 92U_AP, SELF_AP */ +{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; + +void rtw_hal_turbo_edca(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct recv_priv *precvpriv = &(adapter->recvpriv); + struct registry_priv *pregpriv = &adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* Parameter suggested by Scott */ + u32 EDCA_BE_UL = 0x5ea42b; + u32 EDCA_BE_DL = 0x00a42b; + u8 ic_type = rtw_get_chip_type(adapter); + + u8 iot_peer = 0; + u8 wireless_mode = 0xFF; /* invalid value */ + u8 traffic_index; + u32 edca_param; + u64 cur_tx_bytes = 0; + u64 cur_rx_bytes = 0; + u8 bbtchange = _TRUE; + u8 is_bias_on_rx = _FALSE; + u8 is_linked = _FALSE; + u8 interface_type; + + if (hal_data->dis_turboedca) + return; + + if (rtw_mi_check_status(adapter, MI_ASSOC)) + is_linked = _TRUE; + + if (is_linked != _TRUE) { + precvpriv->is_any_non_be_pkts = _FALSE; + return; + } + + if ((pregpriv->wifi_spec == 1)) { /* || (pmlmeinfo->HT_enable == 0)) */ + precvpriv->is_any_non_be_pkts = _FALSE; + return; + } + + interface_type = rtw_get_intf_type(adapter); + wireless_mode = pmlmeext->cur_wireless_mode; + + iot_peer = pmlmeinfo->assoc_AP_vendor; + + if (iot_peer >= HT_IOT_PEER_MAX) { + precvpriv->is_any_non_be_pkts = _FALSE; + return; + } + + if (ic_type == RTL8188E) { + if ((iot_peer == HT_IOT_PEER_RALINK) || (iot_peer == HT_IOT_PEER_ATHEROS)) + is_bias_on_rx = _TRUE; + } + + /* Check if the status needs to be changed. */ + if ((bbtchange) || (!precvpriv->is_any_non_be_pkts)) { + cur_tx_bytes = dvobj->traffic_stat.cur_tx_bytes; + cur_rx_bytes = dvobj->traffic_stat.cur_rx_bytes; + + /* traffic, TX or RX */ + if (is_bias_on_rx) { + if (cur_tx_bytes > (cur_rx_bytes << 2)) { + /* Uplink TP is present. */ + traffic_index = UP_LINK; + } else { + /* Balance TP is present. */ + traffic_index = DOWN_LINK; + } + } else { + if (cur_rx_bytes > (cur_tx_bytes << 2)) { + /* Downlink TP is present. */ + traffic_index = DOWN_LINK; + } else { + /* Balance TP is present. */ + traffic_index = UP_LINK; + } + } + { + if (interface_type == RTW_PCIE) { + EDCA_BE_UL = 0x6ea42b; + EDCA_BE_DL = 0x6ea42b; + } + + /* 92D txop can't be set to 0x3e for cisco1250 */ + if ((iot_peer == HT_IOT_PEER_CISCO) && (wireless_mode == ODM_WM_N24G)) { + EDCA_BE_DL = edca_setting_DL[iot_peer]; + EDCA_BE_UL = edca_setting_UL[iot_peer]; + } + /* merge from 92s_92c_merge temp*/ + else if ((iot_peer == HT_IOT_PEER_CISCO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == (ODM_WM_B | ODM_WM_G)) || (wireless_mode == ODM_WM_A) || (wireless_mode == ODM_WM_B))) + EDCA_BE_DL = edca_setting_dl_g_mode[iot_peer]; + else if ((iot_peer == HT_IOT_PEER_AIRGO) && ((wireless_mode == ODM_WM_G) || (wireless_mode == ODM_WM_A))) + EDCA_BE_DL = 0xa630; + else if (iot_peer == HT_IOT_PEER_MARVELL) { + EDCA_BE_DL = edca_setting_DL[iot_peer]; + EDCA_BE_UL = edca_setting_UL[iot_peer]; + } else if (iot_peer == HT_IOT_PEER_ATHEROS) { + /* Set DL EDCA for Atheros peer to 0x3ea42b.*/ + /* Suggested by SD3 Wilson for ASUS TP issue.*/ + EDCA_BE_DL = edca_setting_DL[iot_peer]; + } + + if ((ic_type == RTL8812) || (ic_type == RTL8821) || (ic_type == RTL8192E)) { /* add 8812AU/8812AE */ + EDCA_BE_UL = 0x5ea42b; + EDCA_BE_DL = 0x5ea42b; + + RTW_DBG("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x\n", EDCA_BE_UL, EDCA_BE_DL); + } + + if (interface_type == RTW_PCIE && + (ic_type == RTL8822B)) { + EDCA_BE_UL = 0x6ea42b; + EDCA_BE_DL = 0x6ea42b; + } + + if (traffic_index == DOWN_LINK) + edca_param = EDCA_BE_DL; + else + edca_param = EDCA_BE_UL; + + rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param)); + + RTW_DBG("Turbo EDCA =0x%x\n", edca_param); + + hal_data->prv_traffic_idx = traffic_index; + } + + hal_data->is_turbo_edca = _TRUE; + } else { + /* */ + /* Turn Off EDCA turbo here. */ + /* Restore original EDCA according to the declaration of AP. */ + /* */ + if (hal_data->is_turbo_edca) { + edca_param = hal_data->ac_param_be; + rtw_hal_set_hwreg(adapter, HW_VAR_AC_PARAM_BE, (u8 *)(&edca_param)); + hal_data->is_turbo_edca = _FALSE; + } + } + +} + diff --git a/drivers/staging/rtl8821ce/hal/hal_dm.h b/drivers/staging/rtl8821ce/hal/hal_dm.h new file mode 100644 index 000000000000..6a6cc2779df6 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_dm.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_DM_H__ +#define __HAL_DM_H__ + +void Init_ODM_ComInfo(_adapter *adapter); +void rtw_hal_turbo_edca(_adapter *adapter); + +#endif /* __HAL_DM_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/hal_halmac.c b/drivers/staging/rtl8821ce/hal/hal_halmac.c new file mode 100644 index 000000000000..be1acb7d15f2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_halmac.c @@ -0,0 +1,1832 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_HALMAC_C_ + +#include <drv_types.h> /* PADAPTER, struct dvobj_priv, SDIO_ERR_VAL8 and etc. */ +#include <hal_data.h> /* efuse, PHAL_DATA_TYPE and etc. */ +#include "halmac/halmac_api.h" /* HALMAC_FW_SIZE_MAX_88XX and etc. */ +#include "hal_halmac.h" /* dvobj_to_halmac() and ect. */ + +#define DEFAULT_INDICATOR_TIMELMT 1000 /* ms */ +#define FIRMWARE_MAX_SIZE HALMAC_FW_SIZE_MAX_88XX +#define MSG_PREFIX "[HALMAC]" + +/* + * Driver API for HALMAC operations + */ + +static u8 _halmac_reg_read_8(void *p, u32 offset) +{ + struct dvobj_priv *d; + PADAPTER adapter; + + d = (struct dvobj_priv *)p; + adapter = dvobj_get_primary_adapter(d); + + return rtw_read8(adapter, offset); +} + +static u16 _halmac_reg_read_16(void *p, u32 offset) +{ + struct dvobj_priv *d; + PADAPTER adapter; + + d = (struct dvobj_priv *)p; + adapter = dvobj_get_primary_adapter(d); + + return rtw_read16(adapter, offset); +} + +static u32 _halmac_reg_read_32(void *p, u32 offset) +{ + struct dvobj_priv *d; + PADAPTER adapter; + + d = (struct dvobj_priv *)p; + adapter = dvobj_get_primary_adapter(d); + + return rtw_read32(adapter, offset); +} + +static void _halmac_reg_write_8(void *p, u32 offset, u8 val) +{ + struct dvobj_priv *d; + PADAPTER adapter; + int err; + + d = (struct dvobj_priv *)p; + adapter = dvobj_get_primary_adapter(d); + + err = rtw_write8(adapter, offset, val); + if (err == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); +} + +static void _halmac_reg_write_16(void *p, u32 offset, u16 val) +{ + struct dvobj_priv *d; + PADAPTER adapter; + int err; + + d = (struct dvobj_priv *)p; + adapter = dvobj_get_primary_adapter(d); + + err = rtw_write16(adapter, offset, val); + if (err == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); +} + +static void _halmac_reg_write_32(void *p, u32 offset, u32 val) +{ + struct dvobj_priv *d; + PADAPTER adapter; + int err; + + d = (struct dvobj_priv *)p; + adapter = dvobj_get_primary_adapter(d); + + err = rtw_write32(adapter, offset, val); + if (err == _FAIL) + RTW_ERR("%s: I/O FAIL!\n", __FUNCTION__); +} + +static u8 _halmac_mfree(void *p, void *buffer, u32 size) +{ + rtw_mfree(buffer, size); + return _TRUE; +} + +static void *_halmac_malloc(void *p, u32 size) +{ + return rtw_zmalloc(size); +} + +static u8 _halmac_memcpy(void *p, void *dest, void *src, u32 size) +{ + _rtw_memcpy(dest, src, size); + return _TRUE; +} + +static u8 _halmac_memset(void *p, void *addr, u8 value, u32 size) +{ + _rtw_memset(addr, value, size); + return _TRUE; +} + +static void _halmac_udelay(void *p, u32 us) +{ + rtw_udelay_os(us); +} + +static u8 _halmac_mutex_init(void *p, HALMAC_MUTEX *pMutex) +{ + _rtw_mutex_init(pMutex); + return _TRUE; +} + +static u8 _halmac_mutex_deinit(void *p, HALMAC_MUTEX *pMutex) +{ + _rtw_mutex_free(pMutex); + return _TRUE; +} + +static u8 _halmac_mutex_lock(void *p, HALMAC_MUTEX *pMutex) +{ + int err; + + err = _enter_critical_mutex(pMutex, NULL); + if (err) + return _FALSE; + + return _TRUE; +} + +static u8 _halmac_mutex_unlock(void *p, HALMAC_MUTEX *pMutex) +{ + _exit_critical_mutex(pMutex, NULL); + return _TRUE; +} + +static u8 _halmac_msg_print(void *p, u32 msg_type, u8 msg_level, s8 *fmt, ...) +{ +#define MSG_LEN 100 + va_list args; + u8 str[MSG_LEN] = {0}; + int err; + u8 ret = _TRUE; + + str[0] = '\n'; + va_start(args, fmt); + err = vsnprintf(str, MSG_LEN, fmt, args); + va_end(args); + + /* An output error is encountered */ + if (err < 0) + return _FALSE; + /* Output may be truncated due to size limit */ + if ((err == (MSG_LEN - 1)) && (str[MSG_LEN - 2] != '\n')) + ret = _FALSE; + + if (msg_level == HALMAC_DBG_ALWAYS) + RTW_PRINT(MSG_PREFIX "%s", str); + else if (msg_level <= HALMAC_DBG_ERR) + RTW_ERR(MSG_PREFIX "%s", str); + else if (msg_level <= HALMAC_DBG_WARN) + RTW_WARN(MSG_PREFIX "%s", str); + else + RTW_DBG(MSG_PREFIX "%s", str); + + return ret; +} + +static u8 _halmac_buff_print(void *p, u32 msg_type, u8 msg_level, s8 *buf, u32 size) +{ + if (msg_level <= HALMAC_DBG_WARN) + RTW_INFO_DUMP(MSG_PREFIX, buf, size); + else + RTW_DBG_DUMP(MSG_PREFIX, buf, size); + + return _TRUE; +} + +const char *const RTW_HALMAC_FEATURE_NAME[] = { + "HALMAC_FEATURE_CFG_PARA", + "HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE", + "HALMAC_FEATURE_DUMP_LOGICAL_EFUSE", + "HALMAC_FEATURE_UPDATE_PACKET", + "HALMAC_FEATURE_UPDATE_DATAPACK", + "HALMAC_FEATURE_RUN_DATAPACK", + "HALMAC_FEATURE_CHANNEL_SWITCH", + "HALMAC_FEATURE_IQK", + "HALMAC_FEATURE_POWER_TRACKING", + "HALMAC_FEATURE_PSD", + "HALMAC_FEATURE_ALL" +}; + +static inline u8 is_valid_id_status(HALMAC_FEATURE_ID id, HALMAC_CMD_PROCESS_STATUS status) +{ + switch (id) { + case HALMAC_FEATURE_CFG_PARA: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + if (HALMAC_CMD_PROCESS_DONE != status) + RTW_INFO("%s: id(%d) unspecified status(%d)!\n", + __FUNCTION__, id, status); + break; + case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + if (HALMAC_CMD_PROCESS_DONE != status) + RTW_INFO("%s: id(%d) unspecified status(%d)!\n", + __FUNCTION__, id, status); + break; + case HALMAC_FEATURE_UPDATE_PACKET: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_UPDATE_DATAPACK: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_RUN_DATAPACK: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_CHANNEL_SWITCH: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_IQK: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_POWER_TRACKING: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_PSD: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + case HALMAC_FEATURE_ALL: + RTW_INFO("%s: %s\n", __FUNCTION__, RTW_HALMAC_FEATURE_NAME[id]); + break; + default: + RTW_ERR("%s: unknown feature id(%d)\n", __FUNCTION__, id); + return _FALSE; + } + + return _TRUE; +} + +static int init_halmac_event_with_waittime(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size, u32 time) +{ + struct submit_ctx *sctx; + + if (!d->hmpriv.indicator[id].sctx) { + sctx = (struct submit_ctx *)rtw_zmalloc(sizeof(*sctx)); + if (!sctx) + return -1; + } else { + RTW_WARN("%s: id(%d) sctx is not NULL!!\n", __FUNCTION__, id); + sctx = d->hmpriv.indicator[id].sctx; + d->hmpriv.indicator[id].sctx = NULL; + } + + rtw_sctx_init(sctx, time); + d->hmpriv.indicator[id].buffer = buf; + d->hmpriv.indicator[id].buf_size = size; + d->hmpriv.indicator[id].ret_size = 0; + d->hmpriv.indicator[id].status = 0; + /* fill sctx at least to sure other variables are all ready! */ + d->hmpriv.indicator[id].sctx = sctx; + + return 0; +} + +static inline int init_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id, u8 *buf, u32 size) +{ + return init_halmac_event_with_waittime(d, id, buf, size, DEFAULT_INDICATOR_TIMELMT); +} + +static void free_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) +{ + struct submit_ctx *sctx; + + if (!d->hmpriv.indicator[id].sctx) + return; + + sctx = d->hmpriv.indicator[id].sctx; + d->hmpriv.indicator[id].sctx = NULL; + rtw_mfree((u8 *)sctx, sizeof(*sctx)); +} + +static int wait_halmac_event(struct dvobj_priv *d, HALMAC_FEATURE_ID id) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + struct submit_ctx *sctx; + int ret; + + sctx = d->hmpriv.indicator[id].sctx; + if (!sctx) + return -1; + + ret = rtw_sctx_wait(sctx, RTW_HALMAC_FEATURE_NAME[id]); + free_halmac_event(d, id); + if (_SUCCESS == ret) + return 0; + + /* timeout! We have to reset halmac state */ + RTW_ERR("%s: Wait id(%d, %s) TIMEOUT! Reset HALMAC state!\n", + __FUNCTION__, id, RTW_HALMAC_FEATURE_NAME[id]); + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + api->halmac_reset_feature(mac, id); + + return -1; +} + +/* + * Return: + * Always return _TRUE, HALMAC don't care the return value. + */ +static u8 _halmac_event_indication(void *p, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size) +{ + struct dvobj_priv *d; + PADAPTER adapter; + PHAL_DATA_TYPE hal; + struct halmac_indicator *tbl, *indicator; + struct submit_ctx *sctx; + u32 cpsz; + u8 ret; + + d = (struct dvobj_priv *)p; + adapter = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(adapter); + tbl = d->hmpriv.indicator; + + /* Filter(Skip) middle status indication */ + ret = is_valid_id_status(feature_id, process_status); + if (_FALSE == ret) + goto exit; + + indicator = &tbl[feature_id]; + indicator->status = process_status; + indicator->ret_size = size; + if (!indicator->sctx) { + RTW_WARN("%s: No feature id(%d, %s) waiting!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]); + goto exit; + } + sctx = indicator->sctx; + + if (HALMAC_CMD_PROCESS_ERROR == process_status) { + RTW_ERR("%s: Something wrong id(%d, %s)!!\n", __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id]); + rtw_sctx_done_err(&sctx, RTW_SCTX_DONE_UNKNOWN); + goto exit; + } + + if (size > indicator->buf_size) { + RTW_WARN("%s: id(%d, %s) buffer is not enough(%d<%d), data will be truncated!\n", + __FUNCTION__, feature_id, RTW_HALMAC_FEATURE_NAME[feature_id], indicator->buf_size, size); + cpsz = indicator->buf_size; + } else { + cpsz = size; + } + if (cpsz && indicator->buffer) + _rtw_memcpy(indicator->buffer, buf, cpsz); + + rtw_sctx_done(&sctx); + +exit: + return _TRUE; +} + +HALMAC_PLATFORM_API rtw_halmac_platform_api = { + /* R/W register */ + .REG_READ_8 = _halmac_reg_read_8, + .REG_READ_16 = _halmac_reg_read_16, + .REG_READ_32 = _halmac_reg_read_32, + .REG_WRITE_8 = _halmac_reg_write_8, + .REG_WRITE_16 = _halmac_reg_write_16, + .REG_WRITE_32 = _halmac_reg_write_32, + + /* Write data */ + /* Memory allocate */ + .RTL_FREE = _halmac_mfree, + .RTL_MALLOC = _halmac_malloc, + .RTL_MEMCPY = _halmac_memcpy, + .RTL_MEMSET = _halmac_memset, + + /* Sleep */ + .RTL_DELAY_US = _halmac_udelay, + + /* Process Synchronization */ + .MUTEX_INIT = _halmac_mutex_init, + .MUTEX_DEINIT = _halmac_mutex_deinit, + .MUTEX_LOCK = _halmac_mutex_lock, + .MUTEX_UNLOCK = _halmac_mutex_unlock, + + .MSG_PRINT = _halmac_msg_print, + .BUFF_PRINT = _halmac_buff_print, + .EVENT_INDICATION = _halmac_event_indication, +}; + +static int init_priv(struct halmacpriv *priv) +{ + struct halmac_indicator *indicator; + u32 count, size; + + size = sizeof(*priv); + _rtw_memset(priv, 0, size); + + count = HALMAC_FEATURE_ALL + 1; + size = sizeof(*indicator) * count; + indicator = (struct halmac_indicator *)rtw_zmalloc(size); + if (!indicator) + return -1; + priv->indicator = indicator; + + return 0; +} + +static void deinit_priv(struct halmacpriv *priv) +{ + struct halmac_indicator *indicator; + + indicator = priv->indicator; + priv->indicator = NULL; + if (indicator) { + u32 count, size; + + count = HALMAC_FEATURE_ALL + 1; + { + struct submit_ctx *sctx; + u32 i; + + for (i = 0; i < count; i++) { + if (!indicator[i].sctx) + continue; + + RTW_WARN("%s: %s id(%d) sctx still exist!!\n", + __FUNCTION__, RTW_HALMAC_FEATURE_NAME[i], i); + sctx = indicator[i].sctx; + indicator[i].sctx = NULL; + rtw_mfree((u8 *)sctx, sizeof(*sctx)); + } + } + size = sizeof(*indicator) * count; + rtw_mfree((u8 *)indicator, size); + } +} + +int rtw_halmac_init_adapter(struct dvobj_priv *d, PHALMAC_PLATFORM_API pf_api) +{ + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_INTERFACE intf; + HALMAC_RET_STATUS status; + int err = 0; + + halmac = dvobj_to_halmac(d); + if (halmac) { + err = 0; + goto out; + } + + err = init_priv(&d->hmpriv); + if (err) + goto out; + + intf = HALMAC_INTERFACE_PCIE; + status = halmac_init_adapter(d, pf_api, intf, &halmac, &api); + if (HALMAC_RET_SUCCESS != status) { + RTW_ERR("%s: halmac_init_adapter fail!(status=%d)\n", __FUNCTION__, status); + err = -1; + goto out; + } + + dvobj_set_halmac(d, halmac); + + status = api->halmac_phy_cfg(halmac, HALMAC_INTF_PHY_PLATFORM_ALL); + if (status != HALMAC_RET_SUCCESS) { + RTW_ERR("%s: halmac_phy_cfg fail!(status=%d)\n", __FUNCTION__, status); + err = -1; + goto out; + } + +out: + if (err) + rtw_halmac_deinit_adapter(d); + + return err; +} + +int rtw_halmac_deinit_adapter(struct dvobj_priv *d) +{ + PHALMAC_ADAPTER halmac; + HALMAC_RET_STATUS status; + int err = 0; + + halmac = dvobj_to_halmac(d); + if (!halmac) { + err = 0; + goto out; + } + + deinit_priv(&d->hmpriv); + + status = halmac_deinit_adapter(halmac); + dvobj_set_halmac(d, NULL); + if (status != HALMAC_RET_SUCCESS) { + err = -1; + goto out; + } + +out: + return err; +} + +/* + * Description: + * Power on device hardware. + * [Notice!] If device's power state is on before, + * it would be power off first and turn on power again. + * + * Return: + * 0 power on success + * -1 power on fail + * -2 power state unchange + */ +int rtw_halmac_poweron(struct dvobj_priv *d) +{ + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + int err = -1; + + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + + api = HALMAC_GET_API(halmac); + + status = api->halmac_pre_init_system_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); + if (HALMAC_RET_PWR_UNCHANGE == status) { + /* + * Work around for warm reboot but device not power off, + * but it would also fall into this case when auto power on is enabled. + */ + api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_ON); + RTW_WARN("%s: Power state abnormal, try to recover...%s\n", + __FUNCTION__, (HALMAC_RET_SUCCESS == status)?"OK":"FAIL!"); + } + if (HALMAC_RET_SUCCESS != status) { + if (HALMAC_RET_PWR_UNCHANGE == status) + err = -2; + goto out; + } + + status = api->halmac_init_system_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/* + * Description: + * Power off device hardware. + * + * Return: + * 0 Power off success + * -1 Power off fail + */ +int rtw_halmac_poweroff(struct dvobj_priv *d) +{ + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + int err = -1; + + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + + api = HALMAC_GET_API(halmac); + + status = api->halmac_mac_power_switch(halmac, HALMAC_MAC_POWER_OFF); + if ((HALMAC_RET_SUCCESS != status) + && (HALMAC_RET_PWR_UNCHANGE != status)) + goto out; + + err = 0; +out: + return err; +} + +/* + * Note: + * When this function return, the register REG_RCR may be changed. + */ +int rtw_halmac_config_rx_info(struct dvobj_priv *d, HALMAC_DRV_INFO info) +{ + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + int err = -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + status = api->halmac_cfg_drv_info(halmac, info); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + + +static u8 _get_drv_rsvd_page(HALMAC_DRV_RSVD_PG_NUM rsvd_page_number) +{ + if (HALMAC_RSVD_PG_NUM16 == rsvd_page_number) + return 16; + else if (HALMAC_RSVD_PG_NUM24 == rsvd_page_number) + return 24; + else if (HALMAC_RSVD_PG_NUM32 == rsvd_page_number) + return 32; + + RTW_ERR("%s unknown HALMAC_RSVD_PG type :%d\n", __func__, rsvd_page_number); + rtw_warn_on(1); + return 0; +} + +static HALMAC_TRX_MODE _choose_trx_mode(struct dvobj_priv *d) +{ + PADAPTER p; + + p = dvobj_get_primary_adapter(d); + + if (p->registrypriv.wifi_spec) + return HALMAC_TRX_MODE_WMM; + + + return HALMAC_TRX_MODE_NORMAL; +} + +static inline HALMAC_RF_TYPE _rf_type_drv2halmac(RT_RF_TYPE_DEF_E rf_drv) +{ + HALMAC_RF_TYPE rf_mac; + + switch (rf_drv) { + case RF_1T2R: + rf_mac = HALMAC_RF_1T2R; + break; + case RF_2T4R: + rf_mac = HALMAC_RF_2T4R; + break; + case RF_2T2R: + rf_mac = HALMAC_RF_2T2R; + break; + case RF_1T1R: + rf_mac = HALMAC_RF_1T1R; + break; + case RF_2T2R_GREEN: + rf_mac = HALMAC_RF_2T2R_GREEN; + break; + case RF_2T3R: + rf_mac = HALMAC_RF_2T3R; + break; + case RF_3T3R: + rf_mac = HALMAC_RF_3T3R; + break; + case RF_3T4R: + rf_mac = HALMAC_RF_3T4R; + break; + case RF_4T4R: + rf_mac = HALMAC_RF_4T4R; + break; + default: + rf_mac = (HALMAC_RF_TYPE)rf_drv; + break; + } + + return rf_mac; +} + +static int _send_general_info(struct dvobj_priv *d) +{ + PADAPTER adapter; + PHAL_DATA_TYPE hal; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_GENERAL_INFO info; + HALMAC_RET_STATUS status; + u8 val8; + + adapter = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(adapter); + halmac = dvobj_to_halmac(d); + if (!halmac) + return -1; + api = HALMAC_GET_API(halmac); + + _rtw_memset(&info, 0, sizeof(info)); + info.rfe_type = (u8)hal->rfe_type; + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, &val8); + info.rf_type = _rf_type_drv2halmac(val8); + + status = api->halmac_send_general_info(halmac, &info); + switch (status) { + case HALMAC_RET_SUCCESS: + break; + case HALMAC_RET_NO_DLFW: + RTW_WARN("%s: halmac_send_general_info() fail because fw not dl!\n", + __FUNCTION__); + /* go through */ + default: + return -1; + } + + return 0; +} + +/* + * Description: + * Downlaod Firmware Flow + * + * Parameters: + * d pointer of struct dvobj_priv + * fw firmware array + * fwsize firmware size + * re_dl re-download firmware or not + * 0: run in init hal flow, not re-download + * 1: it is a stand alone operation, not in init hal flow + * + * Return: + * 0 Success + * others Fail + */ +static int download_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize, u8 re_dl) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + int err = 0; + PHAL_DATA_TYPE hal; + HALMAC_FW_VERSION fw_vesion; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + hal = GET_HAL_DATA(dvobj_get_primary_adapter(d)); + + if ((!fw) || (!fwsize)) + return -1; + + /* 1. Driver Stop Tx */ + /* ToDo */ + + /* 2. Driver Check Tx FIFO is empty */ + /* ToDo */ + + /* 3. Config MAX download size */ + /* required a even length from u32 */ + api->halmac_cfg_max_dl_size(mac, (MAX_CMDBUF_SZ - TXDESC_OFFSET) & 0xFFFFFFFE); + + /* 4. Download Firmware */ + status = api->halmac_download_firmware(mac, fw, fwsize); + if (HALMAC_RET_SUCCESS != status) + return -1; + + /* 5. Driver resume TX if needed */ + /* ToDo */ + + if (re_dl) { + HALMAC_TRX_MODE mode; + + /* 6. Init TRX Configuration */ + mode = _choose_trx_mode(d); + status = api->halmac_init_trx_cfg(mac, mode); + if (HALMAC_RET_SUCCESS != status) + return -1; + + /* 7. Config RX Aggregation */ + err = rtw_halmac_rx_agg_switch(d, _TRUE); + if (err) + return -1; + + /* 8. Send General Info */ + err = _send_general_info(d); + if (err) + return -1; + } + + /* 9. Reset driver variables if needed */ + hal->LastHMEBoxNum = 0; + + /* 10. Get FW version */ + status = api->halmac_get_fw_version(mac, &fw_vesion); + if (status == HALMAC_RET_SUCCESS) { + hal->firmware_version = fw_vesion.version; + hal->firmware_sub_version = fw_vesion.sub_version; + hal->firmware_size = fwsize; + } + + return err; +} + +static HALMAC_RET_STATUS init_mac_flow(struct dvobj_priv *d) +{ + PADAPTER p; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_WLAN_ADDR hwa; + HALMAC_TRX_MODE trx_mode; + HALMAC_RET_STATUS status; + u8 nettype; + int err; + PHAL_DATA_TYPE hal; + HALMAC_DRV_RSVD_PG_NUM rsvd_page_number = HALMAC_RSVD_PG_NUM16;/*HALMAC_RSVD_PG_NUM24/HALMAC_RSVD_PG_NUM32*/ + + p = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(p); + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + + status = api->halmac_cfg_drv_rsvd_pg_num(halmac, rsvd_page_number); + if (status != HALMAC_RET_SUCCESS) + goto out; + hal->drv_rsvd_page_number = _get_drv_rsvd_page(rsvd_page_number); + + trx_mode = _choose_trx_mode(d); + status = api->halmac_init_mac_cfg(halmac, trx_mode); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = rtw_halmac_rx_agg_switch(d, _TRUE); + if (err) + goto out; + + nettype = dvobj_to_regsty(d)->wireless_mode; + if (is_supported_vht(nettype) == _TRUE) + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_AC); + else if (is_supported_ht(nettype) == _TRUE) + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_N); + else if (IsSupportedTxOFDM(nettype) == _TRUE) + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_G); + else + status = api->halmac_cfg_operation_mode(halmac, HALMAC_WIRELESS_MODE_B); + if (status != HALMAC_RET_SUCCESS) + goto out; + +out: + return status; +} + +/* + * Notices: + * Make sure + * 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE) + * 2. HAL_DATA_TYPE.rfe_type + * already ready for use before calling this function. + */ +static int _halmac_init_hal(struct dvobj_priv *d, u8 *fw, u32 fwsize) +{ + PADAPTER adapter; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 ok = _TRUE; + u8 fw_ok = _FALSE; + int err, err_ret = -1; + + adapter = dvobj_get_primary_adapter(d); + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + api = HALMAC_GET_API(halmac); + + /* StatePowerOff */ + + /* SKIP: halmac_init_adapter (Already done before) */ + + /* halmac_pre_Init_system_cfg */ + /* halmac_mac_power_switch(on) */ + /* halmac_Init_system_cfg */ + ok = rtw_hal_power_on(adapter); + if (_FAIL == ok) + goto out; + + /* StatePowerOn */ + + /* DownloadFW */ + if (fw && fwsize) { + err = download_fw(d, fw, fwsize, 0); + if (err) + goto out; + fw_ok = _TRUE; + } + + /* InitMACFlow */ + status = init_mac_flow(d); + if (status != HALMAC_RET_SUCCESS) + goto out; + + /* halmac_send_general_info */ + if (_TRUE == fw_ok) { + err = _send_general_info(d); + if (err) + goto out; + } + + /* Init Phy parameter-MAC */ + ok = rtw_hal_init_mac_register(adapter); + if (_FALSE == ok) + goto out; + + /* StateMacInitialized */ + + /* halmac_cfg_drv_info */ + err = rtw_halmac_config_rx_info(d, HALMAC_DRV_INFO_PHY_STATUS); + if (err) + goto out; + + /* halmac_set_hw_value(HALMAC_HW_EN_BB_RF) */ + /* Init BB, RF */ + ok = rtw_hal_init_phy(adapter); + if (_FALSE == ok) + goto out; + + status = api->halmac_init_interface_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + /* SKIP: halmac_verify_platform_api */ + /* SKIP: halmac_h2c_lb */ + + /* StateRxIdle */ + + err_ret = 0; +out: + return err_ret; +} + +/* + * Notices: + * Make sure + * 1. rtw_hal_get_hwreg(HW_VAR_RF_TYPE) + * 2. HAL_DATA_TYPE.rfe_type + * already ready for use before calling this function. + */ +int rtw_halmac_init_hal_fw(struct dvobj_priv *d, u8 *fw, u32 fwsize) +{ + return _halmac_init_hal(d, fw, fwsize); +} + +int rtw_halmac_deinit_hal(struct dvobj_priv *d) +{ + PADAPTER adapter; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + int err = -1; + + adapter = dvobj_get_primary_adapter(d); + halmac = dvobj_to_halmac(d); + if (!halmac) + goto out; + api = HALMAC_GET_API(halmac); + + status = api->halmac_deinit_interface_cfg(halmac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + rtw_hal_power_off(adapter); + + err = 0; +out: + return err; +} + +int rtw_halmac_self_verify(struct dvobj_priv *d) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + int err = -1; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_verify_platform_api(mac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + status = api->halmac_h2c_lb(mac); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +u8 rtw_halmac_txfifo_is_empty(struct dvobj_priv *d) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + u8 rst = _TRUE; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + if (HALMAC_RET_TXFIFO_NO_EMPTY == api->halmac_txfifo_is_empty(mac, 10)) + rst = _FALSE; + + return rst; +} + +static HALMAC_DLFW_MEM _get_halmac_fw_mem(enum fw_mem mem) +{ + if (FW_EMEM == mem) + return HALMAC_DLFW_MEM_EMEM; + else if (FW_IMEM == mem) + return HALMAC_DLFW_MEM_UNDEFINE; + else if (FW_DMEM == mem) + return HALMAC_DLFW_MEM_UNDEFINE; + else + return HALMAC_DLFW_MEM_UNDEFINE; +} + +#define DBG_DL_FW_MEM +int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + int err = 0; + u8 chk_cnt = 0; + bool txfifo_empty = _FALSE; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + if ((!fw) || (!fwsize)) + return -1; + + /* 1. Driver Stop Tx */ + /* ToDo */ + + /* 2. Driver Check Tx FIFO is empty */ + do { + txfifo_empty = rtw_halmac_txfifo_is_empty(d); + chk_cnt++; + RTW_INFO("polling txfifo empty chk_cnt:%d\n", chk_cnt); + rtw_msleep_os(2); + } while ((!txfifo_empty) && (chk_cnt < 100)); + + if (_FALSE == txfifo_empty) { + { + PADAPTER adapter = dvobj_get_primary_adapter(d); + + RTW_ERR("%s => polling txfifo empty failed\n", __func__); + RTW_ERR("REG_210:0x%08x\n", rtw_read32(adapter, 0x210)); + RTW_ERR("REG_230:0x%08x\n", rtw_read32(adapter, 0x230)); + RTW_ERR("REG_234:0x%08x\n", rtw_read32(adapter, 0x234)); + RTW_ERR("REG_238:0x%08x\n", rtw_read32(adapter, 0x238)); + RTW_ERR("REG_23C:0x%08x\n", rtw_read32(adapter, 0x23C)); + RTW_ERR("REG_240:0x%08x\n", rtw_read32(adapter, 0x240)); + RTW_ERR("REG_41A:0x%08x\n", rtw_read32(adapter, 0x41A)); + + RTW_ERR("REG_10FC:0x%08x\n", rtw_read32(adapter, 0x10FC)); + RTW_ERR("REG_10F8:0x%08x\n", rtw_read32(adapter, 0x10F8)); + RTW_ERR("REG_11F4:0x%08x\n", rtw_read32(adapter, 0x11F4)); + RTW_ERR("REG_11F8:0x%08x\n", rtw_read32(adapter, 0x11F8)); + } + return -1; + } + + /* 3. Download Firmware MEM */ + status = api->halmac_free_download_firmware(mac, _get_halmac_fw_mem(mem), fw, fwsize); + if (HALMAC_RET_SUCCESS != status) { + RTW_ERR("%s => halmac_free_download_firmware failed\n", __func__); + return -1; + } + /* 4. Driver resume TX if needed */ + /* ToDo */ + + return err; +} + +/* + * Return: + * 0 Success + * -22 Invalid arguemnt + */ +int rtw_halmac_dlfw(struct dvobj_priv *d, u8 *fw, u32 fwsize) +{ + PADAPTER adapter; + HALMAC_RET_STATUS status; + u32 ok = _TRUE; + int err, err_ret = -1; + + if (!fw || !fwsize) + return -22; + + adapter = dvobj_get_primary_adapter(d); + + /* re-download firmware */ + if (rtw_is_hw_init_completed(adapter)) + return download_fw(d, fw, fwsize, 1); + + /* Download firmware before hal init */ + /* Power on, download firmware and init mac */ + ok = rtw_hal_power_on(adapter); + if (_FAIL == ok) + goto out; + + err = download_fw(d, fw, fwsize, 0); + if (err) { + err_ret = err; + goto out; + } + + status = init_mac_flow(d); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = _send_general_info(d); + if (err) + goto out; + + err_ret = 0; + +out: + return err_ret; +} + +static u8 _is_fw_read_cmd_down(PADAPTER adapter, u8 msgbox_num) +{ + u8 read_down = _FALSE; + int retry_cnts = 100; + u8 valid; + + do { + valid = rtw_read8(adapter, REG_HMETFR) & BIT(msgbox_num); + if (0 == valid) + read_down = _TRUE; + else + rtw_msleep_os(1); + } while ((!read_down) && (retry_cnts--)); + + if (_FALSE == read_down) + RTW_WARN("%s, reg_1cc(%x), msg_box(%d)...\n", __func__, rtw_read8(adapter, REG_HMETFR), msgbox_num); + + return read_down; +} + +int rtw_halmac_send_h2c(struct dvobj_priv *d, u8 *h2c) +{ + PADAPTER adapter = dvobj_get_primary_adapter(d); + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u8 h2c_box_num = 0; + u32 msgbox_addr = 0; + u32 msgbox_ex_addr = 0; + u32 h2c_cmd = 0; + u32 h2c_cmd_ex = 0; + s32 ret = _FAIL; + + if (adapter->bFWReady == _FALSE) { + RTW_WARN("%s: return H2C cmd because fw is not ready\n", __FUNCTION__); + return ret; + } + + if (!h2c) { + RTW_WARN("%s: pbuf is NULL\n", __FUNCTION__); + return ret; + } + + if (rtw_is_surprise_removed(adapter)) { + RTW_WARN("%s: surprise removed\n", __FUNCTION__); + return ret; + } + + _enter_critical_mutex(&d->h2c_fwcmd_mutex, NULL); + + /* pay attention to if race condition happened in H2C cmd setting */ + h2c_box_num = hal->LastHMEBoxNum; + + if (!_is_fw_read_cmd_down(adapter, h2c_box_num)) { + RTW_WARN(" fw read cmd failed...\n"); + goto exit; + } + + /* Write Ext command(byte 4 -7) */ + msgbox_ex_addr = REG_HMEBOX_E0 + (h2c_box_num * EX_MESSAGE_BOX_SIZE); + _rtw_memcpy((u8 *)(&h2c_cmd_ex), h2c + 4, EX_MESSAGE_BOX_SIZE); + h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex); + rtw_write32(adapter, msgbox_ex_addr, h2c_cmd_ex); + + /* Write command (byte 0 -3 ) */ + msgbox_addr = REG_HMEBOX0 + (h2c_box_num * MESSAGE_BOX_SIZE); + _rtw_memcpy((u8 *)(&h2c_cmd), h2c, 4); + h2c_cmd = le32_to_cpu(h2c_cmd); + rtw_write32(adapter, msgbox_addr, h2c_cmd); + + /* update last msg box number */ + hal->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS; + ret = _SUCCESS; + +exit: + _exit_critical_mutex(&d->h2c_fwcmd_mutex, NULL); + return ret; +} + +int rtw_halmac_c2h_handle(struct dvobj_priv *d, u8 *c2h, u32 size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_get_c2h_info(mac, c2h, size); + if (HALMAC_RET_SUCCESS != status) + return -1; + + return 0; +} + +int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 val; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_get_efuse_available_size(mac, &val); + if (HALMAC_RET_SUCCESS != status) + return -1; + + *size = val; + return 0; +} + +int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *d, u32 *size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 val; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_get_efuse_size(mac, &val); + if (HALMAC_RET_SUCCESS != status) + return -1; + + *size = val; + return 0; +} + +int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + HALMAC_FEATURE_ID id; + int ret; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + id = HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE; + + ret = init_halmac_event(d, id, map, size); + if (ret) + return -1; + + status = api->halmac_dump_efuse_map(mac, HALMAC_EFUSE_R_AUTO); + if (HALMAC_RET_SUCCESS != status) { + free_halmac_event(d, id); + return -1; + } + + ret = wait_halmac_event(d, id); + if (ret) + return -1; + + return 0; +} + +int rtw_halmac_read_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u8 v; + u32 i; + u8 *efuse = NULL; + u32 size = 0; + int err = 0; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + if (api->halmac_read_efuse) { + for (i = 0; i < cnt; i++) { + status = api->halmac_read_efuse(mac, offset + i, &v); + if (HALMAC_RET_SUCCESS != status) + return -1; + data[i] = v; + } + } else { + err = rtw_halmac_get_physical_efuse_size(d, &size); + if (err) + return -1; + + efuse = rtw_zmalloc(size); + if (!efuse) + return -1; + + err = rtw_halmac_read_physical_efuse_map(d, efuse, size); + if (err) + err = -1; + else + _rtw_memcpy(data, efuse + offset, cnt); + + rtw_mfree(efuse, size); + } + + return err; +} + +int rtw_halmac_write_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 i; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + if (api->halmac_write_efuse == NULL) + return -1; + + for (i = 0; i < cnt; i++) { + status = api->halmac_write_efuse(mac, offset + i, data[i]); + if (HALMAC_RET_SUCCESS != status) + return -1; + } + + return 0; +} + +int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *d, u32 *size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 val; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_get_logical_efuse_size(mac, &val); + if (HALMAC_RET_SUCCESS != status) + return -1; + + *size = val; + return 0; +} + +int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + HALMAC_FEATURE_ID id; + int ret; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + id = HALMAC_FEATURE_DUMP_LOGICAL_EFUSE; + + ret = init_halmac_event(d, id, map, size); + if (ret) + return -1; + + status = api->halmac_dump_logical_efuse_map(mac, HALMAC_EFUSE_R_DRV); + if (HALMAC_RET_SUCCESS != status) { + free_halmac_event(d, id); + return -1; + } + + ret = wait_halmac_event(d, id); + if (ret) + return -1; + + return 0; +} + +int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size, u8 *maskmap, u32 masksize) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_PG_EFUSE_INFO pginfo; + HALMAC_RET_STATUS status; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + pginfo.pEfuse_map = map; + pginfo.efuse_map_size = size; + pginfo.pEfuse_mask = maskmap; + pginfo.efuse_mask_size = masksize; + + status = api->halmac_pg_efuse_by_map(mac, &pginfo, HALMAC_EFUSE_R_AUTO); + if (HALMAC_RET_SUCCESS != status) + return -1; + + return 0; +} + +int rtw_halmac_read_logical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u8 v; + u32 i; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + for (i = 0; i < cnt; i++) { + status = api->halmac_read_logical_efuse(mac, offset + i, &v); + if (HALMAC_RET_SUCCESS != status) + return -1; + data[i] = v; + } + + return 0; +} + +int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *d, u32 offset, u32 cnt, u8 *data) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u32 i; + u8 bank = 1; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + for (i = 0; i < cnt; i++) { + status = api->halmac_write_efuse_bt(mac, offset + i, data[i], bank); + if (HALMAC_RET_SUCCESS != status) { + printk("%s: halmac_write_efuse_bt status = %d\n", __FUNCTION__, status); + return -1; + } + } + printk("%s: halmac_write_efuse_bt status = HALMAC_RET_SUCCESS %d\n", __FUNCTION__, status); + return 0; +} + +int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *d, u8 *map, u32 size) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + HALMAC_FEATURE_ID id; + int ret; + int bank = 1; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_dump_efuse_map_bt(mac, bank, size, map); + if (HALMAC_RET_SUCCESS != status) { + printk("%s: halmac_dump_efuse_map_bt fail!\n", __FUNCTION__); + return -1; + } + + printk("%s: OK!\n", __FUNCTION__); + + return 0; +} + +static inline u8 _hw_port_drv2halmac(enum _hw_port hwport) +{ + u8 port = 0; + + switch (hwport) { + case HW_PORT0: + port = 0; + break; + case HW_PORT1: + port = 1; + break; + case HW_PORT2: + port = 2; + break; + case HW_PORT3: + port = 3; + break; + case HW_PORT4: + port = 4; + break; + default: + port = hwport; + break; + } + + return port; +} + +int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + u8 port; + HALMAC_WLAN_ADDR hwa; + HALMAC_RET_STATUS status; + int err = -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + + port = _hw_port_drv2halmac(hwport); + _rtw_memset(&hwa, 0, sizeof(hwa)); + _rtw_memcpy(hwa.Address, addr, 6); + + status = api->halmac_cfg_mac_addr(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr) +{ + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + u8 port; + HALMAC_WLAN_ADDR hwa; + HALMAC_RET_STATUS status; + int err = -1; + + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + port = _hw_port_drv2halmac(hwport); + + _rtw_memset(&hwa, 0, sizeof(HALMAC_WLAN_ADDR)); + _rtw_memcpy(hwa.Address, addr, 6); + status = api->halmac_cfg_bssid(halmac, port, &hwa); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + status = api->halmac_cfg_ch_bw(mac, channel, pri_ch_idx, bw); + if (HALMAC_RET_SUCCESS != status) + return -1; + + return 0; +} + +static HAL_FIFO_SEL _fifo_sel_drv2halmac(u8 fifo_sel) +{ + if (0 == fifo_sel) + return HAL_FIFO_SEL_TX; + else if (1 == fifo_sel) + return HAL_FIFO_SEL_RX; + else if (2 == fifo_sel) + return HAL_FIFO_SEL_RSVD_PAGE; + else if (3 == fifo_sel) + return HAL_FIFO_SEL_REPORT; + else if (4 == fifo_sel) + return HAL_FIFO_SEL_LLT; + else + return HAL_FIFO_SEL_RSVD_PAGE; +} + +#define CONFIG_HALMAC_FIFO_DUMP +int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer) +{ + PHALMAC_ADAPTER mac; + PHALMAC_API api; + HALMAC_RET_STATUS status; + u8 *pfifo_map = NULL; + u32 fifo_size = 0; + s8 ret = 0;/* 0:success, -1:error */ + u8 mem_created = _FALSE; + + HAL_FIFO_SEL halmac_fifo_sel; + + mac = dvobj_to_halmac(d); + api = HALMAC_GET_API(mac); + + if ((size != 0) && (buffer == NULL)) + return -1; + + halmac_fifo_sel = _fifo_sel_drv2halmac(fifo_sel); + + if ((size) && (buffer)) { + pfifo_map = buffer; + fifo_size = size; + } else { + fifo_size = api->halmac_get_fifo_size(mac, halmac_fifo_sel); + + if (fifo_size) + pfifo_map = rtw_zvmalloc(fifo_size); + if (pfifo_map == NULL) + return -1; + mem_created = _TRUE; + } + + status = api->halmac_dump_fifo(mac, halmac_fifo_sel, addr, fifo_size, pfifo_map); + if (HALMAC_RET_SUCCESS != status) { + ret = -1; + goto _exit; + } + + { + static const char * const fifo_sel_str[] = { + "TX", "RX", "RSVD_PAGE", "REPORT", "LLT" + }; + + RTW_INFO("%s FIFO DUMP [start_addr:0x%04x , size:%d]\n", fifo_sel_str[halmac_fifo_sel], addr, fifo_size); + RTW_INFO_DUMP("\n", pfifo_map, fifo_size); + RTW_INFO(" ==================================================\n"); + } + +_exit: + if (mem_created && pfifo_map) + rtw_vmfree(pfifo_map, fifo_size); + return ret; + +} + +int rtw_halmac_rx_agg_switch(struct dvobj_priv *d, u8 enable) +{ + PADAPTER adapter; + PHAL_DATA_TYPE hal; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + HALMAC_RXAGG_CFG rxaggcfg; + HALMAC_RET_STATUS status; + int err = -1; + + adapter = dvobj_get_primary_adapter(d); + hal = GET_HAL_DATA(adapter); + halmac = dvobj_to_halmac(d); + api = HALMAC_GET_API(halmac); + _rtw_memset((void *)&rxaggcfg, 0, sizeof(rxaggcfg)); + + if (_TRUE == enable) { + } else + rxaggcfg.mode = HALMAC_RX_AGG_MODE_NONE; + + status = api->halmac_cfg_rx_aggregation(halmac, &rxaggcfg); + if (status != HALMAC_RET_SUCCESS) + goto out; + + err = 0; +out: + return err; +} + +/* + * Description: + * Get RX driver info size. RX driver info is a small memory space between + * scriptor and RX payload. + * + * +-------------------------+ + * | RX descriptor | + * | usually 24 bytes | + * +-------------------------+ + * | RX driver info | + * | depends on driver cfg | + * +-------------------------+ + * | RX paylad | + * | | + * +-------------------------+ + * + * Parameter: + * d pointer to struct dvobj_priv of driver + * sz rx driver info size in bytes. + * + * Rteurn: + * 0 Success + * other Fail + */ +int rtw_halmac_get_drv_info_sz(struct dvobj_priv *d, u8 *sz) +{ + HALMAC_RET_STATUS status; + PHALMAC_ADAPTER halmac = dvobj_to_halmac(d); + PHALMAC_API api = HALMAC_GET_API(halmac); + u8 dw = 0; + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_DRV_INFO_SIZE, &dw); + if (status != HALMAC_RET_SUCCESS) + return -1; + + *sz = dw * 8; + return 0; +} +int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg) +{ + HALMAC_RET_STATUS status; + PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); + PHALMAC_API api = HALMAC_GET_API(halmac); + + status = api->halmac_get_hw_value(halmac, HALMAC_HW_RSVD_PG_BNDY, drv_pg); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; +} + +/* + * Description + * Fill following spec info from HALMAC API: + * sec_cam_ent_num + * + * Return + * 0 Success + * others Fail + */ +int rtw_halmac_fill_hal_spec(struct dvobj_priv *dvobj, struct hal_spec_t *spec) +{ + HALMAC_RET_STATUS status; + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + u8 cam = 0; /* Security Cam Entry Number */ + + halmac = dvobj_to_halmac(dvobj); + api = HALMAC_GET_API(halmac); + + /* Prepare data from HALMAC */ + status = api->halmac_get_hw_value(halmac, HALMAC_HW_CAM_ENTRY_NUM, &cam); + if (status != HALMAC_RET_SUCCESS) + return -1; + + /* Fill data to hal_spec_t */ + spec->sec_cam_ent_num = cam; + + return 0; +} + +int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para) +{ + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_ADAPTER halmac = dvobj_to_halmac(dvobj); + PHALMAC_API api = HALMAC_GET_API(halmac); + HALMAC_P2PPS halmac_p2p_ps; + + (&halmac_p2p_ps)->offload_en = pp2p_ps_para->offload_en; + (&halmac_p2p_ps)->role = pp2p_ps_para->role; + (&halmac_p2p_ps)->ctwindow_en = pp2p_ps_para->ctwindow_en; + (&halmac_p2p_ps)->noa_en = pp2p_ps_para->noa_en; + (&halmac_p2p_ps)->noa_sel = pp2p_ps_para->noa_sel; + (&halmac_p2p_ps)->all_sta_sleep = pp2p_ps_para->all_sta_sleep; + (&halmac_p2p_ps)->discovery = pp2p_ps_para->discovery; + (&halmac_p2p_ps)->p2p_port_id = _hw_port_drv2halmac(pp2p_ps_para->p2p_port_id); + (&halmac_p2p_ps)->p2p_group = pp2p_ps_para->p2p_group; + (&halmac_p2p_ps)->p2p_macid = pp2p_ps_para->p2p_macid; + (&halmac_p2p_ps)->ctwindow_length = pp2p_ps_para->ctwindow_length; + (&halmac_p2p_ps)->noa_duration_para = pp2p_ps_para->noa_duration_para; + (&halmac_p2p_ps)->noa_interval_para = pp2p_ps_para->noa_interval_para; + (&halmac_p2p_ps)->noa_start_time_para = pp2p_ps_para->noa_start_time_para; + (&halmac_p2p_ps)->noa_count_para = pp2p_ps_para->noa_count_para; + + status = api->halmac_p2pps(halmac, (&halmac_p2p_ps)); + if (status != HALMAC_RET_SUCCESS) + return -1; + + return 0; + +} + diff --git a/drivers/staging/rtl8821ce/hal/hal_halmac.h b/drivers/staging/rtl8821ce/hal/hal_halmac.h new file mode 100644 index 000000000000..dbe8befa176a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_halmac.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _HAL_HALMAC_H_ +#define _HAL_HALMAC_H_ + +#include <drv_types.h> /* adapter_to_dvobj(), struct intf_hdl and etc. */ +#include <hal_data.h> /* struct hal_spec_t */ +#include "halmac/halmac_api.h" /* PHALMAC_ADAPTER and etc. */ + +/* HALMAC Definition for Driver */ +#define RTW_HALMAC_H2C_MAX_SIZE HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX +#define RTW_HALMAC_BA_SSN_RPT_SIZE 4 + +#define dvobj_set_halmac(d, mac) ((d)->halmac = (mac)) +#define dvobj_to_halmac(d) ((PHALMAC_ADAPTER)((d)->halmac)) +#define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p)) + +/* for H2C cmd */ +#define MAX_H2C_BOX_NUMS 4 +#define MESSAGE_BOX_SIZE 4 +#define EX_MESSAGE_BOX_SIZE 4 + +typedef enum _RTW_HALMAC_MODE { + RTW_HALMAC_MODE_NORMAL, + RTW_HALMAC_MODE_WIFI_TEST, +} RTW_HALMAC_MODE; + +extern HALMAC_PLATFORM_API rtw_halmac_platform_api; + +/* HALMAC API for Driver(HAL) */ +u8 rtw_halmac_read8(struct intf_hdl *, u32 addr); +u16 rtw_halmac_read16(struct intf_hdl *, u32 addr); +u32 rtw_halmac_read32(struct intf_hdl *, u32 addr); +void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); +int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value); +int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value); +int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value); + +void rtw_dump_halmac_info(void *sel); +int rtw_halmac_init_adapter(struct dvobj_priv *, PHALMAC_PLATFORM_API); +int rtw_halmac_deinit_adapter(struct dvobj_priv *); +int rtw_halmac_poweron(struct dvobj_priv *); +int rtw_halmac_poweroff(struct dvobj_priv *); +int rtw_halmac_init_hal(struct dvobj_priv *); +int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize); +int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath); +int rtw_halmac_deinit_hal(struct dvobj_priv *); +int rtw_halmac_self_verify(struct dvobj_priv *); +int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize); +int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath); +int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem); +int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem); +int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable); +int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c); +int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size); +int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size); + +int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size); +int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); +int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); +int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); +int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size); +int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); +int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize); +int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); +int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); + +int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data); +int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size); + +int rtw_halmac_config_rx_info(struct dvobj_priv *, HALMAC_DRV_INFO); +int rtw_halmac_set_mac_address(struct dvobj_priv *, enum _hw_port, u8 *addr); +int rtw_halmac_set_bssid(struct dvobj_priv *, enum _hw_port hwport, u8 *addr); + +int rtw_halmac_set_bandwidth(struct dvobj_priv *, u8 channel, u8 pri_ch_idx, u8 bw); +int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer); +int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable); +int rtw_halmac_get_hw_value(struct dvobj_priv *, HALMAC_HW_ID hw_id, VOID *pvalue); +int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason); +int rtw_halmac_get_drv_info_sz(struct dvobj_priv *, u8 *sz); +int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *dvobj, u16 *drv_pg); +int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size); +int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *); +int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para); + +#endif /* _HAL_HALMAC_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/hal_intf.c b/drivers/staging/rtl8821ce/hal/hal_intf.c new file mode 100644 index 000000000000..59c10fa43ff0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_intf.c @@ -0,0 +1,1080 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _HAL_INTF_C_ + +#include <drv_types.h> +#include <hal_data.h> + +const u32 _chip_type_to_odm_ic_type[] = { + 0, + ODM_RTL8188E, + ODM_RTL8192E, + ODM_RTL8812, + ODM_RTL8821, + ODM_RTL8723B, + ODM_RTL8814A, + ODM_RTL8703B, + ODM_RTL8188F, + ODM_RTL8822B, + ODM_RTL8723D, + ODM_RTL8821C, + 0, +}; + +void rtw_hal_chip_configure(_adapter *padapter) +{ + padapter->hal_func.intf_chip_configure(padapter); +} + +/* + * Description: + * Read chip internal ROM data + * + * Return: + * _SUCCESS success + * _FAIL fail + */ +u8 rtw_hal_read_chip_info(_adapter *padapter) +{ + u8 rtn = _SUCCESS; + u8 hci_type = rtw_get_intf_type(padapter); + u32 start = rtw_get_current_time(); + + /* before access eFuse, make sure card enable has been called */ + if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI) + && !rtw_is_hw_init_completed(padapter)) + rtw_hal_power_on(padapter); + + rtn = padapter->hal_func.read_adapter_info(padapter); + + if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI) + && !rtw_is_hw_init_completed(padapter)) + rtw_hal_power_off(padapter); + + RTW_INFO("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start)); + + return rtn; +} + +void rtw_hal_read_chip_version(_adapter *padapter) +{ + padapter->hal_func.read_chip_version(padapter); + rtw_odm_init_ic_type(padapter); +} + +void rtw_hal_def_value_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + padapter->hal_func.init_default_value(padapter); + + rtw_init_hal_com_default_value(padapter); + + { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + + /* hal_spec is ready here */ + dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT); + + dvobj->cam_ctl.sec_cap = hal_spec->sec_cap; + dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT); + } + } +} + +u8 rtw_hal_data_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + padapter->hal_data_sz = sizeof(HAL_DATA_TYPE); + padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz); + if (padapter->HalData == NULL) { + RTW_INFO("cant not alloc memory for HAL DATA\n"); + return _FAIL; + } + } + return _SUCCESS; +} + +void rtw_hal_data_deinit(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + if (padapter->HalData) { + phy_free_filebuf(padapter); + rtw_vmfree(padapter->HalData, padapter->hal_data_sz); + padapter->HalData = NULL; + padapter->hal_data_sz = 0; + } + } +} + +void rtw_hal_free_data(_adapter *padapter) +{ + /* free HAL Data */ + rtw_hal_data_deinit(padapter); +} +void rtw_hal_dm_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + padapter->hal_func.dm_init(padapter); + + _rtw_spinlock_init(&pHalData->IQKSpinLock); + + phy_load_tx_power_ext_info(padapter, 1); + } +} +void rtw_hal_dm_deinit(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + padapter->hal_func.dm_deinit(padapter); + + _rtw_spinlock_free(&pHalData->IQKSpinLock); + } +} +void rtw_hal_sw_led_init(_adapter *padapter) +{ + if (padapter->hal_func.InitSwLeds) + padapter->hal_func.InitSwLeds(padapter); +} + +void rtw_hal_sw_led_deinit(_adapter *padapter) +{ + if (padapter->hal_func.DeInitSwLeds) + padapter->hal_func.DeInitSwLeds(padapter); +} + +u32 rtw_hal_power_on(_adapter *padapter) +{ + u32 ret = 0; + + ret = padapter->hal_func.hal_power_on(padapter); + + if (ret == _SUCCESS) + rtw_btcoex_PowerOnSetting(padapter); + + return ret; +} +void rtw_hal_power_off(_adapter *padapter) +{ + struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl; + + _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT); + + rtw_btcoex_PowerOffSetting(padapter); + + padapter->hal_func.hal_power_off(padapter); +} + +void rtw_hal_init_opmode(_adapter *padapter) +{ + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + sint fw_state; + + fw_state = get_fwstate(pmlmepriv); + + if (fw_state & WIFI_ADHOC_STATE) + networkType = Ndis802_11IBSS; + else if (fw_state & WIFI_STATION_STATE) + networkType = Ndis802_11Infrastructure; + else if (fw_state & WIFI_AP_STATE) + networkType = Ndis802_11APMode; + else + return; + + rtw_setopmode_cmd(padapter, networkType, _FALSE); +} + +uint rtw_hal_init(_adapter *padapter) +{ + uint status = _SUCCESS; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + int i; + + status = padapter->hal_func.hal_init(padapter); + + if (status == _SUCCESS) { + pHalData->hw_init_completed = _TRUE; + rtw_restore_mac_addr(padapter); + + if (padapter->registrypriv.notch_filter == 1) + rtw_hal_notch_filter(padapter, 1); + + for (i = 0; i < dvobj->iface_nums; i++) + rtw_sec_restore_wep_key(dvobj->padapters[i]); + + rtw_led_control(padapter, LED_CTL_POWER_ON); + + init_hw_mlme_ext(padapter); + + rtw_hal_init_opmode(padapter); + + + } else { + pHalData->hw_init_completed = _FALSE; + RTW_INFO("rtw_hal_init: hal_init fail\n"); + } + + return status; + +} + +uint rtw_hal_deinit(_adapter *padapter) +{ + uint status = _SUCCESS; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + int i; + + status = padapter->hal_func.hal_deinit(padapter); + + if (status == _SUCCESS) { + rtw_led_control(padapter, LED_CTL_POWER_OFF); + pHalData->hw_init_completed = _FALSE; + } else + RTW_INFO("\n rtw_hal_deinit: hal_init fail\n"); + + return status; +} + +void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) +{ + padapter->hal_func.set_hw_reg_handler(padapter, variable, val); +} + +void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val) +{ + padapter->hal_func.GetHwRegHandler(padapter, variable, val); +} + +u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) +{ + return padapter->hal_func.SetHalDefVarHandler(padapter, eVariable, pValue); +} +u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) +{ + return padapter->hal_func.get_hal_def_var_handler(padapter, eVariable, pValue); +} + +void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet) +{ + padapter->hal_func.SetHalODMVarHandler(padapter, eVariable, pValue1, bSet); +} +void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2) +{ + padapter->hal_func.GetHalODMVarHandler(padapter, eVariable, pValue1, pValue2); +} + +/* FOR SDIO & PCIE */ +void rtw_hal_enable_interrupt(_adapter *padapter) +{ + padapter->hal_func.enable_interrupt(padapter); +} + +/* FOR SDIO & PCIE */ +void rtw_hal_disable_interrupt(_adapter *padapter) +{ + padapter->hal_func.disable_interrupt(padapter); +} + +u8 rtw_hal_check_ips_status(_adapter *padapter) +{ + u8 val = _FALSE; + if (padapter->hal_func.check_ips_status) + val = padapter->hal_func.check_ips_status(padapter); + else + RTW_INFO("%s: hal_func.check_ips_status is NULL!\n", __FUNCTION__); + + return val; +} + +s32 rtw_hal_fw_dl(_adapter *padapter) +{ + return padapter->hal_func.fw_dl(padapter); +} + +u32 rtw_hal_inirp_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) + return padapter->hal_func.inirp_init(padapter); + return _SUCCESS; +} +u32 rtw_hal_inirp_deinit(_adapter *padapter) +{ + + if (is_primary_adapter(padapter)) + return padapter->hal_func.inirp_deinit(padapter); + + return _SUCCESS; +} + +void rtw_hal_irp_reset(_adapter *padapter) +{ + padapter->hal_func.irp_reset(GET_PRIMARY_ADAPTER(padapter)); +} + +void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data) +{ + u16 cmd[2]; + + cmd[0] = addr; + cmd[1] = data; + + padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_DBI, (u8 *) cmd); +} + +u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr) +{ + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_DBI, (u8 *)(&addr)); + + return (u8)addr; +} + +void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data) +{ + u16 cmd[2]; + + cmd[0] = (u16)addr; + cmd[1] = data; + + padapter->hal_func.set_hw_reg_handler(padapter, HW_VAR_MDIO, (u8 *) cmd); +} + +u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr) +{ + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_MDIO, &addr); + + return (u8)addr; +} + +u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter) +{ + u8 l1off; + + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_NIC_SUPPORT, &l1off); + return l1off; +} + +u8 rtw_hal_pci_l1off_capability(_adapter *padapter) +{ + u8 l1off; + + padapter->hal_func.GetHwRegHandler(padapter, HW_VAR_L1OFF_CAPABILITY, &l1off); + return l1off; +} + +s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + return padapter->hal_func.hal_xmitframe_enqueue(padapter, pxmitframe); +} + +s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + return padapter->hal_func.hal_xmit(padapter, pxmitframe); +} + +/* + * [IMPORTANT] This function would be run in interrupt context. + */ +s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + s32 ret = _FAIL; + u8 *pframe, subtype; + struct rtw_ieee80211_hdr *pwlanhdr; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + update_mgntframe_attrib_addr(padapter, pmgntframe); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + subtype = get_frame_sub_type(pframe); /* bit(7)~bit(2) */ + + /* pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; */ + /* _rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); */ + + ret = padapter->hal_func.mgnt_xmit(padapter, pmgntframe); + return ret; +} + +s32 rtw_hal_init_xmit_priv(_adapter *padapter) +{ + return padapter->hal_func.init_xmit_priv(padapter); +} +void rtw_hal_free_xmit_priv(_adapter *padapter) +{ + padapter->hal_func.free_xmit_priv(padapter); +} + +s32 rtw_hal_init_recv_priv(_adapter *padapter) +{ + return padapter->hal_func.init_recv_priv(padapter); +} +void rtw_hal_free_recv_priv(_adapter *padapter) +{ + padapter->hal_func.free_recv_priv(padapter); +} + +void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw) +{ + struct macid_cfg h2c_macid_cfg; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + u8 disable_cck_rate = FALSE, MimoPs_enable = FALSE; + u32 ratr_bitmap_msb = 0, ratr_bitmap_lsb = 0; + u64 mask = 0, rate_bitmap = 0; + u8 bw, short_gi; + + if (psta == NULL) { + RTW_ERR(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", FUNC_ADPT_ARG(padapter), mac_id); + rtw_warn_on(1); + return; + } + _rtw_memset(&h2c_macid_cfg, 0, sizeof(struct macid_cfg)); + + bw = rtw_get_tx_bw_mode(padapter, psta); + short_gi = query_ra_short_GI(psta, bw); + + ratr_bitmap_msb = (u32)(psta->ra_mask >> 32); + ratr_bitmap_lsb = (u32)(psta->ra_mask); + + phydm_update_hal_ra_mask(&hal_data->odmpriv, psta->wireless_mode, hal_data->rf_type, bw, MimoPs_enable, disable_cck_rate, &ratr_bitmap_msb, &ratr_bitmap_lsb, rssi_level); + mask = (((u64)ratr_bitmap_msb) << 32) | ((u64)ratr_bitmap_lsb); + + if (hal_data->EEPROMBluetoothCoexist == 1) { + rate_bitmap = rtw_btcoex_GetRaMask(padapter); + mask &= ~rate_bitmap; + } + +#ifdef CONFIG_CMCC_TEST + if (pmlmeext->cur_wireless_mode & WIRELESS_11G) { + if (mac_id == 0) { + RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); + /*mask &=0xffffffc0; //disable CCK & <12M OFDM rate for 11G mode for CMCC */ + mask &= 0xffffff00; /*disable CCK & <24M OFDM rate for 11G mode for CMCC */ + RTW_INFO("CMCC_BT update raid entry, mask=0x%x\n", mask); + } + } +#endif + + /*set correct initial date rate for each mac_id */ + hal_data->INIDATA_RATE[mac_id] = psta->init_rate; + + RTW_INFO("%s => mac_id:%d, networkType:0x%02x, mask:0x%016llx\n\t ==> rssi_level:%d, rate_bitmap:0x%016llx, shortGIrate=%d\n\t ==> bw:%d, ignore_bw:0x%d\n", + __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap, short_gi, bw, (!is_update_bw)); + + rtw_macid_ctl_set_bw(macid_ctl, mac_id, bw); + rtw_macid_ctl_set_vht_en(macid_ctl, mac_id, is_supported_vht(psta->wireless_mode)); + rtw_macid_ctl_set_rate_bmp0(macid_ctl, mac_id, mask); + rtw_macid_ctl_set_rate_bmp1(macid_ctl, mac_id, mask >> 32); + rtw_update_tx_rate_bmp(adapter_to_dvobj(padapter)); + + h2c_macid_cfg.mac_id = mac_id; + h2c_macid_cfg.rate_id = psta->raid; + h2c_macid_cfg.bandwidth = bw; + h2c_macid_cfg.ignore_bw = (!is_update_bw); + h2c_macid_cfg.short_gi = short_gi; + h2c_macid_cfg.ra_mask = mask; + + padapter->hal_func.update_ra_mask_handler(padapter, psta, &h2c_macid_cfg); +} + +void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw) +{ + _adapter *padapter; + struct mlme_priv *pmlmepriv; + + if (!psta) + return; + + padapter = psta->padapter; + + pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + add_RATid(padapter, psta, rssi_level, is_update_bw); + else { + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + rtw_update_ramask(padapter, psta, psta->mac_id, rssi_level, is_update_bw); + } +} + +/* Start specifical interface thread */ +void rtw_hal_start_thread(_adapter *padapter) +{ +} +/* Start specifical interface thread */ +void rtw_hal_stop_thread(_adapter *padapter) +{ +} + +u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask) +{ + u32 data = 0; + if (padapter->hal_func.read_bbreg) + data = padapter->hal_func.read_bbreg(padapter, RegAddr, BitMask); + return data; +} +void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) +{ + if (padapter->hal_func.write_bbreg) + padapter->hal_func.write_bbreg(padapter, RegAddr, BitMask, Data); +} + +u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask) +{ + u32 data = 0; + + if (padapter->hal_func.read_rfreg) { + data = padapter->hal_func.read_rfreg(padapter, eRFPath, RegAddr, BitMask); + + if (match_rf_read_sniff_ranges(eRFPath, RegAddr, BitMask)) { + RTW_INFO("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n" + , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data); + } + } + + return data; +} + +void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +{ + if (padapter->hal_func.write_rfreg) { + + if (match_rf_write_sniff_ranges(eRFPath, RegAddr, BitMask)) { + RTW_INFO("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n" + , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data); + } + + padapter->hal_func.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data); + + if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/ + rtw_udelay_os(2); + } +} + +s32 rtw_hal_interrupt_handler(_adapter *padapter) +{ + s32 ret = _FAIL; + ret = padapter->hal_func.interrupt_handler(padapter); + return ret; +} + +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + u8 cch_160 = Bandwidth == CHANNEL_WIDTH_160 ? channel : 0; + u8 cch_80 = Bandwidth == CHANNEL_WIDTH_80 ? channel : 0; + u8 cch_40 = Bandwidth == CHANNEL_WIDTH_40 ? channel : 0; + u8 cch_20 = Bandwidth == CHANNEL_WIDTH_20 ? channel : 0; + + odm_acquire_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); + if (pDM_Odm->rf_calibrate_info.is_iqk_in_progress == _TRUE) + RTW_ERR("%s, %d, IQK may race condition\n", __func__, __LINE__); + odm_release_spin_lock(pDM_Odm, RT_IQK_SPINLOCK); + + /* MP mode channel don't use secondary channel */ + if (rtw_mi_mp_mode_check(padapter) == _FALSE) { + if (cch_80 != 0) + cch_40 = rtw_get_scch_by_cch_offset(cch_80, CHANNEL_WIDTH_80, Offset80); + if (cch_40 != 0) + cch_20 = rtw_get_scch_by_cch_offset(cch_40, CHANNEL_WIDTH_40, Offset40); + } + + pHalData->cch_80 = cch_80; + pHalData->cch_40 = cch_40; + pHalData->cch_20 = cch_20; + + if (0) + RTW_INFO("%s cch:%u, %s, offset40:%u, offset80:%u (%u, %u, %u)\n", __func__ + , channel, ch_width_str(Bandwidth), Offset40, Offset80 + , pHalData->cch_80, pHalData->cch_40, pHalData->cch_20); + + padapter->hal_func.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80); +} + +void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel) +{ + if (padapter->hal_func.set_tx_power_level_handler) + padapter->hal_func.set_tx_power_level_handler(padapter, channel); +} + +void rtw_hal_dm_watchdog(_adapter *padapter) +{ + rtw_hal_turbo_edca(padapter); + padapter->hal_func.hal_dm_watchdog(padapter); + +} + +void rtw_hal_bcn_related_reg_setting(_adapter *padapter) +{ + padapter->hal_func.SetBeaconRelatedRegistersHandler(padapter); +} + +void rtw_hal_sreset_init(_adapter *padapter) +{ + padapter->hal_func.sreset_init_value(padapter); +} +void rtw_hal_sreset_reset(_adapter *padapter) +{ + padapter = GET_PRIMARY_ADAPTER(padapter); + padapter->hal_func.silentreset(padapter); +} + +void rtw_hal_sreset_reset_value(_adapter *padapter) +{ + padapter->hal_func.sreset_reset_value(padapter); +} + +void rtw_hal_sreset_xmit_status_check(_adapter *padapter) +{ + padapter->hal_func.sreset_xmit_status_check(padapter); +} +void rtw_hal_sreset_linked_status_check(_adapter *padapter) +{ + padapter->hal_func.sreset_linked_status_check(padapter); +} + +bool rtw_hal_sreset_inprogress(_adapter *padapter) +{ + padapter = GET_PRIMARY_ADAPTER(padapter); + return padapter->hal_func.sreset_inprogress(padapter); +} + +void rtw_hal_notch_filter(_adapter *adapter, bool enable) +{ + if (adapter->hal_func.hal_notch_filter) + adapter->hal_func.hal_notch_filter(adapter, enable); +} + +s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *odm = &hal_data->odmpriv; + u8 sub_id = 0; + s32 ret = _SUCCESS; + + switch (id) { + case C2H_FW_SCAN_COMPLETE: + RTW_INFO("[C2H], FW Scan Complete\n"); + break; + + case C2H_BT_INFO: + rtw_btcoex_BtInfoNotify(adapter, plen, payload); + break; + case C2H_BT_MP_INFO: + rtw_btcoex_BtMpRptNotify(adapter, plen, payload); + break; + case C2H_MAILBOX_STATUS: + RTW_INFO_DUMP("C2H_MAILBOX_STATUS: ", payload, plen); + break; + + case C2H_IQK_FINISH: + c2h_iqk_offload(adapter, payload, plen); + break; + + case C2H_MAC_HIDDEN_RPT: + c2h_mac_hidden_rpt_hdl(adapter, payload, plen); + break; + case C2H_MAC_HIDDEN_RPT_2: + c2h_mac_hidden_rpt_2_hdl(adapter, payload, plen); + break; + + case C2H_DEFEATURE_DBG: + c2h_defeature_dbg_hdl(adapter, payload, plen); + break; + + + case C2H_EXTEND: + sub_id = payload[0]; + /* no handle, goto default */ + + default: + if (phydm_c2H_content_parsing(odm, id, plen, payload) != TRUE) + ret = _FAIL; + break; + } + + if (ret != _SUCCESS) { + if (id == C2H_EXTEND) + RTW_WARN("%s: unknown C2H(0x%02x, 0x%02x)\n", __func__, id, sub_id); + else + RTW_WARN("%s: unknown C2H(0x%02x)\n", __func__, id); + } + + return ret; +} + +s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter) +{ + return GET_HAL_DATA(padapter)->bDisableSWChannelPlan; +} + +s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 support; + + support = _FALSE; + rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); + if (_FALSE == support) + return _FAIL; + + if (macid >= macid_ctl->num) { + RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n", + FUNC_ADPT_ARG(padapter), macid); + return _FAIL; + } + + rtw_hal_set_hwreg(padapter, HW_VAR_MACID_SLEEP, &macid); + + return _SUCCESS; +} + +s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 support; + + support = _FALSE; + rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); + if (_FALSE == support) + return _FAIL; + + if (macid >= macid_ctl->num) { + RTW_ERR(FUNC_ADPT_FMT": Invalid macid(%u)\n", + FUNC_ADPT_ARG(padapter), macid); + return _FAIL; + } + + rtw_hal_set_hwreg(padapter, HW_VAR_MACID_WAKEUP, &macid); + + return _SUCCESS; +} + +s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) +{ + _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); + + if (pri_adapter->bFWReady == _TRUE) + return padapter->hal_func.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer); + else if (padapter->registrypriv.mp_mode == 0) + RTW_PRINT(FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n" + , FUNC_ADPT_ARG(padapter), ElementID); + return _FAIL; +} + +void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame) +{ + padapter->hal_func.fill_fake_txdesc(padapter, pDesc, BufferLen, IsPsPoll, IsBTQosNull, bDataFrame); + +} +u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan) +{ + return adapter->hal_func.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); +} + +void rtw_hal_set_tx_power_index(PADAPTER padapter, u32 powerindex, u8 rfpath, u8 rate) +{ + return padapter->hal_func.set_tx_power_index_handler(padapter, powerindex, rfpath, rate); +} + +u8 rtw_hal_get_tx_power_index(PADAPTER padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) +{ + return padapter->hal_func.get_tx_power_index_handler(padapter, rfpath, rate, bandwidth, channel, tic); +} + +/* + * Description: + * Initialize MAC registers + * + * Return: + * _TRUE success + * _FALSE fail + */ +u8 rtw_hal_init_mac_register(PADAPTER adapter) +{ + return adapter->hal_func.init_mac_register(adapter); +} + +/* + * Description: + * Initialize PHY(BB/RF) related functions + * + * Return: + * _TRUE success + * _FALSE fail + */ +u8 rtw_hal_init_phy(PADAPTER adapter) +{ + return adapter->hal_func.init_phy(adapter); +} + +#define rtw_hal_error_msg(ops_fun) \ + RTW_PRINT("### %s - Error : Please hook hal_func.%s ###\n", __FUNCTION__, ops_fun) + +u8 rtw_hal_ops_check(_adapter *padapter) +{ + u8 ret = _SUCCESS; + /*** initialize section ***/ + if (NULL == padapter->hal_func.read_chip_version) { + rtw_hal_error_msg("read_chip_version"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.init_default_value) { + rtw_hal_error_msg("init_default_value"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.intf_chip_configure) { + rtw_hal_error_msg("intf_chip_configure"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.read_adapter_info) { + rtw_hal_error_msg("read_adapter_info"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.hal_power_on) { + rtw_hal_error_msg("hal_power_on"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.hal_power_off) { + rtw_hal_error_msg("hal_power_off"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.hal_init) { + rtw_hal_error_msg("hal_init"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.hal_deinit) { + rtw_hal_error_msg("hal_deinit"); + ret = _FAIL; + } + + /*** xmit section ***/ + if (NULL == padapter->hal_func.init_xmit_priv) { + rtw_hal_error_msg("init_xmit_priv"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.free_xmit_priv) { + rtw_hal_error_msg("free_xmit_priv"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.hal_xmit) { + rtw_hal_error_msg("hal_xmit"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.mgnt_xmit) { + rtw_hal_error_msg("mgnt_xmit"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.hal_xmitframe_enqueue) { + rtw_hal_error_msg("hal_xmitframe_enqueue"); + ret = _FAIL; + } + + /*** recv section ***/ + if (NULL == padapter->hal_func.init_recv_priv) { + rtw_hal_error_msg("init_recv_priv"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.free_recv_priv) { + rtw_hal_error_msg("free_recv_priv"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.inirp_init) { + rtw_hal_error_msg("inirp_init"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.inirp_deinit) { + rtw_hal_error_msg("inirp_deinit"); + ret = _FAIL; + } + + /*** interrupt hdl section ***/ + if (NULL == padapter->hal_func.irp_reset) { + rtw_hal_error_msg("irp_reset"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.interrupt_handler) { + rtw_hal_error_msg("interrupt_handler"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.enable_interrupt) { + rtw_hal_error_msg("enable_interrupt"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.disable_interrupt) { + rtw_hal_error_msg("disable_interrupt"); + ret = _FAIL; + } + + /*** DM section ***/ + if (NULL == padapter->hal_func.dm_init) { + rtw_hal_error_msg("dm_init"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.dm_deinit) { + rtw_hal_error_msg("dm_deinit"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.hal_dm_watchdog) { + rtw_hal_error_msg("hal_dm_watchdog"); + ret = _FAIL; + } + + /*** xxx section ***/ + if (NULL == padapter->hal_func.set_chnl_bw_handler) { + rtw_hal_error_msg("set_chnl_bw_handler"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.set_hw_reg_handler) { + rtw_hal_error_msg("set_hw_reg_handler"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.GetHwRegHandler) { + rtw_hal_error_msg("GetHwRegHandler"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.get_hal_def_var_handler) { + rtw_hal_error_msg("get_hal_def_var_handler"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.SetHalDefVarHandler) { + rtw_hal_error_msg("SetHalDefVarHandler"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.GetHalODMVarHandler) { + rtw_hal_error_msg("GetHalODMVarHandler"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.SetHalODMVarHandler) { + rtw_hal_error_msg("SetHalODMVarHandler"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.update_ra_mask_handler) { + rtw_hal_error_msg("update_ra_mask_handler"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.SetBeaconRelatedRegistersHandler) { + rtw_hal_error_msg("SetBeaconRelatedRegistersHandler"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.fill_h2c_cmd) { + rtw_hal_error_msg("fill_h2c_cmd"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.hal_mac_c2h_handler) { + rtw_hal_error_msg("hal_mac_c2h_handler"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.fill_fake_txdesc) { + rtw_hal_error_msg("fill_fake_txdesc"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.hal_get_tx_buff_rsvd_page_num) { + rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num"); + ret = _FAIL; + } + + + if (NULL == padapter->hal_func.fw_dl) { + rtw_hal_error_msg("fw_dl"); + ret = _FAIL; + } + + + if ((IS_HARDWARE_TYPE_8814A(padapter) + || IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter)) + && NULL == padapter->hal_func.fw_correct_bcn) { + rtw_hal_error_msg("fw_correct_bcn"); + ret = _FAIL; + } + + if (IS_HARDWARE_TYPE_8822B(padapter) || IS_HARDWARE_TYPE_8821C(padapter)) { + if (!padapter->hal_func.set_tx_power_index_handler) { + rtw_hal_error_msg("set_tx_power_index_handler"); + ret = _FAIL; + } + } + + if (!padapter->hal_func.get_tx_power_index_handler) { + rtw_hal_error_msg("get_tx_power_index_handler"); + ret = _FAIL; + } + + /*** SReset section ***/ + if (NULL == padapter->hal_func.sreset_init_value) { + rtw_hal_error_msg("sreset_init_value"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.sreset_reset_value) { + rtw_hal_error_msg("sreset_reset_value"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.silentreset) { + rtw_hal_error_msg("silentreset"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.sreset_xmit_status_check) { + rtw_hal_error_msg("sreset_xmit_status_check"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.sreset_linked_status_check) { + rtw_hal_error_msg("sreset_linked_status_check"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.sreset_get_wifi_status) { + rtw_hal_error_msg("sreset_get_wifi_status"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.sreset_inprogress) { + rtw_hal_error_msg("sreset_inprogress"); + ret = _FAIL; + } + + if (NULL == padapter->hal_func.init_mac_register) { + rtw_hal_error_msg("init_mac_register"); + ret = _FAIL; + } + if (NULL == padapter->hal_func.init_phy) { + rtw_hal_error_msg("init_phy"); + ret = _FAIL; + } + return ret; +} diff --git a/drivers/staging/rtl8821ce/hal/hal_mp.c b/drivers/staging/rtl8821ce/hal/hal_mp.c new file mode 100644 index 000000000000..d2f0aa346f8c --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/hal_mp.c @@ -0,0 +1,1414 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <hal_data.h> /* struct HAL_DATA_TYPE, RF register definition and etc. */ + +void hal_mpt_SwitchRfSetting(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u8 ChannelToSw = pMptCtx->MptChannelToSw; + ULONG ulRateIdx = pMptCtx->mpt_rate_index; + ULONG ulbandwidth = pMptCtx->MptBandWidth; + + /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/ + if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) && + (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) { + pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0); + + if ((PlatformEFIORead4Byte(pAdapter, 0xF4) & BIT29) == BIT29) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); + } else { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD); + } + } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/ + if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + } else { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + } + } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); + } +} + +s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + + if (!netif_running(padapter->pnetdev)) { + return _FAIL; + } + + if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { + return _FAIL; + } + if (enable) + pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE; + else + pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE; + + return _SUCCESS; +} + +void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) +{ + u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0; + u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12; + u8 i; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); + u1Byte u1Channel = pHalData->current_channel; + ULONG ulRateIdx = pMptCtx->mpt_rate_index; + u1Byte DataRate = 0xFF; + + /* Do not modify CCK TX filter parameters for 8822B*/ + if(IS_HARDWARE_TYPE_8822B(Adapter) || IS_HARDWARE_TYPE_8821C(Adapter) || IS_HARDWARE_TYPE_8723D(Adapter)) + return; + + DataRate = mpt_to_mgnt_rate(ulRateIdx); + + if (u1Channel == 14 && IS_CCK_RATE(DataRate)) + pHalData->bCCKinCH14 = TRUE; + else + pHalData->bCCKinCH14 = FALSE; + + if (IS_HARDWARE_TYPE_8703B(Adapter)) { + if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) { + /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */ + phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0); + phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskLWord, 0); + + } else { + /* Normal setting for 8703B, just recover to the default setting. */ + /* This hardcore values reference from the parameter which BB team gave. */ + for (i = 0 ; i < 2 ; ++i) + phy_set_bb_reg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value); + + } + } else if (IS_HARDWARE_TYPE_8723D(Adapter)) { + /* 2.4G CCK TX DFIR */ + /* 2016.01.20 Suggest from RS BB mingzhi*/ + if ((u1Channel == 14)) { + phy_set_bb_reg(Adapter, rCCK0_TxFilter2, bMaskDWord, 0x0000B81C); + phy_set_bb_reg(Adapter, rCCK0_DebugPort, bMaskDWord, 0x00000000); + phy_set_bb_reg(Adapter, 0xAAC, bMaskDWord, 0x00003667); + } else { + for (i = 0 ; i < 3 ; ++i) { + phy_set_bb_reg(Adapter, + pHalData->RegForRecover[i].offset, + bMaskDWord, + pHalData->RegForRecover[i].value); + } + } + } else if (IS_HARDWARE_TYPE_8188F(Adapter)) { + /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/ + CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); + CCKSwingIndex = 20; /* default index */ + + if (!pHalData->bCCKinCH14) { + /* Readback the current bb cck swing value and compare with the table to */ + /* get the current swing index */ + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13_88f[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13_88f[i][1])) { + CCKSwingIndex = i; + break; + } + } + write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][0]); + write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][1]); + write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][2]); + write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][3]); + write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][4]); + write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][5]); + write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][6]); + write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][7]); + write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][8]); + write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][9]); + write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][10]); + write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][11]); + write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][12]); + write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][13]); + write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][14]); + write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch1_ch13_88f[CCKSwingIndex][15]); + RTW_INFO("%s , cck_swing_table_ch1_ch13_88f[%d]\n", __func__, CCKSwingIndex); + } else { + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14_88f[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14_88f[i][1])) { + CCKSwingIndex = i; + break; + } + } + write_bbreg(Adapter, 0xa22, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][0]); + write_bbreg(Adapter, 0xa23, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][1]); + write_bbreg(Adapter, 0xa24, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][2]); + write_bbreg(Adapter, 0xa25, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][3]); + write_bbreg(Adapter, 0xa26, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][4]); + write_bbreg(Adapter, 0xa27, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][5]); + write_bbreg(Adapter, 0xa28, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][6]); + write_bbreg(Adapter, 0xa29, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][7]); + write_bbreg(Adapter, 0xa9a, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][8]); + write_bbreg(Adapter, 0xa9b, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][9]); + write_bbreg(Adapter, 0xa9c, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][10]); + write_bbreg(Adapter, 0xa9d, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][11]); + write_bbreg(Adapter, 0xaa0, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][12]); + write_bbreg(Adapter, 0xaa1, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][13]); + write_bbreg(Adapter, 0xaa2, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][14]); + write_bbreg(Adapter, 0xaa3, bMaskByte0, cck_swing_table_ch14_88f[CCKSwingIndex][15]); + RTW_INFO("%s , cck_swing_table_ch14_88f[%d]\n", __func__, CCKSwingIndex); + } + } else { + + /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/ + CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); + + if (!pHalData->bCCKinCH14) { + /* Readback the current bb cck swing value and compare with the table to */ + /* get the current swing index */ + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch1_ch13[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch1_ch13[i][1])) { + CCKSwingIndex = i; + break; + } + } + + /*Write 0xa22 0xa23*/ + TempVal = cck_swing_table_ch1_ch13[CCKSwingIndex][0] + + (cck_swing_table_ch1_ch13[CCKSwingIndex][1] << 8); + + /*Write 0xa24 ~ 0xa27*/ + TempVal2 = 0; + TempVal2 = cck_swing_table_ch1_ch13[CCKSwingIndex][2] + + (cck_swing_table_ch1_ch13[CCKSwingIndex][3] << 8) + + (cck_swing_table_ch1_ch13[CCKSwingIndex][4] << 16) + + (cck_swing_table_ch1_ch13[CCKSwingIndex][5] << 24); + + /*Write 0xa28 0xa29*/ + TempVal3 = 0; + TempVal3 = cck_swing_table_ch1_ch13[CCKSwingIndex][6] + + (cck_swing_table_ch1_ch13[CCKSwingIndex][7] << 8); + } else { + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (((CurrCCKSwingVal & 0xff) == (u32)cck_swing_table_ch14[i][0]) && + (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)cck_swing_table_ch14[i][1])) { + CCKSwingIndex = i; + break; + } + } + + /*Write 0xa22 0xa23*/ + TempVal = cck_swing_table_ch14[CCKSwingIndex][0] + + (cck_swing_table_ch14[CCKSwingIndex][1] << 8); + + /*Write 0xa24 ~ 0xa27*/ + TempVal2 = 0; + TempVal2 = cck_swing_table_ch14[CCKSwingIndex][2] + + (cck_swing_table_ch14[CCKSwingIndex][3] << 8) + + (cck_swing_table_ch14[CCKSwingIndex][4] << 16) + + (cck_swing_table_ch14[CCKSwingIndex][5] << 24); + + /*Write 0xa28 0xa29*/ + TempVal3 = 0; + TempVal3 = cck_swing_table_ch14[CCKSwingIndex][6] + + (cck_swing_table_ch14[CCKSwingIndex][7] << 8); + } + + write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal); + write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2); + write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3); + } + +} + +void hal_mpt_SetChannel(PADAPTER pAdapter) +{ + u8 eRFPath; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + struct mp_priv *pmp = &pAdapter->mppriv; + u8 channel = pmp->channel; + u8 bandwidth = pmp->bandwidth; + + hal_mpt_SwitchRfSetting(pAdapter); + + pHalData->bSwChnl = _TRUE; + pHalData->bSetChnlBW = _TRUE; + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + + hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14); + +} + +/* + * Notice + * Switch bandwitdth may change center frequency(channel) + */ +void hal_mpt_SetBandwidth(PADAPTER pAdapter) +{ + struct mp_priv *pmp = &pAdapter->mppriv; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + u8 channel = pmp->channel; + u8 bandwidth = pmp->bandwidth; + + pHalData->bSwChnl = _TRUE; + pHalData->bSetChnlBW = _TRUE; + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + + hal_mpt_SwitchRfSetting(pAdapter); +} + +void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) +{ + switch (Rate) { + case MPT_CCK: { + u4Byte TxAGC = 0, pwr = 0; + u1Byte rf; + + pwr = pTxPower[ODM_RF_PATH_A]; + if (pwr < 0x3f) { + TxAGC = (pwr << 16) | (pwr << 8) | (pwr); + phy_set_bb_reg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + } + pwr = pTxPower[ODM_RF_PATH_B]; + if (pwr < 0x3f) { + TxAGC = (pwr << 16) | (pwr << 8) | (pwr); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]); + phy_set_bb_reg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC); + } + } + break; + + case MPT_OFDM_AND_HT: { + u4Byte TxAGC = 0; + u1Byte pwr = 0, rf; + + pwr = pTxPower[0]; + if (pwr < 0x3f) { + TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + RTW_INFO("HT Tx-rf(A) Power = 0x%x\n", TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + } + TxAGC = 0; + pwr = pTxPower[1]; + if (pwr < 0x3f) { + TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + RTW_INFO("HT Tx-rf(B) Power = 0x%x\n", TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); + phy_set_bb_reg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); + } + } + break; + + default: + break; + } + RTW_INFO("<===mpt_SetTxPower_Old()\n"); +} + +void +mpt_SetTxPower( + PADAPTER pAdapter, + MPT_TXPWR_DEF Rate, + pu1Byte pTxPower +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + u1Byte path = 0 , i = 0, MaxRate = MGN_6M; + u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B; + + if (IS_HARDWARE_TYPE_8814A(pAdapter)) + EndPath = ODM_RF_PATH_D; + else if (IS_HARDWARE_TYPE_8188F(pAdapter) || IS_HARDWARE_TYPE_8723D(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) + EndPath = ODM_RF_PATH_A; + + switch (Rate) { + case MPT_CCK: { + u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; + + for (path = StartPath; path <= EndPath; path++) + for (i = 0; i < sizeof(rate); ++i) + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } + break; + case MPT_OFDM: { + u1Byte rate[] = { + MGN_6M, MGN_9M, MGN_12M, MGN_18M, + MGN_24M, MGN_36M, MGN_48M, MGN_54M, + }; + + for (path = StartPath; path <= EndPath; path++) + for (i = 0; i < sizeof(rate); ++i) + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } + break; + case MPT_HT: { + u1Byte rate[] = { + MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, + MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9, + MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, + MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, + MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24, + MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, + MGN_MCS30, MGN_MCS31, + }; + if (pHalData->rf_type == RF_3T3R) + MaxRate = MGN_MCS23; + else if (pHalData->rf_type == RF_2T2R) + MaxRate = MGN_MCS15; + else + MaxRate = MGN_MCS7; + for (path = StartPath; path <= EndPath; path++) { + for (i = 0; i < sizeof(rate); ++i) { + if (rate[i] > MaxRate) + break; + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } + } + } + break; + case MPT_VHT: { + u1Byte rate[] = { + MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9, + MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, + MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, + MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4, + MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9, + }; + if (pHalData->rf_type == RF_3T3R) + MaxRate = MGN_VHT3SS_MCS9; + else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) + MaxRate = MGN_VHT2SS_MCS9; + else + MaxRate = MGN_VHT1SS_MCS9; + + for (path = StartPath; path <= EndPath; path++) { + for (i = 0; i < sizeof(rate); ++i) { + if (rate[i] > MaxRate) + break; + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } + } + } + break; + default: + RTW_INFO("<===mpt_SetTxPower: Illegal channel!!\n"); + break; + } +} + +void hal_mpt_SetTxPower(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + + if (pHalData->rf_chip < RF_TYPE_MAX) { + if (IS_HARDWARE_TYPE_8188E(pAdapter) || + IS_HARDWARE_TYPE_8723B(pAdapter) || + IS_HARDWARE_TYPE_8192E(pAdapter) || + IS_HARDWARE_TYPE_8703B(pAdapter) || + IS_HARDWARE_TYPE_8188F(pAdapter)) { + u8 path = (pHalData->antenna_tx_path == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B); + + RTW_INFO("===> MPT_ProSetTxPower: Old\n"); + + mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel); + mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel); + + } else { + RTW_INFO("===> MPT_ProSetTxPower: Jaguar/Jaguar2\n"); + mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel); + mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel); + mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel); + mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel); + + } + } else + RTW_INFO("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip); + + odm_clear_txpowertracking_state(pDM_Odm); +} + +void hal_mpt_SetDataRate(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u32 DataRate; + + DataRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index); + + hal_mpt_SwitchRfSetting(pAdapter); + + hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14); +} + +#define RF_PATH_AB 22 + +VOID +mpt_SetSingleTone_8814A( + IN PADAPTER pAdapter, + IN BOOLEAN bSingleTone, + IN BOOLEAN bEnPMacTx) +{ + + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A; + static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0; + + if (bSingleTone) { + regIG0 = phy_query_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/ + regIG1 = phy_query_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/ + regIG2 = phy_query_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/ + regIG3 = phy_query_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/ + + switch (pMptCtx->mpt_rf_path) { + case ODM_RF_PATH_A: + case ODM_RF_PATH_B: + case ODM_RF_PATH_C: + case ODM_RF_PATH_D: + StartPath = pMptCtx->mpt_rf_path; + EndPath = pMptCtx->mpt_rf_path; + break; + case ODM_RF_PATH_AB: + EndPath = ODM_RF_PATH_B; + break; + case ODM_RF_PATH_BC: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_ABC: + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_BCD: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_D; + break; + case ODM_RF_PATH_ABCD: + EndPath = ODM_RF_PATH_D; + break; + } + + if (bEnPMacTx == FALSE) { + hal_mpt_SetContinuousTx(pAdapter, _TRUE); + issue_nulldata(pAdapter, NULL, 1, 3, 500); + } + + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/ + + for (; StartPath <= EndPath; StartPath++) { + phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ + phy_set_rf_reg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ + + phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + } + + phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/ + phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/ + phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/ + phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/ + } else { + switch (pMptCtx->mpt_rf_path) { + case ODM_RF_PATH_A: + case ODM_RF_PATH_B: + case ODM_RF_PATH_C: + case ODM_RF_PATH_D: + StartPath = pMptCtx->mpt_rf_path; + EndPath = pMptCtx->mpt_rf_path; + break; + case ODM_RF_PATH_AB: + EndPath = ODM_RF_PATH_B; + break; + case ODM_RF_PATH_BC: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_ABC: + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_BCD: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_D; + break; + case ODM_RF_PATH_ABCD: + EndPath = ODM_RF_PATH_D; + break; + } + for (; StartPath <= EndPath; StartPath++) + phy_set_rf_reg(pAdapter, StartPath, lna_low_gain_3, BIT1, 0x0); /* RF LO disabled */ + + phy_set_bb_reg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/ + + if (bEnPMacTx == FALSE) + hal_mpt_SetContinuousTx(pAdapter, _FALSE); + + phy_set_bb_reg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/ + phy_set_bb_reg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/ + phy_set_bb_reg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/ + phy_set_bb_reg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/ + } +} + +VOID mpt_SetRFPath_819X(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u4Byte ulAntennaTx, ulAntennaRx; + R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ + R_ANTENNA_SELECT_CCK *p_cck_txrx; + u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0; + u1Byte chgTx = 0, chgRx = 0; + u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0; + + ulAntennaTx = pHalData->antenna_tx_path; + ulAntennaRx = pHalData->AntennaRxPath; + + p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val; + p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val; + + p_ofdm_tx->r_ant_ht1 = 0x1; + p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/ + p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */ + + switch (ulAntennaTx) { + case ANTENNA_A: + p_ofdm_tx->r_tx_antenna = 0x1; + r_ofdm_tx_en_val = 0x1; + p_ofdm_tx->r_ant_l = 0x1; + p_ofdm_tx->r_ant_ht_s1 = 0x1; + p_ofdm_tx->r_ant_non_ht_s1 = 0x1; + p_cck_txrx->r_ccktx_enable = 0x8; + chgTx = 1; + /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/ + /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ + { + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); + r_ofdm_tx_en_val = 0x3; + /*/ Power save*/ + /*/cosa r_ant_select_ofdm_val = 0x11111111;*/ + /*/ We need to close RFB by SW control*/ + if (pHalData->rf_type == RF_2T2R) { + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); + } + } + pMptCtx->mpt_rf_path = ODM_RF_PATH_A; + break; + case ANTENNA_B: + p_ofdm_tx->r_tx_antenna = 0x2; + r_ofdm_tx_en_val = 0x2; + p_ofdm_tx->r_ant_l = 0x2; + p_ofdm_tx->r_ant_ht_s1 = 0x2; + p_ofdm_tx->r_ant_non_ht_s1 = 0x2; + p_cck_txrx->r_ccktx_enable = 0x4; + chgTx = 1; + /*/ From SD3 Willis suggestion !!! Set RF A as standby*/ + /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ + { + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); + + /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/ + /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/ + if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) { + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); + /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); + } + } + pMptCtx->mpt_rf_path = ODM_RF_PATH_B; + break; + case ANTENNA_AB:/*/ For 8192S*/ + p_ofdm_tx->r_tx_antenna = 0x3; + r_ofdm_tx_en_val = 0x3; + p_ofdm_tx->r_ant_l = 0x3; + p_ofdm_tx->r_ant_ht_s1 = 0x3; + p_ofdm_tx->r_ant_non_ht_s1 = 0x3; + p_cck_txrx->r_ccktx_enable = 0xC; + chgTx = 1; + /*/ From SD3Willis suggestion !!! Set RF B as standby*/ + /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ + { + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); + /* Disable Power save*/ + /*cosa r_ant_select_ofdm_val = 0x3321333;*/ + /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/ + if (pHalData->rf_type == RF_2T2R) { + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); + + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); + /*/phy_set_bb_reg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); + } + } + pMptCtx->mpt_rf_path = ODM_RF_PATH_AB; + break; + default: + break; + } + switch (ulAntennaRx) { + case ANTENNA_A: + r_rx_antenna_ofdm = 0x1; /* A*/ + p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/ + p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/ + chgRx = 1; + break; + case ANTENNA_B: + r_rx_antenna_ofdm = 0x2; /*/ B*/ + p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/ + p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/ + chgRx = 1; + break; + case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/ + r_rx_antenna_ofdm = 0x3;/*/ AB*/ + p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/ + p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/ + chgRx = 1; + break; + default: + break; + } + + if (chgTx && chgRx) { + switch (pHalData->rf_chip) { + case RF_8225: + case RF_8256: + case RF_6052: + /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/ + phy_set_bb_reg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/ + phy_set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ + phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ + if (IS_HARDWARE_TYPE_8192E(pAdapter)) { + phy_set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ + phy_set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ + } + phy_set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/ + break; + + default: + RTW_INFO("Unsupported RFChipID for switching antenna.\n"); + break; + } + } +} /* MPT_ProSetRFPath */ + +void hal_mpt_SetAntenna(PADAPTER pAdapter) + +{ + RTW_INFO("Do %s\n", __func__); + if (IS_HARDWARE_TYPE_8821C(pAdapter)) { + rtl8821c_mp_config_rfpath(pAdapter); + return; + } + + /* else if (IS_HARDWARE_TYPE_8821B(pAdapter)) + mpt_SetRFPath_8821B(pAdapter); + Prepare for 8822B + else if (IS_HARDWARE_TYPE_8822B(Context)) + mpt_SetRFPath_8822B(Context); + */ + mpt_SetRFPath_819X(pAdapter); + RTW_INFO("mpt_SetRFPath_819X Do %s\n", __func__); +} + +s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + if (!netif_running(pAdapter->pnetdev)) { + return _FAIL; + } + + if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { + return _FAIL; + } + + target_ther &= 0xff; + if (target_ther < 0x07) + target_ther = 0x07; + else if (target_ther > 0x1d) + target_ther = 0x1d; + + pHalData->eeprom_thermal_meter = target_ther; + + return _SUCCESS; +} + +void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) +{ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); + +} + +u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter) + +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(pAdapter); + struct PHY_DM_STRUCT *p_dm_odm = &hal_data->odmpriv; + u32 ThermalValue = 0; + s32 thermal_value_temp = 0; + s8 thermal_offset = 0; + + ThermalValue = (u1Byte)phy_query_rf_reg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ + thermal_offset = phydm_get_thermal_offset(p_dm_odm); + + thermal_value_temp = ThermalValue + thermal_offset; + + if (thermal_value_temp > 63) + ThermalValue = 63; + else if (thermal_value_temp < 0) + ThermalValue = 0; + else + ThermalValue = thermal_value_temp; + + return (u8)ThermalValue; +} + +void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value) +{ + hal_mpt_TriggerRFThermalMeter(pAdapter); + rtw_msleep_os(1000); + *value = hal_mpt_ReadRFThermalMeter(pAdapter); + +} + +void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + pAdapter->mppriv.mpt_ctx.bSingleCarrier = bStart; + + if (bStart) {/*/ Start Single Carrier.*/ + /*/ Start Single Carrier.*/ + /*/ 1. if OFDM block on?*/ + if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/ + + /*/ 2. set CCK test mode off, set to CCK normal mode*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0); + + /*/ 3. turn on scramble setting*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1); + + /*/ 4. Turn On Continue Tx and turn off the other test modes.*/ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) + phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_SingleCarrier); + else + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleCarrier); + + } else { + /*/ Stop Single Carrier.*/ + /*/ Stop Single Carrier.*/ + /*/ Turn off all test modes.*/ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) + phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + else + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + + rtw_msleep_os(10); + /*/BB Reset*/ + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + } +} + +void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u4Byte ulAntennaTx = pHalData->antenna_tx_path; + static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0; + u8 rfPath; + + switch (ulAntennaTx) { + case ANTENNA_B: + rfPath = ODM_RF_PATH_B; + break; + case ANTENNA_C: + rfPath = ODM_RF_PATH_C; + break; + case ANTENNA_D: + rfPath = ODM_RF_PATH_D; + break; + case ANTENNA_A: + default: + rfPath = ODM_RF_PATH_A; + break; + } + + pAdapter->mppriv.mpt_ctx.is_single_tone = bStart; + if (bStart) { + /*/ Start Single Tone.*/ + /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/ + if (IS_HARDWARE_TYPE_8188E(pAdapter)) { + regRF = phy_query_rf_reg(pAdapter, rfPath, lna_low_gain_3, bRFRegOffsetMask); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); + } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/ + /*/Set MAC REG 88C: Prevent SingleTone Fail*/ + phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0xF); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); /*/ RF LO disabled*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ + } else { + /*/ S0/S1 both use PATH A to configure*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ + } + } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ + } + } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { + /*Set BB REG 88C: Prevent SingleTone Fail*/ + phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x1); + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x2); + + } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x1); + } else {/* S0/S1 both use PATH A to configure */ + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x0); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x1); + } + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { + } + else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) + mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE); + + else /*/ Turn On SingleTone and turn off the other test modes.*/ + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_SingleTone); + + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + } else {/*/ Stop Single Ton e.*/ + + if (IS_HARDWARE_TYPE_8188E(pAdapter)) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, lna_low_gain_3, bRFRegOffsetMask, regRF); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); + } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0);/*/ RF LO disabled */ + /*/ RESTORE MAC REG 88C: Enable RF Functions*/ + phy_set_mac_reg(pAdapter, 0x88C, 0xF00000, 0x0); + } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ + } else { + /*/ S0/S1 both use PATH A to configure*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ + } + } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ + } + } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, RF_AC, 0xF0000, 0x3); /*Tx mode*/ + phy_set_rf_reg(pAdapter, pMptCtx->mpt_rf_path, lna_low_gain_3, BIT1, 0x0); /*RF LO disabled*/ + /*Set BB REG 88C: Prevent SingleTone Fail*/ + phy_set_bb_reg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc); + } else if (IS_HARDWARE_TYPE_8723D(pAdapter)) { + if (pMptCtx->mpt_rf_path == ODM_RF_PATH_A) { + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x53, BIT0, 0x0); + } else { /* S0/S1 both use PATH A to configure */ + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x3); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, RF_AC, BIT16, 0x1); + phy_set_rf_reg(pAdapter, ODM_RF_PATH_A, 0x63, BIT0, 0x0); + } + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { + } + else if (IS_HARDWARE_TYPE_8814A(pAdapter) || IS_HARDWARE_TYPE_8821C(pAdapter)) + mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE); + + else/*/ Turn off all test modes.*/ + phy_set_bb_reg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + + } +} + +void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) +{ + u8 Rate; + + pAdapter->mppriv.mpt_ctx.is_carrier_suppression = bStart; + + Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); + if (bStart) {/* Start Carrier Suppression.*/ + if (Rate <= MPT_RATE_11M) { + /*/ 1. if CCK block on?*/ + if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) + write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/ + + /*/Turn Off All Test Mode*/ + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); /* rSingleTone_ContTx_Jaguar*/ + else + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + + write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/ + write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/ + + /*/Set CCK Tx Test Rate*/ + write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/ + } + + /*Set for dynamic set Power index*/ + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + } else {/* Stop Carrier Suppression.*/ + + if (Rate <= MPT_RATE_11M) { + write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/ + write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + + /*BB Reset*/ + write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + } + /*Stop for dynamic set Power index*/ + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + } + RTW_INFO("\n MPT_ProSetCarrierSupp() is finished.\n"); +} + +u32 hal_mpt_query_phytxok(PADAPTER pAdapter) +{ + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; + u16 count = 0; + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + count = phy_query_bb_reg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/ + else + count = phy_query_bb_reg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/ + + if (count > 50000) { + rtw_reset_phy_trx_ok_counters(pAdapter); + pAdapter->mppriv.tx.sended += count; + count = 0; + } + + return pAdapter->mppriv.tx.sended + count; + +} + +static VOID mpt_StopCckContTx( + PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u1Byte u1bReg; + + pMptCtx->bCckContTx = FALSE; + pMptCtx->bOfdmContTx = FALSE; + + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + + if (!IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ + + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 0); + phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 0); + } + + /*BB Reset*/ + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + +} /* mpt_StopCckContTx */ + +static VOID mpt_StopOfdmContTx( + PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u1Byte u1bReg; + u4Byte data; + + pMptCtx->bCckContTx = FALSE; + pMptCtx->bOfdmContTx = FALSE; + + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + else + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + + rtw_mdelay_os(10); + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ + } + + /*BB Reset*/ + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + phy_set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); +} /* mpt_StopOfdmContTx */ + +static VOID mpt_StartCckContTx( + PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + u4Byte cckrate; + + /* 1. if CCK block on */ + if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/ + + /*Turn Off All Test Mode*/ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ALL_OFF); + else + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ALL_OFF); + + cckrate = pAdapter->mppriv.rateidx; + + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); + + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + + if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) { + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/ + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, BIT14, 1); + phy_set_bb_reg(pAdapter, 0x0B34, BIT14, 1); + } + + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + pMptCtx->bCckContTx = TRUE; + pMptCtx->bOfdmContTx = FALSE; + +} /* mpt_StartCckContTx */ + +static VOID mpt_StartOfdmContTx( + PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx); + + /* 1. if OFDM block on?*/ + if (!phy_query_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) + phy_set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/ + + /* 2. set CCK test mode off, set to CCK normal mode*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0); + + /* 3. turn on scramble setting*/ + phy_set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, 1); + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + phy_set_bb_reg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/ + phy_set_bb_reg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/ + } + + /* 4. Turn On Continue Tx and turn off the other test modes.*/ + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) + phy_set_bb_reg(pAdapter, 0x914, BIT18 | BIT17 | BIT16, OFDM_ContinuousTx); + else + phy_set_bb_reg(pAdapter, rOFDM1_LSTF, BIT30 | BIT29 | BIT28, OFDM_ContinuousTx); + + phy_set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + phy_set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + pMptCtx->bCckContTx = FALSE; + pMptCtx->bOfdmContTx = TRUE; +} /* mpt_StartOfdmContTx */ + +/* for HW TX mode */ +void mpt_ProSetPMacTx(PADAPTER Adapter) +{ + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx); + RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; + u32 u4bTmp; + + dbg_print("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); + dbg_print("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, + PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern); + + if (PMacTxInfo.bEnPMacTx == FALSE) { + if (PMacTxInfo.Mode == CONTINUOUS_TX) { + phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StopCckContTx(Adapter); + else + mpt_StopOfdmContTx(Adapter); + } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp = phy_query_bb_reg(Adapter, 0xf50, bMaskLWord); + phy_set_bb_reg(Adapter, 0xb1c, bMaskLWord, u4bTmp + 50); + phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/ + } else + phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ + + if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { + /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/ + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StopCckContTx(Adapter); + else + mpt_StopOfdmContTx(Adapter); + + mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE); + } + + return; + } + + if (PMacTxInfo.Mode == CONTINUOUS_TX) { + PMacTxInfo.PacketCount = 1; + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StartCckContTx(Adapter); + else + mpt_StartOfdmContTx(Adapter); + } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { + /* Continuous TX -> HW TX -> RF Setting */ + PMacTxInfo.PacketCount = 1; + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StartCckContTx(Adapter); + else + mpt_StartOfdmContTx(Adapter); + } else if (PMacTxInfo.Mode == PACKETS_TX) { + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0) + PMacTxInfo.PacketCount = 0xffff; + } + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { + /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/ + u4bTmp = PMacTxInfo.PacketCount | (PMacTxInfo.SFD << 16); + phy_set_bb_reg(Adapter, 0xb1c, bMaskDWord, u4bTmp); + /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/ + u4bTmp = PMacTxInfo.SignalField | (PMacTxInfo.ServiceField << 8) | (PMacTxInfo.LENGTH << 16); + phy_set_bb_reg(Adapter, 0xb40, bMaskDWord, u4bTmp); + u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8); + phy_set_bb_reg(Adapter, 0xb44, bMaskLWord, u4bTmp); + + if (PMacTxInfo.bSPreamble) + phy_set_bb_reg(Adapter, 0xb0c, BIT27, 0); + else + phy_set_bb_reg(Adapter, 0xb0c, BIT27, 1); + } else { + phy_set_bb_reg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount); + + u4bTmp = PMacTxInfo.LSIG[0] | ((PMacTxInfo.LSIG[1]) << 8) | ((PMacTxInfo.LSIG[2]) << 16) | ((PMacTxInfo.PacketPattern) << 24); + phy_set_bb_reg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/ + + if (PMacTxInfo.PacketPattern == 0x12) + u4bTmp = 0x3000000; + else + u4bTmp = 0; + } + + if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp |= PMacTxInfo.HT_SIG[0] | ((PMacTxInfo.HT_SIG[1]) << 8) | ((PMacTxInfo.HT_SIG[2]) << 16); + phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp); + u4bTmp = PMacTxInfo.HT_SIG[3] | ((PMacTxInfo.HT_SIG[4]) << 8) | ((PMacTxInfo.HT_SIG[5]) << 16); + phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp); + } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp |= PMacTxInfo.VHT_SIG_A[0] | ((PMacTxInfo.VHT_SIG_A[1]) << 8) | ((PMacTxInfo.VHT_SIG_A[2]) << 16); + phy_set_bb_reg(Adapter, 0xb0c, bMaskDWord, u4bTmp); + u4bTmp = PMacTxInfo.VHT_SIG_A[3] | ((PMacTxInfo.VHT_SIG_A[4]) << 8) | ((PMacTxInfo.VHT_SIG_A[5]) << 16); + phy_set_bb_reg(Adapter, 0xb10, 0xffffff, u4bTmp); + + _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4); + phy_set_bb_reg(Adapter, 0xb14, bMaskDWord, u4bTmp); + } + + if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24) | PMacTxInfo.PacketPeriod; /* for TX interval */ + phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, u4bTmp); + + _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4); + phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, u4bTmp); + + /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/ + /*& Duration & Frame control*/ + phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, 0x00000040); + + /* Address1 [0:3]*/ + u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24); + phy_set_bb_reg(Adapter, 0xb2C, bMaskDWord, u4bTmp); + + /* Address3 [3:0]*/ + phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp); + + /* Address2[0:1] & Address1 [5:4]*/ + u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24); + phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp); + + /* Address2 [5:2]*/ + u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24); + phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp); + + /* Sequence Control & Address3 [5:4]*/ + /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/ + /*phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/ + } else { + phy_set_bb_reg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/ + /* & Duration & Frame control */ + phy_set_bb_reg(Adapter, 0xb24, bMaskDWord, 0x00000040); + + /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/ + /* Address1 [0:3]*/ + u4bTmp = PMacTxInfo.MacAddress[0] | (PMacTxInfo.MacAddress[1] << 8) | (PMacTxInfo.MacAddress[2] << 16) | (PMacTxInfo.MacAddress[3] << 24); + phy_set_bb_reg(Adapter, 0xb28, bMaskDWord, u4bTmp); + + /* Address3 [3:0]*/ + phy_set_bb_reg(Adapter, 0xb34, bMaskDWord, u4bTmp); + + /* Address2[0:1] & Address1 [5:4]*/ + u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8) | (Adapter->mac_addr[0] << 16) | (Adapter->mac_addr[1] << 24); + phy_set_bb_reg(Adapter, 0xb2c, bMaskDWord, u4bTmp); + + /* Address2 [5:2] */ + u4bTmp = Adapter->mac_addr[2] | (Adapter->mac_addr[3] << 8) | (Adapter->mac_addr[4] << 16) | (Adapter->mac_addr[5] << 24); + phy_set_bb_reg(Adapter, 0xb30, bMaskDWord, u4bTmp); + + /* Sequence Control & Address3 [5:4]*/ + u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8); + phy_set_bb_reg(Adapter, 0xb38, bMaskDWord, u4bTmp); + } + + phy_set_bb_reg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX); + + /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/ + u4bTmp = (PMacTxInfo.TX_SC) | ((PMacTxInfo.BandWidth) << 4) | ((PMacTxInfo.m_STBC - 1) << 6) | ((PMacTxInfo.NDP_sound) << 8); + phy_set_bb_reg(Adapter, 0xb4c, 0x1ff, u4bTmp); + + if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) { + u4Byte offset = 0xb44; + + if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE)) + phy_set_bb_reg(Adapter, offset, 0xc0000000, 0); + else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) + phy_set_bb_reg(Adapter, offset, 0xc0000000, 1); + else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) + phy_set_bb_reg(Adapter, offset, 0xc0000000, 2); + } + + phy_set_bb_reg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/ + /* phy_set_bb_reg(Adapter, 0xb04, 0xf, 2); */ /* TX Stop */ + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { + phy_set_bb_reg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/ + phy_set_bb_reg(Adapter, 0xA84, BIT31, 0); + } else + phy_set_bb_reg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */ + + if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) + mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE); + +} + +void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + u8 Rate; + + RT_TRACE(_module_mp_, _drv_info_, + ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); + Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); + pAdapter->mppriv.mpt_ctx.is_start_cont_tx = bStart; + + if (Rate <= MPT_RATE_11M) { + if (bStart) + mpt_StartCckContTx(pAdapter); + else + mpt_StopCckContTx(pAdapter); + + } else if (Rate >= MPT_RATE_6M) { + if (bStart) + mpt_StartOfdmContTx(pAdapter); + else + mpt_StopOfdmContTx(pAdapter); + } +} + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_2_platform.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_2_platform.h new file mode 100644 index 000000000000..89f00b7315a5 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_2_platform.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _HALMAC_2_PLATFORM_H_ +#define _HALMAC_2_PLATFORM_H_ + +/*[Driver] always set BUILD_TEST =0*/ +#define BUILD_TEST 0 + +#if BUILD_TEST +#include "../Platform/App/Test/halmac_2_platformapi.h" +#else +/*[Driver] use their own header files*/ +#include <drv_conf.h> /* for basic_types.h and osdep_service.h */ +#include <basic_types.h> /* u8, u16, u32 and etc.*/ +#include <osdep_service.h> /* __BIG_ENDIAN, __LITTLE_ENDIAN, _sema, _mutex */ +#endif + +/*[Driver] provide the define of _TRUE, _FALSE, NULL, u8, u16, u32*/ +#ifndef NULL +#define NULL ((void *)0) +#endif + +#define HALMAC_INLINE inline + +typedef u8 *pu8; +typedef u16 *pu16; +typedef u32 *pu32; +typedef s8 *ps8; +typedef s16 *ps16; +typedef s32 *ps32; + +#define HALMAC_PLATFORM_LITTLE_ENDIAN 1 +#define HALMAC_PLATFORM_BIG_ENDIAN 0 + +/* Note : Named HALMAC_PLATFORM_LITTLE_ENDIAN / HALMAC_PLATFORM_BIG_ENDIAN + * is not mandatory. But Little endian must be '1'. Big endian must be '0' + */ +/*[Driver] config the system endian*/ +#ifdef __LITTLE_ENDIAN +#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_LITTLE_ENDIAN +#else /* !__LITTLE_ENDIAN */ +#define HALMAC_SYSTEM_ENDIAN HALMAC_PLATFORM_BIG_ENDIAN +#endif /* !__LITTLE_ENDIAN */ + +/*[Driver] config if the operating platform*/ +#define HALMAC_PLATFORM_WINDOWS 0 +#define HALMAC_PLATFORM_LINUX 1 +#define HALMAC_PLATFORM_AP 0 + +/*[Driver] config if enable the dbg msg or notl*/ +#define HALMAC_DBG_MSG_ENABLE 1 + +/*[Driver] define the Rx FIFO expanding mode packet size unit for 8821C and 8822B */ +/*Should be 8 Byte alignment*/ +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 /*Bytes*/ + +/*[Driver] provide the type mutex*/ +/* Mutex type */ +typedef _mutex HALMAC_MUTEX; + +#endif /* _HALMAC_2_PLATFORM_H_ */ + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h new file mode 100644 index 000000000000..10f7a96df9e1 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_cfg.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_8821C_CFG_H_ +#define _HALMAC_8821C_CFG_H_ + +#include "halmac_8821c_pwr_seq.h" +#include "halmac_api_8821c.h" +#include "halmac_api_8821c_pcie.h" +#include "../../halmac_reg2.h" +#include "../../halmac_api.h" + +#define HALMAC_TX_FIFO_SIZE_8821C 65536 /* 64k */ +#define HALMAC_TX_FIFO_SIZE_LA_8821C 32768 /* 32k */ +#define HALMAC_RX_FIFO_SIZE_8821C 16384 /* 16k */ +#define HALMAC_TX_PAGE_SIZE_8821C 128 /* PageSize 128Byte */ +#define HALMAC_TX_ALIGN_SIZE_8821C 8 +#define HALMAC_TX_PAGE_SIZE_2_POWER_8821C 7 /* 128 = 2^7 */ +#define HALMAC_SECURITY_CAM_ENTRY_NUM_8821C 64 /* CAM Entry Size */ +#define HALMAC_TX_DESC_SIZE_8821C 48 +#define HALMAC_RX_DESC_SIZE_8821C 24 +#define HALMAC_C2H_PKT_BUF_8821C 256 + +#define HALMAC_RX_FIFO_EXPANDING_UNIT_8821C (HALMAC_RX_DESC_SIZE_8821C + HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE) /* should be 8 Byte alignment*/ +#define HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8821C (HALMAC_RX_DESC_SIZE_8821C + HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX + HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_88XX) /* should be 8 Byte alignment*/ +#define HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C 32768 /* 32k */ +#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C ((((HALMAC_RX_FIFO_EXPANDING_UNIT_8821C << 8) - 1) >> 10) << 10) /* < 48k*/ +#define HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8821C ((((HALMAC_RX_FIFO_EXPANDING_UNIT_MAX_8821C << 8) - 1) >> 10) << 10) /* 45k < 48k*/ + +#define HALMAC_EFUSE_SIZE_8821C 512 /* 0x2000 */ +#define HALMAC_EEPROM_SIZE_8821C 0x200 +#define HALMAC_BT_EFUSE_SIZE_8821C 128 + +#define HALMAC_CR_TRX_ENABLE_8821C (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \ + BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \ + BIT_MACTXEN | BIT_MACRXEN) + +#define HALMAC_BLK_DESC_NUM_8821C 0x3 /* Only for USB */ + +/* AMPDU max time (unit : 32us) */ +#define HALMAC_AMPDU_MAX_TIME_8821C 0x70 + +/* Protect mode control */ +#define HALMAC_PROT_RTS_LEN_TH_8821C 0xFF +#define HALMAC_PROT_RTS_TX_TIME_TH_8821C 0x08 +#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8821C 0x10 +#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8821C 0x10 +#define HALMAC_PROT_MAX_AGG_PKT_LIMIT_8821C_SDIO 0x2B +#define HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8821C_SDIO 0x2B + +/* Fast EDCA setting */ +#define HALMAC_FAST_EDCA_VO_TH_8821C 0x06 +#define HALMAC_FAST_EDCA_VI_TH_8821C 0x06 +#define HALMAC_FAST_EDCA_BE_TH_8821C 0x06 +#define HALMAC_FAST_EDCA_BK_TH_8821C 0x06 + +/* BAR setting */ +#define HALMAC_BAR_RETRY_LIMIT_8821C 0x01 +#define HALMAC_RA_TRY_RATE_AGG_LIMIT_8821C 0x08 + +typedef enum _HALMAC_NORMAL_RXAGG_TH_TO_8821C { + HALMAC_NORMAL_RXAGG_THRESHOLD_8821C = 0xFF, + HALMAC_NORMAL_RXAGG_TIMEOUT_8821C = 0x01, +} HALMAC_NORMAL_RXAGG_TH_TO_8821C; + +typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO_8821C { + HALMAC_LOOPBACK_RXAGG_THRESHOLD_8821C = 0xFF, + HALMAC_LOOPBACK_RXAGG_TIMEOUT_8821C = 0x01, +} HALMAC_LOOPBACK_RXAGG_TH_TO_8821C; + +#define HALMAC_RSVD_DRV_PGNUM_8821C 16 /*2048*/ +#define HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C 32 /*4096*/ +#define HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C 8 /*1024*/ +#define HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C 0 /*0*/ +#define HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C 4 /*512*/ + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c new file mode 100644 index 000000000000..87f0240f5d60 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_phy.c @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "../halmac_88xx_cfg.h" +#include "halmac_8821c_cfg.h" + +/** + * ============ip sel item list============ + * HALMAC_IP_SEL_INTF_PHY + * USB2 : usb2 phy, 1byte value + * USB3 : usb3 phy, 2byte value + * PCIE1 : pcie gen1 mdio, 2byte value + * PCIE2 : pcie gen2 mdio, 2byte value + * HALMAC_IP_SEL_MAC + * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value + * HALMAC_IP_SEL_PCIE_DBI + * USB2 USB3 : none + * PCIE1, PCIE2 : pcie dbi, 1byte value + */ + +HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_USB2_PHY[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_USB3_PHY[] = { + /* {offset, value, cut mask, platform mask} */ + {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN1[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; + +HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN2[] = { + /* {offset, value, ip sel, cut mask, platform mask} */ + {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, HALMAC_INTF_PHY_PLATFORM_ALL}, +}; diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c new file mode 100644 index 000000000000..1b90a0ba8938 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.c @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "../halmac_88xx_cfg.h" +#include "halmac_8821c_cfg.h" + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_ACT[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ + {0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1, HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/ + {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/ + {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* Disable USB suspend */ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /* wait till 0x04[17] = 1 power ready*/ + {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* Enable USB suspend */ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0 }, /* disable HWPDN 0x04[15]=0*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, /* disable WL suspend*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* polling until return 0*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(0), 0}, + {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Enable XTAL_CLK*/ + {0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x74[5]=1 , PCIE WAKE# enabled*/ + {0x0022, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*0x22[1]=0 , turn off usb bandgap*/ + {0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), (BIT(7) | BIT(6) | BIT(5))}, /*PCIE , GPIO15/14/13 set to output mode*/ + {0x0061, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, /*PCIE , GPIO15/14/13 set to output value 0*/ + {0x007C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /*SWR freq�אּ2.4MHz*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_ACT_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ + {0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Enable rising edge triggering interrupt*/ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* release WLON reset 0x04[16]=1*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* Whole BB is reset */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ + {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), 0}, /* XTAL_CLK gated*/ + {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_SUS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/ + {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_SUS_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_CARDDIS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* SOP option to disable BG/MB*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0}, /*BIT_PAPE_WLBT_SEL*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, /*enable WL suspend*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*enable SW LPS*/ + {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*disable GPIO9 as EXT WAKEUP*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), 0 }, /* 0: BT PAPE control ; 1: WL BB LNAON control*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0 }, /* 0: BT GPIO[11:10] control ; 1: WL BB LNAON control*/ + {0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0 }, /* 0: BT Control*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0 }, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */ + {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6) }, /* GPIO[6] : Output mode*/ + {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0 }, /* turn off BT_GPIO[16] */ + {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7) }, /* GPIO[7] : Output mode*/ + {0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4) }, /* GPIO[12] : Output mode */ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*disable 32k clock*/ + {0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*disable 32k clock by indirect access*/ + {0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x90}, /*disable 32k clock by indirect access*/ + {0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x00}, /*disable 32k clock by indirect access*/ + {0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, 0xFF, 0x04}, /*disable 32k clock by indirect access*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDDIS_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/ + {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_POLLING, BIT(1), BIT(1)}, /*wait power state to suspend*/ + {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, /*clear suspend enable and power down enable*/ + {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, /*PCIe DMA start*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_CARDEMU_TO_PDN[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK | HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ + {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0x04[16] = 0*/ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* 0x04[15] = 1*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_PDN_TO_CARDEMU[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_ACT_TO_LPS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/ + {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/ + {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/ + {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/ + {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/ + {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x42}, /* LPS Option MAC OFF enable*/ + {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/ + {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/ + {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/ + {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/ + {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/ + {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/ + {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/ + {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=0 TSF in 40M*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_ACT_TO_DEEP_LPS[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/ + {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3), BIT(3)}, /*Register write data of 32K calibration*/ + {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/ + {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/ + {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable 32K CLK*/ + {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x40}, /* LPS Option MAC OFF enable*/ + {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x20}, /* LPS Option Enable memory to deep sleep mode*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, /* enable reg use 32K CLK*/ + {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*PCIe DMA stop*/ + {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*Tx Pause*/ + {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, 0xFF, 0}, /*Should be zero if no packet is transmitting*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*Whole BB is reset*/ + {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x3F}, /*Reset MAC TRX*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /*check if removed later*/ + {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/ + {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* switch TSF clock to 32K*/ + {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), BIT(7)}, /*Polling 0x109[7]=1 TSF in 32K*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0), BIT(0)}, /* enable WL_LPS_EN*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +HALMAC_WLAN_PWR_CFG HALMAC_RTL8821C_TRANS_LPS_TO_ACT[] = { + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */ + {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/ + {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO, HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/ + {0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/ + {0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/ + {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(4), 0}, /*switch TSF to 40M*/ + {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0 TSF in 40M*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), BIT(1)}, + {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF }, /*enable WMAC TRX*/ + {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*enable BB macro*/ + {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0}, + {0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0x03}, /*clear RPWM INT*/ + {0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF, 0xFF}, /*clear FW INT*/ + {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1), 0}, /* disable reg use 32K CLK*/ + {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*disable 32k calibration and thermal meter*/ + {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK, HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0}, +}; + +/* Card Enable Array */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_card_enable_flow[] = { + HALMAC_RTL8821C_TRANS_CARDDIS_TO_CARDEMU, + HALMAC_RTL8821C_TRANS_CARDEMU_TO_ACT, + NULL +}; + +/* Card Disable Array */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_card_disable_flow[] = { + HALMAC_RTL8821C_TRANS_ACT_TO_CARDEMU, + HALMAC_RTL8821C_TRANS_CARDEMU_TO_CARDDIS, + NULL +}; + +/* Suspend Array */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_suspend_flow[] = { + HALMAC_RTL8821C_TRANS_ACT_TO_CARDEMU, + HALMAC_RTL8821C_TRANS_CARDEMU_TO_SUS, + NULL +}; + +/* Resume Array */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_resume_flow[] = { + HALMAC_RTL8821C_TRANS_SUS_TO_CARDEMU, + HALMAC_RTL8821C_TRANS_CARDEMU_TO_ACT, + NULL +}; + +/* HWPDN Array - HW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_hwpdn_flow[] = { + NULL +}; + +/* Enter LPS - FW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_lps_flow[] = { + HALMAC_RTL8821C_TRANS_ACT_TO_LPS, + NULL +}; + +/* Enter Deep LPS - FW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_deep_lps_flow[] = { + HALMAC_RTL8821C_TRANS_ACT_TO_DEEP_LPS, + NULL +}; + +/* Leave LPS -FW behavior */ +PHALMAC_WLAN_PWR_CFG halmac_8821c_leave_lps_flow[] = { + HALMAC_RTL8821C_TRANS_LPS_TO_ACT, + NULL +}; + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h new file mode 100644 index 000000000000..02f75ad64e3d --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_8821c_pwr_seq.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef HALMAC_POWER_SEQUENCE_8821C +#define HALMAC_POWER_SEQUENCE_8821C + +#include "../../halmac_pwr_seq_cmd.h" + +#define HALMAC_8821C_PWR_SEQ_VER "V13" +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_card_disable_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_card_enable_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_suspend_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_resume_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_hwpdn_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_lps_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_enter_deep_lps_flow[]; +extern PHALMAC_WLAN_PWR_CFG halmac_8821c_leave_lps_flow[]; + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c new file mode 100644 index 000000000000..6c9d43503539 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.c @@ -0,0 +1,269 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "halmac_8821c_cfg.h" +#include "halmac_func_8821c.h" +#include "../halmac_func_88xx.h" + +/** + * halmac_mount_api_8821c() - attach functions to function pointer + * @pHalmac_adapter + * + * SD1 internal use + * + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + */ +HALMAC_RET_STATUS +halmac_mount_api_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8821C; + pHalmac_adapter->hw_config_info.efuse_size = HALMAC_EFUSE_SIZE_8821C; + pHalmac_adapter->hw_config_info.eeprom_size = HALMAC_EEPROM_SIZE_8821C; + pHalmac_adapter->hw_config_info.bt_efuse_size = HALMAC_BT_EFUSE_SIZE_8821C; + pHalmac_adapter->hw_config_info.cam_entry_num = HALMAC_SECURITY_CAM_ENTRY_NUM_8821C; + pHalmac_adapter->hw_config_info.txdesc_size = HALMAC_TX_DESC_SIZE_8821C; + pHalmac_adapter->hw_config_info.rxdesc_size = HALMAC_RX_DESC_SIZE_8821C; + pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_8821C; + pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_8821C; + pHalmac_adapter->hw_config_info.page_size = HALMAC_TX_PAGE_SIZE_8821C; + pHalmac_adapter->hw_config_info.tx_align_size = HALMAC_TX_ALIGN_SIZE_8821C; + pHalmac_adapter->hw_config_info.page_size_2_power = HALMAC_TX_PAGE_SIZE_2_POWER_8821C; + + pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = HALMAC_RSVD_DRV_PGNUM_8821C; + + pHalmac_api->halmac_init_trx_cfg = halmac_init_trx_cfg_8821C; + pHalmac_api->halmac_init_protocol_cfg = halmac_init_protocol_cfg_8821c; + pHalmac_api->halmac_init_h2c = halmac_init_h2c_8821c; + + if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) { + pHalmac_api->halmac_mac_power_switch = halmac_mac_power_switch_8821c_pcie; + pHalmac_api->halmac_cfg_tx_agg_align = halmac_cfg_tx_agg_align_pcie_not_support_88xx; + pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8821c; + pHalmac_api->halmac_phy_cfg = halmac_phy_cfg_8821c_pcie; + pHalmac_api->halmac_interface_integration_tuning = halmac_interface_integration_tuning_8821c_pcie; + } else { + pHalmac_api->halmac_pcie_switch = halmac_pcie_switch_8821c_nc; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_trx_cfg_8821c() - config trx dma register + * @pHalmac_adapter : the adapter of halmac + * @halmac_trx_mode : trx mode selection + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_trx_cfg_8821C( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode +) +{ + u8 value8; + u32 value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_TRX_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + pHalmac_adapter->trx_mode = halmac_trx_mode; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg ==========>halmac_trx_mode = %d\n", halmac_trx_mode); + + status = halmac_txdma_queue_mapping_8821c(pHalmac_adapter, halmac_trx_mode); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n"); + return status; + } + + value8 = 0; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); + value8 = HALMAC_CR_TRX_ENABLE_8821C; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); + + status = halmac_priority_queue_config_8821c(pHalmac_adapter, halmac_trx_mode); + if (HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE != pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX >> 3); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_txdma_queue_mapping fail!\n"); + return status; + } + + /* Config H2C packet buffer */ + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD); + /* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */ + /* value32 = (value32 & 0xFFFC0000) | pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy * HALMAC_TX_PAGE_SIZE_8821C; */ + value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR); + /* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */ + value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL); + /* value32 = (value32 & 0xFFFC0000) | (HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C + HALMAC_RSVD_H2C_QUEUE_SIZE_8821C); */ + value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); + value8 = (u8)((value8 & 0xFC) | 0x01); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); + value8 = (u8)((value8 & 0xFB) | 0x04); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1); + value8 = (u8)((value8 & 0x7f) | 0x80); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8); + + pHalmac_adapter->h2c_buff_size = HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C; + halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter); + + if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n"); + return HALMAC_RET_GET_H2C_SPACE_ERR; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_trx_cfg <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_protocol_cfg_8821c() - config protocol register + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_protocol_cfg_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u32 max_agg_num, max_rts_agg_num; + u32 value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8821c ==========>\n"); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AMPDU_MAX_TIME_V1, HALMAC_AMPDU_MAX_TIME_8821C); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); + + max_agg_num = HALMAC_PROT_MAX_AGG_PKT_LIMIT_8821C; + max_rts_agg_num = HALMAC_PROT_RTS_MAX_AGG_PKT_LIMIT_8821C; + + value32 = HALMAC_PROT_RTS_LEN_TH_8821C | (HALMAC_PROT_RTS_TX_TIME_TH_8821C << 8) | (max_agg_num << 16) | (max_rts_agg_num << 24); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PROT_MODE_CTRL, value32); + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BAR_MODE_CTRL + 2, HALMAC_BAR_RETRY_LIMIT_8821C | HALMAC_RA_TRY_RATE_AGG_LIMIT_8821C << 8); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING, HALMAC_FAST_EDCA_VO_TH_8821C); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_VOVI_SETTING + 2, HALMAC_FAST_EDCA_VI_TH_8821C); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING, HALMAC_FAST_EDCA_BE_TH_8821C); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FAST_EDCA_BEBK_SETTING + 2, HALMAC_FAST_EDCA_BK_TH_8821C); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_init_protocol_cfg_8821c <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_h2c_8821c() - config h2c packet buffer + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_h2c_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 value8; + u32 value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + value8 = 0; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); + value8 = HALMAC_CR_TRX_ENABLE_8821C; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_HEAD); + /* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */ + value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_HEAD, value32); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_READ_ADDR); + /* value32 = (value32 & 0xFFFC0000) | HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C; */ + value32 = (value32 & 0xFFFC0000) | (pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_READ_ADDR, value32); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_TAIL); + /* value32 = (value32 & 0xFFFC0000) | (HALMAC_RSVD_H2C_QUEUE_BOUNDARY_8821C + HALMAC_RSVD_H2C_QUEUE_SIZE_8821C); */ + value32 = (value32 & 0xFFFC0000) | ((pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_8821C) + (HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2C_TAIL, value32); + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); + value8 = (u8)((value8 & 0xFC) | 0x01); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_H2C_INFO); + value8 = (u8)((value8 & 0xFB) | 0x04); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_H2C_INFO, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1); + value8 = (u8)((value8 & 0x7f) | 0x80); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, value8); + + pHalmac_adapter->h2c_buff_size = (HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C << HALMAC_TX_PAGE_SIZE_2_POWER_8821C); + halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter); + + if (pHalmac_adapter->h2c_buff_size != pHalmac_adapter->h2c_buf_free_space) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "get h2c free space error!\n"); + return HALMAC_RET_GET_H2C_SPACE_ERR; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "h2c free space : %d\n", pHalmac_adapter->h2c_buf_free_space); + + return HALMAC_RET_SUCCESS; +} diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h new file mode 100644 index 000000000000..dab3d949240f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_API_8821C_H_ +#define _HALMAC_API_8821C_H_ + +#include "../../halmac_2_platform.h" +#include "../../halmac_type.h" + +HALMAC_RET_STATUS +halmac_mount_api_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_init_trx_cfg_8821C( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode +); + +HALMAC_RET_STATUS +halmac_init_protocol_cfg_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_init_h2c_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +#endif/* _HALMAC_API_8821C_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c new file mode 100644 index 000000000000..2fe2a8626b2c --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.c @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "../halmac_88xx_cfg.h" +#include "halmac_8821c_cfg.h" + +#define CLKCAL_CTRL_PHYPARA 0x00 +#define CLKCAL_SET_PHYPARA 0x20 +#define CLKCAL_TRG_VAL_PHYPARA 0x21 + +static HALMAC_RET_STATUS +halmac_auto_refclk_cal_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +/** + * halmac_mac_power_switch_8821c_pcie() - switch mac power + * @pHalmac_adapter : the adapter of halmac + * @halmac_power : power state + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_mac_power_switch_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_MAC_POWER halmac_power +) +{ + u8 interface_mask; + u8 value8; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MAC_POWER_SWITCH); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_pcie halmac_power = %x ==========>\n", halmac_power); + interface_mask = HALMAC_PWR_INTF_PCI_MSK; + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); + if (0xEA == value8) + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + else + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; + + /* Check if power switch is needed */ + if (halmac_power == HALMAC_MAC_POWER_ON && pHalmac_adapter->halmac_state.mac_power == HALMAC_MAC_POWER_ON) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "halmac_mac_power_switch power state unchange!\n"); + return HALMAC_RET_PWR_UNCHANGE; + } else { + if (HALMAC_MAC_POWER_OFF == halmac_power) { + if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8821c_card_disable_flow)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power off cmd error\n"); + return HALMAC_RET_POWER_OFF_FAIL; + } + + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_OFF; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_UNDEFINE; + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); + } else { + if (HALMAC_RET_SUCCESS != halmac_pwr_seq_parser_88xx(pHalmac_adapter, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_TSMC_MSK, + interface_mask, halmac_8821c_card_enable_flow)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "Handle power on cmd error\n"); + return HALMAC_RET_POWER_ON_FAIL; + } + + pHalmac_adapter->halmac_state.mac_power = HALMAC_MAC_POWER_ON; + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; + } + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_mac_power_switch_88xx_pcie <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pcie_switch_8821c() - pcie gen1/gen2 switch + * @pHalmac_adapter : the adapter of halmac + * @pcie_cfg : gen1/gen2 selection + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pcie_switch_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PCIE_SWITCH); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_pcie_switch_8821c_nc( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PCIE_SWITCH); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c_nc ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_pcie_switch_8821c_nc <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_phy_cfg_8821c_pcie() - phy config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_phy_cfg_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PHY_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg ==========>\n"); + + status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8821C_PCIE_PHY_GEN1, platform, HAL_INTF_PHY_PCIE_GEN1); + + if (HALMAC_RET_SUCCESS != status) + return status; + + status = halmac_parse_intf_phy_88xx(pHalmac_adapter, HALMAC_RTL8821C_PCIE_PHY_GEN2, platform, HAL_INTF_PHY_PCIE_GEN2); + + if (HALMAC_RET_SUCCESS != status) + return status; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_phy_cfg <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_interface_integration_tuning_8821c_pcie() - pcie interface fine tuning + * @pHalmac_adapter : the adapter of halmac + * Author : Rick Liu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + HALMAC_RET_STATUS status; + + status = halmac_auto_refclk_cal_8821c_pcie(pHalmac_adapter); + + return status; +} + +static HALMAC_RET_STATUS +halmac_auto_refclk_cal_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u16 read_tmp; + u16 cal_target; + u16 margin; + HALMAC_RET_STATUS status; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + /* Set reference clock div number at 0x00[7:6] */ + read_tmp = halmac_mdio_read_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, HAL_INTF_PHY_PCIE_GEN1); + /* status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp & ~(BIT(6) | BIT(7)), HAL_INTF_PHY_PCIE_GEN1); */ + /* status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp & ~(BIT(6)) | BIT(7), HAL_INTF_PHY_PCIE_GEN1); */ + status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp | BIT(7) | BIT(6), HAL_INTF_PHY_PCIE_GEN1); + if (HALMAC_RET_SUCCESS != status) + return status; + + /* Set 0x00[11] to count 1T of reference clock and read target value at 0x21[11:0] */ + read_tmp = halmac_mdio_read_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, HAL_INTF_PHY_PCIE_GEN1); + status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp | BIT(11), HAL_INTF_PHY_PCIE_GEN1); + if (HALMAC_RET_SUCCESS != status) + return status; + PLATFORM_RTL_DELAY_US(pDriver_adapter, 22); + cal_target = halmac_mdio_read_88xx(pHalmac_adapter, CLKCAL_TRG_VAL_PHYPARA, HAL_INTF_PHY_PCIE_GEN1); + + /* Set calibration target at 0x20[11:0] and margin at 0x20[15:12] */ + margin = 0x0003; + status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_SET_PHYPARA, (cal_target & 0x0FFF) | (margin << 12), HAL_INTF_PHY_PCIE_GEN1); + if (HALMAC_RET_SUCCESS != status) + return status; + + /* Turn on calibration mechanium at 0x00[9] */ + status = halmac_mdio_write_88xx(pHalmac_adapter, CLKCAL_CTRL_PHYPARA, read_tmp | BIT(9), HAL_INTF_PHY_PCIE_GEN1); + + return HALMAC_RET_SUCCESS; +} diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h new file mode 100644 index 000000000000..33baea0e2cbd --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_api_8821c_pcie.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_API_8821C_PCIE_H_ +#define _HALMAC_API_8821C_PCIE_H_ + +#include "../../halmac_2_platform.h" +#include "../../halmac_type.h" + +extern HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN1[]; +extern HALMAC_INTF_PHY_PARA HALMAC_RTL8821C_PCIE_PHY_GEN2[]; + +HALMAC_RET_STATUS +halmac_mac_power_switch_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_MAC_POWER halmac_power +); + +HALMAC_RET_STATUS +halmac_pcie_switch_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +); + +HALMAC_RET_STATUS +halmac_pcie_switch_8821c_nc( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PCIE_CFG pcie_cfg +); + +HALMAC_RET_STATUS +halmac_phy_cfg_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_INTF_PHY_PLATFORM platform +); + +HALMAC_RET_STATUS +halmac_interface_integration_tuning_8821c_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +#endif/* _HALMAC_API_8821C_PCIE_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c new file mode 100644 index 000000000000..3c7d2bb5d9c0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.c @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "halmac_8821c_cfg.h" + +#if HALMAC_PLATFORM_WINDOWS +/*SDIO RQPN Mapping for Windows, extra queue is not implemented in Driver code*/ +HALMAC_RQPN HALMAC_RQPN_SDIO_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; +#else +/*SDIO RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_SDIO_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; +#endif + +/*PCIE RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_PCIE_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; + +/*USB 2 Bulkout RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_2BULKOUT_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 3 Bulkout RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_3BULKOUT_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_HQ, HALMAC_MAP2_HQ}, +}; + +/*USB 4 Bulkout RQPN Mapping*/ +HALMAC_RQPN HALMAC_RQPN_4BULKOUT_8821C[] = { + /* { mode, vo_map, vi_map, be_map, bk_map, mg_map, hi_map } */ + {HALMAC_TRX_MODE_NORMAL, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_TRXSHARE, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_WMM, HALMAC_MAP2_HQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_NQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_P2P, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, HALMAC_MAP2_NQ, HALMAC_MAP2_NQ, HALMAC_MAP2_LQ, HALMAC_MAP2_LQ, HALMAC_MAP2_EXQ, HALMAC_MAP2_HQ}, +}; +#if HALMAC_PLATFORM_WINDOWS +/*SDIO Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 0, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 256}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 256}, +}; +#else +/*SDIO Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_SDIO_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 8, 8, 8, 8, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 256}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 256}, +}; +#endif + +/*PCIE Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_PCIE_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 256}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 256}, +}; + +/*USB 2 Bulkout Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_2BULKOUT_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 0, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 0, 0, 256}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 0, 0, 256}, +}; + +/*USB 3 Bulkout Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_3BULKOUT_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 0, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 0, 256}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 0, 256}, +}; + +/*USB 4 Bulkout Page Number*/ +HALMAC_PG_NUM HALMAC_PG_NUM_4BULKOUT_8821C[] = { + /* { mode, hq_num, nq_num, lq_num, exq_num, gap_num} */ + {HALMAC_TRX_MODE_NORMAL, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_TRXSHARE, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_WMM, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_P2P, 16, 16, 16, 14, 1}, + {HALMAC_TRX_MODE_LOOPBACK, 16, 16, 16, 14, 256}, + {HALMAC_TRX_MODE_DELAY_LOOPBACK, 16, 16, 16, 14, 256}, +}; + +HALMAC_RET_STATUS +halmac_txdma_queue_mapping_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode +) +{ + u16 value16; + VOID *pDriver_adapter = NULL; + PHALMAC_RQPN pCurr_rqpn_Sel = NULL; + HALMAC_RET_STATUS status; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { + pCurr_rqpn_Sel = HALMAC_RQPN_SDIO_8821C; + } else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) { + pCurr_rqpn_Sel = HALMAC_RQPN_PCIE_8821C; + } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + if (pHalmac_adapter->halmac_bulkout_num == 2) { + pCurr_rqpn_Sel = HALMAC_RQPN_2BULKOUT_8821C; + } else if (pHalmac_adapter->halmac_bulkout_num == 3) { + pCurr_rqpn_Sel = HALMAC_RQPN_3BULKOUT_8821C; + } else if (pHalmac_adapter->halmac_bulkout_num == 4) { + pCurr_rqpn_Sel = HALMAC_RQPN_4BULKOUT_8821C; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "interface not support\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } + + status = halmac_rqpn_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_rqpn_Sel); + if (HALMAC_RET_SUCCESS != status) + return status; + + value16 = 0; + value16 |= BIT_TXDMA_HIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]); + value16 |= BIT_TXDMA_MGQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]); + value16 |= BIT_TXDMA_BKQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]); + value16 |= BIT_TXDMA_BEQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]); + value16 |= BIT_TXDMA_VIQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]); + value16 |= BIT_TXDMA_VOQ_MAP(pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXDMA_PQ_MAP, value16); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_priority_queue_config_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode +) +{ + u8 transfer_mode = 0; + u8 value8; + u32 counter; + HALMAC_RET_STATUS status; + PHALMAC_PG_NUM pCurr_pg_num = NULL; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (HALMAC_LA_MODE_DISABLE == pHalmac_adapter->txff_allocation.la_mode) { + if (HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE == pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode) { + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C; + } else if (HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK == pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode) { + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C; + pHalmac_adapter->hw_config_info.tx_fifo_size = HALMAC_TX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C; + if (HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C <= HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8821C) + pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_8821C; + else + pHalmac_adapter->hw_config_info.rx_fifo_size = HALMAC_RX_FIFO_SIZE_RX_FIFO_EXPANDING_1_BLOCK_MAX_8821C; + } else { + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "rx_fifo_expanding_mode = %d not support\n", pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode); + } + } else { + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = HALMAC_TX_FIFO_SIZE_LA_8821C >> HALMAC_TX_PAGE_SIZE_2_POWER_8821C; + } + pHalmac_adapter->txff_allocation.rsvd_pg_num = (pHalmac_adapter->txff_allocation.rsvd_drv_pg_num + + HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C + + HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C + + HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C + + HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C); + if (pHalmac_adapter->txff_allocation.rsvd_pg_num > pHalmac_adapter->txff_allocation.tx_fifo_pg_num) + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + + pHalmac_adapter->txff_allocation.ac_q_pg_num = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num; + pHalmac_adapter->txff_allocation.rsvd_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - pHalmac_adapter->txff_allocation.rsvd_pg_num; + pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = pHalmac_adapter->txff_allocation.tx_fifo_pg_num - HALMAC_RSVD_FW_TXBUFF_PGNUM_8821C; + pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - HALMAC_RSVD_CPU_INSTRUCTION_PGNUM_8821C; + pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy - HALMAC_RSVD_H2C_QUEUE_PGNUM_8821C; + pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy - HALMAC_RSVD_H2C_EXTRAINFO_PGNUM_8821C; + pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_drv_pg_num; + + if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { + pCurr_pg_num = HALMAC_PG_NUM_SDIO_8821C; + } else if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) { + pCurr_pg_num = HALMAC_PG_NUM_PCIE_8821C; + } else if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + if (pHalmac_adapter->halmac_bulkout_num == 2) { + pCurr_pg_num = HALMAC_PG_NUM_2BULKOUT_8821C; + } else if (pHalmac_adapter->halmac_bulkout_num == 3) { + pCurr_pg_num = HALMAC_PG_NUM_3BULKOUT_8821C; + } else if (pHalmac_adapter->halmac_bulkout_num == 4) { + pCurr_pg_num = HALMAC_PG_NUM_4BULKOUT_8821C; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "interface not support\n"); + return HALMAC_RET_NOT_SUPPORT; + } + } + + status = halmac_pg_num_parser_88xx(pHalmac_adapter, halmac_trx_mode, pCurr_pg_num); + if (HALMAC_RET_SUCCESS != status) + return status; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Set FIFO page\n"); + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, pHalmac_adapter->txff_allocation.high_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_2, pHalmac_adapter->txff_allocation.low_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_3, pHalmac_adapter->txff_allocation.normal_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_4, pHalmac_adapter->txff_allocation.extra_queue_pg_num); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_5, pHalmac_adapter->txff_allocation.pub_queue_pg_num); + + pHalmac_adapter->sdio_free_space.high_queue_number = pHalmac_adapter->txff_allocation.high_queue_pg_num; + pHalmac_adapter->sdio_free_space.normal_queue_number = pHalmac_adapter->txff_allocation.normal_queue_pg_num; + pHalmac_adapter->sdio_free_space.low_queue_number = pHalmac_adapter->txff_allocation.low_queue_pg_num; + pHalmac_adapter->sdio_free_space.public_queue_number = pHalmac_adapter->txff_allocation.pub_queue_pg_num; + pHalmac_adapter->sdio_free_space.extra_queue_number = pHalmac_adapter->txff_allocation.extra_queue_pg_num; + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31)); + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BCNQ1_BDNY_V1, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCNQ_PGBNDY_V1)); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFF_BNDY, pHalmac_adapter->hw_config_info.rx_fifo_size - HALMAC_C2H_PKT_BUF_8821C - 1); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Init LLT table\n"); + + if (HALMAC_INTERFACE_USB == pHalmac_adapter->halmac_interface) { + value8 = (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & ~(BIT_MASK_BLK_DESC_NUM << BIT_SHIFT_BLK_DESC_NUM)); + value8 = (u8)(value8 | (HALMAC_BLK_DESC_NUM_8821C << BIT_SHIFT_BLK_DESC_NUM)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, value8); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1 + 3, HALMAC_BLK_DESC_NUM_8821C); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1, HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_OFFSET_CHK + 1) | BIT(1)); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_AUTO_LLT_V1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) | BIT_AUTO_INIT_LLT_V1)); + counter = 1000; + while (HALMAC_REG_READ_8(pHalmac_adapter, REG_AUTO_LLT_V1) & BIT_AUTO_INIT_LLT_V1) { + counter--; + if (counter == 0) + return HALMAC_RET_INIT_LLT_FAIL; + } + + if (HALMAC_TRX_MODE_DELAY_LOOPBACK == halmac_trx_mode) { + transfer_mode = HALMAC_TRNSFER_LOOPBACK_DELAY; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_WMAC_LBK_BUF_HD_V1, (u16)pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + } else if (HALMAC_TRX_MODE_LOOPBACK == halmac_trx_mode) + transfer_mode = HALMAC_TRNSFER_LOOPBACK_DIRECT; + else + transfer_mode = HALMAC_TRNSFER_NORMAL; + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 3, (u8)transfer_mode); + + return HALMAC_RET_SUCCESS; +} diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h new file mode 100644 index 000000000000..f5036457b99a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_8821c/halmac_func_8821c.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_FUNC_8821C_H_ +#define _HALMAC_FUNC_8821C_H_ + +#include "../../halmac_type.h" + +HALMAC_RET_STATUS +halmac_txdma_queue_mapping_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode +); + +HALMAC_RET_STATUS +halmac_priority_queue_config_8821c( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode +); + +#endif /* _HALMAC_FUNC_8821C_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h new file mode 100644 index 000000000000..369e0366a0a2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_88xx_cfg.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_88XX_CFG_H_ +#define _HALMAC_88XX_CFG_H_ + +#include "../halmac_2_platform.h" +#include "../halmac_type.h" +#include "../halmac_api.h" +#include "../halmac_reg2.h" +#include "../halmac_pwr_seq_cmd.h" +#include "halmac_func_88xx.h" +#include "halmac_api_88xx.h" +#include "halmac_api_88xx_pcie.h" + +#define HALMAC_SVN_VER_88XX "13359M" + +#define HALMAC_MAJOR_VER_88XX 0x0001 /* major version, ver_1 for async_api */ +#define HALMAC_PROTOTYPE_VER_88XX 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ +#define HALMAC_MINOR_VER_88XX 0x0006 /* else increment minor version */ +#define HALMAC_PATCH_VER_88XX 0x0002 /* patch version */ + +#define HALMAC_C2H_DATA_OFFSET_88XX 10 +#define HALMAC_RX_AGG_ALIGNMENT_SIZE_88XX 8 +#define HALMAC_TX_AGG_ALIGNMENT_SIZE_88XX 8 +#define HALMAC_TX_AGG_BUFF_SIZE_88XX 32768 +#define HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX 80 /*8*10 Bytes*/ +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE_MAX_88XX 80 /* should be 8 Byte alignment*/ + +#define HALMAC_TX_PAGE_SIZE_88XX 128 /* PageSize 128Byte */ +#define HALMAC_TX_PAGE_SIZE_2_POWER_88XX 7 /* 128 = 2^7 */ + +#define HALMAC_EXTRA_INFO_BUFF_SIZE_88XX 4096 /*4K*/ +#define HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX 16384 /*16K*/ +#define HALMAC_FW_OFFLOAD_CMD_SIZE_88XX 12 /*Fw config parameter cmd size, each 12 byte*/ + +#define HALMAC_H2C_CMD_ORIGINAL_SIZE_88XX 8 +#define HALMAC_H2C_CMD_SIZE_UNIT_88XX 32 /* Only support 32 byte packet now */ + +#define HALMAC_NLO_INFO_SIZE_88XX 1024 + +/* Download FW */ +#define HALMAC_FW_SIZE_MAX_88XX 0x40000 +#define HALMAC_FWHDR_SIZE_88XX 64 +#define HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX 8 +#define HALMAC_FW_MAX_DL_SIZE_88XX 0x2000 /* need power of 2 */ +/* Max dlfw size can not over 31K, because SDIO HW restriction */ +#define HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX 0x7C00 + +#define DLFW_RESTORE_REG_NUM_88XX 9 +#define ID_INFORM_DLEMEM_RDY 0x80 + +/* FW header information */ +#define HALMAC_FWHDR_OFFSET_VERSION_88XX 4 +#define HALMAC_FWHDR_OFFSET_SUBVERSION_88XX 6 +#define HALMAC_FWHDR_OFFSET_SUBINDEX_88XX 7 +#define HALMAC_FWHDR_OFFSET_MONTH_88XX 16 +#define HALMAC_FWHDR_OFFSET_DATE_88XX 17 +#define HALMAC_FWHDR_OFFSET_HOUR_88XX 18 +#define HALMAC_FWHDR_OFFSET_MIN_88XX 19 +#define HALMAC_FWHDR_OFFSET_YEAR_88XX 20 +#define HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX 24 +#define HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX 28 +#define HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX 32 +#define HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX 36 +#define HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX 48 +#define HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX 52 +#define HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX 56 +#define HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX 60 + +/* HW memory address */ +#define HALMAC_OCPBASE_TXBUF_88XX 0x18780000 +#define HALMAC_OCPBASE_DMEM_88XX 0x00200000 +#define HALMAC_OCPBASE_IMEM_88XX 0x00000000 + +/* define the SDIO Bus CLK threshold, for avoiding CMD53 fails that result from SDIO CLK sync to ana_clk fail */ +#define HALMAC_SDIO_CLK_THRESHOLD_88XX 150 /* 150MHz */ +#define HALMAC_SDIO_CLOCK_SPEED_MAX_88XX 208 /* 208MHz */ + +/* MAC clock */ +#define HALMAC_MAC_CLOCK_88XX 80 /* 80M */ + +/* H2C/C2H*/ +#define HALMAC_H2C_CMD_SIZE_88XX 32 +#define HALMAC_H2C_CMD_HDR_SIZE_88XX 8 + +#define HALMAC_PROTECTED_EFUSE_SIZE_88XX 0x60 + +/* Function enable */ +#define HALMAC_FUNCTION_ENABLE_88XX 0xDC + +/* FIFO size & packet size */ +/* #define HALMAC_WOWLAN_PATTERN_SIZE 256 */ + +/* CFEND rate */ +#define HALMAC_BASIC_CFEND_RATE_88XX 0x5 +#define HALMAC_STBC_CFEND_RATE_88XX 0xF + +/* Response rate */ +#define HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX 0xFFFFF +#define HALMAC_RESPONSE_RATE_88XX HALMAC_RESPONSE_RATE_BITMAP_ALL_88XX + +/* Spec SIFS */ +#define HALMAC_SIFS_CCK_PTCL_88XX 16 +#define HALMAC_SIFS_OFDM_PTCL_88XX 16 + +/* Retry limit */ +#define HALMAC_LONG_RETRY_LIMIT_88XX 8 +#define HALMAC_SHORT_RETRY_LIMIT_88XX 7 + +/* Slot, SIFS, PIFS time */ +#define HALMAC_SLOT_TIME_88XX 0x05 +#define HALMAC_PIFS_TIME_88XX 0x19 +#define HALMAC_SIFS_CCK_CTX_88XX 0xA +#define HALMAC_SIFS_OFDM_CTX_88XX 0xA +#define HALMAC_SIFS_CCK_TRX_88XX 0x10 +#define HALMAC_SIFS_OFDM_TRX_88XX 0x10 + +/* TXOP limit */ +#define HALMAC_VO_TXOP_LIMIT_88XX 0x186 +#define HALMAC_VI_TXOP_LIMIT_88XX 0x3BC + +/* NAV */ +#define HALMAC_RDG_NAV_88XX 0x05 +#define HALMAC_TXOP_NAV_88XX 0x1B + +/* TSF */ +#define HALMAC_CCK_RX_TSF_88XX 0x30 +#define HALMAC_OFDM_RX_TSF_88XX 0x30 + +/* Send beacon related */ +#define HALMAC_TBTT_PROHIBIT_88XX 0x04 +#define HALMAC_TBTT_HOLD_TIME_88XX 0x064 +#define HALMAC_DRIVER_EARLY_INT_88XX 0x04 +#define HALMAC_BEACON_DMA_TIM_88XX 0x02 + +/* RX filter */ +#define HALMAC_RX_FILTER0_RECIVE_ALL_88XX 0xFFFFFFF +#define HALMAC_RX_FILTER0_88XX HALMAC_RX_FILTER0_RECIVE_ALL_88XX +#define HALMAC_RX_FILTER_RECIVE_ALL_88XX 0xFFFF +#define HALMAC_RX_FILTER_88XX HALMAC_RX_FILTER_RECIVE_ALL_88XX + +/* RCR */ +#define HALMAC_RCR_CONFIG_88XX 0xE400631E + +/* Security config */ +#define HALMAC_SECURITY_CONFIG_88XX 0x01CC + +/* CCK rate ACK timeout */ +#define HALMAC_ACK_TO_CCK_88XX 0x40 + +/* RX pkt max size */ +#define HALMAC_RXPKT_MAX_SIZE 12288 /* 12K */ +#define HALMAC_RXPKT_MAX_SIZE_BASE512 (HALMAC_RXPKT_MAX_SIZE >> 9) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c new file mode 100644 index 000000000000..e524b9bc8665 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.c @@ -0,0 +1,5404 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "halmac_88xx_cfg.h" + +/** + * halmac_init_adapter_para_88xx() - int halmac adapter + * @pHalmac_adapter + * + * SD1 internal use + * + * Author : KaiYuan Chang/Ivan Lin + * Return : VOID + */ +VOID +halmac_init_adapter_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + pHalmac_adapter->api_record.array_wptr = 0; + pHalmac_adapter->pHalAdapter_backup = pHalmac_adapter; + pHalmac_adapter->pHalEfuse_map = (u8 *)NULL; + pHalmac_adapter->hal_efuse_map_valid = _FALSE; + pHalmac_adapter->efuse_end = 0; + pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_Low = 0; + pHalmac_adapter->pHal_mac_addr[0].Address_L_H.Address_High = 0; + pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_Low = 0; + pHalmac_adapter->pHal_mac_addr[1].Address_L_H.Address_High = 0; + pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_Low = 0; + pHalmac_adapter->pHal_bss_addr[0].Address_L_H.Address_High = 0; + pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_Low = 0; + pHalmac_adapter->pHal_bss_addr[1].Address_L_H.Address_High = 0; + + pHalmac_adapter->low_clk = _FALSE; + pHalmac_adapter->max_download_size = HALMAC_FW_MAX_DL_SIZE_88XX; + + /* Init LPS Option */ + pHalmac_adapter->fwlps_option.mode = 0x01; /*0:Active 1:LPS 2:WMMPS*/ + pHalmac_adapter->fwlps_option.awake_interval = 1; + pHalmac_adapter->fwlps_option.enter_32K = 1; + pHalmac_adapter->fwlps_option.clk_request = 0; + pHalmac_adapter->fwlps_option.rlbm = 0; + pHalmac_adapter->fwlps_option.smart_ps = 0; + pHalmac_adapter->fwlps_option.awake_interval = 1; + pHalmac_adapter->fwlps_option.all_queue_uapsd = 0; + pHalmac_adapter->fwlps_option.pwr_state = 0; + pHalmac_adapter->fwlps_option.low_pwr_rx_beacon = 0; + pHalmac_adapter->fwlps_option.ant_auto_switch = 0; + pHalmac_adapter->fwlps_option.ps_allow_bt_high_Priority = 0; + pHalmac_adapter->fwlps_option.protect_bcn = 0; + pHalmac_adapter->fwlps_option.silence_period = 0; + pHalmac_adapter->fwlps_option.fast_bt_connect = 0; + pHalmac_adapter->fwlps_option.two_antenna_en = 0; + pHalmac_adapter->fwlps_option.adopt_user_Setting = 1; + pHalmac_adapter->fwlps_option.drv_bcn_early_shift = 0; + + pHalmac_adapter->config_para_info.pCfg_para_buf = NULL; + pHalmac_adapter->config_para_info.pPara_buf_w = NULL; + pHalmac_adapter->config_para_info.para_num = 0; + pHalmac_adapter->config_para_info.full_fifo_mode = _FALSE; + pHalmac_adapter->config_para_info.para_buf_size = 0; + pHalmac_adapter->config_para_info.avai_para_buf_size = 0; + pHalmac_adapter->config_para_info.offset_accumulation = 0; + pHalmac_adapter->config_para_info.value_accumulation = 0; + pHalmac_adapter->config_para_info.datapack_segment = 0; + + pHalmac_adapter->ch_sw_info.ch_info_buf = NULL; + pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL; + pHalmac_adapter->ch_sw_info.extra_info_en = 0; + pHalmac_adapter->ch_sw_info.buf_size = 0; + pHalmac_adapter->ch_sw_info.avai_buf_size = 0; + pHalmac_adapter->ch_sw_info.total_size = 0; + pHalmac_adapter->ch_sw_info.ch_num = 0; + + pHalmac_adapter->drv_info_size = 0; + + PLATFORM_RTL_MEMSET(pHalmac_adapter->pDriver_adapter, pHalmac_adapter->api_record.api_array, HALMAC_API_STUFF, sizeof(pHalmac_adapter->api_record.api_array)); + + pHalmac_adapter->txff_allocation.tx_fifo_pg_num = 0; + pHalmac_adapter->txff_allocation.ac_q_pg_num = 0; + pHalmac_adapter->txff_allocation.rsvd_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_h2c_queue_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_cpu_instr_pg_bndy = 0; + pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy = 0; + pHalmac_adapter->txff_allocation.pub_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.high_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.low_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.normal_queue_pg_num = 0; + pHalmac_adapter->txff_allocation.extra_queue_pg_num = 0; + + pHalmac_adapter->txff_allocation.la_mode = HALMAC_LA_MODE_DISABLE; + pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE; + + pHalmac_adapter->sdio_cmd53_4byte = HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE; + pHalmac_adapter->sdio_hw_info.io_hi_speed_flag = 0; + pHalmac_adapter->sdio_hw_info.spec_ver = HALMAC_SDIO_SPEC_VER_2_00; + pHalmac_adapter->sdio_hw_info.clock_speed = 50; + + halmac_init_adapter_dynamic_para_88xx(pHalmac_adapter); + halmac_init_state_machine_88xx(pHalmac_adapter); + +} + +/** + * halmac_init_adapter_dynamic_para_88xx() - int halmac adapter + * @pHalmac_adapter + * + * SD1 internal use + * + * Author : KaiYuan Chang/Ivan Lin + * Return : VOID + */ +VOID +halmac_init_adapter_dynamic_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + pHalmac_adapter->h2c_packet_seq = 0; + pHalmac_adapter->h2c_buf_free_space = 0; + pHalmac_adapter->gen_info_valid = _FALSE; +} + +/** + * halmac_init_state_machine_88xx() - init halmac software state machine + * @pHalmac_adapter + * + * SD1 internal use. + * + * Author : KaiYuan Chang/Ivan Lin + * Return : VOID + */ +VOID +halmac_init_state_machine_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state); + + halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter); + + pState->api_state = HALMAC_API_STATE_INIT; + + pState->dlfw_state = HALMAC_DLFW_NONE; + pState->mac_power = HALMAC_MAC_POWER_OFF; + pState->ps_state = HALMAC_PS_STATE_UNDEFINE; +} + +/** + * halmac_mount_api_88xx() - attach functions to function pointer + * @pHalmac_adapter + * + * SD1 internal use + * + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + */ +HALMAC_RET_STATUS +halmac_mount_api_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + PHALMAC_API pHalmac_api = (PHALMAC_API)NULL; + + pHalmac_adapter->pHalmac_api = (PHALMAC_API)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_API)); + if (NULL == pHalmac_adapter->pHalmac_api) + return HALMAC_RET_MALLOC_FAIL; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER_88XX"\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER_88XX = %x\n", HALMAC_MAJOR_VER_88XX); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_88XX = %x\n", HALMAC_PROTOTYPE_VER_88XX); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER_88XX = %x\n", HALMAC_MINOR_VER_88XX); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER_88XX = %x\n", HALMAC_PATCH_VER_88XX); + + /* Mount function pointer */ + pHalmac_api->halmac_download_firmware = halmac_download_firmware_88xx; + pHalmac_api->halmac_free_download_firmware = halmac_free_download_firmware_88xx; + pHalmac_api->halmac_get_fw_version = halmac_get_fw_version_88xx; + pHalmac_api->halmac_cfg_mac_addr = halmac_cfg_mac_addr_88xx; + pHalmac_api->halmac_cfg_bssid = halmac_cfg_bssid_88xx; + pHalmac_api->halmac_cfg_multicast_addr = halmac_cfg_multicast_addr_88xx; + pHalmac_api->halmac_pre_init_system_cfg = halmac_pre_init_system_cfg_88xx; + pHalmac_api->halmac_init_system_cfg = halmac_init_system_cfg_88xx; + pHalmac_api->halmac_init_edca_cfg = halmac_init_edca_cfg_88xx; + pHalmac_api->halmac_cfg_operation_mode = halmac_cfg_operation_mode_88xx; + pHalmac_api->halmac_cfg_ch_bw = halmac_cfg_ch_bw_88xx; + pHalmac_api->halmac_cfg_bw = halmac_cfg_bw_88xx; + pHalmac_api->halmac_init_wmac_cfg = halmac_init_wmac_cfg_88xx; + pHalmac_api->halmac_init_mac_cfg = halmac_init_mac_cfg_88xx; + pHalmac_api->halmac_init_pcie_cfg = halmac_init_pcie_cfg_88xx; + pHalmac_api->halmac_deinit_pcie_cfg = halmac_deinit_pcie_cfg_88xx; + pHalmac_api->halmac_dump_efuse_map = halmac_dump_efuse_map_88xx; + pHalmac_api->halmac_dump_efuse_map_bt = halmac_dump_efuse_map_bt_88xx; + pHalmac_api->halmac_write_efuse_bt = halmac_write_efuse_bt_88xx; + pHalmac_api->halmac_dump_logical_efuse_map = halmac_dump_logical_efuse_map_88xx; + pHalmac_api->halmac_pg_efuse_by_map = halmac_pg_efuse_by_map_88xx; + pHalmac_api->halmac_get_efuse_size = halmac_get_efuse_size_88xx; + pHalmac_api->halmac_get_efuse_available_size = halmac_get_efuse_available_size_88xx; + pHalmac_api->halmac_get_c2h_info = halmac_get_c2h_info_88xx; + + pHalmac_api->halmac_get_logical_efuse_size = halmac_get_logical_efuse_size_88xx; + + pHalmac_api->halmac_write_logical_efuse = halmac_write_logical_efuse_88xx; + pHalmac_api->halmac_read_logical_efuse = halmac_read_logical_efuse_88xx; + + pHalmac_api->halmac_cfg_fwlps_option = halmac_cfg_fwlps_option_88xx; + pHalmac_api->halmac_cfg_fwips_option = halmac_cfg_fwips_option_88xx; + pHalmac_api->halmac_enter_wowlan = halmac_enter_wowlan_88xx; + pHalmac_api->halmac_leave_wowlan = halmac_leave_wowlan_88xx; + pHalmac_api->halmac_enter_ps = halmac_enter_ps_88xx; + pHalmac_api->halmac_leave_ps = halmac_leave_ps_88xx; + pHalmac_api->halmac_h2c_lb = halmac_h2c_lb_88xx; + pHalmac_api->halmac_debug = halmac_debug_88xx; + pHalmac_api->halmac_cfg_parameter = halmac_cfg_parameter_88xx; + pHalmac_api->halmac_update_datapack = halmac_update_datapack_88xx; + pHalmac_api->halmac_run_datapack = halmac_run_datapack_88xx; + pHalmac_api->halmac_cfg_drv_info = halmac_cfg_drv_info_88xx; + pHalmac_api->halmac_send_bt_coex = halmac_send_bt_coex_88xx; + pHalmac_api->halmac_verify_platform_api = halmac_verify_platform_api_88xx; + pHalmac_api->halmac_update_packet = halmac_update_packet_88xx; + pHalmac_api->halmac_bcn_ie_filter = halmac_bcn_ie_filter_88xx; + pHalmac_api->halmac_cfg_txbf = halmac_cfg_txbf_88xx; + pHalmac_api->halmac_cfg_mumimo = halmac_cfg_mumimo_88xx; + pHalmac_api->halmac_cfg_sounding = halmac_cfg_sounding_88xx; + pHalmac_api->halmac_del_sounding = halmac_del_sounding_88xx; + pHalmac_api->halmac_su_bfer_entry_init = halmac_su_bfer_entry_init_88xx; + pHalmac_api->halmac_su_bfee_entry_init = halmac_su_bfee_entry_init_88xx; + pHalmac_api->halmac_mu_bfer_entry_init = halmac_mu_bfer_entry_init_88xx; + pHalmac_api->halmac_mu_bfee_entry_init = halmac_mu_bfee_entry_init_88xx; + pHalmac_api->halmac_su_bfer_entry_del = halmac_su_bfer_entry_del_88xx; + pHalmac_api->halmac_su_bfee_entry_del = halmac_su_bfee_entry_del_88xx; + pHalmac_api->halmac_mu_bfer_entry_del = halmac_mu_bfer_entry_del_88xx; + pHalmac_api->halmac_mu_bfee_entry_del = halmac_mu_bfee_entry_del_88xx; + + pHalmac_api->halmac_add_ch_info = halmac_add_ch_info_88xx; + pHalmac_api->halmac_add_extra_ch_info = halmac_add_extra_ch_info_88xx; + pHalmac_api->halmac_ctrl_ch_switch = halmac_ctrl_ch_switch_88xx; + pHalmac_api->halmac_p2pps = halmac_p2pps_88xx; + pHalmac_api->halmac_clear_ch_info = halmac_clear_ch_info_88xx; + pHalmac_api->halmac_send_general_info = halmac_send_general_info_88xx; + + pHalmac_api->halmac_start_iqk = halmac_start_iqk_88xx; + pHalmac_api->halmac_ctrl_pwr_tracking = halmac_ctrl_pwr_tracking_88xx; + pHalmac_api->halmac_psd = halmac_psd_88xx; + pHalmac_api->halmac_cfg_la_mode = halmac_cfg_la_mode_88xx; + pHalmac_api->halmac_cfg_rx_fifo_expanding_mode = halmac_cfg_rx_fifo_expanding_mode_88xx; + + pHalmac_api->halmac_config_security = halmac_config_security_88xx; + pHalmac_api->halmac_get_used_cam_entry_num = halmac_get_used_cam_entry_num_88xx; + pHalmac_api->halmac_read_cam_entry = halmac_read_cam_entry_88xx; + pHalmac_api->halmac_write_cam = halmac_write_cam_88xx; + pHalmac_api->halmac_clear_cam_entry = halmac_clear_cam_entry_88xx; + + pHalmac_api->halmac_get_hw_value = halmac_get_hw_value_88xx; + pHalmac_api->halmac_set_hw_value = halmac_set_hw_value_88xx; + + pHalmac_api->halmac_cfg_drv_rsvd_pg_num = halmac_cfg_drv_rsvd_pg_num_88xx; + pHalmac_api->halmac_get_chip_version = halmac_get_chip_version_88xx; + + pHalmac_api->halmac_query_status = halmac_query_status_88xx; + pHalmac_api->halmac_reset_feature = halmac_reset_feature_88xx; + pHalmac_api->halmac_check_fw_status = halmac_check_fw_status_88xx; + pHalmac_api->halmac_dump_fw_dmem = halmac_dump_fw_dmem_88xx; + pHalmac_api->halmac_cfg_max_dl_size = halmac_cfg_max_dl_size_88xx; + + pHalmac_api->halmac_dump_fifo = halmac_dump_fifo_88xx; + pHalmac_api->halmac_get_fifo_size = halmac_get_fifo_size_88xx; + + pHalmac_api->halmac_chk_txdesc = halmac_chk_txdesc_88xx; + pHalmac_api->halmac_dl_drv_rsvd_page = halmac_dl_drv_rsvd_page_88xx; + pHalmac_api->halmac_cfg_csi_rate = halmac_cfg_csi_rate_88xx; + + pHalmac_api->halmac_txfifo_is_empty = halmac_txfifo_is_empty_88xx; + + if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface) { + pHalmac_api->halmac_cfg_rx_aggregation = halmac_cfg_rx_aggregation_88xx_pcie; + pHalmac_api->halmac_init_interface_cfg = halmac_init_pcie_cfg_88xx; + pHalmac_api->halmac_deinit_interface_cfg = halmac_deinit_pcie_cfg_88xx; + pHalmac_api->halmac_reg_read_8 = halmac_reg_read_8_pcie_88xx; + pHalmac_api->halmac_reg_write_8 = halmac_reg_write_8_pcie_88xx; + pHalmac_api->halmac_reg_read_16 = halmac_reg_read_16_pcie_88xx; + pHalmac_api->halmac_reg_write_16 = halmac_reg_write_16_pcie_88xx; + pHalmac_api->halmac_reg_read_32 = halmac_reg_read_32_pcie_88xx; + pHalmac_api->halmac_reg_write_32 = halmac_reg_write_32_pcie_88xx; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Set halmac io function Error!!\n"); + } + + pHalmac_api->halmac_timer_2s = halmac_timer_2s_88xx; + pHalmac_api->halmac_fill_txdesc_checksum = halmac_fill_txdesc_check_sum_88xx; + + if (HALMAC_CHIP_ID_8822B == pHalmac_adapter->chip_id) { + + } else if (HALMAC_CHIP_ID_8821C == pHalmac_adapter->chip_id) { + /*mount 8822b function and data*/ + halmac_mount_api_8821c(pHalmac_adapter); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Chip ID undefine!!\n"); + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_download_firmware_88xx() - download Firmware + * @pHalmac_adapter : the adapter of halmac + * @pHamacl_fw : firmware bin + * @halmac_fw_size : firmware size + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_download_firmware_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +) +{ + u8 value8; + u8 *pFile_ptr; + u16 value16; + u32 restore_index = 0; + u32 halmac_h2c_ver = 0, fw_h2c_ver = 0; + u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RESTORE_INFO restore_info[DLFW_RESTORE_REG_NUM_88XX]; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DOWNLOAD_FIRMWARE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx start!!\n"); + + if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size error!\n"); + return HALMAC_RET_FW_SIZE_ERR; + } + + fw_h2c_ver = rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX))); + halmac_h2c_ver = H2C_FORMAT_VERSION; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac h2c/c2h format = %x, fw h2c/c2h format = %x!!\n", halmac_h2c_ver, fw_h2c_ver); + if (fw_h2c_ver != halmac_h2c_ver) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]H2C/C2H version between HALMAC and FW is compatible!!\n"); + + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_NONE; + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1); + value8 = (u8)(value8 & ~(BIT(2))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Disable CPU reset */ + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1); + value8 = (u8)(value8 & ~(BIT(0))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8); + + restore_info[restore_index].length = 1; + restore_info[restore_index].mac_register = REG_TXDMA_PQ_MAP + 1; + restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1); + restore_index++; + value8 = HALMAC_DMA_MAPPING_HIGH << 6; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXDMA_PQ_MAP + 1, value8); /* set HIQ to hi priority */ + + /* DLFW only use HIQ, map HIQ to hi priority */ + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = HALMAC_DMA_MAPPING_HIGH; + restore_info[restore_index].length = 1; + restore_info[restore_index].mac_register = REG_CR; + restore_info[restore_index].value = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR); + restore_index++; + restore_info[restore_index].length = 4; + restore_info[restore_index].mac_register = REG_H2CQ_CSR; + restore_info[restore_index].value = BIT(31); + restore_index++; + value8 = BIT_HCI_TXDMA_EN | BIT_TXDMA_EN; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR, value8); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_H2CQ_CSR, BIT(31)); + + /* Config hi priority queue and public priority queue page number (only for DLFW) */ + restore_info[restore_index].length = 2; + restore_info[restore_index].mac_register = REG_FIFOPAGE_INFO_1; + restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1); + restore_index++; + restore_info[restore_index].length = 4; + restore_info[restore_index].mac_register = REG_RQPN_CTRL_2; + restore_info[restore_index].value = HALMAC_REG_READ_32(pHalmac_adapter, REG_RQPN_CTRL_2) | BIT(31); + restore_index++; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_INFO_1, 0x200); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RQPN_CTRL_2, restore_info[restore_index - 1].value); + + halmac_update_fw_info_88xx(pHalmac_adapter, pHamacl_fw, halmac_fw_size); + + dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX)); + iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX)); + if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4))) + eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX)); + + dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size); + iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size); + eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size); + + dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + if (0 != eram_pkt_size) + eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + + if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "FW size mismatch the real fw size!\n"); + goto DLFW_FAIL; + } + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); + restore_info[restore_index].length = 1; + restore_info[restore_index].mac_register = REG_CR + 1; + restore_info[restore_index].value = value8; + restore_index++; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); /* Enable SW TX beacon */ + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); + restore_info[restore_index].length = 1; + restore_info[restore_index].mac_register = REG_BCN_CTRL; + restore_info[restore_index].value = value8; + restore_index++; + value8 = (u8)((value8 & (~BIT(3))) | BIT(4)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); /* Disable beacon related functions */ + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); + restore_info[restore_index].length = 1; + restore_info[restore_index].mac_register = REG_FWHW_TXQ_CTRL + 2; + restore_info[restore_index].value = value8; + restore_index++; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); /* Disable ptcl tx bcnq */ + + restore_info[restore_index].length = 2; + restore_info[restore_index].mac_register = REG_FIFOPAGE_CTRL_2; + restore_info[restore_index].value = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15); + restore_index++; + value16 = 0x8000; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, value16); /* Set beacon header to 0 */ + + value16 = (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) & 0x3800); + value16 |= BIT(0); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, value16); /* MCU/FW setting */ + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2); + value8 &= ~(BIT(0)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8); + value8 |= BIT(0); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CPU_DMEM_CON + 2, value8); + + /* Download to DMEM */ + pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX; + /* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_DMEM_88XX, dmem_pkt_size)) */ + if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_ADDR_88XX))) & ~(BIT(31)), dmem_pkt_size)) + goto DLFW_END; + + /* Download to IMEM */ + pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size; + /* if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, HALMAC_OCPBASE_IMEM_88XX, iram_pkt_size)) */ + if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_ADDR_88XX))) & ~(BIT(31)), iram_pkt_size)) + goto DLFW_END; + + /* Download to EMEM */ + if (0 != eram_pkt_size) { + pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size; + if (HALMAC_RET_SUCCESS != halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size)) + goto DLFW_END; + } + + halmac_init_offload_feature_state_machine_88xx(pHalmac_adapter); +DLFW_END: + + halmac_restore_mac_register_88xx(pHalmac_adapter, restore_info, DLFW_RESTORE_REG_NUM_88XX); + + if (HALMAC_RET_SUCCESS != halmac_dlfw_end_flow_88xx(pHalmac_adapter)) + goto DLFW_FAIL; + + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_DLFW_DONE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_download_firmware_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; + +DLFW_FAIL: + + /* Disable FWDL_EN */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0)))); + + return HALMAC_RET_DLFW_FAIL; +} + +/** + * halmac_free_download_firmware_88xx() - download specific memory firmware + * @pHalmac_adapter + * @dlfw_mem : memory selection + * @pHamacl_fw : firmware bin + * @halmac_fw_size : firmware size + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + */ +HALMAC_RET_STATUS +halmac_free_download_firmware_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DLFW_MEM dlfw_mem, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +) +{ + u8 tx_pause_backup; + u8 *pFile_ptr; + u16 bcn_head_backup; + u32 iram_pkt_size, dmem_pkt_size, eram_pkt_size = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_DLFW_FAIL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx ==========>\n"); + + if (halmac_fw_size > HALMAC_FW_SIZE_MAX_88XX || halmac_fw_size < HALMAC_FWHDR_SIZE_88XX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size error!\n"); + return HALMAC_RET_FW_SIZE_ERR; + } + + dmem_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_DMEM_SIZE_88XX)); + iram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_IRAM_SIZE_88XX)); + if (0 != ((*(pHamacl_fw + HALMAC_FWHDR_OFFSET_MEM_USAGE_88XX)) & BIT(4))) + eram_pkt_size = *((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_ERAM_SIZE_88XX)); + + dmem_pkt_size = rtk_le32_to_cpu(dmem_pkt_size); + iram_pkt_size = rtk_le32_to_cpu(iram_pkt_size); + eram_pkt_size = rtk_le32_to_cpu(eram_pkt_size); + + dmem_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + iram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + if (0 != eram_pkt_size) + eram_pkt_size += HALMAC_FW_CHKSUM_DUMMY_SIZE_88XX; + + if (halmac_fw_size != (HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size + eram_pkt_size)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]FW size mismatch the real fw size!\n"); + return HALMAC_RET_DLFW_FAIL; + } + + tx_pause_backup = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPAUSE); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup | BIT(7)); + + bcn_head_backup = HALMAC_REG_READ_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2) | BIT(15); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0x8000); + + if (0 != eram_pkt_size) { + pFile_ptr = pHamacl_fw + HALMAC_FWHDR_SIZE_88XX + dmem_pkt_size + iram_pkt_size; + status = halmac_dlfw_to_mem_88xx(pHalmac_adapter, pFile_ptr, + rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_EMEM_ADDR_88XX))) & ~(BIT(31)), eram_pkt_size); + if (HALMAC_RET_SUCCESS != status) + goto DL_FREE_FW_END; + } + + status = halmac_free_dl_fw_end_flow_88xx(pHalmac_adapter); + +DL_FREE_FW_END: + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXPAUSE, tx_pause_backup); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, bcn_head_backup); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_free_download_firmware_88xx <==========\n"); + + return status; +} + +/** + * halmac_get_fw_version_88xx() - get FW version + * @pHalmac_adapter : the adapter of halmac + * @pFw_version : fw version info + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_fw_version_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT PHALMAC_FW_VERSION pFw_version +) +{ + PHALMAC_FW_VERSION pFw_info = &(pHalmac_adapter->fw_version); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (pFw_version == NULL) + return HALMAC_RET_NULL_POINTER; + + if (pHalmac_adapter->halmac_state.dlfw_state == HALMAC_DLFW_NONE) { + return HALMAC_RET_NO_DLFW; + } else { + pFw_version->version = pFw_info->version; + pFw_version->sub_version = pFw_info->sub_version; + pFw_version->sub_index = pFw_info->sub_index; + pFw_version->h2c_version = pFw_info->h2c_version; + pFw_version->build_time.month = pFw_info->build_time.month; + pFw_version->build_time.date = pFw_info->build_time.date; + pFw_version->build_time.hour = pFw_info->build_time.hour; + pFw_version->build_time.min = pFw_info->build_time.min; + pFw_version->build_time.year = pFw_info->build_time.year; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_mac_addr_88xx() - config mac address + * @pHalmac_adapter : the adapter of halmac + * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @pHal_address : mac address + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_mac_addr_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 halmac_port, + IN PHALMAC_WLAN_ADDR pHal_address +) +{ + u16 mac_address_H; + u32 mac_address_L; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx ==========>\n"); + + if (halmac_port >= HALMAC_PORTIDMAX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + mac_address_L = pHal_address->Address_L_H.Address_Low; + mac_address_H = pHal_address->Address_L_H.Address_High; + + mac_address_L = rtk_le32_to_cpu(mac_address_L); + mac_address_H = rtk_le16_to_cpu(mac_address_H); + + pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_Low = mac_address_L; + pHalmac_adapter->pHal_mac_addr[halmac_port].Address_L_H.Address_High = mac_address_H; + + switch (halmac_port) { + + case HALMAC_PORTID0: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID + 4, mac_address_H); + break; + + case HALMAC_PORTID1: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID1, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID1 + 4, mac_address_H); + break; + + case HALMAC_PORTID2: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID2, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID2 + 4, mac_address_H); + break; + + case HALMAC_PORTID3: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID3, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID3 + 4, mac_address_H); + break; + + case HALMAC_PORTID4: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MACID4, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MACID4 + 4, mac_address_H); + break; + + default: + break; + + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_mac_addr_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_bssid_88xx() - config BSSID + * @pHalmac_adapter : the adapter of halmac + * @halmac_port : 0 for port0, 1 for port1, 2 for port2, 3 for port3, 4 for port4 + * @pHal_address : bssid + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_bssid_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 halmac_port, + IN PHALMAC_WLAN_ADDR pHal_address +) +{ + u16 bssid_address_H; + u32 bssid_address_L; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx ==========>\n"); + + if (halmac_port >= HALMAC_PORTIDMAX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]port index > 5\n"); + return HALMAC_RET_PORT_NOT_SUPPORT; + } + + bssid_address_L = pHal_address->Address_L_H.Address_Low; + bssid_address_H = pHal_address->Address_L_H.Address_High; + + bssid_address_L = rtk_le32_to_cpu(bssid_address_L); + bssid_address_H = rtk_le16_to_cpu(bssid_address_H); + + pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_Low = bssid_address_L; + pHalmac_adapter->pHal_bss_addr[halmac_port].Address_L_H.Address_High = bssid_address_H; + + switch (halmac_port) { + + case HALMAC_PORTID0: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID + 4, bssid_address_H); + break; + + case HALMAC_PORTID1: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID1, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID1 + 4, bssid_address_H); + break; + + case HALMAC_PORTID2: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID2, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID2 + 4, bssid_address_H); + break; + + case HALMAC_PORTID3: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID3, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID3 + 4, bssid_address_H); + break; + + case HALMAC_PORTID4: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BSSID4, bssid_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_BSSID4 + 4, bssid_address_H); + break; + + default: + break; + + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_cfg_bssid_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_multicast_addr_88xx() - config multicast address + * @pHalmac_adapter : the adapter of halmac + * @pHal_address : multicast address + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_multicast_addr_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_WLAN_ADDR pHal_address +) +{ + u16 address_H; + u32 address_L; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MULTICAST_ADDR); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx ==========>\n"); + + address_L = pHal_address->Address_L_H.Address_Low; + address_H = pHal_address->Address_L_H.Address_High; + + address_L = rtk_le32_to_cpu(address_L); + address_H = rtk_le16_to_cpu(address_H); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MAR, address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MAR + 4, address_H); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_multicast_addr_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pre_init_system_cfg_88xx() - pre-init system config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pre_init_system_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u32 value32, counter; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 enable_bb; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PRE_INIT_SYSTEM_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg ==========>\n"); + + /* Config PIN Mux */ + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL1); + value32 = value32 & (~(BIT(28) | BIT(29))); + value32 = value32 | BIT(28) | BIT(29); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL1, value32); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_LED_CFG); + value32 = value32 & (~(BIT(25) | BIT(26))); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_LED_CFG, value32); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG); + value32 = value32 & (~(BIT(2))); + value32 = value32 | BIT(2); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, value32); + + enable_bb = _FALSE; + halmac_set_hw_value_88xx(pHalmac_adapter, HALMAC_HW_EN_BB_RF, &enable_bb); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pre_init_system_cfg <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_system_cfg_88xx() - init system config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_system_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u32 temp = 0; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_SYSTEM_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg ==========>\n"); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, HALMAC_FUNCTION_ENABLE_88XX); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SYS_SDIO_CTRL, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_SYS_SDIO_CTRL) | BIT_LTE_MUX_CTRL_PATH)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CPU_DMEM_CON, (u32)(HALMAC_REG_READ_32(pHalmac_adapter, REG_CPU_DMEM_CON) | BIT_WL_PLATFORM_RST)); + + /*disable boot-from-flash for driver's DL FW*/ + temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_MCUFW_CTRL); + if (temp & BIT_BOOT_FSPI_EN) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MCUFW_CTRL, temp & (~BIT_BOOT_FSPI_EN)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_GPIO_MUXCFG, HALMAC_REG_READ_32(pHalmac_adapter, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN)); + } + + /* pHalmac_api->halmac_init_h2c(pHalmac_adapter); */ + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_system_cfg <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_edca_cfg_88xx() - init EDCA config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_edca_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 value8; + u32 value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_EDCA_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx ==========>\n"); + + /* Clear TX pause */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXPAUSE, 0x0000); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SLOT, HALMAC_SLOT_TIME_88XX); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PIFS, HALMAC_PIFS_TIME_88XX); + value32 = HALMAC_SIFS_CCK_CTX_88XX | (HALMAC_SIFS_OFDM_CTX_88XX << BIT_SHIFT_SIFS_OFDM_CTX) | + (HALMAC_SIFS_CCK_TRX_88XX << BIT_SHIFT_SIFS_CCK_TRX) | (HALMAC_SIFS_OFDM_TRX_88XX << BIT_SHIFT_SIFS_OFDM_TRX); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_SIFS, value32); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EDCA_VO_PARAM, HALMAC_REG_READ_32(pHalmac_adapter, REG_EDCA_VO_PARAM) & 0xFFFF); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VO_PARAM + 2, HALMAC_VO_TXOP_LIMIT_88XX); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_EDCA_VI_PARAM + 2, HALMAC_VI_TXOP_LIMIT_88XX); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RD_NAV_NXT, HALMAC_RDG_NAV_88XX | (HALMAC_TXOP_NAV_88XX << 16)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXTSF_OFFSET_CCK, HALMAC_CCK_RX_TSF_88XX | (HALMAC_OFDM_RX_TSF_88XX) << 8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RD_CTRL + 1); + value8 |= (BIT_VOQ_RD_INIT_EN | BIT_VIQ_RD_INIT_EN | BIT_BEQ_RD_INIT_EN); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RD_CTRL + 1, value8); + + /* Set beacon cotnrol - enable TSF and other related functions */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL) | BIT_EN_BCN_FUNCTION)); + + /* Set send beacon related registers */ + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TBTT_PROHIBIT, HALMAC_TBTT_PROHIBIT_88XX | (HALMAC_TBTT_HOLD_TIME_88XX << BIT_SHIFT_TBTT_HOLD_TIME_AP)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DRVERLYINT, HALMAC_DRIVER_EARLY_INT_88XX); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCNDMATIM, HALMAC_BEACON_DMA_TIM_88XX); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_edca_cfg_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_wmac_cfg_88xx() - init wmac config + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_wmac_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_WMAC_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx ==========>\n"); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RXFLTMAP0, HALMAC_RX_FILTER0_88XX); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RXFLTMAP, HALMAC_RX_FILTER_88XX); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, HALMAC_RCR_CONFIG_88XX); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_PKT_LIMIT, HALMAC_RXPKT_MAX_SIZE_BASE512); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_TCR + 1) | 0x30)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 2, 0x30); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TCR + 1, 0x00); + + if (HALMAC_CHIP_ID_8821C == pHalmac_adapter->chip_id) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_ACKTO_CCK, HALMAC_ACK_TO_CCK_88XX); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 8, 0x30810041); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, 0x50802080); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_wmac_cfg_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_init_mac_cfg_88xx() - config page1~page7 register + * @pHalmac_adapter : the adapter of halmac + * @mode : trx mode + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_mac_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE mode +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_MAC_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx ==========>mode = %d\n", mode); + + status = pHalmac_api->halmac_init_trx_cfg(pHalmac_adapter, mode); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_trx_cfg errorr = %x\n", status); + return status; + } + status = pHalmac_api->halmac_init_protocol_cfg(pHalmac_adapter); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_protocol_cfg_88xx error = %x\n", status); + return status; + } + + status = halmac_init_edca_cfg_88xx(pHalmac_adapter); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_edca_cfg_88xx error = %x\n", status); + return status; + } + + status = halmac_init_wmac_cfg_88xx(pHalmac_adapter); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_init_wmac_cfg_88xx error = %x\n", status); + return status; + } + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_mac_cfg_88xx <==========\n"); + + return status; +} + +/** + * halmac_cfg_operation_mode_88xx() - config operation mode + * @pHalmac_adapter : the adapter of halmac + * @wireless_mode : 802.11 standard(b/g/n/ac�K) + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_operation_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_WIRELESS_MODE wireless_mode +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_WIRELESS_MODE wireless_mode_local = HALMAC_WIRELESS_MODE_UNDEFINE; + + wireless_mode_local = wireless_mode; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_OPERATION_MODE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx ==========>wireless_mode = %d\n", wireless_mode); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_operation_mode_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_ch_bw_88xx() - config channel & bandwidth + * @pHalmac_adapter : the adapter of halmac + * @channel : WLAN channel, support 2.4G & 5G + * @pri_ch_idx : primary channel index, idx1, idx2, idx3, idx4 + * @bw : band width, 20, 40, 80, 160, 5 ,10 + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_ch_bw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 channel, + IN HALMAC_PRI_CH_IDX pri_ch_idx, + IN HALMAC_BW bw +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx ==========>ch = %d, idx=%d, bw=%d\n", channel, pri_ch_idx, bw); + + halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, pri_ch_idx); + + halmac_cfg_bw_88xx(pHalmac_adapter, bw); + + halmac_cfg_ch_88xx(pHalmac_adapter, channel); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_bw_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_cfg_ch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 channel +) +{ + u8 value8; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx ==========>ch = %d\n", channel); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CCK_CHECK); + value8 = value8 & (~(BIT(7))); + + if (channel > 35) + value8 = value8 | BIT(7); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CCK_CHECK, value8); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_ch_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_cfg_pri_ch_idx_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PRI_CH_IDX pri_ch_idx +) +{ + u8 txsc_40 = 0, txsc_20 = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CH_BW); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx ==========> idx=%d\n", pri_ch_idx); + + txsc_20 = pri_ch_idx; + if ((HALMAC_CH_IDX_1 == txsc_20) || (HALMAC_CH_IDX_3 == txsc_20)) + txsc_40 = 9; + else + txsc_40 = 10; + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DATA_SC, BIT_TXSC_20M(txsc_20) | BIT_TXSC_40M(txsc_40)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_pri_ch_idx_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; + +} + +/** + * halmac_cfg_bw_88xx() - config bandwidth + * @pHalmac_adapter : the adapter of halmac + * @bw : band width, 20, 40, 80, 160, 5 ,10 + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_bw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_BW bw +) +{ + u32 value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_BW); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx ==========>bw=%d\n", bw); + + /* RF Mode */ + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL); + value32 = value32 & (~(BIT(7) | BIT(8))); + + switch (bw) { + case HALMAC_BW_80: + value32 = value32 | BIT(7); + break; + case HALMAC_BW_40: + value32 = value32 | BIT(8); + break; + case HALMAC_BW_20: + case HALMAC_BW_10: + case HALMAC_BW_5: + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_bw_88xx switch case not support\n"); + break; + } + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_TRXPTCL_CTL, value32); + + /* MAC CLK */ + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_AFE_CTRL1); + value32 = (value32 & (~(BIT(20) | BIT(21)))) | (HALMAC_MAC_CLOCK_HW_DEF_80M << BIT_SHIFT_MAC_CLK_SEL); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_AFE_CTRL1, value32); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_TSF, HALMAC_MAC_CLOCK_88XX); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_USTIME_EDCA, HALMAC_MAC_CLOCK_88XX); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_bw_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_dump_efuse_map_88xx() - dump "physical" efuse map + * @pHalmac_adapter : the adapter of halmac + * @cfg : dump efuse method + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_dump_efuse_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_READ_CFG cfg +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx ==========>cfg=%d\n", cfg); + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump efuse in suspend mode\n"); + + *pProcess_status = HALMAC_CMD_PROCESS_IDLE; + pHalmac_adapter->event_trigger.physical_efuse_map = 1; + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status); + return status; + } + + if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) { + *pProcess_status = HALMAC_CMD_PROCESS_DONE; + + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, *pProcess_status, + pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); + pHalmac_adapter->event_trigger.physical_efuse_map = 0; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_dump_efuse_map_bt_88xx() - dump "BT physical" efuse map + * @pHalmac_adapter : the adapter of halmac + * @halmac_efuse_bank : bt efuse bank + * @bt_efuse_map_size : bt efuse map size. get from halmac_get_efuse_size API + * @pBT_efuse_map : bt efuse map + * Author : Soar / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_dump_efuse_map_bt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_BANK halmac_efuse_bank, + IN u32 bt_efuse_map_size, + OUT u8 *pBT_efuse_map +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_EFUSE_MAP_BT); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx ==========>\n"); + + if (pHalmac_adapter->hw_config_info.bt_efuse_size != bt_efuse_map_size) + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + + if ((halmac_efuse_bank >= HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + status = halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, bt_efuse_map_size, pBT_efuse_map); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_hw_efuse_88xx error = %x\n", status); + return status; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_efuse_map_bt_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_write_efuse_bt_88xx() - write "BT physical" efuse offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : offset + * @halmac_value : Write value + * @pBT_efuse_map : bt efuse map + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_write_efuse_bt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u8 halmac_value, + IN HALMAC_EFUSE_BANK halmac_efuse_bank +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_EFUSE_BT); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx ==========>\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "offset : %X value : %X Bank : %X\n", halmac_offset, halmac_value, halmac_efuse_bank); + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (halmac_offset >= pHalmac_adapter->hw_config_info.efuse_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if ((halmac_efuse_bank > HALMAC_EFUSE_BANK_MAX) || (halmac_efuse_bank == HALMAC_EFUSE_BANK_WIFI)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Undefined BT bank\n"); + return HALMAC_RET_EFUSE_BANK_INCORRECT; + } + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, halmac_efuse_bank); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + status = halmac_func_write_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_write_efuse error = %x\n", status); + return status; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_efuse_bt_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_efuse_available_size_88xx() - get efuse available size + * @pHalmac_adapter : the adapter of halmac + * @halmac_size : physical efuse available size + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_efuse_available_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +) +{ + HALMAC_RET_STATUS status; + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx ==========>\n"); + + status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV); + + if (HALMAC_RET_SUCCESS != status) + return status; + + *halmac_size = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_available_size_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_efuse_size_88xx() - get "physical" efuse size + * @pHalmac_adapter : the adapter of halmac + * @halmac_size : physical efuse size + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_efuse_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_EFUSE_SIZE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx ==========>\n"); + + *halmac_size = pHalmac_adapter->hw_config_info.efuse_size; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_efuse_size_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_logical_efuse_size_88xx() - get "logical" efuse size + * @pHalmac_adapter : the adapter of halmac + * @halmac_size : logical efuse size + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_logical_efuse_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_LOGICAL_EFUSE_SIZE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx ==========>\n"); + + *halmac_size = pHalmac_adapter->hw_config_info.eeprom_size; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_get_logical_efuse_size_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_dump_logical_efuse_map_88xx() - dump "logical" efuse map + * @pHalmac_adapter : the adapter of halmac + * @cfg : dump efuse method + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_dump_logical_efuse_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_READ_CFG cfg +) +{ + u8 *pEeprom_map = NULL; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_LOGICAL_EFUSE_MAP); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx ==========>cfg = %d\n", cfg); + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (HALMAC_MAC_POWER_OFF == pHalmac_adapter->halmac_state.mac_power) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_WARN, "[WARN]Dump logical efuse in suspend mode\n"); + + *pProcess_status = HALMAC_CMD_PROCESS_IDLE; + pHalmac_adapter->event_trigger.logical_efuse_map = 1; + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + status = halmac_dump_efuse_88xx(pHalmac_adapter, cfg); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_eeprom_parser_88xx error = %x\n", status); + return status; + } + + if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) { + *pProcess_status = HALMAC_CMD_PROCESS_DONE; + + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (NULL == pEeprom_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, *pProcess_status, pEeprom_map, eeprom_size); + pHalmac_adapter->event_trigger.logical_efuse_map = 0; + + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + } + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_dump_logical_efuse_map_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_read_logical_efuse_88xx() - read logical efuse map 1 byte + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : offset + * @pValue : 1 byte efuse value + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_read_logical_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + OUT u8 *pValue +) +{ + u8 *pEeprom_map = NULL; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_READ_LOGICAL_EFUSE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx ==========>\n"); + + if (halmac_offset >= eeprom_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (NULL == pEeprom_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_logical_efuse_map error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return status; + } + + *pValue = *(pEeprom_map + halmac_offset); + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_ERROR_STATE; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_read_logical_efuse_88xx <==========\n"); + + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_write_logical_efuse_88xx() - write "logical" efuse offset + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : offset + * @halmac_value : value + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_write_logical_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u8 halmac_value +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_WRITE_LOGICAL_EFUSE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx ==========>\n"); + + if (halmac_offset >= pHalmac_adapter->hw_config_info.eeprom_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Offset is too large\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + status = halmac_func_write_logical_efuse_88xx(pHalmac_adapter, halmac_offset, halmac_value); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_write_logical_efuse error = %x\n", status); + return status; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_write_logical_efuse_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_pg_efuse_by_map_88xx() - pg logical efuse by map + * @pHalmac_adapter : the adapter of halmac + * @pPg_efuse_info : efuse map information + * @cfg : dump efuse method + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_pg_efuse_by_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN HALMAC_EFUSE_READ_CFG cfg +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PG_EFUSE_BY_MAP); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx ==========>\n"); + + if (pPg_efuse_info->efuse_map_size != pHalmac_adapter->hw_config_info.eeprom_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size is incorrect, should be %d bytes\n", pHalmac_adapter->hw_config_info.eeprom_size); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if ((pPg_efuse_info->efuse_map_size & 0xF) > 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map_size should be multiple of 16\n"); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (pPg_efuse_info->efuse_mask_size != pPg_efuse_info->efuse_map_size >> 4) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask_size is incorrect, should be %d bytes\n", pPg_efuse_info->efuse_map_size >> 4); + return HALMAC_RET_EFUSE_SIZE_INCORRECT; + } + + if (NULL == pPg_efuse_info->pEfuse_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_map is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (NULL == pPg_efuse_info->pEfuse_mask) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "efuse_mask is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait/Rcvd event(dump efuse)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != halmac_query_efuse_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(dump efuse)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + status = halmac_func_switch_efuse_bank_88xx(pHalmac_adapter, HALMAC_EFUSE_BANK_WIFI); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_func_switch_efuse_bank error = %x\n", status); + return status; + } + + status = halmac_func_pg_efuse_by_map_88xx(pHalmac_adapter, pPg_efuse_info, cfg); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_pg_efuse_by_map error = %x\n", status); + return status; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_TRACE, "halmac_pg_efuse_by_map_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_c2h_info_88xx() - process halmac C2H packet + * @pHalmac_adapter : the adapter of halmac + * @halmac_buf : RX Packet pointer + * @halmac_size : RX Packet size + * Author : KaiYuan Chang/Ivan Lin + * + * Used to process c2h packet info from RX path. After receiving the packet, + * user need to call this api and pass the packet pointer. + * + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_c2h_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *halmac_buf, + IN u32 halmac_size +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_C2H_INFO); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx ==========>\n"); */ + + /* Check if it is C2H packet */ + if (_TRUE == GET_RX_DESC_C2H(halmac_buf)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H packet, start parsing!\n"); + + status = halmac_parse_c2h_packet_88xx(pHalmac_adapter, halmac_buf, halmac_size); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_parse_c2h_packet_88xx error = %x\n", status); + return status; + } + } + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_c2h_info_88xx <==========\n"); */ + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_cfg_fwlps_option_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_FWLPS_OPTION pLps_option +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_FWLPS_OPTION pHal_fwlps_option; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWLPS_OPTION); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHal_fwlps_option = &(pHalmac_adapter->fwlps_option); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx ==========>\n"); + + pHal_fwlps_option->mode = pLps_option->mode; + pHal_fwlps_option->clk_request = pLps_option->clk_request; + pHal_fwlps_option->rlbm = pLps_option->rlbm; + pHal_fwlps_option->smart_ps = pLps_option->smart_ps; + pHal_fwlps_option->awake_interval = pLps_option->awake_interval; + pHal_fwlps_option->all_queue_uapsd = pLps_option->all_queue_uapsd; + pHal_fwlps_option->pwr_state = pLps_option->pwr_state; + pHal_fwlps_option->low_pwr_rx_beacon = pLps_option->low_pwr_rx_beacon; + pHal_fwlps_option->ant_auto_switch = pLps_option->ant_auto_switch; + pHal_fwlps_option->ps_allow_bt_high_Priority = pLps_option->ps_allow_bt_high_Priority; + pHal_fwlps_option->protect_bcn = pLps_option->protect_bcn; + pHal_fwlps_option->silence_period = pLps_option->silence_period; + pHal_fwlps_option->fast_bt_connect = pLps_option->fast_bt_connect; + pHal_fwlps_option->two_antenna_en = pLps_option->two_antenna_en; + pHal_fwlps_option->adopt_user_Setting = pLps_option->adopt_user_Setting; + pHal_fwlps_option->drv_bcn_early_shift = pLps_option->drv_bcn_early_shift; + pHal_fwlps_option->enter_32K = pLps_option->enter_32K; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwlps_option_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_cfg_fwips_option_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_FWIPS_OPTION pIps_option +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_FWIPS_OPTION pIps_option_local; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_FWIPS_OPTION); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx ==========>\n"); + + pIps_option_local = pIps_option; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_cfg_fwips_option_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_enter_wowlan_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_WOWLAN_OPTION pWowlan_option +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_WOWLAN_OPTION pWowlan_option_local; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_WOWLAN); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx ==========>\n"); + + pWowlan_option_local = pWowlan_option; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_wowlan_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_leave_wowlan_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_WOWLAN); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_wowlan_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_enter_ps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PS_STATE ps_state +) +{ + u8 rpwm; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ENTER_PS); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx ==========>\n"); + + if (ps_state == pHalmac_adapter->halmac_state.ps_state) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in PS State!!\n"); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_PS_STATE_LPS == ps_state) { + status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(pHalmac_adapter->fwlps_option)); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error = %x!!\n", status); + return status; + } + } else if (HALMAC_PS_STATE_IPS == ps_state) { + } + + pHalmac_adapter->halmac_state.ps_state = ps_state; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_enter_ps_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_leave_ps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 rpwm, cpwm; + u32 counter; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_FWLPS_OPTION fw_lps_option; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_LEAVE_PS); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx ==========>\n"); + + if (HALMAC_PS_STATE_ACT == pHalmac_adapter->halmac_state.ps_state) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "power state is already in active!!\n"); + return HALMAC_RET_SUCCESS; + } + + if (_TRUE == pHalmac_adapter->low_clk) { + cpwm = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1); + rpwm = (u8)(((pHalmac_adapter->rpwm_record ^ (BIT(7))) | (BIT(6))) & 0xC0); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SDIO_HRPWM1, rpwm); + + cpwm = (u8)((cpwm ^ BIT(7)) & BIT(7)); + counter = 100; + while (cpwm != (HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_HRPWM1) & BIT(7))) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + counter--; + if (0 == counter) + return HALMAC_RET_CHANGE_PS_FAIL; + } + pHalmac_adapter->low_clk = _FALSE; + } + + PLATFORM_RTL_MEMCPY(pDriver_adapter, &fw_lps_option, &(pHalmac_adapter->fwlps_option), sizeof(HALMAC_FWLPS_OPTION)); + fw_lps_option.mode = 0; + + status = halmac_send_h2c_set_pwr_mode_88xx(pHalmac_adapter, &(fw_lps_option)); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx error!!=%x\n", status); + return status; + } + + pHalmac_adapter->halmac_state.ps_state = HALMAC_PS_STATE_ACT; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_TRACE, "halmac_leave_ps_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * (debug API)halmac_h2c_lb_88xx() - send h2c loopback packet + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_h2c_lb_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_H2C_LB); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_h2c_lb_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_debug_88xx() - dump information for debugging + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_debug_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 temp8 = 0; + u32 i = 0, temp32 = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEBUG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx ==========>\n"); + + if (HALMAC_INTERFACE_SDIO == pHalmac_adapter->halmac_interface) { + /* Dump CCCR, it needs new platform api */ + + /*Dump SDIO Local Register, use CMD52*/ + for (i = 0x10250000; i < 0x102500ff; i++) { + temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: sdio[%x]=%x\n", i, temp8); + } + + /*Dump MAC Register*/ + for (i = 0x0000; i < 0x17ff; i++) { + temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); + } + + /*Check RX Fifo status*/ + i = REG_RXFF_PTR_V1; + temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); + i = REG_RXFF_WTR_V1; + temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); + i = REG_RXFF_PTR_V1; + temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); + i = REG_RXFF_WTR_V1; + temp8 = PLATFORM_SDIO_CMD52_READ(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp8); + } else { + /*Dump MAC Register*/ + for (i = 0x0000; i < 0x17fc; i += 4) { + temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); + } + + /*Check RX Fifo status*/ + i = REG_RXFF_PTR_V1; + temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); + i = REG_RXFF_WTR_V1; + temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); + i = REG_RXFF_PTR_V1; + temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); + i = REG_RXFF_WTR_V1; + temp32 = HALMAC_REG_READ_32(pHalmac_adapter, i); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug: mac[%x]=%x\n", i, temp32); + } + + /* TODO: Add check register code, including MAC CLK, CPU CLK */ + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_debug_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_parameter_88xx() - config parameter by FW + * @pHalmac_adapter : the adapter of halmac + * @para_info : cmd id, content + * @full_fifo : parameter information + * + * If msk_en = _TRUE, the format of array is {reg_info, mask, value}. + * If msk_en =_FAUSE, the format of array is {reg_info, value} + * The format of reg_info is + * reg_info[31]=rf_reg, 0: MAC_BB reg, 1: RF reg + * reg_info[27:24]=rf_path, 0: path_A, 1: path_B + * if rf_reg=0(MAC_BB reg), rf_path is meaningless. + * ref_info[15:0]=offset + * + * Example: msk_en = _FALSE + * {0x8100000a, 0x00001122} + * =>Set RF register, path_B, offset 0xA to 0x00001122 + * {0x00000824, 0x11224433} + * =>Set MAC_BB register, offset 0x800 to 0x11224433 + * + * Note : full fifo mode only for init flow + * + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_parameter_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PHY_PARAMETER_INFO para_info, + IN u8 full_fifo +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.cfg_para_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_PARAMETER); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx ==========>\n"); */ + + if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_cfg_parameter_88xx Fail due to DLFW NONE!!\n"); + return HALMAC_RET_DLFW_FAIL; + } + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(cfg para)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter)) && + (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_cfg_para_curr_state_88xx(pHalmac_adapter))) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Not idle state(cfg para)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + *pProcess_status = HALMAC_CMD_PROCESS_IDLE; + + ret_status = halmac_send_h2c_phy_parameter_88xx(pHalmac_adapter, para_info, full_fifo); + + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_phy_parameter_88xx Fail!! = %x\n", ret_status); + return ret_status; + } + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_parameter_88xx <==========\n"); */ + + return ret_status; +} + +/** + * halmac_update_packet_88xx() - send specific packet to FW + * @pHalmac_adapter : the adapter of halmac + * @pkt_id : packet id, to know the purpose of this packet + * @pkt : packet + * @pkt_size : packet size + * + * Note : TX_DESC is not included in the pkt + * + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_update_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PACKET_ID pkt_id, + IN u8 *pkt, + IN u32 pkt_size +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.update_packet_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_UPDATE_PACKET); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx ==========>\n"); + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(update_packet)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + *pProcess_status = HALMAC_CMD_PROCESS_SENDING; + + status = halmac_send_h2c_update_packet_88xx(pHalmac_adapter, pkt_id, pkt, pkt_size); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx packet = %x, fail = %x!!\n", pkt_id, status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_packet_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_bcn_ie_filter_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_BCN_IE_INFO pBcn_ie_info +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_BCN_IE_FILTER); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx ==========>\n"); + + status = halmac_send_h2c_update_bcn_parse_info_88xx(pHalmac_adapter, pBcn_ie_info); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_bcn_parse_info_88xx fail = %x\n", status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_bcn_ie_filter_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_update_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DATA_TYPE halmac_data_type, + IN PHALMAC_PHY_PARAMETER_INFO para_info +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx ==========>\n"); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_update_datapack_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_run_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DATA_TYPE halmac_data_type +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RUN_DATAPACK); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_run_datapack_88xx ==========>\n"); + + ret_status = halmac_send_h2c_run_datapack_88xx(pHalmac_adapter, halmac_data_type); + + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_run_datapack_88xx Fail, datatype = %x, status = %x!!\n", halmac_data_type, ret_status); + return ret_status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_update_datapack_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_drv_info_88xx() - config driver info + * @pHalmac_adapter : the adapter of halmac + * @halmac_drv_info : driver information selection + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_drv_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DRV_INFO halmac_drv_info +) +{ + u8 drv_info_size = 0; + u8 phy_status_en = 0; + u8 sniffer_en = 0; + u8 plcp_hdr_en = 0; + u32 value32; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_INFO); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info = %d\n", halmac_drv_info); + + switch (halmac_drv_info) { + case HALMAC_DRV_INFO_NONE: + drv_info_size = 0; + phy_status_en = 0; + sniffer_en = 0; + plcp_hdr_en = 0; + break; + case HALMAC_DRV_INFO_PHY_STATUS: + drv_info_size = 4; + phy_status_en = 1; + sniffer_en = 0; + plcp_hdr_en = 0; + break; + case HALMAC_DRV_INFO_PHY_SNIFFER: + drv_info_size = 5; /* phy status 4byte, sniffer info 1byte */ + phy_status_en = 1; + sniffer_en = 1; + plcp_hdr_en = 0; + break; + case HALMAC_DRV_INFO_PHY_PLCP: + drv_info_size = 6; /* phy status 4byte, plcp header 2byte */ + phy_status_en = 1; + sniffer_en = 0; + plcp_hdr_en = 1; + break; + default: + status = HALMAC_RET_SW_CASE_NOT_SUPPORT; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_cfg_drv_info_88xx error = %x\n", status); + return status; + } + + if (HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE != pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode) + drv_info_size = HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX >> 3; + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RX_DRVINFO_SZ, drv_info_size); + + pHalmac_adapter->drv_info_size = drv_info_size; + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_RCR); + value32 = (value32 & (~BIT_APP_PHYSTS)); + if (1 == phy_status_en) + value32 = value32 | BIT_APP_PHYSTS; + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_RCR, value32); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4); + value32 = (value32 & (~(BIT(8) | BIT(9)))); + if (1 == sniffer_en) + value32 = value32 | BIT(9); + if (1 == plcp_hdr_en) + value32 = value32 | BIT(8); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WMAC_OPTION_FUNCTION + 4, value32); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_info_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_send_bt_coex_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pBt_buf, + IN u32 bt_size, + IN u8 ack +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_BT_COEX); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx ==========>\n"); + + ret_status = halmac_send_bt_coex_cmd_88xx(pHalmac_adapter, pBt_buf, bt_size, ack); + + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_bt_coex_cmd_88xx Fail = %x!!\n", ret_status); + return ret_status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * (debug API)halmac_verify_platform_api_88xx() - verify platform api + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_verify_platform_api_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_VERIFY_PLATFORM_API); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx ==========>\n"); + + ret_status = halmac_verify_io_88xx(pHalmac_adapter); + + if (HALMAC_RET_SUCCESS != ret_status) + return ret_status; + + if (HALMAC_LA_MODE_FULL != pHalmac_adapter->txff_allocation.la_mode) + ret_status = halmac_verify_send_rsvd_page_88xx(pHalmac_adapter); + + if (HALMAC_RET_SUCCESS != ret_status) + return ret_status; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_verify_platform_api_88xx <==========\n"); + + return ret_status; +} + +HALMAC_RET_STATUS +halmac_timer_2s_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_timer_2s_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_fill_txdesc_check_sum_88xx() - fill in tx desc check sum + * @pHalmac_adapter : the adapter of halmac + * @pCur_desc : tx desc packet + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_fill_txdesc_check_sum_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + INOUT u8 *pCur_desc +) +{ + u16 chk_result = 0; + u16 *pData = (u16 *)NULL; + u32 i; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_FILL_TXDESC_CHECKSUM); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (NULL == pCur_desc) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fill_txdesc_check_sum_88xx NULL PTR"); + return HALMAC_RET_NULL_POINTER; + } + + SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, 0x0000); + + pData = (u16 *)(pCur_desc); + + /* HW clculates only 32byte */ + for (i = 0; i < 8; i++) + chk_result ^= (*(pData + 2 * i) ^ *(pData + (2 * i + 1))); + + /* *(pData + 2 * i) & *(pData + (2 * i + 1) have endain issue*/ + /* Process eniadn issue after checksum calculation */ + chk_result = rtk_le16_to_cpu(chk_result); + + SET_TX_DESC_TXDESC_CHECKSUM(pCur_desc, chk_result); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_dump_fifo_88xx() - dump fifo data + * @pHalmac_adapter : the adapter of halmac + * @halmac_fifo_sel : FIFO selection + * @halmac_start_addr : start address of selected FIFO + * @halmac_fifo_dump_size : dump size of selected FIFO + * @pFifo_map : FIFO data + * + * Note : before dump fifo, user need to call halmac_get_fifo_size to + * get fifo size. Then input this size to halmac_dump_fifo. + * + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_dump_fifo_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_FIFO_SEL halmac_fifo_sel, + IN u32 halmac_start_addr, + IN u32 halmac_fifo_dump_size, + OUT u8 *pFifo_map +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FIFO); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx ==========>\n"); + + if (HAL_FIFO_SEL_TX == halmac_fifo_sel && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.tx_fifo_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TX fifo dump size is too large\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if (HAL_FIFO_SEL_RX == halmac_fifo_sel && (halmac_start_addr + halmac_fifo_dump_size) > pHalmac_adapter->hw_config_info.rx_fifo_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "RX fifo dump size is too large\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if (0 != (halmac_fifo_dump_size & (4 - 1))) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_fifo_dump_size shall 4byte align\n"); + return HALMAC_RET_DUMP_FIFOSIZE_INCORRECT; + } + + if (NULL == pFifo_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "pFifo_map address is NULL\n"); + return HALMAC_RET_NULL_POINTER; + } + + status = halmac_buffer_read_88xx(pHalmac_adapter, halmac_start_addr, halmac_fifo_dump_size, halmac_fifo_sel, pFifo_map); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_buffer_read_88xx error = %x\n", status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dump_fifo_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_fifo_size_88xx() - get fifo size + * @pHalmac_adapter : the adapter of halmac + * @halmac_fifo_sel : FIFO selection + * Author : Ivan Lin/KaiYuan Chang + * Return : u32 + * More details of status code can be found in prototype document + */ +u32 +halmac_get_fifo_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_FIFO_SEL halmac_fifo_sel +) +{ + u32 fifo_size = 0; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_FIFO_SIZE); + + if (HAL_FIFO_SEL_TX == halmac_fifo_sel) + fifo_size = pHalmac_adapter->hw_config_info.tx_fifo_size; + else if (HAL_FIFO_SEL_RX == halmac_fifo_sel) + fifo_size = pHalmac_adapter->hw_config_info.rx_fifo_size; + else if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel) + fifo_size = ((pHalmac_adapter->hw_config_info.tx_fifo_size >> HALMAC_TX_PAGE_SIZE_2_POWER_88XX) + - pHalmac_adapter->txff_allocation.rsvd_pg_bndy) << HALMAC_TX_PAGE_SIZE_2_POWER_88XX; + else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel) + fifo_size = 65536; + else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel) + fifo_size = 65536; + + return fifo_size; +} + +/** + * halmac_cfg_txbf_88xx() - enable/disable specific user's txbf + * @pHalmac_adapter : the adapter of halmac + * @userid : su bfee userid = 0 or 1 to apply TXBF + * @bw : the sounding bandwidth + * @txbf_en : 0: disable TXBF, 1: enable TXBF + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_txbf_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid, + IN HALMAC_BW bw, + IN u8 txbf_en +) +{ + u16 temp42C = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TXBF); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (txbf_en) { + switch (bw) { + case HALMAC_BW_80: + temp42C |= BIT_R_TXBF0_80M; + case HALMAC_BW_40: + temp42C |= BIT_R_TXBF0_40M; + case HALMAC_BW_20: + temp42C |= BIT_R_TXBF0_20M; + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid TXBF BW setting 0x%x of userid %d\n", bw, userid); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + } + + switch (userid) { + case 0: + temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C); + break; + case 1: + temp42C |= HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_txbf_88xx invalid userid %d\n", userid); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_txbf_88xx, txbf_en = %x <==========\n", txbf_en); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_mumimo_88xx() -config mumimo + * @pHalmac_adapter : the adapter of halmac + * @pCfgmu : parameters to configure MU PPDU Tx/Rx + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_mumimo_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CFG_MUMIMO_PARA pCfgmu +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 i, idx, id0, id1, gid, mu_tab_sel; + u8 mu_tab_valid = 0; + u32 gid_valid[6] = {0}; + u8 temp14C0 = 0; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MUMIMO); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (pCfgmu->role == HAL_BFEE) { + /*config MU BFEE*/ + temp14C0 = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~BIT_MASK_R_MU_TABLE_VALID; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, (temp14C0|BIT(0)|BIT(1)) & ~(BIT(7))); /*enable MU table 0 and 1, disable MU TX*/ + + /*config GID valid table and user position table*/ + mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2)); + for (i = 0; i < 2; i++) { + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, mu_tab_sel | i); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, pCfgmu->given_gid_tab[i]); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pCfgmu->given_user_pos[i*2]); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pCfgmu->given_user_pos[i*2+1]); + } + } else { + /*config MU BFER*/ + if (_FALSE == pCfgmu->mu_tx_en) { + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(7))); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx disable mu tx <==========\n"); + return HALMAC_RET_SUCCESS; + } + + /*Transform BB grouping bitmap[14:0] to MAC GID_valid table*/ + for (idx = 0; idx < 15; idx++) { + if (idx < 5) { + /*grouping_bitmap bit0~4, MU_STA0 with MUSTA1~5*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { + /*grouping_bitmap bit5~8, MU_STA1 with MUSTA2~5*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { + /*grouping_bitmap bit9~11, MU_STA2 with MUSTA3~5*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { + /*grouping_bitmap bit12~13, MU_STA3 with MUSTA4~5*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { + /*grouping_bitmap bit14, MU_STA4 with MUSTA5*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + if (pCfgmu->grouping_bitmap & BIT(idx)) { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + } else { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + } + } + + /*set MU STA GID valid TABLE*/ + mu_tab_sel = HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL+1) & ~(BIT(0)|BIT(1)|BIT(2)); + for (idx = 0; idx < 6; idx++) { + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL+1, idx | mu_tab_sel); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, gid_valid[idx]); + } + + /*To validate the sounding successful MU STA and enable MU TX*/ + for (i = 0; i < 6; i++) { + if (_TRUE == pCfgmu->sounding_sts[i]) + mu_tab_valid |= BIT(i); + } + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, mu_tab_valid | BIT(7)); + } + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_mumimo_88xx <==========\n"); + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_sounding_88xx() - configure general sounding + * @pHalmac_adapter : the adapter of halmac + * @role : driver's role, BFer or BFee + * @datarate : set ndpa tx rate if driver is BFer, or set csi response rate if driver is BFee + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_sounding_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SND_ROLE role, + IN HALMAC_DATA_RATE datarate +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_SOUNDING); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (role) { + case HAL_BFER: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_TXBF_CTRL) | BIT_R_ENABLE_NDPA + | BIT_USE_NDPA_PARAMETER | BIT_R_EN_NDPA_INT | BIT_DIS_NDP_BFEN); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_RATE, datarate); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_NDPA_OPT_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_NDPA_OPT_CTRL) & (~(BIT(0) | BIT(1)))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 1, 0x2 | BIT(7)); /*service file length 2 bytes; fix non-STA1 csi start offset */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 2, 0x2); + break; + case HAL_BFEE: + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0xDB); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL + 3, 0x50); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BBPSF_CTRL + 3, HALMAC_OFDM54 | BIT(6)); //use ndpa rx rate to decide csi rate + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR) | BIT(datarate)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP1, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP1) & (~(BIT(4)))); /*RXFF do not accept BF Rpt Poll, avoid CSI crc error*/ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RXFLTMAP4, HALMAC_REG_READ_8(pHalmac_adapter, REG_RXFLTMAP4) & (~(BIT(4)))); /*FWFF do not accept BF Rpt Poll, avoid CSI crc error*/ + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_cfg_sounding_88xx invalid role\n"); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_sounding_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_del_sounding_88xx() - reset general sounding + * @pHalmac_adapter : the adapter of halmac + * @role : driver's role, BFer or BFee + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_del_sounding_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SND_ROLE role +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEL_SOUNDING); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (role) { + case HAL_BFER: + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_TXBF_CTRL + 3, 0); + break; + case HAL_BFEE: + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SND_PTCL_CTRL, 0); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_del_sounding_88xx invalid role\n"); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_del_sounding_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_su_bfee_entry_init_88xx() - config SU beamformee's registers + * @pHalmac_adapter : the adapter of halmac + * @userid : SU bfee userid = 0 or 1 to be added + * @paid : partial AID of this bfee + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_su_bfee_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid, + IN u16 paid +) +{ + u16 temp42C = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_INIT); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (userid) { + case 0: + temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, temp42C | paid); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, paid); + break; + case 1: + temp42C = HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, temp42C | paid); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, paid | BIT(9)); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_init_88xx invalid userid %d\n", userid); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_init_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_su_bfee_entry_init_88xx() - config SU beamformer's registers + * @pHalmac_adapter : the adapter of halmac + * @pSu_bfer_init : parameters to configure SU BFER entry + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_su_bfer_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init +) +{ + u16 mac_address_H; + u32 mac_address_L; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_INIT); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + /* mac_address_L = bfer_address.Address_L_H.Address_Low; */ + /* mac_address_H = bfer_address.Address_L_H.Address_High; */ + + mac_address_L = rtk_le32_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_Low); + mac_address_H = rtk_le16_to_cpu(pSu_bfer_init->bfer_address.Address_L_H.Address_High); + + switch (pSu_bfer_init->userid) { + case 0: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pSu_bfer_init->paid); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pSu_bfer_init->csi_para); + break; + case 1: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, mac_address_H); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 6, pSu_bfer_init->paid); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20 + 2, pSu_bfer_init->csi_para); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_init_88xx invalid userid %d\n", pSu_bfer_init->userid); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_init_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_mu_bfee_entry_init_88xx() - config MU beamformee's registers + * @pHalmac_adapter : the adapter of halmac + * @pMu_bfee_init : parameters to configure MU BFEE entry + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_mu_bfee_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init +) +{ + u16 temp168X = 0, temp14C0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_INIT); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + temp168X |= pMu_bfee_init->paid | BIT(9); + HALMAC_REG_WRITE_16(pHalmac_adapter, (0x1680 + pMu_bfee_init->userid * 2), temp168X); + + temp14C0 = HALMAC_REG_READ_16(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(8)|BIT(9)|BIT(10)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MU_TX_CTL, temp14C0|((pMu_bfee_init->userid-2)<<8)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_GID_VLD, 0); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO, pMu_bfee_init->user_position_l); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_MU_STA_USER_POS_INFO+4, pMu_bfee_init->user_position_h); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_init_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_mu_bfer_entry_init_88xx() - config MU beamformer's registers + * @pHalmac_adapter : the adapter of halmac + * @pMu_bfer_init : parameters to configure MU BFER entry + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_mu_bfer_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init +) +{ + u16 temp1680 = 0; + u16 mac_address_H; + u32 mac_address_L; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_INIT); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + /* mac_address_L = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_Low; */ + /* mac_address_H = pHalmac_adapter->snd_info.bfer_address.Address_L_H.Address_High; */ + + mac_address_L = rtk_le32_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_Low); + mac_address_H = rtk_le16_to_cpu(pMu_bfer_init->bfer_address.Address_L_H.Address_High); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, mac_address_L); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, mac_address_H); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 6, pMu_bfer_init->paid); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TX_CSI_RPT_PARAM_BW20, pMu_bfer_init->csi_para); + + temp1680 = HALMAC_REG_READ_16(pHalmac_adapter, 0x1680) & 0xC000; + temp1680 |= pMu_bfer_init->my_aid | (pMu_bfer_init->csi_length_sel << 12); + HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, temp1680); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_init_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_su_bfee_entry_del_88xx() - reset SU beamformee's registers + * @pHalmac_adapter : the adapter of halmac + * @userid : the SU BFee userid to be deleted + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_su_bfee_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFEE_ENTRY_DEL); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (userid) { + case 0: + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL) & + ~(BIT_MASK_R_TXBF0_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL, 0); + break; + case 1: + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_TXBF_CTRL + 2, HALMAC_REG_READ_16(pHalmac_adapter, REG_TXBF_CTRL + 2) & + ~(BIT_MASK_R_TXBF1_AID | BIT_R_TXBF0_20M | BIT_R_TXBF0_40M | BIT_R_TXBF0_80M)); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_ASSOCIATED_BFMEE_SEL + 2, 0); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfee_entry_del_88xx invalid userid %d\n", userid); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfee_entry_del_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_su_bfee_entry_del_88xx() - reset SU beamformer's registers + * @pHalmac_adapter : the adapter of halmac + * @userid : the SU BFer userid to be deleted + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_su_bfer_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SU_BFER_ENTRY_DEL); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (userid) { + case 0: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0); + break; + case 1: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO, 0); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER1_INFO + 4, 0); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_su_bfer_entry_del_88xx invalid userid %d\n", userid); + return HALMAC_RET_INVALID_SOUNDING_SETTING; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_su_bfer_entry_del_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_mu_bfee_entry_del_88xx() - reset MU beamformee's registers + * @pHalmac_adapter : the adapter of halmac + * @userid : the MU STA userid to be deleted + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_mu_bfee_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFEE_ENTRY_DEL); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680 + userid * 2, 0); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, HALMAC_REG_READ_8(pHalmac_adapter, REG_MU_TX_CTL) & ~(BIT(userid-2))); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfee_entry_del_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_mu_bfer_entry_del_88xx() -reset MU beamformer's registers + * @pHalmac_adapter : the adapter of halmac + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_mu_bfer_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_MU_BFER_ENTRY_DEL); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO, 0); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_ASSOCIATED_BFMER0_INFO + 4, 0); + HALMAC_REG_WRITE_16(pHalmac_adapter, 0x1680, 0); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MU_TX_CTL, 0); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_mu_bfer_entry_del_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_add_ch_info_88xx() -add channel information + * @pHalmac_adapter : the adapter of halmac + * @pCh_info : channel information + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_add_ch_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_INFO pCh_info +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_CS_INFO pCh_sw_info; + HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pCh_sw_info = &(pHalmac_adapter->ch_sw_info); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx ==========>\n"); + + if (HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: gen_info is not send to FW!!!!\n"); + return HALMAC_RET_GEN_INFO_NOT_SENT; + } + + state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter); + if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) && (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "[WARN]Scan machine fail(add ch info)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (NULL == pCh_sw_info->ch_info_buf) { + pCh_sw_info->ch_info_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, HALMAC_EXTRA_INFO_BUFF_SIZE_88XX); + if (NULL == pCh_sw_info->ch_info_buf) + return HALMAC_RET_NULL_POINTER; + pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf; + pCh_sw_info->buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; + pCh_sw_info->avai_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; + pCh_sw_info->total_size = 0; + pCh_sw_info->extra_info_en = 0; + pCh_sw_info->ch_num = 0; + } + + if (1 == pCh_sw_info->extra_info_en) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: construct sequence wrong!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (4 > pCh_sw_info->avai_buf_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_add_ch_info_88xx: no available buffer!!\n"); + return HALMAC_RET_CH_SW_NO_BUF; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) + return HALMAC_RET_ERROR_STATE; + + CHANNEL_INFO_SET_CHANNEL(pCh_sw_info->ch_info_buf_w, pCh_info->channel); + CHANNEL_INFO_SET_PRI_CH_IDX(pCh_sw_info->ch_info_buf_w, pCh_info->pri_ch_idx); + CHANNEL_INFO_SET_BANDWIDTH(pCh_sw_info->ch_info_buf_w, pCh_info->bw); + CHANNEL_INFO_SET_TIMEOUT(pCh_sw_info->ch_info_buf_w, pCh_info->timeout); + CHANNEL_INFO_SET_ACTION_ID(pCh_sw_info->ch_info_buf_w, pCh_info->action_id); + CHANNEL_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_info->extra_info); + + pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - 4; + pCh_sw_info->total_size = pCh_sw_info->total_size + 4; + pCh_sw_info->ch_num++; + pCh_sw_info->extra_info_en = pCh_info->extra_info; + pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + 4; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_add_ch_info_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_add_extra_ch_info_88xx() -add extra channel information + * @pHalmac_adapter : the adapter of halmac + * @pCh_extra_info : extra channel information + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_add_extra_ch_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_EXTRA_INFO pCh_extra_info +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_CS_INFO pCh_sw_info; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_ADD_EXTRA_CH_INFO); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pCh_sw_info = &(pHalmac_adapter->ch_sw_info); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx ==========>\n"); + + if (NULL == pCh_sw_info->ch_info_buf) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: NULL==pCh_sw_info->ch_info_buf!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (0 == pCh_sw_info->extra_info_en) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: construct sequence wrong!!\n"); + return HALMAC_RET_CH_SW_SEQ_WRONG; + } + + if (pCh_sw_info->avai_buf_size < (u32)(pCh_extra_info->extra_info_size + 2)) {/* 2:ch_extra_info_id, ch_extra_info, ch_extra_info_size are totally 2Byte */ + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_add_extra_ch_info_88xx: no available buffer!!\n"); + return HALMAC_RET_CH_SW_NO_BUF; + } + + if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != halmac_query_scan_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(add extra ch info)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING)) + return HALMAC_RET_ERROR_STATE; + + CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_action_id); + CH_EXTRA_INFO_SET_CH_EXTRA_INFO(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info); + CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(pCh_sw_info->ch_info_buf_w, pCh_extra_info->extra_info_size); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pCh_sw_info->ch_info_buf_w + 2, pCh_extra_info->extra_info_data, pCh_extra_info->extra_info_size); + + pCh_sw_info->avai_buf_size = pCh_sw_info->avai_buf_size - (2 + pCh_extra_info->extra_info_size); + pCh_sw_info->total_size = pCh_sw_info->total_size + (2 + pCh_extra_info->extra_info_size); + pCh_sw_info->extra_info_en = pCh_extra_info->extra_info; + pCh_sw_info->ch_info_buf_w = pCh_sw_info->ch_info_buf_w + (2 + pCh_extra_info->extra_info_size); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_add_extra_ch_info_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_ctrl_ch_switch_88xx() -send channel switch cmd + * @pHalmac_adapter : the adapter of halmac + * @pCs_option : channel switch config + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_ctrl_ch_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_SWITCH_OPTION pCs_option +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_SCAN_CMD_CONSTRUCT_STATE state_scan; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_CH_SWITCH); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx pCs_option->switch_en = %d==========>\n", pCs_option->switch_en); + + if (_FALSE == pCs_option->switch_en) + *pProcess_status = HALMAC_CMD_PROCESS_IDLE; + + if ((HALMAC_CMD_PROCESS_SENDING == *pProcess_status) || (HALMAC_CMD_PROCESS_RCVD == *pProcess_status)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(ctrl ch switch)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + state_scan = halmac_query_scan_curr_state_88xx(pHalmac_adapter); + if (_TRUE == pCs_option->switch_en) { + if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != state_scan) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(on) invalid in state %x\n", state_scan); + return HALMAC_RET_ERROR_STATE; + } + } else { + if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != state_scan) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx(off) invalid in state %x\n", state_scan); + return HALMAC_RET_ERROR_STATE; + } + } + + status = halmac_func_ctrl_ch_switch_88xx(pHalmac_adapter, pCs_option); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_ctrl_ch_switch FAIL = %x!!\n", status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_clear_ch_info_88xx() -clear channel information + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_clear_ch_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CLEAR_CH_INFO); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx ==========>\n"); + + if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == halmac_query_scan_curr_state_88xx(pHalmac_adapter)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Scan machine fail(clear ch info)...\n"); + return HALMAC_RET_ERROR_STATE; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED)) + return HALMAC_RET_ERROR_STATE; + + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size); + pHalmac_adapter->ch_sw_info.ch_info_buf = NULL; + pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL; + pHalmac_adapter->ch_sw_info.extra_info_en = 0; + pHalmac_adapter->ch_sw_info.buf_size = 0; + pHalmac_adapter->ch_sw_info.avai_buf_size = 0; + pHalmac_adapter->ch_sw_info.total_size = 0; + pHalmac_adapter->ch_sw_info.ch_num = 0; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_clear_ch_info_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +static HALMAC_RET_STATUS +halmac_func_p2pps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_P2PPS pP2PPS +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]halmac_p2pps !!\n"); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + P2PPS_SET_OFFLOAD_EN(pH2c_buff, pP2PPS->offload_en); + P2PPS_SET_ROLE(pH2c_buff, pP2PPS->role); + P2PPS_SET_CTWINDOW_EN(pH2c_buff, pP2PPS->ctwindow_en); + P2PPS_SET_NOA_EN(pH2c_buff, pP2PPS->noa_en); + P2PPS_SET_NOA_SEL(pH2c_buff, pP2PPS->noa_sel); + P2PPS_SET_ALLSTASLEEP(pH2c_buff, pP2PPS->all_sta_sleep); + P2PPS_SET_DISCOVERY(pH2c_buff, pP2PPS->discovery); + P2PPS_SET_P2P_PORT_ID(pH2c_buff, pP2PPS->p2p_port_id); + P2PPS_SET_P2P_GROUP(pH2c_buff, pP2PPS->p2p_group); + P2PPS_SET_P2P_MACID(pH2c_buff, pP2PPS->p2p_macid); + + P2PPS_SET_CTWINDOW_LENGTH(pH2c_buff, pP2PPS->ctwindow_length); + + P2PPS_SET_NOA_DURATION_PARA(pH2c_buff, pP2PPS->noa_duration_para); + P2PPS_SET_NOA_INTERVAL_PARA(pH2c_buff, pP2PPS->noa_interval_para); + P2PPS_SET_NOA_START_TIME_PARA(pH2c_buff, pP2PPS->noa_start_time_para); + P2PPS_SET_NOA_COUNT_PARA(pH2c_buff, pP2PPS->noa_count_para); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_P2PPS; + h2c_header_info.content_size = 24; + h2c_header_info.ack = _FALSE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _FALSE); + + if (HALMAC_RET_SUCCESS != status) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_send_h2c_p2pps_88xx Fail = %x!!\n", status); + + return status; +} + +HALMAC_RET_STATUS +halmac_p2pps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_P2PPS pP2PPS +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 6) + return HALMAC_RET_FW_NO_SUPPORT; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + status = halmac_func_p2pps_88xx(pHalmac_adapter, pP2PPS); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]halmac_p2pps FAIL = %x!!\n", status); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_send_general_info_88xx() -send general information to FW + * @pHalmac_adapter : the adapter of halmac + * @pGeneral_info : general information + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_send_general_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_GENERAL_INFO pGeneral_info +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + if (pHalmac_adapter->fw_version.h2c_version < 4) + return HALMAC_RET_FW_NO_SUPPORT; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_SEND_GENERAL_INFO); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx ==========>\n"); + + if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_general_info_88xx Fail due to DLFW NONE!!\n"); + return HALMAC_RET_DLFW_FAIL; + } + + status = halmac_func_send_general_info_88xx(pHalmac_adapter, pGeneral_info); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_general_info error = %x\n", status); + return status; + } + + if (HALMAC_DLFW_DONE == pHalmac_adapter->halmac_state.dlfw_state) + pHalmac_adapter->halmac_state.dlfw_state = HALMAC_GEN_INFO_SENT; + + pHalmac_adapter->gen_info_valid = _TRUE; + PLATFORM_RTL_MEMCPY(pDriver_adapter, &(pHalmac_adapter->general_info), pGeneral_info, sizeof(HALMAC_GENERAL_INFO)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_start_iqk_88xx() -trigger FW IQK + * @pHalmac_adapter : the adapter of halmac + * @pIqk_para : IQK parameter + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_start_iqk_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_IQK_PARA pIqk_para +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_num = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.iqk_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_START_IQK); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n"); + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(iqk)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + *pProcess_status = HALMAC_CMD_PROCESS_SENDING; + + IQK_SET_CLEAR(pH2c_buff, pIqk_para->clear); + IQK_SET_SEGMENT_IQK(pH2c_buff, pIqk_para->segment_iqk); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_IQK; + h2c_header_info.content_size = 1; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_num); + + pHalmac_adapter->halmac_state.iqk_set.seq_num = h2c_seq_num; + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_ctrl_pwr_tracking_88xx() -trigger FW power tracking + * @pHalmac_adapter : the adapter of halmac + * @pPwr_tracking_opt : power tracking option + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_ctrl_pwr_tracking_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.power_tracking_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CTRL_PWR_TRACKING); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx ==========>\n"); + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(pwr tracking)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + *pProcess_status = HALMAC_CMD_PROCESS_SENDING; + + POWER_TRACKING_SET_TYPE(pH2c_buff, pPwr_tracking_opt->type); + POWER_TRACKING_SET_BBSWING_INDEX(pH2c_buff, pPwr_tracking_opt->bbswing_index); + POWER_TRACKING_SET_ENABLE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].enable); + POWER_TRACKING_SET_TX_PWR_INDEX_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tx_pwr_index); + POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].pwr_tracking_offset_value); + POWER_TRACKING_SET_TSSI_VALUE_A(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_A].tssi_value); + POWER_TRACKING_SET_ENABLE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].enable); + POWER_TRACKING_SET_TX_PWR_INDEX_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tx_pwr_index); + POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].pwr_tracking_offset_value); + POWER_TRACKING_SET_TSSI_VALUE_B(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_B].tssi_value); + POWER_TRACKING_SET_ENABLE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].enable); + POWER_TRACKING_SET_TX_PWR_INDEX_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tx_pwr_index); + POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].pwr_tracking_offset_value); + POWER_TRACKING_SET_TSSI_VALUE_C(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_C].tssi_value); + POWER_TRACKING_SET_ENABLE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].enable); + POWER_TRACKING_SET_TX_PWR_INDEX_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tx_pwr_index); + POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].pwr_tracking_offset_value); + POWER_TRACKING_SET_TSSI_VALUE_D(pH2c_buff, pPwr_tracking_opt->pwr_tracking_para[HALMAC_RF_PATH_D].tssi_value); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_POWER_TRACKING; + h2c_header_info.content_size = 20; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + pHalmac_adapter->halmac_state.power_tracking_set.seq_num = h2c_seq_mum; + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_start_iqk_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_query_status_88xx() -query the offload feature status + * @pHalmac_adapter : the adapter of halmac + * @feature_id : feature_id + * @pProcess_status : feature_status + * @data : data buffer + * @size : data size + * + * Note : + * If user wants to know the data size, use can allocate zero + * size buffer first. If this size less than the data size, halmac + * will return HALMAC_RET_BUFFER_TOO_SMALL. User need to + * re-allocate data buffer with correct data size. + * + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_query_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_FEATURE_ID feature_id, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_QUERY_STATE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx ==========>\n"); */ + + if (NULL == pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "null pointer!!\n"); + return HALMAC_RET_NULL_POINTER; + } + + switch (feature_id) { + case HALMAC_FEATURE_CFG_PARA: + status = halmac_query_cfg_para_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: + status = halmac_query_dump_physical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: + status = halmac_query_dump_logical_efuse_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + case HALMAC_FEATURE_CHANNEL_SWITCH: + status = halmac_query_channel_switch_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + case HALMAC_FEATURE_UPDATE_PACKET: + status = halmac_query_update_packet_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + case HALMAC_FEATURE_IQK: + status = halmac_query_iqk_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + case HALMAC_FEATURE_POWER_TRACKING: + status = halmac_query_power_tracking_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + case HALMAC_FEATURE_PSD: + status = halmac_query_psd_status_88xx(pHalmac_adapter, pProcess_status, data, size); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_query_status_88xx invalid feature id %d\n", feature_id); + return HALMAC_RET_INVALID_FEATURE_ID; + } + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_query_status_88xx <==========\n"); */ + + return status; +} + +/** + * halmac_reset_feature_88xx() -reset async api cmd status + * @pHalmac_adapter : the adapter of halmac + * @feature_id : feature_id + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS. + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_reset_feature_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_FEATURE_ID feature_id +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_RESET_FEATURE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx ==========>\n"); + + switch (feature_id) { + case HALMAC_FEATURE_CFG_PARA: + pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; + break; + case HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE: + case HALMAC_FEATURE_DUMP_LOGICAL_EFUSE: + pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; + break; + case HALMAC_FEATURE_CHANNEL_SWITCH: + pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; + break; + case HALMAC_FEATURE_UPDATE_PACKET: + pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; + break; + case HALMAC_FEATURE_ALL: + pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; + pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; + pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; + pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_ERR, "halmac_reset_feature_88xx invalid feature id %d\n", feature_id); + return HALMAC_RET_INVALID_FEATURE_ID; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_reset_feature_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_check_fw_status_88xx() -check fw status + * @pHalmac_adapter : the adapter of halmac + * @fw_status : fw status + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_check_fw_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u8 *fw_status +) +{ + u32 value32 = 0, value32_backup = 0, i = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CHECK_FW_STATUS); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx ==========>\n"); + + value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG6); + + if (0 != value32) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status REG_FW_DBG6 !=0\n"); + *fw_status = _FALSE; + return status; + } + + value32_backup = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7); + + for (i = 0; i <= 10; i++) { + value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_FW_DBG7); + if (value32_backup != value32) { + break; + } else { + if (10 == i) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_check_fw_status Polling FW PC fail\n"); + *fw_status = _FALSE; + return status; + } + } + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_check_fw_status_88xx <==========\n"); + + return status; +} + +HALMAC_RET_STATUS +halmac_dump_fw_dmem_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + INOUT u8 *dmem, + INOUT u32 *size +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DUMP_FW_DMEM); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_dump_fw_dmem_88xx <==========\n"); + + return status; +} + +/** + * halmac_cfg_max_dl_size_88xx() - config max download FW size + * @pHalmac_adapter : the adapter of halmac + * @size : max download fw size + * + * Halmac uses this setting to set max packet size for + * download FW. + * If user has not called this API, halmac use default + * setting for download FW + * Note1 : size need multiple of 2 + * Note2 : max size is 31K + * + * Author : Ivan Lin/KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_max_dl_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 size +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_MAX_DL_SIZE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx ==========>\n"); + + if (size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX_88XX) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size > HALMAC_FW_CFG_MAX_DL_SIZE_MAX!\n"); + return HALMAC_RET_CFG_DLFW_SIZE_FAIL; + } + + if (0 != (size & (2 - 1))) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "size is not power of 2!\n"); + return HALMAC_RET_CFG_DLFW_SIZE_FAIL; + } + + pHalmac_adapter->max_download_size = size; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "Cfg max size is : %X\n", size); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_TRACE, "halmac_cfg_max_dl_size_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_psd_88xx() - trigger fw psd + * @pHalmac_adapter : the adapter of halmac + * @start_psd : start PSD + * @end_psd : end PSD + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_psd_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 start_psd, + IN u16 end_psd +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.psd_set.process_status); + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_fw_validate(pHalmac_adapter)) + return HALMAC_RET_NO_DLFW; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_PSD); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx ==========>\n"); + + if (HALMAC_CMD_PROCESS_SENDING == *pProcess_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Wait event(psd)...\n"); + return HALMAC_RET_BUSY_STATE; + } + + if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) { + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size); + pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL; + } + + pHalmac_adapter->halmac_state.psd_set.data_size = 0; + pHalmac_adapter->halmac_state.psd_set.segment_size = 0; + + *pProcess_status = HALMAC_CMD_PROCESS_SENDING; + + PSD_SET_START_PSD(pH2c_buff, start_psd); + PSD_SET_END_PSD(pH2c_buff, end_psd); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_PSD; + h2c_header_info.content_size = 4; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_psd_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_la_mode_88xx() - config la mode + * @pHalmac_adapter : the adapter of halmac + * @la_mode : + * disable : no TXFF space reserved for LA debug + * partial : partial TXFF space is reserved for LA debug + * full : all TXFF space is reserved for LA debug + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_la_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_LA_MODE la_mode +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_LA_MODE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx ==========>la_mode = %d\n", la_mode); + + pHalmac_adapter->txff_allocation.la_mode = la_mode; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_la_mode_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} +/** + * halmac_cfg_rx_fifo_expanding_mode_88xx() - rx fifo expanding + * @pHalmac_adapter : the adapter of halmac + * @la_mode : + * disable : normal mode + * 1 block : Rx FIFO + 1 FIFO block; Tx fifo - 1 FIFO block + * 2 block : Rx FIFO + 2 FIFO block; Tx fifo - 2 FIFO block + * 3 block : Rx FIFO + 3 FIFO block; Tx fifo - 3 FIFO block + * Author : Soar + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_rx_fifo_expanding_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx ==========>rx_fifo_expanding_mode = %d\n", rx_fifo_expanding_mode); + + pHalmac_adapter->txff_allocation.rx_fifo_expanding_mode = rx_fifo_expanding_mode; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_rx_fifo_expanding_mode_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_config_security_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_SECURITY_SETTING pSec_setting +) +{ + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx ==========>\n"); + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_CR, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_CR) | BIT_MAC_SEC_EN)); + + if (1 == pSec_setting->tx_encryption) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(2)); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(2))); + + if (1 == pSec_setting->rx_decryption) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) | BIT(3)); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SECCFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_SECCFG) & ~(BIT(3))); + + if (1 == pSec_setting->bip_enable) { + if (HALMAC_CHIP_ID_8822B == pHalmac_adapter->chip_id) + return HALMAC_RET_BIP_NO_SUPPORT; + if (1 == pSec_setting->tx_encryption) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(3) | BIT(5))); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(3) | BIT(5))); + + if (1 == pSec_setting->rx_decryption) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) | (BIT(4) | BIT(6))); + else + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_WSEC_OPTION + 2, HALMAC_REG_READ_8(pHalmac_adapter, REG_WSEC_OPTION + 2) & ~(BIT(4) | BIT(6))); + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_config_security_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +u8 +halmac_get_used_cam_entry_num_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_SECURITY_TYPE sec_type +) +{ + u8 entry_num; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx ==========>\n"); + + switch (sec_type) { + case HAL_SECURITY_TYPE_WEP40: + case HAL_SECURITY_TYPE_WEP104: + case HAL_SECURITY_TYPE_TKIP: + case HAL_SECURITY_TYPE_AES128: + case HAL_SECURITY_TYPE_GCMP128: + case HAL_SECURITY_TYPE_GCMSMS4: + case HAL_SECURITY_TYPE_BIP: + entry_num = 1; + break; + case HAL_SECURITY_TYPE_WAPI: + case HAL_SECURITY_TYPE_AES256: + case HAL_SECURITY_TYPE_GCMP256: + entry_num = 2; + break; + default: + entry_num = 0; + break; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_get_used_cam_entry_num_88xx <==========\n"); + + return entry_num; +} + +HALMAC_RET_STATUS +halmac_write_cam_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info +) +{ + u32 i; + u32 command = 0x80010000; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx ==========>\n"); + + if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + if (pCam_entry_info->key_id > 3) + return HALMAC_RET_FAIL; + + pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format)); + if (NULL == pCam_entry_format) + return HALMAC_RET_NULL_POINTER; + PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format)); + + pCam_entry_format->key_id = pCam_entry_info->key_id; + pCam_entry_format->valid = pCam_entry_info->valid; + PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->mac_address, pCam_entry_info->mac_address, 6); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key, 16); + + switch (pCam_entry_info->security_type) { + case HAL_SECURITY_TYPE_NONE: + pCam_entry_format->type = 0; + break; + case HAL_SECURITY_TYPE_WEP40: + pCam_entry_format->type = 1; + break; + case HAL_SECURITY_TYPE_WEP104: + pCam_entry_format->type = 5; + break; + case HAL_SECURITY_TYPE_TKIP: + pCam_entry_format->type = 2; + break; + case HAL_SECURITY_TYPE_AES128: + pCam_entry_format->type = 4; + break; + case HAL_SECURITY_TYPE_WAPI: + pCam_entry_format->type = 6; + break; + case HAL_SECURITY_TYPE_AES256: + pCam_entry_format->type = 4; + pCam_entry_format->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_GCMP128: + pCam_entry_format->type = 7; + break; + case HAL_SECURITY_TYPE_GCMP256: + case HAL_SECURITY_TYPE_GCMSMS4: + pCam_entry_format->type = 7; + pCam_entry_format->ext_sectype = 1; + break; + case HAL_SECURITY_TYPE_BIP: + pCam_entry_format->type = (1 == pCam_entry_info->unicast) ? 4 : 0; + pCam_entry_format->mgnt = 1; + pCam_entry_format->grp = (1 == pCam_entry_info->unicast) ? 0 : 1; + break; + default: + PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); + return HALMAC_RET_FAIL; + } + + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]1 - REG_CAMCMD : %X\n", command | ((entry_index << 3) + i)); + } + + if (HAL_SECURITY_TYPE_WAPI == pCam_entry_info->security_type || HAL_SECURITY_TYPE_AES256 == pCam_entry_info->security_type || + HAL_SECURITY_TYPE_GCMP256 == pCam_entry_info->security_type || HAL_SECURITY_TYPE_GCMSMS4 == pCam_entry_info->security_type) { + pCam_entry_format->mic = 1; + PLATFORM_RTL_MEMCPY(pDriver_adapter, pCam_entry_format->key, pCam_entry_info->key_ext, 16); + + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | (((entry_index + 1) << 3) + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - CAM entry format : %X\n", *((u32 *)pCam_entry_format + i)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]2 - REG_CAMCMD : %X\n", command | (((entry_index + 1) << 3) + i)); + } + } + + PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "[TRACE]halmac_write_cam_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_read_cam_entry_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + OUT PHALMAC_CAM_ENTRY_FORMAT pContent +) +{ + u32 i; + u32 command = 0x80000000; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx ==========>\n"); + + if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); + *((u32 *)pContent + i) = HALMAC_REG_READ_32(pHalmac_adapter, REG_CAMREAD); + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_read_cam_entry_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_clear_cam_entry_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index +) +{ + u32 i; + u32 command = 0x80010000; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + PHALMAC_CAM_ENTRY_FORMAT pCam_entry_format; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx ==========>\n"); + + if (entry_index >= pHalmac_adapter->hw_config_info.cam_entry_num) + return HALMAC_RET_ENTRY_INDEX_ERROR; + + pCam_entry_format = (PHALMAC_CAM_ENTRY_FORMAT)PLATFORM_RTL_MALLOC(pDriver_adapter, sizeof(*pCam_entry_format)); + if (NULL == pCam_entry_format) + return HALMAC_RET_NULL_POINTER; + PLATFORM_RTL_MEMSET(pDriver_adapter, pCam_entry_format, 0x00, sizeof(*pCam_entry_format)); + + for (i = 0; i < 8; i++) { + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMWRITE, *((u32 *)pCam_entry_format + i)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_CAMCMD, command | ((entry_index << 3) + i)); + } + + PLATFORM_RTL_FREE(pDriver_adapter, pCam_entry_format, sizeof(*pCam_entry_format)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_clear_security_cam_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_hw_value_88xx() -get hw config value + * @pHalmac_adapter : the adapter of halmac + * @hw_id : hw id for driver to query + * @pvalue : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_hw_value_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_HW_ID hw_id, + OUT VOID *pvalue +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx ==========>\n"); + + if (NULL == pvalue) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_get_hw_value_88xx (NULL ==pvalue)==========>\n"); + return HALMAC_RET_NULL_POINTER; + } + + switch (hw_id) { + case HALMAC_HW_RQPN_MAPPING: + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_vo = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_vi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_be = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_bk = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_mg = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG]; + ((PHALMAC_RQPN_MAP)pvalue)->dma_map_hi = pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI]; + break; + case HALMAC_HW_EFUSE_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size; + break; + case HALMAC_HW_EEPROM_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.eeprom_size; + break; + case HALMAC_HW_BT_BANK_EFUSE_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.bt_efuse_size; + break; + case HALMAC_HW_BT_BANK1_EFUSE_SIZE: + case HALMAC_HW_BT_BANK2_EFUSE_SIZE: + *(u32 *)pvalue = 0; + break; + case HALMAC_HW_TXFIFO_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.tx_fifo_size; + break; + case HALMAC_HW_RSVD_PG_BNDY: + *(u16 *)pvalue = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy; + break; + case HALMAC_HW_CAM_ENTRY_NUM: + *(u8 *)pvalue = pHalmac_adapter->hw_config_info.cam_entry_num; + break; + case HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE: /*Remove later*/ + status = halmac_dump_logical_efuse_map_88xx(pHalmac_adapter, HALMAC_EFUSE_R_DRV); + if (HALMAC_RET_SUCCESS != status) + return status; + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - pHalmac_adapter->efuse_end; + break; + case HALMAC_HW_IC_VERSION: + *(u8 *)pvalue = pHalmac_adapter->chip_version; + break; + case HALMAC_HW_PAGE_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.page_size; + break; + case HALMAC_HW_TX_AGG_ALIGN_SIZE: + *(u16 *)pvalue = pHalmac_adapter->hw_config_info.tx_align_size; + break; + case HALMAC_HW_RX_AGG_ALIGN_SIZE: + *(u8 *)pvalue = 8; + break; + case HALMAC_HW_DRV_INFO_SIZE: + *(u8 *)pvalue = pHalmac_adapter->drv_info_size; + break; + case HALMAC_HW_TXFF_ALLOCATION: + PLATFORM_RTL_MEMCPY(pDriver_adapter, pvalue, &(pHalmac_adapter->txff_allocation), sizeof(HALMAC_TXFF_ALLOCATION)); + break; + case HALMAC_HW_TX_DESC_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.txdesc_size; + break; + case HALMAC_HW_RX_DESC_SIZE: + *(u32 *)pvalue = pHalmac_adapter->hw_config_info.rxdesc_size; + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_hw_value_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_set_hw_value_88xx() -set hw config value + * @pHalmac_adapter : the adapter of halmac + * @hw_id : hw id for driver to config + * @pvalue : hw value, reference table to get data type + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_set_hw_value_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_HW_ID hw_id, + IN VOID *pvalue +) +{ + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_GET_HW_VALUE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx ==========>\n"); + + if (NULL == pvalue) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_set_hw_value_88xx (NULL == pvalue)==========>\n"); + return HALMAC_RET_NULL_POINTER; + } + + switch (hw_id) { + case HALMAC_HW_USB_MODE: + status = halmac_set_usb_mode_88xx(pHalmac_adapter, *(HALMAC_USB_MODE *)pvalue); + if (HALMAC_RET_SUCCESS != status) + return status; + break; + case HALMAC_HW_SEQ_EN: + /*if (_TRUE == hw_seq_en) { + } else { + }*/ + break; + case HALMAC_HW_BANDWIDTH: + halmac_cfg_bw_88xx(pHalmac_adapter, *(HALMAC_BW *)pvalue); + break; + case HALMAC_HW_CHANNEL: + halmac_cfg_ch_88xx(pHalmac_adapter, *(u8 *)pvalue); + break; + case HALMAC_HW_PRI_CHANNEL_IDX: + halmac_cfg_pri_ch_idx_88xx(pHalmac_adapter, *(HALMAC_PRI_CH_IDX *)pvalue); + break; + case HALMAC_HW_EN_BB_RF: + halmac_enable_bb_rf_88xx(pHalmac_adapter, *(u8 *)pvalue); + break; + case HALMAC_HW_SDIO_TX_PAGE_THRESHOLD: + halmac_config_sdio_tx_page_threshold_88xx(pHalmac_adapter, (PHALMAC_TX_PAGE_THRESHOLD_INFO)pvalue); + break; + case HALMAC_HW_AMPDU_CONFIG: + halmac_config_ampdu_88xx(pHalmac_adapter, (PHALMAC_AMPDU_CONFIG)pvalue); + break; + default: + return HALMAC_RET_PARA_NOT_SUPPORT; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_hw_value_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_drv_rsvd_pg_num_88xx() -config reserved page number for driver + * @pHalmac_adapter : the adapter of halmac + * @pg_num : page number + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_drv_rsvd_pg_num_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DRV_RSVD_PG_NUM pg_num +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_DRV_RSVD_PG_NUM); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx ==========>pg_num = %d\n", pg_num); + + switch (pg_num) { + case HALMAC_RSVD_PG_NUM16: + pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 16; + break; + case HALMAC_RSVD_PG_NUM24: + pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 24; + break; + case HALMAC_RSVD_PG_NUM32: + pHalmac_adapter->txff_allocation.rsvd_drv_pg_num = 32; + break; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_cfg_drv_rsvd_pg_num_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_get_chip_version_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_VER pVersion +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx ==========>\n"); + pVersion->major_ver = (u8)HALMAC_MAJOR_VER_88XX; + pVersion->prototype_ver = (u8)HALMAC_PROTOTYPE_VER_88XX; + pVersion->minor_ver = (u8)HALMAC_MINOR_VER_88XX; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_get_chip_version_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_chk_txdesc_88xx() -check if the tx packet format is incorrect + * @pHalmac_adapter : the adapter of halmac + * @halmac_buf : tx Packet buffer, tx desc is included + * @halmac_size : tx packet size + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_chk_txdesc_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_buf, + IN u32 halmac_size +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_chk_txdesc_88xx ==========>\n"); + + if (_TRUE == GET_TX_DESC_BMC(pHalmac_buf)) + if (_TRUE == GET_TX_DESC_AGG_EN(pHalmac_buf)) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: Agg should not be set when BMC\n"); + + if (halmac_size < (GET_TX_DESC_TXPKTSIZE(pHalmac_buf) + GET_TX_DESC_OFFSET(pHalmac_buf))) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "TxDesc: PktSize too small\n"); + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_WARN, "halmac_chk_txdesc_88xx <==========\n"); */ + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_dl_drv_rsvd_page_88xx() - download packet to rsvd page + * @pHalmac_adapter : the adapter of halmac + * @pg_offset : page offset of driver's rsvd page + * @halmac_buf : data to be downloaded, tx_desc is not included + * @halmac_size : data size to be downloaded + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_dl_drv_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 pg_offset, + IN u8 *pHalmac_buf, + IN u32 halmac_size +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS ret_status; + u16 drv_pg_bndy = 0; + u32 dl_pg_num = 0; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DL_DRV_RSVD_PG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx ==========>\n"); + + /*check boundary and size valid*/ + dl_pg_num = halmac_size/pHalmac_adapter->hw_config_info.page_size + ((halmac_size & (pHalmac_adapter->hw_config_info.page_size - 1)) ? 1 : 0); + if (pg_offset + dl_pg_num > pHalmac_adapter->txff_allocation.rsvd_drv_pg_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERROR] driver download offset or size error ==========>\n"); + return HALMAC_RET_DRV_DL_ERR; + } + + /*update to target download boundary*/ + drv_pg_bndy = pHalmac_adapter->txff_allocation.rsvd_drv_pg_bndy + pg_offset; + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(drv_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_buf, halmac_size); + + /*restore to original bundary*/ + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + return ret_status; + } + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_dl_drv_rsvd_page_88xx < ==========\n"); + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_csi_rate_88xx() - config CSI frame Tx rate + * @pHalmac_adapter : the adapter of halmac + * @rssi : rssi in decimal value + * @current_rate : current CSI frame rate + * @fixrate_en : enable to fix CSI frame in VHT rate, otherwise legacy OFDM rate + * @new_rate : API returns the final CSI frame rate + * Author : chunchu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_csi_rate_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 rssi, + IN u8 current_rate, + IN u8 fixrate_en, + OUT u8 *new_rate +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u32 temp_csi_setting; + u16 current_rrsr; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_CSI_RATE); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_SND, HALMAC_DBG_TRACE, "halmac_cfg_csi_rate_88xx ==========>\n"); + + if (pHalmac_adapter->chip_id == HALMAC_CHIP_ID_8821C) { + if (fixrate_en) { + temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_CSI_FORCE_RATE_EN | BIT_CSI_RSC(1) | BIT_WMAC_CSI_RATE(HALMAC_VHT_NSS1_MCS3)); + *new_rate = HALMAC_VHT_NSS1_MCS3; + return HALMAC_RET_SUCCESS; + } + } + temp_csi_setting = HALMAC_REG_READ_32(pHalmac_adapter, REG_BBPSF_CTRL) & ~(BIT_MASK_WMAC_CSI_RATE << BIT_SHIFT_WMAC_CSI_RATE) & ~BIT_CSI_FORCE_RATE_EN; + + current_rrsr = HALMAC_REG_READ_16(pHalmac_adapter, REG_RRSR); + + if (rssi >= 40) { + if (current_rate != HALMAC_OFDM54) { + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr | BIT(HALMAC_OFDM54)); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM54)); + } + *new_rate = HALMAC_OFDM54; + return HALMAC_RET_SUCCESS; + } else { + if (current_rate != HALMAC_OFDM24) { + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_RRSR, current_rrsr & ~(BIT(HALMAC_OFDM54))); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_BBPSF_CTRL, temp_csi_setting | BIT_WMAC_CSI_RATE(HALMAC_OFDM24)); + } + *new_rate = HALMAC_OFDM24; + return HALMAC_RET_SUCCESS; + } +} + +/** + * halmac_txfifo_is_empty_88xx() -check if txfifo is empty + * @pHalmac_adapter : the adapter of halmac + * Author : Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_txfifo_is_empty_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 chk_num +) +{ + u32 counter; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx ==========>\n"); + + counter = (chk_num <= 10) ? 10 : chk_num; + do { + if (0xFF != HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY)) + return HALMAC_RET_TXFIFO_NO_EMPTY; + + if (0x07 != (HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY + 1) & 0x07)) + return HALMAC_RET_TXFIFO_NO_EMPTY; + counter--; + + } while (0 != counter); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_TRACE, "halmac_txfifo_is_empty_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h new file mode 100644 index 000000000000..642bbde499a2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx.h @@ -0,0 +1,601 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_API_88XX_H_ +#define _HALMAC_API_88XX_H_ + +#include "../halmac_2_platform.h" +#include "../halmac_type.h" + +VOID +halmac_init_state_machine_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +VOID +halmac_init_adapter_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +VOID +halmac_init_adapter_dynamic_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_mount_api_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_download_firmware_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +); + +HALMAC_RET_STATUS +halmac_free_download_firmware_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DLFW_MEM dlfw_mem, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +); + +HALMAC_RET_STATUS +halmac_get_fw_version_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT PHALMAC_FW_VERSION pFw_version +); + +HALMAC_RET_STATUS +halmac_cfg_mac_addr_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 halmac_port, + IN PHALMAC_WLAN_ADDR pHal_address +); + +HALMAC_RET_STATUS +halmac_cfg_bssid_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 halmac_port, + IN PHALMAC_WLAN_ADDR pHal_address +); + +HALMAC_RET_STATUS +halmac_cfg_multicast_addr_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_WLAN_ADDR pHal_address +); + +HALMAC_RET_STATUS +halmac_pre_init_system_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_init_system_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_cfg_rx_aggregation_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_RXAGG_CFG halmac_rxagg_cfg +); + +HALMAC_RET_STATUS +halmac_init_edca_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_cfg_operation_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_WIRELESS_MODE wireless_mode +); + +HALMAC_RET_STATUS +halmac_cfg_ch_bw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 channel, + IN HALMAC_PRI_CH_IDX pri_ch_idx, + IN HALMAC_BW bw +); + +HALMAC_RET_STATUS +halmac_cfg_ch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 channel +); + +HALMAC_RET_STATUS +halmac_cfg_pri_ch_idx_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PRI_CH_IDX pri_ch_idx +); + +HALMAC_RET_STATUS +halmac_cfg_bw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_BW bw +); + +HALMAC_RET_STATUS +halmac_init_wmac_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_init_mac_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE mode +); + +HALMAC_RET_STATUS +halmac_dump_efuse_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_READ_CFG cfg +); + +HALMAC_RET_STATUS +halmac_dump_efuse_map_bt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_BANK halmac_efuse_bank, + IN u32 bt_efuse_map_size, + OUT u8 *pBT_efuse_map +); + +HALMAC_RET_STATUS +halmac_write_efuse_bt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u8 halmac_value, + IN HALMAC_EFUSE_BANK halmac_efuse_bank +); + +HALMAC_RET_STATUS +halmac_pg_efuse_by_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN HALMAC_EFUSE_READ_CFG cfg +); + +HALMAC_RET_STATUS +halmac_get_efuse_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +); + +HALMAC_RET_STATUS +halmac_get_efuse_available_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +); + +HALMAC_RET_STATUS +halmac_get_c2h_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *halmac_buf, + IN u32 halmac_size +); + +HALMAC_RET_STATUS +halmac_get_logical_efuse_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u32 *halmac_size +); + +HALMAC_RET_STATUS +halmac_dump_logical_efuse_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_READ_CFG cfg +); + +HALMAC_RET_STATUS +halmac_write_logical_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u8 halmac_value +); + +HALMAC_RET_STATUS +halmac_read_logical_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + OUT u8 *pValue +); + +HALMAC_RET_STATUS +halmac_cfg_fwlps_option_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_FWLPS_OPTION pLps_option +); + +HALMAC_RET_STATUS +halmac_cfg_fwips_option_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_FWIPS_OPTION pIps_option +); + +HALMAC_RET_STATUS +halmac_enter_wowlan_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_WOWLAN_OPTION pWowlan_option +); + +HALMAC_RET_STATUS +halmac_leave_wowlan_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_enter_ps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PS_STATE ps_state +); + +HALMAC_RET_STATUS +halmac_leave_ps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_h2c_lb_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_debug_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_cfg_parameter_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PHY_PARAMETER_INFO para_info, + IN u8 full_fifo +); + +HALMAC_RET_STATUS +halmac_update_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PACKET_ID pkt_id, + IN u8 *pkt, + IN u32 pkt_size +); + +HALMAC_RET_STATUS +halmac_bcn_ie_filter_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_BCN_IE_INFO pBcn_ie_info +); + +HALMAC_RET_STATUS +halmac_send_original_h2c_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *original_h2c, + IN u16 *seq, + IN u8 ack +); + +HALMAC_RET_STATUS +halmac_update_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DATA_TYPE halmac_data_type, + IN PHALMAC_PHY_PARAMETER_INFO para_info +); + +HALMAC_RET_STATUS +halmac_run_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DATA_TYPE halmac_data_type +); + +HALMAC_RET_STATUS +halmac_cfg_drv_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DRV_INFO halmac_drv_info +); + +HALMAC_RET_STATUS +halmac_send_bt_coex_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pBt_buf, + IN u32 bt_size, + IN u8 ack +); + +HALMAC_RET_STATUS +halmac_verify_platform_api_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_timer_2s_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_fill_txdesc_check_sum_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *cur_desc +); + +HALMAC_RET_STATUS +halmac_dump_fifo_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_FIFO_SEL halmac_fifo_sel, + IN u32 halmac_start_addr, + IN u32 halmac_fifo_dump_size, + OUT u8 *pFifo_map +); + +u32 +halmac_get_fifo_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_FIFO_SEL halmac_fifo_sel +); + +HALMAC_RET_STATUS +halmac_cfg_txbf_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid, + IN HALMAC_BW bw, + IN u8 txbf_en +); + +HALMAC_RET_STATUS +halmac_cfg_mumimo_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CFG_MUMIMO_PARA pCfgmu +); + +HALMAC_RET_STATUS +halmac_cfg_sounding_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SND_ROLE role, + IN HALMAC_DATA_RATE datarate +); + +HALMAC_RET_STATUS +halmac_del_sounding_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SND_ROLE role +); + +HALMAC_RET_STATUS +halmac_su_bfee_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid, + IN u16 paid +); + +HALMAC_RET_STATUS +halmac_su_bfer_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init +); + +HALMAC_RET_STATUS +halmac_mu_bfee_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init +); + +HALMAC_RET_STATUS +halmac_mu_bfer_entry_init_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init +); + +HALMAC_RET_STATUS +halmac_su_bfee_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid +); + +HALMAC_RET_STATUS +halmac_su_bfer_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid +); + +HALMAC_RET_STATUS +halmac_mu_bfee_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 userid +); + +HALMAC_RET_STATUS +halmac_mu_bfer_entry_del_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_add_ch_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_INFO pCh_info +); + +HALMAC_RET_STATUS +halmac_add_extra_ch_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_EXTRA_INFO pCh_extra_info +); + +HALMAC_RET_STATUS +halmac_ctrl_ch_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_SWITCH_OPTION pCs_option +); + +HALMAC_RET_STATUS +halmac_p2pps_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_P2PPS pP2PPS +); + +HALMAC_RET_STATUS +halmac_clear_ch_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_send_general_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_GENERAL_INFO pGeneral_info +); + +HALMAC_RET_STATUS +halmac_start_iqk_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_IQK_PARA pIqk_para +); + +HALMAC_RET_STATUS +halmac_ctrl_pwr_tracking_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt +); + +HALMAC_RET_STATUS +halmac_query_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_FEATURE_ID feature_id, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_reset_feature_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_FEATURE_ID feature_id +); + +HALMAC_RET_STATUS +halmac_check_fw_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u8 *fw_status +); + +HALMAC_RET_STATUS +halmac_dump_fw_dmem_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + INOUT u8 *dmem, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_cfg_max_dl_size_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 size +); + +HALMAC_RET_STATUS +halmac_psd_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 start_psd, + IN u16 end_psd +); + +HALMAC_RET_STATUS +halmac_cfg_la_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_LA_MODE la_mode +); + +HALMAC_RET_STATUS +halmac_cfg_rx_fifo_expanding_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode +); + +HALMAC_RET_STATUS +halmac_config_security_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_SECURITY_SETTING pSec_setting +); + +u8 +halmac_get_used_cam_entry_num_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HAL_SECURITY_TYPE sec_type +); + +HALMAC_RET_STATUS +halmac_write_cam_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + IN PHALMAC_CAM_ENTRY_INFO pCam_entry_info +); + +HALMAC_RET_STATUS +halmac_read_cam_entry_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index, + OUT PHALMAC_CAM_ENTRY_FORMAT pContent +); + +HALMAC_RET_STATUS +halmac_clear_cam_entry_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 entry_index +); + +HALMAC_RET_STATUS +halmac_get_hw_value_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_HW_ID hw_id, + OUT VOID *pvalue +); + +HALMAC_RET_STATUS +halmac_set_hw_value_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_HW_ID hw_id, + IN VOID *pvalue +); + +HALMAC_RET_STATUS +halmac_cfg_drv_rsvd_pg_num_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DRV_RSVD_PG_NUM pg_num +); + +HALMAC_RET_STATUS +halmac_get_chip_version_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_VER pVersion +); + +HALMAC_RET_STATUS +halmac_chk_txdesc_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHalmac_buf, + IN u32 halmac_size +); + +HALMAC_RET_STATUS +halmac_dl_drv_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 pg_offset, + IN u8 *pHalmac_buf, + IN u32 halmac_size +); + +HALMAC_RET_STATUS +halmac_cfg_csi_rate_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 rssi, + IN u8 current_rate, + IN u8 fixrate_en, + OUT u8 *new_rate +); + +HALMAC_RET_STATUS +halmac_txfifo_is_empty_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 chk_num +); + +#endif/* _HALMAC_API_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c new file mode 100644 index 000000000000..500c4c718ee7 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.c @@ -0,0 +1,322 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "halmac_88xx_cfg.h" + +/** + * halmac_init_pcie_cfg_88xx() - init PCIe + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_pcie_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_INIT_PCIE_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_pcie_cfg_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_deinit_pcie_cfg_88xx() - deinit PCIE + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_deinit_pcie_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_DEINIT_PCIE_CFG); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_deinit_pcie_cfg_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_rx_aggregation_88xx_pcie() - config rx aggregation + * @pHalmac_adapter : the adapter of halmac + * @halmac_rx_agg_mode + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_rx_aggregation_88xx_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_RX_AGGREGATION); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_rx_aggregation_88xx_pcie <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_reg_read_8_pcie_88xx() - read 1byte register + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +u8 +halmac_reg_read_8_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + return PLATFORM_REG_READ_8(pDriver_adapter, halmac_offset); +} + +/** + * halmac_reg_write_8_pcie_88xx() - write 1byte register + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_reg_write_8_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u8 halmac_data +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_REG_WRITE_8(pDriver_adapter, halmac_offset, halmac_data); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_reg_read_16_pcie_88xx() - read 2byte register + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +u16 +halmac_reg_read_16_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + return PLATFORM_REG_READ_16(pDriver_adapter, halmac_offset); +} + +/** + * halmac_reg_write_16_pcie_88xx() - write 2byte register + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_reg_write_16_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u16 halmac_data +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_REG_WRITE_16(pDriver_adapter, halmac_offset, halmac_data); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_reg_read_32_pcie_88xx() - read 4byte register + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +u32 +halmac_reg_read_32_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + return PLATFORM_REG_READ_32(pDriver_adapter, halmac_offset); +} + +/** + * halmac_reg_write_32_pcie_88xx() - write 4byte register + * @pHalmac_adapter : the adapter of halmac + * @halmac_offset : register offset + * @halmac_data : register value + * Author : KaiYuan Chang/Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_reg_write_32_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u32 halmac_data +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_REG_WRITE_32(pDriver_adapter, halmac_offset, halmac_data); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_cfg_tx_agg_align_pcie_88xx() -config sdio bus tx agg alignment + * @pHalmac_adapter : the adapter of halmac + * @enable : function enable(1)/disable(0) + * @align_size : sdio bus tx agg alignment size (2^n, n = 3~11) + * Author : Soar Tu + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_cfg_tx_agg_align_pcie_not_support_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable, + IN u16 align_size +) +{ + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + if (HALMAC_RET_SUCCESS != halmac_api_validate(pHalmac_adapter)) + return HALMAC_RET_API_INVALID; + + halmac_api_record_id_88xx(pHalmac_adapter, HALMAC_API_CFG_TX_AGG_ALIGN); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx ==========>\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx not support\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_cfg_tx_agg_align_pcie_not_support_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h new file mode 100644 index 000000000000..3219513abab0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_api_88xx_pcie.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_API_88XX_PCIE_H_ +#define _HALMAC_API_88XX_PCIE_H_ + +#include "../halmac_2_platform.h" +#include "../halmac_type.h" + +#define LINK_CTRL2_REG_OFFSET 0xA0 +#define GEN2_CTRL_OFFSET 0x80C +#define LINK_STATUS_REG_OFFSET 0x82 +#define GEN1_SPEED 0x01 +#define GEN2_SPEED 0x02 + +HALMAC_RET_STATUS +halmac_init_pcie_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_deinit_pcie_cfg_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_cfg_rx_aggregation_88xx_pcie( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_RXAGG_CFG phalmac_rxagg_cfg +); + +u8 +halmac_reg_read_8_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +); + +HALMAC_RET_STATUS +halmac_reg_write_8_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u8 halmac_data +); + +u16 +halmac_reg_read_16_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +); + +HALMAC_RET_STATUS +halmac_reg_write_16_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u16 halmac_data +); + +u32 +halmac_reg_read_32_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset +); + +HALMAC_RET_STATUS +halmac_reg_write_32_pcie_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 halmac_offset, + IN u32 halmac_data +); + +HALMAC_RET_STATUS +halmac_cfg_tx_agg_align_pcie_not_support_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable, + IN u16 align_size +); + +#endif/* _HALMAC_API_88XX_PCIE_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c new file mode 100644 index 000000000000..2668399ee310 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.c @@ -0,0 +1,3735 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "halmac_88xx_cfg.h" + +HALMAC_RET_STATUS +halmac_dump_efuse_fw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_dump_efuse_drv_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_update_eeprom_mask_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + OUT u8 *pEeprom_mask_updated +); + +HALMAC_RET_STATUS +halmac_check_efuse_enough_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN u8 *pEeprom_mask_updated +); + +HALMAC_RET_STATUS +halmac_program_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN u8 *pEeprom_mask_updated +); + +HALMAC_RET_STATUS +halmac_pwr_sub_seq_parer_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg +); + +HALMAC_RET_STATUS +halmac_parse_c2h_debug_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_scan_status_rpt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_psd_data_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_efuse_data_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_physical_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_enqueue_para_buff_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PHY_PARAMETER_INFO para_info, + IN u8 *pCurr_buff_wptr, + OUT u8 *pEnd_cmd +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_phy_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_cfg_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_gen_cfg_para_h2c_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pH2c_buff +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_update_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); +HALMAC_RET_STATUS +halmac_parse_h2c_ack_update_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_run_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_channel_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_iqk_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_power_tracking_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +); + +VOID +halmac_init_offload_feature_state_machine_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + PHALMAC_STATE pState = &(pHalmac_adapter->halmac_state); + + pState->efuse_state_set.efuse_cmd_construct_state = HALMAC_EFUSE_CMD_CONSTRUCT_IDLE; + pState->efuse_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->efuse_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->cfg_para_state_set.cfg_para_cmd_construct_state = HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE; + pState->cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->cfg_para_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->scan_state_set.scan_cmd_construct_state = HALMAC_SCAN_CMD_CONSTRUCT_IDLE; + pState->scan_state_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->scan_state_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->update_packet_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->update_packet_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->iqk_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->iqk_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->power_tracking_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->power_tracking_set.seq_num = pHalmac_adapter->h2c_packet_seq; + + pState->psd_set.process_status = HALMAC_CMD_PROCESS_IDLE; + pState->psd_set.seq_num = pHalmac_adapter->h2c_packet_seq; + pState->psd_set.data_size = 0; + pState->psd_set.segment_size = 0; + pState->psd_set.pData = NULL; +} + +HALMAC_RET_STATUS +halmac_dump_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_READ_CFG cfg +) +{ + u32 chk_h2c_init; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.efuse_state_set.process_status); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + *pProcess_status = HALMAC_CMD_PROCESS_SENDING; + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + + if (HALMAC_EFUSE_R_AUTO == cfg) { + chk_h2c_init = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR); + if (HALMAC_DLFW_NONE == pHalmac_adapter->halmac_state.dlfw_state || 0 == chk_h2c_init) + status = halmac_dump_efuse_drv_88xx(pHalmac_adapter); + else + status = halmac_dump_efuse_fw_88xx(pHalmac_adapter); + } else if (HALMAC_EFUSE_R_FW == cfg) { + status = halmac_dump_efuse_fw_88xx(pHalmac_adapter); + } else { + status = halmac_dump_efuse_drv_88xx(pHalmac_adapter); + } + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "halmac_read_efuse error = %x\n", status); + return status; + } + + return status; +} + +HALMAC_RET_STATUS +halmac_func_read_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u32 size, + OUT u8 *pEfuse_map +) +{ + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + if (NULL == pEfuse_map) { + PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Malloc for dump efuse map error\n"); + return HALMAC_RET_NULL_POINTER; + } + + if (_TRUE == pHalmac_adapter->hal_efuse_map_valid) + PLATFORM_RTL_MEMCPY(pDriver_adapter, pEfuse_map, pHalmac_adapter->pHalEfuse_map + offset, size); + else + if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, offset, size, pEfuse_map)) + return HALMAC_RET_EFUSE_R_FAIL; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_read_hw_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u32 size, + OUT u8 *pEfuse_map +) +{ + u8 value8; + u32 value32; + u32 address; + u32 tmp32, counter; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + /* Read efuse no need 2.5V LDO */ + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3); + if (value8 & BIT(7)) + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(value8 & ~(BIT(7)))); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); + + for (address = offset; address < offset + size; address++) { + value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)); + value32 = value32 | ((address & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 & (~BIT_EF_FLAG)); + + counter = 1000000; + do { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1); + tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pHalmac_adapter->pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "HALMAC_RET_EFUSE_R_FAIL\n"); + return HALMAC_RET_EFUSE_R_FAIL; + } + } while (0 == (tmp32 & BIT_EF_FLAG)); + + *(pEfuse_map + address - offset) = (u8)(tmp32 & BIT_MASK_EF_DATA); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_dump_efuse_drv_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 *pEfuse_map = NULL; + u32 efuse_size; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + efuse_size = pHalmac_adapter->hw_config_info.efuse_size; + + if (NULL == pHalmac_adapter->pHalEfuse_map) { + pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); + if (NULL == pHalmac_adapter->pHalEfuse_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + } + + pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); + if (NULL == pEfuse_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + if (HALMAC_RET_SUCCESS != halmac_read_hw_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + return HALMAC_RET_EFUSE_R_FAIL; + } + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size); + pHalmac_adapter->hal_efuse_map_valid = _TRUE; + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_dump_efuse_fw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_DUMP_PHYSICAL_EFUSE; + h2c_header_info.content_size = 0; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + pHalmac_adapter->halmac_state.efuse_state_set.seq_num = h2c_seq_mum; + + if (NULL == pHalmac_adapter->pHalEfuse_map) { + pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pHalmac_adapter->hw_config_info.efuse_size); + if (NULL == pHalmac_adapter->pHalEfuse_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac allocate efuse map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + } + + if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) { + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_read_efuse_fw Fail = %x!!\n", status); + return status; + } + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_func_write_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u8 value +) +{ + const u8 wite_protect_code = 0x69; + u32 value32, tmp32, counter; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + pHalmac_adapter->hal_efuse_map_valid = _FALSE; + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, wite_protect_code); + + /* Enable 2.5V LDO */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) | BIT(7))); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); + value32 = value32 & ~((BIT_MASK_EF_DATA) | (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)); + value32 = value32 | ((offset & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) | (value & BIT_MASK_EF_DATA); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_EFUSE_CTRL, value32 | BIT_EF_FLAG); + + counter = 1000000; + do { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1); + tmp32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_EFUSE_CTRL); + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_write_efuse Fail !!\n"); + return HALMAC_RET_EFUSE_W_FAIL; + } + } while (BIT_EF_FLAG == (tmp32 & BIT_EF_FLAG)); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PMC_DBG_CTRL2 + 3, 0x00); + + /* Disable 2.5V LDO */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 3) & ~(BIT(7)))); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_func_switch_efuse_bank_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_BANK efuse_bank +) +{ + u8 reg_value; + PHALMAC_API pHalmac_api; + + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_transition_efuse_state_88xx(pHalmac_adapter, HALMAC_EFUSE_CMD_CONSTRUCT_BUSY)) + return HALMAC_RET_ERROR_STATE; + + reg_value = HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1); + + if (efuse_bank == (reg_value & (BIT(0) | BIT(1)))) + return HALMAC_RET_SUCCESS; + + reg_value &= ~(BIT(0) | BIT(1)); + reg_value |= efuse_bank; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1, reg_value); + + if ((HALMAC_REG_READ_8(pHalmac_adapter, REG_LDO_EFUSE_CTRL + 1) & (BIT(0) | BIT(1))) != efuse_bank) + return HALMAC_RET_SWITCH_EFUSE_BANK_FAIL; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_eeprom_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pPhysical_efuse_map, + OUT u8 *pLogical_efuse_map +) +{ + u8 j; + u8 value8; + u8 block_index; + u8 valid_word_enable, word_enable; + u8 efuse_read_header, efuse_read_header2 = 0; + u32 eeprom_index; + u32 efuse_index = 0; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_RTL_MEMSET(pDriver_adapter, pLogical_efuse_map, 0xFF, eeprom_size); + + do { + value8 = *(pPhysical_efuse_map + efuse_index); + efuse_read_header = value8; + + if ((efuse_read_header & 0x1f) == 0x0f) { + efuse_index++; + value8 = *(pPhysical_efuse_map + efuse_index); + efuse_read_header2 = value8; + block_index = ((efuse_read_header2 & 0xF0) >> 1) | ((efuse_read_header >> 5) & 0x07); + word_enable = efuse_read_header2 & 0x0F; + } else { + block_index = (efuse_read_header & 0xF0) >> 4; + word_enable = efuse_read_header & 0x0F; + } + + if (efuse_read_header == 0xff) + break; + + efuse_index++; + + if (efuse_index >= pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + for (j = 0; j < 4; j++) { + valid_word_enable = (u8)((~(word_enable >> j)) & BIT(0)); + if (valid_word_enable == 1) { + eeprom_index = (block_index << 3) + (j << 1); + + if ((eeprom_index + 1) > eeprom_size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM addr exceeds eeprom_size:0x%X, at eFuse 0x%X\n", eeprom_size, efuse_index - 1); + if ((efuse_read_header & 0x1f) == 0x0f) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X, 0x%X,\n", efuse_read_header, efuse_read_header2); + else + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "Error: EEPROM header: 0x%X,\n", efuse_read_header); + + return HALMAC_RET_EEPROM_PARSING_FAIL; + } else { + value8 = *(pPhysical_efuse_map + efuse_index); + *(pLogical_efuse_map + eeprom_index) = value8; + + eeprom_index++; + efuse_index++; + + if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX - 1) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + value8 = *(pPhysical_efuse_map + efuse_index); + *(pLogical_efuse_map + eeprom_index) = value8; + + efuse_index++; + + if (efuse_index > pHalmac_adapter->hw_config_info.efuse_size - HALMAC_PROTECTED_EFUSE_SIZE_88XX) + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + } + } + } while (1); + + pHalmac_adapter->efuse_end = efuse_index; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_read_logical_efuse_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pMap +) +{ + u8 *pEfuse_map = NULL; + u32 efuse_size; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + efuse_size = pHalmac_adapter->hw_config_info.efuse_size; + + if (_FALSE == pHalmac_adapter->hal_efuse_map_valid) { + pEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); + if (NULL == pEfuse_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local efuse map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + status = halmac_func_read_efuse_88xx(pHalmac_adapter, 0, efuse_size, pEfuse_map); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_efuse error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + return status; + } + + if (NULL == pHalmac_adapter->pHalEfuse_map) { + pHalmac_adapter->pHalEfuse_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, efuse_size); + if (NULL == pHalmac_adapter->pHalEfuse_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate efuse map Fail!!\n"); + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + return HALMAC_RET_MALLOC_FAIL; + } + } + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pEfuse_map, efuse_size); + pHalmac_adapter->hal_efuse_map_valid = _TRUE; + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + + PLATFORM_RTL_FREE(pDriver_adapter, pEfuse_map, efuse_size); + } + + if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pMap)) + return HALMAC_RET_EEPROM_PARSING_FAIL; + + return status; +} + +HALMAC_RET_STATUS +halmac_func_write_logical_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u8 value +) +{ + u8 pg_efuse_byte1, pg_efuse_byte2; + u8 pg_block, pg_block_index; + u8 pg_efuse_header, pg_efuse_header2; + u8 *pEeprom_map = NULL; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + u32 efuse_end, pg_efuse_num; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (NULL == pEeprom_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_read_logical_efuse_map_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return status; + } + + if (*(pEeprom_map + offset) != value) { + efuse_end = pHalmac_adapter->efuse_end; + pg_block = (u8)(offset >> 3); + pg_block_index = (u8)((offset & (8 - 1)) >> 1); + + if (offset > 0x7f) { + pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F; + pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + ((0x1 << pg_block_index) ^ 0x0F)); + } else { + pg_efuse_header = (u8)((pg_block << 4) + ((0x01 << pg_block_index) ^ 0x0F)); + } + + if ((offset & 1) == 0) { + pg_efuse_byte1 = value; + pg_efuse_byte2 = *(pEeprom_map + offset + 1); + } else { + pg_efuse_byte1 = *(pEeprom_map + offset - 1); + pg_efuse_byte2 = value; + } + + if (offset > 0x7f) { + pg_efuse_num = 4; + if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte1); + status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 3, pg_efuse_byte2); + } else { + pg_efuse_num = 3; + if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_EFUSE_NOT_ENOUGH; + } + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_byte1); + status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 2, pg_efuse_byte2); + } + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_write_logical_efuse error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return status; + } + } + + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_func_pg_efuse_by_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN HALMAC_EFUSE_READ_CFG cfg +) +{ + u8 *pEeprom_mask_updated = NULL; + u32 eeprom_mask_size = pHalmac_adapter->hw_config_info.eeprom_size >> 4; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pEeprom_mask_updated = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_mask_size); + if (NULL == pEeprom_mask_updated) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, eeprom_mask_size); + + status = halmac_update_eeprom_mask_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_update_eeprom_mask_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); + return status; + } + + status = halmac_check_efuse_enough_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_check_efuse_enough_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); + return status; + } + + status = halmac_program_efuse_88xx(pHalmac_adapter, pPg_efuse_info, pEeprom_mask_updated); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac_program_efuse_88xx error = %x\n", status); + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); + return status; + } + + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_mask_updated, eeprom_mask_size); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_update_eeprom_mask_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + INOUT PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + OUT u8 *pEeprom_mask_updated +) +{ + u8 *pEeprom_map = NULL; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + u8 *pEeprom_map_pg, *pEeprom_mask; + u16 i, j; + u16 map_byte_offset, mask_byte_offset; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + VOID *pDriver_adapter = NULL; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (NULL == pEeprom_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_mask_updated, 0x00, pPg_efuse_info->efuse_mask_size); + + status = halmac_read_logical_efuse_map_88xx(pHalmac_adapter, pEeprom_map); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return status; + } + + pEeprom_map_pg = pPg_efuse_info->pEfuse_map; + pEeprom_mask = pPg_efuse_info->pEfuse_mask; + + for (i = 0; i < pPg_efuse_info->efuse_mask_size; i++) + *(pEeprom_mask_updated + i) = *(pEeprom_mask + i); + + for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 16) { + for (j = 0; j < 16; j = j + 2) { + map_byte_offset = i + j; + mask_byte_offset = i >> 4; + if (*(pEeprom_map_pg + map_byte_offset) == *(pEeprom_map + map_byte_offset)) { + if (*(pEeprom_map_pg + map_byte_offset + 1) == *(pEeprom_map + map_byte_offset + 1)) { + switch (j) { + case 0: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(4) ^ 0xFF); + break; + case 2: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(5) ^ 0xFF); + break; + case 4: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(6) ^ 0xFF); + break; + case 6: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(7) ^ 0xFF); + break; + case 8: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(0) ^ 0xFF); + break; + case 10: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(1) ^ 0xFF); + break; + case 12: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(2) ^ 0xFF); + break; + case 14: + *(pEeprom_mask_updated + mask_byte_offset) = *(pEeprom_mask_updated + mask_byte_offset) & (BIT(3) ^ 0xFF); + break; + default: + break; + } + } + } + } + } + + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + + return status; +} + +HALMAC_RET_STATUS +halmac_check_efuse_enough_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN u8 *pEeprom_mask_updated +) +{ + u8 pre_word_enb, word_enb; + u8 pg_efuse_header, pg_efuse_header2; + u8 pg_block; + u16 i, j; + u32 efuse_end; + u32 tmp_eeprom_offset, pg_efuse_num = 0; + + efuse_end = pHalmac_adapter->efuse_end; + + for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) { + tmp_eeprom_offset = i; + + if ((tmp_eeprom_offset & 7) > 0) { + pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F); + word_enb = pre_word_enb ^ 0x0F; + } else { + pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4); + word_enb = pre_word_enb ^ 0x0F; + } + + pg_block = (u8)(tmp_eeprom_offset >> 3); + + if (pre_word_enb > 0) { + if (tmp_eeprom_offset > 0x7f) { + pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F; + pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb); + } else { + pg_efuse_header = (u8)((pg_block << 4) + word_enb); + } + + if (tmp_eeprom_offset > 0x7f) { + pg_efuse_num++; + pg_efuse_num++; + efuse_end = efuse_end + 2; + for (j = 0; j < 4; j++) { + if (((pre_word_enb >> j) & 0x1) > 0) { + pg_efuse_num++; + pg_efuse_num++; + efuse_end = efuse_end + 2; + } + } + } else { + pg_efuse_num++; + efuse_end = efuse_end + 1; + for (j = 0; j < 4; j++) { + if (((pre_word_enb >> j) & 0x1) > 0) { + pg_efuse_num++; + pg_efuse_num++; + efuse_end = efuse_end + 2; + } + } + } + } + } + + if (pHalmac_adapter->hw_config_info.efuse_size <= (pg_efuse_num + HALMAC_PROTECTED_EFUSE_SIZE_88XX + pHalmac_adapter->efuse_end)) + return HALMAC_RET_EFUSE_NOT_ENOUGH; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_program_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN u8 *pEeprom_mask_updated +) +{ + u8 pre_word_enb, word_enb; + u8 pg_efuse_header, pg_efuse_header2; + u8 pg_block; + u16 i, j; + u32 efuse_end; + u32 tmp_eeprom_offset; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + efuse_end = pHalmac_adapter->efuse_end; + + for (i = 0; i < pPg_efuse_info->efuse_map_size; i = i + 8) { + tmp_eeprom_offset = i; + + if (((tmp_eeprom_offset >> 3) & 1) > 0) { + pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) & 0x0F); + word_enb = pre_word_enb ^ 0x0F; + } else { + pre_word_enb = (*(pEeprom_mask_updated + (i >> 4)) >> 4); + word_enb = pre_word_enb ^ 0x0F; + } + + pg_block = (u8)(tmp_eeprom_offset >> 3); + + if (pre_word_enb > 0) { + if (tmp_eeprom_offset > 0x7f) { + pg_efuse_header = (((pg_block & 0x07) << 5) & 0xE0) | 0x0F; + pg_efuse_header2 = (u8)(((pg_block & 0x78) << 1) + word_enb); + } else { + pg_efuse_header = (u8)((pg_block << 4) + word_enb); + } + + if (tmp_eeprom_offset > 0x7f) { + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); + status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, pg_efuse_header2); + efuse_end = efuse_end + 2; + for (j = 0; j < 4; j++) { + if (((pre_word_enb >> j) & 0x1) > 0) { + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); + status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1)); + efuse_end = efuse_end + 2; + } + } + } else { + status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, pg_efuse_header); + efuse_end = efuse_end + 1; + for (j = 0; j < 4; j++) { + if (((pre_word_enb >> j) & 0x1) > 0) { + halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1))); + status = halmac_func_write_efuse_88xx(pHalmac_adapter, efuse_end + 1, *(pPg_efuse_info->pEfuse_map + tmp_eeprom_offset + (j << 1) + 1)); + efuse_end = efuse_end + 2; + } + } + } + } + } + + return status; +} + +HALMAC_RET_STATUS +halmac_update_fw_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +) +{ + PHALMAC_FW_VERSION pFw_info = &(pHalmac_adapter->fw_version); + + pFw_info->version = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_VERSION_88XX))); + pFw_info->sub_version = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBVERSION_88XX); + pFw_info->sub_index = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_SUBINDEX_88XX); + pFw_info->h2c_version = (u16)rtk_le32_to_cpu(*((u32 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_H2C_FORMAT_VER_88XX))); + pFw_info->build_time.month = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MONTH_88XX); + pFw_info->build_time.date = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_DATE_88XX); + pFw_info->build_time.hour = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_HOUR_88XX); + pFw_info->build_time.min = *(pHamacl_fw + HALMAC_FWHDR_OFFSET_MIN_88XX); + pFw_info->build_time.year = rtk_le16_to_cpu(*((u16 *)(pHamacl_fw + HALMAC_FWHDR_OFFSET_YEAR_88XX))); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_dlfw_to_mem_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pRam_code, + IN u32 dest, + IN u32 code_size +) +{ + u8 *pCode_ptr; + u8 first_part; + u32 mem_offset; + u32 pkt_size_tmp, send_pkt_size; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + pCode_ptr = pRam_code; + mem_offset = 0; + first_part = 1; + pkt_size_tmp = code_size; + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) | BIT_DDMACH0_RESET_CHKSUM_STS); + + while (0 != pkt_size_tmp) { + if (pkt_size_tmp >= pHalmac_adapter->max_download_size) + send_pkt_size = pHalmac_adapter->max_download_size; + else + send_pkt_size = pkt_size_tmp; + + if (HALMAC_RET_SUCCESS != halmac_send_fwpkt_88xx(pHalmac_adapter, pCode_ptr + mem_offset, send_pkt_size)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_send_fwpkt_88xx fail!!"); + return HALMAC_RET_DLFW_FAIL; + } + + if (HALMAC_RET_SUCCESS != halmac_iddma_dlfw_88xx(pHalmac_adapter, HALMAC_OCPBASE_TXBUF_88XX + pHalmac_adapter->hw_config_info.txdesc_size, + dest + mem_offset, send_pkt_size, first_part)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx fail!!"); + return HALMAC_RET_DLFW_FAIL; + } + + first_part = 0; + mem_offset += send_pkt_size; + pkt_size_tmp -= send_pkt_size; + } + + if (HALMAC_RET_SUCCESS != halmac_check_fw_chksum_88xx(pHalmac_adapter, dest)) { + PLATFORM_MSG_PRINT(pHalmac_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx fail!!"); + return HALMAC_RET_DLFW_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_send_fwpkt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pRam_code, + IN u32 code_size +) +{ + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + if (HALMAC_RET_SUCCESS != halmac_download_rsvd_page_88xx(pHalmac_adapter, pRam_code, code_size)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 0 error!!\n"); + return HALMAC_RET_DL_RSVD_PAGE_FAIL; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_iddma_dlfw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 source, + IN u32 dest, + IN u32 length, + IN u8 first +) +{ + u32 counter; + u32 ch0_control = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN); + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + counter = HALMC_DDMA_POLLING_COUNT; + while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-1!!\n"); + return HALMAC_RET_DDMA_FAIL; + } + } + + ch0_control |= (length & BIT_MASK_DDMACH0_DLEN); + if (0 == first) + ch0_control |= BIT_DDMACH0_CHKSUM_CONT; + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0SA, source); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0DA, dest); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_DDMA_CH0CTRL, ch0_control); + + counter = HALMC_DDMA_POLLING_COUNT; + while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_iddma_dlfw_88xx error-2!!\n"); + return HALMAC_RET_DDMA_FAIL; + } + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_check_fw_chksum_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 memory_address +) +{ + u8 mcu_fw_ctrl; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + mcu_fw_ctrl = HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL); + + if (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) { + if (memory_address < HALMAC_OCPBASE_DMEM_88XX) { + mcu_fw_ctrl |= BIT_IMEM_DW_OK; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_IMEM_CHKSUM_OK))); + } else { + mcu_fw_ctrl |= BIT_DMEM_DW_OK; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl & ~(BIT_DMEM_CHKSUM_OK))); + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_FW, HALMAC_DBG_ERR, "halmac_check_fw_chksum_88xx error!!\n"); + + return HALMAC_RET_FW_CHECKSUM_FAIL; + } else { + if (memory_address < HALMAC_OCPBASE_DMEM_88XX) { + mcu_fw_ctrl |= BIT_IMEM_DW_OK; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_IMEM_CHKSUM_OK)); + } else { + mcu_fw_ctrl |= BIT_DMEM_DW_OK; + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(mcu_fw_ctrl | BIT_DMEM_CHKSUM_OK)); + } + + return HALMAC_RET_SUCCESS; + } +} + +HALMAC_RET_STATUS +halmac_dlfw_end_flow_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 value8; + u32 counter; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TXDMA_STATUS, BIT(2)); + + /* Check IMEM & DMEM checksum is OK or not */ + if (0x50 == (HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & 0x50)) + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MCUFW_CTRL, (u16)(HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL) | BIT_FW_DW_RDY)); + else + return HALMAC_RET_DLFW_FAIL; + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_MCUFW_CTRL, (u8)(HALMAC_REG_READ_8(pHalmac_adapter, REG_MCUFW_CTRL) & ~(BIT(0)))); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RSV_CTRL + 1); + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RSV_CTRL + 1, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1); + value8 = (u8)(value8 | BIT(2)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN + 1, value8); /* Release MCU reset */ + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Download Finish, Reset CPU\n"); + + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1, 0xC00F0038); + + counter = 10000; + while (0xC078 != HALMAC_REG_READ_16(pHalmac_adapter, REG_MCUFW_CTRL)) { + if (counter == 0) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Check 0x80 = 0xC078 fail\n"); + if (0xFAAAAA00 == (HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG7) & 0xFFFFFF00)) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Key fail\n"); + return HALMAC_RET_DLFW_FAIL; + } + counter--; + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Check 0x80 = 0xC078 counter = %d\n", counter); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_free_dl_fw_end_flow_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u32 counter; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + counter = 100; + while (0 != HALMAC_REG_READ_8(pHalmac_adapter, REG_HMETFR + 3)) { + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1CF != 0\n"); + return HALMAC_RET_DLFW_FAIL; + } + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_HMETFR + 3, ID_INFORM_DLEMEM_RDY); + + counter = 10000; + while (ID_INFORM_DLEMEM_RDY != HALMAC_REG_READ_8(pHalmac_adapter, REG_C2HEVT_3 + 3)) { + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]0x1AF != 0x80\n"); + return HALMAC_RET_DLFW_FAIL; + } + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_C2HEVT_3 + 3, 0); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_pwr_seq_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg +) +{ + u32 seq_idx = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_WLAN_PWR_CFG pSeq_cmd; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + do { + pSeq_cmd = &(*ppPwr_seq_cfg[seq_idx]); + + if (NULL == pSeq_cmd) + break; + + status = halmac_pwr_sub_seq_parer_88xx(pHalmac_adapter, cut, fab, intf, pSeq_cmd); + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[Err]pwr sub seq parser fail, status = 0x%X!\n", status); + return status; + } + + seq_idx++; + } while (1); + + return status; +} + +HALMAC_RET_STATUS +halmac_pwr_sub_seq_parer_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG pPwr_sub_seq_cfg +) +{ + u8 value, flag; + u8 polling_bit; + u32 offset; + u32 polling_count; + static u32 poll_to_static, poll_long_static; + VOID *pDriver_adapter = NULL; + PHALMAC_WLAN_PWR_CFG pSub_seq_cmd; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + pSub_seq_cmd = pPwr_sub_seq_cfg; + + do { + if ((pSub_seq_cmd->interface_msk & intf) && (pSub_seq_cmd->fab_msk & fab) && (pSub_seq_cmd->cut_msk & cut)) { + switch (pSub_seq_cmd->cmd) { + case HALMAC_PWR_CMD_WRITE: + offset = pSub_seq_cmd->offset; + + value = HALMAC_REG_READ_8(pHalmac_adapter, offset); + value = (u8)(value & (u8)(~(pSub_seq_cmd->msk))); + value = (u8)(value | (u8)(pSub_seq_cmd->value & pSub_seq_cmd->msk)); + + HALMAC_REG_WRITE_8(pHalmac_adapter, offset, value); + break; + case HALMAC_PWR_CMD_POLLING: + polling_bit = 0; + polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; + flag = 0; + + offset = pSub_seq_cmd->offset; + + do { + polling_count--; + value = HALMAC_REG_READ_8(pHalmac_adapter, offset); + value = (u8)(value & pSub_seq_cmd->msk); + + if (value == (pSub_seq_cmd->value & pSub_seq_cmd->msk)) { + polling_bit = 1; + } else { + if (0 == polling_count) { + if (HALMAC_INTERFACE_PCIE == pHalmac_adapter->halmac_interface && 0 == flag) { + /* For PCIE + USB package poll power bit timeout issue */ + poll_to_static++; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_WARN, "[WARN]PCIE polling timeout : %d!!\n", poll_to_static); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT(3)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_PW_CTRL) & ~BIT(3)); + polling_bit = 0; + polling_count = HALMAC_POLLING_READY_TIMEOUT_COUNT; + flag = 1; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd polling timeout!!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd offset : %X!!\n", pSub_seq_cmd->offset); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd value : %X!!\n", pSub_seq_cmd->value); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Pwr cmd msk : %X!!\n", pSub_seq_cmd->msk); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_PWR, HALMAC_DBG_ERR, "[ERR]Read offset = %X value = %X!!\n", offset, value); + return HALMAC_RET_PWRSEQ_POLLING_FAIL; + } + } else { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 50); + } + } + } while (!polling_bit); + break; + case HALMAC_PWR_CMD_DELAY: + if (pSub_seq_cmd->value == HALMAC_PWRSEQ_DELAY_US) + PLATFORM_RTL_DELAY_US(pDriver_adapter, pSub_seq_cmd->offset); + else + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000 * pSub_seq_cmd->offset); + break; + case HALMAC_PWR_CMD_READ: + break; + case HALMAC_PWR_CMD_END: + return HALMAC_RET_SUCCESS; + default: + return HALMAC_RET_PWRSEQ_CMD_INCORRECT; + } + } + pSub_seq_cmd++; + } while (1); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_get_h2c_buff_free_space_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u32 hw_wptr, fw_rptr; + PHALMAC_API pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + hw_wptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_WR_ADDR; + fw_rptr = HALMAC_REG_READ_32(pHalmac_adapter, REG_H2C_PKT_READADDR) & BIT_MASK_H2C_READ_ADDR; + + if (hw_wptr >= fw_rptr) + pHalmac_adapter->h2c_buf_free_space = pHalmac_adapter->h2c_buff_size - (hw_wptr - fw_rptr); + else + pHalmac_adapter->h2c_buf_free_space = fw_rptr - hw_wptr; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_send_h2c_pkt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHal_h2c_cmd, + IN u32 size, + IN u8 ack +) +{ + u32 counter = 100; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + while (pHalmac_adapter->h2c_buf_free_space <= HALMAC_H2C_CMD_SIZE_UNIT_88XX) { + halmac_get_h2c_buff_free_space_88xx(pHalmac_adapter); + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "h2c free space is not enough!!\n"); + return HALMAC_RET_H2C_SPACE_FULL; + } + } + + /* Send TxDesc + H2C_CMD */ + if (_FALSE == PLATFORM_SEND_H2C_PKT(pDriver_adapter, pHal_h2c_cmd, size)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Send H2C_CMD pkt error!!\n"); + return HALMAC_RET_SEND_H2C_FAIL; + } + + pHalmac_adapter->h2c_buf_free_space -= HALMAC_H2C_CMD_SIZE_UNIT_88XX; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "H2C free space : %d\n", pHalmac_adapter->h2c_buf_free_space); + + return status; +} + +HALMAC_RET_STATUS +halmac_download_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHal_buf, + IN u32 size +) +{ + u8 restore[3]; + u8 value8; + u32 counter; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (0 == size) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Rsvd page packet size is zero!!\n"); + return HALMAC_RET_ZERO_LEN_RSVD_PACKET; + } + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1); + value8 = (u8)(value8 | BIT(7)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_CR + 1); + restore[0] = value8; + value8 = (u8)(value8 | BIT(0)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_BCN_CTRL); + restore[1] = value8; + value8 = (u8)((value8 & ~(BIT(3))) | BIT(4)); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2); + restore[2] = value8; + value8 = (u8)(value8 & ~(BIT(6))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, value8); + + if (_FALSE == PLATFORM_SEND_RSVD_PAGE(pDriver_adapter, pHal_buf, size)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "PLATFORM_SEND_RSVD_PAGE 1 error!!\n"); + status = HALMAC_RET_DL_RSVD_PAGE_FAIL; + } + + /* Check Bcn_Valid_Bit */ + counter = 1000; + while (!(HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1) & BIT(7))) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + counter--; + if (0 == counter) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Polling Bcn_Valid_Fail error!!\n"); + status = HALMAC_RET_POLLING_BCN_VALID_FAIL; + break; + } + } + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FIFOPAGE_CTRL_2 + 1, (value8 | BIT(7))); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_FWHW_TXQ_CTRL + 2, restore[2]); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_BCN_CTRL, restore[1]); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_CR + 1, restore[0]); + + return status; +} + +HALMAC_RET_STATUS +halmac_set_h2c_header_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u8 *pHal_h2c_hdr, + IN u16 *seq, + IN u8 ack +) +{ + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_h2c_header_88xx!!\n"); + + H2C_CMD_HEADER_SET_CATEGORY(pHal_h2c_hdr, 0x00); + H2C_CMD_HEADER_SET_TOTAL_LEN(pHal_h2c_hdr, 16); + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + H2C_CMD_HEADER_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq); + *seq = pHalmac_adapter->h2c_packet_seq; + pHalmac_adapter->h2c_packet_seq++; + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + + if (_TRUE == ack) + H2C_CMD_HEADER_SET_ACK(pHal_h2c_hdr, _TRUE); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_set_fw_offload_h2c_header_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u8 *pHal_h2c_hdr, + IN PHALMAC_H2C_HEADER_INFO pH2c_header_info, + OUT u16 *pSeq_num +) +{ + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_set_fw_offload_h2c_header_88xx!!\n"); + + FW_OFFLOAD_H2C_SET_TOTAL_LEN(pHal_h2c_hdr, 8 + pH2c_header_info->content_size); + FW_OFFLOAD_H2C_SET_SUB_CMD_ID(pHal_h2c_hdr, pH2c_header_info->sub_cmd_id); + + FW_OFFLOAD_H2C_SET_CATEGORY(pHal_h2c_hdr, 0x01); + FW_OFFLOAD_H2C_SET_CMD_ID(pHal_h2c_hdr, 0xFF); + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + FW_OFFLOAD_H2C_SET_SEQ_NUM(pHal_h2c_hdr, pHalmac_adapter->h2c_packet_seq); + *pSeq_num = pHalmac_adapter->h2c_packet_seq; + pHalmac_adapter->h2c_packet_seq++; + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + + if (_TRUE == pH2c_header_info->ack) + FW_OFFLOAD_H2C_SET_ACK(pHal_h2c_hdr, _TRUE); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_send_h2c_set_pwr_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt +) +{ + u8 h2c_buff[HALMAC_H2C_CMD_SIZE_88XX]; + u8 *pH2c_header, *pH2c_cmd; + u16 seq = 0; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_set_pwr_mode_88xx!!\n"); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pH2c_header = h2c_buff; + pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX; + + PLATFORM_RTL_MEMSET(pDriver_adapter, h2c_buff, 0x00, HALMAC_H2C_CMD_SIZE_88XX); + + SET_PWR_MODE_SET_CMD_ID(pH2c_cmd, CMD_ID_SET_PWR_MODE); + SET_PWR_MODE_SET_CLASS(pH2c_cmd, CLASS_SET_PWR_MODE); + SET_PWR_MODE_SET_MODE(pH2c_cmd, pHal_FwLps_Opt->mode); + SET_PWR_MODE_SET_CLK_REQUEST(pH2c_cmd, pHal_FwLps_Opt->clk_request); + SET_PWR_MODE_SET_RLBM(pH2c_cmd, pHal_FwLps_Opt->rlbm); + SET_PWR_MODE_SET_SMART_PS(pH2c_cmd, pHal_FwLps_Opt->smart_ps); + SET_PWR_MODE_SET_AWAKE_INTERVAL(pH2c_cmd, pHal_FwLps_Opt->awake_interval); + SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(pH2c_cmd, pHal_FwLps_Opt->all_queue_uapsd); + SET_PWR_MODE_SET_PWR_STATE(pH2c_cmd, pHal_FwLps_Opt->pwr_state); + SET_PWR_MODE_SET_ANT_AUTO_SWITCH(pH2c_cmd, pHal_FwLps_Opt->ant_auto_switch); + SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(pH2c_cmd, pHal_FwLps_Opt->ps_allow_bt_high_Priority); + SET_PWR_MODE_SET_PROTECT_BCN(pH2c_cmd, pHal_FwLps_Opt->protect_bcn); + SET_PWR_MODE_SET_SILENCE_PERIOD(pH2c_cmd, pHal_FwLps_Opt->silence_period); + SET_PWR_MODE_SET_FAST_BT_CONNECT(pH2c_cmd, pHal_FwLps_Opt->fast_bt_connect); + SET_PWR_MODE_SET_TWO_ANTENNA_EN(pH2c_cmd, pHal_FwLps_Opt->two_antenna_en); + SET_PWR_MODE_SET_ADOPT_USER_SETTING(pH2c_cmd, pHal_FwLps_Opt->adopt_user_Setting); + SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(pH2c_cmd, pHal_FwLps_Opt->drv_bcn_early_shift); + + halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, &seq, _TRUE); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, h2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_set_pwr_mode_88xx Fail = %x!!\n", status); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_func_send_original_h2c_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *original_h2c, + IN u16 *seq, + IN u8 ack +) +{ + u8 H2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u8 *pH2c_header, *pH2c_cmd; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c ==========>\n"); + + pH2c_header = H2c_buff; + pH2c_cmd = pH2c_header + HALMAC_H2C_CMD_HDR_SIZE_88XX; + PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_cmd, original_h2c, 8); /* Original H2C 8 byte */ + + halmac_set_h2c_header_88xx(pHalmac_adapter, pH2c_header, seq, ack); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, H2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_original_h2c Fail = %x!!\n", status); + return status; + } + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_original_h2c <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_send_h2c_update_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PACKET_ID pkt_id, + IN u8 *pkt, + IN u32 pkt_size +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pkt, pkt_size); + + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", ret_status); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + return ret_status; + } + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + UPDATE_PACKET_SET_SIZE(pH2c_buff, pkt_size + pHalmac_adapter->hw_config_info.txdesc_size); + UPDATE_PACKET_SET_PACKET_ID(pH2c_buff, pkt_id); + UPDATE_PACKET_SET_PACKET_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_PACKET; + h2c_header_info.content_size = 8; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + pHalmac_adapter->halmac_state.update_packet_set.seq_num = h2c_seq_mum; + + ret_status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_update_packet_88xx Fail = %x!!\n", ret_status); + return ret_status; + } + + return ret_status; +} + +HALMAC_RET_STATUS +halmac_send_h2c_phy_parameter_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PHY_PARAMETER_INFO para_info, + IN u8 full_fifo +) +{ + u8 drv_trigger_send = _FALSE; + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + u32 info_size = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + PHALMAC_CONFIG_PARA_INFO pConfig_para_info; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + pConfig_para_info = &(pHalmac_adapter->config_para_info); + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_phy_parameter_88xx!!\n"); */ + + if (NULL == pConfig_para_info->pCfg_para_buf) { + if (_TRUE == full_fifo) + pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_FULL_FIFO_88XX; + else + pConfig_para_info->para_buf_size = HALMAC_EXTRA_INFO_BUFF_SIZE_88XX; + + pConfig_para_info->pCfg_para_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pConfig_para_info->para_buf_size); + + if (NULL != pConfig_para_info->pCfg_para_buf) { + PLATFORM_RTL_MEMSET(pDriver_adapter, pConfig_para_info->pCfg_para_buf, 0x00, pConfig_para_info->para_buf_size); + pConfig_para_info->full_fifo_mode = full_fifo; + pConfig_para_info->pPara_buf_w = pConfig_para_info->pCfg_para_buf; + pConfig_para_info->para_num = 0; + pConfig_para_info->avai_para_buf_size = pConfig_para_info->para_buf_size; + pConfig_para_info->value_accumulation = 0; + pConfig_para_info->offset_accumulation = 0; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Allocate pCfg_para_buf fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + } + + if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING)) + return HALMAC_RET_ERROR_STATE; + + halmac_enqueue_para_buff_88xx(pHalmac_adapter, para_info, pConfig_para_info->pPara_buf_w, &drv_trigger_send); + + if (HALMAC_PARAMETER_CMD_END != para_info->cmd_id) { + pConfig_para_info->para_num++; + pConfig_para_info->pPara_buf_w += HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; + pConfig_para_info->avai_para_buf_size = pConfig_para_info->avai_para_buf_size - HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; + } + + if (((pConfig_para_info->avai_para_buf_size - pHalmac_adapter->hw_config_info.txdesc_size) > HALMAC_FW_OFFLOAD_CMD_SIZE_88XX) && + (_FALSE == drv_trigger_send)) { + return HALMAC_RET_SUCCESS; + } else { + if (0 == pConfig_para_info->para_num) { + PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); + pConfig_para_info->pCfg_para_buf = NULL; + pConfig_para_info->pPara_buf_w = NULL; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "no cfg parameter element!!\n"); + + if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + + pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = HALMAC_CMD_PROCESS_SENDING; + + if (_TRUE == pConfig_para_info->full_fifo_mode) + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, 0); + else + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + info_size = pConfig_para_info->para_num * HALMAC_FW_OFFLOAD_CMD_SIZE_88XX; + + status = halmac_download_rsvd_page_88xx(pHalmac_adapter, (u8 *)pConfig_para_info->pCfg_para_buf, info_size); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail!!\n"); + } else { + halmac_gen_cfg_para_h2c_88xx(pHalmac_adapter, pH2c_buff); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_CFG_PARAMETER; + h2c_header_info.content_size = 4; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num = h2c_seq_mum; + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail!!\n"); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "config parameter time = %d\n", HALMAC_REG_READ_32(pHalmac_adapter, REG_FW_DBG6)); + } + + PLATFORM_RTL_FREE(pDriver_adapter, pConfig_para_info->pCfg_para_buf, pConfig_para_info->para_buf_size); + pConfig_para_info->pCfg_para_buf = NULL; + pConfig_para_info->pPara_buf_w = NULL; + + /* Restore bcn head */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + if (HALMAC_RET_SUCCESS != halmac_transition_cfg_para_state_88xx(pHalmac_adapter, HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + } + + if (_FALSE == drv_trigger_send) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "Buffer full trigger sending H2C!!\n"); + return HALMAC_RET_PARA_SENDING; + } + + return status; +} + +HALMAC_RET_STATUS +halmac_enqueue_para_buff_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PHY_PARAMETER_INFO para_info, + IN u8 *pCurr_buff_wptr, + OUT u8 *pEnd_cmd +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info); + + *pEnd_cmd = _FALSE; + + PHY_PARAMETER_INFO_SET_LENGTH(pCurr_buff_wptr, HALMAC_FW_OFFLOAD_CMD_SIZE_88XX); + PHY_PARAMETER_INFO_SET_IO_CMD(pCurr_buff_wptr, para_info->cmd_id); + + switch (para_info->cmd_id) { + case HALMAC_PARAMETER_CMD_BB_W8: + case HALMAC_PARAMETER_CMD_BB_W16: + case HALMAC_PARAMETER_CMD_BB_W32: + case HALMAC_PARAMETER_CMD_MAC_W8: + case HALMAC_PARAMETER_CMD_MAC_W16: + case HALMAC_PARAMETER_CMD_MAC_W32: + PHY_PARAMETER_INFO_SET_IO_ADDR(pCurr_buff_wptr, para_info->content.MAC_REG_W.offset); + PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.MAC_REG_W.value); + PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk); + PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.MAC_REG_W.msk_en); + pConfig_para_info->value_accumulation += para_info->content.MAC_REG_W.value; + pConfig_para_info->offset_accumulation += para_info->content.MAC_REG_W.offset; + break; + case HALMAC_PARAMETER_CMD_RF_W: + PHY_PARAMETER_INFO_SET_RF_ADDR(pCurr_buff_wptr, para_info->content.RF_REG_W.offset); /*In rf register, the address is only 1 byte*/ + PHY_PARAMETER_INFO_SET_RF_PATH(pCurr_buff_wptr, para_info->content.RF_REG_W.rf_path); + PHY_PARAMETER_INFO_SET_DATA(pCurr_buff_wptr, para_info->content.RF_REG_W.value); + PHY_PARAMETER_INFO_SET_MASK(pCurr_buff_wptr, para_info->content.RF_REG_W.msk); + PHY_PARAMETER_INFO_SET_MSK_EN(pCurr_buff_wptr, para_info->content.RF_REG_W.msk_en); + pConfig_para_info->value_accumulation += para_info->content.RF_REG_W.value; + pConfig_para_info->offset_accumulation += (para_info->content.RF_REG_W.offset + (para_info->content.RF_REG_W.rf_path << 8)); + break; + case HALMAC_PARAMETER_CMD_DELAY_US: + case HALMAC_PARAMETER_CMD_DELAY_MS: + PHY_PARAMETER_INFO_SET_DELAY_VALUE(pCurr_buff_wptr, para_info->content.DELAY_TIME.delay_time); + break; + case HALMAC_PARAMETER_CMD_END: + *pEnd_cmd = _TRUE; + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, " halmac_send_h2c_phy_parameter_88xx illegal cmd_id!!\n"); + break; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_gen_cfg_para_h2c_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pH2c_buff +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_CONFIG_PARA_INFO pConfig_para_info = &(pHalmac_adapter->config_para_info); + + CFG_PARAMETER_SET_NUM(pH2c_buff, pConfig_para_info->para_num); + + if (_TRUE == pConfig_para_info->full_fifo_mode) { + CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x1); + CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, 0); + } else { + CFG_PARAMETER_SET_INIT_CASE(pH2c_buff, 0x0); + CFG_PARAMETER_SET_PHY_PARAMETER_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + } + + return HALMAC_RET_SUCCESS; +} +HALMAC_RET_STATUS +halmac_send_h2c_run_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DATA_TYPE halmac_data_type +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_run_datapack_88xx!!\n"); + + RUN_DATAPACK_SET_DATAPACK_ID(pH2c_buff, halmac_data_type); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_RUN_DATAPACK; + h2c_header_info.content_size = 4; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_send_bt_coex_cmd_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pBt_buf, + IN u32 bt_size, + IN u8 ack +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_bt_coex_cmd_88xx!!\n"); + + PLATFORM_RTL_MEMCPY(pDriver_adapter, pH2c_buff + 8, pBt_buf, bt_size); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_BT_COEX; + h2c_header_info.content_size = (u16)bt_size; + h2c_header_info.ack = ack; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, ack); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + return status; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_func_ctrl_ch_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_SWITCH_OPTION pCs_option +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + HALMAC_CMD_PROCESS_STATUS *pProcess_status = &(pHalmac_adapter->halmac_state.scan_state_set.process_status); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_ctrl_ch_switch!!\n"); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT)) + return HALMAC_RET_ERROR_STATE; + + *pProcess_status = HALMAC_CMD_PROCESS_SENDING; + + if (0 != pCs_option->switch_en) { + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + + status = halmac_download_rsvd_page_88xx(pHalmac_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.total_size); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "halmac_download_rsvd_page_88xx Fail = %x!!\n", status); + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + return status; + } + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_FIFOPAGE_CTRL_2, (u16)(pHalmac_adapter->txff_allocation.rsvd_pg_bndy & BIT_MASK_BCN_HEAD_1_V1)); + } + + CHANNEL_SWITCH_SET_SWITCH_START(pH2c_buff, pCs_option->switch_en); + CHANNEL_SWITCH_SET_CHANNEL_NUM(pH2c_buff, pHalmac_adapter->ch_sw_info.ch_num); + CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_h2c_extra_info_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + CHANNEL_SWITCH_SET_DEST_CH_EN(pH2c_buff, pCs_option->dest_ch_en); + CHANNEL_SWITCH_SET_DEST_CH(pH2c_buff, pCs_option->dest_ch); + CHANNEL_SWITCH_SET_PRI_CH_IDX(pH2c_buff, pCs_option->dest_pri_ch_idx); + CHANNEL_SWITCH_SET_ABSOLUTE_TIME(pH2c_buff, pCs_option->absolute_time_en); + CHANNEL_SWITCH_SET_TSF_LOW(pH2c_buff, pCs_option->tsf_low); + CHANNEL_SWITCH_SET_PERIODIC_OPTION(pH2c_buff, pCs_option->periodic_option); + CHANNEL_SWITCH_SET_NORMAL_CYCLE(pH2c_buff, pCs_option->normal_cycle); + CHANNEL_SWITCH_SET_NORMAL_PERIOD(pH2c_buff, pCs_option->normal_period); + CHANNEL_SWITCH_SET_SLOW_PERIOD(pH2c_buff, pCs_option->phase_2_period); + CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(pH2c_buff, pHalmac_adapter->ch_sw_info.total_size); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_CHANNEL_SWITCH; + h2c_header_info.content_size = 20; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + pHalmac_adapter->halmac_state.scan_state_set.seq_num = h2c_seq_mum; + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->ch_sw_info.ch_info_buf, pHalmac_adapter->ch_sw_info.buf_size); + pHalmac_adapter->ch_sw_info.ch_info_buf = NULL; + pHalmac_adapter->ch_sw_info.ch_info_buf_w = NULL; + pHalmac_adapter->ch_sw_info.extra_info_en = 0; + pHalmac_adapter->ch_sw_info.buf_size = 0; + pHalmac_adapter->ch_sw_info.avai_buf_size = 0; + pHalmac_adapter->ch_sw_info.total_size = 0; + pHalmac_adapter->ch_sw_info.ch_num = 0; + + if (HALMAC_RET_SUCCESS != halmac_transition_scan_state_88xx(pHalmac_adapter, HALMAC_SCAN_CMD_CONSTRUCT_IDLE)) + return HALMAC_RET_ERROR_STATE; + + return status; +} + +HALMAC_RET_STATUS +halmac_func_send_general_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_GENERAL_INFO pGeneral_info +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_general_info!!\n"); + + GENERAL_INFO_SET_REF_TYPE(pH2c_buff, pGeneral_info->rfe_type); + GENERAL_INFO_SET_RF_TYPE(pH2c_buff, pGeneral_info->rf_type); + GENERAL_INFO_SET_FW_TX_BOUNDARY(pH2c_buff, pHalmac_adapter->txff_allocation.rsvd_fw_txbuff_pg_bndy - pHalmac_adapter->txff_allocation.rsvd_pg_bndy); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_GENERAL_INFO; + h2c_header_info.content_size = 4; + h2c_header_info.ack = _FALSE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail = %x!!\n", status); + + return status; +} + +HALMAC_RET_STATUS +halmac_send_h2c_update_bcn_parse_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_BCN_IE_INFO pBcn_ie_info +) +{ + u8 pH2c_buff[HALMAC_H2C_CMD_SIZE_88XX] = { 0 }; + u16 h2c_seq_mum = 0; + VOID *pDriver_adapter = NULL; + HALMAC_H2C_HEADER_INFO h2c_header_info; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_send_h2c_update_bcn_parse_info_88xx!!\n"); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(pH2c_buff, pBcn_ie_info->func_en); + UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(pH2c_buff, pBcn_ie_info->size_th); + UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(pH2c_buff, pBcn_ie_info->timeout); + + UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[0])); + UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[1])); + UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[2])); + UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[3])); + UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(pH2c_buff, (u32)(pBcn_ie_info->ie_bmp[4])); + + h2c_header_info.sub_cmd_id = SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO; + h2c_header_info.content_size = 24; + h2c_header_info.ack = _TRUE; + halmac_set_fw_offload_h2c_header_88xx(pHalmac_adapter, pH2c_buff, &h2c_header_info, &h2c_seq_mum); + + status = halmac_send_h2c_pkt_88xx(pHalmac_adapter, pH2c_buff, HALMAC_H2C_CMD_SIZE_88XX, _TRUE); + + if (HALMAC_RET_SUCCESS != status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "halmac_send_h2c_pkt_88xx Fail =%x !!\n", status); + return status; + } + + return status; +} + +HALMAC_RET_STATUS +halmac_parse_c2h_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *halmac_buf, + IN u32 halmac_size +) +{ + u8 c2h_cmd, c2h_sub_cmd_id; + u8 *pC2h_buf = halmac_buf + pHalmac_adapter->hw_config_info.rxdesc_size; + u32 c2h_size = halmac_size - pHalmac_adapter->hw_config_info.rxdesc_size; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + /* PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "halmac_parse_c2h_packet_88xx!!\n"); */ + + c2h_cmd = (u8)C2H_HDR_GET_CMD_ID(pC2h_buf); + + /* FW offload C2H cmd is 0xFF */ + if (0xFF != c2h_cmd) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT not for FwOffloadC2HFormat!!\n"); + return HALMAC_RET_C2H_NOT_HANDLED; + } + + /* Get C2H sub cmd ID */ + c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pC2h_buf); + + switch (c2h_sub_cmd_id) { + case C2H_SUB_CMD_ID_C2H_DBG: + status = halmac_parse_c2h_debug_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case C2H_SUB_CMD_ID_H2C_ACK_HDR: + status = halmac_parse_h2c_ack_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case C2H_SUB_CMD_ID_BT_COEX_INFO: + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + case C2H_SUB_CMD_ID_SCAN_STATUS_RPT: + status = halmac_parse_scan_status_rpt_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case C2H_SUB_CMD_ID_PSD_DATA: + status = halmac_parse_psd_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + + case C2H_SUB_CMD_ID_EFUSE_DATA: + status = halmac_parse_efuse_data_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "c2h_sub_cmd_id switch case out of boundary!!\n"); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "[ERR]c2h pkt : %.8X %.8X!!\n", *(u32 *)pC2h_buf, *(u32 *)(pC2h_buf + 4)); + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + } + + return status; +} + +HALMAC_RET_STATUS +halmac_parse_c2h_debug_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + VOID *pDriver_adapter = NULL; + u8 *pC2h_buf_local = (u8 *)NULL; + u32 c2h_size_local = 0; + u8 dbg_content_length = 0; + u8 dbg_seq_num = 0; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pC2h_buf_local = pC2h_buf; + c2h_size_local = c2h_size; + + dbg_content_length = (u8)C2H_HDR_GET_LEN((u8 *)pC2h_buf_local); + + if (dbg_content_length > C2H_DBG_CONTENT_MAX_LENGTH) { + return HALMAC_RET_SUCCESS; + } else { + *(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + dbg_content_length - 2) = '\n'; + dbg_seq_num = (u8)(*(pC2h_buf_local + C2H_DBG_HEADER_LENGTH)); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[RTKFW, SEQ=%d]: %s", dbg_seq_num, (char *)(pC2h_buf_local + C2H_DBG_HEADER_LENGTH + 1)); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_scan_status_rpt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status; + + h2c_return_code = (u8)SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(pC2h_buf); + process_status = (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) ? HALMAC_CMD_PROCESS_DONE : HALMAC_CMD_PROCESS_ERROR; + + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0); + + pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]scan status : %X\n", process_status); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_psd_data_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 segment_id = 0, segment_size = 0, h2c_seq = 0; + u16 total_size; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status; + PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set); + + h2c_seq = (u8)PSD_DATA_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); + if (h2c_seq != pPsd_set->seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pPsd_set->seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pPsd_set->process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + total_size = (u16)PSD_DATA_GET_TOTAL_SIZE(pC2h_buf); + segment_id = (u8)PSD_DATA_GET_SEGMENT_ID(pC2h_buf); + segment_size = (u8)PSD_DATA_GET_SEGMENT_SIZE(pC2h_buf); + pPsd_set->data_size = total_size; + + if (NULL == pPsd_set->pData) + pPsd_set->pData = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, pPsd_set->data_size); + + if (0 == segment_id) + pPsd_set->segment_size = segment_size; + + PLATFORM_RTL_MEMCPY(pDriver_adapter, pPsd_set->pData + segment_id * pPsd_set->segment_size, pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size); + + if (_FALSE == PSD_DATA_GET_END_SEGMENT(pC2h_buf)) + return HALMAC_RET_SUCCESS; + + process_status = HALMAC_CMD_PROCESS_DONE; + pPsd_set->process_status = process_status; + + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_PSD, process_status, pPsd_set->pData, pPsd_set->data_size); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_efuse_data_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 segment_id = 0, segment_size = 0, h2c_seq = 0; + u8 *pEeprom_map = NULL; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + u8 h2c_return_code = 0; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status; + + h2c_seq = (u8)EFUSE_DATA_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.efuse_state_set.process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + segment_id = (u8)EFUSE_DATA_GET_SEGMENT_ID(pC2h_buf); + segment_size = (u8)EFUSE_DATA_GET_SEGMENT_SIZE(pC2h_buf); + if (0 == segment_id) + pHalmac_adapter->efuse_segment_size = segment_size; + + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (NULL == pEeprom_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_RTL_MEMCPY(pDriver_adapter, pHalmac_adapter->pHalEfuse_map + segment_id * pHalmac_adapter->efuse_segment_size, + pC2h_buf + HALMAC_C2H_DATA_OFFSET_88XX, segment_size); + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + + if (_FALSE == EFUSE_DATA_GET_END_SEGMENT(pC2h_buf)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code; + + if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + process_status = HALMAC_CMD_PROCESS_DONE; + pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status; + + PLATFORM_MUTEX_LOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + pHalmac_adapter->hal_efuse_map_valid = _TRUE; + PLATFORM_MUTEX_UNLOCK(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + + if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) { + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); + pHalmac_adapter->event_trigger.physical_efuse_map = 0; + } + + if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) { + if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, pEeprom_map, eeprom_size); + pHalmac_adapter->event_trigger.logical_efuse_map = 0; + } + } else { + process_status = HALMAC_CMD_PROCESS_ERROR; + pHalmac_adapter->halmac_state.efuse_state_set.process_status = process_status; + + if (1 == pHalmac_adapter->event_trigger.physical_efuse_map) { + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1); + pHalmac_adapter->event_trigger.physical_efuse_map = 0; + } + + if (1 == pHalmac_adapter->event_trigger.logical_efuse_map) { + if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, process_status, &(pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code), 1); + pHalmac_adapter->event_trigger.logical_efuse_map = 0; + } + } + + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_cmd_id, h2c_sub_cmd_id; + u8 h2c_seq = 0, offset = 0, shift = 0; + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Ack for C2H!!\n"); + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + if (HALMAC_H2C_RETURN_SUCCESS != (HALMAC_H2C_RETURN_CODE)h2c_return_code) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "C2H_PKT Status Error!! Status = %d\n", h2c_return_code); + + h2c_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_CMD_ID(pC2h_buf); + + if (0xFF != h2c_cmd_id) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "original h2c ack is not handled!!\n"); + status = HALMAC_RET_C2H_NOT_HANDLED; + } else { + h2c_sub_cmd_id = (u8)H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(pC2h_buf); + + switch (h2c_sub_cmd_id) { + case H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK: + status = halmac_parse_h2c_ack_phy_efuse_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_CFG_PARAMETER_ACK: + status = halmac_parse_h2c_ack_cfg_para_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_UPDATE_PACKET_ACK: + status = halmac_parse_h2c_ack_update_packet_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK: + status = halmac_parse_h2c_ack_update_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_RUN_DATAPACK_ACK: + status = halmac_parse_h2c_ack_run_datapack_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK: + status = halmac_parse_h2c_ack_channel_switch_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_IQK_ACK: + status = halmac_parse_h2c_ack_iqk_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_POWER_TRACKING_ACK: + status = halmac_parse_h2c_ack_power_tracking_88xx(pHalmac_adapter, pC2h_buf, c2h_size); + break; + case H2C_SUB_CMD_ID_PSD_ACK: + break; + default: + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_WARN, "h2c_sub_cmd_id switch case out of boundary!!\n"); + status = HALMAC_RET_C2H_NOT_HANDLED; + break; + } + } + + return status; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_phy_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_seq = 0; + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.efuse_state_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.efuse_state_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.efuse_state_set.process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + pHalmac_adapter->halmac_state.efuse_state_set.fw_return_code = h2c_return_code; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_cfg_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_seq = 0; + u8 h2c_return_code; + u32 offset_accu = 0, value_accu = 0; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + + h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.cfg_para_state_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.cfg_para_state_set.process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code = h2c_return_code; + offset_accu = CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(pC2h_buf); + value_accu = CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(pC2h_buf); + + if ((offset_accu != pHalmac_adapter->config_para_info.offset_accumulation) || (value_accu != pHalmac_adapter->config_para_info.value_accumulation)) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[C2H]offset_accu : %x, value_accu : %x!!\n", offset_accu, value_accu); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[Adapter]offset_accu : %x, value_accu : %x!!\n", pHalmac_adapter->config_para_info.offset_accumulation, pHalmac_adapter->config_para_info.value_accumulation); + process_status = HALMAC_CMD_PROCESS_ERROR; + } + + if ((HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) && (HALMAC_CMD_PROCESS_ERROR != process_status)) { + process_status = HALMAC_CMD_PROCESS_DONE; + pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, NULL, 0); + } else { + process_status = HALMAC_CMD_PROCESS_ERROR; + pHalmac_adapter->halmac_state.cfg_para_state_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CFG_PARA, process_status, &(pHalmac_adapter->halmac_state.cfg_para_state_set.fw_return_code), 1); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_update_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_seq = 0; + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status; + + h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.update_packet_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.update_packet_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.update_packet_set.process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + pHalmac_adapter->halmac_state.update_packet_set.fw_return_code = h2c_return_code; + + if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + process_status = HALMAC_CMD_PROCESS_DONE; + pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, NULL, 0); + } else { + process_status = HALMAC_CMD_PROCESS_ERROR; + pHalmac_adapter->halmac_state.update_packet_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_PACKET, process_status, &(pHalmac_adapter->halmac_state.update_packet_set.fw_return_code), 1); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_update_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_UPDATE_DATAPACK, process_status, NULL, 0); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_run_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status = HALMAC_CMD_PROCESS_UNDEFINE; + + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_RUN_DATAPACK, process_status, NULL, 0); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_channel_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_seq = 0; + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status; + + h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.scan_state_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.scan_state_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.scan_state_set.process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + pHalmac_adapter->halmac_state.scan_state_set.fw_return_code = h2c_return_code; + + if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + process_status = HALMAC_CMD_PROCESS_RCVD; + pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, NULL, 0); + } else { + process_status = HALMAC_CMD_PROCESS_ERROR; + pHalmac_adapter->halmac_state.scan_state_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_CHANNEL_SWITCH, process_status, &(pHalmac_adapter->halmac_state.scan_state_set.fw_return_code), 1); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_iqk_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_seq = 0; + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status; + + h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.iqk_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.iqk_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.iqk_set.process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + pHalmac_adapter->halmac_state.iqk_set.fw_return_code = h2c_return_code; + + if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + process_status = HALMAC_CMD_PROCESS_DONE; + pHalmac_adapter->halmac_state.iqk_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, NULL, 0); + } else { + process_status = HALMAC_CMD_PROCESS_ERROR; + pHalmac_adapter->halmac_state.iqk_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_IQK, process_status, &(pHalmac_adapter->halmac_state.iqk_set.fw_return_code), 1); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_h2c_ack_power_tracking_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pC2h_buf, + IN u32 c2h_size +) +{ + u8 h2c_seq = 0; + u8 h2c_return_code; + VOID *pDriver_adapter = pHalmac_adapter->pDriver_adapter; + HALMAC_CMD_PROCESS_STATUS process_status; + + h2c_seq = (u8)H2C_ACK_HDR_GET_H2C_SEQ(pC2h_buf); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_TRACE, "[TRACE]Seq num : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); + if (h2c_seq != pHalmac_adapter->halmac_state.power_tracking_set.seq_num) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Seq num mismactch : h2c -> %d c2h -> %d\n", pHalmac_adapter->halmac_state.power_tracking_set.seq_num, h2c_seq); + return HALMAC_RET_SUCCESS; + } + + if (HALMAC_CMD_PROCESS_SENDING != pHalmac_adapter->halmac_state.power_tracking_set.process_status) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "[ERR]Not in HALMAC_CMD_PROCESS_SENDING\n"); + return HALMAC_RET_SUCCESS; + } + + h2c_return_code = (u8)H2C_ACK_HDR_GET_H2C_RETURN_CODE(pC2h_buf); + pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code = h2c_return_code; + + if (HALMAC_H2C_RETURN_SUCCESS == (HALMAC_H2C_RETURN_CODE)h2c_return_code) { + process_status = HALMAC_CMD_PROCESS_DONE; + pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, NULL, 0); + } else { + process_status = HALMAC_CMD_PROCESS_ERROR; + pHalmac_adapter->halmac_state.power_tracking_set.process_status = process_status; + PLATFORM_EVENT_INDICATION(pDriver_adapter, HALMAC_FEATURE_POWER_TRACKING, process_status, &(pHalmac_adapter->halmac_state.power_tracking_set.fw_return_code), 1); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_update_oqt_free_space_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + PHALMAC_SDIO_FREE_SPACE pSdio_free_space; + u8 value; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx ==========>\n"); + + pSdio_free_space = &(pHalmac_adapter->sdio_free_space); + + pSdio_free_space->ac_oqt_number = HALMAC_REG_READ_8(pHalmac_adapter, REG_SDIO_OQT_FREE_TXPG_V1 + 2); + /* pSdio_free_space->non_ac_oqt_number = (u8)BIT_GET_NOAC_OQT_FREEPG_V1(oqt_free_page); */ + pSdio_free_space->ac_empty = 0; + value = HALMAC_REG_READ_8(pHalmac_adapter, REG_TXPKT_EMPTY); + while (value > 0) { + value = value & (value - 1); + pSdio_free_space->ac_empty++; + }; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_update_oqt_free_space_88xx <==========\n"); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_EFUSE_CMD_CONSTRUCT_STATE +halmac_query_efuse_curr_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + return pHalmac_adapter->halmac_state.efuse_state_set.efuse_cmd_construct_state; +} + +HALMAC_RET_STATUS +halmac_transition_efuse_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state +) +{ + PHALMAC_EFUSE_STATE_SET pEfuse_state = &(pHalmac_adapter->halmac_state.efuse_state_set); + + if ((HALMAC_EFUSE_CMD_CONSTRUCT_IDLE != pEfuse_state->efuse_cmd_construct_state) + && (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY != pEfuse_state->efuse_cmd_construct_state) + && (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT != pEfuse_state->efuse_cmd_construct_state)) + return HALMAC_RET_ERROR_STATE; + + if (pEfuse_state->efuse_cmd_construct_state == dest_state) + return HALMAC_RET_ERROR_STATE; + + if (HALMAC_EFUSE_CMD_CONSTRUCT_BUSY == dest_state) { + if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == pEfuse_state->efuse_cmd_construct_state) + return HALMAC_RET_ERROR_STATE; + } else if (HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT == dest_state) { + if (HALMAC_EFUSE_CMD_CONSTRUCT_IDLE == pEfuse_state->efuse_cmd_construct_state) + return HALMAC_RET_ERROR_STATE; + } + + pEfuse_state->efuse_cmd_construct_state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE +halmac_query_cfg_para_curr_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + return pHalmac_adapter->halmac_state.cfg_para_state_set.cfg_para_cmd_construct_state; +} + +HALMAC_RET_STATUS +halmac_transition_cfg_para_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state +) +{ + PHALMAC_CFG_PARA_STATE_SET pCfg_para = &(pHalmac_adapter->halmac_state.cfg_para_state_set); + + if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE != pCfg_para->cfg_para_cmd_construct_state) && + (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING != pCfg_para->cfg_para_cmd_construct_state) && + (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT != pCfg_para->cfg_para_cmd_construct_state)) + return HALMAC_RET_ERROR_STATE; + + if (HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == dest_state) { + if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == pCfg_para->cfg_para_cmd_construct_state) + return HALMAC_RET_ERROR_STATE; + } else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING == dest_state) { + if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state) + return HALMAC_RET_ERROR_STATE; + } else if (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == dest_state) { + if ((HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE == pCfg_para->cfg_para_cmd_construct_state) + || (HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT == pCfg_para->cfg_para_cmd_construct_state)) + return HALMAC_RET_ERROR_STATE; + } + + pCfg_para->cfg_para_cmd_construct_state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_SCAN_CMD_CONSTRUCT_STATE +halmac_query_scan_curr_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + return pHalmac_adapter->halmac_state.scan_state_set.scan_cmd_construct_state; +} + +HALMAC_RET_STATUS +halmac_transition_scan_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state +) +{ + PHALMAC_SCAN_STATE_SET pScan = &(pHalmac_adapter->halmac_state.scan_state_set); + + if (pScan->scan_cmd_construct_state > HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT) + return HALMAC_RET_ERROR_STATE; + + if (HALMAC_SCAN_CMD_CONSTRUCT_IDLE == dest_state) { + if ((HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == pScan->scan_cmd_construct_state) || + (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == pScan->scan_cmd_construct_state)) + return HALMAC_RET_ERROR_STATE; + } else if (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED == dest_state) { + if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state) + return HALMAC_RET_ERROR_STATE; + } else if (HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING == dest_state) { + if ((HALMAC_SCAN_CMD_CONSTRUCT_IDLE == pScan->scan_cmd_construct_state) || + (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == pScan->scan_cmd_construct_state)) + return HALMAC_RET_ERROR_STATE; + } else if (HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT == dest_state) { + if ((HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING != pScan->scan_cmd_construct_state) && + (HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED != pScan->scan_cmd_construct_state)) + return HALMAC_RET_ERROR_STATE; + } + + pScan->scan_cmd_construct_state = dest_state; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_cfg_para_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + PHALMAC_CFG_PARA_STATE_SET pCfg_para_state_set = &(pHalmac_adapter->halmac_state.cfg_para_state_set); + + *pProcess_status = pCfg_para_state_set->process_status; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_dump_physical_efuse_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + *pProcess_status = pEfuse_state_set->process_status; + + if (NULL == data) + return HALMAC_RET_NULL_POINTER; + + if (NULL == size) + return HALMAC_RET_NULL_POINTER; + + if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) { + if (*size < pHalmac_adapter->hw_config_info.efuse_size) { + *size = pHalmac_adapter->hw_config_info.efuse_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = pHalmac_adapter->hw_config_info.efuse_size; + PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pHalmac_adapter->pHalEfuse_map, *size); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_dump_logical_efuse_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + u8 *pEeprom_map = NULL; + u32 eeprom_size = pHalmac_adapter->hw_config_info.eeprom_size; + VOID *pDriver_adapter = NULL; + PHALMAC_EFUSE_STATE_SET pEfuse_state_set = &(pHalmac_adapter->halmac_state.efuse_state_set); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + *pProcess_status = pEfuse_state_set->process_status; + + if (NULL == data) + return HALMAC_RET_NULL_POINTER; + + if (NULL == size) + return HALMAC_RET_NULL_POINTER; + + if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) { + if (*size < eeprom_size) { + *size = eeprom_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = eeprom_size; + + pEeprom_map = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, eeprom_size); + if (NULL == pEeprom_map) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_EFUSE, HALMAC_DBG_ERR, "[ERR]halmac allocate local eeprom map Fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + PLATFORM_RTL_MEMSET(pDriver_adapter, pEeprom_map, 0xFF, eeprom_size); + + if (HALMAC_RET_SUCCESS != halmac_eeprom_parser_88xx(pHalmac_adapter, pHalmac_adapter->pHalEfuse_map, pEeprom_map)) { + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + return HALMAC_RET_EEPROM_PARSING_FAIL; + } + + PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pEeprom_map, *size); + + PLATFORM_RTL_FREE(pDriver_adapter, pEeprom_map, eeprom_size); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_channel_switch_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + PHALMAC_SCAN_STATE_SET pScan_state_set = &(pHalmac_adapter->halmac_state.scan_state_set); + + *pProcess_status = pScan_state_set->process_status; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_update_packet_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + PHALMAC_UPDATE_PACKET_STATE_SET pUpdate_packet_set = &(pHalmac_adapter->halmac_state.update_packet_set); + + *pProcess_status = pUpdate_packet_set->process_status; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_iqk_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + PHALMAC_IQK_STATE_SET pIqk_set = &(pHalmac_adapter->halmac_state.iqk_set); + + *pProcess_status = pIqk_set->process_status; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_power_tracking_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + PHALMAC_POWER_TRACKING_STATE_SET pPower_tracking_state_set = &(pHalmac_adapter->halmac_state.power_tracking_set);; + + *pProcess_status = pPower_tracking_state_set->process_status; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_query_psd_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_PSD_STATE_SET pPsd_set = &(pHalmac_adapter->halmac_state.psd_set); + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + *pProcess_status = pPsd_set->process_status; + + if (NULL == data) + return HALMAC_RET_NULL_POINTER; + + if (NULL == size) + return HALMAC_RET_NULL_POINTER; + + if (HALMAC_CMD_PROCESS_DONE == *pProcess_status) { + if (*size < pPsd_set->data_size) { + *size = pPsd_set->data_size; + return HALMAC_RET_BUFFER_TOO_SMALL; + } + + *size = pPsd_set->data_size; + PLATFORM_RTL_MEMCPY(pDriver_adapter, data, pPsd_set->pData, *size); + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_verify_io_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 value8, wvalue8; + u32 value32, value32_2, wvalue32; + u32 halmac_offset; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + wvalue32 = 0x77665511; + PLATFORM_REG_WRITE_32(pDriver_adapter, REG_PAGE5_DUMMY, wvalue32); + + value32 = PLATFORM_REG_READ_32(pDriver_adapter, REG_PAGE5_DUMMY); + if (value32 != wvalue32) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "reg rw\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "reg rw ok\n"); + } + + return ret_status; +} + +HALMAC_RET_STATUS +halmac_verify_send_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + u8 *rsvd_buf = NULL; + u8 *rsvd_page = NULL; + u32 i; + u32 h2c_pkt_verify_size = 64, h2c_pkt_verify_payload = 0xab; + VOID *pDriver_adapter = NULL; + HALMAC_RET_STATUS ret_status = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + rsvd_buf = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size); + + if (NULL == rsvd_buf) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd buffer malloc fail!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + + PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_buf, (u8)h2c_pkt_verify_payload, h2c_pkt_verify_size); + + ret_status = halmac_download_rsvd_page_88xx(pHalmac_adapter, rsvd_buf, h2c_pkt_verify_size); + + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); + return ret_status; + } + + rsvd_page = (u8 *)PLATFORM_RTL_MALLOC(pDriver_adapter, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); + + if (NULL == rsvd_page) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]rsvd page malloc fail!!\n"); + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); + return HALMAC_RET_MALLOC_FAIL; + } + + PLATFORM_RTL_MEMSET(pDriver_adapter, rsvd_page, 0x00, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); + + ret_status = halmac_dump_fifo_88xx(pHalmac_adapter, HAL_FIFO_SEL_RSVD_PAGE, 0, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size, rsvd_page); + + if (HALMAC_RET_SUCCESS != ret_status) { + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); + return ret_status; + } + + for (i = 0; i < h2c_pkt_verify_size; i++) { + if (*(rsvd_buf + i) != *(rsvd_page + (i + pHalmac_adapter->hw_config_info.txdesc_size))) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "[ERR]Compare RSVD page Fail\n"); + ret_status = HALMAC_RET_PLATFORM_API_INCORRECT; + } + } + + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_buf, h2c_pkt_verify_size); + PLATFORM_RTL_FREE(pDriver_adapter, rsvd_page, h2c_pkt_verify_size + pHalmac_adapter->hw_config_info.txdesc_size); + + return ret_status; +} + +HALMAC_RET_STATUS +halmac_buffer_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u32 size, + IN HAL_FIFO_SEL halmac_fifo_sel, + OUT u8 *pFifo_map +) +{ + u32 start_page, value_read; + u32 i, counter = 0, residue; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel) + offset = offset + (pHalmac_adapter->txff_allocation.rsvd_pg_bndy << HALMAC_TX_PAGE_SIZE_2_POWER_88XX); + + start_page = offset >> 12; + residue = offset & (4096 - 1); + + if ((HAL_FIFO_SEL_TX == halmac_fifo_sel) || (HAL_FIFO_SEL_RSVD_PAGE == halmac_fifo_sel)) + start_page += 0x780; + else if (HAL_FIFO_SEL_RX == halmac_fifo_sel) + start_page += 0x700; + else if (HAL_FIFO_SEL_REPORT == halmac_fifo_sel) + start_page += 0x660; + else if (HAL_FIFO_SEL_LLT == halmac_fifo_sel) + start_page += 0x650; + else + return HALMAC_RET_NOT_SUPPORT; + + value_read = HALMAC_REG_READ_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL); + + do { + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)(start_page | (value_read & 0xF000))); + + for (i = 0x8000 + residue; i <= 0x8FFF; i += 4) { + *(u32 *)(pFifo_map + counter) = HALMAC_REG_READ_32(pHalmac_adapter, i); + *(u32 *)(pFifo_map + counter) = rtk_le32_to_cpu(*(u32 *)(pFifo_map + counter)); + counter += 4; + if (size == counter) + goto HALMAC_BUF_READ_OK; + } + + residue = 0; + start_page++; + } while (1); + +HALMAC_BUF_READ_OK: + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_PKTBUF_DBG_CTRL, (u16)value_read); + + return HALMAC_RET_SUCCESS; +} + +VOID +halmac_restore_mac_register_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_RESTORE_INFO pRestore_info, + IN u32 restore_num +) +{ + u8 value_length; + u32 i; + u32 mac_register; + u32 mac_value; + PHALMAC_API pHalmac_api; + PHALMAC_RESTORE_INFO pCurr_restore_info = pRestore_info; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + for (i = 0; i < restore_num; i++) { + mac_register = pCurr_restore_info->mac_register; + mac_value = pCurr_restore_info->value; + value_length = pCurr_restore_info->length; + + if (1 == value_length) + HALMAC_REG_WRITE_8(pHalmac_adapter, mac_register, (u8)mac_value); + else if (2 == value_length) + HALMAC_REG_WRITE_16(pHalmac_adapter, mac_register, (u16)mac_value); + else if (4 == value_length) + HALMAC_REG_WRITE_32(pHalmac_adapter, mac_register, mac_value); + + pCurr_restore_info++; + } +} + +VOID +halmac_api_record_id_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_API_ID api_id +) +{ + +} + +HALMAC_RET_STATUS +halmac_set_usb_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_USB_MODE usb_mode +) +{ + u32 usb_temp; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + HALMAC_USB_MODE current_usb_mode; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + current_usb_mode = (HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_CFG2 + 3) == 0x20) ? HALMAC_USB_MODE_U3 : HALMAC_USB_MODE_U2; + + /*check if HW supports usb2_usb3 swtich*/ + usb_temp = HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2); + if (_FALSE == (BIT_GET_USB23_SW_MODE_V1(usb_temp) | (usb_temp & BIT_USB3_USB2_TRANSITION))) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode HW unsupport\n"); + return HALMAC_RET_USB2_3_SWITCH_UNSUPPORT; + } + + if (usb_mode == current_usb_mode) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_H2C, HALMAC_DBG_ERR, "HALMAC_HW_USB_MODE usb mode unchange\n"); + return HALMAC_RET_USB_MODE_UNCHANGE; + } + + usb_temp &= ~(BIT_USB23_SW_MODE_V1(0x3)); + + if (HALMAC_USB_MODE_U2 == usb_mode) { + /* usb3 to usb2 */ + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U2) | BIT_RSM_EN_V1); + } else { + /* usb2 to usb3 */ + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, usb_temp | BIT_USB23_SW_MODE_V1(HALMAC_USB_MODE_U3) | BIT_RSM_EN_V1); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PAD_CTRL2 + 1, 4); /* set counter down timer 4x64 ms */ + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_SYS_PW_CTRL, HALMAC_REG_READ_16(pHalmac_adapter, REG_SYS_PW_CTRL) | BIT_APFM_OFFMAC); + PLATFORM_RTL_DELAY_US(pDriver_adapter, 1000); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_PAD_CTRL2, HALMAC_REG_READ_32(pHalmac_adapter, REG_PAD_CTRL2) | BIT_NO_PDN_CHIPOFF_V1); + + return HALMAC_RET_SUCCESS; +} + +VOID +halmac_enable_bb_rf_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable +) +{ + u8 value8; + u32 value32; + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (1 == enable) { + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); + value8 = value8 | BIT(0) | BIT(1); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); + value8 = value8 | BIT(0) | BIT(1) | BIT(2); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); + value32 = value32 | BIT(24) | BIT(25) | BIT(26); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); + } else { + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_SYS_FUNC_EN); + value8 = value8 & (~(BIT(0) | BIT(1))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_SYS_FUNC_EN, value8); + + value8 = HALMAC_REG_READ_8(pHalmac_adapter, REG_RF_CTRL); + value8 = value8 & (~(BIT(0) | BIT(1) | BIT(2))); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_RF_CTRL, value8); + + value32 = HALMAC_REG_READ_32(pHalmac_adapter, REG_WLRF1); + value32 = value32 & (~(BIT(24) | BIT(25) | BIT(26))); + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_WLRF1, value32); + } +} + +VOID +halmac_config_sdio_tx_page_threshold_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info +) +{ + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (pThreshold_info->dma_queue_sel) { + case HALMAC_MAP2_HQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT1, pThreshold_info->threshold); + break; + case HALMAC_MAP2_NQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT2, pThreshold_info->threshold); + break; + case HALMAC_MAP2_LQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT3, pThreshold_info->threshold); + break; + case HALMAC_MAP2_EXQ: + HALMAC_REG_WRITE_32(pHalmac_adapter, REG_TQPNT4, pThreshold_info->threshold); + break; + default: + break; + } +} + +VOID +halmac_config_ampdu_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_AMPDU_CONFIG pAmpdu_config +) +{ + PHALMAC_API pHalmac_api; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 2, pAmpdu_config->max_agg_num); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PROT_MODE_CTRL + 3, pAmpdu_config->max_agg_num); +}; + +HALMAC_RET_STATUS +halmac_rqpn_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_RQPN pRqpn_table +) +{ + u8 search_flag; + u32 i; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + search_flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (halmac_trx_mode == pRqpn_table[i].mode) { + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VO] = pRqpn_table[i].dma_map_vo; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_VI] = pRqpn_table[i].dma_map_vi; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BE] = pRqpn_table[i].dma_map_be; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_BK] = pRqpn_table[i].dma_map_bk; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_MG] = pRqpn_table[i].dma_map_mg; + pHalmac_adapter->halmac_ptcl_queue[HALMAC_PTCL_QUEUE_HI] = pRqpn_table[i].dma_map_hi; + search_flag = 1; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_rqpn_parser_88xx done\n"); + break; + } + } + + if (0 == search_flag) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_pg_num_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_PG_NUM pPg_num_table +) +{ + u8 search_flag; + u16 HPQ_num = 0, LPQ_Nnum = 0, NPQ_num = 0, GAPQ_num = 0; + u16 EXPQ_num = 0, PUBQ_num = 0; + u32 i = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + search_flag = 0; + for (i = 0; i < HALMAC_TRX_MODE_MAX; i++) { + if (halmac_trx_mode == pPg_num_table[i].mode) { + HPQ_num = pPg_num_table[i].hq_num; + LPQ_Nnum = pPg_num_table[i].lq_num; + NPQ_num = pPg_num_table[i].nq_num; + EXPQ_num = pPg_num_table[i].exq_num; + GAPQ_num = pPg_num_table[i].gap_num; + PUBQ_num = pHalmac_adapter->txff_allocation.ac_q_pg_num - HPQ_num - LPQ_Nnum - NPQ_num - EXPQ_num - GAPQ_num; + search_flag = 1; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_pg_num_parser_88xx done\n"); + break; + } + } + + if (0 == search_flag) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_TRX_MODE_NOT_SUPPORT 1 switch case not support\n"); + return HALMAC_RET_TRX_MODE_NOT_SUPPORT; + } + + if (pHalmac_adapter->txff_allocation.ac_q_pg_num < HPQ_num + LPQ_Nnum + NPQ_num + EXPQ_num + GAPQ_num) + return HALMAC_RET_CFG_TXFIFO_PAGE_FAIL; + + pHalmac_adapter->txff_allocation.high_queue_pg_num = HPQ_num; + pHalmac_adapter->txff_allocation.low_queue_pg_num = LPQ_Nnum; + pHalmac_adapter->txff_allocation.normal_queue_pg_num = NPQ_num; + pHalmac_adapter->txff_allocation.extra_queue_pg_num = EXPQ_num; + pHalmac_adapter->txff_allocation.pub_queue_pg_num = PUBQ_num; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_parse_intf_phy_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_INTF_PHY_PARA pIntf_phy_para, + IN HALMAC_INTF_PHY_PLATFORM platform, + IN HAL_INTF_PHY intf_phy +) +{ + u16 value; + u16 curr_cut; + u16 offset; + u16 ip_sel; + PHALMAC_INTF_PHY_PARA pCurr_phy_para; + PHALMAC_API pHalmac_api; + VOID *pDriver_adapter = NULL; + u8 result = HALMAC_RET_SUCCESS; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + switch (pHalmac_adapter->chip_version) { + case HALMAC_CHIP_VER_A_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_A; + break; + case HALMAC_CHIP_VER_B_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_B; + break; + case HALMAC_CHIP_VER_C_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_C; + break; + case HALMAC_CHIP_VER_D_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_D; + break; + case HALMAC_CHIP_VER_E_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_E; + break; + case HALMAC_CHIP_VER_F_CUT: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_F; + break; + case HALMAC_CHIP_VER_TEST: + curr_cut = (u16)HALMAC_INTF_PHY_CUT_TESTCHIP; + break; + default: + return HALMAC_RET_FAIL; + } + + pCurr_phy_para = pIntf_phy_para; + + do { + if ((pCurr_phy_para->cut & curr_cut) && (pCurr_phy_para->plaform & (u16)platform)) { + offset = pCurr_phy_para->offset; + value = pCurr_phy_para->value; + ip_sel = pCurr_phy_para->ip_sel; + + if (0xFFFF == offset) + break; + + if (HALMAC_IP_SEL_MAC == ip_sel) { + HALMAC_REG_WRITE_8(pHalmac_adapter, (u32)offset, (u8)value); + } else if (HAL_INTF_PHY_USB2 == intf_phy) { + + result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB2); + + if (HALMAC_RET_SUCCESS != result) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB2PHY fail!\n"); + + } else if (HAL_INTF_PHY_USB3 == intf_phy) { + + result = halmac_usbphy_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_USB3); + + if (HALMAC_RET_SUCCESS != result) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Write USB3PHY fail!\n"); + + } else if (HAL_INTF_PHY_PCIE_GEN1 == intf_phy) { + + if (HALMAC_IP_SEL_INTF_PHY == ip_sel) + result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN1); + else + result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value); + + if (HALMAC_RET_SUCCESS != result) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN1 fail!\n"); + + } else if (HAL_INTF_PHY_PCIE_GEN2 == intf_phy) { + + if (HALMAC_IP_SEL_INTF_PHY == ip_sel) + result = halmac_mdio_write_88xx(pHalmac_adapter, (u8)offset, value, HAL_INTF_PHY_PCIE_GEN2); + else + result = halmac_dbi_write8_88xx(pHalmac_adapter, offset, (u8)value); + + if (HALMAC_RET_SUCCESS != result) + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "[ERR]MDIO write GEN2 fail!\n"); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_COMMON, HALMAC_DBG_ERR, "[ERR]Parse intf phy cfg error!\n"); + } + + } + pCurr_phy_para++; + } while (1); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_dbi_write8_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr, + IN u8 data +) +{ + u8 tmp_u1b = 0; + u32 count = 0; + u16 write_addr = 0; + u16 remainder = addr & (4 - 1); + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; ; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_WDATA_V1 + remainder, data); + + write_addr = ((addr & 0x0ffc) | (BIT(0) << (remainder + 12))); + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_DBI_FLAG_V1, write_addr); + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_TRACE, "WriteAddr = %x\n", write_addr); + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2, 0x01); + + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1 + 2); + + count = 20; + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_DBI_FLAG_V1+2); + count--; + } + + if (tmp_u1b) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_DBI, HALMAC_DBG_ERR, "DBI write fail!\n"); + return HALMAC_RET_FAIL; + } else { + + return HALMAC_RET_SUCCESS; + } + +} + +HALMAC_RET_STATUS +halmac_mdio_write_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u16 data, + IN u8 speed +) +{ + u8 tmp_u1b = 0; + u32 count = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 real_addr = 0; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + HALMAC_REG_WRITE_16(pHalmac_adapter, REG_MDIO_V1, data); + + /* address : 5bit */ + real_addr = (addr & 0x1F); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr); + + if (HAL_INTF_PHY_PCIE_GEN1 == speed) { + + /* GEN1 page 0 */ + if (addr < 0x20) { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b00 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00); + + /* GEN1 page 1 */ + } else { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b01 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01); + } + + } else if (HAL_INTF_PHY_PCIE_GEN2 == speed) { + + /* GEN2 page 0 */ + if (addr < 0x20) { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b10 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02); + + /* GEN2 page 1 */ + } else { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b11 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03); + } + } else { + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n"); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_WFLAG_V1); + + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1 ; + count = 20; + + while (tmp_u1b && (count != 0)) { + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_WFLAG_V1; + count--; + } + + if (tmp_u1b) { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO write fail!\n"); + return HALMAC_RET_FAIL; + } else { + + return HALMAC_RET_SUCCESS; + } + +} + +u16 +halmac_mdio_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u8 speed + +) +{ + u16 ret = 0; + u8 tmp_u1b = 0; + u32 count = 0; + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + u8 real_addr = 0; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + /* address : 5bit */ + real_addr = (addr & 0x1F); + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, real_addr); + + if (HAL_INTF_PHY_PCIE_GEN1 == speed) { + /* GEN1 page 0 */ + if (addr < 0x20) { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b00 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x00); + + /* GEN1 page 1 */ + } else { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b01 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x01); + } + + } else if (HAL_INTF_PHY_PCIE_GEN2 == speed) { + + /* GEN2 page 0 */ + if (addr < 0x20) { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b10 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x02); + + /* GEN2 page 1 */ + } else { + + /* select MDIO PHY Addr : reg 0x3F8[28:24]=5'b11 */ + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG + 3, 0x03); + } + } else { + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "Error Speed !\n"); + } + + HALMAC_REG_WRITE_8(pHalmac_adapter, REG_PCIE_MIX_CFG, HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) | BIT_MDIO_RFLAG_V1); + + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1 ; + count = 20; + + while (tmp_u1b && (count != 0)) { + + PLATFORM_RTL_DELAY_US(pDriver_adapter, 10); + tmp_u1b = HALMAC_REG_READ_8(pHalmac_adapter, REG_PCIE_MIX_CFG) & BIT_MDIO_RFLAG_V1; + count--; + } + + if (tmp_u1b) { + ret = 0xFFFF; + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_ERR, "MDIO read fail!\n"); + + } else { + ret = HALMAC_REG_READ_16(pHalmac_adapter, REG_MDIO_V1+2); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_MDIO, HALMAC_DBG_TRACE, "Read Value = %x\n", ret); + } + + return ret; +} + +HALMAC_RET_STATUS +halmac_usbphy_write_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u16 data, + IN u8 speed +) +{ + VOID *pDriver_adapter = NULL; + PHALMAC_API pHalmac_api; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + if (HAL_INTF_PHY_USB3 == speed) { + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0d, (u8)data); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0e, (u8)(data>>8)); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xff0c, addr|BIT(7)); + } else if (HAL_INTF_PHY_USB2 == speed) { + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe41, (u8)data); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe40, addr); + HALMAC_REG_WRITE_8(pHalmac_adapter, 0xfe42, 0x81); + } else { + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_USB, HALMAC_DBG_ERR, "[ERR]Error USB Speed !\n"); + return HALMAC_RET_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h new file mode 100644 index 000000000000..f6d6edbfffb4 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_88xx/halmac_func_88xx.h @@ -0,0 +1,523 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_FUNC_88XX_H_ +#define _HALMAC_FUNC_88XX_H_ + +#include "../halmac_type.h" + +VOID +halmac_init_offload_feature_state_machine_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_send_h2c_pkt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHal_buff, + IN u32 size, + IN u8 ack +); + +HALMAC_RET_STATUS +halmac_download_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHal_buf, + IN u32 size +); + +HALMAC_RET_STATUS +halmac_set_h2c_header_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u8 *pHal_h2c_hdr, + IN u16 *seq, + IN u8 ack +); + +HALMAC_RET_STATUS +halmac_set_fw_offload_h2c_header_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT u8 *pHal_h2c_hdr, + IN PHALMAC_H2C_HEADER_INFO pH2c_header_info, + OUT u16 *pSeq_num +); + +HALMAC_RET_STATUS +halmac_dump_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_READ_CFG cfg +); + +HALMAC_RET_STATUS +halmac_func_read_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u32 size, + OUT u8 *pEfuse_map +); + +HALMAC_RET_STATUS +halmac_func_write_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u8 value +); + +HALMAC_RET_STATUS +halmac_func_switch_efuse_bank_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_BANK efuse_bank +); + +HALMAC_RET_STATUS +halmac_read_logical_efuse_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pMap +); + +HALMAC_RET_STATUS +halmac_func_write_logical_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u8 value +); + +HALMAC_RET_STATUS +halmac_func_pg_efuse_by_map_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PG_EFUSE_INFO pPg_efuse_info, + IN HALMAC_EFUSE_READ_CFG cfg +); + +HALMAC_RET_STATUS +halmac_eeprom_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pPhysical_efuse_map, + OUT u8 *pLogical_efuse_map +); + +HALMAC_RET_STATUS +halmac_read_hw_efuse_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u32 size, + OUT u8 *pEfuse_map +); + +HALMAC_RET_STATUS +halmac_update_fw_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pHamacl_fw, + IN u32 halmac_fw_size +); + +HALMAC_RET_STATUS +halmac_dlfw_to_mem_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pRam_code, + IN u32 dest, + IN u32 code_size +); + +HALMAC_RET_STATUS +halmac_send_fwpkt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pRam_code, + IN u32 code_size +); + +HALMAC_RET_STATUS +halmac_iddma_dlfw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 source, + IN u32 dest, + IN u32 length, + IN u8 first +); + +HALMAC_RET_STATUS +halmac_check_fw_chksum_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 memory_address +); + +HALMAC_RET_STATUS +halmac_dlfw_end_flow_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_free_dl_fw_end_flow_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_pwr_seq_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 cut, + IN u8 fab, + IN u8 intf, + IN PHALMAC_WLAN_PWR_CFG *ppPwr_seq_cfg + +); + +HALMAC_RET_STATUS +halmac_get_h2c_buff_free_space_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_send_h2c_set_pwr_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_FWLPS_OPTION pHal_FwLps_Opt +); + +HALMAC_RET_STATUS +halmac_func_send_original_h2c_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *original_h2c, + IN u16 *seq, + IN u8 ack +); + +HALMAC_RET_STATUS +halmac_media_status_rpt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 op_mode, + IN u8 mac_id_ind, + IN u8 mac_id, + IN u8 mac_id_end +); + +HALMAC_RET_STATUS +halmac_send_h2c_update_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DATA_TYPE halmac_data_type, + IN PHALMAC_PHY_PARAMETER_INFO para_info +); + +HALMAC_RET_STATUS +halmac_send_h2c_run_datapack_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_DATA_TYPE halmac_data_type +); + +HALMAC_RET_STATUS +halmac_send_bt_coex_cmd_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *pBt_buf, + IN u32 bt_size, + IN u8 ack +); + +HALMAC_RET_STATUS +halmac_func_ctrl_ch_switch_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_CH_SWITCH_OPTION pCs_option +); + +HALMAC_RET_STATUS +halmac_func_send_general_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_GENERAL_INFO pGeneral_info +); + +HALMAC_RET_STATUS +halmac_send_h2c_ps_tuning_para_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_parse_c2h_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 *halmac_buf, + IN u32 halmac_size +); + +HALMAC_RET_STATUS +halmac_send_h2c_update_packet_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_PACKET_ID pkt_id, + IN u8 *pkt, + IN u32 pkt_size +); + +HALMAC_RET_STATUS +halmac_send_h2c_phy_parameter_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_PHY_PARAMETER_INFO para_info, + IN u8 full_fifo +); + +HALMAC_RET_STATUS +halmac_dump_physical_efuse_fw_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u32 Size, + OUT u8 *pEfuse_map +); + +HALMAC_RET_STATUS +halmac_send_h2c_update_bcn_parse_info_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_BCN_IE_INFO pBcn_ie_info +); + +HALMAC_RET_STATUS +halmac_convert_to_sdio_bus_offset_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + INOUT u32 *halmac_offset +); + +HALMAC_RET_STATUS +halmac_update_sdio_free_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_update_oqt_free_space_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_EFUSE_CMD_CONSTRUCT_STATE +halmac_query_efuse_curr_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_transition_efuse_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_EFUSE_CMD_CONSTRUCT_STATE dest_state +); + +HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE +halmac_query_cfg_para_curr_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_transition_cfg_para_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE dest_state +); + +HALMAC_SCAN_CMD_CONSTRUCT_STATE +halmac_query_scan_curr_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_transition_scan_state_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_SCAN_CMD_CONSTRUCT_STATE dest_state +); + +HALMAC_RET_STATUS +halmac_query_cfg_para_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_query_dump_physical_efuse_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_query_dump_logical_efuse_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_query_channel_switch_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_query_update_packet_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_query_iqk_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_query_power_tracking_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_query_psd_status_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + OUT HALMAC_CMD_PROCESS_STATUS *pProcess_status, + INOUT u8 *data, + INOUT u32 *size +); + +HALMAC_RET_STATUS +halmac_verify_io_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_verify_send_rsvd_page_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +VOID +halmac_power_save_cb_88xx( + IN VOID *CbData +); + +HALMAC_RET_STATUS +halmac_buffer_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 offset, + IN u32 size, + IN HAL_FIFO_SEL halmac_fifo_sel, + OUT u8 *pFifo_map +); + +VOID +halmac_restore_mac_register_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_RESTORE_INFO pRestore_info, + IN u32 restore_num +); + +VOID +halmac_api_record_id_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_API_ID api_id +); + +HALMAC_RET_STATUS +halmac_set_usb_mode_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_USB_MODE usb_mode +); + +VOID +halmac_enable_bb_rf_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 enable +); + +VOID +halmac_config_sdio_tx_page_threshold_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_TX_PAGE_THRESHOLD_INFO pThreshold_info +); + +HALMAC_RET_STATUS +halmac_rqpn_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_RQPN pPwr_seq_cfg +); + +HALMAC_RET_STATUS +halmac_check_oqt_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u32 tx_agg_num, + IN u8 *pHalmac_buf +); + +HALMAC_RET_STATUS +halmac_pg_num_parser_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN HALMAC_TRX_MODE halmac_trx_mode, + IN PHALMAC_PG_NUM pPg_num_table +); + +HALMAC_RET_STATUS +halmac_parse_intf_phy_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_INTF_PHY_PARA pIntf_phy_para, + IN HALMAC_INTF_PHY_PLATFORM platform, + IN HAL_INTF_PHY intf_phy +); + +HALMAC_RET_STATUS +halmac_dbi_write32_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr, + IN u32 data +); + +u32 +halmac_dbi_read32_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr +); + +HALMAC_RET_STATUS +halmac_dbi_write8_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr, + IN u8 data +); + +u8 +halmac_dbi_read8_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u16 addr +); + +u16 +halmac_mdio_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u8 speed + +); + +HALMAC_RET_STATUS +halmac_mdio_write_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u16 data, + IN u8 speed +); + +VOID +halmac_config_ampdu_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN PHALMAC_AMPDU_CONFIG pAmpdu_config +); + +HALMAC_RET_STATUS +halmac_usbphy_write_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u16 data, + IN u8 speed +); + +u16 +halmac_usbphy_read_88xx( + IN PHALMAC_ADAPTER pHalmac_adapter, + IN u8 addr, + IN u8 speed +); +#endif /* _HALMAC_FUNC_88XX_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_api.c b/drivers/staging/rtl8821ce/hal/halmac/halmac_api.c new file mode 100644 index 000000000000..1fefc22e6598 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_api.c @@ -0,0 +1,359 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "halmac_2_platform.h" +#include "halmac_type.h" +#if HALMAC_PLATFORM_WINDOWS == 1 +#include "halmac_88xx/halmac_api_win8821c.h" +#include "halmac_88xx/halmac_win8821c_cfg.h" + +#else +#include "halmac_88xx/halmac_api_88xx.h" +#include "halmac_88xx/halmac_88xx_cfg.h" +#endif + +#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" + +HALMAC_RET_STATUS +halmac_check_platform_api( + IN VOID *pDriver_adapter, + IN HALMAC_INTERFACE halmac_interface, + IN PHALMAC_PLATFORM_API pHalmac_platform_api +); + +HALMAC_RET_STATUS +halmac_get_chip_info( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN HALMAC_INTERFACE halmac_interface, + IN PHALMAC_ADAPTER pHalmac_adapter +); + +/** + * halmac_init_adapter() - init halmac_adapter + * @pDriver_adapter : the adapter of caller + * @pHalmac_platform_api : the platform APIs which is used in halmac APIs + * @halmac_interface : bus interface + * @ppHalmac_adapter : the adapter of halmac + * @ppHalmac_api : the function pointer of APIs, caller shall call APIs by function pointer + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_init_adapter( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN HALMAC_INTERFACE halmac_interface, + OUT PHALMAC_ADAPTER *ppHalmac_adapter, + OUT PHALMAC_API *ppHalmac_api +) +{ + PHALMAC_ADAPTER pHalmac_adapter = (PHALMAC_ADAPTER)NULL; + HALMAC_RET_STATUS status = HALMAC_RET_SUCCESS; + u8 *pBuf = NULL; + +#if HALMAC_PLATFORM_WINDOWS == 1 + u8 chip_id = 0; +#endif + union { + u32 i; + u8 x[4]; + } ENDIAN_CHECK = { 0x01000000 }; + + status = halmac_check_platform_api(pDriver_adapter, halmac_interface, pHalmac_platform_api); + if (HALMAC_RET_SUCCESS != status) + return status; + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, HALMAC_SVN_VER "\n"); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MAJOR_VER = %x\n", HALMAC_MAJOR_VER); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PROTOTYPE_VER = %x\n", HALMAC_PROTOTYPE_VER); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_MINOR_VER = %x\n", HALMAC_MINOR_VER); + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ALWAYS, "HALMAC_PATCH_VER = %x\n", HALMAC_PATCH_VER); + + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx ==========>\n"); + + /* Check endian setting - Little endian : 1, Big endian : 0*/ + if (HALMAC_SYSTEM_ENDIAN == ENDIAN_CHECK.x[0]) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Endian setting Err!!\n"); + return HALMAC_RET_ENDIAN_ERR; + } + + pBuf = (u8 *)pHalmac_platform_api->RTL_MALLOC(pDriver_adapter, sizeof(HALMAC_ADAPTER)); + + if (pBuf == NULL) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "Malloc HAL Adapter Err!!\n"); + return HALMAC_RET_MALLOC_FAIL; + } + pHalmac_platform_api->RTL_MEMSET(pDriver_adapter, pBuf, 0x00, sizeof(HALMAC_ADAPTER)); + pHalmac_adapter = (PHALMAC_ADAPTER)pBuf; + + /* return halmac adapter address to caller */ + *ppHalmac_adapter = pHalmac_adapter; + + /* Record caller info */ + pHalmac_adapter->pHalmac_platform_api = pHalmac_platform_api; + pHalmac_adapter->pDriver_adapter = pDriver_adapter; + halmac_interface = (HALMAC_INTERFACE_AXI == halmac_interface) ? HALMAC_INTERFACE_PCIE : halmac_interface; + pHalmac_adapter->halmac_interface = halmac_interface; + + PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_INIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + + /*Get Chip*/ + if (HALMAC_RET_SUCCESS != halmac_get_chip_info(pDriver_adapter, pHalmac_platform_api, halmac_interface, pHalmac_adapter)) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "HALMAC_RET_CHIP_NOT_SUPPORT\n"); + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + + /* Assign function pointer to halmac API */ +#if HALMAC_PLATFORM_WINDOWS == 0 + halmac_init_adapter_para_88xx(pHalmac_adapter); + status = halmac_mount_api_88xx(pHalmac_adapter); +#else + + if (HALMAC_CHIP_ID_8821C == pHalmac_adapter->chip_id) { + halmac_init_adapter_para_win8821c(pHalmac_adapter); + status = halmac_mount_api_win8821c(pHalmac_adapter); + } + +#endif + + /* Return halmac API function pointer */ + *ppHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_init_adapter_88xx <==========\n"); + + return status; +} + +/** + * halmac_deinit_adapter() - deinit halmac adapter + * @pHalmac_adapter : the adapter of halmac + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_deinit_adapter( + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + VOID *pDriver_adapter = NULL; + + if (HALMAC_RET_SUCCESS != halmac_adapter_validate(pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + pDriver_adapter = pHalmac_adapter->pDriver_adapter; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]halmac_deinit_adapter_88xx ==========>\n"); + + PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->EfuseMutex)); + PLATFORM_MUTEX_DEINIT(pDriver_adapter, &(pHalmac_adapter->h2c_seq_mutex)); + + if (NULL != pHalmac_adapter->pHalEfuse_map) { + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalEfuse_map, pHalmac_adapter->hw_config_info.efuse_size); + pHalmac_adapter->pHalEfuse_map = (u8 *)NULL; + } + + if (NULL != pHalmac_adapter->halmac_state.psd_set.pData) { + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->halmac_state.psd_set.pData, pHalmac_adapter->halmac_state.psd_set.data_size); + pHalmac_adapter->halmac_state.psd_set.pData = (u8 *)NULL; + } + + if (NULL != pHalmac_adapter->pHalmac_api) { + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter->pHalmac_api, sizeof(HALMAC_API)); + pHalmac_adapter->pHalmac_api = NULL; + } + + pHalmac_adapter->pHalAdapter_backup = NULL; + PLATFORM_RTL_FREE(pDriver_adapter, pHalmac_adapter, sizeof(HALMAC_ADAPTER)); + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_check_platform_api( + IN VOID *pDriver_adapter, + IN HALMAC_INTERFACE halmac_interface, + IN PHALMAC_PLATFORM_API pHalmac_platform_api +) +{ + VOID *pAdapter_Local = NULL; + + pAdapter_Local = pDriver_adapter; + + if (NULL == pHalmac_platform_api) + return HALMAC_RET_PLATFORM_API_NULL; + + if (NULL == pHalmac_platform_api->MSG_PRINT) + return HALMAC_RET_PLATFORM_API_NULL; + + if (HALMAC_INTERFACE_SDIO == halmac_interface) { + if (NULL == pHalmac_platform_api->SDIO_CMD52_READ) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_READ)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_8) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_8)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_16) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_16)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_32) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_32)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD53_READ_N) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_READ_N)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD52_WRITE) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD52_WRITE)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_8) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_8)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_16) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_16)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->SDIO_CMD53_WRITE_32) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->SDIO_CMD53_WRITE_32)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + } + + if ((HALMAC_INTERFACE_USB == halmac_interface) || (HALMAC_INTERFACE_PCIE == halmac_interface)) { + if (NULL == pHalmac_platform_api->REG_READ_8) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_8)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->REG_READ_16) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_16)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->REG_READ_32) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_READ_32)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->REG_WRITE_8) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_8)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->REG_WRITE_16) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_16)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->REG_WRITE_32) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->REG_WRITE_32)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + } + + if (NULL == pHalmac_platform_api->RTL_FREE) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_FREE)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + + if (NULL == pHalmac_platform_api->RTL_MALLOC) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MALLOC)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->RTL_MEMCPY) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMCPY)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->RTL_MEMSET) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_MEMSET)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->RTL_DELAY_US) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->RTL_DELAY_US)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + + if (NULL == pHalmac_platform_api->MUTEX_INIT) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_INIT)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->MUTEX_DEINIT) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_DEINIT)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->MUTEX_LOCK) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_LOCK)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->MUTEX_UNLOCK) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->MUTEX_UNLOCK)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + if (NULL == pHalmac_platform_api->EVENT_INDICATION) { + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_ERR, "(NULL==pHalmac_platform_api->EVENT_INDICATION)\n"); + return HALMAC_RET_PLATFORM_API_NULL; + } + + pHalmac_platform_api->MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "halmac_check_platform_api ==========>\n"); + + return HALMAC_RET_SUCCESS; +} + +/** + * halmac_get_version() - get HALMAC version + * @version : return version of major, prototype and minor information + * Author : KaiYuan Chang / Ivan Lin + * Return : HALMAC_RET_STATUS + * More details of status code can be found in prototype document + */ +HALMAC_RET_STATUS +halmac_get_version( + OUT HALMAC_VER *version +) +{ + version->major_ver = (u8)HALMAC_MAJOR_VER; + version->prototype_ver = (u8)HALMAC_PROTOTYPE_VER; + version->minor_ver = (u8)HALMAC_MINOR_VER; + + return HALMAC_RET_SUCCESS; +} + +HALMAC_RET_STATUS +halmac_get_chip_info( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN HALMAC_INTERFACE halmac_interface, + IN PHALMAC_ADAPTER pHalmac_adapter +) +{ + PHALMAC_API pHalmac_api = (PHALMAC_API)NULL; + u8 chip_id, chip_version; + u32 polling_count; + + pHalmac_api = (PHALMAC_API)pHalmac_adapter->pHalmac_api; + + /* Get Chip_id and Chip_version */ + chip_id = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG2); + chip_version = pHalmac_platform_api->REG_READ_8(pDriver_adapter, REG_SYS_CFG1 + 1) >> 4; + + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip id : 0x%X\n", chip_id); + PLATFORM_MSG_PRINT(pDriver_adapter, HALMAC_MSG_INIT, HALMAC_DBG_TRACE, "[TRACE]Chip version : 0x%X\n", chip_version); + + pHalmac_adapter->chip_version = (HALMAC_CHIP_VER)chip_version; + + if (HALMAC_CHIP_ID_HW_DEF_8822B == chip_id) + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8822B; + else if (HALMAC_CHIP_ID_HW_DEF_8821C == chip_id) + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8821C; + else if (HALMAC_CHIP_ID_HW_DEF_8814B == chip_id) + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8814B; + else if (HALMAC_CHIP_ID_HW_DEF_8197F == chip_id) + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_8197F; + else { + pHalmac_adapter->chip_id = HALMAC_CHIP_ID_UNDEFINE; + return HALMAC_RET_CHIP_NOT_SUPPORT; + } + + return HALMAC_RET_SUCCESS; +} diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_api.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_api.h new file mode 100644 index 000000000000..3f7a10dba071 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_api.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_API_H_ +#define _HALMAC_API_H_ + +#define HALMAC_SVN_VER "13348M" + +#define HALMAC_MAJOR_VER 0x0001 /* major version, ver_1 for async_api */ +#define HALMAC_PROTOTYPE_VER 0x0003 /* For halmac_api num change or prototype change, increment prototype version */ +#define HALMAC_MINOR_VER 0x0006 /* else increment minor version */ +#define HALMAC_PATCH_VER 0x0002 /* patch version */ + +#include "halmac_2_platform.h" +#include "halmac_type.h" + +#include "halmac_pcie_reg.h" + +#include "halmac_bit2.h" +#include "halmac_reg2.h" + +#if (HALMAC_PLATFORM_WINDOWS || HALMAC_PLATFORM_LINUX) +#include "halmac_tx_desc_nic.h" +#include "halmac_rx_desc_nic.h" +#include "halmac_tx_bd_nic.h" +#include "halmac_rx_bd_nic.h" +#include "halmac_fw_offload_c2h_nic.h" +#include "halmac_fw_offload_h2c_nic.h" +#include "halmac_h2c_extra_info_nic.h" +#include "halmac_original_c2h_nic.h" +#include "halmac_original_h2c_nic.h" +#endif + +#if (HALMAC_PLATFORM_AP) +#include "halmac_rx_desc_ap.h" +#include "halmac_tx_desc_ap.h" +#include "halmac_rx_bd_ap.h" +#include "halmac_tx_bd_ap.h" +#include "halmac_fw_offload_c2h_ap.h" +#include "halmac_fw_offload_h2c_ap.h" +#include "halmac_h2c_extra_info_ap.h" +#include "halmac_original_c2h_ap.h" +#include "halmac_original_h2c_ap.h" +#endif + +#include "halmac_tx_desc_chip.h" +#include "halmac_rx_desc_chip.h" +#include "halmac_tx_bd_chip.h" +#include "halmac_rx_bd_chip.h" +#if HALMAC_PLATFORM_WINDOWS == 1 + +#include "halmac_88xx/halmac_win8821c_cfg.h" + +#else +#include "halmac_88xx/halmac_88xx_cfg.h" +#endif + +#include "halmac_88xx/halmac_8821c/halmac_8821c_cfg.h" +#include "halmac_reg_8821c.h" +#include "halmac_bit_8821c.h" + +HALMAC_RET_STATUS +halmac_init_adapter( + IN VOID *pDriver_adapter, + IN PHALMAC_PLATFORM_API pHalmac_platform_api, + IN HALMAC_INTERFACE halmac_interface, + OUT PHALMAC_ADAPTER *ppHalmac_adapter, + OUT PHALMAC_API *ppHalmac_api +); + +HALMAC_RET_STATUS +halmac_deinit_adapter( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_halt_api( + IN PHALMAC_ADAPTER pHalmac_adapter +); + +HALMAC_RET_STATUS +halmac_get_version( + OUT HALMAC_VER *version +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_bit2.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_bit2.h new file mode 100644 index 000000000000..411f8d128bad --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_bit2.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __RTL_WLAN_BITDEF_H__ +#define __RTL_WLAN_BITDEF_H__ + +#define CPU_OPT_WIDTH 0x1F + +#define BIT_APFM_OFFMAC BIT(9) + +#define BIT_SHIFT_MID_FREEPG_V1 16 +#define BIT_MASK_MID_FREEPG_V1 0xfff +#define BIT_GET_MID_FREEPG_V1(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) + +#define BIT_SHIFT_HIQ_FREEPG_V1 0 +#define BIT_MASK_HIQ_FREEPG_V1 0xfff +#define BIT_GET_HIQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) + +#define BIT_SHIFT_MAC_CLK_SEL 20 + +#define BIT_SHIFT_PUB_FREEPG_V1 16 +#define BIT_MASK_PUB_FREEPG_V1 0xfff +#define BIT_GET_PUB_FREEPG_V1(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) + +#define BIT_SHIFT_LOW_FREEPG_V1 0 +#define BIT_MASK_LOW_FREEPG_V1 0xfff +#define BIT_GET_LOW_FREEPG_V1(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) + +#define BIT_SHIFT_EXQ_FREEPG_V1 0 +#define BIT_MASK_EXQ_FREEPG_V1 0xfff +#define BIT_GET_EXQ_FREEPG_V1(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) + +#define BIT_EF_FLAG BIT(31) +#define BIT_SHIFT_EF_ADDR 8 +#define BIT_MASK_EF_ADDR 0x3ff +#define BIT_MASK_EF_DATA 0xff + +#define BIT_FSPI_EN BIT(19) + +#define BIT_LTE_MUX_CTRL_PATH BIT(26) + +#define BIT_BOOT_FSPI_EN BIT(20) + +#define BIT_FW_DW_RDY BIT(14) + +#define BIT_DMEM_CHKSUM_OK BIT(6) +#define BIT_DMEM_DW_OK BIT(5) +#define BIT_IMEM_CHKSUM_OK BIT(4) +#define BIT_IMEM_DW_OK BIT(3) + +#define BIT_TXBCN0ERR_MSK BIT(26) +#define BIT_TXBCN0OK_MSK BIT(25) + +#define BIT_BCNDMAINT0_MSK BIT(20) +#define BIT_BCNDERR0_MSK BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK BIT(15) + +#define BIT_C2HCMD_MSK BIT(10) +#define BIT_HIGHDOK_MSK BIT(7) +#define BIT_MGTDOK_MSK BIT(6) +#define BIT_BKDOK_MSK BIT(5) +#define BIT_BEDOK_MSK BIT(4) +#define BIT_VIDOK_MSK BIT(3) +#define BIT_VODOK_MSK BIT(2) +#define BIT_RDU_MSK BIT(1) +#define BIT_RXOK_MSK BIT(0) + +#define BIT_RDU BIT(1) +#define BIT_RXOK BIT(0) + +#define BIT_RXERR_MSK BIT(10) +#define BIT_FOVW_MSK BIT(8) + +#define BIT_RXERR_INT BIT(10) +#define BIT_TXFOVW BIT(9) +#define BIT_FOVW BIT(8) + +#define BIT_USB3_USB2_TRANSITION BIT(20) +#define BIT_SHIFT_USB23_SW_MODE_V1 18 +#define BIT_MASK_USB23_SW_MODE_V1 0x3 +#define BIT_USB23_SW_MODE_V1(x) (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) +#define BIT_GET_USB23_SW_MODE_V1(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) + +#define BIT_NO_PDN_CHIPOFF_V1 BIT(17) + +#define BIT_RSM_EN_V1 BIT(16) + +#define BIT_MAC_SEC_EN BIT(9) +#define BIT_MACRXEN BIT(7) +#define BIT_MACTXEN BIT(6) +#define BIT_SCHEDULE_EN BIT(5) +#define BIT_PROTOCOL_EN BIT(4) +#define BIT_RXDMA_EN BIT(3) +#define BIT_TXDMA_EN BIT(2) +#define BIT_HCI_RXDMA_EN BIT(1) +#define BIT_HCI_TXDMA_EN BIT(0) + +#define BIT_SHIFT_TXDMA_HIQ_MAP 14 +#define BIT_MASK_TXDMA_HIQ_MAP 0x3 +#define BIT_TXDMA_HIQ_MAP(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) + +#define BIT_SHIFT_TXDMA_MGQ_MAP 12 +#define BIT_MASK_TXDMA_MGQ_MAP 0x3 +#define BIT_TXDMA_MGQ_MAP(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) + +#define BIT_SHIFT_TXDMA_BKQ_MAP 10 +#define BIT_MASK_TXDMA_BKQ_MAP 0x3 +#define BIT_TXDMA_BKQ_MAP(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) + +#define BIT_SHIFT_TXDMA_BEQ_MAP 8 +#define BIT_MASK_TXDMA_BEQ_MAP 0x3 +#define BIT_TXDMA_BEQ_MAP(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) + +#define BIT_SHIFT_TXDMA_VIQ_MAP 6 +#define BIT_MASK_TXDMA_VIQ_MAP 0x3 +#define BIT_TXDMA_VIQ_MAP(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) + +#define BIT_SHIFT_TXDMA_VOQ_MAP 4 +#define BIT_MASK_TXDMA_VOQ_MAP 0x3 +#define BIT_TXDMA_VOQ_MAP(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) + +#define BIT_MASK_BCN_HEAD_1_V1 0xfff + +#define BIT_SHIFT_BLK_DESC_NUM 4 +#define BIT_MASK_BLK_DESC_NUM 0xf + +#define BIT_AUTO_INIT_LLT_V1 BIT(0) + +#define BIT_MASK_H2C_READ_ADDR 0x3ffff + +#define BIT_MASK_H2C_WR_ADDR 0x3ffff + +#define BIT_MASK_BCNQ_PGBNDY_V1 0xfff + +#define BIT_R_ENABLE_NDPA BIT(31) +#define BIT_USE_NDPA_PARAMETER BIT(30) +#define BIT_R_EN_NDPA_INT BIT(28) + +#define BIT_MASK_R_TXBF1_AID 0x1ff + +#define BIT_DIS_NDP_BFEN BIT(15) + +#define BIT_R_TXBF0_80M BIT(11) +#define BIT_R_TXBF0_40M BIT(10) +#define BIT_R_TXBF0_20M BIT(9) + +#define BIT_MASK_R_TXBF0_AID 0x1ff + +#define BIT_SHIFT_RRSC_BITMAP 0 +#define BIT_MASK_RRSC_BITMAP 0xfffff +#define BIT_RRSC_BITMAP(x) (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) + +#define BIT_EN_EOF_V1 BIT(2) + +#define BIT_SHIFT_TXSC_40M 4 +#define BIT_MASK_TXSC_40M 0xf +#define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) + +#define BIT_SHIFT_TXSC_20M 0 +#define BIT_MASK_TXSC_20M 0xf +#define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) + +#define BIT_SHIFT_SIFS_OFDM_TRX 24 + +#define BIT_SHIFT_SIFS_CCK_TRX 16 + +#define BIT_SHIFT_SIFS_OFDM_CTX 8 + +#define BIT_BEQ_RD_INIT_EN BIT(6) +#define BIT_VIQ_RD_INIT_EN BIT(5) +#define BIT_VOQ_RD_INIT_EN BIT(4) + +#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 + +#define BIT_DIS_TSF_UDT BIT(4) +#define BIT_EN_BCN_FUNCTION BIT(3) + +#define BIT_TSFTR_CLI3_RST BIT(4) +#define BIT_TSFTR_CLI2_RST BIT(3) +#define BIT_TSFTR_CLI1_RST BIT(2) +#define BIT_TSFTR_CLI0_RST BIT(1) +#define BIT_TSFTR_RST BIT(0) + +#define BIT_SYNC_CLI BIT(1) + +#define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) +#define BIT_CFEND_FORMAT BIT(9) + +#define BIT_APP_FCS BIT(31) +#define BIT_APP_MIC BIT(30) +#define BIT_APP_ICV BIT(29) +#define BIT_APP_PHYSTS BIT(28) + +#define BIT_VHT_DACK BIT(26) + +#define BIT_HTC_LOC_CTRL BIT(14) + +#define BIT_CBSSID_BCN BIT(7) +#define BIT_CBSSID_DATA BIT(6) +#define BIT_AB BIT(3) +#define BIT_APM BIT(1) + +#define BIT_SHIFT_WMAC_CSI_RATE 24 +#define BIT_MASK_WMAC_CSI_RATE 0x3f +#define BIT_WMAC_CSI_RATE(x) (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) + +#define BIT_CSI_FORCE_RATE_EN BIT(15) +#define BIT_SHIFT_CSI_RSC 13 +#define BIT_MASK_CSI_RSC 0x3 +#define BIT_CSI_RSC(x) (((x) & BIT_MASK_CSI_RSC) << BIT_SHIFT_CSI_RSC) + +#define BIT_WL_PLATFORM_RST BIT(16) + +#define BIT_SETH2CDOK_MASK BIT(16) + +#define BIT_DDMACH0_OWN BIT(31) +#define BIT_DDMACH0_CHKSUM_EN BIT(29) +#define BIT_DDMACH0_CHKSUM_STS BIT(27) +#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT BIT(24) +#define BIT_MASK_DDMACH0_DLEN 0x3ffff + +#define BIT_MDIO_RFLAG_V1 BIT(6) +#define BIT_MDIO_WFLAG_V1 BIT(5) + +#define BIT_MASK_R_MU_TABLE_VALID 0x3f + +#endif/* __RTL_WLAN_BITDEF_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_bit_8821c.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_bit_8821c.h new file mode 100644 index 000000000000..5a7d1f9e2dd2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_bit_8821c.h @@ -0,0 +1,9782 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_HALMAC_BIT_8821C_H +#define __INC_HALMAC_BIT_8821C_H + +#define CPU_OPT_WIDTH 0x1F + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_SYS_ISO_CTRL_8821C */ +#define BIT_PWC_EV12V_8821C BIT(15) +#define BIT_PWC_EV25V_8821C BIT(14) +#define BIT_PA33V_EN_8821C BIT(13) +#define BIT_PA12V_EN_8821C BIT(12) +#define BIT_UA33V_EN_8821C BIT(11) +#define BIT_UA12V_EN_8821C BIT(10) +#define BIT_ISO_RFDIO_8821C BIT(9) +#define BIT_ISO_EB2CORE_8821C BIT(8) +#define BIT_ISO_DIOE_8821C BIT(7) +#define BIT_ISO_WLPON2PP_8821C BIT(6) +#define BIT_ISO_IP2MAC_WA2PP_8821C BIT(5) +#define BIT_ISO_PD2CORE_8821C BIT(4) +#define BIT_ISO_PA2PCIE_8821C BIT(3) +#define BIT_ISO_UD2CORE_8821C BIT(2) +#define BIT_ISO_UA2USB_8821C BIT(1) +#define BIT_ISO_WD2PP_8821C BIT(0) + +/* 2 REG_SYS_FUNC_EN_8821C */ +#define BIT_FEN_MREGEN_8821C BIT(15) +#define BIT_FEN_HWPDN_8821C BIT(14) +#define BIT_EN_25_1_8821C BIT(13) +#define BIT_FEN_ELDR_8821C BIT(12) +#define BIT_FEN_DCORE_8821C BIT(11) +#define BIT_FEN_CPUEN_8821C BIT(10) +#define BIT_FEN_DIOE_8821C BIT(9) +#define BIT_FEN_PCIED_8821C BIT(8) +#define BIT_FEN_PPLL_8821C BIT(7) +#define BIT_FEN_PCIEA_8821C BIT(6) +#define BIT_FEN_DIO_PCIE_8821C BIT(5) +#define BIT_FEN_USBD_8821C BIT(4) +#define BIT_FEN_UPLL_8821C BIT(3) +#define BIT_FEN_USBA_8821C BIT(2) +#define BIT_FEN_BB_GLB_RSTN_8821C BIT(1) +#define BIT_FEN_BBRSTB_8821C BIT(0) + +/* 2 REG_SYS_PW_CTRL_8821C */ +#define BIT_SOP_EABM_8821C BIT(31) +#define BIT_SOP_ACKF_8821C BIT(30) +#define BIT_SOP_ERCK_8821C BIT(29) +#define BIT_SOP_ESWR_8821C BIT(28) +#define BIT_SOP_PWMM_8821C BIT(27) +#define BIT_SOP_EECK_8821C BIT(26) +#define BIT_SOP_EXTL_8821C BIT(24) +#define BIT_SYM_OP_RING_12M_8821C BIT(22) +#define BIT_ROP_SWPR_8821C BIT(21) +#define BIT_DIS_HW_LPLDM_8821C BIT(20) +#define BIT_OPT_SWRST_WLMCU_8821C BIT(19) +#define BIT_RDY_SYSPWR_8821C BIT(17) +#define BIT_EN_WLON_8821C BIT(16) +#define BIT_APDM_HPDN_8821C BIT(15) +#define BIT_AFSM_PCIE_SUS_EN_8821C BIT(12) +#define BIT_AFSM_WLSUS_EN_8821C BIT(11) +#define BIT_APFM_SWLPS_8821C BIT(10) +#define BIT_APFM_OFFMAC_8821C BIT(9) +#define BIT_APFN_ONMAC_8821C BIT(8) +#define BIT_CHIP_PDN_EN_8821C BIT(7) +#define BIT_RDY_MACDIS_8821C BIT(6) +#define BIT_RING_CLK_12M_EN_8821C BIT(4) +#define BIT_PFM_WOWL_8821C BIT(3) +#define BIT_PFM_LDKP_8821C BIT(2) +#define BIT_WL_HCI_ALD_8821C BIT(1) +#define BIT_PFM_LDALL_8821C BIT(0) + +/* 2 REG_SYS_CLK_CTRL_8821C */ +#define BIT_LDO_DUMMY_8821C BIT(15) +#define BIT_CPU_CLK_EN_8821C BIT(14) +#define BIT_SYMREG_CLK_EN_8821C BIT(13) +#define BIT_HCI_CLK_EN_8821C BIT(12) +#define BIT_MAC_CLK_EN_8821C BIT(11) +#define BIT_SEC_CLK_EN_8821C BIT(10) +#define BIT_PHY_SSC_RSTB_8821C BIT(9) +#define BIT_EXT_32K_EN_8821C BIT(8) +#define BIT_WL_CLK_TEST_8821C BIT(7) +#define BIT_OP_SPS_PWM_EN_8821C BIT(6) +#define BIT_LOADER_CLK_EN_8821C BIT(5) +#define BIT_MACSLP_8821C BIT(4) +#define BIT_WAKEPAD_EN_8821C BIT(3) +#define BIT_ROMD16V_EN_8821C BIT(2) +#define BIT_CKANA12M_EN_8821C BIT(1) +#define BIT_CNTD16V_EN_8821C BIT(0) + +/* 2 REG_SYS_EEPROM_CTRL_8821C */ + +#define BIT_SHIFT_VPDIDX_8821C 8 +#define BIT_MASK_VPDIDX_8821C 0xff +#define BIT_VPDIDX_8821C(x) (((x) & BIT_MASK_VPDIDX_8821C) << BIT_SHIFT_VPDIDX_8821C) +#define BIT_GET_VPDIDX_8821C(x) (((x) >> BIT_SHIFT_VPDIDX_8821C) & BIT_MASK_VPDIDX_8821C) + +#define BIT_SHIFT_EEM1_0_8821C 6 +#define BIT_MASK_EEM1_0_8821C 0x3 +#define BIT_EEM1_0_8821C(x) (((x) & BIT_MASK_EEM1_0_8821C) << BIT_SHIFT_EEM1_0_8821C) +#define BIT_GET_EEM1_0_8821C(x) (((x) >> BIT_SHIFT_EEM1_0_8821C) & BIT_MASK_EEM1_0_8821C) + +#define BIT_AUTOLOAD_SUS_8821C BIT(5) +#define BIT_EERPOMSEL_8821C BIT(4) +#define BIT_EECS_V1_8821C BIT(3) +#define BIT_EESK_V1_8821C BIT(2) +#define BIT_EEDI_V1_8821C BIT(1) +#define BIT_EEDO_V1_8821C BIT(0) + +/* 2 REG_EE_VPD_8821C */ + +#define BIT_SHIFT_VPD_DATA_8821C 0 +#define BIT_MASK_VPD_DATA_8821C 0xffffffffL +#define BIT_VPD_DATA_8821C(x) (((x) & BIT_MASK_VPD_DATA_8821C) << BIT_SHIFT_VPD_DATA_8821C) +#define BIT_GET_VPD_DATA_8821C(x) (((x) >> BIT_SHIFT_VPD_DATA_8821C) & BIT_MASK_VPD_DATA_8821C) + +/* 2 REG_SYS_SWR_CTRL1_8821C */ +#define BIT_C2_L_BIT0_8821C BIT(31) + +#define BIT_SHIFT_C1_L_8821C 29 +#define BIT_MASK_C1_L_8821C 0x3 +#define BIT_C1_L_8821C(x) (((x) & BIT_MASK_C1_L_8821C) << BIT_SHIFT_C1_L_8821C) +#define BIT_GET_C1_L_8821C(x) (((x) >> BIT_SHIFT_C1_L_8821C) & BIT_MASK_C1_L_8821C) + +#define BIT_SHIFT_REG_FREQ_L_8821C 25 +#define BIT_MASK_REG_FREQ_L_8821C 0x7 +#define BIT_REG_FREQ_L_8821C(x) (((x) & BIT_MASK_REG_FREQ_L_8821C) << BIT_SHIFT_REG_FREQ_L_8821C) +#define BIT_GET_REG_FREQ_L_8821C(x) (((x) >> BIT_SHIFT_REG_FREQ_L_8821C) & BIT_MASK_REG_FREQ_L_8821C) + +#define BIT_REG_EN_DUTY_8821C BIT(24) + +#define BIT_SHIFT_REG_MODE_8821C 22 +#define BIT_MASK_REG_MODE_8821C 0x3 +#define BIT_REG_MODE_8821C(x) (((x) & BIT_MASK_REG_MODE_8821C) << BIT_SHIFT_REG_MODE_8821C) +#define BIT_GET_REG_MODE_8821C(x) (((x) >> BIT_SHIFT_REG_MODE_8821C) & BIT_MASK_REG_MODE_8821C) + +#define BIT_REG_EN_SP_8821C BIT(21) +#define BIT_REG_AUTO_L_8821C BIT(20) +#define BIT_SW18_SELD_BIT0_8821C BIT(19) +#define BIT_SW18_POWOCP_8821C BIT(18) + +#define BIT_SHIFT_OCP_L1_8821C 15 +#define BIT_MASK_OCP_L1_8821C 0x7 +#define BIT_OCP_L1_8821C(x) (((x) & BIT_MASK_OCP_L1_8821C) << BIT_SHIFT_OCP_L1_8821C) +#define BIT_GET_OCP_L1_8821C(x) (((x) >> BIT_SHIFT_OCP_L1_8821C) & BIT_MASK_OCP_L1_8821C) + +#define BIT_SHIFT_CF_L_8821C 13 +#define BIT_MASK_CF_L_8821C 0x3 +#define BIT_CF_L_8821C(x) (((x) & BIT_MASK_CF_L_8821C) << BIT_SHIFT_CF_L_8821C) +#define BIT_GET_CF_L_8821C(x) (((x) >> BIT_SHIFT_CF_L_8821C) & BIT_MASK_CF_L_8821C) + +#define BIT_SW18_FPWM_8821C BIT(11) +#define BIT_SW18_SWEN_8821C BIT(9) +#define BIT_SW18_LDEN_8821C BIT(8) +#define BIT_MAC_ID_EN_8821C BIT(7) +#define BIT_AFE_BGEN_8821C BIT(0) + +/* 2 REG_SYS_SWR_CTRL2_8821C */ +#define BIT_POW_ZCD_L_8821C BIT(31) +#define BIT_AUTOZCD_L_8821C BIT(30) + +#define BIT_SHIFT_REG_DELAY_8821C 28 +#define BIT_MASK_REG_DELAY_8821C 0x3 +#define BIT_REG_DELAY_8821C(x) (((x) & BIT_MASK_REG_DELAY_8821C) << BIT_SHIFT_REG_DELAY_8821C) +#define BIT_GET_REG_DELAY_8821C(x) (((x) >> BIT_SHIFT_REG_DELAY_8821C) & BIT_MASK_REG_DELAY_8821C) + +#define BIT_SHIFT_V15ADJ_L1_V1_8821C 24 +#define BIT_MASK_V15ADJ_L1_V1_8821C 0x7 +#define BIT_V15ADJ_L1_V1_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_V1_8821C) << BIT_SHIFT_V15ADJ_L1_V1_8821C) +#define BIT_GET_V15ADJ_L1_V1_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_V1_8821C) & BIT_MASK_V15ADJ_L1_V1_8821C) + +#define BIT_SHIFT_VOL_L1_V1_8821C 20 +#define BIT_MASK_VOL_L1_V1_8821C 0xf +#define BIT_VOL_L1_V1_8821C(x) (((x) & BIT_MASK_VOL_L1_V1_8821C) << BIT_SHIFT_VOL_L1_V1_8821C) +#define BIT_GET_VOL_L1_V1_8821C(x) (((x) >> BIT_SHIFT_VOL_L1_V1_8821C) & BIT_MASK_VOL_L1_V1_8821C) + +#define BIT_SHIFT_IN_L1_V1_8821C 17 +#define BIT_MASK_IN_L1_V1_8821C 0x7 +#define BIT_IN_L1_V1_8821C(x) (((x) & BIT_MASK_IN_L1_V1_8821C) << BIT_SHIFT_IN_L1_V1_8821C) +#define BIT_GET_IN_L1_V1_8821C(x) (((x) >> BIT_SHIFT_IN_L1_V1_8821C) & BIT_MASK_IN_L1_V1_8821C) + +#define BIT_SHIFT_TBOX_L1_8821C 15 +#define BIT_MASK_TBOX_L1_8821C 0x3 +#define BIT_TBOX_L1_8821C(x) (((x) & BIT_MASK_TBOX_L1_8821C) << BIT_SHIFT_TBOX_L1_8821C) +#define BIT_GET_TBOX_L1_8821C(x) (((x) >> BIT_SHIFT_TBOX_L1_8821C) & BIT_MASK_TBOX_L1_8821C) + +#define BIT_SW18_SEL_8821C BIT(13) + +/* 2 REG_NOT_VALID_8821C */ +#define BIT_SW18_SD_8821C BIT(10) + +#define BIT_SHIFT_R3_L_8821C 7 +#define BIT_MASK_R3_L_8821C 0x3 +#define BIT_R3_L_8821C(x) (((x) & BIT_MASK_R3_L_8821C) << BIT_SHIFT_R3_L_8821C) +#define BIT_GET_R3_L_8821C(x) (((x) >> BIT_SHIFT_R3_L_8821C) & BIT_MASK_R3_L_8821C) + +#define BIT_SHIFT_SW18_R2_8821C 5 +#define BIT_MASK_SW18_R2_8821C 0x3 +#define BIT_SW18_R2_8821C(x) (((x) & BIT_MASK_SW18_R2_8821C) << BIT_SHIFT_SW18_R2_8821C) +#define BIT_GET_SW18_R2_8821C(x) (((x) >> BIT_SHIFT_SW18_R2_8821C) & BIT_MASK_SW18_R2_8821C) + +#define BIT_SHIFT_SW18_R1_8821C 3 +#define BIT_MASK_SW18_R1_8821C 0x3 +#define BIT_SW18_R1_8821C(x) (((x) & BIT_MASK_SW18_R1_8821C) << BIT_SHIFT_SW18_R1_8821C) +#define BIT_GET_SW18_R1_8821C(x) (((x) >> BIT_SHIFT_SW18_R1_8821C) & BIT_MASK_SW18_R1_8821C) + +#define BIT_SHIFT_C3_L_C3_8821C 1 +#define BIT_MASK_C3_L_C3_8821C 0x3 +#define BIT_C3_L_C3_8821C(x) (((x) & BIT_MASK_C3_L_C3_8821C) << BIT_SHIFT_C3_L_C3_8821C) +#define BIT_GET_C3_L_C3_8821C(x) (((x) >> BIT_SHIFT_C3_L_C3_8821C) & BIT_MASK_C3_L_C3_8821C) + +#define BIT_C2_L_BIT1_8821C BIT(0) + +/* 2 REG_SYS_SWR_CTRL3_8821C */ +#define BIT_SPS18_OCP_DIS_8821C BIT(31) + +#define BIT_SHIFT_SPS18_OCP_TH_8821C 16 +#define BIT_MASK_SPS18_OCP_TH_8821C 0x7fff +#define BIT_SPS18_OCP_TH_8821C(x) (((x) & BIT_MASK_SPS18_OCP_TH_8821C) << BIT_SHIFT_SPS18_OCP_TH_8821C) +#define BIT_GET_SPS18_OCP_TH_8821C(x) (((x) >> BIT_SHIFT_SPS18_OCP_TH_8821C) & BIT_MASK_SPS18_OCP_TH_8821C) + +#define BIT_SHIFT_OCP_WINDOW_8821C 0 +#define BIT_MASK_OCP_WINDOW_8821C 0xffff +#define BIT_OCP_WINDOW_8821C(x) (((x) & BIT_MASK_OCP_WINDOW_8821C) << BIT_SHIFT_OCP_WINDOW_8821C) +#define BIT_GET_OCP_WINDOW_8821C(x) (((x) >> BIT_SHIFT_OCP_WINDOW_8821C) & BIT_MASK_OCP_WINDOW_8821C) + +/* 2 REG_RSV_CTRL_8821C */ +#define BIT_HREG_DBG_8821C BIT(23) +#define BIT_WLMCUIOIF_8821C BIT(8) +#define BIT_LOCK_ALL_EN_8821C BIT(7) +#define BIT_R_DIS_PRST_8821C BIT(6) +#define BIT_WLOCK_1C_B6_8821C BIT(5) +#define BIT_WLOCK_40_8821C BIT(4) +#define BIT_WLOCK_08_8821C BIT(3) +#define BIT_WLOCK_04_8821C BIT(2) +#define BIT_WLOCK_00_8821C BIT(1) +#define BIT_WLOCK_ALL_8821C BIT(0) + +/* 2 REG_RF_CTRL_8821C */ +#define BIT_RF_SDMRSTB_8821C BIT(2) +#define BIT_RF_RSTB_8821C BIT(1) +#define BIT_RF_EN_8821C BIT(0) + +/* 2 REG_AFE_LDO_CTRL_8821C */ + +#define BIT_SHIFT_LPLDH12_RSV_8821C 29 +#define BIT_MASK_LPLDH12_RSV_8821C 0x7 +#define BIT_LPLDH12_RSV_8821C(x) (((x) & BIT_MASK_LPLDH12_RSV_8821C) << BIT_SHIFT_LPLDH12_RSV_8821C) +#define BIT_GET_LPLDH12_RSV_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_RSV_8821C) & BIT_MASK_LPLDH12_RSV_8821C) + +#define BIT_LPLDH12_SLP_8821C BIT(28) + +#define BIT_SHIFT_LPLDH12_VADJ_8821C 24 +#define BIT_MASK_LPLDH12_VADJ_8821C 0xf +#define BIT_LPLDH12_VADJ_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_8821C) << BIT_SHIFT_LPLDH12_VADJ_8821C) +#define BIT_GET_LPLDH12_VADJ_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_8821C) & BIT_MASK_LPLDH12_VADJ_8821C) + +#define BIT_PCIE_CALIB_EN_8821C BIT(17) +#define BIT_LDH12_EN_8821C BIT(16) +#define BIT_WLBBOFF_BIG_PWC_EN_8821C BIT(14) +#define BIT_WLBBOFF_SMALL_PWC_EN_8821C BIT(13) +#define BIT_WLMACOFF_BIG_PWC_EN_8821C BIT(12) +#define BIT_WLPON_PWC_EN_8821C BIT(11) +#define BIT_POW_REGU_P1_8821C BIT(10) +#define BIT_LDOV12W_EN_8821C BIT(8) +#define BIT_EX_XTAL_DRV_DIGI_8821C BIT(7) +#define BIT_EX_XTAL_DRV_USB_8821C BIT(6) +#define BIT_EX_XTAL_DRV_AFE_8821C BIT(5) +#define BIT_EX_XTAL_DRV_RF2_8821C BIT(4) +#define BIT_EX_XTAL_DRV_RF1_8821C BIT(3) +#define BIT_POW_REGU_P0_8821C BIT(2) + +/* 2 REG_NOT_VALID_8821C */ +#define BIT_POW_PLL_LDO_8821C BIT(0) + +/* 2 REG_AFE_CTRL1_8821C */ +#define BIT_AGPIO_GPE_8821C BIT(31) + +#define BIT_SHIFT_XTAL_CAP_XI_8821C 25 +#define BIT_MASK_XTAL_CAP_XI_8821C 0x3f +#define BIT_XTAL_CAP_XI_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XI_8821C) << BIT_SHIFT_XTAL_CAP_XI_8821C) +#define BIT_GET_XTAL_CAP_XI_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XI_8821C) & BIT_MASK_XTAL_CAP_XI_8821C) + +#define BIT_SHIFT_XTAL_DRV_DIGI_8821C 23 +#define BIT_MASK_XTAL_DRV_DIGI_8821C 0x3 +#define BIT_XTAL_DRV_DIGI_8821C(x) (((x) & BIT_MASK_XTAL_DRV_DIGI_8821C) << BIT_SHIFT_XTAL_DRV_DIGI_8821C) +#define BIT_GET_XTAL_DRV_DIGI_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_DIGI_8821C) & BIT_MASK_XTAL_DRV_DIGI_8821C) + +#define BIT_XTAL_DRV_USB_BIT1_8821C BIT(22) + +#define BIT_SHIFT_MAC_CLK_SEL_8821C 20 +#define BIT_MASK_MAC_CLK_SEL_8821C 0x3 +#define BIT_MAC_CLK_SEL_8821C(x) (((x) & BIT_MASK_MAC_CLK_SEL_8821C) << BIT_SHIFT_MAC_CLK_SEL_8821C) +#define BIT_GET_MAC_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_MAC_CLK_SEL_8821C) & BIT_MASK_MAC_CLK_SEL_8821C) + +#define BIT_XTAL_DRV_USB_BIT0_8821C BIT(19) + +#define BIT_SHIFT_XTAL_DRV_AFE_8821C 17 +#define BIT_MASK_XTAL_DRV_AFE_8821C 0x3 +#define BIT_XTAL_DRV_AFE_8821C(x) (((x) & BIT_MASK_XTAL_DRV_AFE_8821C) << BIT_SHIFT_XTAL_DRV_AFE_8821C) +#define BIT_GET_XTAL_DRV_AFE_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_AFE_8821C) & BIT_MASK_XTAL_DRV_AFE_8821C) + +#define BIT_SHIFT_XTAL_DRV_RF2_8821C 15 +#define BIT_MASK_XTAL_DRV_RF2_8821C 0x3 +#define BIT_XTAL_DRV_RF2_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF2_8821C) << BIT_SHIFT_XTAL_DRV_RF2_8821C) +#define BIT_GET_XTAL_DRV_RF2_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF2_8821C) & BIT_MASK_XTAL_DRV_RF2_8821C) + +#define BIT_SHIFT_XTAL_DRV_RF1_8821C 13 +#define BIT_MASK_XTAL_DRV_RF1_8821C 0x3 +#define BIT_XTAL_DRV_RF1_8821C(x) (((x) & BIT_MASK_XTAL_DRV_RF1_8821C) << BIT_SHIFT_XTAL_DRV_RF1_8821C) +#define BIT_GET_XTAL_DRV_RF1_8821C(x) (((x) >> BIT_SHIFT_XTAL_DRV_RF1_8821C) & BIT_MASK_XTAL_DRV_RF1_8821C) + +#define BIT_XTAL_DELAY_DIGI_8821C BIT(12) +#define BIT_XTAL_DELAY_USB_8821C BIT(11) +#define BIT_XTAL_DELAY_AFE_8821C BIT(10) + +#define BIT_SHIFT_XTAL_LDO_VREF_8821C 7 +#define BIT_MASK_XTAL_LDO_VREF_8821C 0x7 +#define BIT_XTAL_LDO_VREF_8821C(x) (((x) & BIT_MASK_XTAL_LDO_VREF_8821C) << BIT_SHIFT_XTAL_LDO_VREF_8821C) +#define BIT_GET_XTAL_LDO_VREF_8821C(x) (((x) >> BIT_SHIFT_XTAL_LDO_VREF_8821C) & BIT_MASK_XTAL_LDO_VREF_8821C) + +#define BIT_XTAL_XQSEL_RF_8821C BIT(6) +#define BIT_XTAL_XQSEL_8821C BIT(5) + +#define BIT_SHIFT_XTAL_GMN_V2_8821C 3 +#define BIT_MASK_XTAL_GMN_V2_8821C 0x3 +#define BIT_XTAL_GMN_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMN_V2_8821C) << BIT_SHIFT_XTAL_GMN_V2_8821C) +#define BIT_GET_XTAL_GMN_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMN_V2_8821C) & BIT_MASK_XTAL_GMN_V2_8821C) + +#define BIT_SHIFT_XTAL_GMP_V2_8821C 1 +#define BIT_MASK_XTAL_GMP_V2_8821C 0x3 +#define BIT_XTAL_GMP_V2_8821C(x) (((x) & BIT_MASK_XTAL_GMP_V2_8821C) << BIT_SHIFT_XTAL_GMP_V2_8821C) +#define BIT_GET_XTAL_GMP_V2_8821C(x) (((x) >> BIT_SHIFT_XTAL_GMP_V2_8821C) & BIT_MASK_XTAL_GMP_V2_8821C) + +#define BIT_XTAL_EN_8821C BIT(0) + +/* 2 REG_AFE_CTRL2_8821C */ + +#define BIT_SHIFT_REG_C3_V4_8821C 30 +#define BIT_MASK_REG_C3_V4_8821C 0x3 +#define BIT_REG_C3_V4_8821C(x) (((x) & BIT_MASK_REG_C3_V4_8821C) << BIT_SHIFT_REG_C3_V4_8821C) +#define BIT_GET_REG_C3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_C3_V4_8821C) & BIT_MASK_REG_C3_V4_8821C) + +#define BIT_REG_CP_BIT1_8821C BIT(29) + +#define BIT_SHIFT_REG_RS_V4_8821C 26 +#define BIT_MASK_REG_RS_V4_8821C 0x7 +#define BIT_REG_RS_V4_8821C(x) (((x) & BIT_MASK_REG_RS_V4_8821C) << BIT_SHIFT_REG_RS_V4_8821C) +#define BIT_GET_REG_RS_V4_8821C(x) (((x) >> BIT_SHIFT_REG_RS_V4_8821C) & BIT_MASK_REG_RS_V4_8821C) + +#define BIT_SHIFT_REG__CS_8821C 24 +#define BIT_MASK_REG__CS_8821C 0x3 +#define BIT_REG__CS_8821C(x) (((x) & BIT_MASK_REG__CS_8821C) << BIT_SHIFT_REG__CS_8821C) +#define BIT_GET_REG__CS_8821C(x) (((x) >> BIT_SHIFT_REG__CS_8821C) & BIT_MASK_REG__CS_8821C) + +#define BIT_SHIFT_REG_CP_OFFSET_8821C 21 +#define BIT_MASK_REG_CP_OFFSET_8821C 0x7 +#define BIT_REG_CP_OFFSET_8821C(x) (((x) & BIT_MASK_REG_CP_OFFSET_8821C) << BIT_SHIFT_REG_CP_OFFSET_8821C) +#define BIT_GET_REG_CP_OFFSET_8821C(x) (((x) >> BIT_SHIFT_REG_CP_OFFSET_8821C) & BIT_MASK_REG_CP_OFFSET_8821C) + +#define BIT_SHIFT_CP_BIAS_8821C 18 +#define BIT_MASK_CP_BIAS_8821C 0x7 +#define BIT_CP_BIAS_8821C(x) (((x) & BIT_MASK_CP_BIAS_8821C) << BIT_SHIFT_CP_BIAS_8821C) +#define BIT_GET_CP_BIAS_8821C(x) (((x) >> BIT_SHIFT_CP_BIAS_8821C) & BIT_MASK_CP_BIAS_8821C) + +#define BIT_REG_IDOUBLE_V2_8821C BIT(17) +#define BIT_EN_SYN_8821C BIT(16) + +#define BIT_SHIFT_MCCO_8821C 14 +#define BIT_MASK_MCCO_8821C 0x3 +#define BIT_MCCO_8821C(x) (((x) & BIT_MASK_MCCO_8821C) << BIT_SHIFT_MCCO_8821C) +#define BIT_GET_MCCO_8821C(x) (((x) >> BIT_SHIFT_MCCO_8821C) & BIT_MASK_MCCO_8821C) + +#define BIT_SHIFT_REG_LDO_SEL_8821C 12 +#define BIT_MASK_REG_LDO_SEL_8821C 0x3 +#define BIT_REG_LDO_SEL_8821C(x) (((x) & BIT_MASK_REG_LDO_SEL_8821C) << BIT_SHIFT_REG_LDO_SEL_8821C) +#define BIT_GET_REG_LDO_SEL_8821C(x) (((x) >> BIT_SHIFT_REG_LDO_SEL_8821C) & BIT_MASK_REG_LDO_SEL_8821C) + +#define BIT_REG_KVCO_V2_8821C BIT(10) +#define BIT_AGPIO_GPO_8821C BIT(9) + +#define BIT_SHIFT_AGPIO_DRV_8821C 7 +#define BIT_MASK_AGPIO_DRV_8821C 0x3 +#define BIT_AGPIO_DRV_8821C(x) (((x) & BIT_MASK_AGPIO_DRV_8821C) << BIT_SHIFT_AGPIO_DRV_8821C) +#define BIT_GET_AGPIO_DRV_8821C(x) (((x) >> BIT_SHIFT_AGPIO_DRV_8821C) & BIT_MASK_AGPIO_DRV_8821C) + +#define BIT_SHIFT_XTAL_CAP_XO_8821C 1 +#define BIT_MASK_XTAL_CAP_XO_8821C 0x3f +#define BIT_XTAL_CAP_XO_8821C(x) (((x) & BIT_MASK_XTAL_CAP_XO_8821C) << BIT_SHIFT_XTAL_CAP_XO_8821C) +#define BIT_GET_XTAL_CAP_XO_8821C(x) (((x) >> BIT_SHIFT_XTAL_CAP_XO_8821C) & BIT_MASK_XTAL_CAP_XO_8821C) + +#define BIT_POW_PLL_8821C BIT(0) + +/* 2 REG_AFE_CTRL3_8821C */ + +#define BIT_SHIFT_PS_8821C 7 +#define BIT_MASK_PS_8821C 0x7 +#define BIT_PS_8821C(x) (((x) & BIT_MASK_PS_8821C) << BIT_SHIFT_PS_8821C) +#define BIT_GET_PS_8821C(x) (((x) >> BIT_SHIFT_PS_8821C) & BIT_MASK_PS_8821C) + +#define BIT_PSEN_8821C BIT(6) +#define BIT_DOGENB_8821C BIT(5) +#define BIT_REG_MBIAS_8821C BIT(4) + +#define BIT_SHIFT_REG_R3_V4_8821C 1 +#define BIT_MASK_REG_R3_V4_8821C 0x7 +#define BIT_REG_R3_V4_8821C(x) (((x) & BIT_MASK_REG_R3_V4_8821C) << BIT_SHIFT_REG_R3_V4_8821C) +#define BIT_GET_REG_R3_V4_8821C(x) (((x) >> BIT_SHIFT_REG_R3_V4_8821C) & BIT_MASK_REG_R3_V4_8821C) + +#define BIT_REG_CP_BIT0_8821C BIT(0) + +/* 2 REG_EFUSE_CTRL_8821C */ +#define BIT_EF_FLAG_8821C BIT(31) + +#define BIT_SHIFT_EF_PGPD_8821C 28 +#define BIT_MASK_EF_PGPD_8821C 0x7 +#define BIT_EF_PGPD_8821C(x) (((x) & BIT_MASK_EF_PGPD_8821C) << BIT_SHIFT_EF_PGPD_8821C) +#define BIT_GET_EF_PGPD_8821C(x) (((x) >> BIT_SHIFT_EF_PGPD_8821C) & BIT_MASK_EF_PGPD_8821C) + +#define BIT_SHIFT_EF_RDT_8821C 24 +#define BIT_MASK_EF_RDT_8821C 0xf +#define BIT_EF_RDT_8821C(x) (((x) & BIT_MASK_EF_RDT_8821C) << BIT_SHIFT_EF_RDT_8821C) +#define BIT_GET_EF_RDT_8821C(x) (((x) >> BIT_SHIFT_EF_RDT_8821C) & BIT_MASK_EF_RDT_8821C) + +#define BIT_SHIFT_EF_PGTS_8821C 20 +#define BIT_MASK_EF_PGTS_8821C 0xf +#define BIT_EF_PGTS_8821C(x) (((x) & BIT_MASK_EF_PGTS_8821C) << BIT_SHIFT_EF_PGTS_8821C) +#define BIT_GET_EF_PGTS_8821C(x) (((x) >> BIT_SHIFT_EF_PGTS_8821C) & BIT_MASK_EF_PGTS_8821C) + +#define BIT_EF_PDWN_8821C BIT(19) +#define BIT_EF_ALDEN_8821C BIT(18) + +#define BIT_SHIFT_EF_ADDR_8821C 8 +#define BIT_MASK_EF_ADDR_8821C 0x3ff +#define BIT_EF_ADDR_8821C(x) (((x) & BIT_MASK_EF_ADDR_8821C) << BIT_SHIFT_EF_ADDR_8821C) +#define BIT_GET_EF_ADDR_8821C(x) (((x) >> BIT_SHIFT_EF_ADDR_8821C) & BIT_MASK_EF_ADDR_8821C) + +#define BIT_SHIFT_EF_DATA_8821C 0 +#define BIT_MASK_EF_DATA_8821C 0xff +#define BIT_EF_DATA_8821C(x) (((x) & BIT_MASK_EF_DATA_8821C) << BIT_SHIFT_EF_DATA_8821C) +#define BIT_GET_EF_DATA_8821C(x) (((x) >> BIT_SHIFT_EF_DATA_8821C) & BIT_MASK_EF_DATA_8821C) + +/* 2 REG_LDO_EFUSE_CTRL_8821C */ +#define BIT_LDOE25_EN_8821C BIT(31) + +#define BIT_SHIFT_LDOE25_V12ADJ_L_8821C 27 +#define BIT_MASK_LDOE25_V12ADJ_L_8821C 0xf +#define BIT_LDOE25_V12ADJ_L_8821C(x) (((x) & BIT_MASK_LDOE25_V12ADJ_L_8821C) << BIT_SHIFT_LDOE25_V12ADJ_L_8821C) +#define BIT_GET_LDOE25_V12ADJ_L_8821C(x) (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L_8821C) & BIT_MASK_LDOE25_V12ADJ_L_8821C) + +#define BIT_EF_CRES_SEL_8821C BIT(26) + +#define BIT_SHIFT_EF_SCAN_START_V1_8821C 16 +#define BIT_MASK_EF_SCAN_START_V1_8821C 0x3ff +#define BIT_EF_SCAN_START_V1_8821C(x) (((x) & BIT_MASK_EF_SCAN_START_V1_8821C) << BIT_SHIFT_EF_SCAN_START_V1_8821C) +#define BIT_GET_EF_SCAN_START_V1_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_START_V1_8821C) & BIT_MASK_EF_SCAN_START_V1_8821C) + +#define BIT_SHIFT_EF_SCAN_END_8821C 12 +#define BIT_MASK_EF_SCAN_END_8821C 0xf +#define BIT_EF_SCAN_END_8821C(x) (((x) & BIT_MASK_EF_SCAN_END_8821C) << BIT_SHIFT_EF_SCAN_END_8821C) +#define BIT_GET_EF_SCAN_END_8821C(x) (((x) >> BIT_SHIFT_EF_SCAN_END_8821C) & BIT_MASK_EF_SCAN_END_8821C) + +#define BIT_EF_PD_DIS_8821C BIT(11) + +#define BIT_SHIFT_EF_CELL_SEL_8821C 8 +#define BIT_MASK_EF_CELL_SEL_8821C 0x3 +#define BIT_EF_CELL_SEL_8821C(x) (((x) & BIT_MASK_EF_CELL_SEL_8821C) << BIT_SHIFT_EF_CELL_SEL_8821C) +#define BIT_GET_EF_CELL_SEL_8821C(x) (((x) >> BIT_SHIFT_EF_CELL_SEL_8821C) & BIT_MASK_EF_CELL_SEL_8821C) + +#define BIT_EF_TRPT_8821C BIT(7) + +#define BIT_SHIFT_EF_TTHD_8821C 0 +#define BIT_MASK_EF_TTHD_8821C 0x7f +#define BIT_EF_TTHD_8821C(x) (((x) & BIT_MASK_EF_TTHD_8821C) << BIT_SHIFT_EF_TTHD_8821C) +#define BIT_GET_EF_TTHD_8821C(x) (((x) >> BIT_SHIFT_EF_TTHD_8821C) & BIT_MASK_EF_TTHD_8821C) + +/* 2 REG_PWR_OPTION_CTRL_8821C */ + +#define BIT_SHIFT_DBG_SEL_V1_8821C 16 +#define BIT_MASK_DBG_SEL_V1_8821C 0xff +#define BIT_DBG_SEL_V1_8821C(x) (((x) & BIT_MASK_DBG_SEL_V1_8821C) << BIT_SHIFT_DBG_SEL_V1_8821C) +#define BIT_GET_DBG_SEL_V1_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_V1_8821C) & BIT_MASK_DBG_SEL_V1_8821C) + +#define BIT_SHIFT_DBG_SEL_BYTE_8821C 14 +#define BIT_MASK_DBG_SEL_BYTE_8821C 0x3 +#define BIT_DBG_SEL_BYTE_8821C(x) (((x) & BIT_MASK_DBG_SEL_BYTE_8821C) << BIT_SHIFT_DBG_SEL_BYTE_8821C) +#define BIT_GET_DBG_SEL_BYTE_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_BYTE_8821C) & BIT_MASK_DBG_SEL_BYTE_8821C) + +#define BIT_SHIFT_STD_L1_V1_8821C 12 +#define BIT_MASK_STD_L1_V1_8821C 0x3 +#define BIT_STD_L1_V1_8821C(x) (((x) & BIT_MASK_STD_L1_V1_8821C) << BIT_SHIFT_STD_L1_V1_8821C) +#define BIT_GET_STD_L1_V1_8821C(x) (((x) >> BIT_SHIFT_STD_L1_V1_8821C) & BIT_MASK_STD_L1_V1_8821C) + +#define BIT_SYSON_DBG_PAD_E2_8821C BIT(11) +#define BIT_SYSON_LED_PAD_E2_8821C BIT(10) +#define BIT_SYSON_GPEE_PAD_E2_8821C BIT(9) +#define BIT_SYSON_PCI_PAD_E2_8821C BIT(8) +#define BIT_AUTO_SW_LDO_VOL_EN_8821C BIT(7) + +#define BIT_SHIFT_SYSON_SPS0WWV_WT_8821C 4 +#define BIT_MASK_SYSON_SPS0WWV_WT_8821C 0x3 +#define BIT_SYSON_SPS0WWV_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) << BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) +#define BIT_GET_SYSON_SPS0WWV_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT_8821C) & BIT_MASK_SYSON_SPS0WWV_WT_8821C) + +#define BIT_SHIFT_SYSON_SPS0LDO_WT_8821C 2 +#define BIT_MASK_SYSON_SPS0LDO_WT_8821C 0x3 +#define BIT_SYSON_SPS0LDO_WT_8821C(x) (((x) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) << BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) +#define BIT_GET_SYSON_SPS0LDO_WT_8821C(x) (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT_8821C) & BIT_MASK_SYSON_SPS0LDO_WT_8821C) + +#define BIT_SHIFT_SYSON_RCLK_SCALE_8821C 0 +#define BIT_MASK_SYSON_RCLK_SCALE_8821C 0x3 +#define BIT_SYSON_RCLK_SCALE_8821C(x) (((x) & BIT_MASK_SYSON_RCLK_SCALE_8821C) << BIT_SHIFT_SYSON_RCLK_SCALE_8821C) +#define BIT_GET_SYSON_RCLK_SCALE_8821C(x) (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE_8821C) & BIT_MASK_SYSON_RCLK_SCALE_8821C) + +/* 2 REG_CAL_TIMER_8821C */ + +#define BIT_SHIFT_MATCH_CNT_8821C 8 +#define BIT_MASK_MATCH_CNT_8821C 0xff +#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) +#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) + +#define BIT_SHIFT_CAL_SCAL_8821C 0 +#define BIT_MASK_CAL_SCAL_8821C 0xff +#define BIT_CAL_SCAL_8821C(x) (((x) & BIT_MASK_CAL_SCAL_8821C) << BIT_SHIFT_CAL_SCAL_8821C) +#define BIT_GET_CAL_SCAL_8821C(x) (((x) >> BIT_SHIFT_CAL_SCAL_8821C) & BIT_MASK_CAL_SCAL_8821C) + +/* 2 REG_ACLK_MON_8821C */ + +#define BIT_SHIFT_RCLK_MON_8821C 5 +#define BIT_MASK_RCLK_MON_8821C 0x7ff +#define BIT_RCLK_MON_8821C(x) (((x) & BIT_MASK_RCLK_MON_8821C) << BIT_SHIFT_RCLK_MON_8821C) +#define BIT_GET_RCLK_MON_8821C(x) (((x) >> BIT_SHIFT_RCLK_MON_8821C) & BIT_MASK_RCLK_MON_8821C) + +#define BIT_CAL_EN_8821C BIT(4) + +#define BIT_SHIFT_DPSTU_8821C 2 +#define BIT_MASK_DPSTU_8821C 0x3 +#define BIT_DPSTU_8821C(x) (((x) & BIT_MASK_DPSTU_8821C) << BIT_SHIFT_DPSTU_8821C) +#define BIT_GET_DPSTU_8821C(x) (((x) >> BIT_SHIFT_DPSTU_8821C) & BIT_MASK_DPSTU_8821C) + +#define BIT_SUS_16X_8821C BIT(1) + +/* 2 REG_GPIO_MUXCFG_8821C */ +#define BIT_FSPI_EN_8821C BIT(19) +#define BIT_WL_RTS_EXT_32K_SEL_8821C BIT(18) +#define BIT_WLGP_SPI_EN_8821C BIT(16) +#define BIT_SIC_LBK_8821C BIT(15) +#define BIT_ENHTP_8821C BIT(14) +#define BIT_ENSIC_8821C BIT(12) +#define BIT_SIC_SWRST_8821C BIT(11) +#define BIT_PO_WIFI_PTA_PINS_8821C BIT(10) +#define BIT_PO_BT_PTA_PINS_8821C BIT(9) +#define BIT_ENUART_8821C BIT(8) + +#define BIT_SHIFT_BTMODE_8821C 6 +#define BIT_MASK_BTMODE_8821C 0x3 +#define BIT_BTMODE_8821C(x) (((x) & BIT_MASK_BTMODE_8821C) << BIT_SHIFT_BTMODE_8821C) +#define BIT_GET_BTMODE_8821C(x) (((x) >> BIT_SHIFT_BTMODE_8821C) & BIT_MASK_BTMODE_8821C) + +#define BIT_ENBT_8821C BIT(5) +#define BIT_EROM_EN_8821C BIT(4) +#define BIT_WLRFE_6_7_EN_8821C BIT(3) +#define BIT_WLRFE_4_5_EN_8821C BIT(2) + +#define BIT_SHIFT_GPIOSEL_8821C 0 +#define BIT_MASK_GPIOSEL_8821C 0x3 +#define BIT_GPIOSEL_8821C(x) (((x) & BIT_MASK_GPIOSEL_8821C) << BIT_SHIFT_GPIOSEL_8821C) +#define BIT_GET_GPIOSEL_8821C(x) (((x) >> BIT_SHIFT_GPIOSEL_8821C) & BIT_MASK_GPIOSEL_8821C) + +/* 2 REG_GPIO_PIN_CTRL_8821C */ + +#define BIT_SHIFT_GPIO_MOD_7_TO_0_8821C 24 +#define BIT_MASK_GPIO_MOD_7_TO_0_8821C 0xff +#define BIT_GPIO_MOD_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) << BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) +#define BIT_GET_GPIO_MOD_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0_8821C) & BIT_MASK_GPIO_MOD_7_TO_0_8821C) + +#define BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C 16 +#define BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C 0xff +#define BIT_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) +#define BIT_GET_GPIO_IO_SEL_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0_8821C) & BIT_MASK_GPIO_IO_SEL_7_TO_0_8821C) + +#define BIT_SHIFT_GPIO_OUT_7_TO_0_8821C 8 +#define BIT_MASK_GPIO_OUT_7_TO_0_8821C 0xff +#define BIT_GPIO_OUT_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) << BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) +#define BIT_GET_GPIO_OUT_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0_8821C) & BIT_MASK_GPIO_OUT_7_TO_0_8821C) + +#define BIT_SHIFT_GPIO_IN_7_TO_0_8821C 0 +#define BIT_MASK_GPIO_IN_7_TO_0_8821C 0xff +#define BIT_GPIO_IN_7_TO_0_8821C(x) (((x) & BIT_MASK_GPIO_IN_7_TO_0_8821C) << BIT_SHIFT_GPIO_IN_7_TO_0_8821C) +#define BIT_GET_GPIO_IN_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0_8821C) & BIT_MASK_GPIO_IN_7_TO_0_8821C) + +/* 2 REG_GPIO_INTM_8821C */ + +#define BIT_SHIFT_MUXDBG_SEL_8821C 30 +#define BIT_MASK_MUXDBG_SEL_8821C 0x3 +#define BIT_MUXDBG_SEL_8821C(x) (((x) & BIT_MASK_MUXDBG_SEL_8821C) << BIT_SHIFT_MUXDBG_SEL_8821C) +#define BIT_GET_MUXDBG_SEL_8821C(x) (((x) >> BIT_SHIFT_MUXDBG_SEL_8821C) & BIT_MASK_MUXDBG_SEL_8821C) + +#define BIT_EXTWOL_SEL_8821C BIT(17) +#define BIT_EXTWOL_EN_8821C BIT(16) +#define BIT_GPIOF_INT_MD_8821C BIT(15) +#define BIT_GPIOE_INT_MD_8821C BIT(14) +#define BIT_GPIOD_INT_MD_8821C BIT(13) +#define BIT_GPIOF_INT_MD_8821C BIT(15) +#define BIT_GPIOE_INT_MD_8821C BIT(14) +#define BIT_GPIOD_INT_MD_8821C BIT(13) +#define BIT_GPIOC_INT_MD_8821C BIT(12) +#define BIT_GPIOB_INT_MD_8821C BIT(11) +#define BIT_GPIOA_INT_MD_8821C BIT(10) +#define BIT_GPIO9_INT_MD_8821C BIT(9) +#define BIT_GPIO8_INT_MD_8821C BIT(8) +#define BIT_GPIO7_INT_MD_8821C BIT(7) +#define BIT_GPIO6_INT_MD_8821C BIT(6) +#define BIT_GPIO5_INT_MD_8821C BIT(5) +#define BIT_GPIO4_INT_MD_8821C BIT(4) +#define BIT_GPIO3_INT_MD_8821C BIT(3) +#define BIT_GPIO2_INT_MD_8821C BIT(2) +#define BIT_GPIO1_INT_MD_8821C BIT(1) +#define BIT_GPIO0_INT_MD_8821C BIT(0) + +/* 2 REG_LED_CFG_8821C */ +#define BIT_GPIO3_WL_CTRL_EN_8821C BIT(27) +#define BIT_LNAON_SEL_EN_8821C BIT(26) +#define BIT_PAPE_SEL_EN_8821C BIT(25) +#define BIT_DPDT_WLBT_SEL_8821C BIT(24) +#define BIT_DPDT_SEL_EN_8821C BIT(23) +#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22) +#define BIT_GPIO13_14_WL_CTRL_EN_8821C BIT(22) +#define BIT_LED2DIS_8821C BIT(21) +#define BIT_LED2PL_8821C BIT(20) +#define BIT_LED2SV_8821C BIT(19) + +#define BIT_SHIFT_LED2CM_8821C 16 +#define BIT_MASK_LED2CM_8821C 0x7 +#define BIT_LED2CM_8821C(x) (((x) & BIT_MASK_LED2CM_8821C) << BIT_SHIFT_LED2CM_8821C) +#define BIT_GET_LED2CM_8821C(x) (((x) >> BIT_SHIFT_LED2CM_8821C) & BIT_MASK_LED2CM_8821C) + +#define BIT_LED1DIS_8821C BIT(15) +#define BIT_LED1PL_8821C BIT(12) +#define BIT_LED1SV_8821C BIT(11) + +#define BIT_SHIFT_LED1CM_8821C 8 +#define BIT_MASK_LED1CM_8821C 0x7 +#define BIT_LED1CM_8821C(x) (((x) & BIT_MASK_LED1CM_8821C) << BIT_SHIFT_LED1CM_8821C) +#define BIT_GET_LED1CM_8821C(x) (((x) >> BIT_SHIFT_LED1CM_8821C) & BIT_MASK_LED1CM_8821C) + +#define BIT_LED0DIS_8821C BIT(7) + +#define BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C 5 +#define BIT_MASK_AFE_LDO_SWR_CHECK_8821C 0x3 +#define BIT_AFE_LDO_SWR_CHECK_8821C(x) (((x) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) << BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) +#define BIT_GET_AFE_LDO_SWR_CHECK_8821C(x) (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK_8821C) & BIT_MASK_AFE_LDO_SWR_CHECK_8821C) + +#define BIT_LED0PL_8821C BIT(4) +#define BIT_LED0SV_8821C BIT(3) + +#define BIT_SHIFT_LED0CM_8821C 0 +#define BIT_MASK_LED0CM_8821C 0x7 +#define BIT_LED0CM_8821C(x) (((x) & BIT_MASK_LED0CM_8821C) << BIT_SHIFT_LED0CM_8821C) +#define BIT_GET_LED0CM_8821C(x) (((x) >> BIT_SHIFT_LED0CM_8821C) & BIT_MASK_LED0CM_8821C) + +/* 2 REG_FSIMR_8821C */ +#define BIT_FS_PDNINT_EN_8821C BIT(31) +#define BIT_NFC_INT_PAD_EN_8821C BIT(30) +#define BIT_FS_SPS_OCP_INT_EN_8821C BIT(29) +#define BIT_FS_PWMERR_INT_EN_8821C BIT(28) +#define BIT_FS_GPIOF_INT_EN_8821C BIT(27) +#define BIT_FS_GPIOE_INT_EN_8821C BIT(26) +#define BIT_FS_GPIOD_INT_EN_8821C BIT(25) +#define BIT_FS_GPIOC_INT_EN_8821C BIT(24) +#define BIT_FS_GPIOB_INT_EN_8821C BIT(23) +#define BIT_FS_GPIOA_INT_EN_8821C BIT(22) +#define BIT_FS_GPIO9_INT_EN_8821C BIT(21) +#define BIT_FS_GPIO8_INT_EN_8821C BIT(20) +#define BIT_FS_GPIO7_INT_EN_8821C BIT(19) +#define BIT_FS_GPIO6_INT_EN_8821C BIT(18) +#define BIT_FS_GPIO5_INT_EN_8821C BIT(17) +#define BIT_FS_GPIO4_INT_EN_8821C BIT(16) +#define BIT_FS_GPIO3_INT_EN_8821C BIT(15) +#define BIT_FS_GPIO2_INT_EN_8821C BIT(14) +#define BIT_FS_GPIO1_INT_EN_8821C BIT(13) +#define BIT_FS_GPIO0_INT_EN_8821C BIT(12) +#define BIT_FS_HCI_SUS_EN_8821C BIT(11) +#define BIT_FS_HCI_RES_EN_8821C BIT(10) +#define BIT_FS_HCI_RESET_EN_8821C BIT(9) +#define BIT_USB_SCSI_CMD_EN_8821C BIT(8) +#define BIT_FS_BTON_STS_UPDATE_MSK_EN_8821C BIT(7) +#define BIT_ACT2RECOVERY_INT_EN_V1_8821C BIT(6) +#define BIT_GEN1GEN2_SWITCH_8821C BIT(5) +#define BIT_HCI_TXDMA_REQ_HIMR_8821C BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_MAK_8821C BIT(3) +#define BIT_FS_32K_ENTER_SETTING_MAK_8821C BIT(2) +#define BIT_FS_USB_LPMRSM_MSK_8821C BIT(1) +#define BIT_FS_USB_LPMINT_MSK_8821C BIT(0) + +/* 2 REG_FSISR_8821C */ +#define BIT_FS_PDNINT_8821C BIT(31) +#define BIT_FS_SPS_OCP_INT_8821C BIT(29) +#define BIT_FS_PWMERR_INT_8821C BIT(28) +#define BIT_FS_GPIOF_INT_8821C BIT(27) +#define BIT_FS_GPIOE_INT_8821C BIT(26) +#define BIT_FS_GPIOD_INT_8821C BIT(25) +#define BIT_FS_GPIOC_INT_8821C BIT(24) +#define BIT_FS_GPIOB_INT_8821C BIT(23) +#define BIT_FS_GPIOA_INT_8821C BIT(22) +#define BIT_FS_GPIO9_INT_8821C BIT(21) +#define BIT_FS_GPIO8_INT_8821C BIT(20) +#define BIT_FS_GPIO7_INT_8821C BIT(19) +#define BIT_FS_GPIO6_INT_8821C BIT(18) +#define BIT_FS_GPIO5_INT_8821C BIT(17) +#define BIT_FS_GPIO4_INT_8821C BIT(16) +#define BIT_FS_GPIO3_INT_8821C BIT(15) +#define BIT_FS_GPIO2_INT_8821C BIT(14) +#define BIT_FS_GPIO1_INT_8821C BIT(13) +#define BIT_FS_GPIO0_INT_8821C BIT(12) +#define BIT_FS_HCI_SUS_INT_8821C BIT(11) +#define BIT_FS_HCI_RES_INT_8821C BIT(10) +#define BIT_FS_HCI_RESET_INT_8821C BIT(9) +#define BIT_USB_SCSI_CMD_INT_8821C BIT(8) +#define BIT_ACT2RECOVERY_8821C BIT(6) +#define BIT_GEN1GEN2_SWITCH_8821C BIT(5) +#define BIT_HCI_TXDMA_REQ_HISR_8821C BIT(4) +#define BIT_FS_32K_LEAVE_SETTING_INT_8821C BIT(3) +#define BIT_FS_32K_ENTER_SETTING_INT_8821C BIT(2) +#define BIT_FS_USB_LPMRSM_INT_8821C BIT(1) +#define BIT_FS_USB_LPMINT_INT_8821C BIT(0) + +/* 2 REG_HSIMR_8821C */ +#define BIT_GPIOF_INT_EN_8821C BIT(31) +#define BIT_GPIOE_INT_EN_8821C BIT(30) +#define BIT_GPIOD_INT_EN_8821C BIT(29) +#define BIT_GPIOC_INT_EN_8821C BIT(28) +#define BIT_GPIOB_INT_EN_8821C BIT(27) +#define BIT_GPIOA_INT_EN_8821C BIT(26) +#define BIT_GPIO9_INT_EN_8821C BIT(25) +#define BIT_GPIO8_INT_EN_8821C BIT(24) +#define BIT_GPIO7_INT_EN_8821C BIT(23) +#define BIT_GPIO6_INT_EN_8821C BIT(22) +#define BIT_GPIO5_INT_EN_8821C BIT(21) +#define BIT_GPIO4_INT_EN_8821C BIT(20) +#define BIT_GPIO3_INT_EN_8821C BIT(19) +#define BIT_GPIO2_INT_EN_V1_8821C BIT(16) +#define BIT_GPIO1_INT_EN_8821C BIT(17) +#define BIT_GPIO0_INT_EN_8821C BIT(16) +#define BIT_PDNINT_EN_8821C BIT(7) +#define BIT_RON_INT_EN_8821C BIT(6) +#define BIT_SPS_OCP_INT_EN_8821C BIT(5) +#define BIT_GPIO15_0_INT_EN_8821C BIT(0) + +/* 2 REG_HSISR_8821C */ +#define BIT_GPIOF_INT_8821C BIT(31) +#define BIT_GPIOE_INT_8821C BIT(30) +#define BIT_GPIOD_INT_8821C BIT(29) +#define BIT_GPIOC_INT_8821C BIT(28) +#define BIT_GPIOB_INT_8821C BIT(27) +#define BIT_GPIOA_INT_8821C BIT(26) +#define BIT_GPIO9_INT_8821C BIT(25) +#define BIT_GPIO8_INT_8821C BIT(24) +#define BIT_GPIO7_INT_8821C BIT(23) +#define BIT_GPIO6_INT_8821C BIT(22) +#define BIT_GPIO5_INT_8821C BIT(21) +#define BIT_GPIO4_INT_8821C BIT(20) +#define BIT_GPIO3_INT_8821C BIT(19) +#define BIT_GPIO2_INT_V1_8821C BIT(16) +#define BIT_GPIO1_INT_8821C BIT(17) +#define BIT_GPIO0_INT_8821C BIT(16) +#define BIT_PDNINT_8821C BIT(7) +#define BIT_RON_INT_8821C BIT(6) +#define BIT_SPS_OCP_INT_8821C BIT(5) +#define BIT_GPIO15_0_INT_8821C BIT(0) + +/* 2 REG_GPIO_EXT_CTRL_8821C */ + +#define BIT_SHIFT_GPIO_MOD_15_TO_8_8821C 24 +#define BIT_MASK_GPIO_MOD_15_TO_8_8821C 0xff +#define BIT_GPIO_MOD_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) << BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) +#define BIT_GET_GPIO_MOD_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8_8821C) & BIT_MASK_GPIO_MOD_15_TO_8_8821C) + +#define BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C 16 +#define BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C 0xff +#define BIT_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) +#define BIT_GET_GPIO_IO_SEL_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8_8821C) & BIT_MASK_GPIO_IO_SEL_15_TO_8_8821C) + +#define BIT_SHIFT_GPIO_OUT_15_TO_8_8821C 8 +#define BIT_MASK_GPIO_OUT_15_TO_8_8821C 0xff +#define BIT_GPIO_OUT_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) << BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) +#define BIT_GET_GPIO_OUT_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8_8821C) & BIT_MASK_GPIO_OUT_15_TO_8_8821C) + +#define BIT_SHIFT_GPIO_IN_15_TO_8_8821C 0 +#define BIT_MASK_GPIO_IN_15_TO_8_8821C 0xff +#define BIT_GPIO_IN_15_TO_8_8821C(x) (((x) & BIT_MASK_GPIO_IN_15_TO_8_8821C) << BIT_SHIFT_GPIO_IN_15_TO_8_8821C) +#define BIT_GET_GPIO_IN_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8_8821C) & BIT_MASK_GPIO_IN_15_TO_8_8821C) + +/* 2 REG_PAD_CTRL1_8821C */ +#define BIT_PAPE_WLBT_SEL_8821C BIT(29) +#define BIT_LNAON_WLBT_SEL_8821C BIT(28) +#define BIT_BTGP_GPG3_FEN_8821C BIT(26) +#define BIT_BTGP_GPG2_FEN_8821C BIT(25) +#define BIT_BTGP_JTAG_EN_8821C BIT(24) +#define BIT_XTAL_CLK_EXTARNAL_EN_8821C BIT(23) +#define BIT_BTGP_UART0_EN_8821C BIT(22) +#define BIT_BTGP_UART1_EN_8821C BIT(21) +#define BIT_BTGP_SPI_EN_8821C BIT(20) +#define BIT_BTGP_GPIO_E2_8821C BIT(19) +#define BIT_BTGP_GPIO_EN_8821C BIT(18) + +#define BIT_SHIFT_BTGP_GPIO_SL_8821C 16 +#define BIT_MASK_BTGP_GPIO_SL_8821C 0x3 +#define BIT_BTGP_GPIO_SL_8821C(x) (((x) & BIT_MASK_BTGP_GPIO_SL_8821C) << BIT_SHIFT_BTGP_GPIO_SL_8821C) +#define BIT_GET_BTGP_GPIO_SL_8821C(x) (((x) >> BIT_SHIFT_BTGP_GPIO_SL_8821C) & BIT_MASK_BTGP_GPIO_SL_8821C) + +#define BIT_PAD_SDIO_SR_8821C BIT(14) +#define BIT_GPIO14_OUTPUT_PL_8821C BIT(13) +#define BIT_HOST_WAKE_PAD_PULL_EN_8821C BIT(12) +#define BIT_HOST_WAKE_PAD_SL_8821C BIT(11) +#define BIT_PAD_LNAON_SR_8821C BIT(10) +#define BIT_PAD_LNAON_E2_8821C BIT(9) +#define BIT_SW_LNAON_G_SEL_DATA_8821C BIT(8) +#define BIT_SW_LNAON_A_SEL_DATA_8821C BIT(7) +#define BIT_PAD_PAPE_SR_8821C BIT(6) +#define BIT_PAD_PAPE_E2_8821C BIT(5) +#define BIT_SW_PAPE_G_SEL_DATA_8821C BIT(4) +#define BIT_SW_PAPE_A_SEL_DATA_8821C BIT(3) +#define BIT_PAD_DPDT_SR_8821C BIT(2) +#define BIT_PAD_DPDT_PAD_E2_8821C BIT(1) +#define BIT_SW_DPDT_SEL_DATA_8821C BIT(0) + +/* 2 REG_WL_BT_PWR_CTRL_8821C */ +#define BIT_ISO_BD2PP_8821C BIT(31) +#define BIT_LDOV12B_EN_8821C BIT(30) +#define BIT_CKEN_BTGPS_8821C BIT(29) +#define BIT_FEN_BTGPS_8821C BIT(28) +#define BIT_BTCPU_BOOTSEL_8821C BIT(27) +#define BIT_SPI_SPEEDUP_8821C BIT(26) +#define BIT_DEVWAKE_PAD_TYPE_SEL_8821C BIT(24) +#define BIT_CLKREQ_PAD_TYPE_SEL_8821C BIT(23) +#define BIT_ISO_BTPON2PP_8821C BIT(22) +#define BIT_BT_HWROF_EN_8821C BIT(19) +#define BIT_BT_FUNC_EN_8821C BIT(18) +#define BIT_BT_HWPDN_SL_8821C BIT(17) +#define BIT_BT_DISN_EN_8821C BIT(16) +#define BIT_BT_PDN_PULL_EN_8821C BIT(15) +#define BIT_WL_PDN_PULL_EN_8821C BIT(14) +#define BIT_EXTERNAL_REQUEST_PL_8821C BIT(13) +#define BIT_GPIO0_2_3_PULL_LOW_EN_8821C BIT(12) +#define BIT_ISO_BA2PP_8821C BIT(11) +#define BIT_BT_AFE_LDO_EN_8821C BIT(10) +#define BIT_BT_AFE_PLL_EN_8821C BIT(9) +#define BIT_BT_DIG_CLK_EN_8821C BIT(8) +#define BIT_WL_DRV_EXIST_IDX_8821C BIT(5) +#define BIT_DOP_EHPAD_8821C BIT(4) +#define BIT_WL_HWROF_EN_8821C BIT(3) +#define BIT_WL_FUNC_EN_8821C BIT(2) +#define BIT_WL_HWPDN_SL_8821C BIT(1) +#define BIT_WL_HWPDN_EN_8821C BIT(0) + +/* 2 REG_SDM_DEBUG_8821C */ + +#define BIT_SHIFT_WLCLK_PHASE_8821C 0 +#define BIT_MASK_WLCLK_PHASE_8821C 0x1f +#define BIT_WLCLK_PHASE_8821C(x) (((x) & BIT_MASK_WLCLK_PHASE_8821C) << BIT_SHIFT_WLCLK_PHASE_8821C) +#define BIT_GET_WLCLK_PHASE_8821C(x) (((x) >> BIT_SHIFT_WLCLK_PHASE_8821C) & BIT_MASK_WLCLK_PHASE_8821C) + +/* 2 REG_SYS_SDIO_CTRL_8821C */ +#define BIT_DBG_GNT_WL_BT_8821C BIT(27) +#define BIT_LTE_MUX_CTRL_PATH_8821C BIT(26) +#define BIT_LTE_COEX_UART_8821C BIT(25) +#define BIT_3W_LTE_WL_GPIO_8821C BIT(24) +#define BIT_SDIO_INT_POLARITY_8821C BIT(19) +#define BIT_SDIO_INT_8821C BIT(18) +#define BIT_SDIO_OFF_EN_8821C BIT(17) +#define BIT_SDIO_ON_EN_8821C BIT(16) +#define BIT_PCIE_WAIT_TIMEOUT_EVENT_8821C BIT(10) +#define BIT_PCIE_WAIT_TIME_8821C BIT(9) +#define BIT_MPCIE_REFCLK_XTAL_SEL_8821C BIT(8) +#define BIT_RES_USB_MASS_STORAGE_DESC_8821C BIT(1) +#define BIT_USB_WAIT_TIME_8821C BIT(0) + +/* 2 REG_HCI_OPT_CTRL_8821C */ + +#define BIT_SHIFT_TSFT_SEL_8821C 29 +#define BIT_MASK_TSFT_SEL_8821C 0x7 +#define BIT_TSFT_SEL_8821C(x) (((x) & BIT_MASK_TSFT_SEL_8821C) << BIT_SHIFT_TSFT_SEL_8821C) +#define BIT_GET_TSFT_SEL_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_8821C) & BIT_MASK_TSFT_SEL_8821C) + +#define BIT_USB_HOST_PWR_OFF_EN_8821C BIT(12) +#define BIT_SYM_LPS_BLOCK_EN_8821C BIT(11) +#define BIT_USB_LPM_ACT_EN_8821C BIT(10) +#define BIT_USB_LPM_NY_8821C BIT(9) +#define BIT_USB_SUS_DIS_8821C BIT(8) + +#define BIT_SHIFT_SDIO_PAD_E_8821C 5 +#define BIT_MASK_SDIO_PAD_E_8821C 0x7 +#define BIT_SDIO_PAD_E_8821C(x) (((x) & BIT_MASK_SDIO_PAD_E_8821C) << BIT_SHIFT_SDIO_PAD_E_8821C) +#define BIT_GET_SDIO_PAD_E_8821C(x) (((x) >> BIT_SHIFT_SDIO_PAD_E_8821C) & BIT_MASK_SDIO_PAD_E_8821C) + +#define BIT_USB_LPPLL_EN_8821C BIT(4) +#define BIT_ROP_SW15_8821C BIT(2) +#define BIT_PCI_CKRDY_OPT_8821C BIT(1) +#define BIT_PCI_VAUX_EN_8821C BIT(0) + +/* 2 REG_AFE_CTRL4_8821C */ + +/* 2 REG_LDO_SWR_CTRL_8821C */ +#define BIT_ZCD_HW_AUTO_EN_8821C BIT(27) +#define BIT_ZCD_REGSEL_8821C BIT(26) + +#define BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C 21 +#define BIT_MASK_AUTO_ZCD_IN_CODE_8821C 0x1f +#define BIT_AUTO_ZCD_IN_CODE_8821C(x) (((x) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) << BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) +#define BIT_GET_AUTO_ZCD_IN_CODE_8821C(x) (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE_8821C) & BIT_MASK_AUTO_ZCD_IN_CODE_8821C) + +#define BIT_SHIFT_ZCD_CODE_IN_L_8821C 16 +#define BIT_MASK_ZCD_CODE_IN_L_8821C 0x1f +#define BIT_ZCD_CODE_IN_L_8821C(x) (((x) & BIT_MASK_ZCD_CODE_IN_L_8821C) << BIT_SHIFT_ZCD_CODE_IN_L_8821C) +#define BIT_GET_ZCD_CODE_IN_L_8821C(x) (((x) >> BIT_SHIFT_ZCD_CODE_IN_L_8821C) & BIT_MASK_ZCD_CODE_IN_L_8821C) + +#define BIT_SHIFT_LDO_HV5_DUMMY_8821C 14 +#define BIT_MASK_LDO_HV5_DUMMY_8821C 0x3 +#define BIT_LDO_HV5_DUMMY_8821C(x) (((x) & BIT_MASK_LDO_HV5_DUMMY_8821C) << BIT_SHIFT_LDO_HV5_DUMMY_8821C) +#define BIT_GET_LDO_HV5_DUMMY_8821C(x) (((x) >> BIT_SHIFT_LDO_HV5_DUMMY_8821C) & BIT_MASK_LDO_HV5_DUMMY_8821C) + +#define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C 12 +#define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C 0x3 +#define BIT_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) +#define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1_8821C) + +#define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C 10 +#define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C 0x3 +#define BIT_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) +#define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1_8821C) + +#define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C 8 +#define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C 0x3 +#define BIT_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) +#define BIT_GET_REG_LOAD33_BIT0_TO_BIT1_8821C(x) (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1_8821C) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1_8821C) + +#define BIT_REG_BYPASS_L_8821C BIT(7) +#define BIT_REG_LDOF_L_8821C BIT(6) +#define BIT_REG_OCPS_L_8821C BIT(5) +#define BIT_ARENB_L_8821C BIT(3) + +#define BIT_SHIFT_CFC_L_8821C 1 +#define BIT_MASK_CFC_L_8821C 0x3 +#define BIT_CFC_L_8821C(x) (((x) & BIT_MASK_CFC_L_8821C) << BIT_SHIFT_CFC_L_8821C) +#define BIT_GET_CFC_L_8821C(x) (((x) >> BIT_SHIFT_CFC_L_8821C) & BIT_MASK_CFC_L_8821C) + +#define BIT_REG_TYPE_L_8821C BIT(0) + +/* 2 REG_MCUFW_CTRL_8821C */ + +#define BIT_SHIFT_RPWM_8821C 24 +#define BIT_MASK_RPWM_8821C 0xff +#define BIT_RPWM_8821C(x) (((x) & BIT_MASK_RPWM_8821C) << BIT_SHIFT_RPWM_8821C) +#define BIT_GET_RPWM_8821C(x) (((x) >> BIT_SHIFT_RPWM_8821C) & BIT_MASK_RPWM_8821C) + +#define BIT_ANA_PORT_EN_8821C BIT(22) +#define BIT_MAC_PORT_EN_8821C BIT(21) +#define BIT_BOOT_FSPI_EN_8821C BIT(20) +#define BIT_ROM_DLEN_8821C BIT(19) + +#define BIT_SHIFT_ROM_PGE_8821C 16 +#define BIT_MASK_ROM_PGE_8821C 0x7 +#define BIT_ROM_PGE_8821C(x) (((x) & BIT_MASK_ROM_PGE_8821C) << BIT_SHIFT_ROM_PGE_8821C) +#define BIT_GET_ROM_PGE_8821C(x) (((x) >> BIT_SHIFT_ROM_PGE_8821C) & BIT_MASK_ROM_PGE_8821C) + +#define BIT_FW_INIT_RDY_8821C BIT(15) +#define BIT_FW_DW_RDY_8821C BIT(14) + +#define BIT_SHIFT_CPU_CLK_SEL_8821C 12 +#define BIT_MASK_CPU_CLK_SEL_8821C 0x3 +#define BIT_CPU_CLK_SEL_8821C(x) (((x) & BIT_MASK_CPU_CLK_SEL_8821C) << BIT_SHIFT_CPU_CLK_SEL_8821C) +#define BIT_GET_CPU_CLK_SEL_8821C(x) (((x) >> BIT_SHIFT_CPU_CLK_SEL_8821C) & BIT_MASK_CPU_CLK_SEL_8821C) + +#define BIT_CCLK_CHG_MASK_8821C BIT(11) +#define BIT_EMEM__TXBUF_CHKSUM_OK_8821C BIT(10) +#define BIT_EMEM_TXBUF_DW_RDY_8821C BIT(9) +#define BIT_EMEM_CHKSUM_OK_8821C BIT(8) +#define BIT_EMEM_DW_OK_8821C BIT(7) +#define BIT_DMEM_CHKSUM_OK_8821C BIT(6) +#define BIT_DMEM_DW_OK_8821C BIT(5) +#define BIT_IMEM_CHKSUM_OK_8821C BIT(4) +#define BIT_IMEM_DW_OK_8821C BIT(3) +#define BIT_IMEM_BOOT_LOAD_CHKSUM_OK_8821C BIT(2) +#define BIT_IMEM_BOOT_LOAD_DW_OK_8821C BIT(1) +#define BIT_MCUFWDL_EN_8821C BIT(0) + +/* 2 REG_MCU_TST_CFG_8821C */ + +#define BIT_SHIFT_LBKTST_8821C 0 +#define BIT_MASK_LBKTST_8821C 0xffff +#define BIT_LBKTST_8821C(x) (((x) & BIT_MASK_LBKTST_8821C) << BIT_SHIFT_LBKTST_8821C) +#define BIT_GET_LBKTST_8821C(x) (((x) >> BIT_SHIFT_LBKTST_8821C) & BIT_MASK_LBKTST_8821C) + +/* 2 REG_HMEBOX_E0_E1_8821C */ + +#define BIT_SHIFT_HOST_MSG_E1_8821C 16 +#define BIT_MASK_HOST_MSG_E1_8821C 0xffff +#define BIT_HOST_MSG_E1_8821C(x) (((x) & BIT_MASK_HOST_MSG_E1_8821C) << BIT_SHIFT_HOST_MSG_E1_8821C) +#define BIT_GET_HOST_MSG_E1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E1_8821C) & BIT_MASK_HOST_MSG_E1_8821C) + +#define BIT_SHIFT_HOST_MSG_E0_8821C 0 +#define BIT_MASK_HOST_MSG_E0_8821C 0xffff +#define BIT_HOST_MSG_E0_8821C(x) (((x) & BIT_MASK_HOST_MSG_E0_8821C) << BIT_SHIFT_HOST_MSG_E0_8821C) +#define BIT_GET_HOST_MSG_E0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E0_8821C) & BIT_MASK_HOST_MSG_E0_8821C) + +/* 2 REG_HMEBOX_E2_E3_8821C */ + +#define BIT_SHIFT_HOST_MSG_E3_8821C 16 +#define BIT_MASK_HOST_MSG_E3_8821C 0xffff +#define BIT_HOST_MSG_E3_8821C(x) (((x) & BIT_MASK_HOST_MSG_E3_8821C) << BIT_SHIFT_HOST_MSG_E3_8821C) +#define BIT_GET_HOST_MSG_E3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E3_8821C) & BIT_MASK_HOST_MSG_E3_8821C) + +#define BIT_SHIFT_HOST_MSG_E2_8821C 0 +#define BIT_MASK_HOST_MSG_E2_8821C 0xffff +#define BIT_HOST_MSG_E2_8821C(x) (((x) & BIT_MASK_HOST_MSG_E2_8821C) << BIT_SHIFT_HOST_MSG_E2_8821C) +#define BIT_GET_HOST_MSG_E2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_E2_8821C) & BIT_MASK_HOST_MSG_E2_8821C) + +/* 2 REG_WLLPS_CTRL_8821C */ +#define BIT_WLLPSOP_EABM_8821C BIT(31) +#define BIT_WLLPSOP_ACKF_8821C BIT(30) +#define BIT_WLLPSOP_DLDM_8821C BIT(29) +#define BIT_WLLPSOP_ESWR_8821C BIT(28) +#define BIT_WLLPSOP_PWMM_8821C BIT(27) +#define BIT_WLLPSOP_EECK_8821C BIT(26) +#define BIT_WLLPSOP_WLMACOFF_8821C BIT(25) +#define BIT_WLLPSOP_EXTAL_8821C BIT(24) +#define BIT_WL_SYNPON_VOLTSPDN_8821C BIT(23) +#define BIT_WLLPSOP_WLBBOFF_8821C BIT(22) +#define BIT_WLLPSOP_WLMEM_DS_8821C BIT(21) + +#define BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C 12 +#define BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C 0xf +#define BIT_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) << BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) +#define BIT_GET_LPLDH12_VADJ_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN_8821C) & BIT_MASK_LPLDH12_VADJ_STEP_DN_8821C) + +#define BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C 8 +#define BIT_MASK_V15ADJ_L1_STEP_DN_8821C 0x7 +#define BIT_V15ADJ_L1_STEP_DN_8821C(x) (((x) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) << BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) +#define BIT_GET_V15ADJ_L1_STEP_DN_8821C(x) (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN_8821C) & BIT_MASK_V15ADJ_L1_STEP_DN_8821C) + +#define BIT_REGU_32K_CLK_EN_8821C BIT(1) +#define BIT_WL_LPS_EN_8821C BIT(0) + +/* 2 REG_AFE_CTRL5_8821C */ +#define BIT_BB_DBG_SEL_AFE_SDM_BIT0_8821C BIT(31) +#define BIT_ORDER_SDM_8821C BIT(30) +#define BIT_RFE_SEL_SDM_8821C BIT(29) + +#define BIT_SHIFT_REF_SEL_8821C 25 +#define BIT_MASK_REF_SEL_8821C 0xf +#define BIT_REF_SEL_8821C(x) (((x) & BIT_MASK_REF_SEL_8821C) << BIT_SHIFT_REF_SEL_8821C) +#define BIT_GET_REF_SEL_8821C(x) (((x) >> BIT_SHIFT_REF_SEL_8821C) & BIT_MASK_REF_SEL_8821C) + +#define BIT_SHIFT_F0F_SDM_8821C 12 +#define BIT_MASK_F0F_SDM_8821C 0x1fff +#define BIT_F0F_SDM_8821C(x) (((x) & BIT_MASK_F0F_SDM_8821C) << BIT_SHIFT_F0F_SDM_8821C) +#define BIT_GET_F0F_SDM_8821C(x) (((x) >> BIT_SHIFT_F0F_SDM_8821C) & BIT_MASK_F0F_SDM_8821C) + +#define BIT_SHIFT_F0N_SDM_8821C 9 +#define BIT_MASK_F0N_SDM_8821C 0x7 +#define BIT_F0N_SDM_8821C(x) (((x) & BIT_MASK_F0N_SDM_8821C) << BIT_SHIFT_F0N_SDM_8821C) +#define BIT_GET_F0N_SDM_8821C(x) (((x) >> BIT_SHIFT_F0N_SDM_8821C) & BIT_MASK_F0N_SDM_8821C) + +#define BIT_SHIFT_DIVN_SDM_8821C 3 +#define BIT_MASK_DIVN_SDM_8821C 0x3f +#define BIT_DIVN_SDM_8821C(x) (((x) & BIT_MASK_DIVN_SDM_8821C) << BIT_SHIFT_DIVN_SDM_8821C) +#define BIT_GET_DIVN_SDM_8821C(x) (((x) >> BIT_SHIFT_DIVN_SDM_8821C) & BIT_MASK_DIVN_SDM_8821C) + +/* 2 REG_GPIO_DEBOUNCE_CTRL_8821C */ +#define BIT_WLGP_DBC1EN_8821C BIT(15) + +#define BIT_SHIFT_WLGP_DBC1_8821C 8 +#define BIT_MASK_WLGP_DBC1_8821C 0xf +#define BIT_WLGP_DBC1_8821C(x) (((x) & BIT_MASK_WLGP_DBC1_8821C) << BIT_SHIFT_WLGP_DBC1_8821C) +#define BIT_GET_WLGP_DBC1_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC1_8821C) & BIT_MASK_WLGP_DBC1_8821C) + +#define BIT_WLGP_DBC0EN_8821C BIT(7) + +#define BIT_SHIFT_WLGP_DBC0_8821C 0 +#define BIT_MASK_WLGP_DBC0_8821C 0xf +#define BIT_WLGP_DBC0_8821C(x) (((x) & BIT_MASK_WLGP_DBC0_8821C) << BIT_SHIFT_WLGP_DBC0_8821C) +#define BIT_GET_WLGP_DBC0_8821C(x) (((x) >> BIT_SHIFT_WLGP_DBC0_8821C) & BIT_MASK_WLGP_DBC0_8821C) + +/* 2 REG_RPWM2_8821C */ + +#define BIT_SHIFT_RPWM2_8821C 16 +#define BIT_MASK_RPWM2_8821C 0xffff +#define BIT_RPWM2_8821C(x) (((x) & BIT_MASK_RPWM2_8821C) << BIT_SHIFT_RPWM2_8821C) +#define BIT_GET_RPWM2_8821C(x) (((x) >> BIT_SHIFT_RPWM2_8821C) & BIT_MASK_RPWM2_8821C) + +/* 2 REG_SYSON_FSM_MON_8821C */ + +#define BIT_SHIFT_FSM_MON_SEL_8821C 24 +#define BIT_MASK_FSM_MON_SEL_8821C 0x7 +#define BIT_FSM_MON_SEL_8821C(x) (((x) & BIT_MASK_FSM_MON_SEL_8821C) << BIT_SHIFT_FSM_MON_SEL_8821C) +#define BIT_GET_FSM_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_FSM_MON_SEL_8821C) & BIT_MASK_FSM_MON_SEL_8821C) + +#define BIT_DOP_ELDO_8821C BIT(23) +#define BIT_FSM_MON_UPD_8821C BIT(15) + +#define BIT_SHIFT_FSM_PAR_8821C 0 +#define BIT_MASK_FSM_PAR_8821C 0x7fff +#define BIT_FSM_PAR_8821C(x) (((x) & BIT_MASK_FSM_PAR_8821C) << BIT_SHIFT_FSM_PAR_8821C) +#define BIT_GET_FSM_PAR_8821C(x) (((x) >> BIT_SHIFT_FSM_PAR_8821C) & BIT_MASK_FSM_PAR_8821C) + +/* 2 REG_AFE_CTRL6_8821C */ + +#define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0 +#define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C 0x7 +#define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) +#define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C(x) (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1_8821C) + +/* 2 REG_PMC_DBG_CTRL1_8821C */ +#define BIT_BT_INT_EN_8821C BIT(31) + +#define BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C 16 +#define BIT_MASK_RD_WR_WIFI_BT_INFO_8821C 0x7fff +#define BIT_RD_WR_WIFI_BT_INFO_8821C(x) (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) << BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) +#define BIT_GET_RD_WR_WIFI_BT_INFO_8821C(x) (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO_8821C) & BIT_MASK_RD_WR_WIFI_BT_INFO_8821C) + +#define BIT_PMC_WR_OVF_8821C BIT(8) + +#define BIT_SHIFT_WLPMC_ERRINT_8821C 0 +#define BIT_MASK_WLPMC_ERRINT_8821C 0xff +#define BIT_WLPMC_ERRINT_8821C(x) (((x) & BIT_MASK_WLPMC_ERRINT_8821C) << BIT_SHIFT_WLPMC_ERRINT_8821C) +#define BIT_GET_WLPMC_ERRINT_8821C(x) (((x) >> BIT_SHIFT_WLPMC_ERRINT_8821C) & BIT_MASK_WLPMC_ERRINT_8821C) + +/* 2 REG_AFE_CTRL7_8821C */ + +#define BIT_SHIFT_SEL_V_8821C 30 +#define BIT_MASK_SEL_V_8821C 0x3 +#define BIT_SEL_V_8821C(x) (((x) & BIT_MASK_SEL_V_8821C) << BIT_SHIFT_SEL_V_8821C) +#define BIT_GET_SEL_V_8821C(x) (((x) >> BIT_SHIFT_SEL_V_8821C) & BIT_MASK_SEL_V_8821C) + +#define BIT_SEL_LDO_PC_8821C BIT(29) + +#define BIT_SHIFT_CK_MON_SEL_8821C 26 +#define BIT_MASK_CK_MON_SEL_8821C 0x7 +#define BIT_CK_MON_SEL_8821C(x) (((x) & BIT_MASK_CK_MON_SEL_8821C) << BIT_SHIFT_CK_MON_SEL_8821C) +#define BIT_GET_CK_MON_SEL_8821C(x) (((x) >> BIT_SHIFT_CK_MON_SEL_8821C) & BIT_MASK_CK_MON_SEL_8821C) + +#define BIT_CK_MON_EN_8821C BIT(25) +#define BIT_FREF_EDGE_8821C BIT(24) +#define BIT_CK320M_EN_8821C BIT(23) +#define BIT_CK_5M_EN_8821C BIT(22) +#define BIT_TESTEN_8821C BIT(21) + +/* 2 REG_HIMR0_8821C */ +#define BIT_TIMEOUT_INTERRUPT2_MASK_8821C BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_MASK_8821C BIT(30) +#define BIT_PSTIMEOUT_MSK_8821C BIT(29) +#define BIT_GTINT4_MSK_8821C BIT(28) +#define BIT_GTINT3_MSK_8821C BIT(27) +#define BIT_TXBCN0ERR_MSK_8821C BIT(26) +#define BIT_TXBCN0OK_MSK_8821C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_MSK_8821C BIT(24) +#define BIT_BCNDMAINT0_MSK_8821C BIT(20) +#define BIT_BCNDERR0_MSK_8821C BIT(16) +#define BIT_HSISR_IND_ON_INT_MSK_8821C BIT(15) +#define BIT_BCNDMAINT_E_MSK_8821C BIT(14) +#define BIT_CTWEND_MSK_8821C BIT(12) +#define BIT_HISR1_IND_MSK_8821C BIT(11) +#define BIT_C2HCMD_MSK_8821C BIT(10) +#define BIT_CPWM2_MSK_8821C BIT(9) +#define BIT_CPWM_MSK_8821C BIT(8) +#define BIT_HIGHDOK_MSK_8821C BIT(7) +#define BIT_MGTDOK_MSK_8821C BIT(6) +#define BIT_BKDOK_MSK_8821C BIT(5) +#define BIT_BEDOK_MSK_8821C BIT(4) +#define BIT_VIDOK_MSK_8821C BIT(3) +#define BIT_VODOK_MSK_8821C BIT(2) +#define BIT_RDU_MSK_8821C BIT(1) +#define BIT_RXOK_MSK_8821C BIT(0) + +/* 2 REG_HISR0_8821C */ +#define BIT_TIMEOUT_INTERRUPT2_8821C BIT(31) +#define BIT_TIMEOUT_INTERRUTP1_8821C BIT(30) +#define BIT_PSTIMEOUT_8821C BIT(29) +#define BIT_GTINT4_8821C BIT(28) +#define BIT_GTINT3_8821C BIT(27) +#define BIT_TXBCN0ERR_8821C BIT(26) +#define BIT_TXBCN0OK_8821C BIT(25) +#define BIT_TSF_BIT32_TOGGLE_8821C BIT(24) +#define BIT_BCNDMAINT0_8821C BIT(20) +#define BIT_BCNDERR0_8821C BIT(16) +#define BIT_HSISR_IND_ON_INT_8821C BIT(15) +#define BIT_BCNDMAINT_E_8821C BIT(14) +#define BIT_CTWEND_8821C BIT(12) +#define BIT_HISR1_IND_INT_8821C BIT(11) +#define BIT_C2HCMD_8821C BIT(10) +#define BIT_CPWM2_8821C BIT(9) +#define BIT_CPWM_8821C BIT(8) +#define BIT_HIGHDOK_8821C BIT(7) +#define BIT_MGTDOK_8821C BIT(6) +#define BIT_BKDOK_8821C BIT(5) +#define BIT_BEDOK_8821C BIT(4) +#define BIT_VIDOK_8821C BIT(3) +#define BIT_VODOK_8821C BIT(2) +#define BIT_RDU_8821C BIT(1) +#define BIT_RXOK_8821C BIT(0) + +/* 2 REG_HIMR1_8821C */ +#define BIT_TXFIFO_TH_INT_8821C BIT(30) +#define BIT_BTON_STS_UPDATE_MASK_8821C BIT(29) +#define BIT_MCU_ERR_MASK_8821C BIT(28) +#define BIT_BCNDMAINT7__MSK_8821C BIT(27) +#define BIT_BCNDMAINT6__MSK_8821C BIT(26) +#define BIT_BCNDMAINT5__MSK_8821C BIT(25) +#define BIT_BCNDMAINT4__MSK_8821C BIT(24) +#define BIT_BCNDMAINT3_MSK_8821C BIT(23) +#define BIT_BCNDMAINT2_MSK_8821C BIT(22) +#define BIT_BCNDMAINT1_MSK_8821C BIT(21) +#define BIT_BCNDERR7_MSK_8821C BIT(20) +#define BIT_BCNDERR6_MSK_8821C BIT(19) +#define BIT_BCNDERR5_MSK_8821C BIT(18) +#define BIT_BCNDERR4_MSK_8821C BIT(17) +#define BIT_BCNDERR3_MSK_8821C BIT(16) +#define BIT_BCNDERR2_MSK_8821C BIT(15) +#define BIT_BCNDERR1_MSK_8821C BIT(14) +#define BIT_ATIMEND_E_MSK_8821C BIT(13) +#define BIT_ATIMEND__MSK_8821C BIT(12) +#define BIT_TXERR_MSK_8821C BIT(11) +#define BIT_RXERR_MSK_8821C BIT(10) +#define BIT_TXFOVW_MSK_8821C BIT(9) +#define BIT_FOVW_MSK_8821C BIT(8) +#define BIT_CPU_MGQ_TXDONE_MSK_8821C BIT(5) +#define BIT_PS_TIMER_C_MSK_8821C BIT(4) +#define BIT_PS_TIMER_B_MSK_8821C BIT(3) +#define BIT_PS_TIMER_A_MSK_8821C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_MSK_8821C BIT(1) + +/* 2 REG_HISR1_8821C */ +#define BIT_TXFIFO_TH_INT_8821C BIT(30) +#define BIT_BTON_STS_UPDATE_INT_8821C BIT(29) +#define BIT_MCU_ERR_8821C BIT(28) +#define BIT_BCNDMAINT7_8821C BIT(27) +#define BIT_BCNDMAINT6_8821C BIT(26) +#define BIT_BCNDMAINT5_8821C BIT(25) +#define BIT_BCNDMAINT4_8821C BIT(24) +#define BIT_BCNDMAINT3_8821C BIT(23) +#define BIT_BCNDMAINT2_8821C BIT(22) +#define BIT_BCNDMAINT1_8821C BIT(21) +#define BIT_BCNDERR7_8821C BIT(20) +#define BIT_BCNDERR6_8821C BIT(19) +#define BIT_BCNDERR5_8821C BIT(18) +#define BIT_BCNDERR4_8821C BIT(17) +#define BIT_BCNDERR3_8821C BIT(16) +#define BIT_BCNDERR2_8821C BIT(15) +#define BIT_BCNDERR1_8821C BIT(14) +#define BIT_ATIMEND_E_8821C BIT(13) +#define BIT_ATIMEND_8821C BIT(12) +#define BIT_TXERR_INT_8821C BIT(11) +#define BIT_RXERR_INT_8821C BIT(10) +#define BIT_TXFOVW_8821C BIT(9) +#define BIT_FOVW_8821C BIT(8) + +/* 2 REG_NOT_VALID_8821C */ +#define BIT_CPU_MGQ_TXDONE_8821C BIT(5) +#define BIT_PS_TIMER_C_8821C BIT(4) +#define BIT_PS_TIMER_B_8821C BIT(3) +#define BIT_PS_TIMER_A_8821C BIT(2) +#define BIT_CPUMGQ_TX_TIMER_8821C BIT(1) + +/* 2 REG_DBG_PORT_SEL_8821C */ + +#define BIT_SHIFT_DEBUG_ST_8821C 0 +#define BIT_MASK_DEBUG_ST_8821C 0xffffffffL +#define BIT_DEBUG_ST_8821C(x) (((x) & BIT_MASK_DEBUG_ST_8821C) << BIT_SHIFT_DEBUG_ST_8821C) +#define BIT_GET_DEBUG_ST_8821C(x) (((x) >> BIT_SHIFT_DEBUG_ST_8821C) & BIT_MASK_DEBUG_ST_8821C) + +/* 2 REG_PAD_CTRL2_8821C */ +#define BIT_USB3_USB2_TRANSITION_8821C BIT(20) + +#define BIT_SHIFT_USB23_SW_MODE_V1_8821C 18 +#define BIT_MASK_USB23_SW_MODE_V1_8821C 0x3 +#define BIT_USB23_SW_MODE_V1_8821C(x) (((x) & BIT_MASK_USB23_SW_MODE_V1_8821C) << BIT_SHIFT_USB23_SW_MODE_V1_8821C) +#define BIT_GET_USB23_SW_MODE_V1_8821C(x) (((x) >> BIT_SHIFT_USB23_SW_MODE_V1_8821C) & BIT_MASK_USB23_SW_MODE_V1_8821C) + +#define BIT_NO_PDN_CHIPOFF_V1_8821C BIT(17) +#define BIT_RSM_EN_V1_8821C BIT(16) + +#define BIT_SHIFT_MATCH_CNT_8821C 8 +#define BIT_MASK_MATCH_CNT_8821C 0xff +#define BIT_MATCH_CNT_8821C(x) (((x) & BIT_MASK_MATCH_CNT_8821C) << BIT_SHIFT_MATCH_CNT_8821C) +#define BIT_GET_MATCH_CNT_8821C(x) (((x) >> BIT_SHIFT_MATCH_CNT_8821C) & BIT_MASK_MATCH_CNT_8821C) + +#define BIT_LD_B12V_EN_8821C BIT(7) +#define BIT_EECS_IOSEL_V1_8821C BIT(6) +#define BIT_EECS_DATA_O_V1_8821C BIT(5) +#define BIT_EECS_DATA_I_V1_8821C BIT(4) +#define BIT_EESK_IOSEL_V1_8821C BIT(2) +#define BIT_EESK_DATA_O_V1_8821C BIT(1) +#define BIT_EESK_DATA_I_V1_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_PMC_DBG_CTRL2_8821C */ + +#define BIT_SHIFT_EFUSE_BURN_GNT_8821C 24 +#define BIT_MASK_EFUSE_BURN_GNT_8821C 0xff +#define BIT_EFUSE_BURN_GNT_8821C(x) (((x) & BIT_MASK_EFUSE_BURN_GNT_8821C) << BIT_SHIFT_EFUSE_BURN_GNT_8821C) +#define BIT_GET_EFUSE_BURN_GNT_8821C(x) (((x) >> BIT_SHIFT_EFUSE_BURN_GNT_8821C) & BIT_MASK_EFUSE_BURN_GNT_8821C) + +#define BIT_STOP_WL_PMC_8821C BIT(9) +#define BIT_STOP_SYM_PMC_8821C BIT(8) +#define BIT_BT_ACCESS_WL_PAGE0_8821C BIT(6) +#define BIT_REG_RST_WLPMC_8821C BIT(5) +#define BIT_REG_RST_PD12N_8821C BIT(4) +#define BIT_SYSON_DIS_WLREG_WRMSK_8821C BIT(3) +#define BIT_SYSON_DIS_PMCREG_WRMSK_8821C BIT(2) + +#define BIT_SHIFT_SYSON_REG_ARB_8821C 0 +#define BIT_MASK_SYSON_REG_ARB_8821C 0x3 +#define BIT_SYSON_REG_ARB_8821C(x) (((x) & BIT_MASK_SYSON_REG_ARB_8821C) << BIT_SHIFT_SYSON_REG_ARB_8821C) +#define BIT_GET_SYSON_REG_ARB_8821C(x) (((x) >> BIT_SHIFT_SYSON_REG_ARB_8821C) & BIT_MASK_SYSON_REG_ARB_8821C) + +/* 2 REG_BIST_CTRL_8821C */ +#define BIT_BIST_USB_DIS_8821C BIT(27) +#define BIT_BIST_PCI_DIS_8821C BIT(26) +#define BIT_BIST_BT_DIS_8821C BIT(25) +#define BIT_BIST_WL_DIS_8821C BIT(24) + +#define BIT_SHIFT_BIST_RPT_SEL_8821C 16 +#define BIT_MASK_BIST_RPT_SEL_8821C 0xf +#define BIT_BIST_RPT_SEL_8821C(x) (((x) & BIT_MASK_BIST_RPT_SEL_8821C) << BIT_SHIFT_BIST_RPT_SEL_8821C) +#define BIT_GET_BIST_RPT_SEL_8821C(x) (((x) >> BIT_SHIFT_BIST_RPT_SEL_8821C) & BIT_MASK_BIST_RPT_SEL_8821C) + +#define BIT_BIST_RESUME_PS_8821C BIT(4) +#define BIT_BIST_RESUME_8821C BIT(3) +#define BIT_BIST_NORMAL_8821C BIT(2) +#define BIT_BIST_RSTN_8821C BIT(1) +#define BIT_BIST_CLK_EN_8821C BIT(0) + +/* 2 REG_BIST_RPT_8821C */ + +#define BIT_SHIFT_MBIST_REPORT_8821C 0 +#define BIT_MASK_MBIST_REPORT_8821C 0xffffffffL +#define BIT_MBIST_REPORT_8821C(x) (((x) & BIT_MASK_MBIST_REPORT_8821C) << BIT_SHIFT_MBIST_REPORT_8821C) +#define BIT_GET_MBIST_REPORT_8821C(x) (((x) >> BIT_SHIFT_MBIST_REPORT_8821C) & BIT_MASK_MBIST_REPORT_8821C) + +/* 2 REG_MEM_CTRL_8821C */ +#define BIT_UMEM_RME_8821C BIT(31) + +#define BIT_SHIFT_BT_SPRAM_8821C 28 +#define BIT_MASK_BT_SPRAM_8821C 0x3 +#define BIT_BT_SPRAM_8821C(x) (((x) & BIT_MASK_BT_SPRAM_8821C) << BIT_SHIFT_BT_SPRAM_8821C) +#define BIT_GET_BT_SPRAM_8821C(x) (((x) >> BIT_SHIFT_BT_SPRAM_8821C) & BIT_MASK_BT_SPRAM_8821C) + +#define BIT_SHIFT_BT_ROM_8821C 24 +#define BIT_MASK_BT_ROM_8821C 0xf +#define BIT_BT_ROM_8821C(x) (((x) & BIT_MASK_BT_ROM_8821C) << BIT_SHIFT_BT_ROM_8821C) +#define BIT_GET_BT_ROM_8821C(x) (((x) >> BIT_SHIFT_BT_ROM_8821C) & BIT_MASK_BT_ROM_8821C) + +#define BIT_SHIFT_PCI_DPRAM_8821C 10 +#define BIT_MASK_PCI_DPRAM_8821C 0x3 +#define BIT_PCI_DPRAM_8821C(x) (((x) & BIT_MASK_PCI_DPRAM_8821C) << BIT_SHIFT_PCI_DPRAM_8821C) +#define BIT_GET_PCI_DPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_DPRAM_8821C) & BIT_MASK_PCI_DPRAM_8821C) + +#define BIT_SHIFT_PCI_SPRAM_8821C 8 +#define BIT_MASK_PCI_SPRAM_8821C 0x3 +#define BIT_PCI_SPRAM_8821C(x) (((x) & BIT_MASK_PCI_SPRAM_8821C) << BIT_SHIFT_PCI_SPRAM_8821C) +#define BIT_GET_PCI_SPRAM_8821C(x) (((x) >> BIT_SHIFT_PCI_SPRAM_8821C) & BIT_MASK_PCI_SPRAM_8821C) + +#define BIT_SHIFT_USB_SPRAM_8821C 6 +#define BIT_MASK_USB_SPRAM_8821C 0x3 +#define BIT_USB_SPRAM_8821C(x) (((x) & BIT_MASK_USB_SPRAM_8821C) << BIT_SHIFT_USB_SPRAM_8821C) +#define BIT_GET_USB_SPRAM_8821C(x) (((x) >> BIT_SHIFT_USB_SPRAM_8821C) & BIT_MASK_USB_SPRAM_8821C) + +#define BIT_SHIFT_USB_SPRF_8821C 4 +#define BIT_MASK_USB_SPRF_8821C 0x3 +#define BIT_USB_SPRF_8821C(x) (((x) & BIT_MASK_USB_SPRF_8821C) << BIT_SHIFT_USB_SPRF_8821C) +#define BIT_GET_USB_SPRF_8821C(x) (((x) >> BIT_SHIFT_USB_SPRF_8821C) & BIT_MASK_USB_SPRF_8821C) + +#define BIT_SHIFT_MCU_ROM_8821C 0 +#define BIT_MASK_MCU_ROM_8821C 0xf +#define BIT_MCU_ROM_8821C(x) (((x) & BIT_MASK_MCU_ROM_8821C) << BIT_SHIFT_MCU_ROM_8821C) +#define BIT_GET_MCU_ROM_8821C(x) (((x) >> BIT_SHIFT_MCU_ROM_8821C) & BIT_MASK_MCU_ROM_8821C) + +/* 2 REG_AFE_CTRL8_8821C */ +#define BIT_SYN_AGPIO_8821C BIT(20) +#define BIT_XTAL_LP_8821C BIT(4) +#define BIT_XTAL_GM_SEP_8821C BIT(3) + +#define BIT_SHIFT_XTAL_SEL_TOK_8821C 0 +#define BIT_MASK_XTAL_SEL_TOK_8821C 0x7 +#define BIT_XTAL_SEL_TOK_8821C(x) (((x) & BIT_MASK_XTAL_SEL_TOK_8821C) << BIT_SHIFT_XTAL_SEL_TOK_8821C) +#define BIT_GET_XTAL_SEL_TOK_8821C(x) (((x) >> BIT_SHIFT_XTAL_SEL_TOK_8821C) & BIT_MASK_XTAL_SEL_TOK_8821C) + +/* 2 REG_USB_SIE_INTF_8821C */ +#define BIT_RD_SEL_8821C BIT(31) +#define BIT_USB_SIE_INTF_WE_V1_8821C BIT(30) +#define BIT_USB_SIE_INTF_BYIOREG_V1_8821C BIT(29) +#define BIT_USB_SIE_SELECT_8821C BIT(28) + +#define BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C 16 +#define BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C 0x1ff +#define BIT_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) << BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) +#define BIT_GET_USB_SIE_INTF_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1_8821C) & BIT_MASK_USB_SIE_INTF_ADDR_V1_8821C) + +#define BIT_SHIFT_USB_SIE_INTF_RD_8821C 8 +#define BIT_MASK_USB_SIE_INTF_RD_8821C 0xff +#define BIT_USB_SIE_INTF_RD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_RD_8821C) << BIT_SHIFT_USB_SIE_INTF_RD_8821C) +#define BIT_GET_USB_SIE_INTF_RD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_RD_8821C) & BIT_MASK_USB_SIE_INTF_RD_8821C) + +#define BIT_SHIFT_USB_SIE_INTF_WD_8821C 0 +#define BIT_MASK_USB_SIE_INTF_WD_8821C 0xff +#define BIT_USB_SIE_INTF_WD_8821C(x) (((x) & BIT_MASK_USB_SIE_INTF_WD_8821C) << BIT_SHIFT_USB_SIE_INTF_WD_8821C) +#define BIT_GET_USB_SIE_INTF_WD_8821C(x) (((x) >> BIT_SHIFT_USB_SIE_INTF_WD_8821C) & BIT_MASK_USB_SIE_INTF_WD_8821C) + +/* 2 REG_PCIE_MIO_INTF_8821C */ +#define BIT_PCIE_MIO_BYIOREG_8821C BIT(13) +#define BIT_PCIE_MIO_RE_8821C BIT(12) + +#define BIT_SHIFT_PCIE_MIO_WE_8821C 8 +#define BIT_MASK_PCIE_MIO_WE_8821C 0xf +#define BIT_PCIE_MIO_WE_8821C(x) (((x) & BIT_MASK_PCIE_MIO_WE_8821C) << BIT_SHIFT_PCIE_MIO_WE_8821C) +#define BIT_GET_PCIE_MIO_WE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_WE_8821C) & BIT_MASK_PCIE_MIO_WE_8821C) + +#define BIT_SHIFT_PCIE_MIO_ADDR_8821C 0 +#define BIT_MASK_PCIE_MIO_ADDR_8821C 0xff +#define BIT_PCIE_MIO_ADDR_8821C(x) (((x) & BIT_MASK_PCIE_MIO_ADDR_8821C) << BIT_SHIFT_PCIE_MIO_ADDR_8821C) +#define BIT_GET_PCIE_MIO_ADDR_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_ADDR_8821C) & BIT_MASK_PCIE_MIO_ADDR_8821C) + +/* 2 REG_PCIE_MIO_INTD_8821C */ + +#define BIT_SHIFT_PCIE_MIO_DATA_8821C 0 +#define BIT_MASK_PCIE_MIO_DATA_8821C 0xffffffffL +#define BIT_PCIE_MIO_DATA_8821C(x) (((x) & BIT_MASK_PCIE_MIO_DATA_8821C) << BIT_SHIFT_PCIE_MIO_DATA_8821C) +#define BIT_GET_PCIE_MIO_DATA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MIO_DATA_8821C) & BIT_MASK_PCIE_MIO_DATA_8821C) + +/* 2 REG_WLRF1_8821C */ + +#define BIT_SHIFT_WLRF1_CTRL_8821C 24 +#define BIT_MASK_WLRF1_CTRL_8821C 0xff +#define BIT_WLRF1_CTRL_8821C(x) (((x) & BIT_MASK_WLRF1_CTRL_8821C) << BIT_SHIFT_WLRF1_CTRL_8821C) +#define BIT_GET_WLRF1_CTRL_8821C(x) (((x) >> BIT_SHIFT_WLRF1_CTRL_8821C) & BIT_MASK_WLRF1_CTRL_8821C) + +/* 2 REG_SYS_CFG1_8821C */ + +#define BIT_SHIFT_TRP_ICFG_8821C 28 +#define BIT_MASK_TRP_ICFG_8821C 0xf +#define BIT_TRP_ICFG_8821C(x) (((x) & BIT_MASK_TRP_ICFG_8821C) << BIT_SHIFT_TRP_ICFG_8821C) +#define BIT_GET_TRP_ICFG_8821C(x) (((x) >> BIT_SHIFT_TRP_ICFG_8821C) & BIT_MASK_TRP_ICFG_8821C) + +#define BIT_RF_TYPE_ID_8821C BIT(27) +#define BIT_BD_HCI_SEL_8821C BIT(26) +#define BIT_BD_PKG_SEL_8821C BIT(25) +#define BIT_SPSLDO_SEL_8821C BIT(24) +#define BIT_RTL_ID_8821C BIT(23) +#define BIT_PAD_HWPD_IDN_8821C BIT(22) +#define BIT_TESTMODE_8821C BIT(20) + +#define BIT_SHIFT_VENDOR_ID_8821C 16 +#define BIT_MASK_VENDOR_ID_8821C 0xf +#define BIT_VENDOR_ID_8821C(x) (((x) & BIT_MASK_VENDOR_ID_8821C) << BIT_SHIFT_VENDOR_ID_8821C) +#define BIT_GET_VENDOR_ID_8821C(x) (((x) >> BIT_SHIFT_VENDOR_ID_8821C) & BIT_MASK_VENDOR_ID_8821C) + +#define BIT_SHIFT_CHIP_VER_8821C 12 +#define BIT_MASK_CHIP_VER_8821C 0xf +#define BIT_CHIP_VER_8821C(x) (((x) & BIT_MASK_CHIP_VER_8821C) << BIT_SHIFT_CHIP_VER_8821C) +#define BIT_GET_CHIP_VER_8821C(x) (((x) >> BIT_SHIFT_CHIP_VER_8821C) & BIT_MASK_CHIP_VER_8821C) + +#define BIT_BD_MAC3_8821C BIT(11) +#define BIT_BD_MAC1_8821C BIT(10) +#define BIT_BD_MAC2_8821C BIT(9) +#define BIT_SIC_IDLE_8821C BIT(8) +#define BIT_SW_OFFLOAD_EN_8821C BIT(7) +#define BIT_OCP_SHUTDN_8821C BIT(6) +#define BIT_V15_VLD_8821C BIT(5) +#define BIT_PCIRSTB_8821C BIT(4) +#define BIT_PCLK_VLD_8821C BIT(3) +#define BIT_UCLK_VLD_8821C BIT(2) +#define BIT_ACLK_VLD_8821C BIT(1) +#define BIT_XCLK_VLD_8821C BIT(0) + +/* 2 REG_SYS_STATUS1_8821C */ + +#define BIT_SHIFT_RF_RL_ID_8821C 28 +#define BIT_MASK_RF_RL_ID_8821C 0xf +#define BIT_RF_RL_ID_8821C(x) (((x) & BIT_MASK_RF_RL_ID_8821C) << BIT_SHIFT_RF_RL_ID_8821C) +#define BIT_GET_RF_RL_ID_8821C(x) (((x) >> BIT_SHIFT_RF_RL_ID_8821C) & BIT_MASK_RF_RL_ID_8821C) + +#define BIT_HPHY_ICFG_8821C BIT(19) + +#define BIT_SHIFT_SEL_0XC0_8821C 16 +#define BIT_MASK_SEL_0XC0_8821C 0x3 +#define BIT_SEL_0XC0_8821C(x) (((x) & BIT_MASK_SEL_0XC0_8821C) << BIT_SHIFT_SEL_0XC0_8821C) +#define BIT_GET_SEL_0XC0_8821C(x) (((x) >> BIT_SHIFT_SEL_0XC0_8821C) & BIT_MASK_SEL_0XC0_8821C) + +#define BIT_USB_OPERATION_MODE_8821C BIT(10) +#define BIT_BT_PDN_8821C BIT(9) +#define BIT_AUTO_WLPON_8821C BIT(8) +#define BIT_WL_MODE_8821C BIT(7) +#define BIT_PKG_SEL_HCI_8821C BIT(6) + +#define BIT_SHIFT_HCI_SEL_8821C 4 +#define BIT_MASK_HCI_SEL_8821C 0x3 +#define BIT_HCI_SEL_8821C(x) (((x) & BIT_MASK_HCI_SEL_8821C) << BIT_SHIFT_HCI_SEL_8821C) +#define BIT_GET_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_HCI_SEL_8821C) & BIT_MASK_HCI_SEL_8821C) + +#define BIT_SHIFT_PAD_HCI_SEL_8821C 2 +#define BIT_MASK_PAD_HCI_SEL_8821C 0x3 +#define BIT_PAD_HCI_SEL_8821C(x) (((x) & BIT_MASK_PAD_HCI_SEL_8821C) << BIT_SHIFT_PAD_HCI_SEL_8821C) +#define BIT_GET_PAD_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_PAD_HCI_SEL_8821C) & BIT_MASK_PAD_HCI_SEL_8821C) + +#define BIT_SHIFT_EFS_HCI_SEL_8821C 0 +#define BIT_MASK_EFS_HCI_SEL_8821C 0x3 +#define BIT_EFS_HCI_SEL_8821C(x) (((x) & BIT_MASK_EFS_HCI_SEL_8821C) << BIT_SHIFT_EFS_HCI_SEL_8821C) +#define BIT_GET_EFS_HCI_SEL_8821C(x) (((x) >> BIT_SHIFT_EFS_HCI_SEL_8821C) & BIT_MASK_EFS_HCI_SEL_8821C) + +/* 2 REG_SYS_STATUS2_8821C */ +#define BIT_SIO_ALDN_8821C BIT(19) +#define BIT_USB_ALDN_8821C BIT(18) +#define BIT_PCI_ALDN_8821C BIT(17) +#define BIT_SYS_ALDN_8821C BIT(16) + +#define BIT_SHIFT_EPVID1_8821C 8 +#define BIT_MASK_EPVID1_8821C 0xff +#define BIT_EPVID1_8821C(x) (((x) & BIT_MASK_EPVID1_8821C) << BIT_SHIFT_EPVID1_8821C) +#define BIT_GET_EPVID1_8821C(x) (((x) >> BIT_SHIFT_EPVID1_8821C) & BIT_MASK_EPVID1_8821C) + +#define BIT_SHIFT_EPVID0_8821C 0 +#define BIT_MASK_EPVID0_8821C 0xff +#define BIT_EPVID0_8821C(x) (((x) & BIT_MASK_EPVID0_8821C) << BIT_SHIFT_EPVID0_8821C) +#define BIT_GET_EPVID0_8821C(x) (((x) >> BIT_SHIFT_EPVID0_8821C) & BIT_MASK_EPVID0_8821C) + +/* 2 REG_SYS_CFG2_8821C */ +#define BIT_HCI_SEL_EMBEDED_8821C BIT(8) + +#define BIT_SHIFT_HW_ID_8821C 0 +#define BIT_MASK_HW_ID_8821C 0xff +#define BIT_HW_ID_8821C(x) (((x) & BIT_MASK_HW_ID_8821C) << BIT_SHIFT_HW_ID_8821C) +#define BIT_GET_HW_ID_8821C(x) (((x) >> BIT_SHIFT_HW_ID_8821C) & BIT_MASK_HW_ID_8821C) + +/* 2 REG_SYS_CFG3_8821C */ +#define BIT_PWC_MA33V_8821C BIT(15) +#define BIT_PWC_MA12V_8821C BIT(14) +#define BIT_PWC_MD12V_8821C BIT(13) +#define BIT_PWC_PD12V_8821C BIT(12) +#define BIT_PWC_UD12V_8821C BIT(11) +#define BIT_ISO_MA2MD_8821C BIT(1) +#define BIT_ISO_MD2PP_8821C BIT(0) + +/* 2 REG_SYS_CFG4_8821C */ + +/* 2 REG_SYS_CFG5_8821C */ +#define BIT_LPS_STATUS_8821C BIT(3) +#define BIT_HCI_TXDMA_BUSY_8821C BIT(2) +#define BIT_HCI_TXDMA_ALLOW_8821C BIT(1) +#define BIT_FW_CTRL_HCI_TXDMA_EN_8821C BIT(0) + +/* 2 REG_CPU_DMEM_CON_8821C */ +#define BIT_WDT_AUTO_MODE_8821C BIT(22) +#define BIT_WDT_PLATFORM_EN_8821C BIT(21) +#define BIT_WDT_CPU_EN_8821C BIT(20) +#define BIT_WDT_OPT_IOWRAPPER_8821C BIT(19) +#define BIT_ANA_PORT_IDLE_8821C BIT(18) +#define BIT_MAC_PORT_IDLE_8821C BIT(17) +#define BIT_WL_PLATFORM_RST_8821C BIT(16) +#define BIT_WL_SECURITY_CLK_8821C BIT(15) + +#define BIT_SHIFT_CPU_DMEM_CON_8821C 0 +#define BIT_MASK_CPU_DMEM_CON_8821C 0xff +#define BIT_CPU_DMEM_CON_8821C(x) (((x) & BIT_MASK_CPU_DMEM_CON_8821C) << BIT_SHIFT_CPU_DMEM_CON_8821C) +#define BIT_GET_CPU_DMEM_CON_8821C(x) (((x) >> BIT_SHIFT_CPU_DMEM_CON_8821C) & BIT_MASK_CPU_DMEM_CON_8821C) + +/* 2 REG_BOOT_REASON_8821C */ + +#define BIT_SHIFT_BOOT_REASON_8821C 0 +#define BIT_MASK_BOOT_REASON_8821C 0x7 +#define BIT_BOOT_REASON_8821C(x) (((x) & BIT_MASK_BOOT_REASON_8821C) << BIT_SHIFT_BOOT_REASON_8821C) +#define BIT_GET_BOOT_REASON_8821C(x) (((x) >> BIT_SHIFT_BOOT_REASON_8821C) & BIT_MASK_BOOT_REASON_8821C) + +/* 2 REG_NFCPAD_CTRL_8821C */ +#define BIT_PAD_SHUTDW_8821C BIT(18) +#define BIT_SYSON_NFC_PAD_8821C BIT(17) +#define BIT_NFC_INT_PAD_CTRL_8821C BIT(16) +#define BIT_NFC_RFDIS_PAD_CTRL_8821C BIT(15) +#define BIT_NFC_CLK_PAD_CTRL_8821C BIT(14) +#define BIT_NFC_DATA_PAD_CTRL_8821C BIT(13) +#define BIT_NFC_PAD_PULL_CTRL_8821C BIT(12) + +#define BIT_SHIFT_NFCPAD_IO_SEL_8821C 8 +#define BIT_MASK_NFCPAD_IO_SEL_8821C 0xf +#define BIT_NFCPAD_IO_SEL_8821C(x) (((x) & BIT_MASK_NFCPAD_IO_SEL_8821C) << BIT_SHIFT_NFCPAD_IO_SEL_8821C) +#define BIT_GET_NFCPAD_IO_SEL_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IO_SEL_8821C) & BIT_MASK_NFCPAD_IO_SEL_8821C) + +#define BIT_SHIFT_NFCPAD_OUT_8821C 4 +#define BIT_MASK_NFCPAD_OUT_8821C 0xf +#define BIT_NFCPAD_OUT_8821C(x) (((x) & BIT_MASK_NFCPAD_OUT_8821C) << BIT_SHIFT_NFCPAD_OUT_8821C) +#define BIT_GET_NFCPAD_OUT_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_OUT_8821C) & BIT_MASK_NFCPAD_OUT_8821C) + +#define BIT_SHIFT_NFCPAD_IN_8821C 0 +#define BIT_MASK_NFCPAD_IN_8821C 0xf +#define BIT_NFCPAD_IN_8821C(x) (((x) & BIT_MASK_NFCPAD_IN_8821C) << BIT_SHIFT_NFCPAD_IN_8821C) +#define BIT_GET_NFCPAD_IN_8821C(x) (((x) >> BIT_SHIFT_NFCPAD_IN_8821C) & BIT_MASK_NFCPAD_IN_8821C) + +/* 2 REG_HIMR2_8821C */ +#define BIT_BCNDMAINT_P4_MSK_8821C BIT(31) +#define BIT_BCNDMAINT_P3_MSK_8821C BIT(30) +#define BIT_BCNDMAINT_P2_MSK_8821C BIT(29) +#define BIT_BCNDMAINT_P1_MSK_8821C BIT(28) +#define BIT_ATIMEND7_MSK_8821C BIT(22) +#define BIT_ATIMEND6_MSK_8821C BIT(21) +#define BIT_ATIMEND5_MSK_8821C BIT(20) +#define BIT_ATIMEND4_MSK_8821C BIT(19) +#define BIT_ATIMEND3_MSK_8821C BIT(18) +#define BIT_ATIMEND2_MSK_8821C BIT(17) +#define BIT_ATIMEND1_MSK_8821C BIT(16) +#define BIT_TXBCN7OK_MSK_8821C BIT(14) +#define BIT_TXBCN6OK_MSK_8821C BIT(13) +#define BIT_TXBCN5OK_MSK_8821C BIT(12) +#define BIT_TXBCN4OK_MSK_8821C BIT(11) +#define BIT_TXBCN3OK_MSK_8821C BIT(10) +#define BIT_TXBCN2OK_MSK_8821C BIT(9) +#define BIT_TXBCN1OK_MSK_V1_8821C BIT(8) +#define BIT_TXBCN7ERR_MSK_8821C BIT(6) +#define BIT_TXBCN6ERR_MSK_8821C BIT(5) +#define BIT_TXBCN5ERR_MSK_8821C BIT(4) +#define BIT_TXBCN4ERR_MSK_8821C BIT(3) +#define BIT_TXBCN3ERR_MSK_8821C BIT(2) +#define BIT_TXBCN2ERR_MSK_8821C BIT(1) +#define BIT_TXBCN1ERR_MSK_V1_8821C BIT(0) + +/* 2 REG_HISR2_8821C */ +#define BIT_BCNDMAINT_P4_8821C BIT(31) +#define BIT_BCNDMAINT_P3_8821C BIT(30) +#define BIT_BCNDMAINT_P2_8821C BIT(29) +#define BIT_BCNDMAINT_P1_8821C BIT(28) +#define BIT_ATIMEND7_8821C BIT(22) +#define BIT_ATIMEND6_8821C BIT(21) +#define BIT_ATIMEND5_8821C BIT(20) +#define BIT_ATIMEND4_8821C BIT(19) +#define BIT_ATIMEND3_8821C BIT(18) +#define BIT_ATIMEND2_8821C BIT(17) +#define BIT_ATIMEND1_8821C BIT(16) +#define BIT_TXBCN7OK_8821C BIT(14) +#define BIT_TXBCN6OK_8821C BIT(13) +#define BIT_TXBCN5OK_8821C BIT(12) +#define BIT_TXBCN4OK_8821C BIT(11) +#define BIT_TXBCN3OK_8821C BIT(10) +#define BIT_TXBCN2OK_8821C BIT(9) +#define BIT_TXBCN1OK_8821C BIT(8) +#define BIT_TXBCN7ERR_8821C BIT(6) +#define BIT_TXBCN6ERR_8821C BIT(5) +#define BIT_TXBCN5ERR_8821C BIT(4) +#define BIT_TXBCN4ERR_8821C BIT(3) +#define BIT_TXBCN3ERR_8821C BIT(2) +#define BIT_TXBCN2ERR_8821C BIT(1) +#define BIT_TXBCN1ERR_8821C BIT(0) + +/* 2 REG_HIMR3_8821C */ +#define BIT_WDT_PLATFORM_INT_MSK_8821C BIT(18) +#define BIT_WDT_CPU_INT_MSK_8821C BIT(17) +#define BIT_SETH2CDOK_MASK_8821C BIT(16) +#define BIT_H2C_CMD_FULL_MASK_8821C BIT(15) +#define BIT_PWR_INT_127_MASK_8821C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK_8821C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_MASK_8821C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_MASK_8821C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_MAS_8821C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_MASK_8821C BIT(9) +#define BIT_PWR_INT_127_MASK_V1_8821C BIT(8) +#define BIT_PWR_INT_126TO96_MASK_8821C BIT(7) +#define BIT_PWR_INT_95TO64_MASK_8821C BIT(6) +#define BIT_PWR_INT_63TO32_MASK_8821C BIT(5) +#define BIT_PWR_INT_31TO0_MASK_8821C BIT(4) +#define BIT_DDMA0_LP_INT_MSK_8821C BIT(1) +#define BIT_DDMA0_HP_INT_MSK_8821C BIT(0) + +/* 2 REG_HISR3_8821C */ +#define BIT_WDT_PLATFORM_INT_8821C BIT(18) +#define BIT_WDT_CPU_INT_8821C BIT(17) +#define BIT_SETH2CDOK_8821C BIT(16) +#define BIT_H2C_CMD_FULL_8821C BIT(15) +#define BIT_PWR_INT_127_8821C BIT(14) +#define BIT_TXSHORTCUT_TXDESUPDATEOK_8821C BIT(13) +#define BIT_TXSHORTCUT_BKUPDATEOK_8821C BIT(12) +#define BIT_TXSHORTCUT_BEUPDATEOK_8821C BIT(11) +#define BIT_TXSHORTCUT_VIUPDATEOK_8821C BIT(10) +#define BIT_TXSHORTCUT_VOUPDATEOK_8821C BIT(9) +#define BIT_PWR_INT_127_V1_8821C BIT(8) +#define BIT_PWR_INT_126TO96_8821C BIT(7) +#define BIT_PWR_INT_95TO64_8821C BIT(6) +#define BIT_PWR_INT_63TO32_8821C BIT(5) +#define BIT_PWR_INT_31TO0_8821C BIT(4) +#define BIT_DDMA0_LP_INT_8821C BIT(1) +#define BIT_DDMA0_HP_INT_8821C BIT(0) + +/* 2 REG_SW_MDIO_8821C */ +#define BIT_DIS_TIMEOUT_IO_8821C BIT(24) + +/* 2 REG_SW_FLUSH_8821C */ +#define BIT_FLUSH_HOLDN_EN_8821C BIT(25) +#define BIT_FLUSH_WR_EN_8821C BIT(24) +#define BIT_SW_FLASH_CONTROL_8821C BIT(23) +#define BIT_SW_FLASH_WEN_E_8821C BIT(19) +#define BIT_SW_FLASH_HOLDN_E_8821C BIT(18) +#define BIT_SW_FLASH_SO_E_8821C BIT(17) +#define BIT_SW_FLASH_SI_E_8821C BIT(16) +#define BIT_SW_FLASH_SK_O_8821C BIT(13) +#define BIT_SW_FLASH_CEN_O_8821C BIT(12) +#define BIT_SW_FLASH_WEN_O_8821C BIT(11) +#define BIT_SW_FLASH_HOLDN_O_8821C BIT(10) +#define BIT_SW_FLASH_SO_O_8821C BIT(9) +#define BIT_SW_FLASH_SI_O_8821C BIT(8) +#define BIT_SW_FLASH_WEN_I_8821C BIT(3) +#define BIT_SW_FLASH_HOLDN_I_8821C BIT(2) +#define BIT_SW_FLASH_SO_I_8821C BIT(1) +#define BIT_SW_FLASH_SI_I_8821C BIT(0) + +/* 2 REG_H2C_PKT_READADDR_8821C */ + +#define BIT_SHIFT_H2C_PKT_READADDR_8821C 0 +#define BIT_MASK_H2C_PKT_READADDR_8821C 0x3ffff +#define BIT_H2C_PKT_READADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_READADDR_8821C) << BIT_SHIFT_H2C_PKT_READADDR_8821C) +#define BIT_GET_H2C_PKT_READADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_READADDR_8821C) & BIT_MASK_H2C_PKT_READADDR_8821C) + +/* 2 REG_H2C_PKT_WRITEADDR_8821C */ + +#define BIT_SHIFT_H2C_PKT_WRITEADDR_8821C 0 +#define BIT_MASK_H2C_PKT_WRITEADDR_8821C 0x3ffff +#define BIT_H2C_PKT_WRITEADDR_8821C(x) (((x) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) << BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) +#define BIT_GET_H2C_PKT_WRITEADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR_8821C) & BIT_MASK_H2C_PKT_WRITEADDR_8821C) + +/* 2 REG_MEM_PWR_CRTL_8821C */ +#define BIT_MEM_BB_SD_8821C BIT(17) +#define BIT_MEM_BB_DS_8821C BIT(16) +#define BIT_MEM_BT_DS_8821C BIT(10) +#define BIT_MEM_SDIO_LS_8821C BIT(9) +#define BIT_MEM_SDIO_DS_8821C BIT(8) +#define BIT_MEM_USB_LS_8821C BIT(7) +#define BIT_MEM_USB_DS_8821C BIT(6) +#define BIT_MEM_PCI_LS_8821C BIT(5) +#define BIT_MEM_PCI_DS_8821C BIT(4) +#define BIT_MEM_WLMAC_LS_8821C BIT(3) +#define BIT_MEM_WLMAC_DS_8821C BIT(2) +#define BIT_MEM_WLMCU_LS_8821C BIT(1) +#define BIT_MEM_WLMCU_DS_8821C BIT(0) + +/* 2 REG_FW_DBG0_8821C */ + +#define BIT_SHIFT_FW_DBG0_8821C 0 +#define BIT_MASK_FW_DBG0_8821C 0xffffffffL +#define BIT_FW_DBG0_8821C(x) (((x) & BIT_MASK_FW_DBG0_8821C) << BIT_SHIFT_FW_DBG0_8821C) +#define BIT_GET_FW_DBG0_8821C(x) (((x) >> BIT_SHIFT_FW_DBG0_8821C) & BIT_MASK_FW_DBG0_8821C) + +/* 2 REG_FW_DBG1_8821C */ + +#define BIT_SHIFT_FW_DBG1_8821C 0 +#define BIT_MASK_FW_DBG1_8821C 0xffffffffL +#define BIT_FW_DBG1_8821C(x) (((x) & BIT_MASK_FW_DBG1_8821C) << BIT_SHIFT_FW_DBG1_8821C) +#define BIT_GET_FW_DBG1_8821C(x) (((x) >> BIT_SHIFT_FW_DBG1_8821C) & BIT_MASK_FW_DBG1_8821C) + +/* 2 REG_FW_DBG2_8821C */ + +#define BIT_SHIFT_FW_DBG2_8821C 0 +#define BIT_MASK_FW_DBG2_8821C 0xffffffffL +#define BIT_FW_DBG2_8821C(x) (((x) & BIT_MASK_FW_DBG2_8821C) << BIT_SHIFT_FW_DBG2_8821C) +#define BIT_GET_FW_DBG2_8821C(x) (((x) >> BIT_SHIFT_FW_DBG2_8821C) & BIT_MASK_FW_DBG2_8821C) + +/* 2 REG_FW_DBG3_8821C */ + +#define BIT_SHIFT_FW_DBG3_8821C 0 +#define BIT_MASK_FW_DBG3_8821C 0xffffffffL +#define BIT_FW_DBG3_8821C(x) (((x) & BIT_MASK_FW_DBG3_8821C) << BIT_SHIFT_FW_DBG3_8821C) +#define BIT_GET_FW_DBG3_8821C(x) (((x) >> BIT_SHIFT_FW_DBG3_8821C) & BIT_MASK_FW_DBG3_8821C) + +/* 2 REG_FW_DBG4_8821C */ + +#define BIT_SHIFT_FW_DBG4_8821C 0 +#define BIT_MASK_FW_DBG4_8821C 0xffffffffL +#define BIT_FW_DBG4_8821C(x) (((x) & BIT_MASK_FW_DBG4_8821C) << BIT_SHIFT_FW_DBG4_8821C) +#define BIT_GET_FW_DBG4_8821C(x) (((x) >> BIT_SHIFT_FW_DBG4_8821C) & BIT_MASK_FW_DBG4_8821C) + +/* 2 REG_FW_DBG5_8821C */ + +#define BIT_SHIFT_FW_DBG5_8821C 0 +#define BIT_MASK_FW_DBG5_8821C 0xffffffffL +#define BIT_FW_DBG5_8821C(x) (((x) & BIT_MASK_FW_DBG5_8821C) << BIT_SHIFT_FW_DBG5_8821C) +#define BIT_GET_FW_DBG5_8821C(x) (((x) >> BIT_SHIFT_FW_DBG5_8821C) & BIT_MASK_FW_DBG5_8821C) + +/* 2 REG_FW_DBG6_8821C */ + +#define BIT_SHIFT_FW_DBG6_8821C 0 +#define BIT_MASK_FW_DBG6_8821C 0xffffffffL +#define BIT_FW_DBG6_8821C(x) (((x) & BIT_MASK_FW_DBG6_8821C) << BIT_SHIFT_FW_DBG6_8821C) +#define BIT_GET_FW_DBG6_8821C(x) (((x) >> BIT_SHIFT_FW_DBG6_8821C) & BIT_MASK_FW_DBG6_8821C) + +/* 2 REG_FW_DBG7_8821C */ + +#define BIT_SHIFT_FW_DBG7_8821C 0 +#define BIT_MASK_FW_DBG7_8821C 0xffffffffL +#define BIT_FW_DBG7_8821C(x) (((x) & BIT_MASK_FW_DBG7_8821C) << BIT_SHIFT_FW_DBG7_8821C) +#define BIT_GET_FW_DBG7_8821C(x) (((x) >> BIT_SHIFT_FW_DBG7_8821C) & BIT_MASK_FW_DBG7_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_CR_8821C */ + +#define BIT_SHIFT_LBMODE_8821C 24 +#define BIT_MASK_LBMODE_8821C 0x1f +#define BIT_LBMODE_8821C(x) (((x) & BIT_MASK_LBMODE_8821C) << BIT_SHIFT_LBMODE_8821C) +#define BIT_GET_LBMODE_8821C(x) (((x) >> BIT_SHIFT_LBMODE_8821C) & BIT_MASK_LBMODE_8821C) + +#define BIT_SHIFT_NETYPE1_8821C 18 +#define BIT_MASK_NETYPE1_8821C 0x3 +#define BIT_NETYPE1_8821C(x) (((x) & BIT_MASK_NETYPE1_8821C) << BIT_SHIFT_NETYPE1_8821C) +#define BIT_GET_NETYPE1_8821C(x) (((x) >> BIT_SHIFT_NETYPE1_8821C) & BIT_MASK_NETYPE1_8821C) + +#define BIT_SHIFT_NETYPE0_8821C 16 +#define BIT_MASK_NETYPE0_8821C 0x3 +#define BIT_NETYPE0_8821C(x) (((x) & BIT_MASK_NETYPE0_8821C) << BIT_SHIFT_NETYPE0_8821C) +#define BIT_GET_NETYPE0_8821C(x) (((x) >> BIT_SHIFT_NETYPE0_8821C) & BIT_MASK_NETYPE0_8821C) + +#define BIT_I2C_MAILBOX_EN_8821C BIT(12) +#define BIT_SHCUT_EN_8821C BIT(11) +#define BIT_32K_CAL_TMR_EN_8821C BIT(10) +#define BIT_MAC_SEC_EN_8821C BIT(9) +#define BIT_ENSWBCN_8821C BIT(8) +#define BIT_MACRXEN_8821C BIT(7) +#define BIT_MACTXEN_8821C BIT(6) +#define BIT_SCHEDULE_EN_8821C BIT(5) +#define BIT_PROTOCOL_EN_8821C BIT(4) +#define BIT_RXDMA_EN_8821C BIT(3) +#define BIT_TXDMA_EN_8821C BIT(2) +#define BIT_HCI_RXDMA_EN_8821C BIT(1) +#define BIT_HCI_TXDMA_EN_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_PKT_BUFF_ACCESS_CTRL_8821C */ + +#define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C 0 +#define BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C 0xff +#define BIT_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) +#define BIT_GET_PKT_BUFF_ACCESS_CTRL_8821C(x) (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL_8821C) & BIT_MASK_PKT_BUFF_ACCESS_CTRL_8821C) + +/* 2 REG_TSF_CLK_STATE_8821C */ +#define BIT_TSF_CLK_STABLE_8821C BIT(15) + +/* 2 REG_TXDMA_PQ_MAP_8821C */ + +#define BIT_SHIFT_TXDMA_HIQ_MAP_8821C 14 +#define BIT_MASK_TXDMA_HIQ_MAP_8821C 0x3 +#define BIT_TXDMA_HIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_HIQ_MAP_8821C) << BIT_SHIFT_TXDMA_HIQ_MAP_8821C) +#define BIT_GET_TXDMA_HIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP_8821C) & BIT_MASK_TXDMA_HIQ_MAP_8821C) + +#define BIT_SHIFT_TXDMA_MGQ_MAP_8821C 12 +#define BIT_MASK_TXDMA_MGQ_MAP_8821C 0x3 +#define BIT_TXDMA_MGQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_MGQ_MAP_8821C) << BIT_SHIFT_TXDMA_MGQ_MAP_8821C) +#define BIT_GET_TXDMA_MGQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP_8821C) & BIT_MASK_TXDMA_MGQ_MAP_8821C) + +#define BIT_SHIFT_TXDMA_BKQ_MAP_8821C 10 +#define BIT_MASK_TXDMA_BKQ_MAP_8821C 0x3 +#define BIT_TXDMA_BKQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BKQ_MAP_8821C) << BIT_SHIFT_TXDMA_BKQ_MAP_8821C) +#define BIT_GET_TXDMA_BKQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP_8821C) & BIT_MASK_TXDMA_BKQ_MAP_8821C) + +#define BIT_SHIFT_TXDMA_BEQ_MAP_8821C 8 +#define BIT_MASK_TXDMA_BEQ_MAP_8821C 0x3 +#define BIT_TXDMA_BEQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_BEQ_MAP_8821C) << BIT_SHIFT_TXDMA_BEQ_MAP_8821C) +#define BIT_GET_TXDMA_BEQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP_8821C) & BIT_MASK_TXDMA_BEQ_MAP_8821C) + +#define BIT_SHIFT_TXDMA_VIQ_MAP_8821C 6 +#define BIT_MASK_TXDMA_VIQ_MAP_8821C 0x3 +#define BIT_TXDMA_VIQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VIQ_MAP_8821C) << BIT_SHIFT_TXDMA_VIQ_MAP_8821C) +#define BIT_GET_TXDMA_VIQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP_8821C) & BIT_MASK_TXDMA_VIQ_MAP_8821C) + +#define BIT_SHIFT_TXDMA_VOQ_MAP_8821C 4 +#define BIT_MASK_TXDMA_VOQ_MAP_8821C 0x3 +#define BIT_TXDMA_VOQ_MAP_8821C(x) (((x) & BIT_MASK_TXDMA_VOQ_MAP_8821C) << BIT_SHIFT_TXDMA_VOQ_MAP_8821C) +#define BIT_GET_TXDMA_VOQ_MAP_8821C(x) (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP_8821C) & BIT_MASK_TXDMA_VOQ_MAP_8821C) + +#define BIT_RXDMA_AGG_EN_8821C BIT(2) +#define BIT_RXSHFT_EN_8821C BIT(1) +#define BIT_RXDMA_ARBBW_EN_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_TRXFF_BNDY_8821C */ + +#define BIT_SHIFT_RXFFOVFL_RSV_V2_8821C 8 +#define BIT_MASK_RXFFOVFL_RSV_V2_8821C 0xf +#define BIT_RXFFOVFL_RSV_V2_8821C(x) (((x) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) << BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) +#define BIT_GET_RXFFOVFL_RSV_V2_8821C(x) (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2_8821C) & BIT_MASK_RXFFOVFL_RSV_V2_8821C) + +#define BIT_SHIFT_TXPKTBUF_PGBNDY_8821C 0 +#define BIT_MASK_TXPKTBUF_PGBNDY_8821C 0xff +#define BIT_TXPKTBUF_PGBNDY_8821C(x) (((x) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) << BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) +#define BIT_GET_TXPKTBUF_PGBNDY_8821C(x) (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY_8821C) & BIT_MASK_TXPKTBUF_PGBNDY_8821C) + +/* 2 REG_PTA_I2C_MBOX_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_I2C_M_STATUS_8821C 8 +#define BIT_MASK_I2C_M_STATUS_8821C 0xf +#define BIT_I2C_M_STATUS_8821C(x) (((x) & BIT_MASK_I2C_M_STATUS_8821C) << BIT_SHIFT_I2C_M_STATUS_8821C) +#define BIT_GET_I2C_M_STATUS_8821C(x) (((x) >> BIT_SHIFT_I2C_M_STATUS_8821C) & BIT_MASK_I2C_M_STATUS_8821C) + +#define BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C 4 +#define BIT_MASK_I2C_M_BUS_GNT_FW_8821C 0x7 +#define BIT_I2C_M_BUS_GNT_FW_8821C(x) (((x) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) << BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) +#define BIT_GET_I2C_M_BUS_GNT_FW_8821C(x) (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW_8821C) & BIT_MASK_I2C_M_BUS_GNT_FW_8821C) + +#define BIT_I2C_M_GNT_FW_8821C BIT(3) + +#define BIT_SHIFT_I2C_M_SPEED_8821C 1 +#define BIT_MASK_I2C_M_SPEED_8821C 0x3 +#define BIT_I2C_M_SPEED_8821C(x) (((x) & BIT_MASK_I2C_M_SPEED_8821C) << BIT_SHIFT_I2C_M_SPEED_8821C) +#define BIT_GET_I2C_M_SPEED_8821C(x) (((x) >> BIT_SHIFT_I2C_M_SPEED_8821C) & BIT_MASK_I2C_M_SPEED_8821C) + +#define BIT_I2C_M_UNLOCK_8821C BIT(0) + +/* 2 REG_RXFF_BNDY_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_RXFF0_BNDY_V2_8821C 0 +#define BIT_MASK_RXFF0_BNDY_V2_8821C 0x3ffff +#define BIT_RXFF0_BNDY_V2_8821C(x) (((x) & BIT_MASK_RXFF0_BNDY_V2_8821C) << BIT_SHIFT_RXFF0_BNDY_V2_8821C) +#define BIT_GET_RXFF0_BNDY_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_BNDY_V2_8821C) & BIT_MASK_RXFF0_BNDY_V2_8821C) + +/* 2 REG_FE1IMR_8821C */ +#define BIT_FS_RXDMA2_DONE_INT_EN_8821C BIT(28) +#define BIT_FS_RXDONE3_INT_EN_8821C BIT(27) +#define BIT_FS_RXDONE2_INT_EN_8821C BIT(26) +#define BIT_FS_RX_BCN_P4_INT_EN_8821C BIT(25) +#define BIT_FS_RX_BCN_P3_INT_EN_8821C BIT(24) +#define BIT_FS_RX_BCN_P2_INT_EN_8821C BIT(23) +#define BIT_FS_RX_BCN_P1_INT_EN_8821C BIT(22) +#define BIT_FS_RX_BCN_P0_INT_EN_8821C BIT(21) +#define BIT_FS_RX_UMD0_INT_EN_8821C BIT(20) +#define BIT_FS_RX_UMD1_INT_EN_8821C BIT(19) +#define BIT_FS_RX_BMD0_INT_EN_8821C BIT(18) +#define BIT_FS_RX_BMD1_INT_EN_8821C BIT(17) +#define BIT_FS_RXDONE_INT_EN_8821C BIT(16) +#define BIT_FS_WWLAN_INT_EN_8821C BIT(15) +#define BIT_FS_SOUND_DONE_INT_EN_8821C BIT(14) +#define BIT_FS_LP_STBY_INT_EN_8821C BIT(13) +#define BIT_FS_TRL_MTR_INT_EN_8821C BIT(12) +#define BIT_FS_BF1_PRETO_INT_EN_8821C BIT(11) +#define BIT_FS_BF0_PRETO_INT_EN_8821C BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_EN_8821C BIT(9) +#define BIT_FS_LTE_COEX_EN_8821C BIT(6) +#define BIT_FS_WLACTOFF_INT_EN_8821C BIT(5) +#define BIT_FS_WLACTON_INT_EN_8821C BIT(4) +#define BIT_FS_BTCMD_INT_EN_8821C BIT(3) +#define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN_8821C BIT(2) +#define BIT_FS_TRPC_TO_INT_EN_V1_8821C BIT(1) +#define BIT_FS_RPC_O_T_INT_EN_V1_8821C BIT(0) + +/* 2 REG_FE1ISR_8821C */ +#define BIT_FS_RXDMA2_DONE_INT_8821C BIT(28) +#define BIT_FS_RXDONE3_INT_8821C BIT(27) +#define BIT_FS_RXDONE2_INT_8821C BIT(26) +#define BIT_FS_RX_BCN_P4_INT_8821C BIT(25) +#define BIT_FS_RX_BCN_P3_INT_8821C BIT(24) +#define BIT_FS_RX_BCN_P2_INT_8821C BIT(23) +#define BIT_FS_RX_BCN_P1_INT_8821C BIT(22) +#define BIT_FS_RX_BCN_P0_INT_8821C BIT(21) +#define BIT_FS_RX_UMD0_INT_8821C BIT(20) +#define BIT_FS_RX_UMD1_INT_8821C BIT(19) +#define BIT_FS_RX_BMD0_INT_8821C BIT(18) +#define BIT_FS_RX_BMD1_INT_8821C BIT(17) +#define BIT_FS_RXDONE_INT_8821C BIT(16) +#define BIT_FS_WWLAN_INT_8821C BIT(15) +#define BIT_FS_SOUND_DONE_INT_8821C BIT(14) +#define BIT_FS_LP_STBY_INT_8821C BIT(13) +#define BIT_FS_TRL_MTR_INT_8821C BIT(12) +#define BIT_FS_BF1_PRETO_INT_8821C BIT(11) +#define BIT_FS_BF0_PRETO_INT_8821C BIT(10) +#define BIT_FS_PTCL_RELEASE_MACID_INT_8821C BIT(9) +#define BIT_FS_LTE_COEX_INT_8821C BIT(6) +#define BIT_FS_WLACTOFF_INT_8821C BIT(5) +#define BIT_FS_WLACTON_INT_8821C BIT(4) +#define BIT_FS_BCN_RX_INT_INT_8821C BIT(3) +#define BIT_FS_MAILBOX_TO_I2C_INT_8821C BIT(2) +#define BIT_FS_TRPC_TO_INT_8821C BIT(1) +#define BIT_FS_RPC_O_T_INT_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_CPWM_8821C */ +#define BIT_CPWM_TOGGLING_8821C BIT(31) + +#define BIT_SHIFT_CPWM_MOD_8821C 24 +#define BIT_MASK_CPWM_MOD_8821C 0x7f +#define BIT_CPWM_MOD_8821C(x) (((x) & BIT_MASK_CPWM_MOD_8821C) << BIT_SHIFT_CPWM_MOD_8821C) +#define BIT_GET_CPWM_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM_MOD_8821C) & BIT_MASK_CPWM_MOD_8821C) + +/* 2 REG_FWIMR_8821C */ +#define BIT_FS_TXBCNOK_MB7_INT_EN_8821C BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_EN_8821C BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_EN_8821C BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_EN_8821C BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_EN_8821C BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_EN_8821C BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_EN_8821C BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_EN_8821C BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_EN_8821C BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_EN_8821C BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_EN_8821C BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_EN_8821C BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_EN_8821C BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_EN_8821C BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_EN_8821C BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_EN_8821C BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_EN_8821C BIT(15) +#define BIT_SIFS_OVERSPEC_INT_EN_8821C BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN_8821C BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_EN_8821C BIT(12) +#define BIT_FS_DDMA1_LP_INT_EN_8821C BIT(11) +#define BIT_FS_DDMA1_HP_INT_EN_8821C BIT(10) +#define BIT_FS_DDMA0_LP_INT_EN_8821C BIT(9) +#define BIT_FS_DDMA0_HP_INT_EN_8821C BIT(8) +#define BIT_FS_TRXRPT_INT_EN_8821C BIT(7) +#define BIT_FS_C2H_W_READY_INT_EN_8821C BIT(6) +#define BIT_FS_HRCV_INT_EN_8821C BIT(5) +#define BIT_FS_H2CCMD_INT_EN_8821C BIT(4) +#define BIT_FS_TXPKTIN_INT_EN_8821C BIT(3) +#define BIT_FS_ERRORHDL_INT_EN_8821C BIT(2) +#define BIT_FS_TXCCX_INT_EN_8821C BIT(1) +#define BIT_FS_TXCLOSE_INT_EN_8821C BIT(0) + +/* 2 REG_FWISR_8821C */ +#define BIT_FS_TXBCNOK_MB7_INT_8821C BIT(31) +#define BIT_FS_TXBCNOK_MB6_INT_8821C BIT(30) +#define BIT_FS_TXBCNOK_MB5_INT_8821C BIT(29) +#define BIT_FS_TXBCNOK_MB4_INT_8821C BIT(28) +#define BIT_FS_TXBCNOK_MB3_INT_8821C BIT(27) +#define BIT_FS_TXBCNOK_MB2_INT_8821C BIT(26) +#define BIT_FS_TXBCNOK_MB1_INT_8821C BIT(25) +#define BIT_FS_TXBCNOK_MB0_INT_8821C BIT(24) +#define BIT_FS_TXBCNERR_MB7_INT_8821C BIT(23) +#define BIT_FS_TXBCNERR_MB6_INT_8821C BIT(22) +#define BIT_FS_TXBCNERR_MB5_INT_8821C BIT(21) +#define BIT_FS_TXBCNERR_MB4_INT_8821C BIT(20) +#define BIT_FS_TXBCNERR_MB3_INT_8821C BIT(19) +#define BIT_FS_TXBCNERR_MB2_INT_8821C BIT(18) +#define BIT_FS_TXBCNERR_MB1_INT_8821C BIT(17) +#define BIT_FS_TXBCNERR_MB0_INT_8821C BIT(16) +#define BIT_CPU_MGQ_TXDONE_INT_8821C BIT(15) +#define BIT_SIFS_OVERSPEC_INT_8821C BIT(14) +#define BIT_FS_MGNTQ_RPTR_RELEASE_INT_8821C BIT(13) +#define BIT_FS_MGNTQFF_TO_INT_8821C BIT(12) +#define BIT_FS_DDMA1_LP_INT_8821C BIT(11) +#define BIT_FS_DDMA1_HP_INT_8821C BIT(10) +#define BIT_FS_DDMA0_LP_INT_8821C BIT(9) +#define BIT_FS_DDMA0_HP_INT_8821C BIT(8) +#define BIT_FS_TRXRPT_INT_8821C BIT(7) +#define BIT_FS_C2H_W_READY_INT_8821C BIT(6) +#define BIT_FS_HRCV_INT_8821C BIT(5) +#define BIT_FS_H2CCMD_INT_8821C BIT(4) +#define BIT_FS_TXPKTIN_INT_8821C BIT(3) +#define BIT_FS_ERRORHDL_INT_8821C BIT(2) +#define BIT_FS_TXCCX_INT_8821C BIT(1) +#define BIT_FS_TXCLOSE_INT_8821C BIT(0) + +/* 2 REG_FTIMR_8821C */ +#define BIT_PS_TIMER_C_EARLY_INT_EN_8821C BIT(23) +#define BIT_PS_TIMER_B_EARLY_INT_EN_8821C BIT(22) +#define BIT_PS_TIMER_A_EARLY_INT_EN_8821C BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN_8821C BIT(20) +#define BIT_PS_TIMER_C_INT_EN_8821C BIT(19) +#define BIT_PS_TIMER_B_INT_EN_8821C BIT(18) +#define BIT_PS_TIMER_A_INT_EN_8821C BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_EN_8821C BIT(16) +#define BIT_FS_PS_TIMEOUT2_EN_8821C BIT(15) +#define BIT_FS_PS_TIMEOUT1_EN_8821C BIT(14) +#define BIT_FS_PS_TIMEOUT0_EN_8821C BIT(13) +#define BIT_FS_GTINT8_EN_8821C BIT(8) +#define BIT_FS_GTINT7_EN_8821C BIT(7) +#define BIT_FS_GTINT6_EN_8821C BIT(6) +#define BIT_FS_GTINT5_EN_8821C BIT(5) +#define BIT_FS_GTINT4_EN_8821C BIT(4) +#define BIT_FS_GTINT3_EN_8821C BIT(3) +#define BIT_FS_GTINT2_EN_8821C BIT(2) +#define BIT_FS_GTINT1_EN_8821C BIT(1) +#define BIT_FS_GTINT0_EN_8821C BIT(0) + +/* 2 REG_FTISR_8821C */ +#define BIT_PS_TIMER_C_EARLY__INT_8821C BIT(23) +#define BIT_PS_TIMER_B_EARLY__INT_8821C BIT(22) +#define BIT_PS_TIMER_A_EARLY__INT_8821C BIT(21) +#define BIT_CPUMGQ_TX_TIMER_EARLY_INT_8821C BIT(20) +#define BIT_PS_TIMER_C_INT_8821C BIT(19) +#define BIT_PS_TIMER_B_INT_8821C BIT(18) +#define BIT_PS_TIMER_A_INT_8821C BIT(17) +#define BIT_CPUMGQ_TX_TIMER_INT_8821C BIT(16) +#define BIT_FS_PS_TIMEOUT2_INT_8821C BIT(15) +#define BIT_FS_PS_TIMEOUT1_INT_8821C BIT(14) +#define BIT_FS_PS_TIMEOUT0_INT_8821C BIT(13) +#define BIT_FS_GTINT8_INT_8821C BIT(8) +#define BIT_FS_GTINT7_INT_8821C BIT(7) +#define BIT_FS_GTINT6_INT_8821C BIT(6) +#define BIT_FS_GTINT5_INT_8821C BIT(5) +#define BIT_FS_GTINT4_INT_8821C BIT(4) +#define BIT_FS_GTINT3_INT_8821C BIT(3) +#define BIT_FS_GTINT2_INT_8821C BIT(2) +#define BIT_FS_GTINT1_INT_8821C BIT(1) +#define BIT_FS_GTINT0_INT_8821C BIT(0) + +/* 2 REG_PKTBUF_DBG_CTRL_8821C */ + +#define BIT_SHIFT_PKTBUF_WRITE_EN_8821C 24 +#define BIT_MASK_PKTBUF_WRITE_EN_8821C 0xff +#define BIT_PKTBUF_WRITE_EN_8821C(x) (((x) & BIT_MASK_PKTBUF_WRITE_EN_8821C) << BIT_SHIFT_PKTBUF_WRITE_EN_8821C) +#define BIT_GET_PKTBUF_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN_8821C) & BIT_MASK_PKTBUF_WRITE_EN_8821C) + +#define BIT_TXRPTBUF_DBG_8821C BIT(23) + +/* 2 REG_NOT_VALID_8821C */ +#define BIT_TXPKTBUF_DBG_V2_8821C BIT(20) +#define BIT_RXPKTBUF_DBG_8821C BIT(16) + +#define BIT_SHIFT_PKTBUF_DBG_ADDR_8821C 0 +#define BIT_MASK_PKTBUF_DBG_ADDR_8821C 0x1fff +#define BIT_PKTBUF_DBG_ADDR_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) << BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) +#define BIT_GET_PKTBUF_DBG_ADDR_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR_8821C) & BIT_MASK_PKTBUF_DBG_ADDR_8821C) + +/* 2 REG_PKTBUF_DBG_DATA_L_8821C */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C 0 +#define BIT_MASK_PKTBUF_DBG_DATA_L_8821C 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_L_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) +#define BIT_GET_PKTBUF_DBG_DATA_L_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L_8821C) & BIT_MASK_PKTBUF_DBG_DATA_L_8821C) + +/* 2 REG_PKTBUF_DBG_DATA_H_8821C */ + +#define BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C 0 +#define BIT_MASK_PKTBUF_DBG_DATA_H_8821C 0xffffffffL +#define BIT_PKTBUF_DBG_DATA_H_8821C(x) (((x) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) << BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) +#define BIT_GET_PKTBUF_DBG_DATA_H_8821C(x) (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H_8821C) & BIT_MASK_PKTBUF_DBG_DATA_H_8821C) + +/* 2 REG_CPWM2_8821C */ + +#define BIT_SHIFT_L0S_TO_RCVY_NUM_8821C 16 +#define BIT_MASK_L0S_TO_RCVY_NUM_8821C 0xff +#define BIT_L0S_TO_RCVY_NUM_8821C(x) (((x) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) << BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) +#define BIT_GET_L0S_TO_RCVY_NUM_8821C(x) (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM_8821C) & BIT_MASK_L0S_TO_RCVY_NUM_8821C) + +#define BIT_CPWM2_TOGGLING_8821C BIT(15) + +#define BIT_SHIFT_CPWM2_MOD_8821C 0 +#define BIT_MASK_CPWM2_MOD_8821C 0x7fff +#define BIT_CPWM2_MOD_8821C(x) (((x) & BIT_MASK_CPWM2_MOD_8821C) << BIT_SHIFT_CPWM2_MOD_8821C) +#define BIT_GET_CPWM2_MOD_8821C(x) (((x) >> BIT_SHIFT_CPWM2_MOD_8821C) & BIT_MASK_CPWM2_MOD_8821C) + +/* 2 REG_TC0_CTRL_8821C */ +#define BIT_TC0INT_EN_8821C BIT(26) +#define BIT_TC0MODE_8821C BIT(25) +#define BIT_TC0EN_8821C BIT(24) + +#define BIT_SHIFT_TC0DATA_8821C 0 +#define BIT_MASK_TC0DATA_8821C 0xffffff +#define BIT_TC0DATA_8821C(x) (((x) & BIT_MASK_TC0DATA_8821C) << BIT_SHIFT_TC0DATA_8821C) +#define BIT_GET_TC0DATA_8821C(x) (((x) >> BIT_SHIFT_TC0DATA_8821C) & BIT_MASK_TC0DATA_8821C) + +/* 2 REG_TC1_CTRL_8821C */ +#define BIT_TC1INT_EN_8821C BIT(26) +#define BIT_TC1MODE_8821C BIT(25) +#define BIT_TC1EN_8821C BIT(24) + +#define BIT_SHIFT_TC1DATA_8821C 0 +#define BIT_MASK_TC1DATA_8821C 0xffffff +#define BIT_TC1DATA_8821C(x) (((x) & BIT_MASK_TC1DATA_8821C) << BIT_SHIFT_TC1DATA_8821C) +#define BIT_GET_TC1DATA_8821C(x) (((x) >> BIT_SHIFT_TC1DATA_8821C) & BIT_MASK_TC1DATA_8821C) + +/* 2 REG_TC2_CTRL_8821C */ +#define BIT_TC2INT_EN_8821C BIT(26) +#define BIT_TC2MODE_8821C BIT(25) +#define BIT_TC2EN_8821C BIT(24) + +#define BIT_SHIFT_TC2DATA_8821C 0 +#define BIT_MASK_TC2DATA_8821C 0xffffff +#define BIT_TC2DATA_8821C(x) (((x) & BIT_MASK_TC2DATA_8821C) << BIT_SHIFT_TC2DATA_8821C) +#define BIT_GET_TC2DATA_8821C(x) (((x) >> BIT_SHIFT_TC2DATA_8821C) & BIT_MASK_TC2DATA_8821C) + +/* 2 REG_TC3_CTRL_8821C */ +#define BIT_TC3INT_EN_8821C BIT(26) +#define BIT_TC3MODE_8821C BIT(25) +#define BIT_TC3EN_8821C BIT(24) + +#define BIT_SHIFT_TC3DATA_8821C 0 +#define BIT_MASK_TC3DATA_8821C 0xffffff +#define BIT_TC3DATA_8821C(x) (((x) & BIT_MASK_TC3DATA_8821C) << BIT_SHIFT_TC3DATA_8821C) +#define BIT_GET_TC3DATA_8821C(x) (((x) >> BIT_SHIFT_TC3DATA_8821C) & BIT_MASK_TC3DATA_8821C) + +/* 2 REG_TC4_CTRL_8821C */ +#define BIT_TC4INT_EN_8821C BIT(26) +#define BIT_TC4MODE_8821C BIT(25) +#define BIT_TC4EN_8821C BIT(24) + +#define BIT_SHIFT_TC4DATA_8821C 0 +#define BIT_MASK_TC4DATA_8821C 0xffffff +#define BIT_TC4DATA_8821C(x) (((x) & BIT_MASK_TC4DATA_8821C) << BIT_SHIFT_TC4DATA_8821C) +#define BIT_GET_TC4DATA_8821C(x) (((x) >> BIT_SHIFT_TC4DATA_8821C) & BIT_MASK_TC4DATA_8821C) + +/* 2 REG_TCUNIT_BASE_8821C */ + +#define BIT_SHIFT_TCUNIT_BASE_8821C 0 +#define BIT_MASK_TCUNIT_BASE_8821C 0x3fff +#define BIT_TCUNIT_BASE_8821C(x) (((x) & BIT_MASK_TCUNIT_BASE_8821C) << BIT_SHIFT_TCUNIT_BASE_8821C) +#define BIT_GET_TCUNIT_BASE_8821C(x) (((x) >> BIT_SHIFT_TCUNIT_BASE_8821C) & BIT_MASK_TCUNIT_BASE_8821C) + +/* 2 REG_TC5_CTRL_8821C */ +#define BIT_TC5INT_EN_8821C BIT(26) +#define BIT_TC5MODE_8821C BIT(25) +#define BIT_TC5EN_8821C BIT(24) + +#define BIT_SHIFT_TC5DATA_8821C 0 +#define BIT_MASK_TC5DATA_8821C 0xffffff +#define BIT_TC5DATA_8821C(x) (((x) & BIT_MASK_TC5DATA_8821C) << BIT_SHIFT_TC5DATA_8821C) +#define BIT_GET_TC5DATA_8821C(x) (((x) >> BIT_SHIFT_TC5DATA_8821C) & BIT_MASK_TC5DATA_8821C) + +/* 2 REG_TC6_CTRL_8821C */ +#define BIT_TC6INT_EN_8821C BIT(26) +#define BIT_TC6MODE_8821C BIT(25) +#define BIT_TC6EN_8821C BIT(24) + +#define BIT_SHIFT_TC6DATA_8821C 0 +#define BIT_MASK_TC6DATA_8821C 0xffffff +#define BIT_TC6DATA_8821C(x) (((x) & BIT_MASK_TC6DATA_8821C) << BIT_SHIFT_TC6DATA_8821C) +#define BIT_GET_TC6DATA_8821C(x) (((x) >> BIT_SHIFT_TC6DATA_8821C) & BIT_MASK_TC6DATA_8821C) + +/* 2 REG_MBIST_FAIL_8821C */ + +#define BIT_SHIFT_8051_MBIST_FAIL_8821C 26 +#define BIT_MASK_8051_MBIST_FAIL_8821C 0x7 +#define BIT_8051_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_8051_MBIST_FAIL_8821C) << BIT_SHIFT_8051_MBIST_FAIL_8821C) +#define BIT_GET_8051_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_FAIL_8821C) & BIT_MASK_8051_MBIST_FAIL_8821C) + +#define BIT_SHIFT_USB_MBIST_FAIL_8821C 24 +#define BIT_MASK_USB_MBIST_FAIL_8821C 0x3 +#define BIT_USB_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_USB_MBIST_FAIL_8821C) << BIT_SHIFT_USB_MBIST_FAIL_8821C) +#define BIT_GET_USB_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_FAIL_8821C) & BIT_MASK_USB_MBIST_FAIL_8821C) + +#define BIT_SHIFT_PCIE_MBIST_FAIL_8821C 16 +#define BIT_MASK_PCIE_MBIST_FAIL_8821C 0x3f +#define BIT_PCIE_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_FAIL_8821C) << BIT_SHIFT_PCIE_MBIST_FAIL_8821C) +#define BIT_GET_PCIE_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL_8821C) & BIT_MASK_PCIE_MBIST_FAIL_8821C) + +#define BIT_SHIFT_MAC_MBIST_FAIL_8821C 0 +#define BIT_MASK_MAC_MBIST_FAIL_8821C 0xfff +#define BIT_MAC_MBIST_FAIL_8821C(x) (((x) & BIT_MASK_MAC_MBIST_FAIL_8821C) << BIT_SHIFT_MAC_MBIST_FAIL_8821C) +#define BIT_GET_MAC_MBIST_FAIL_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_FAIL_8821C) & BIT_MASK_MAC_MBIST_FAIL_8821C) + +/* 2 REG_MBIST_START_PAUSE_8821C */ + +#define BIT_SHIFT_8051_MBIST_START_PAUSE_8821C 26 +#define BIT_MASK_8051_MBIST_START_PAUSE_8821C 0x7 +#define BIT_8051_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) << BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) +#define BIT_GET_8051_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE_8821C) & BIT_MASK_8051_MBIST_START_PAUSE_8821C) + +#define BIT_SHIFT_USB_MBIST_START_PAUSE_8821C 24 +#define BIT_MASK_USB_MBIST_START_PAUSE_8821C 0x3 +#define BIT_USB_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) << BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) +#define BIT_GET_USB_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE_8821C) & BIT_MASK_USB_MBIST_START_PAUSE_8821C) + +#define BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C 16 +#define BIT_MASK_PCIE_MBIST_START_PAUSE_8821C 0x3f +#define BIT_PCIE_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) << BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) +#define BIT_GET_PCIE_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE_8821C) & BIT_MASK_PCIE_MBIST_START_PAUSE_8821C) + +#define BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C 0 +#define BIT_MASK_MAC_MBIST_START_PAUSE_8821C 0xfff +#define BIT_MAC_MBIST_START_PAUSE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) << BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) +#define BIT_GET_MAC_MBIST_START_PAUSE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE_8821C) & BIT_MASK_MAC_MBIST_START_PAUSE_8821C) + +/* 2 REG_MBIST_DONE_8821C */ + +#define BIT_SHIFT_8051_MBIST_DONE_8821C 26 +#define BIT_MASK_8051_MBIST_DONE_8821C 0x7 +#define BIT_8051_MBIST_DONE_8821C(x) (((x) & BIT_MASK_8051_MBIST_DONE_8821C) << BIT_SHIFT_8051_MBIST_DONE_8821C) +#define BIT_GET_8051_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_8051_MBIST_DONE_8821C) & BIT_MASK_8051_MBIST_DONE_8821C) + +#define BIT_SHIFT_USB_MBIST_DONE_8821C 24 +#define BIT_MASK_USB_MBIST_DONE_8821C 0x3 +#define BIT_USB_MBIST_DONE_8821C(x) (((x) & BIT_MASK_USB_MBIST_DONE_8821C) << BIT_SHIFT_USB_MBIST_DONE_8821C) +#define BIT_GET_USB_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_USB_MBIST_DONE_8821C) & BIT_MASK_USB_MBIST_DONE_8821C) + +#define BIT_SHIFT_PCIE_MBIST_DONE_8821C 16 +#define BIT_MASK_PCIE_MBIST_DONE_8821C 0x3f +#define BIT_PCIE_MBIST_DONE_8821C(x) (((x) & BIT_MASK_PCIE_MBIST_DONE_8821C) << BIT_SHIFT_PCIE_MBIST_DONE_8821C) +#define BIT_GET_PCIE_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_PCIE_MBIST_DONE_8821C) & BIT_MASK_PCIE_MBIST_DONE_8821C) + +#define BIT_SHIFT_MAC_MBIST_DONE_8821C 0 +#define BIT_MASK_MAC_MBIST_DONE_8821C 0xfff +#define BIT_MAC_MBIST_DONE_8821C(x) (((x) & BIT_MASK_MAC_MBIST_DONE_8821C) << BIT_SHIFT_MAC_MBIST_DONE_8821C) +#define BIT_GET_MAC_MBIST_DONE_8821C(x) (((x) >> BIT_SHIFT_MAC_MBIST_DONE_8821C) & BIT_MASK_MAC_MBIST_DONE_8821C) + +/* 2 REG_MBIST_FAIL_NRML_8821C */ + +#define BIT_SHIFT_MBIST_FAIL_NRML_8821C 0 +#define BIT_MASK_MBIST_FAIL_NRML_8821C 0xffffffffL +#define BIT_MBIST_FAIL_NRML_8821C(x) (((x) & BIT_MASK_MBIST_FAIL_NRML_8821C) << BIT_SHIFT_MBIST_FAIL_NRML_8821C) +#define BIT_GET_MBIST_FAIL_NRML_8821C(x) (((x) >> BIT_SHIFT_MBIST_FAIL_NRML_8821C) & BIT_MASK_MBIST_FAIL_NRML_8821C) + +/* 2 REG_AES_DECRPT_DATA_8821C */ + +#define BIT_SHIFT_IPS_CFG_ADDR_8821C 0 +#define BIT_MASK_IPS_CFG_ADDR_8821C 0xff +#define BIT_IPS_CFG_ADDR_8821C(x) (((x) & BIT_MASK_IPS_CFG_ADDR_8821C) << BIT_SHIFT_IPS_CFG_ADDR_8821C) +#define BIT_GET_IPS_CFG_ADDR_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_ADDR_8821C) & BIT_MASK_IPS_CFG_ADDR_8821C) + +/* 2 REG_AES_DECRPT_CFG_8821C */ + +#define BIT_SHIFT_IPS_CFG_DATA_8821C 0 +#define BIT_MASK_IPS_CFG_DATA_8821C 0xffffffffL +#define BIT_IPS_CFG_DATA_8821C(x) (((x) & BIT_MASK_IPS_CFG_DATA_8821C) << BIT_SHIFT_IPS_CFG_DATA_8821C) +#define BIT_GET_IPS_CFG_DATA_8821C(x) (((x) >> BIT_SHIFT_IPS_CFG_DATA_8821C) & BIT_MASK_IPS_CFG_DATA_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_TMETER_8821C */ +#define BIT_TEMP_VALID_8821C BIT(31) + +#define BIT_SHIFT_TEMP_VALUE_8821C 24 +#define BIT_MASK_TEMP_VALUE_8821C 0x3f +#define BIT_TEMP_VALUE_8821C(x) (((x) & BIT_MASK_TEMP_VALUE_8821C) << BIT_SHIFT_TEMP_VALUE_8821C) +#define BIT_GET_TEMP_VALUE_8821C(x) (((x) >> BIT_SHIFT_TEMP_VALUE_8821C) & BIT_MASK_TEMP_VALUE_8821C) + +#define BIT_SHIFT_REG_TMETER_TIMER_8821C 8 +#define BIT_MASK_REG_TMETER_TIMER_8821C 0xfff +#define BIT_REG_TMETER_TIMER_8821C(x) (((x) & BIT_MASK_REG_TMETER_TIMER_8821C) << BIT_SHIFT_REG_TMETER_TIMER_8821C) +#define BIT_GET_REG_TMETER_TIMER_8821C(x) (((x) >> BIT_SHIFT_REG_TMETER_TIMER_8821C) & BIT_MASK_REG_TMETER_TIMER_8821C) + +#define BIT_SHIFT_REG_TEMP_DELTA_8821C 2 +#define BIT_MASK_REG_TEMP_DELTA_8821C 0x3f +#define BIT_REG_TEMP_DELTA_8821C(x) (((x) & BIT_MASK_REG_TEMP_DELTA_8821C) << BIT_SHIFT_REG_TEMP_DELTA_8821C) +#define BIT_GET_REG_TEMP_DELTA_8821C(x) (((x) >> BIT_SHIFT_REG_TEMP_DELTA_8821C) & BIT_MASK_REG_TEMP_DELTA_8821C) + +#define BIT_REG_TMETER_EN_8821C BIT(0) + +/* 2 REG_OSC_32K_CTRL_8821C */ + +#define BIT_SHIFT_OSC_32K_CLKGEN_0_8821C 16 +#define BIT_MASK_OSC_32K_CLKGEN_0_8821C 0xffff +#define BIT_OSC_32K_CLKGEN_0_8821C(x) (((x) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) << BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) +#define BIT_GET_OSC_32K_CLKGEN_0_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0_8821C) & BIT_MASK_OSC_32K_CLKGEN_0_8821C) + +#define BIT_SHIFT_OSC_32K_RES_COMP_8821C 4 +#define BIT_MASK_OSC_32K_RES_COMP_8821C 0x3 +#define BIT_OSC_32K_RES_COMP_8821C(x) (((x) & BIT_MASK_OSC_32K_RES_COMP_8821C) << BIT_SHIFT_OSC_32K_RES_COMP_8821C) +#define BIT_GET_OSC_32K_RES_COMP_8821C(x) (((x) >> BIT_SHIFT_OSC_32K_RES_COMP_8821C) & BIT_MASK_OSC_32K_RES_COMP_8821C) + +#define BIT_OSC_32K_OUT_SEL_8821C BIT(3) +#define BIT_ISO_WL_2_OSC_32K_8821C BIT(1) +#define BIT_POW_CKGEN_8821C BIT(0) + +/* 2 REG_32K_CAL_REG1_8821C */ +#define BIT_CAL_32K_REG_WR_8821C BIT(31) +#define BIT_CAL_32K_DBG_SEL_8821C BIT(22) + +#define BIT_SHIFT_CAL_32K_REG_ADDR_8821C 16 +#define BIT_MASK_CAL_32K_REG_ADDR_8821C 0x3f +#define BIT_CAL_32K_REG_ADDR_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_ADDR_8821C) << BIT_SHIFT_CAL_32K_REG_ADDR_8821C) +#define BIT_GET_CAL_32K_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR_8821C) & BIT_MASK_CAL_32K_REG_ADDR_8821C) + +#define BIT_SHIFT_CAL_32K_REG_DATA_8821C 0 +#define BIT_MASK_CAL_32K_REG_DATA_8821C 0xffff +#define BIT_CAL_32K_REG_DATA_8821C(x) (((x) & BIT_MASK_CAL_32K_REG_DATA_8821C) << BIT_SHIFT_CAL_32K_REG_DATA_8821C) +#define BIT_GET_CAL_32K_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_CAL_32K_REG_DATA_8821C) & BIT_MASK_CAL_32K_REG_DATA_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_C2HEVT_8821C */ + +#define BIT_SHIFT_C2HEVT_MSG_V1_8821C 0 +#define BIT_MASK_C2HEVT_MSG_V1_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_V1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_V1_8821C) << BIT_SHIFT_C2HEVT_MSG_V1_8821C) +#define BIT_GET_C2HEVT_MSG_V1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_V1_8821C) & BIT_MASK_C2HEVT_MSG_V1_8821C) + +/* 2 REG_C2HEVT_1_8821C */ + +#define BIT_SHIFT_C2HEVT_MSG_1_8821C 0 +#define BIT_MASK_C2HEVT_MSG_1_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_1_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_1_8821C) << BIT_SHIFT_C2HEVT_MSG_1_8821C) +#define BIT_GET_C2HEVT_MSG_1_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_1_8821C) & BIT_MASK_C2HEVT_MSG_1_8821C) + +/* 2 REG_C2HEVT_2_8821C */ + +#define BIT_SHIFT_C2HEVT_MSG_2_8821C 0 +#define BIT_MASK_C2HEVT_MSG_2_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_2_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_2_8821C) << BIT_SHIFT_C2HEVT_MSG_2_8821C) +#define BIT_GET_C2HEVT_MSG_2_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_2_8821C) & BIT_MASK_C2HEVT_MSG_2_8821C) + +/* 2 REG_C2HEVT_3_8821C */ + +#define BIT_SHIFT_C2HEVT_MSG_3_8821C 0 +#define BIT_MASK_C2HEVT_MSG_3_8821C 0xffffffffL +#define BIT_C2HEVT_MSG_3_8821C(x) (((x) & BIT_MASK_C2HEVT_MSG_3_8821C) << BIT_SHIFT_C2HEVT_MSG_3_8821C) +#define BIT_GET_C2HEVT_MSG_3_8821C(x) (((x) >> BIT_SHIFT_C2HEVT_MSG_3_8821C) & BIT_MASK_C2HEVT_MSG_3_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_SW_DEFINED_PAGE1_8821C */ + +#define BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C 0 +#define BIT_MASK_SW_DEFINED_PAGE1_V1_8821C 0xffffffffL +#define BIT_SW_DEFINED_PAGE1_V1_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) << BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) +#define BIT_GET_SW_DEFINED_PAGE1_V1_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1_V1_8821C) & BIT_MASK_SW_DEFINED_PAGE1_V1_8821C) + +/* 2 REG_SW_DEFINED_PAGE2_8821C */ + +#define BIT_SHIFT_SW_DEFINED_PAGE2_8821C 0 +#define BIT_MASK_SW_DEFINED_PAGE2_8821C 0xffffffffL +#define BIT_SW_DEFINED_PAGE2_8821C(x) (((x) & BIT_MASK_SW_DEFINED_PAGE2_8821C) << BIT_SHIFT_SW_DEFINED_PAGE2_8821C) +#define BIT_GET_SW_DEFINED_PAGE2_8821C(x) (((x) >> BIT_SHIFT_SW_DEFINED_PAGE2_8821C) & BIT_MASK_SW_DEFINED_PAGE2_8821C) + +/* 2 REG_MCUTST_I_8821C */ + +#define BIT_SHIFT_MCUDMSG_I_8821C 0 +#define BIT_MASK_MCUDMSG_I_8821C 0xffffffffL +#define BIT_MCUDMSG_I_8821C(x) (((x) & BIT_MASK_MCUDMSG_I_8821C) << BIT_SHIFT_MCUDMSG_I_8821C) +#define BIT_GET_MCUDMSG_I_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_I_8821C) & BIT_MASK_MCUDMSG_I_8821C) + +/* 2 REG_MCUTST_II_8821C */ + +#define BIT_SHIFT_MCUDMSG_II_8821C 0 +#define BIT_MASK_MCUDMSG_II_8821C 0xffffffffL +#define BIT_MCUDMSG_II_8821C(x) (((x) & BIT_MASK_MCUDMSG_II_8821C) << BIT_SHIFT_MCUDMSG_II_8821C) +#define BIT_GET_MCUDMSG_II_8821C(x) (((x) >> BIT_SHIFT_MCUDMSG_II_8821C) & BIT_MASK_MCUDMSG_II_8821C) + +/* 2 REG_FMETHR_8821C */ +#define BIT_FMSG_INT_8821C BIT(31) + +#define BIT_SHIFT_FW_MSG_8821C 0 +#define BIT_MASK_FW_MSG_8821C 0xffffffffL +#define BIT_FW_MSG_8821C(x) (((x) & BIT_MASK_FW_MSG_8821C) << BIT_SHIFT_FW_MSG_8821C) +#define BIT_GET_FW_MSG_8821C(x) (((x) >> BIT_SHIFT_FW_MSG_8821C) & BIT_MASK_FW_MSG_8821C) + +/* 2 REG_HMETFR_8821C */ + +#define BIT_SHIFT_HRCV_MSG_8821C 24 +#define BIT_MASK_HRCV_MSG_8821C 0xff +#define BIT_HRCV_MSG_8821C(x) (((x) & BIT_MASK_HRCV_MSG_8821C) << BIT_SHIFT_HRCV_MSG_8821C) +#define BIT_GET_HRCV_MSG_8821C(x) (((x) >> BIT_SHIFT_HRCV_MSG_8821C) & BIT_MASK_HRCV_MSG_8821C) + +#define BIT_INT_BOX3_8821C BIT(3) +#define BIT_INT_BOX2_8821C BIT(2) +#define BIT_INT_BOX1_8821C BIT(1) +#define BIT_INT_BOX0_8821C BIT(0) + +/* 2 REG_HMEBOX0_8821C */ + +#define BIT_SHIFT_HOST_MSG_0_8821C 0 +#define BIT_MASK_HOST_MSG_0_8821C 0xffffffffL +#define BIT_HOST_MSG_0_8821C(x) (((x) & BIT_MASK_HOST_MSG_0_8821C) << BIT_SHIFT_HOST_MSG_0_8821C) +#define BIT_GET_HOST_MSG_0_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_0_8821C) & BIT_MASK_HOST_MSG_0_8821C) + +/* 2 REG_HMEBOX1_8821C */ + +#define BIT_SHIFT_HOST_MSG_1_8821C 0 +#define BIT_MASK_HOST_MSG_1_8821C 0xffffffffL +#define BIT_HOST_MSG_1_8821C(x) (((x) & BIT_MASK_HOST_MSG_1_8821C) << BIT_SHIFT_HOST_MSG_1_8821C) +#define BIT_GET_HOST_MSG_1_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_1_8821C) & BIT_MASK_HOST_MSG_1_8821C) + +/* 2 REG_HMEBOX2_8821C */ + +#define BIT_SHIFT_HOST_MSG_2_8821C 0 +#define BIT_MASK_HOST_MSG_2_8821C 0xffffffffL +#define BIT_HOST_MSG_2_8821C(x) (((x) & BIT_MASK_HOST_MSG_2_8821C) << BIT_SHIFT_HOST_MSG_2_8821C) +#define BIT_GET_HOST_MSG_2_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_2_8821C) & BIT_MASK_HOST_MSG_2_8821C) + +/* 2 REG_HMEBOX3_8821C */ + +#define BIT_SHIFT_HOST_MSG_3_8821C 0 +#define BIT_MASK_HOST_MSG_3_8821C 0xffffffffL +#define BIT_HOST_MSG_3_8821C(x) (((x) & BIT_MASK_HOST_MSG_3_8821C) << BIT_SHIFT_HOST_MSG_3_8821C) +#define BIT_GET_HOST_MSG_3_8821C(x) (((x) >> BIT_SHIFT_HOST_MSG_3_8821C) & BIT_MASK_HOST_MSG_3_8821C) + +/* 2 REG_LLT_INIT_8821C */ + +#define BIT_SHIFT_LLTE_RWM_8821C 30 +#define BIT_MASK_LLTE_RWM_8821C 0x3 +#define BIT_LLTE_RWM_8821C(x) (((x) & BIT_MASK_LLTE_RWM_8821C) << BIT_SHIFT_LLTE_RWM_8821C) +#define BIT_GET_LLTE_RWM_8821C(x) (((x) >> BIT_SHIFT_LLTE_RWM_8821C) & BIT_MASK_LLTE_RWM_8821C) + +#define BIT_SHIFT_LLTINI_PDATA_V1_8821C 16 +#define BIT_MASK_LLTINI_PDATA_V1_8821C 0xfff +#define BIT_LLTINI_PDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_PDATA_V1_8821C) << BIT_SHIFT_LLTINI_PDATA_V1_8821C) +#define BIT_GET_LLTINI_PDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_PDATA_V1_8821C) & BIT_MASK_LLTINI_PDATA_V1_8821C) + +#define BIT_SHIFT_LLTINI_HDATA_V1_8821C 0 +#define BIT_MASK_LLTINI_HDATA_V1_8821C 0xfff +#define BIT_LLTINI_HDATA_V1_8821C(x) (((x) & BIT_MASK_LLTINI_HDATA_V1_8821C) << BIT_SHIFT_LLTINI_HDATA_V1_8821C) +#define BIT_GET_LLTINI_HDATA_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_HDATA_V1_8821C) & BIT_MASK_LLTINI_HDATA_V1_8821C) + +/* 2 REG_LLT_INIT_ADDR_8821C */ + +#define BIT_SHIFT_LLTINI_ADDR_V1_8821C 0 +#define BIT_MASK_LLTINI_ADDR_V1_8821C 0xfff +#define BIT_LLTINI_ADDR_V1_8821C(x) (((x) & BIT_MASK_LLTINI_ADDR_V1_8821C) << BIT_SHIFT_LLTINI_ADDR_V1_8821C) +#define BIT_GET_LLTINI_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LLTINI_ADDR_V1_8821C) & BIT_MASK_LLTINI_ADDR_V1_8821C) + +/* 2 REG_BB_ACCESS_CTRL_8821C */ + +#define BIT_SHIFT_BB_WRITE_READ_8821C 30 +#define BIT_MASK_BB_WRITE_READ_8821C 0x3 +#define BIT_BB_WRITE_READ_8821C(x) (((x) & BIT_MASK_BB_WRITE_READ_8821C) << BIT_SHIFT_BB_WRITE_READ_8821C) +#define BIT_GET_BB_WRITE_READ_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_READ_8821C) & BIT_MASK_BB_WRITE_READ_8821C) + +#define BIT_SHIFT_BB_WRITE_EN_8821C 12 +#define BIT_MASK_BB_WRITE_EN_8821C 0xf +#define BIT_BB_WRITE_EN_8821C(x) (((x) & BIT_MASK_BB_WRITE_EN_8821C) << BIT_SHIFT_BB_WRITE_EN_8821C) +#define BIT_GET_BB_WRITE_EN_8821C(x) (((x) >> BIT_SHIFT_BB_WRITE_EN_8821C) & BIT_MASK_BB_WRITE_EN_8821C) + +#define BIT_SHIFT_BB_ADDR_8821C 2 +#define BIT_MASK_BB_ADDR_8821C 0x1ff +#define BIT_BB_ADDR_8821C(x) (((x) & BIT_MASK_BB_ADDR_8821C) << BIT_SHIFT_BB_ADDR_8821C) +#define BIT_GET_BB_ADDR_8821C(x) (((x) >> BIT_SHIFT_BB_ADDR_8821C) & BIT_MASK_BB_ADDR_8821C) + +#define BIT_BB_ERRACC_8821C BIT(0) + +/* 2 REG_BB_ACCESS_DATA_8821C */ + +#define BIT_SHIFT_BB_DATA_8821C 0 +#define BIT_MASK_BB_DATA_8821C 0xffffffffL +#define BIT_BB_DATA_8821C(x) (((x) & BIT_MASK_BB_DATA_8821C) << BIT_SHIFT_BB_DATA_8821C) +#define BIT_GET_BB_DATA_8821C(x) (((x) >> BIT_SHIFT_BB_DATA_8821C) & BIT_MASK_BB_DATA_8821C) + +/* 2 REG_HMEBOX_E0_8821C */ + +#define BIT_SHIFT_HMEBOX_E0_8821C 0 +#define BIT_MASK_HMEBOX_E0_8821C 0xffffffffL +#define BIT_HMEBOX_E0_8821C(x) (((x) & BIT_MASK_HMEBOX_E0_8821C) << BIT_SHIFT_HMEBOX_E0_8821C) +#define BIT_GET_HMEBOX_E0_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E0_8821C) & BIT_MASK_HMEBOX_E0_8821C) + +/* 2 REG_HMEBOX_E1_8821C */ + +#define BIT_SHIFT_HMEBOX_E1_8821C 0 +#define BIT_MASK_HMEBOX_E1_8821C 0xffffffffL +#define BIT_HMEBOX_E1_8821C(x) (((x) & BIT_MASK_HMEBOX_E1_8821C) << BIT_SHIFT_HMEBOX_E1_8821C) +#define BIT_GET_HMEBOX_E1_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E1_8821C) & BIT_MASK_HMEBOX_E1_8821C) + +/* 2 REG_HMEBOX_E2_8821C */ + +#define BIT_SHIFT_HMEBOX_E2_8821C 0 +#define BIT_MASK_HMEBOX_E2_8821C 0xffffffffL +#define BIT_HMEBOX_E2_8821C(x) (((x) & BIT_MASK_HMEBOX_E2_8821C) << BIT_SHIFT_HMEBOX_E2_8821C) +#define BIT_GET_HMEBOX_E2_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E2_8821C) & BIT_MASK_HMEBOX_E2_8821C) + +/* 2 REG_HMEBOX_E3_8821C */ + +#define BIT_SHIFT_HMEBOX_E3_8821C 0 +#define BIT_MASK_HMEBOX_E3_8821C 0xffffffffL +#define BIT_HMEBOX_E3_8821C(x) (((x) & BIT_MASK_HMEBOX_E3_8821C) << BIT_SHIFT_HMEBOX_E3_8821C) +#define BIT_GET_HMEBOX_E3_8821C(x) (((x) >> BIT_SHIFT_HMEBOX_E3_8821C) & BIT_MASK_HMEBOX_E3_8821C) + +/* 2 REG_CR_EXT_8821C */ + +#define BIT_SHIFT_PHY_REQ_DELAY_8821C 24 +#define BIT_MASK_PHY_REQ_DELAY_8821C 0xf +#define BIT_PHY_REQ_DELAY_8821C(x) (((x) & BIT_MASK_PHY_REQ_DELAY_8821C) << BIT_SHIFT_PHY_REQ_DELAY_8821C) +#define BIT_GET_PHY_REQ_DELAY_8821C(x) (((x) >> BIT_SHIFT_PHY_REQ_DELAY_8821C) & BIT_MASK_PHY_REQ_DELAY_8821C) + +/* 2 REG_NOT_VALID_8821C */ +#define BIT_SPD_DOWN_8821C BIT(16) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_NETYPE4_8821C 4 +#define BIT_MASK_NETYPE4_8821C 0x3 +#define BIT_NETYPE4_8821C(x) (((x) & BIT_MASK_NETYPE4_8821C) << BIT_SHIFT_NETYPE4_8821C) +#define BIT_GET_NETYPE4_8821C(x) (((x) >> BIT_SHIFT_NETYPE4_8821C) & BIT_MASK_NETYPE4_8821C) + +#define BIT_SHIFT_NETYPE3_8821C 2 +#define BIT_MASK_NETYPE3_8821C 0x3 +#define BIT_NETYPE3_8821C(x) (((x) & BIT_MASK_NETYPE3_8821C) << BIT_SHIFT_NETYPE3_8821C) +#define BIT_GET_NETYPE3_8821C(x) (((x) >> BIT_SHIFT_NETYPE3_8821C) & BIT_MASK_NETYPE3_8821C) + +#define BIT_SHIFT_NETYPE2_8821C 0 +#define BIT_MASK_NETYPE2_8821C 0x3 +#define BIT_NETYPE2_8821C(x) (((x) & BIT_MASK_NETYPE2_8821C) << BIT_SHIFT_NETYPE2_8821C) +#define BIT_GET_NETYPE2_8821C(x) (((x) >> BIT_SHIFT_NETYPE2_8821C) & BIT_MASK_NETYPE2_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_FWFF_8821C */ + +#define BIT_SHIFT_PKTNUM_TH_V1_8821C 24 +#define BIT_MASK_PKTNUM_TH_V1_8821C 0xff +#define BIT_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V1_8821C) << BIT_SHIFT_PKTNUM_TH_V1_8821C) +#define BIT_GET_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V1_8821C) & BIT_MASK_PKTNUM_TH_V1_8821C) + +#define BIT_SHIFT_TIMER_TH_8821C 16 +#define BIT_MASK_TIMER_TH_8821C 0xff +#define BIT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TIMER_TH_8821C) << BIT_SHIFT_TIMER_TH_8821C) +#define BIT_GET_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TIMER_TH_8821C) & BIT_MASK_TIMER_TH_8821C) + +#define BIT_SHIFT_RXPKT1ENADDR_8821C 0 +#define BIT_MASK_RXPKT1ENADDR_8821C 0xffff +#define BIT_RXPKT1ENADDR_8821C(x) (((x) & BIT_MASK_RXPKT1ENADDR_8821C) << BIT_SHIFT_RXPKT1ENADDR_8821C) +#define BIT_GET_RXPKT1ENADDR_8821C(x) (((x) >> BIT_SHIFT_RXPKT1ENADDR_8821C) & BIT_MASK_RXPKT1ENADDR_8821C) + +/* 2 REG_RXFF_PTR_V1_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_RXFF0_RDPTR_V2_8821C 0 +#define BIT_MASK_RXFF0_RDPTR_V2_8821C 0x3ffff +#define BIT_RXFF0_RDPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_RDPTR_V2_8821C) << BIT_SHIFT_RXFF0_RDPTR_V2_8821C) +#define BIT_GET_RXFF0_RDPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2_8821C) & BIT_MASK_RXFF0_RDPTR_V2_8821C) + +/* 2 REG_RXFF_WTR_V1_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_RXFF0_WTPTR_V2_8821C 0 +#define BIT_MASK_RXFF0_WTPTR_V2_8821C 0x3ffff +#define BIT_RXFF0_WTPTR_V2_8821C(x) (((x) & BIT_MASK_RXFF0_WTPTR_V2_8821C) << BIT_SHIFT_RXFF0_WTPTR_V2_8821C) +#define BIT_GET_RXFF0_WTPTR_V2_8821C(x) (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2_8821C) & BIT_MASK_RXFF0_WTPTR_V2_8821C) + +/* 2 REG_FE2IMR_8821C */ +#define BIT__FE4ISR__IND_MSK_8821C BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_EN_8821C BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_EN_8821C BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_EN_8821C BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_EN_8821C BIT(25) +#define BIT_FS_TXSC_VODONE_INT_EN_8821C BIT(24) +#define BIT_FS_ATIM_MB7_INT_EN_8821C BIT(23) +#define BIT_FS_ATIM_MB6_INT_EN_8821C BIT(22) +#define BIT_FS_ATIM_MB5_INT_EN_8821C BIT(21) +#define BIT_FS_ATIM_MB4_INT_EN_8821C BIT(20) +#define BIT_FS_ATIM_MB3_INT_EN_8821C BIT(19) +#define BIT_FS_ATIM_MB2_INT_EN_8821C BIT(18) +#define BIT_FS_ATIM_MB1_INT_EN_8821C BIT(17) +#define BIT_FS_ATIM_MB0_INT_EN_8821C BIT(16) +#define BIT_FS_TBTT4INT_EN_8821C BIT(11) +#define BIT_FS_TBTT3INT_EN_8821C BIT(10) +#define BIT_FS_TBTT2INT_EN_8821C BIT(9) +#define BIT_FS_TBTT1INT_EN_8821C BIT(8) +#define BIT_FS_TBTT0_MB7INT_EN_8821C BIT(7) +#define BIT_FS_TBTT0_MB6INT_EN_8821C BIT(6) +#define BIT_FS_TBTT0_MB5INT_EN_8821C BIT(5) +#define BIT_FS_TBTT0_MB4INT_EN_8821C BIT(4) +#define BIT_FS_TBTT0_MB3INT_EN_8821C BIT(3) +#define BIT_FS_TBTT0_MB2INT_EN_8821C BIT(2) +#define BIT_FS_TBTT0_MB1INT_EN_8821C BIT(1) +#define BIT_FS_TBTT0_INT_EN_8821C BIT(0) + +/* 2 REG_FE2ISR_8821C */ +#define BIT__FE4ISR__IND_INT_8821C BIT(29) +#define BIT_FS_TXSC_DESC_DONE_INT_8821C BIT(28) +#define BIT_FS_TXSC_BKDONE_INT_8821C BIT(27) +#define BIT_FS_TXSC_BEDONE_INT_8821C BIT(26) +#define BIT_FS_TXSC_VIDONE_INT_8821C BIT(25) +#define BIT_FS_TXSC_VODONE_INT_8821C BIT(24) +#define BIT_FS_ATIM_MB7_INT_8821C BIT(23) +#define BIT_FS_ATIM_MB6_INT_8821C BIT(22) +#define BIT_FS_ATIM_MB5_INT_8821C BIT(21) +#define BIT_FS_ATIM_MB4_INT_8821C BIT(20) +#define BIT_FS_ATIM_MB3_INT_8821C BIT(19) +#define BIT_FS_ATIM_MB2_INT_8821C BIT(18) +#define BIT_FS_ATIM_MB1_INT_8821C BIT(17) +#define BIT_FS_ATIM_MB0_INT_8821C BIT(16) +#define BIT_FS_TBTT4INT_8821C BIT(11) +#define BIT_FS_TBTT3INT_8821C BIT(10) +#define BIT_FS_TBTT2INT_8821C BIT(9) +#define BIT_FS_TBTT1INT_8821C BIT(8) +#define BIT_FS_TBTT0_MB7INT_8821C BIT(7) +#define BIT_FS_TBTT0_MB6INT_8821C BIT(6) +#define BIT_FS_TBTT0_MB5INT_8821C BIT(5) +#define BIT_FS_TBTT0_MB4INT_8821C BIT(4) +#define BIT_FS_TBTT0_MB3INT_8821C BIT(3) +#define BIT_FS_TBTT0_MB2INT_8821C BIT(2) +#define BIT_FS_TBTT0_MB1INT_8821C BIT(1) +#define BIT_FS_TBTT0_INT_8821C BIT(0) + +/* 2 REG_FE3IMR_8821C */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN_8821C BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN_8821C BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN_8821C BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN_8821C BIT(28) +#define BIT_FS_BCNDMA4_INT_EN_8821C BIT(27) +#define BIT_FS_BCNDMA3_INT_EN_8821C BIT(26) +#define BIT_FS_BCNDMA2_INT_EN_8821C BIT(25) +#define BIT_FS_BCNDMA1_INT_EN_8821C BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_EN_8821C BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_EN_8821C BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_EN_8821C BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_EN_8821C BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_EN_8821C BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_EN_8821C BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_EN_8821C BIT(17) +#define BIT_FS_BCNDMA0_INT_EN_8821C BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT__EN_8821C BIT(15) +#define BIT_FS_BCNERLY4_INT_EN_8821C BIT(11) +#define BIT_FS_BCNERLY3_INT_EN_8821C BIT(10) +#define BIT_FS_BCNERLY2_INT_EN_8821C BIT(9) +#define BIT_FS_BCNERLY1_INT_EN_8821C BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_EN_8821C BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_EN_8821C BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_EN_8821C BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_EN_8821C BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_EN_8821C BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_EN_8821C BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_EN_8821C BIT(1) +#define BIT_FS_BCNERLY0_INT_EN_8821C BIT(0) + +/* 2 REG_FE3ISR_8821C */ +#define BIT_FS_CLI3_MTI_BCNIVLEAR_INT_8821C BIT(31) +#define BIT_FS_CLI2_MTI_BCNIVLEAR_INT_8821C BIT(30) +#define BIT_FS_CLI1_MTI_BCNIVLEAR_INT_8821C BIT(29) +#define BIT_FS_CLI0_MTI_BCNIVLEAR_INT_8821C BIT(28) +#define BIT_FS_BCNDMA4_INT_8821C BIT(27) +#define BIT_FS_BCNDMA3_INT_8821C BIT(26) +#define BIT_FS_BCNDMA2_INT_8821C BIT(25) +#define BIT_FS_BCNDMA1_INT_8821C BIT(24) +#define BIT_FS_BCNDMA0_MB7_INT_8821C BIT(23) +#define BIT_FS_BCNDMA0_MB6_INT_8821C BIT(22) +#define BIT_FS_BCNDMA0_MB5_INT_8821C BIT(21) +#define BIT_FS_BCNDMA0_MB4_INT_8821C BIT(20) +#define BIT_FS_BCNDMA0_MB3_INT_8821C BIT(19) +#define BIT_FS_BCNDMA0_MB2_INT_8821C BIT(18) +#define BIT_FS_BCNDMA0_MB1_INT_8821C BIT(17) +#define BIT_FS_BCNDMA0_INT_8821C BIT(16) +#define BIT_FS_MTI_BCNIVLEAR_INT_8821C BIT(15) +#define BIT_FS_BCNERLY4_INT_8821C BIT(11) +#define BIT_FS_BCNERLY3_INT_8821C BIT(10) +#define BIT_FS_BCNERLY2_INT_8821C BIT(9) +#define BIT_FS_BCNERLY1_INT_8821C BIT(8) +#define BIT_FS_BCNERLY0_MB7INT_8821C BIT(7) +#define BIT_FS_BCNERLY0_MB6INT_8821C BIT(6) +#define BIT_FS_BCNERLY0_MB5INT_8821C BIT(5) +#define BIT_FS_BCNERLY0_MB4INT_8821C BIT(4) +#define BIT_FS_BCNERLY0_MB3INT_8821C BIT(3) +#define BIT_FS_BCNERLY0_MB2INT_8821C BIT(2) +#define BIT_FS_BCNERLY0_MB1INT_8821C BIT(1) +#define BIT_FS_BCNERLY0_INT_8821C BIT(0) + +/* 2 REG_FE4IMR_8821C */ +#define BIT_FS_CLI3_TXPKTIN_INT_EN_8821C BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_EN_8821C BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_EN_8821C BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_EN_8821C BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_EN_8821C BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_EN_8821C BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_EN_8821C BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_EN_8821C BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_EN_8821C BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_EN_8821C BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_EN_8821C BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_EN_8821C BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_EN_8821C BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_EN_8821C BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_EN_8821C BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_EN_8821C BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_EN_8821C BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_EN_8821C BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_EN_8821C BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_EN_8821C BIT(0) + +/* 2 REG_FE4ISR_8821C */ +#define BIT_FS_CLI3_TXPKTIN_INT_8821C BIT(19) +#define BIT_FS_CLI2_TXPKTIN_INT_8821C BIT(18) +#define BIT_FS_CLI1_TXPKTIN_INT_8821C BIT(17) +#define BIT_FS_CLI0_TXPKTIN_INT_8821C BIT(16) +#define BIT_FS_CLI3_RX_UMD0_INT_8821C BIT(15) +#define BIT_FS_CLI3_RX_UMD1_INT_8821C BIT(14) +#define BIT_FS_CLI3_RX_BMD0_INT_8821C BIT(13) +#define BIT_FS_CLI3_RX_BMD1_INT_8821C BIT(12) +#define BIT_FS_CLI2_RX_UMD0_INT_8821C BIT(11) +#define BIT_FS_CLI2_RX_UMD1_INT_8821C BIT(10) +#define BIT_FS_CLI2_RX_BMD0_INT_8821C BIT(9) +#define BIT_FS_CLI2_RX_BMD1_INT_8821C BIT(8) +#define BIT_FS_CLI1_RX_UMD0_INT_8821C BIT(7) +#define BIT_FS_CLI1_RX_UMD1_INT_8821C BIT(6) +#define BIT_FS_CLI1_RX_BMD0_INT_8821C BIT(5) +#define BIT_FS_CLI1_RX_BMD1_INT_8821C BIT(4) +#define BIT_FS_CLI0_RX_UMD0_INT_8821C BIT(3) +#define BIT_FS_CLI0_RX_UMD1_INT_8821C BIT(2) +#define BIT_FS_CLI0_RX_BMD0_INT_8821C BIT(1) +#define BIT_FS_CLI0_RX_BMD1_INT_8821C BIT(0) + +/* 2 REG_FT1IMR_8821C */ +#define BIT__FT2ISR__IND_MSK_8821C BIT(30) +#define BIT_FTM_PTT_INT_EN_8821C BIT(29) +#define BIT_RXFTMREQ_INT_EN_8821C BIT(28) +#define BIT_RXFTM_INT_EN_8821C BIT(27) +#define BIT_TXFTM_INT_EN_8821C BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_EN_8821C BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_EN_8821C BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_EN_8821C BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_EN_8821C BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_EN_8821C BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_EN_8821C BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_EN_8821C BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_EN_8821C BIT(18) +#define BIT_FS_CTWEND2_INT_EN_8821C BIT(17) +#define BIT_FS_CTWEND1_INT_EN_8821C BIT(16) +#define BIT_FS_CTWEND0_INT_EN_8821C BIT(15) +#define BIT_FS_TX_NULL1_INT_EN_8821C BIT(14) +#define BIT_FS_TX_NULL0_INT_EN_8821C BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_EN_8821C BIT(12) +#define BIT_FS_P2P_RFON2_INT_EN_8821C BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_EN_8821C BIT(10) +#define BIT_FS_P2P_RFON1_INT_EN_8821C BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_EN_8821C BIT(8) +#define BIT_FS_P2P_RFON0_INT_EN_8821C BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_EN_8821C BIT(6) +#define BIT_FS_RX_UAPSDMD1_EN_8821C BIT(5) +#define BIT_FS_RX_UAPSDMD0_EN_8821C BIT(4) +#define BIT_FS_TRIGGER_PKT_EN_8821C BIT(3) +#define BIT_FS_EOSP_INT_EN_8821C BIT(2) +#define BIT_FS_RPWM2_INT_EN_8821C BIT(1) +#define BIT_FS_RPWM_INT_EN_8821C BIT(0) + +/* 2 REG_FT1ISR_8821C */ +#define BIT__FT2ISR__IND_INT_8821C BIT(30) +#define BIT_FTM_PTT_INT_8821C BIT(29) +#define BIT_RXFTMREQ_INT_8821C BIT(28) +#define BIT_RXFTM_INT_8821C BIT(27) +#define BIT_TXFTM_INT_8821C BIT(26) +#define BIT_FS_H2C_CMD_OK_INT_8821C BIT(25) +#define BIT_FS_H2C_CMD_FULL_INT_8821C BIT(24) +#define BIT_FS_MACID_PWRCHANGE5_INT_8821C BIT(23) +#define BIT_FS_MACID_PWRCHANGE4_INT_8821C BIT(22) +#define BIT_FS_MACID_PWRCHANGE3_INT_8821C BIT(21) +#define BIT_FS_MACID_PWRCHANGE2_INT_8821C BIT(20) +#define BIT_FS_MACID_PWRCHANGE1_INT_8821C BIT(19) +#define BIT_FS_MACID_PWRCHANGE0_INT_8821C BIT(18) +#define BIT_FS_CTWEND2_INT_8821C BIT(17) +#define BIT_FS_CTWEND1_INT_8821C BIT(16) +#define BIT_FS_CTWEND0_INT_8821C BIT(15) +#define BIT_FS_TX_NULL1_INT_8821C BIT(14) +#define BIT_FS_TX_NULL0_INT_8821C BIT(13) +#define BIT_FS_TSF_BIT32_TOGGLE_INT_8821C BIT(12) +#define BIT_FS_P2P_RFON2_INT_8821C BIT(11) +#define BIT_FS_P2P_RFOFF2_INT_8821C BIT(10) +#define BIT_FS_P2P_RFON1_INT_8821C BIT(9) +#define BIT_FS_P2P_RFOFF1_INT_8821C BIT(8) +#define BIT_FS_P2P_RFON0_INT_8821C BIT(7) +#define BIT_FS_P2P_RFOFF0_INT_8821C BIT(6) +#define BIT_FS_RX_UAPSDMD1_INT_8821C BIT(5) +#define BIT_FS_RX_UAPSDMD0_INT_8821C BIT(4) +#define BIT_FS_TRIGGER_PKT_INT_8821C BIT(3) +#define BIT_FS_EOSP_INT_8821C BIT(2) +#define BIT_FS_RPWM2_INT_8821C BIT(1) +#define BIT_FS_RPWM_INT_8821C BIT(0) + +/* 2 REG_SPWR0_8821C */ + +#define BIT_SHIFT_MID_31TO0_8821C 0 +#define BIT_MASK_MID_31TO0_8821C 0xffffffffL +#define BIT_MID_31TO0_8821C(x) (((x) & BIT_MASK_MID_31TO0_8821C) << BIT_SHIFT_MID_31TO0_8821C) +#define BIT_GET_MID_31TO0_8821C(x) (((x) >> BIT_SHIFT_MID_31TO0_8821C) & BIT_MASK_MID_31TO0_8821C) + +/* 2 REG_SPWR1_8821C */ + +#define BIT_SHIFT_MID_63TO32_8821C 0 +#define BIT_MASK_MID_63TO32_8821C 0xffffffffL +#define BIT_MID_63TO32_8821C(x) (((x) & BIT_MASK_MID_63TO32_8821C) << BIT_SHIFT_MID_63TO32_8821C) +#define BIT_GET_MID_63TO32_8821C(x) (((x) >> BIT_SHIFT_MID_63TO32_8821C) & BIT_MASK_MID_63TO32_8821C) + +/* 2 REG_SPWR2_8821C */ + +#define BIT_SHIFT_MID_95O64_8821C 0 +#define BIT_MASK_MID_95O64_8821C 0xffffffffL +#define BIT_MID_95O64_8821C(x) (((x) & BIT_MASK_MID_95O64_8821C) << BIT_SHIFT_MID_95O64_8821C) +#define BIT_GET_MID_95O64_8821C(x) (((x) >> BIT_SHIFT_MID_95O64_8821C) & BIT_MASK_MID_95O64_8821C) + +/* 2 REG_SPWR3_8821C */ + +#define BIT_SHIFT_MID_127TO96_8821C 0 +#define BIT_MASK_MID_127TO96_8821C 0xffffffffL +#define BIT_MID_127TO96_8821C(x) (((x) & BIT_MASK_MID_127TO96_8821C) << BIT_SHIFT_MID_127TO96_8821C) +#define BIT_GET_MID_127TO96_8821C(x) (((x) >> BIT_SHIFT_MID_127TO96_8821C) & BIT_MASK_MID_127TO96_8821C) + +/* 2 REG_POWSEQ_8821C */ + +#define BIT_SHIFT_SEQNUM_MID_8821C 16 +#define BIT_MASK_SEQNUM_MID_8821C 0xffff +#define BIT_SEQNUM_MID_8821C(x) (((x) & BIT_MASK_SEQNUM_MID_8821C) << BIT_SHIFT_SEQNUM_MID_8821C) +#define BIT_GET_SEQNUM_MID_8821C(x) (((x) >> BIT_SHIFT_SEQNUM_MID_8821C) & BIT_MASK_SEQNUM_MID_8821C) + +#define BIT_SHIFT_REF_MID_8821C 0 +#define BIT_MASK_REF_MID_8821C 0x7f +#define BIT_REF_MID_8821C(x) (((x) & BIT_MASK_REF_MID_8821C) << BIT_SHIFT_REF_MID_8821C) +#define BIT_GET_REF_MID_8821C(x) (((x) >> BIT_SHIFT_REF_MID_8821C) & BIT_MASK_REF_MID_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_TC7_CTRL_V1_8821C */ +#define BIT_TC7INT_EN_8821C BIT(26) +#define BIT_TC7MODE_8821C BIT(25) +#define BIT_TC7EN_8821C BIT(24) + +#define BIT_SHIFT_TC7DATA_8821C 0 +#define BIT_MASK_TC7DATA_8821C 0xffffff +#define BIT_TC7DATA_8821C(x) (((x) & BIT_MASK_TC7DATA_8821C) << BIT_SHIFT_TC7DATA_8821C) +#define BIT_GET_TC7DATA_8821C(x) (((x) >> BIT_SHIFT_TC7DATA_8821C) & BIT_MASK_TC7DATA_8821C) + +/* 2 REG_TC8_CTRL_V1_8821C */ +#define BIT_TC8INT_EN_8821C BIT(26) +#define BIT_TC8MODE_8821C BIT(25) +#define BIT_TC8EN_8821C BIT(24) + +#define BIT_SHIFT_TC8DATA_8821C 0 +#define BIT_MASK_TC8DATA_8821C 0xffffff +#define BIT_TC8DATA_8821C(x) (((x) & BIT_MASK_TC8DATA_8821C) << BIT_SHIFT_TC8DATA_8821C) +#define BIT_GET_TC8DATA_8821C(x) (((x) >> BIT_SHIFT_TC8DATA_8821C) & BIT_MASK_TC8DATA_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_FT2IMR_8821C */ +#define BIT_FS_CLI3_RX_UAPSDMD1_EN_8821C BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_EN_8821C BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_EN_8821C BIT(29) +#define BIT_FS_CLI3_EOSP_INT_EN_8821C BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_EN_8821C BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_EN_8821C BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_EN_8821C BIT(25) +#define BIT_FS_CLI2_EOSP_INT_EN_8821C BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_EN_8821C BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_EN_8821C BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_EN_8821C BIT(21) +#define BIT_FS_CLI1_EOSP_INT_EN_8821C BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_EN_8821C BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_EN_8821C BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_EN_8821C BIT(17) +#define BIT_FS_CLI0_EOSP_INT_EN_8821C BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN_8821C BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN_8821C BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_EN_8821C BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_EN_8821C BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_EN_8821C BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_EN_8821C BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_EN_8821C BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_EN_8821C BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_EN_8821C BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_EN_8821C BIT(0) + +/* 2 REG_FT2ISR_8821C */ +#define BIT_FS_CLI3_RX_UAPSDMD1_INT_8821C BIT(31) +#define BIT_FS_CLI3_RX_UAPSDMD0_INT_8821C BIT(30) +#define BIT_FS_CLI3_TRIGGER_PKT_INT_8821C BIT(29) +#define BIT_FS_CLI3_EOSP_INT_8821C BIT(28) +#define BIT_FS_CLI2_RX_UAPSDMD1_INT_8821C BIT(27) +#define BIT_FS_CLI2_RX_UAPSDMD0_INT_8821C BIT(26) +#define BIT_FS_CLI2_TRIGGER_PKT_INT_8821C BIT(25) +#define BIT_FS_CLI2_EOSP_INT_8821C BIT(24) +#define BIT_FS_CLI1_RX_UAPSDMD1_INT_8821C BIT(23) +#define BIT_FS_CLI1_RX_UAPSDMD0_INT_8821C BIT(22) +#define BIT_FS_CLI1_TRIGGER_PKT_INT_8821C BIT(21) +#define BIT_FS_CLI1_EOSP_INT_8821C BIT(20) +#define BIT_FS_CLI0_RX_UAPSDMD1_INT_8821C BIT(19) +#define BIT_FS_CLI0_RX_UAPSDMD0_INT_8821C BIT(18) +#define BIT_FS_CLI0_TRIGGER_PKT_INT_8821C BIT(17) +#define BIT_FS_CLI0_EOSP_INT_8821C BIT(16) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT_8821C BIT(9) +#define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT_8821C BIT(8) +#define BIT_FS_CLI3_TX_NULL1_INT_8821C BIT(7) +#define BIT_FS_CLI3_TX_NULL0_INT_8821C BIT(6) +#define BIT_FS_CLI2_TX_NULL1_INT_8821C BIT(5) +#define BIT_FS_CLI2_TX_NULL0_INT_8821C BIT(4) +#define BIT_FS_CLI1_TX_NULL1_INT_8821C BIT(3) +#define BIT_FS_CLI1_TX_NULL0_INT_8821C BIT(2) +#define BIT_FS_CLI0_TX_NULL1_INT_8821C BIT(1) +#define BIT_FS_CLI0_TX_NULL0_INT_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_MSG2_8821C */ + +#define BIT_SHIFT_FW_MSG2_8821C 0 +#define BIT_MASK_FW_MSG2_8821C 0xffffffffL +#define BIT_FW_MSG2_8821C(x) (((x) & BIT_MASK_FW_MSG2_8821C) << BIT_SHIFT_FW_MSG2_8821C) +#define BIT_GET_FW_MSG2_8821C(x) (((x) >> BIT_SHIFT_FW_MSG2_8821C) & BIT_MASK_FW_MSG2_8821C) + +/* 2 REG_MSG3_8821C */ + +#define BIT_SHIFT_FW_MSG3_8821C 0 +#define BIT_MASK_FW_MSG3_8821C 0xffffffffL +#define BIT_FW_MSG3_8821C(x) (((x) & BIT_MASK_FW_MSG3_8821C) << BIT_SHIFT_FW_MSG3_8821C) +#define BIT_GET_FW_MSG3_8821C(x) (((x) >> BIT_SHIFT_FW_MSG3_8821C) & BIT_MASK_FW_MSG3_8821C) + +/* 2 REG_MSG4_8821C */ + +#define BIT_SHIFT_FW_MSG4_8821C 0 +#define BIT_MASK_FW_MSG4_8821C 0xffffffffL +#define BIT_FW_MSG4_8821C(x) (((x) & BIT_MASK_FW_MSG4_8821C) << BIT_SHIFT_FW_MSG4_8821C) +#define BIT_GET_FW_MSG4_8821C(x) (((x) >> BIT_SHIFT_FW_MSG4_8821C) & BIT_MASK_FW_MSG4_8821C) + +/* 2 REG_MSG5_8821C */ + +#define BIT_SHIFT_FW_MSG5_8821C 0 +#define BIT_MASK_FW_MSG5_8821C 0xffffffffL +#define BIT_FW_MSG5_8821C(x) (((x) & BIT_MASK_FW_MSG5_8821C) << BIT_SHIFT_FW_MSG5_8821C) +#define BIT_GET_FW_MSG5_8821C(x) (((x) >> BIT_SHIFT_FW_MSG5_8821C) & BIT_MASK_FW_MSG5_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_FIFOPAGE_CTRL_1_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C 16 +#define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C 0xff +#define BIT_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) +#define BIT_GET_TX_OQT_HE_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C 0 +#define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C 0xff +#define BIT_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) +#define BIT_GET_TX_OQT_NL_FREE_SPACE_V1_8821C(x) (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1_8821C) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1_8821C) + +/* 2 REG_FIFOPAGE_CTRL_2_8821C */ +#define BIT_BCN_VALID_1_V1_8821C BIT(31) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_BCN_HEAD_1_V1_8821C 16 +#define BIT_MASK_BCN_HEAD_1_V1_8821C 0xfff +#define BIT_BCN_HEAD_1_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_1_V1_8821C) << BIT_SHIFT_BCN_HEAD_1_V1_8821C) +#define BIT_GET_BCN_HEAD_1_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_1_V1_8821C) & BIT_MASK_BCN_HEAD_1_V1_8821C) + +#define BIT_BCN_VALID_V1_8821C BIT(15) + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_BCN_HEAD_V1_8821C 0 +#define BIT_MASK_BCN_HEAD_V1_8821C 0xfff +#define BIT_BCN_HEAD_V1_8821C(x) (((x) & BIT_MASK_BCN_HEAD_V1_8821C) << BIT_SHIFT_BCN_HEAD_V1_8821C) +#define BIT_GET_BCN_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_BCN_HEAD_V1_8821C) & BIT_MASK_BCN_HEAD_V1_8821C) + +/* 2 REG_AUTO_LLT_V1_8821C */ + +#define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 24 +#define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C 0xff +#define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) +#define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C(x) (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1_8821C) + +#define BIT_SHIFT_LLT_FREE_PAGE_V1_8821C 8 +#define BIT_MASK_LLT_FREE_PAGE_V1_8821C 0xffff +#define BIT_LLT_FREE_PAGE_V1_8821C(x) (((x) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) << BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) +#define BIT_GET_LLT_FREE_PAGE_V1_8821C(x) (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1_8821C) & BIT_MASK_LLT_FREE_PAGE_V1_8821C) + +#define BIT_SHIFT_BLK_DESC_NUM_8821C 4 +#define BIT_MASK_BLK_DESC_NUM_8821C 0xf +#define BIT_BLK_DESC_NUM_8821C(x) (((x) & BIT_MASK_BLK_DESC_NUM_8821C) << BIT_SHIFT_BLK_DESC_NUM_8821C) +#define BIT_GET_BLK_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BLK_DESC_NUM_8821C) & BIT_MASK_BLK_DESC_NUM_8821C) + +#define BIT_R_BCN_HEAD_SEL_8821C BIT(3) +#define BIT_R_EN_BCN_SW_HEAD_SEL_8821C BIT(2) +#define BIT_LLT_DBG_SEL_8821C BIT(1) +#define BIT_AUTO_INIT_LLT_V1_8821C BIT(0) + +/* 2 REG_TXDMA_OFFSET_CHK_8821C */ +#define BIT_EM_CHKSUM_FIN_8821C BIT(31) +#define BIT_EMN_PCIE_DMA_MOD_8821C BIT(30) +#define BIT_EN_TXQUE_CLR_8821C BIT(29) +#define BIT_EN_PCIE_FIFO_MODE_8821C BIT(28) + +#define BIT_SHIFT_PG_UNDER_TH_V1_8821C 16 +#define BIT_MASK_PG_UNDER_TH_V1_8821C 0xfff +#define BIT_PG_UNDER_TH_V1_8821C(x) (((x) & BIT_MASK_PG_UNDER_TH_V1_8821C) << BIT_SHIFT_PG_UNDER_TH_V1_8821C) +#define BIT_GET_PG_UNDER_TH_V1_8821C(x) (((x) >> BIT_SHIFT_PG_UNDER_TH_V1_8821C) & BIT_MASK_PG_UNDER_TH_V1_8821C) + +/* 2 REG_NOT_VALID_8821C */ +#define BIT_SDIO_TXDESC_CHKSUM_EN_8821C BIT(13) +#define BIT_RST_RDPTR_8821C BIT(12) +#define BIT_RST_WRPTR_8821C BIT(11) +#define BIT_CHK_PG_TH_EN_8821C BIT(10) +#define BIT_DROP_DATA_EN_8821C BIT(9) +#define BIT_CHECK_OFFSET_EN_8821C BIT(8) + +#define BIT_SHIFT_CHECK_OFFSET_8821C 0 +#define BIT_MASK_CHECK_OFFSET_8821C 0xff +#define BIT_CHECK_OFFSET_8821C(x) (((x) & BIT_MASK_CHECK_OFFSET_8821C) << BIT_SHIFT_CHECK_OFFSET_8821C) +#define BIT_GET_CHECK_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CHECK_OFFSET_8821C) & BIT_MASK_CHECK_OFFSET_8821C) + +/* 2 REG_TXDMA_STATUS_8821C */ +#define BIT_TXPKTBUF_REQ_ERR_8821C BIT(18) +#define BIT_HI_OQT_UDN_8821C BIT(17) +#define BIT_HI_OQT_OVF_8821C BIT(16) +#define BIT_PAYLOAD_CHKSUM_ERR_8821C BIT(15) +#define BIT_PAYLOAD_UDN_8821C BIT(14) +#define BIT_PAYLOAD_OVF_8821C BIT(13) +#define BIT_DSC_CHKSUM_FAIL_8821C BIT(12) +#define BIT_UNKNOWN_QSEL_8821C BIT(11) +#define BIT_EP_QSEL_DIFF_8821C BIT(10) +#define BIT_TX_OFFS_UNMATCH_8821C BIT(9) +#define BIT_TXOQT_UDN_8821C BIT(8) +#define BIT_TXOQT_OVF_8821C BIT(7) +#define BIT_TXDMA_SFF_UDN_8821C BIT(6) +#define BIT_TXDMA_SFF_OVF_8821C BIT(5) +#define BIT_LLT_NULL_PG_8821C BIT(4) +#define BIT_PAGE_UDN_8821C BIT(3) +#define BIT_PAGE_OVF_8821C BIT(2) +#define BIT_TXFF_PG_UDN_8821C BIT(1) +#define BIT_TXFF_PG_OVF_8821C BIT(0) + +/* 2 REG_TX_DMA_DBG_8821C */ + +/* 2 REG_TQPNT1_8821C */ + +#define BIT_SHIFT_HPQ_HIGH_TH_V1_8821C 16 +#define BIT_MASK_HPQ_HIGH_TH_V1_8821C 0xfff +#define BIT_HPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) +#define BIT_GET_HPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1_8821C) & BIT_MASK_HPQ_HIGH_TH_V1_8821C) + +#define BIT_SHIFT_HPQ_LOW_TH_V1_8821C 0 +#define BIT_MASK_HPQ_LOW_TH_V1_8821C 0xfff +#define BIT_HPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_HPQ_LOW_TH_V1_8821C) << BIT_SHIFT_HPQ_LOW_TH_V1_8821C) +#define BIT_GET_HPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1_8821C) & BIT_MASK_HPQ_LOW_TH_V1_8821C) + +/* 2 REG_TQPNT2_8821C */ + +#define BIT_SHIFT_NPQ_HIGH_TH_V1_8821C 16 +#define BIT_MASK_NPQ_HIGH_TH_V1_8821C 0xfff +#define BIT_NPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) +#define BIT_GET_NPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1_8821C) & BIT_MASK_NPQ_HIGH_TH_V1_8821C) + +#define BIT_SHIFT_NPQ_LOW_TH_V1_8821C 0 +#define BIT_MASK_NPQ_LOW_TH_V1_8821C 0xfff +#define BIT_NPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_NPQ_LOW_TH_V1_8821C) << BIT_SHIFT_NPQ_LOW_TH_V1_8821C) +#define BIT_GET_NPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1_8821C) & BIT_MASK_NPQ_LOW_TH_V1_8821C) + +/* 2 REG_TQPNT3_8821C */ + +#define BIT_SHIFT_LPQ_HIGH_TH_V1_8821C 16 +#define BIT_MASK_LPQ_HIGH_TH_V1_8821C 0xfff +#define BIT_LPQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) << BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) +#define BIT_GET_LPQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1_8821C) & BIT_MASK_LPQ_HIGH_TH_V1_8821C) + +#define BIT_SHIFT_LPQ_LOW_TH_V1_8821C 0 +#define BIT_MASK_LPQ_LOW_TH_V1_8821C 0xfff +#define BIT_LPQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_LPQ_LOW_TH_V1_8821C) << BIT_SHIFT_LPQ_LOW_TH_V1_8821C) +#define BIT_GET_LPQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1_8821C) & BIT_MASK_LPQ_LOW_TH_V1_8821C) + +/* 2 REG_TQPNT4_8821C */ + +#define BIT_SHIFT_EXQ_HIGH_TH_V1_8821C 16 +#define BIT_MASK_EXQ_HIGH_TH_V1_8821C 0xfff +#define BIT_EXQ_HIGH_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) << BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) +#define BIT_GET_EXQ_HIGH_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1_8821C) & BIT_MASK_EXQ_HIGH_TH_V1_8821C) + +#define BIT_SHIFT_EXQ_LOW_TH_V1_8821C 0 +#define BIT_MASK_EXQ_LOW_TH_V1_8821C 0xfff +#define BIT_EXQ_LOW_TH_V1_8821C(x) (((x) & BIT_MASK_EXQ_LOW_TH_V1_8821C) << BIT_SHIFT_EXQ_LOW_TH_V1_8821C) +#define BIT_GET_EXQ_LOW_TH_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1_8821C) & BIT_MASK_EXQ_LOW_TH_V1_8821C) + +/* 2 REG_RQPN_CTRL_1_8821C */ + +#define BIT_SHIFT_TXPKTNUM_H_8821C 16 +#define BIT_MASK_TXPKTNUM_H_8821C 0xffff +#define BIT_TXPKTNUM_H_8821C(x) (((x) & BIT_MASK_TXPKTNUM_H_8821C) << BIT_SHIFT_TXPKTNUM_H_8821C) +#define BIT_GET_TXPKTNUM_H_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_H_8821C) & BIT_MASK_TXPKTNUM_H_8821C) + +#define BIT_SHIFT_TXPKTNUM_V2_8821C 0 +#define BIT_MASK_TXPKTNUM_V2_8821C 0xffff +#define BIT_TXPKTNUM_V2_8821C(x) (((x) & BIT_MASK_TXPKTNUM_V2_8821C) << BIT_SHIFT_TXPKTNUM_V2_8821C) +#define BIT_GET_TXPKTNUM_V2_8821C(x) (((x) >> BIT_SHIFT_TXPKTNUM_V2_8821C) & BIT_MASK_TXPKTNUM_V2_8821C) + +/* 2 REG_RQPN_CTRL_2_8821C */ +#define BIT_LD_RQPN_8821C BIT(31) +#define BIT_EXQ_PUBLIC_DIS_V1_8821C BIT(19) +#define BIT_NPQ_PUBLIC_DIS_V1_8821C BIT(18) +#define BIT_LPQ_PUBLIC_DIS_V1_8821C BIT(17) +#define BIT_HPQ_PUBLIC_DIS_V1_8821C BIT(16) +#define BIT_SDIO_TXAGG_ALIGN_ADJUST_EN_8821C BIT(15) + +#define BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C 0 +#define BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C 0xfff +#define BIT_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) << BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) +#define BIT_GET_SDIO_TXAGG_ALIGN_SIZE_8821C(x) (((x) >> BIT_SHIFT_SDIO_TXAGG_ALIGN_SIZE_8821C) & BIT_MASK_SDIO_TXAGG_ALIGN_SIZE_8821C) + +/* 2 REG_FIFOPAGE_INFO_1_8821C */ + +#define BIT_SHIFT_HPQ_AVAL_PG_V1_8821C 16 +#define BIT_MASK_HPQ_AVAL_PG_V1_8821C 0xfff +#define BIT_HPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) +#define BIT_GET_HPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1_8821C) & BIT_MASK_HPQ_AVAL_PG_V1_8821C) + +#define BIT_SHIFT_HPQ_V1_8821C 0 +#define BIT_MASK_HPQ_V1_8821C 0xfff +#define BIT_HPQ_V1_8821C(x) (((x) & BIT_MASK_HPQ_V1_8821C) << BIT_SHIFT_HPQ_V1_8821C) +#define BIT_GET_HPQ_V1_8821C(x) (((x) >> BIT_SHIFT_HPQ_V1_8821C) & BIT_MASK_HPQ_V1_8821C) + +/* 2 REG_FIFOPAGE_INFO_2_8821C */ + +#define BIT_SHIFT_LPQ_AVAL_PG_V1_8821C 16 +#define BIT_MASK_LPQ_AVAL_PG_V1_8821C 0xfff +#define BIT_LPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) +#define BIT_GET_LPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1_8821C) & BIT_MASK_LPQ_AVAL_PG_V1_8821C) + +#define BIT_SHIFT_LPQ_V1_8821C 0 +#define BIT_MASK_LPQ_V1_8821C 0xfff +#define BIT_LPQ_V1_8821C(x) (((x) & BIT_MASK_LPQ_V1_8821C) << BIT_SHIFT_LPQ_V1_8821C) +#define BIT_GET_LPQ_V1_8821C(x) (((x) >> BIT_SHIFT_LPQ_V1_8821C) & BIT_MASK_LPQ_V1_8821C) + +/* 2 REG_FIFOPAGE_INFO_3_8821C */ + +#define BIT_SHIFT_NPQ_AVAL_PG_V1_8821C 16 +#define BIT_MASK_NPQ_AVAL_PG_V1_8821C 0xfff +#define BIT_NPQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) << BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) +#define BIT_GET_NPQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1_8821C) & BIT_MASK_NPQ_AVAL_PG_V1_8821C) + +#define BIT_SHIFT_NPQ_V1_8821C 0 +#define BIT_MASK_NPQ_V1_8821C 0xfff +#define BIT_NPQ_V1_8821C(x) (((x) & BIT_MASK_NPQ_V1_8821C) << BIT_SHIFT_NPQ_V1_8821C) +#define BIT_GET_NPQ_V1_8821C(x) (((x) >> BIT_SHIFT_NPQ_V1_8821C) & BIT_MASK_NPQ_V1_8821C) + +/* 2 REG_FIFOPAGE_INFO_4_8821C */ + +#define BIT_SHIFT_EXQ_AVAL_PG_V1_8821C 16 +#define BIT_MASK_EXQ_AVAL_PG_V1_8821C 0xfff +#define BIT_EXQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) << BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) +#define BIT_GET_EXQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1_8821C) & BIT_MASK_EXQ_AVAL_PG_V1_8821C) + +#define BIT_SHIFT_EXQ_V1_8821C 0 +#define BIT_MASK_EXQ_V1_8821C 0xfff +#define BIT_EXQ_V1_8821C(x) (((x) & BIT_MASK_EXQ_V1_8821C) << BIT_SHIFT_EXQ_V1_8821C) +#define BIT_GET_EXQ_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_V1_8821C) & BIT_MASK_EXQ_V1_8821C) + +/* 2 REG_FIFOPAGE_INFO_5_8821C */ + +#define BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C 16 +#define BIT_MASK_PUBQ_AVAL_PG_V1_8821C 0xfff +#define BIT_PUBQ_AVAL_PG_V1_8821C(x) (((x) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) << BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) +#define BIT_GET_PUBQ_AVAL_PG_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1_8821C) & BIT_MASK_PUBQ_AVAL_PG_V1_8821C) + +#define BIT_SHIFT_PUBQ_V1_8821C 0 +#define BIT_MASK_PUBQ_V1_8821C 0xfff +#define BIT_PUBQ_V1_8821C(x) (((x) & BIT_MASK_PUBQ_V1_8821C) << BIT_SHIFT_PUBQ_V1_8821C) +#define BIT_GET_PUBQ_V1_8821C(x) (((x) >> BIT_SHIFT_PUBQ_V1_8821C) & BIT_MASK_PUBQ_V1_8821C) + +/* 2 REG_H2C_HEAD_8821C */ + +#define BIT_SHIFT_H2C_HEAD_8821C 0 +#define BIT_MASK_H2C_HEAD_8821C 0x3ffff +#define BIT_H2C_HEAD_8821C(x) (((x) & BIT_MASK_H2C_HEAD_8821C) << BIT_SHIFT_H2C_HEAD_8821C) +#define BIT_GET_H2C_HEAD_8821C(x) (((x) >> BIT_SHIFT_H2C_HEAD_8821C) & BIT_MASK_H2C_HEAD_8821C) + +/* 2 REG_H2C_TAIL_8821C */ + +#define BIT_SHIFT_H2C_TAIL_8821C 0 +#define BIT_MASK_H2C_TAIL_8821C 0x3ffff +#define BIT_H2C_TAIL_8821C(x) (((x) & BIT_MASK_H2C_TAIL_8821C) << BIT_SHIFT_H2C_TAIL_8821C) +#define BIT_GET_H2C_TAIL_8821C(x) (((x) >> BIT_SHIFT_H2C_TAIL_8821C) & BIT_MASK_H2C_TAIL_8821C) + +/* 2 REG_H2C_READ_ADDR_8821C */ + +#define BIT_SHIFT_H2C_READ_ADDR_8821C 0 +#define BIT_MASK_H2C_READ_ADDR_8821C 0x3ffff +#define BIT_H2C_READ_ADDR_8821C(x) (((x) & BIT_MASK_H2C_READ_ADDR_8821C) << BIT_SHIFT_H2C_READ_ADDR_8821C) +#define BIT_GET_H2C_READ_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_READ_ADDR_8821C) & BIT_MASK_H2C_READ_ADDR_8821C) + +/* 2 REG_H2C_WR_ADDR_8821C */ + +#define BIT_SHIFT_H2C_WR_ADDR_8821C 0 +#define BIT_MASK_H2C_WR_ADDR_8821C 0x3ffff +#define BIT_H2C_WR_ADDR_8821C(x) (((x) & BIT_MASK_H2C_WR_ADDR_8821C) << BIT_SHIFT_H2C_WR_ADDR_8821C) +#define BIT_GET_H2C_WR_ADDR_8821C(x) (((x) >> BIT_SHIFT_H2C_WR_ADDR_8821C) & BIT_MASK_H2C_WR_ADDR_8821C) + +/* 2 REG_H2C_INFO_8821C */ +#define BIT_H2C_SPACE_VLD_8821C BIT(3) +#define BIT_H2C_WR_ADDR_RST_8821C BIT(2) + +#define BIT_SHIFT_H2C_LEN_SEL_8821C 0 +#define BIT_MASK_H2C_LEN_SEL_8821C 0x3 +#define BIT_H2C_LEN_SEL_8821C(x) (((x) & BIT_MASK_H2C_LEN_SEL_8821C) << BIT_SHIFT_H2C_LEN_SEL_8821C) +#define BIT_GET_H2C_LEN_SEL_8821C(x) (((x) >> BIT_SHIFT_H2C_LEN_SEL_8821C) & BIT_MASK_H2C_LEN_SEL_8821C) + +/* 2 REG_RXDMA_AGG_PG_TH_8821C */ + +#define BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C 24 +#define BIT_MASK_RXDMA_AGG_OLD_MOD_8821C 0xff +#define BIT_RXDMA_AGG_OLD_MOD_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) << BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) +#define BIT_GET_RXDMA_AGG_OLD_MOD_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD_8821C) & BIT_MASK_RXDMA_AGG_OLD_MOD_8821C) + +#define BIT_SHIFT_PKT_NUM_WOL_8821C 16 +#define BIT_MASK_PKT_NUM_WOL_8821C 0xff +#define BIT_PKT_NUM_WOL_8821C(x) (((x) & BIT_MASK_PKT_NUM_WOL_8821C) << BIT_SHIFT_PKT_NUM_WOL_8821C) +#define BIT_GET_PKT_NUM_WOL_8821C(x) (((x) >> BIT_SHIFT_PKT_NUM_WOL_8821C) & BIT_MASK_PKT_NUM_WOL_8821C) + +#define BIT_SHIFT_DMA_AGG_TO_8821C 8 +#define BIT_MASK_DMA_AGG_TO_8821C 0xf +#define BIT_DMA_AGG_TO_8821C(x) (((x) & BIT_MASK_DMA_AGG_TO_8821C) << BIT_SHIFT_DMA_AGG_TO_8821C) +#define BIT_GET_DMA_AGG_TO_8821C(x) (((x) >> BIT_SHIFT_DMA_AGG_TO_8821C) & BIT_MASK_DMA_AGG_TO_8821C) + +#define BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C 0 +#define BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C 0xf +#define BIT_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) +#define BIT_GET_RXDMA_AGG_PG_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1_8821C) & BIT_MASK_RXDMA_AGG_PG_TH_V1_8821C) + +/* 2 REG_RXPKT_NUM_8821C */ + +#define BIT_SHIFT_RXPKT_NUM_8821C 24 +#define BIT_MASK_RXPKT_NUM_8821C 0xff +#define BIT_RXPKT_NUM_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_8821C) << BIT_SHIFT_RXPKT_NUM_8821C) +#define BIT_GET_RXPKT_NUM_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_8821C) & BIT_MASK_RXPKT_NUM_8821C) + +#define BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C 20 +#define BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C 0xf +#define BIT_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) << BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) +#define BIT_GET_FW_UPD_RDPTR19_TO_16_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16_8821C) & BIT_MASK_FW_UPD_RDPTR19_TO_16_8821C) + +#define BIT_RXDMA_REQ_8821C BIT(19) +#define BIT_RW_RELEASE_EN_8821C BIT(18) +#define BIT_RXDMA_IDLE_8821C BIT(17) +#define BIT_RXPKT_RELEASE_POLL_8821C BIT(16) + +#define BIT_SHIFT_FW_UPD_RDPTR_8821C 0 +#define BIT_MASK_FW_UPD_RDPTR_8821C 0xffff +#define BIT_FW_UPD_RDPTR_8821C(x) (((x) & BIT_MASK_FW_UPD_RDPTR_8821C) << BIT_SHIFT_FW_UPD_RDPTR_8821C) +#define BIT_GET_FW_UPD_RDPTR_8821C(x) (((x) >> BIT_SHIFT_FW_UPD_RDPTR_8821C) & BIT_MASK_FW_UPD_RDPTR_8821C) + +/* 2 REG_RXDMA_STATUS_8821C */ +#define BIT_C2H_PKT_OVF_8821C BIT(7) +#define BIT_AGG_CONFGI_ISSUE_8821C BIT(6) +#define BIT_FW_POLL_ISSUE_8821C BIT(5) +#define BIT_RX_DATA_UDN_8821C BIT(4) +#define BIT_RX_SFF_UDN_8821C BIT(3) +#define BIT_RX_SFF_OVF_8821C BIT(2) +#define BIT_RXPKT_OVF_8821C BIT(0) + +/* 2 REG_RXDMA_DPR_8821C */ + +#define BIT_SHIFT_RDE_DEBUG_8821C 0 +#define BIT_MASK_RDE_DEBUG_8821C 0xffffffffL +#define BIT_RDE_DEBUG_8821C(x) (((x) & BIT_MASK_RDE_DEBUG_8821C) << BIT_SHIFT_RDE_DEBUG_8821C) +#define BIT_GET_RDE_DEBUG_8821C(x) (((x) >> BIT_SHIFT_RDE_DEBUG_8821C) & BIT_MASK_RDE_DEBUG_8821C) + +/* 2 REG_RXDMA_MODE_8821C */ + +#define BIT_SHIFT_PKTNUM_TH_V2_8821C 24 +#define BIT_MASK_PKTNUM_TH_V2_8821C 0x1f +#define BIT_PKTNUM_TH_V2_8821C(x) (((x) & BIT_MASK_PKTNUM_TH_V2_8821C) << BIT_SHIFT_PKTNUM_TH_V2_8821C) +#define BIT_GET_PKTNUM_TH_V2_8821C(x) (((x) >> BIT_SHIFT_PKTNUM_TH_V2_8821C) & BIT_MASK_PKTNUM_TH_V2_8821C) + +#define BIT_TXBA_BREAK_USBAGG_8821C BIT(23) + +#define BIT_SHIFT_PKTLEN_PARA_8821C 16 +#define BIT_MASK_PKTLEN_PARA_8821C 0x7 +#define BIT_PKTLEN_PARA_8821C(x) (((x) & BIT_MASK_PKTLEN_PARA_8821C) << BIT_SHIFT_PKTLEN_PARA_8821C) +#define BIT_GET_PKTLEN_PARA_8821C(x) (((x) >> BIT_SHIFT_PKTLEN_PARA_8821C) & BIT_MASK_PKTLEN_PARA_8821C) + +#define BIT_SHIFT_BURST_SIZE_8821C 4 +#define BIT_MASK_BURST_SIZE_8821C 0x3 +#define BIT_BURST_SIZE_8821C(x) (((x) & BIT_MASK_BURST_SIZE_8821C) << BIT_SHIFT_BURST_SIZE_8821C) +#define BIT_GET_BURST_SIZE_8821C(x) (((x) >> BIT_SHIFT_BURST_SIZE_8821C) & BIT_MASK_BURST_SIZE_8821C) + +#define BIT_SHIFT_BURST_CNT_8821C 2 +#define BIT_MASK_BURST_CNT_8821C 0x3 +#define BIT_BURST_CNT_8821C(x) (((x) & BIT_MASK_BURST_CNT_8821C) << BIT_SHIFT_BURST_CNT_8821C) +#define BIT_GET_BURST_CNT_8821C(x) (((x) >> BIT_SHIFT_BURST_CNT_8821C) & BIT_MASK_BURST_CNT_8821C) + +#define BIT_DMA_MODE_8821C BIT(1) + +/* 2 REG_C2H_PKT_8821C */ + +#define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C 24 +#define BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C 0xf +#define BIT_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) +#define BIT_GET_R_C2H_STR_ADDR_16_TO_19_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19_8821C) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19_8821C) + +#define BIT_R_C2H_PKT_REQ_8821C BIT(16) + +#define BIT_SHIFT_R_C2H_STR_ADDR_8821C 0 +#define BIT_MASK_R_C2H_STR_ADDR_8821C 0xffff +#define BIT_R_C2H_STR_ADDR_8821C(x) (((x) & BIT_MASK_R_C2H_STR_ADDR_8821C) << BIT_SHIFT_R_C2H_STR_ADDR_8821C) +#define BIT_GET_R_C2H_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_8821C) & BIT_MASK_R_C2H_STR_ADDR_8821C) + +/* 2 REG_FWFF_C2H_8821C */ + +#define BIT_SHIFT_C2H_DMA_ADDR_8821C 0 +#define BIT_MASK_C2H_DMA_ADDR_8821C 0x3ffff +#define BIT_C2H_DMA_ADDR_8821C(x) (((x) & BIT_MASK_C2H_DMA_ADDR_8821C) << BIT_SHIFT_C2H_DMA_ADDR_8821C) +#define BIT_GET_C2H_DMA_ADDR_8821C(x) (((x) >> BIT_SHIFT_C2H_DMA_ADDR_8821C) & BIT_MASK_C2H_DMA_ADDR_8821C) + +/* 2 REG_FWFF_CTRL_8821C */ +#define BIT_FWFF_DMAPKT_REQ_8821C BIT(31) + +#define BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C 16 +#define BIT_MASK_FWFF_DMA_PKT_NUM_8821C 0xff +#define BIT_FWFF_DMA_PKT_NUM_8821C(x) (((x) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) << BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) +#define BIT_GET_FWFF_DMA_PKT_NUM_8821C(x) (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM_8821C) & BIT_MASK_FWFF_DMA_PKT_NUM_8821C) + +#define BIT_SHIFT_FWFF_STR_ADDR_8821C 0 +#define BIT_MASK_FWFF_STR_ADDR_8821C 0xffff +#define BIT_FWFF_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_STR_ADDR_8821C) << BIT_SHIFT_FWFF_STR_ADDR_8821C) +#define BIT_GET_FWFF_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_STR_ADDR_8821C) & BIT_MASK_FWFF_STR_ADDR_8821C) + +/* 2 REG_FWFF_PKT_INFO_8821C */ + +#define BIT_SHIFT_FWFF_PKT_QUEUED_8821C 16 +#define BIT_MASK_FWFF_PKT_QUEUED_8821C 0xff +#define BIT_FWFF_PKT_QUEUED_8821C(x) (((x) & BIT_MASK_FWFF_PKT_QUEUED_8821C) << BIT_SHIFT_FWFF_PKT_QUEUED_8821C) +#define BIT_GET_FWFF_PKT_QUEUED_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED_8821C) & BIT_MASK_FWFF_PKT_QUEUED_8821C) + +#define BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C 0 +#define BIT_MASK_FWFF_PKT_STR_ADDR_8821C 0xffff +#define BIT_FWFF_PKT_STR_ADDR_8821C(x) (((x) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) << BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) +#define BIT_GET_FWFF_PKT_STR_ADDR_8821C(x) (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR_8821C) & BIT_MASK_FWFF_PKT_STR_ADDR_8821C) + +/* 2 REG_DDMA_CH0SA_8821C */ + +#define BIT_SHIFT_DDMACH0_SA_8821C 0 +#define BIT_MASK_DDMACH0_SA_8821C 0xffffffffL +#define BIT_DDMACH0_SA_8821C(x) (((x) & BIT_MASK_DDMACH0_SA_8821C) << BIT_SHIFT_DDMACH0_SA_8821C) +#define BIT_GET_DDMACH0_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_SA_8821C) & BIT_MASK_DDMACH0_SA_8821C) + +/* 2 REG_DDMA_CH0DA_8821C */ + +#define BIT_SHIFT_DDMACH0_DA_8821C 0 +#define BIT_MASK_DDMACH0_DA_8821C 0xffffffffL +#define BIT_DDMACH0_DA_8821C(x) (((x) & BIT_MASK_DDMACH0_DA_8821C) << BIT_SHIFT_DDMACH0_DA_8821C) +#define BIT_GET_DDMACH0_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DA_8821C) & BIT_MASK_DDMACH0_DA_8821C) + +/* 2 REG_DDMA_CH0CTRL_8821C */ +#define BIT_DDMACH0_OWN_8821C BIT(31) +#define BIT_DDMACH0_CHKSUM_EN_8821C BIT(29) +#define BIT_DDMACH0_DA_W_DISABLE_8821C BIT(28) +#define BIT_DDMACH0_CHKSUM_STS_8821C BIT(27) +#define BIT_DDMACH0_DDMA_MODE_8821C BIT(26) +#define BIT_DDMACH0_RESET_CHKSUM_STS_8821C BIT(25) +#define BIT_DDMACH0_CHKSUM_CONT_8821C BIT(24) + +#define BIT_SHIFT_DDMACH0_DLEN_8821C 0 +#define BIT_MASK_DDMACH0_DLEN_8821C 0x3ffff +#define BIT_DDMACH0_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH0_DLEN_8821C) << BIT_SHIFT_DDMACH0_DLEN_8821C) +#define BIT_GET_DDMACH0_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH0_DLEN_8821C) & BIT_MASK_DDMACH0_DLEN_8821C) + +/* 2 REG_DDMA_CH1SA_8821C */ + +#define BIT_SHIFT_DDMACH1_SA_8821C 0 +#define BIT_MASK_DDMACH1_SA_8821C 0xffffffffL +#define BIT_DDMACH1_SA_8821C(x) (((x) & BIT_MASK_DDMACH1_SA_8821C) << BIT_SHIFT_DDMACH1_SA_8821C) +#define BIT_GET_DDMACH1_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_SA_8821C) & BIT_MASK_DDMACH1_SA_8821C) + +/* 2 REG_DDMA_CH1DA_8821C */ + +#define BIT_SHIFT_DDMACH1_DA_8821C 0 +#define BIT_MASK_DDMACH1_DA_8821C 0xffffffffL +#define BIT_DDMACH1_DA_8821C(x) (((x) & BIT_MASK_DDMACH1_DA_8821C) << BIT_SHIFT_DDMACH1_DA_8821C) +#define BIT_GET_DDMACH1_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DA_8821C) & BIT_MASK_DDMACH1_DA_8821C) + +/* 2 REG_DDMA_CH1CTRL_8821C */ +#define BIT_DDMACH1_OWN_8821C BIT(31) +#define BIT_DDMACH1_CHKSUM_EN_8821C BIT(29) +#define BIT_DDMACH1_DA_W_DISABLE_8821C BIT(28) +#define BIT_DDMACH1_CHKSUM_STS_8821C BIT(27) +#define BIT_DDMACH1_DDMA_MODE_8821C BIT(26) +#define BIT_DDMACH1_RESET_CHKSUM_STS_8821C BIT(25) +#define BIT_DDMACH1_CHKSUM_CONT_8821C BIT(24) + +#define BIT_SHIFT_DDMACH1_DLEN_8821C 0 +#define BIT_MASK_DDMACH1_DLEN_8821C 0x3ffff +#define BIT_DDMACH1_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH1_DLEN_8821C) << BIT_SHIFT_DDMACH1_DLEN_8821C) +#define BIT_GET_DDMACH1_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH1_DLEN_8821C) & BIT_MASK_DDMACH1_DLEN_8821C) + +/* 2 REG_DDMA_CH2SA_8821C */ + +#define BIT_SHIFT_DDMACH2_SA_8821C 0 +#define BIT_MASK_DDMACH2_SA_8821C 0xffffffffL +#define BIT_DDMACH2_SA_8821C(x) (((x) & BIT_MASK_DDMACH2_SA_8821C) << BIT_SHIFT_DDMACH2_SA_8821C) +#define BIT_GET_DDMACH2_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_SA_8821C) & BIT_MASK_DDMACH2_SA_8821C) + +/* 2 REG_DDMA_CH2DA_8821C */ + +#define BIT_SHIFT_DDMACH2_DA_8821C 0 +#define BIT_MASK_DDMACH2_DA_8821C 0xffffffffL +#define BIT_DDMACH2_DA_8821C(x) (((x) & BIT_MASK_DDMACH2_DA_8821C) << BIT_SHIFT_DDMACH2_DA_8821C) +#define BIT_GET_DDMACH2_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DA_8821C) & BIT_MASK_DDMACH2_DA_8821C) + +/* 2 REG_DDMA_CH2CTRL_8821C */ +#define BIT_DDMACH2_OWN_8821C BIT(31) +#define BIT_DDMACH2_CHKSUM_EN_8821C BIT(29) +#define BIT_DDMACH2_DA_W_DISABLE_8821C BIT(28) +#define BIT_DDMACH2_CHKSUM_STS_8821C BIT(27) +#define BIT_DDMACH2_DDMA_MODE_8821C BIT(26) +#define BIT_DDMACH2_RESET_CHKSUM_STS_8821C BIT(25) +#define BIT_DDMACH2_CHKSUM_CONT_8821C BIT(24) + +#define BIT_SHIFT_DDMACH2_DLEN_8821C 0 +#define BIT_MASK_DDMACH2_DLEN_8821C 0x3ffff +#define BIT_DDMACH2_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH2_DLEN_8821C) << BIT_SHIFT_DDMACH2_DLEN_8821C) +#define BIT_GET_DDMACH2_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH2_DLEN_8821C) & BIT_MASK_DDMACH2_DLEN_8821C) + +/* 2 REG_DDMA_CH3SA_8821C */ + +#define BIT_SHIFT_DDMACH3_SA_8821C 0 +#define BIT_MASK_DDMACH3_SA_8821C 0xffffffffL +#define BIT_DDMACH3_SA_8821C(x) (((x) & BIT_MASK_DDMACH3_SA_8821C) << BIT_SHIFT_DDMACH3_SA_8821C) +#define BIT_GET_DDMACH3_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_SA_8821C) & BIT_MASK_DDMACH3_SA_8821C) + +/* 2 REG_DDMA_CH3DA_8821C */ + +#define BIT_SHIFT_DDMACH3_DA_8821C 0 +#define BIT_MASK_DDMACH3_DA_8821C 0xffffffffL +#define BIT_DDMACH3_DA_8821C(x) (((x) & BIT_MASK_DDMACH3_DA_8821C) << BIT_SHIFT_DDMACH3_DA_8821C) +#define BIT_GET_DDMACH3_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DA_8821C) & BIT_MASK_DDMACH3_DA_8821C) + +/* 2 REG_DDMA_CH3CTRL_8821C */ +#define BIT_DDMACH3_OWN_8821C BIT(31) +#define BIT_DDMACH3_CHKSUM_EN_8821C BIT(29) +#define BIT_DDMACH3_DA_W_DISABLE_8821C BIT(28) +#define BIT_DDMACH3_CHKSUM_STS_8821C BIT(27) +#define BIT_DDMACH3_DDMA_MODE_8821C BIT(26) +#define BIT_DDMACH3_RESET_CHKSUM_STS_8821C BIT(25) +#define BIT_DDMACH3_CHKSUM_CONT_8821C BIT(24) + +#define BIT_SHIFT_DDMACH3_DLEN_8821C 0 +#define BIT_MASK_DDMACH3_DLEN_8821C 0x3ffff +#define BIT_DDMACH3_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH3_DLEN_8821C) << BIT_SHIFT_DDMACH3_DLEN_8821C) +#define BIT_GET_DDMACH3_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH3_DLEN_8821C) & BIT_MASK_DDMACH3_DLEN_8821C) + +/* 2 REG_DDMA_CH4SA_8821C */ + +#define BIT_SHIFT_DDMACH4_SA_8821C 0 +#define BIT_MASK_DDMACH4_SA_8821C 0xffffffffL +#define BIT_DDMACH4_SA_8821C(x) (((x) & BIT_MASK_DDMACH4_SA_8821C) << BIT_SHIFT_DDMACH4_SA_8821C) +#define BIT_GET_DDMACH4_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_SA_8821C) & BIT_MASK_DDMACH4_SA_8821C) + +/* 2 REG_DDMA_CH4DA_8821C */ + +#define BIT_SHIFT_DDMACH4_DA_8821C 0 +#define BIT_MASK_DDMACH4_DA_8821C 0xffffffffL +#define BIT_DDMACH4_DA_8821C(x) (((x) & BIT_MASK_DDMACH4_DA_8821C) << BIT_SHIFT_DDMACH4_DA_8821C) +#define BIT_GET_DDMACH4_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DA_8821C) & BIT_MASK_DDMACH4_DA_8821C) + +/* 2 REG_DDMA_CH4CTRL_8821C */ +#define BIT_DDMACH4_OWN_8821C BIT(31) +#define BIT_DDMACH4_CHKSUM_EN_8821C BIT(29) +#define BIT_DDMACH4_DA_W_DISABLE_8821C BIT(28) +#define BIT_DDMACH4_CHKSUM_STS_8821C BIT(27) +#define BIT_DDMACH4_DDMA_MODE_8821C BIT(26) +#define BIT_DDMACH4_RESET_CHKSUM_STS_8821C BIT(25) +#define BIT_DDMACH4_CHKSUM_CONT_8821C BIT(24) + +#define BIT_SHIFT_DDMACH4_DLEN_8821C 0 +#define BIT_MASK_DDMACH4_DLEN_8821C 0x3ffff +#define BIT_DDMACH4_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH4_DLEN_8821C) << BIT_SHIFT_DDMACH4_DLEN_8821C) +#define BIT_GET_DDMACH4_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH4_DLEN_8821C) & BIT_MASK_DDMACH4_DLEN_8821C) + +/* 2 REG_DDMA_CH5SA_8821C */ + +#define BIT_SHIFT_DDMACH5_SA_8821C 0 +#define BIT_MASK_DDMACH5_SA_8821C 0xffffffffL +#define BIT_DDMACH5_SA_8821C(x) (((x) & BIT_MASK_DDMACH5_SA_8821C) << BIT_SHIFT_DDMACH5_SA_8821C) +#define BIT_GET_DDMACH5_SA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_SA_8821C) & BIT_MASK_DDMACH5_SA_8821C) + +/* 2 REG_DDMA_CH5DA_8821C */ + +#define BIT_SHIFT_DDMACH5_DA_8821C 0 +#define BIT_MASK_DDMACH5_DA_8821C 0xffffffffL +#define BIT_DDMACH5_DA_8821C(x) (((x) & BIT_MASK_DDMACH5_DA_8821C) << BIT_SHIFT_DDMACH5_DA_8821C) +#define BIT_GET_DDMACH5_DA_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DA_8821C) & BIT_MASK_DDMACH5_DA_8821C) + +/* 2 REG_DDMA_CH5CTRL_8821C */ +#define BIT_DDMACH5_OWN_8821C BIT(31) +#define BIT_DDMACH5_CHKSUM_EN_8821C BIT(29) +#define BIT_DDMACH5_DA_W_DISABLE_8821C BIT(28) +#define BIT_DDMACH5_CHKSUM_STS_8821C BIT(27) +#define BIT_DDMACH5_DDMA_MODE_8821C BIT(26) +#define BIT_DDMACH5_RESET_CHKSUM_STS_8821C BIT(25) +#define BIT_DDMACH5_CHKSUM_CONT_8821C BIT(24) + +#define BIT_SHIFT_DDMACH5_DLEN_8821C 0 +#define BIT_MASK_DDMACH5_DLEN_8821C 0x3ffff +#define BIT_DDMACH5_DLEN_8821C(x) (((x) & BIT_MASK_DDMACH5_DLEN_8821C) << BIT_SHIFT_DDMACH5_DLEN_8821C) +#define BIT_GET_DDMACH5_DLEN_8821C(x) (((x) >> BIT_SHIFT_DDMACH5_DLEN_8821C) & BIT_MASK_DDMACH5_DLEN_8821C) + +/* 2 REG_DDMA_INT_MSK_8821C */ +#define BIT_DDMACH5_MSK_8821C BIT(5) +#define BIT_DDMACH4_MSK_8821C BIT(4) +#define BIT_DDMACH3_MSK_8821C BIT(3) +#define BIT_DDMACH2_MSK_8821C BIT(2) +#define BIT_DDMACH1_MSK_8821C BIT(1) +#define BIT_DDMACH0_MSK_8821C BIT(0) + +/* 2 REG_DDMA_CHSTATUS_8821C */ +#define BIT_DDMACH5_BUSY_8821C BIT(5) +#define BIT_DDMACH4_BUSY_8821C BIT(4) +#define BIT_DDMACH3_BUSY_8821C BIT(3) +#define BIT_DDMACH2_BUSY_8821C BIT(2) +#define BIT_DDMACH1_BUSY_8821C BIT(1) +#define BIT_DDMACH0_BUSY_8821C BIT(0) + +/* 2 REG_DDMA_CHKSUM_8821C */ + +#define BIT_SHIFT_IDDMA0_CHKSUM_8821C 0 +#define BIT_MASK_IDDMA0_CHKSUM_8821C 0xffff +#define BIT_IDDMA0_CHKSUM_8821C(x) (((x) & BIT_MASK_IDDMA0_CHKSUM_8821C) << BIT_SHIFT_IDDMA0_CHKSUM_8821C) +#define BIT_GET_IDDMA0_CHKSUM_8821C(x) (((x) >> BIT_SHIFT_IDDMA0_CHKSUM_8821C) & BIT_MASK_IDDMA0_CHKSUM_8821C) + +/* 2 REG_DDMA_MONITOR_8821C */ +#define BIT_IDDMA0_PERMU_UNDERFLOW_8821C BIT(14) +#define BIT_IDDMA0_FIFO_UNDERFLOW_8821C BIT(13) +#define BIT_IDDMA0_FIFO_OVERFLOW_8821C BIT(12) +#define BIT_CH5_ERR_8821C BIT(5) +#define BIT_CH4_ERR_8821C BIT(4) +#define BIT_CH3_ERR_8821C BIT(3) +#define BIT_CH2_ERR_8821C BIT(2) +#define BIT_CH1_ERR_8821C BIT(1) +#define BIT_CH0_ERR_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_PCIE_CTRL_8821C */ +#define BIT_PCIEIO_PERSTB_SEL_8821C BIT(31) + +#define BIT_SHIFT_PCIE_MAX_RXDMA_8821C 28 +#define BIT_MASK_PCIE_MAX_RXDMA_8821C 0x7 +#define BIT_PCIE_MAX_RXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_RXDMA_8821C) << BIT_SHIFT_PCIE_MAX_RXDMA_8821C) +#define BIT_GET_PCIE_MAX_RXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA_8821C) & BIT_MASK_PCIE_MAX_RXDMA_8821C) + +#define BIT_MULRW_8821C BIT(27) + +#define BIT_SHIFT_PCIE_MAX_TXDMA_8821C 24 +#define BIT_MASK_PCIE_MAX_TXDMA_8821C 0x7 +#define BIT_PCIE_MAX_TXDMA_8821C(x) (((x) & BIT_MASK_PCIE_MAX_TXDMA_8821C) << BIT_SHIFT_PCIE_MAX_TXDMA_8821C) +#define BIT_GET_PCIE_MAX_TXDMA_8821C(x) (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA_8821C) & BIT_MASK_PCIE_MAX_TXDMA_8821C) + +#define BIT_EN_CPL_TIMEOUT_PS_8821C BIT(22) +#define BIT_REG_TXDMA_FAIL_PS_8821C BIT(21) +#define BIT_PCIE_RST_TRXDMA_INTF_8821C BIT(20) +#define BIT_EN_HWENTR_L1_8821C BIT(19) +#define BIT_EN_ADV_CLKGATE_8821C BIT(18) +#define BIT_PCIE_EN_SWENT_L23_8821C BIT(17) +#define BIT_PCIE_EN_HWEXT_L1_8821C BIT(16) +#define BIT_RX_CLOSE_EN_8821C BIT(15) +#define BIT_STOP_BCNQ_8821C BIT(14) +#define BIT_STOP_MGQ_8821C BIT(13) +#define BIT_STOP_VOQ_8821C BIT(12) +#define BIT_STOP_VIQ_8821C BIT(11) +#define BIT_STOP_BEQ_8821C BIT(10) +#define BIT_STOP_BKQ_8821C BIT(9) +#define BIT_STOP_RXQ_8821C BIT(8) +#define BIT_STOP_HI7Q_8821C BIT(7) +#define BIT_STOP_HI6Q_8821C BIT(6) +#define BIT_STOP_HI5Q_8821C BIT(5) +#define BIT_STOP_HI4Q_8821C BIT(4) +#define BIT_STOP_HI3Q_8821C BIT(3) +#define BIT_STOP_HI2Q_8821C BIT(2) +#define BIT_STOP_HI1Q_8821C BIT(1) +#define BIT_STOP_HI0Q_8821C BIT(0) + +/* 2 REG_INT_MIG_8821C */ + +#define BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C 28 +#define BIT_MASK_TXTTIMER_MATCH_NUM_8821C 0xf +#define BIT_TXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) +#define BIT_GET_TXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM_8821C) & BIT_MASK_TXTTIMER_MATCH_NUM_8821C) + +#define BIT_SHIFT_TXPKT_NUM_MATCH_8821C 24 +#define BIT_MASK_TXPKT_NUM_MATCH_8821C 0xf +#define BIT_TXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_TXPKT_NUM_MATCH_8821C) << BIT_SHIFT_TXPKT_NUM_MATCH_8821C) +#define BIT_GET_TXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH_8821C) & BIT_MASK_TXPKT_NUM_MATCH_8821C) + +#define BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C 20 +#define BIT_MASK_RXTTIMER_MATCH_NUM_8821C 0xf +#define BIT_RXTTIMER_MATCH_NUM_8821C(x) (((x) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) << BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) +#define BIT_GET_RXTTIMER_MATCH_NUM_8821C(x) (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM_8821C) & BIT_MASK_RXTTIMER_MATCH_NUM_8821C) + +#define BIT_SHIFT_RXPKT_NUM_MATCH_8821C 16 +#define BIT_MASK_RXPKT_NUM_MATCH_8821C 0xf +#define BIT_RXPKT_NUM_MATCH_8821C(x) (((x) & BIT_MASK_RXPKT_NUM_MATCH_8821C) << BIT_SHIFT_RXPKT_NUM_MATCH_8821C) +#define BIT_GET_RXPKT_NUM_MATCH_8821C(x) (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH_8821C) & BIT_MASK_RXPKT_NUM_MATCH_8821C) + +#define BIT_SHIFT_MIGRATE_TIMER_8821C 0 +#define BIT_MASK_MIGRATE_TIMER_8821C 0xffff +#define BIT_MIGRATE_TIMER_8821C(x) (((x) & BIT_MASK_MIGRATE_TIMER_8821C) << BIT_SHIFT_MIGRATE_TIMER_8821C) +#define BIT_GET_MIGRATE_TIMER_8821C(x) (((x) >> BIT_SHIFT_MIGRATE_TIMER_8821C) & BIT_MASK_MIGRATE_TIMER_8821C) + +/* 2 REG_BCNQ_TXBD_DESA_8821C */ + +#define BIT_SHIFT_BCNQ_TXBD_DESA_8821C 0 +#define BIT_MASK_BCNQ_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_BCNQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BCNQ_TXBD_DESA_8821C) << BIT_SHIFT_BCNQ_TXBD_DESA_8821C) +#define BIT_GET_BCNQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA_8821C) & BIT_MASK_BCNQ_TXBD_DESA_8821C) + +/* 2 REG_MGQ_TXBD_DESA_8821C */ + +#define BIT_SHIFT_MGQ_TXBD_DESA_8821C 0 +#define BIT_MASK_MGQ_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_MGQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_MGQ_TXBD_DESA_8821C) << BIT_SHIFT_MGQ_TXBD_DESA_8821C) +#define BIT_GET_MGQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_MGQ_TXBD_DESA_8821C) & BIT_MASK_MGQ_TXBD_DESA_8821C) + +/* 2 REG_VOQ_TXBD_DESA_8821C */ + +#define BIT_SHIFT_VOQ_TXBD_DESA_8821C 0 +#define BIT_MASK_VOQ_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_VOQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VOQ_TXBD_DESA_8821C) << BIT_SHIFT_VOQ_TXBD_DESA_8821C) +#define BIT_GET_VOQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VOQ_TXBD_DESA_8821C) & BIT_MASK_VOQ_TXBD_DESA_8821C) + +/* 2 REG_VIQ_TXBD_DESA_8821C */ + +#define BIT_SHIFT_VIQ_TXBD_DESA_8821C 0 +#define BIT_MASK_VIQ_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_VIQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_VIQ_TXBD_DESA_8821C) << BIT_SHIFT_VIQ_TXBD_DESA_8821C) +#define BIT_GET_VIQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_VIQ_TXBD_DESA_8821C) & BIT_MASK_VIQ_TXBD_DESA_8821C) + +/* 2 REG_BEQ_TXBD_DESA_8821C */ + +#define BIT_SHIFT_BEQ_TXBD_DESA_8821C 0 +#define BIT_MASK_BEQ_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_BEQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BEQ_TXBD_DESA_8821C) << BIT_SHIFT_BEQ_TXBD_DESA_8821C) +#define BIT_GET_BEQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BEQ_TXBD_DESA_8821C) & BIT_MASK_BEQ_TXBD_DESA_8821C) + +/* 2 REG_BKQ_TXBD_DESA_8821C */ + +#define BIT_SHIFT_BKQ_TXBD_DESA_8821C 0 +#define BIT_MASK_BKQ_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_BKQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_BKQ_TXBD_DESA_8821C) << BIT_SHIFT_BKQ_TXBD_DESA_8821C) +#define BIT_GET_BKQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_BKQ_TXBD_DESA_8821C) & BIT_MASK_BKQ_TXBD_DESA_8821C) + +/* 2 REG_RXQ_RXBD_DESA_8821C */ + +#define BIT_SHIFT_RXQ_RXBD_DESA_8821C 0 +#define BIT_MASK_RXQ_RXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_RXQ_RXBD_DESA_8821C(x) (((x) & BIT_MASK_RXQ_RXBD_DESA_8821C) << BIT_SHIFT_RXQ_RXBD_DESA_8821C) +#define BIT_GET_RXQ_RXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_RXQ_RXBD_DESA_8821C) & BIT_MASK_RXQ_RXBD_DESA_8821C) + +/* 2 REG_HI0Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI0Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI0Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI0Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI0Q_TXBD_DESA_8821C) << BIT_SHIFT_HI0Q_TXBD_DESA_8821C) +#define BIT_GET_HI0Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA_8821C) & BIT_MASK_HI0Q_TXBD_DESA_8821C) + +/* 2 REG_HI1Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI1Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI1Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI1Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI1Q_TXBD_DESA_8821C) << BIT_SHIFT_HI1Q_TXBD_DESA_8821C) +#define BIT_GET_HI1Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA_8821C) & BIT_MASK_HI1Q_TXBD_DESA_8821C) + +/* 2 REG_HI2Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI2Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI2Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI2Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI2Q_TXBD_DESA_8821C) << BIT_SHIFT_HI2Q_TXBD_DESA_8821C) +#define BIT_GET_HI2Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA_8821C) & BIT_MASK_HI2Q_TXBD_DESA_8821C) + +/* 2 REG_HI3Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI3Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI3Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI3Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI3Q_TXBD_DESA_8821C) << BIT_SHIFT_HI3Q_TXBD_DESA_8821C) +#define BIT_GET_HI3Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA_8821C) & BIT_MASK_HI3Q_TXBD_DESA_8821C) + +/* 2 REG_HI4Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI4Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI4Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI4Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI4Q_TXBD_DESA_8821C) << BIT_SHIFT_HI4Q_TXBD_DESA_8821C) +#define BIT_GET_HI4Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA_8821C) & BIT_MASK_HI4Q_TXBD_DESA_8821C) + +/* 2 REG_HI5Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI5Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI5Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI5Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI5Q_TXBD_DESA_8821C) << BIT_SHIFT_HI5Q_TXBD_DESA_8821C) +#define BIT_GET_HI5Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA_8821C) & BIT_MASK_HI5Q_TXBD_DESA_8821C) + +/* 2 REG_HI6Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI6Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI6Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI6Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI6Q_TXBD_DESA_8821C) << BIT_SHIFT_HI6Q_TXBD_DESA_8821C) +#define BIT_GET_HI6Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA_8821C) & BIT_MASK_HI6Q_TXBD_DESA_8821C) + +/* 2 REG_HI7Q_TXBD_DESA_8821C */ + +#define BIT_SHIFT_HI7Q_TXBD_DESA_8821C 0 +#define BIT_MASK_HI7Q_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_HI7Q_TXBD_DESA_8821C(x) (((x) & BIT_MASK_HI7Q_TXBD_DESA_8821C) << BIT_SHIFT_HI7Q_TXBD_DESA_8821C) +#define BIT_GET_HI7Q_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA_8821C) & BIT_MASK_HI7Q_TXBD_DESA_8821C) + +/* 2 REG_MGQ_TXBD_NUM_8821C */ +#define BIT_PCIE_MGQ_FLAG_8821C BIT(14) + +#define BIT_SHIFT_MGQ_DESC_MODE_8821C 12 +#define BIT_MASK_MGQ_DESC_MODE_8821C 0x3 +#define BIT_MGQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_MGQ_DESC_MODE_8821C) << BIT_SHIFT_MGQ_DESC_MODE_8821C) +#define BIT_GET_MGQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_MODE_8821C) & BIT_MASK_MGQ_DESC_MODE_8821C) + +#define BIT_SHIFT_MGQ_DESC_NUM_8821C 0 +#define BIT_MASK_MGQ_DESC_NUM_8821C 0xfff +#define BIT_MGQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_MGQ_DESC_NUM_8821C) << BIT_SHIFT_MGQ_DESC_NUM_8821C) +#define BIT_GET_MGQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_MGQ_DESC_NUM_8821C) & BIT_MASK_MGQ_DESC_NUM_8821C) + +/* 2 REG_RX_RXBD_NUM_8821C */ +#define BIT_SYS_32_64_8821C BIT(15) + +#define BIT_SHIFT_BCNQ_DESC_MODE_8821C 13 +#define BIT_MASK_BCNQ_DESC_MODE_8821C 0x3 +#define BIT_BCNQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BCNQ_DESC_MODE_8821C) << BIT_SHIFT_BCNQ_DESC_MODE_8821C) +#define BIT_GET_BCNQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BCNQ_DESC_MODE_8821C) & BIT_MASK_BCNQ_DESC_MODE_8821C) + +#define BIT_PCIE_BCNQ_FLAG_8821C BIT(12) + +#define BIT_SHIFT_RXQ_DESC_NUM_8821C 0 +#define BIT_MASK_RXQ_DESC_NUM_8821C 0xfff +#define BIT_RXQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_RXQ_DESC_NUM_8821C) << BIT_SHIFT_RXQ_DESC_NUM_8821C) +#define BIT_GET_RXQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_RXQ_DESC_NUM_8821C) & BIT_MASK_RXQ_DESC_NUM_8821C) + +/* 2 REG_VOQ_TXBD_NUM_8821C */ +#define BIT_PCIE_VOQ_FLAG_8821C BIT(14) + +#define BIT_SHIFT_VOQ_DESC_MODE_8821C 12 +#define BIT_MASK_VOQ_DESC_MODE_8821C 0x3 +#define BIT_VOQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VOQ_DESC_MODE_8821C) << BIT_SHIFT_VOQ_DESC_MODE_8821C) +#define BIT_GET_VOQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_MODE_8821C) & BIT_MASK_VOQ_DESC_MODE_8821C) + +#define BIT_SHIFT_VOQ_DESC_NUM_8821C 0 +#define BIT_MASK_VOQ_DESC_NUM_8821C 0xfff +#define BIT_VOQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VOQ_DESC_NUM_8821C) << BIT_SHIFT_VOQ_DESC_NUM_8821C) +#define BIT_GET_VOQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VOQ_DESC_NUM_8821C) & BIT_MASK_VOQ_DESC_NUM_8821C) + +/* 2 REG_VIQ_TXBD_NUM_8821C */ +#define BIT_PCIE_VIQ_FLAG_8821C BIT(14) + +#define BIT_SHIFT_VIQ_DESC_MODE_8821C 12 +#define BIT_MASK_VIQ_DESC_MODE_8821C 0x3 +#define BIT_VIQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_VIQ_DESC_MODE_8821C) << BIT_SHIFT_VIQ_DESC_MODE_8821C) +#define BIT_GET_VIQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_MODE_8821C) & BIT_MASK_VIQ_DESC_MODE_8821C) + +#define BIT_SHIFT_VIQ_DESC_NUM_8821C 0 +#define BIT_MASK_VIQ_DESC_NUM_8821C 0xfff +#define BIT_VIQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_VIQ_DESC_NUM_8821C) << BIT_SHIFT_VIQ_DESC_NUM_8821C) +#define BIT_GET_VIQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_VIQ_DESC_NUM_8821C) & BIT_MASK_VIQ_DESC_NUM_8821C) + +/* 2 REG_BEQ_TXBD_NUM_8821C */ +#define BIT_PCIE_BEQ_FLAG_8821C BIT(14) + +#define BIT_SHIFT_BEQ_DESC_MODE_8821C 12 +#define BIT_MASK_BEQ_DESC_MODE_8821C 0x3 +#define BIT_BEQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BEQ_DESC_MODE_8821C) << BIT_SHIFT_BEQ_DESC_MODE_8821C) +#define BIT_GET_BEQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_MODE_8821C) & BIT_MASK_BEQ_DESC_MODE_8821C) + +#define BIT_SHIFT_BEQ_DESC_NUM_8821C 0 +#define BIT_MASK_BEQ_DESC_NUM_8821C 0xfff +#define BIT_BEQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BEQ_DESC_NUM_8821C) << BIT_SHIFT_BEQ_DESC_NUM_8821C) +#define BIT_GET_BEQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BEQ_DESC_NUM_8821C) & BIT_MASK_BEQ_DESC_NUM_8821C) + +/* 2 REG_BKQ_TXBD_NUM_8821C */ +#define BIT_PCIE_BKQ_FLAG_8821C BIT(14) + +#define BIT_SHIFT_BKQ_DESC_MODE_8821C 12 +#define BIT_MASK_BKQ_DESC_MODE_8821C 0x3 +#define BIT_BKQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_BKQ_DESC_MODE_8821C) << BIT_SHIFT_BKQ_DESC_MODE_8821C) +#define BIT_GET_BKQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_MODE_8821C) & BIT_MASK_BKQ_DESC_MODE_8821C) + +#define BIT_SHIFT_BKQ_DESC_NUM_8821C 0 +#define BIT_MASK_BKQ_DESC_NUM_8821C 0xfff +#define BIT_BKQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_BKQ_DESC_NUM_8821C) << BIT_SHIFT_BKQ_DESC_NUM_8821C) +#define BIT_GET_BKQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_BKQ_DESC_NUM_8821C) & BIT_MASK_BKQ_DESC_NUM_8821C) + +/* 2 REG_HI0Q_TXBD_NUM_8821C */ +#define BIT_HI0Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI0Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI0Q_DESC_MODE_8821C 0x3 +#define BIT_HI0Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_MODE_8821C) << BIT_SHIFT_HI0Q_DESC_MODE_8821C) +#define BIT_GET_HI0Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_MODE_8821C) & BIT_MASK_HI0Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI0Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI0Q_DESC_NUM_8821C 0xfff +#define BIT_HI0Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI0Q_DESC_NUM_8821C) << BIT_SHIFT_HI0Q_DESC_NUM_8821C) +#define BIT_GET_HI0Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI0Q_DESC_NUM_8821C) & BIT_MASK_HI0Q_DESC_NUM_8821C) + +/* 2 REG_HI1Q_TXBD_NUM_8821C */ +#define BIT_HI1Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI1Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI1Q_DESC_MODE_8821C 0x3 +#define BIT_HI1Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_MODE_8821C) << BIT_SHIFT_HI1Q_DESC_MODE_8821C) +#define BIT_GET_HI1Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_MODE_8821C) & BIT_MASK_HI1Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI1Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI1Q_DESC_NUM_8821C 0xfff +#define BIT_HI1Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI1Q_DESC_NUM_8821C) << BIT_SHIFT_HI1Q_DESC_NUM_8821C) +#define BIT_GET_HI1Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI1Q_DESC_NUM_8821C) & BIT_MASK_HI1Q_DESC_NUM_8821C) + +/* 2 REG_HI2Q_TXBD_NUM_8821C */ +#define BIT_HI2Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI2Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI2Q_DESC_MODE_8821C 0x3 +#define BIT_HI2Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_MODE_8821C) << BIT_SHIFT_HI2Q_DESC_MODE_8821C) +#define BIT_GET_HI2Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_MODE_8821C) & BIT_MASK_HI2Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI2Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI2Q_DESC_NUM_8821C 0xfff +#define BIT_HI2Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI2Q_DESC_NUM_8821C) << BIT_SHIFT_HI2Q_DESC_NUM_8821C) +#define BIT_GET_HI2Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI2Q_DESC_NUM_8821C) & BIT_MASK_HI2Q_DESC_NUM_8821C) + +/* 2 REG_HI3Q_TXBD_NUM_8821C */ +#define BIT_HI3Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI3Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI3Q_DESC_MODE_8821C 0x3 +#define BIT_HI3Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_MODE_8821C) << BIT_SHIFT_HI3Q_DESC_MODE_8821C) +#define BIT_GET_HI3Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_MODE_8821C) & BIT_MASK_HI3Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI3Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI3Q_DESC_NUM_8821C 0xfff +#define BIT_HI3Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI3Q_DESC_NUM_8821C) << BIT_SHIFT_HI3Q_DESC_NUM_8821C) +#define BIT_GET_HI3Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI3Q_DESC_NUM_8821C) & BIT_MASK_HI3Q_DESC_NUM_8821C) + +/* 2 REG_HI4Q_TXBD_NUM_8821C */ +#define BIT_HI4Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI4Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI4Q_DESC_MODE_8821C 0x3 +#define BIT_HI4Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_MODE_8821C) << BIT_SHIFT_HI4Q_DESC_MODE_8821C) +#define BIT_GET_HI4Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_MODE_8821C) & BIT_MASK_HI4Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI4Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI4Q_DESC_NUM_8821C 0xfff +#define BIT_HI4Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI4Q_DESC_NUM_8821C) << BIT_SHIFT_HI4Q_DESC_NUM_8821C) +#define BIT_GET_HI4Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI4Q_DESC_NUM_8821C) & BIT_MASK_HI4Q_DESC_NUM_8821C) + +/* 2 REG_HI5Q_TXBD_NUM_8821C */ +#define BIT_HI5Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI5Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI5Q_DESC_MODE_8821C 0x3 +#define BIT_HI5Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_MODE_8821C) << BIT_SHIFT_HI5Q_DESC_MODE_8821C) +#define BIT_GET_HI5Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_MODE_8821C) & BIT_MASK_HI5Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI5Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI5Q_DESC_NUM_8821C 0xfff +#define BIT_HI5Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI5Q_DESC_NUM_8821C) << BIT_SHIFT_HI5Q_DESC_NUM_8821C) +#define BIT_GET_HI5Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI5Q_DESC_NUM_8821C) & BIT_MASK_HI5Q_DESC_NUM_8821C) + +/* 2 REG_HI6Q_TXBD_NUM_8821C */ +#define BIT_HI6Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI6Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI6Q_DESC_MODE_8821C 0x3 +#define BIT_HI6Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_MODE_8821C) << BIT_SHIFT_HI6Q_DESC_MODE_8821C) +#define BIT_GET_HI6Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_MODE_8821C) & BIT_MASK_HI6Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI6Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI6Q_DESC_NUM_8821C 0xfff +#define BIT_HI6Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI6Q_DESC_NUM_8821C) << BIT_SHIFT_HI6Q_DESC_NUM_8821C) +#define BIT_GET_HI6Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI6Q_DESC_NUM_8821C) & BIT_MASK_HI6Q_DESC_NUM_8821C) + +/* 2 REG_HI7Q_TXBD_NUM_8821C */ +#define BIT_HI7Q_FLAG_8821C BIT(14) + +#define BIT_SHIFT_HI7Q_DESC_MODE_8821C 12 +#define BIT_MASK_HI7Q_DESC_MODE_8821C 0x3 +#define BIT_HI7Q_DESC_MODE_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_MODE_8821C) << BIT_SHIFT_HI7Q_DESC_MODE_8821C) +#define BIT_GET_HI7Q_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_MODE_8821C) & BIT_MASK_HI7Q_DESC_MODE_8821C) + +#define BIT_SHIFT_HI7Q_DESC_NUM_8821C 0 +#define BIT_MASK_HI7Q_DESC_NUM_8821C 0xfff +#define BIT_HI7Q_DESC_NUM_8821C(x) (((x) & BIT_MASK_HI7Q_DESC_NUM_8821C) << BIT_SHIFT_HI7Q_DESC_NUM_8821C) +#define BIT_GET_HI7Q_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_HI7Q_DESC_NUM_8821C) & BIT_MASK_HI7Q_DESC_NUM_8821C) + +/* 2 REG_TSFTIMER_HCI_8821C */ + +#define BIT_SHIFT_TSFT2_HCI_8821C 16 +#define BIT_MASK_TSFT2_HCI_8821C 0xffff +#define BIT_TSFT2_HCI_8821C(x) (((x) & BIT_MASK_TSFT2_HCI_8821C) << BIT_SHIFT_TSFT2_HCI_8821C) +#define BIT_GET_TSFT2_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT2_HCI_8821C) & BIT_MASK_TSFT2_HCI_8821C) + +#define BIT_SHIFT_TSFT1_HCI_8821C 0 +#define BIT_MASK_TSFT1_HCI_8821C 0xffff +#define BIT_TSFT1_HCI_8821C(x) (((x) & BIT_MASK_TSFT1_HCI_8821C) << BIT_SHIFT_TSFT1_HCI_8821C) +#define BIT_GET_TSFT1_HCI_8821C(x) (((x) >> BIT_SHIFT_TSFT1_HCI_8821C) & BIT_MASK_TSFT1_HCI_8821C) + +/* 2 REG_BD_RWPTR_CLR_8821C */ +#define BIT_CLR_HI7Q_HW_IDX_8821C BIT(29) +#define BIT_CLR_HI6Q_HW_IDX_8821C BIT(28) +#define BIT_CLR_HI5Q_HW_IDX_8821C BIT(27) +#define BIT_CLR_HI4Q_HW_IDX_8821C BIT(26) +#define BIT_CLR_HI3Q_HW_IDX_8821C BIT(25) +#define BIT_CLR_HI2Q_HW_IDX_8821C BIT(24) +#define BIT_CLR_HI1Q_HW_IDX_8821C BIT(23) +#define BIT_CLR_HI0Q_HW_IDX_8821C BIT(22) +#define BIT_CLR_BKQ_HW_IDX_8821C BIT(21) +#define BIT_CLR_BEQ_HW_IDX_8821C BIT(20) +#define BIT_CLR_VIQ_HW_IDX_8821C BIT(19) +#define BIT_CLR_VOQ_HW_IDX_8821C BIT(18) +#define BIT_CLR_MGQ_HW_IDX_8821C BIT(17) +#define BIT_CLR_RXQ_HW_IDX_8821C BIT(16) +#define BIT_CLR_HI7Q_HOST_IDX_8821C BIT(13) +#define BIT_CLR_HI6Q_HOST_IDX_8821C BIT(12) +#define BIT_CLR_HI5Q_HOST_IDX_8821C BIT(11) +#define BIT_CLR_HI4Q_HOST_IDX_8821C BIT(10) +#define BIT_CLR_HI3Q_HOST_IDX_8821C BIT(9) +#define BIT_CLR_HI2Q_HOST_IDX_8821C BIT(8) +#define BIT_CLR_HI1Q_HOST_IDX_8821C BIT(7) +#define BIT_CLR_HI0Q_HOST_IDX_8821C BIT(6) +#define BIT_CLR_BKQ_HOST_IDX_8821C BIT(5) +#define BIT_CLR_BEQ_HOST_IDX_8821C BIT(4) +#define BIT_CLR_VIQ_HOST_IDX_8821C BIT(3) +#define BIT_CLR_VOQ_HOST_IDX_8821C BIT(2) +#define BIT_CLR_MGQ_HOST_IDX_8821C BIT(1) +#define BIT_CLR_RXQ_HOST_IDX_8821C BIT(0) + +/* 2 REG_VOQ_TXBD_IDX_8821C */ + +#define BIT_SHIFT_VOQ_HW_IDX_8821C 16 +#define BIT_MASK_VOQ_HW_IDX_8821C 0xfff +#define BIT_VOQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HW_IDX_8821C) << BIT_SHIFT_VOQ_HW_IDX_8821C) +#define BIT_GET_VOQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HW_IDX_8821C) & BIT_MASK_VOQ_HW_IDX_8821C) + +#define BIT_SHIFT_VOQ_HOST_IDX_8821C 0 +#define BIT_MASK_VOQ_HOST_IDX_8821C 0xfff +#define BIT_VOQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VOQ_HOST_IDX_8821C) << BIT_SHIFT_VOQ_HOST_IDX_8821C) +#define BIT_GET_VOQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VOQ_HOST_IDX_8821C) & BIT_MASK_VOQ_HOST_IDX_8821C) + +/* 2 REG_VIQ_TXBD_IDX_8821C */ + +#define BIT_SHIFT_VIQ_HW_IDX_8821C 16 +#define BIT_MASK_VIQ_HW_IDX_8821C 0xfff +#define BIT_VIQ_HW_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HW_IDX_8821C) << BIT_SHIFT_VIQ_HW_IDX_8821C) +#define BIT_GET_VIQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HW_IDX_8821C) & BIT_MASK_VIQ_HW_IDX_8821C) + +#define BIT_SHIFT_VIQ_HOST_IDX_8821C 0 +#define BIT_MASK_VIQ_HOST_IDX_8821C 0xfff +#define BIT_VIQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_VIQ_HOST_IDX_8821C) << BIT_SHIFT_VIQ_HOST_IDX_8821C) +#define BIT_GET_VIQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_VIQ_HOST_IDX_8821C) & BIT_MASK_VIQ_HOST_IDX_8821C) + +/* 2 REG_BEQ_TXBD_IDX_8821C */ + +#define BIT_SHIFT_BEQ_HW_IDX_8821C 16 +#define BIT_MASK_BEQ_HW_IDX_8821C 0xfff +#define BIT_BEQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HW_IDX_8821C) << BIT_SHIFT_BEQ_HW_IDX_8821C) +#define BIT_GET_BEQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HW_IDX_8821C) & BIT_MASK_BEQ_HW_IDX_8821C) + +#define BIT_SHIFT_BEQ_HOST_IDX_8821C 0 +#define BIT_MASK_BEQ_HOST_IDX_8821C 0xfff +#define BIT_BEQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BEQ_HOST_IDX_8821C) << BIT_SHIFT_BEQ_HOST_IDX_8821C) +#define BIT_GET_BEQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BEQ_HOST_IDX_8821C) & BIT_MASK_BEQ_HOST_IDX_8821C) + +/* 2 REG_BKQ_TXBD_IDX_8821C */ + +#define BIT_SHIFT_BKQ_HW_IDX_8821C 16 +#define BIT_MASK_BKQ_HW_IDX_8821C 0xfff +#define BIT_BKQ_HW_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HW_IDX_8821C) << BIT_SHIFT_BKQ_HW_IDX_8821C) +#define BIT_GET_BKQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HW_IDX_8821C) & BIT_MASK_BKQ_HW_IDX_8821C) + +#define BIT_SHIFT_BKQ_HOST_IDX_8821C 0 +#define BIT_MASK_BKQ_HOST_IDX_8821C 0xfff +#define BIT_BKQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_BKQ_HOST_IDX_8821C) << BIT_SHIFT_BKQ_HOST_IDX_8821C) +#define BIT_GET_BKQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_BKQ_HOST_IDX_8821C) & BIT_MASK_BKQ_HOST_IDX_8821C) + +/* 2 REG_MGQ_TXBD_IDX_8821C */ + +#define BIT_SHIFT_MGQ_HW_IDX_8821C 16 +#define BIT_MASK_MGQ_HW_IDX_8821C 0xfff +#define BIT_MGQ_HW_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HW_IDX_8821C) << BIT_SHIFT_MGQ_HW_IDX_8821C) +#define BIT_GET_MGQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HW_IDX_8821C) & BIT_MASK_MGQ_HW_IDX_8821C) + +#define BIT_SHIFT_MGQ_HOST_IDX_8821C 0 +#define BIT_MASK_MGQ_HOST_IDX_8821C 0xfff +#define BIT_MGQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_MGQ_HOST_IDX_8821C) << BIT_SHIFT_MGQ_HOST_IDX_8821C) +#define BIT_GET_MGQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_MGQ_HOST_IDX_8821C) & BIT_MASK_MGQ_HOST_IDX_8821C) + +/* 2 REG_RXQ_RXBD_IDX_8821C */ + +#define BIT_SHIFT_RXQ_HW_IDX_8821C 16 +#define BIT_MASK_RXQ_HW_IDX_8821C 0xfff +#define BIT_RXQ_HW_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HW_IDX_8821C) << BIT_SHIFT_RXQ_HW_IDX_8821C) +#define BIT_GET_RXQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HW_IDX_8821C) & BIT_MASK_RXQ_HW_IDX_8821C) + +#define BIT_SHIFT_RXQ_HOST_IDX_8821C 0 +#define BIT_MASK_RXQ_HOST_IDX_8821C 0xfff +#define BIT_RXQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_RXQ_HOST_IDX_8821C) << BIT_SHIFT_RXQ_HOST_IDX_8821C) +#define BIT_GET_RXQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_RXQ_HOST_IDX_8821C) & BIT_MASK_RXQ_HOST_IDX_8821C) + +/* 2 REG_HI0Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI0Q_HW_IDX_8821C 16 +#define BIT_MASK_HI0Q_HW_IDX_8821C 0xfff +#define BIT_HI0Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HW_IDX_8821C) << BIT_SHIFT_HI0Q_HW_IDX_8821C) +#define BIT_GET_HI0Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HW_IDX_8821C) & BIT_MASK_HI0Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI0Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI0Q_HOST_IDX_8821C 0xfff +#define BIT_HI0Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI0Q_HOST_IDX_8821C) << BIT_SHIFT_HI0Q_HOST_IDX_8821C) +#define BIT_GET_HI0Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI0Q_HOST_IDX_8821C) & BIT_MASK_HI0Q_HOST_IDX_8821C) + +/* 2 REG_HI1Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI1Q_HW_IDX_8821C 16 +#define BIT_MASK_HI1Q_HW_IDX_8821C 0xfff +#define BIT_HI1Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HW_IDX_8821C) << BIT_SHIFT_HI1Q_HW_IDX_8821C) +#define BIT_GET_HI1Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HW_IDX_8821C) & BIT_MASK_HI1Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI1Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI1Q_HOST_IDX_8821C 0xfff +#define BIT_HI1Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI1Q_HOST_IDX_8821C) << BIT_SHIFT_HI1Q_HOST_IDX_8821C) +#define BIT_GET_HI1Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI1Q_HOST_IDX_8821C) & BIT_MASK_HI1Q_HOST_IDX_8821C) + +/* 2 REG_HI2Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI2Q_HW_IDX_8821C 16 +#define BIT_MASK_HI2Q_HW_IDX_8821C 0xfff +#define BIT_HI2Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HW_IDX_8821C) << BIT_SHIFT_HI2Q_HW_IDX_8821C) +#define BIT_GET_HI2Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HW_IDX_8821C) & BIT_MASK_HI2Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI2Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI2Q_HOST_IDX_8821C 0xfff +#define BIT_HI2Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI2Q_HOST_IDX_8821C) << BIT_SHIFT_HI2Q_HOST_IDX_8821C) +#define BIT_GET_HI2Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI2Q_HOST_IDX_8821C) & BIT_MASK_HI2Q_HOST_IDX_8821C) + +/* 2 REG_HI3Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI3Q_HW_IDX_8821C 16 +#define BIT_MASK_HI3Q_HW_IDX_8821C 0xfff +#define BIT_HI3Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HW_IDX_8821C) << BIT_SHIFT_HI3Q_HW_IDX_8821C) +#define BIT_GET_HI3Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HW_IDX_8821C) & BIT_MASK_HI3Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI3Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI3Q_HOST_IDX_8821C 0xfff +#define BIT_HI3Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI3Q_HOST_IDX_8821C) << BIT_SHIFT_HI3Q_HOST_IDX_8821C) +#define BIT_GET_HI3Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI3Q_HOST_IDX_8821C) & BIT_MASK_HI3Q_HOST_IDX_8821C) + +/* 2 REG_HI4Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI4Q_HW_IDX_8821C 16 +#define BIT_MASK_HI4Q_HW_IDX_8821C 0xfff +#define BIT_HI4Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HW_IDX_8821C) << BIT_SHIFT_HI4Q_HW_IDX_8821C) +#define BIT_GET_HI4Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HW_IDX_8821C) & BIT_MASK_HI4Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI4Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI4Q_HOST_IDX_8821C 0xfff +#define BIT_HI4Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI4Q_HOST_IDX_8821C) << BIT_SHIFT_HI4Q_HOST_IDX_8821C) +#define BIT_GET_HI4Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI4Q_HOST_IDX_8821C) & BIT_MASK_HI4Q_HOST_IDX_8821C) + +/* 2 REG_HI5Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI5Q_HW_IDX_8821C 16 +#define BIT_MASK_HI5Q_HW_IDX_8821C 0xfff +#define BIT_HI5Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HW_IDX_8821C) << BIT_SHIFT_HI5Q_HW_IDX_8821C) +#define BIT_GET_HI5Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HW_IDX_8821C) & BIT_MASK_HI5Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI5Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI5Q_HOST_IDX_8821C 0xfff +#define BIT_HI5Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI5Q_HOST_IDX_8821C) << BIT_SHIFT_HI5Q_HOST_IDX_8821C) +#define BIT_GET_HI5Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI5Q_HOST_IDX_8821C) & BIT_MASK_HI5Q_HOST_IDX_8821C) + +/* 2 REG_HI6Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI6Q_HW_IDX_8821C 16 +#define BIT_MASK_HI6Q_HW_IDX_8821C 0xfff +#define BIT_HI6Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HW_IDX_8821C) << BIT_SHIFT_HI6Q_HW_IDX_8821C) +#define BIT_GET_HI6Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HW_IDX_8821C) & BIT_MASK_HI6Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI6Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI6Q_HOST_IDX_8821C 0xfff +#define BIT_HI6Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI6Q_HOST_IDX_8821C) << BIT_SHIFT_HI6Q_HOST_IDX_8821C) +#define BIT_GET_HI6Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI6Q_HOST_IDX_8821C) & BIT_MASK_HI6Q_HOST_IDX_8821C) + +/* 2 REG_HI7Q_TXBD_IDX_8821C */ + +#define BIT_SHIFT_HI7Q_HW_IDX_8821C 16 +#define BIT_MASK_HI7Q_HW_IDX_8821C 0xfff +#define BIT_HI7Q_HW_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HW_IDX_8821C) << BIT_SHIFT_HI7Q_HW_IDX_8821C) +#define BIT_GET_HI7Q_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HW_IDX_8821C) & BIT_MASK_HI7Q_HW_IDX_8821C) + +#define BIT_SHIFT_HI7Q_HOST_IDX_8821C 0 +#define BIT_MASK_HI7Q_HOST_IDX_8821C 0xfff +#define BIT_HI7Q_HOST_IDX_8821C(x) (((x) & BIT_MASK_HI7Q_HOST_IDX_8821C) << BIT_SHIFT_HI7Q_HOST_IDX_8821C) +#define BIT_GET_HI7Q_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_HI7Q_HOST_IDX_8821C) & BIT_MASK_HI7Q_HOST_IDX_8821C) + +/* 2 REG_DBG_SEL_V1_8821C */ + +#define BIT_SHIFT_DBG_SEL_8821C 0 +#define BIT_MASK_DBG_SEL_8821C 0xff +#define BIT_DBG_SEL_8821C(x) (((x) & BIT_MASK_DBG_SEL_8821C) << BIT_SHIFT_DBG_SEL_8821C) +#define BIT_GET_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_DBG_SEL_8821C) & BIT_MASK_DBG_SEL_8821C) + +/* 2 REG_PCIE_HRPWM1_V1_8821C */ + +#define BIT_SHIFT_PCIE_HRPWM_8821C 0 +#define BIT_MASK_PCIE_HRPWM_8821C 0xff +#define BIT_PCIE_HRPWM_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM_8821C) << BIT_SHIFT_PCIE_HRPWM_8821C) +#define BIT_GET_PCIE_HRPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM_8821C) & BIT_MASK_PCIE_HRPWM_8821C) + +/* 2 REG_PCIE_HCPWM1_V1_8821C */ + +#define BIT_SHIFT_PCIE_HCPWM_8821C 0 +#define BIT_MASK_PCIE_HCPWM_8821C 0xff +#define BIT_PCIE_HCPWM_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM_8821C) << BIT_SHIFT_PCIE_HCPWM_8821C) +#define BIT_GET_PCIE_HCPWM_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM_8821C) & BIT_MASK_PCIE_HCPWM_8821C) + +/* 2 REG_PCIE_CTRL2_8821C */ +#define BIT_DIS_TXDMA_PRE_8821C BIT(7) +#define BIT_DIS_RXDMA_PRE_8821C BIT(6) + +#define BIT_SHIFT_HPS_CLKR_PCIE_8821C 4 +#define BIT_MASK_HPS_CLKR_PCIE_8821C 0x3 +#define BIT_HPS_CLKR_PCIE_8821C(x) (((x) & BIT_MASK_HPS_CLKR_PCIE_8821C) << BIT_SHIFT_HPS_CLKR_PCIE_8821C) +#define BIT_GET_HPS_CLKR_PCIE_8821C(x) (((x) >> BIT_SHIFT_HPS_CLKR_PCIE_8821C) & BIT_MASK_HPS_CLKR_PCIE_8821C) + +#define BIT_PCIE_INT_8821C BIT(3) +#define BIT_TXFLAG_EXIT_L1_EN_8821C BIT(2) +#define BIT_EN_RXDMA_ALIGN_8821C BIT(1) +#define BIT_EN_TXDMA_ALIGN_8821C BIT(0) + +/* 2 REG_PCIE_HRPWM2_V1_8821C */ + +#define BIT_SHIFT_PCIE_HRPWM2_8821C 0 +#define BIT_MASK_PCIE_HRPWM2_8821C 0xffff +#define BIT_PCIE_HRPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HRPWM2_8821C) << BIT_SHIFT_PCIE_HRPWM2_8821C) +#define BIT_GET_PCIE_HRPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HRPWM2_8821C) & BIT_MASK_PCIE_HRPWM2_8821C) + +/* 2 REG_PCIE_HCPWM2_V1_8821C */ + +#define BIT_SHIFT_PCIE_HCPWM2_8821C 0 +#define BIT_MASK_PCIE_HCPWM2_8821C 0xffff +#define BIT_PCIE_HCPWM2_8821C(x) (((x) & BIT_MASK_PCIE_HCPWM2_8821C) << BIT_SHIFT_PCIE_HCPWM2_8821C) +#define BIT_GET_PCIE_HCPWM2_8821C(x) (((x) >> BIT_SHIFT_PCIE_HCPWM2_8821C) & BIT_MASK_PCIE_HCPWM2_8821C) + +/* 2 REG_PCIE_H2C_MSG_V1_8821C */ + +#define BIT_SHIFT_DRV2FW_INFO_8821C 0 +#define BIT_MASK_DRV2FW_INFO_8821C 0xffffffffL +#define BIT_DRV2FW_INFO_8821C(x) (((x) & BIT_MASK_DRV2FW_INFO_8821C) << BIT_SHIFT_DRV2FW_INFO_8821C) +#define BIT_GET_DRV2FW_INFO_8821C(x) (((x) >> BIT_SHIFT_DRV2FW_INFO_8821C) & BIT_MASK_DRV2FW_INFO_8821C) + +/* 2 REG_PCIE_C2H_MSG_V1_8821C */ + +#define BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C 0 +#define BIT_MASK_HCI_PCIE_C2H_MSG_8821C 0xffffffffL +#define BIT_HCI_PCIE_C2H_MSG_8821C(x) (((x) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) << BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) +#define BIT_GET_HCI_PCIE_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG_8821C) & BIT_MASK_HCI_PCIE_C2H_MSG_8821C) + +/* 2 REG_DBI_WDATA_V1_8821C */ + +#define BIT_SHIFT_DBI_WDATA_8821C 0 +#define BIT_MASK_DBI_WDATA_8821C 0xffffffffL +#define BIT_DBI_WDATA_8821C(x) (((x) & BIT_MASK_DBI_WDATA_8821C) << BIT_SHIFT_DBI_WDATA_8821C) +#define BIT_GET_DBI_WDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_WDATA_8821C) & BIT_MASK_DBI_WDATA_8821C) + +/* 2 REG_DBI_RDATA_V1_8821C */ + +#define BIT_SHIFT_DBI_RDATA_8821C 0 +#define BIT_MASK_DBI_RDATA_8821C 0xffffffffL +#define BIT_DBI_RDATA_8821C(x) (((x) & BIT_MASK_DBI_RDATA_8821C) << BIT_SHIFT_DBI_RDATA_8821C) +#define BIT_GET_DBI_RDATA_8821C(x) (((x) >> BIT_SHIFT_DBI_RDATA_8821C) & BIT_MASK_DBI_RDATA_8821C) + +/* 2 REG_DBI_FLAG_V1_8821C */ +#define BIT_EN_STUCK_DBG_8821C BIT(26) +#define BIT_RX_STUCK_8821C BIT(25) +#define BIT_TX_STUCK_8821C BIT(24) +#define BIT_DBI_RFLAG_8821C BIT(17) +#define BIT_DBI_WFLAG_8821C BIT(16) + +#define BIT_SHIFT_DBI_WREN_8821C 12 +#define BIT_MASK_DBI_WREN_8821C 0xf +#define BIT_DBI_WREN_8821C(x) (((x) & BIT_MASK_DBI_WREN_8821C) << BIT_SHIFT_DBI_WREN_8821C) +#define BIT_GET_DBI_WREN_8821C(x) (((x) >> BIT_SHIFT_DBI_WREN_8821C) & BIT_MASK_DBI_WREN_8821C) + +#define BIT_SHIFT_DBI_ADDR_8821C 0 +#define BIT_MASK_DBI_ADDR_8821C 0xfff +#define BIT_DBI_ADDR_8821C(x) (((x) & BIT_MASK_DBI_ADDR_8821C) << BIT_SHIFT_DBI_ADDR_8821C) +#define BIT_GET_DBI_ADDR_8821C(x) (((x) >> BIT_SHIFT_DBI_ADDR_8821C) & BIT_MASK_DBI_ADDR_8821C) + +/* 2 REG_MDIO_V1_8821C */ + +#define BIT_SHIFT_MDIO_RDATA_8821C 16 +#define BIT_MASK_MDIO_RDATA_8821C 0xffff +#define BIT_MDIO_RDATA_8821C(x) (((x) & BIT_MASK_MDIO_RDATA_8821C) << BIT_SHIFT_MDIO_RDATA_8821C) +#define BIT_GET_MDIO_RDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_RDATA_8821C) & BIT_MASK_MDIO_RDATA_8821C) + +#define BIT_SHIFT_MDIO_WDATA_8821C 0 +#define BIT_MASK_MDIO_WDATA_8821C 0xffff +#define BIT_MDIO_WDATA_8821C(x) (((x) & BIT_MASK_MDIO_WDATA_8821C) << BIT_SHIFT_MDIO_WDATA_8821C) +#define BIT_GET_MDIO_WDATA_8821C(x) (((x) >> BIT_SHIFT_MDIO_WDATA_8821C) & BIT_MASK_MDIO_WDATA_8821C) + +/* 2 REG_PCIE_MIX_CFG_8821C */ + +#define BIT_SHIFT_MDIO_PHY_ADDR_8821C 24 +#define BIT_MASK_MDIO_PHY_ADDR_8821C 0x1f +#define BIT_MDIO_PHY_ADDR_8821C(x) (((x) & BIT_MASK_MDIO_PHY_ADDR_8821C) << BIT_SHIFT_MDIO_PHY_ADDR_8821C) +#define BIT_GET_MDIO_PHY_ADDR_8821C(x) (((x) >> BIT_SHIFT_MDIO_PHY_ADDR_8821C) & BIT_MASK_MDIO_PHY_ADDR_8821C) + +#define BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C 10 +#define BIT_MASK_WATCH_DOG_RECORD_V1_8821C 0x3fff +#define BIT_WATCH_DOG_RECORD_V1_8821C(x) (((x) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) << BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) +#define BIT_GET_WATCH_DOG_RECORD_V1_8821C(x) (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1_8821C) & BIT_MASK_WATCH_DOG_RECORD_V1_8821C) + +#define BIT_R_IO_TIMEOUT_FLAG_V1_8821C BIT(9) +#define BIT_EN_WATCH_DOG_8821C BIT(8) +#define BIT_ECRC_EN_V1_8821C BIT(7) +#define BIT_MDIO_RFLAG_V1_8821C BIT(6) +#define BIT_MDIO_WFLAG_V1_8821C BIT(5) + +#define BIT_SHIFT_MDIO_REG_ADDR_V1_8821C 0 +#define BIT_MASK_MDIO_REG_ADDR_V1_8821C 0x1f +#define BIT_MDIO_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) << BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) +#define BIT_GET_MDIO_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1_8821C) & BIT_MASK_MDIO_REG_ADDR_V1_8821C) + +/* 2 REG_HCI_MIX_CFG_8821C */ +#define BIT_HOST_GEN2_SUPPORT_8821C BIT(20) + +#define BIT_SHIFT_TXDMA_ERR_FLAG_8821C 16 +#define BIT_MASK_TXDMA_ERR_FLAG_8821C 0xf +#define BIT_TXDMA_ERR_FLAG_8821C(x) (((x) & BIT_MASK_TXDMA_ERR_FLAG_8821C) << BIT_SHIFT_TXDMA_ERR_FLAG_8821C) +#define BIT_GET_TXDMA_ERR_FLAG_8821C(x) (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG_8821C) & BIT_MASK_TXDMA_ERR_FLAG_8821C) + +#define BIT_SHIFT_EARLY_MODE_SEL_8821C 12 +#define BIT_MASK_EARLY_MODE_SEL_8821C 0xf +#define BIT_EARLY_MODE_SEL_8821C(x) (((x) & BIT_MASK_EARLY_MODE_SEL_8821C) << BIT_SHIFT_EARLY_MODE_SEL_8821C) +#define BIT_GET_EARLY_MODE_SEL_8821C(x) (((x) >> BIT_SHIFT_EARLY_MODE_SEL_8821C) & BIT_MASK_EARLY_MODE_SEL_8821C) + +#define BIT_EPHY_RX50_EN_8821C BIT(11) + +#define BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C 8 +#define BIT_MASK_MSI_TIMEOUT_ID_V1_8821C 0x7 +#define BIT_MSI_TIMEOUT_ID_V1_8821C(x) (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) << BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) +#define BIT_GET_MSI_TIMEOUT_ID_V1_8821C(x) (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1_8821C) & BIT_MASK_MSI_TIMEOUT_ID_V1_8821C) + +#define BIT_RADDR_RD_8821C BIT(7) +#define BIT_EN_MUL_TAG_8821C BIT(6) +#define BIT_EN_EARLY_MODE_8821C BIT(5) +#define BIT_L0S_LINK_OFF_8821C BIT(4) +#define BIT_ACT_LINK_OFF_8821C BIT(3) +#define BIT_EN_SLOW_MAC_TX_8821C BIT(2) +#define BIT_EN_SLOW_MAC_RX_8821C BIT(1) + +/* 2 REG_STC_INT_CS_8821C(PCIE STATE CHANGE INTERRUPT CONTROL AND STATUS) */ +#define BIT_STC_INT_EN_8821C BIT(31) + +#define BIT_SHIFT_STC_INT_FLAG_8821C 16 +#define BIT_MASK_STC_INT_FLAG_8821C 0xff +#define BIT_STC_INT_FLAG_8821C(x) (((x) & BIT_MASK_STC_INT_FLAG_8821C) << BIT_SHIFT_STC_INT_FLAG_8821C) +#define BIT_GET_STC_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_STC_INT_FLAG_8821C) & BIT_MASK_STC_INT_FLAG_8821C) + +#define BIT_SHIFT_STC_INT_IDX_8821C 8 +#define BIT_MASK_STC_INT_IDX_8821C 0x7 +#define BIT_STC_INT_IDX_8821C(x) (((x) & BIT_MASK_STC_INT_IDX_8821C) << BIT_SHIFT_STC_INT_IDX_8821C) +#define BIT_GET_STC_INT_IDX_8821C(x) (((x) >> BIT_SHIFT_STC_INT_IDX_8821C) & BIT_MASK_STC_INT_IDX_8821C) + +#define BIT_SHIFT_STC_INT_REALTIME_CS_8821C 0 +#define BIT_MASK_STC_INT_REALTIME_CS_8821C 0x3f +#define BIT_STC_INT_REALTIME_CS_8821C(x) (((x) & BIT_MASK_STC_INT_REALTIME_CS_8821C) << BIT_SHIFT_STC_INT_REALTIME_CS_8821C) +#define BIT_GET_STC_INT_REALTIME_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS_8821C) & BIT_MASK_STC_INT_REALTIME_CS_8821C) + +/* 2 REG_ST_INT_CFG_8821C(PCIE STATE CHANGE INTERRUPT CONFIGURATION) */ +#define BIT_STC_INT_GRP_EN_8821C BIT(31) + +#define BIT_SHIFT_STC_INT_EXPECT_LS_8821C 8 +#define BIT_MASK_STC_INT_EXPECT_LS_8821C 0x3f +#define BIT_STC_INT_EXPECT_LS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_LS_8821C) << BIT_SHIFT_STC_INT_EXPECT_LS_8821C) +#define BIT_GET_STC_INT_EXPECT_LS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS_8821C) & BIT_MASK_STC_INT_EXPECT_LS_8821C) + +#define BIT_SHIFT_STC_INT_EXPECT_CS_8821C 0 +#define BIT_MASK_STC_INT_EXPECT_CS_8821C 0x3f +#define BIT_STC_INT_EXPECT_CS_8821C(x) (((x) & BIT_MASK_STC_INT_EXPECT_CS_8821C) << BIT_SHIFT_STC_INT_EXPECT_CS_8821C) +#define BIT_GET_STC_INT_EXPECT_CS_8821C(x) (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS_8821C) & BIT_MASK_STC_INT_EXPECT_CS_8821C) + +/* 2 REG_CMU_DLY_CTRL_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONTROL ) */ +#define BIT_CMU_DLY_EN_8821C BIT(31) +#define BIT_CMU_DLY_MODE_8821C BIT(30) + +#define BIT_SHIFT_CMU_DLY_PRE_DIV_8821C 0 +#define BIT_MASK_CMU_DLY_PRE_DIV_8821C 0xff +#define BIT_CMU_DLY_PRE_DIV_8821C(x) (((x) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) << BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) +#define BIT_GET_CMU_DLY_PRE_DIV_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV_8821C) & BIT_MASK_CMU_DLY_PRE_DIV_8821C) + +/* 2 REG_CMU_DLY_CFG_8821C(PCIE PHY CLOCK MGT UNIT DELAY CONFIGURATION ) */ + +#define BIT_SHIFT_CMU_DLY_LTR_A2I_8821C 24 +#define BIT_MASK_CMU_DLY_LTR_A2I_8821C 0xff +#define BIT_CMU_DLY_LTR_A2I_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) << BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) +#define BIT_GET_CMU_DLY_LTR_A2I_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I_8821C) & BIT_MASK_CMU_DLY_LTR_A2I_8821C) + +#define BIT_SHIFT_CMU_DLY_LTR_I2A_8821C 16 +#define BIT_MASK_CMU_DLY_LTR_I2A_8821C 0xff +#define BIT_CMU_DLY_LTR_I2A_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) << BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) +#define BIT_GET_CMU_DLY_LTR_I2A_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A_8821C) & BIT_MASK_CMU_DLY_LTR_I2A_8821C) + +#define BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C 8 +#define BIT_MASK_CMU_DLY_LTR_IDLE_8821C 0xff +#define BIT_CMU_DLY_LTR_IDLE_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) << BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) +#define BIT_GET_CMU_DLY_LTR_IDLE_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE_8821C) & BIT_MASK_CMU_DLY_LTR_IDLE_8821C) + +#define BIT_SHIFT_CMU_DLY_LTR_ACT_8821C 0 +#define BIT_MASK_CMU_DLY_LTR_ACT_8821C 0xff +#define BIT_CMU_DLY_LTR_ACT_8821C(x) (((x) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) << BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) +#define BIT_GET_CMU_DLY_LTR_ACT_8821C(x) (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT_8821C) & BIT_MASK_CMU_DLY_LTR_ACT_8821C) + +/* 2 REG_H2CQ_TXBD_DESA_8821C */ + +#define BIT_SHIFT_H2CQ_TXBD_DESA_8821C 0 +#define BIT_MASK_H2CQ_TXBD_DESA_8821C 0xffffffffffffffffL +#define BIT_H2CQ_TXBD_DESA_8821C(x) (((x) & BIT_MASK_H2CQ_TXBD_DESA_8821C) << BIT_SHIFT_H2CQ_TXBD_DESA_8821C) +#define BIT_GET_H2CQ_TXBD_DESA_8821C(x) (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA_8821C) & BIT_MASK_H2CQ_TXBD_DESA_8821C) + +/* 2 REG_H2CQ_TXBD_NUM_8821C */ +#define BIT_PCIE_H2CQ_FLAG_8821C BIT(14) + +#define BIT_SHIFT_H2CQ_DESC_MODE_8821C 12 +#define BIT_MASK_H2CQ_DESC_MODE_8821C 0x3 +#define BIT_H2CQ_DESC_MODE_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_MODE_8821C) << BIT_SHIFT_H2CQ_DESC_MODE_8821C) +#define BIT_GET_H2CQ_DESC_MODE_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_MODE_8821C) & BIT_MASK_H2CQ_DESC_MODE_8821C) + +#define BIT_SHIFT_H2CQ_DESC_NUM_8821C 0 +#define BIT_MASK_H2CQ_DESC_NUM_8821C 0xfff +#define BIT_H2CQ_DESC_NUM_8821C(x) (((x) & BIT_MASK_H2CQ_DESC_NUM_8821C) << BIT_SHIFT_H2CQ_DESC_NUM_8821C) +#define BIT_GET_H2CQ_DESC_NUM_8821C(x) (((x) >> BIT_SHIFT_H2CQ_DESC_NUM_8821C) & BIT_MASK_H2CQ_DESC_NUM_8821C) + +/* 2 REG_H2CQ_TXBD_IDX_8821C */ + +#define BIT_SHIFT_H2CQ_HW_IDX_8821C 16 +#define BIT_MASK_H2CQ_HW_IDX_8821C 0xfff +#define BIT_H2CQ_HW_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HW_IDX_8821C) << BIT_SHIFT_H2CQ_HW_IDX_8821C) +#define BIT_GET_H2CQ_HW_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HW_IDX_8821C) & BIT_MASK_H2CQ_HW_IDX_8821C) + +#define BIT_SHIFT_H2CQ_HOST_IDX_8821C 0 +#define BIT_MASK_H2CQ_HOST_IDX_8821C 0xfff +#define BIT_H2CQ_HOST_IDX_8821C(x) (((x) & BIT_MASK_H2CQ_HOST_IDX_8821C) << BIT_SHIFT_H2CQ_HOST_IDX_8821C) +#define BIT_GET_H2CQ_HOST_IDX_8821C(x) (((x) >> BIT_SHIFT_H2CQ_HOST_IDX_8821C) & BIT_MASK_H2CQ_HOST_IDX_8821C) + +/* 2 REG_H2CQ_CSR_8821C[31:0] (H2CQ CONTROL AND STATUS) */ +#define BIT_H2CQ_FULL_8821C BIT(31) +#define BIT_CLR_H2CQ_HOST_IDX_8821C BIT(16) +#define BIT_CLR_H2CQ_HW_IDX_8821C BIT(8) + +/* 2 REG_Q0_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q0_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q0_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) +#define BIT_GET_QUEUEMACID_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1_8821C) & BIT_MASK_QUEUEMACID_Q0_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q0_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q0_V1_8821C 0x3 +#define BIT_QUEUEAC_Q0_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q0_V1_8821C) << BIT_SHIFT_QUEUEAC_Q0_V1_8821C) +#define BIT_GET_QUEUEAC_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1_8821C) & BIT_MASK_QUEUEAC_Q0_V1_8821C) + +#define BIT_TIDEMPTY_Q0_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q0_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q0_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q0_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) +#define BIT_GET_TAIL_PKT_Q0_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2_8821C) & BIT_MASK_TAIL_PKT_Q0_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q0_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q0_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q0_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) +#define BIT_GET_HEAD_PKT_Q0_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1_8821C) & BIT_MASK_HEAD_PKT_Q0_V1_8821C) + +/* 2 REG_Q1_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q1_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q1_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) +#define BIT_GET_QUEUEMACID_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1_8821C) & BIT_MASK_QUEUEMACID_Q1_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q1_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q1_V1_8821C 0x3 +#define BIT_QUEUEAC_Q1_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q1_V1_8821C) << BIT_SHIFT_QUEUEAC_Q1_V1_8821C) +#define BIT_GET_QUEUEAC_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1_8821C) & BIT_MASK_QUEUEAC_Q1_V1_8821C) + +#define BIT_TIDEMPTY_Q1_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q1_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q1_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q1_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) +#define BIT_GET_TAIL_PKT_Q1_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2_8821C) & BIT_MASK_TAIL_PKT_Q1_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q1_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q1_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q1_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) +#define BIT_GET_HEAD_PKT_Q1_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1_8821C) & BIT_MASK_HEAD_PKT_Q1_V1_8821C) + +/* 2 REG_Q2_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q2_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q2_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) +#define BIT_GET_QUEUEMACID_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1_8821C) & BIT_MASK_QUEUEMACID_Q2_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q2_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q2_V1_8821C 0x3 +#define BIT_QUEUEAC_Q2_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q2_V1_8821C) << BIT_SHIFT_QUEUEAC_Q2_V1_8821C) +#define BIT_GET_QUEUEAC_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1_8821C) & BIT_MASK_QUEUEAC_Q2_V1_8821C) + +#define BIT_TIDEMPTY_Q2_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q2_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q2_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q2_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) +#define BIT_GET_TAIL_PKT_Q2_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2_8821C) & BIT_MASK_TAIL_PKT_Q2_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q2_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q2_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q2_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) +#define BIT_GET_HEAD_PKT_Q2_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1_8821C) & BIT_MASK_HEAD_PKT_Q2_V1_8821C) + +/* 2 REG_Q3_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q3_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q3_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) +#define BIT_GET_QUEUEMACID_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1_8821C) & BIT_MASK_QUEUEMACID_Q3_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q3_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q3_V1_8821C 0x3 +#define BIT_QUEUEAC_Q3_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q3_V1_8821C) << BIT_SHIFT_QUEUEAC_Q3_V1_8821C) +#define BIT_GET_QUEUEAC_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1_8821C) & BIT_MASK_QUEUEAC_Q3_V1_8821C) + +#define BIT_TIDEMPTY_Q3_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q3_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q3_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q3_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) +#define BIT_GET_TAIL_PKT_Q3_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2_8821C) & BIT_MASK_TAIL_PKT_Q3_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q3_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q3_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q3_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) +#define BIT_GET_HEAD_PKT_Q3_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1_8821C) & BIT_MASK_HEAD_PKT_Q3_V1_8821C) + +/* 2 REG_MGQ_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_MGQ_V1_8821C 0x7f +#define BIT_QUEUEMACID_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) +#define BIT_GET_QUEUEMACID_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1_8821C) & BIT_MASK_QUEUEMACID_MGQ_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_MGQ_V1_8821C 23 +#define BIT_MASK_QUEUEAC_MGQ_V1_8821C 0x3 +#define BIT_QUEUEAC_MGQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) << BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) +#define BIT_GET_QUEUEAC_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1_8821C) & BIT_MASK_QUEUEAC_MGQ_V1_8821C) + +#define BIT_TIDEMPTY_MGQ_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_MGQ_V2_8821C 0x7ff +#define BIT_TAIL_PKT_MGQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) +#define BIT_GET_TAIL_PKT_MGQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2_8821C) & BIT_MASK_TAIL_PKT_MGQ_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_MGQ_V1_8821C 0x7ff +#define BIT_HEAD_PKT_MGQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) +#define BIT_GET_HEAD_PKT_MGQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1_8821C) & BIT_MASK_HEAD_PKT_MGQ_V1_8821C) + +/* 2 REG_HIQ_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_HIQ_V1_8821C 0x7f +#define BIT_QUEUEMACID_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) +#define BIT_GET_QUEUEMACID_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1_8821C) & BIT_MASK_QUEUEMACID_HIQ_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_HIQ_V1_8821C 23 +#define BIT_MASK_QUEUEAC_HIQ_V1_8821C 0x3 +#define BIT_QUEUEAC_HIQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) << BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) +#define BIT_GET_QUEUEAC_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1_8821C) & BIT_MASK_QUEUEAC_HIQ_V1_8821C) + +#define BIT_TIDEMPTY_HIQ_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_HIQ_V2_8821C 0x7ff +#define BIT_TAIL_PKT_HIQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) +#define BIT_GET_TAIL_PKT_HIQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2_8821C) & BIT_MASK_TAIL_PKT_HIQ_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_HIQ_V1_8821C 0x7ff +#define BIT_HEAD_PKT_HIQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) +#define BIT_GET_HEAD_PKT_HIQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1_8821C) & BIT_MASK_HEAD_PKT_HIQ_V1_8821C) + +/* 2 REG_BCNQ_INFO_8821C */ + +#define BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C 0 +#define BIT_MASK_BCNQ_HEAD_PG_V1_8821C 0xfff +#define BIT_BCNQ_HEAD_PG_V1_8821C(x) (((x) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) << BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) +#define BIT_GET_BCNQ_HEAD_PG_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1_8821C) & BIT_MASK_BCNQ_HEAD_PG_V1_8821C) + +/* 2 REG_TXPKT_EMPTY_8821C */ +#define BIT_BCNQ_EMPTY_8821C BIT(11) +#define BIT_HQQ_EMPTY_8821C BIT(10) +#define BIT_MQQ_EMPTY_8821C BIT(9) +#define BIT_MGQ_CPU_EMPTY_8821C BIT(8) +#define BIT_AC7Q_EMPTY_8821C BIT(7) +#define BIT_AC6Q_EMPTY_8821C BIT(6) +#define BIT_AC5Q_EMPTY_8821C BIT(5) +#define BIT_AC4Q_EMPTY_8821C BIT(4) +#define BIT_AC3Q_EMPTY_8821C BIT(3) +#define BIT_AC2Q_EMPTY_8821C BIT(2) +#define BIT_AC1Q_EMPTY_8821C BIT(1) +#define BIT_AC0Q_EMPTY_8821C BIT(0) + +/* 2 REG_CPU_MGQ_INFO_8821C */ +#define BIT_BCN1_POLL_8821C BIT(30) +#define BIT_CPUMGT_POLL_8821C BIT(29) +#define BIT_BCN_POLL_8821C BIT(28) +#define BIT_CPUMGQ_FW_NUM_V1_8821C BIT(12) + +#define BIT_SHIFT_FW_FREE_TAIL_V1_8821C 0 +#define BIT_MASK_FW_FREE_TAIL_V1_8821C 0xfff +#define BIT_FW_FREE_TAIL_V1_8821C(x) (((x) & BIT_MASK_FW_FREE_TAIL_V1_8821C) << BIT_SHIFT_FW_FREE_TAIL_V1_8821C) +#define BIT_GET_FW_FREE_TAIL_V1_8821C(x) (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1_8821C) & BIT_MASK_FW_FREE_TAIL_V1_8821C) + +/* 2 REG_FWHW_TXQ_CTRL_8821C */ +#define BIT_RTS_LIMIT_IN_OFDM_8821C BIT(23) +#define BIT_EN_BCNQ_DL_8821C BIT(22) +#define BIT_EN_RD_RESP_NAV_BK_8821C BIT(21) +#define BIT_EN_WR_FREE_TAIL_8821C BIT(20) + +#define BIT_SHIFT_EN_QUEUE_RPT_8821C 8 +#define BIT_MASK_EN_QUEUE_RPT_8821C 0xff +#define BIT_EN_QUEUE_RPT_8821C(x) (((x) & BIT_MASK_EN_QUEUE_RPT_8821C) << BIT_SHIFT_EN_QUEUE_RPT_8821C) +#define BIT_GET_EN_QUEUE_RPT_8821C(x) (((x) >> BIT_SHIFT_EN_QUEUE_RPT_8821C) & BIT_MASK_EN_QUEUE_RPT_8821C) + +#define BIT_EN_RTY_BK_8821C BIT(7) +#define BIT_EN_USE_INI_RAT_8821C BIT(6) +#define BIT_EN_RTS_NAV_BK_8821C BIT(5) +#define BIT_DIS_SSN_CHECK_8821C BIT(4) +#define BIT_MACID_MATCH_RTS_8821C BIT(3) +#define BIT_EN_BCN_TRXRPT_V1_8821C BIT(2) +#define BIT_R_EN_FTMRPT_8821C BIT(1) +#define BIT_R_BMC_NAV_PROTECT_8821C BIT(0) + +/* 2 REG_DATAFB_SEL_8821C */ +#define BIT__R_EN_RTY_BK_COD_8821C BIT(2) + +#define BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C 0 +#define BIT_MASK__R_DATA_FALLBACK_SEL_8821C 0x3 +#define BIT__R_DATA_FALLBACK_SEL_8821C(x) (((x) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) << BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) +#define BIT_GET__R_DATA_FALLBACK_SEL_8821C(x) (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL_8821C) & BIT_MASK__R_DATA_FALLBACK_SEL_8821C) + +/* 2 REG_BCNQ_BDNY_V1_8821C */ + +#define BIT_SHIFT_BCNQ_PGBNDY_V1_8821C 0 +#define BIT_MASK_BCNQ_PGBNDY_V1_8821C 0xfff +#define BIT_BCNQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) +#define BIT_GET_BCNQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1_8821C) & BIT_MASK_BCNQ_PGBNDY_V1_8821C) + +/* 2 REG_LIFETIME_EN_8821C */ +#define BIT_BT_INT_CPU_8821C BIT(7) +#define BIT_BT_INT_PTA_8821C BIT(6) +#define BIT_EN_CTRL_RTYBIT_8821C BIT(4) +#define BIT_LIFETIME_BK_EN_8821C BIT(3) +#define BIT_LIFETIME_BE_EN_8821C BIT(2) +#define BIT_LIFETIME_VI_EN_8821C BIT(1) +#define BIT_LIFETIME_VO_EN_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_SPEC_SIFS_8821C */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C 8 +#define BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C 0xff +#define BIT_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) +#define BIT_GET_SPEC_SIFS_OFDM_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL_8821C) & BIT_MASK_SPEC_SIFS_OFDM_PTCL_8821C) + +#define BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C 0 +#define BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C 0xff +#define BIT_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) +#define BIT_GET_SPEC_SIFS_CCK_PTCL_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL_8821C) & BIT_MASK_SPEC_SIFS_CCK_PTCL_8821C) + +/* 2 REG_RETRY_LIMIT_8821C */ + +#define BIT_SHIFT_SRL_8821C 8 +#define BIT_MASK_SRL_8821C 0x3f +#define BIT_SRL_8821C(x) (((x) & BIT_MASK_SRL_8821C) << BIT_SHIFT_SRL_8821C) +#define BIT_GET_SRL_8821C(x) (((x) >> BIT_SHIFT_SRL_8821C) & BIT_MASK_SRL_8821C) + +#define BIT_SHIFT_LRL_8821C 0 +#define BIT_MASK_LRL_8821C 0x3f +#define BIT_LRL_8821C(x) (((x) & BIT_MASK_LRL_8821C) << BIT_SHIFT_LRL_8821C) +#define BIT_GET_LRL_8821C(x) (((x) >> BIT_SHIFT_LRL_8821C) & BIT_MASK_LRL_8821C) + +/* 2 REG_TXBF_CTRL_8821C */ +#define BIT_R_ENABLE_NDPA_8821C BIT(31) +#define BIT_USE_NDPA_PARAMETER_8821C BIT(30) +#define BIT_R_PROP_TXBF_8821C BIT(29) +#define BIT_R_EN_NDPA_INT_8821C BIT(28) +#define BIT_R_TXBF1_80M_8821C BIT(27) +#define BIT_R_TXBF1_40M_8821C BIT(26) +#define BIT_R_TXBF1_20M_8821C BIT(25) + +#define BIT_SHIFT_R_TXBF1_AID_8821C 16 +#define BIT_MASK_R_TXBF1_AID_8821C 0x1ff +#define BIT_R_TXBF1_AID_8821C(x) (((x) & BIT_MASK_R_TXBF1_AID_8821C) << BIT_SHIFT_R_TXBF1_AID_8821C) +#define BIT_GET_R_TXBF1_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF1_AID_8821C) & BIT_MASK_R_TXBF1_AID_8821C) + +#define BIT_DIS_NDP_BFEN_8821C BIT(15) +#define BIT_R_TXBCN_NOBLOCK_NDP_8821C BIT(14) +#define BIT_R_TXBF0_80M_8821C BIT(11) +#define BIT_R_TXBF0_40M_8821C BIT(10) +#define BIT_R_TXBF0_20M_8821C BIT(9) + +#define BIT_SHIFT_R_TXBF0_AID_8821C 0 +#define BIT_MASK_R_TXBF0_AID_8821C 0x1ff +#define BIT_R_TXBF0_AID_8821C(x) (((x) & BIT_MASK_R_TXBF0_AID_8821C) << BIT_SHIFT_R_TXBF0_AID_8821C) +#define BIT_GET_R_TXBF0_AID_8821C(x) (((x) >> BIT_SHIFT_R_TXBF0_AID_8821C) & BIT_MASK_R_TXBF0_AID_8821C) + +/* 2 REG_DARFRC_8821C */ + +#define BIT_SHIFT_DARF_RC8_8821C (56 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC8_8821C 0x1f +#define BIT_DARF_RC8_8821C(x) (((x) & BIT_MASK_DARF_RC8_8821C) << BIT_SHIFT_DARF_RC8_8821C) +#define BIT_GET_DARF_RC8_8821C(x) (((x) >> BIT_SHIFT_DARF_RC8_8821C) & BIT_MASK_DARF_RC8_8821C) + +#define BIT_SHIFT_DARF_RC7_8821C (48 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC7_8821C 0x1f +#define BIT_DARF_RC7_8821C(x) (((x) & BIT_MASK_DARF_RC7_8821C) << BIT_SHIFT_DARF_RC7_8821C) +#define BIT_GET_DARF_RC7_8821C(x) (((x) >> BIT_SHIFT_DARF_RC7_8821C) & BIT_MASK_DARF_RC7_8821C) + +#define BIT_SHIFT_DARF_RC6_8821C (40 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC6_8821C 0x1f +#define BIT_DARF_RC6_8821C(x) (((x) & BIT_MASK_DARF_RC6_8821C) << BIT_SHIFT_DARF_RC6_8821C) +#define BIT_GET_DARF_RC6_8821C(x) (((x) >> BIT_SHIFT_DARF_RC6_8821C) & BIT_MASK_DARF_RC6_8821C) + +#define BIT_SHIFT_DARF_RC5_8821C (32 & CPU_OPT_WIDTH) +#define BIT_MASK_DARF_RC5_8821C 0x1f +#define BIT_DARF_RC5_8821C(x) (((x) & BIT_MASK_DARF_RC5_8821C) << BIT_SHIFT_DARF_RC5_8821C) +#define BIT_GET_DARF_RC5_8821C(x) (((x) >> BIT_SHIFT_DARF_RC5_8821C) & BIT_MASK_DARF_RC5_8821C) + +#define BIT_SHIFT_DARF_RC4_8821C 24 +#define BIT_MASK_DARF_RC4_8821C 0x1f +#define BIT_DARF_RC4_8821C(x) (((x) & BIT_MASK_DARF_RC4_8821C) << BIT_SHIFT_DARF_RC4_8821C) +#define BIT_GET_DARF_RC4_8821C(x) (((x) >> BIT_SHIFT_DARF_RC4_8821C) & BIT_MASK_DARF_RC4_8821C) + +#define BIT_SHIFT_DARF_RC3_8821C 16 +#define BIT_MASK_DARF_RC3_8821C 0x1f +#define BIT_DARF_RC3_8821C(x) (((x) & BIT_MASK_DARF_RC3_8821C) << BIT_SHIFT_DARF_RC3_8821C) +#define BIT_GET_DARF_RC3_8821C(x) (((x) >> BIT_SHIFT_DARF_RC3_8821C) & BIT_MASK_DARF_RC3_8821C) + +#define BIT_SHIFT_DARF_RC2_8821C 8 +#define BIT_MASK_DARF_RC2_8821C 0x1f +#define BIT_DARF_RC2_8821C(x) (((x) & BIT_MASK_DARF_RC2_8821C) << BIT_SHIFT_DARF_RC2_8821C) +#define BIT_GET_DARF_RC2_8821C(x) (((x) >> BIT_SHIFT_DARF_RC2_8821C) & BIT_MASK_DARF_RC2_8821C) + +#define BIT_SHIFT_DARF_RC1_8821C 0 +#define BIT_MASK_DARF_RC1_8821C 0x1f +#define BIT_DARF_RC1_8821C(x) (((x) & BIT_MASK_DARF_RC1_8821C) << BIT_SHIFT_DARF_RC1_8821C) +#define BIT_GET_DARF_RC1_8821C(x) (((x) >> BIT_SHIFT_DARF_RC1_8821C) & BIT_MASK_DARF_RC1_8821C) + +/* 2 REG_RARFRC_8821C */ + +#define BIT_SHIFT_RARF_RC8_8821C (56 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC8_8821C 0x1f +#define BIT_RARF_RC8_8821C(x) (((x) & BIT_MASK_RARF_RC8_8821C) << BIT_SHIFT_RARF_RC8_8821C) +#define BIT_GET_RARF_RC8_8821C(x) (((x) >> BIT_SHIFT_RARF_RC8_8821C) & BIT_MASK_RARF_RC8_8821C) + +#define BIT_SHIFT_RARF_RC7_8821C (48 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC7_8821C 0x1f +#define BIT_RARF_RC7_8821C(x) (((x) & BIT_MASK_RARF_RC7_8821C) << BIT_SHIFT_RARF_RC7_8821C) +#define BIT_GET_RARF_RC7_8821C(x) (((x) >> BIT_SHIFT_RARF_RC7_8821C) & BIT_MASK_RARF_RC7_8821C) + +#define BIT_SHIFT_RARF_RC6_8821C (40 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC6_8821C 0x1f +#define BIT_RARF_RC6_8821C(x) (((x) & BIT_MASK_RARF_RC6_8821C) << BIT_SHIFT_RARF_RC6_8821C) +#define BIT_GET_RARF_RC6_8821C(x) (((x) >> BIT_SHIFT_RARF_RC6_8821C) & BIT_MASK_RARF_RC6_8821C) + +#define BIT_SHIFT_RARF_RC5_8821C (32 & CPU_OPT_WIDTH) +#define BIT_MASK_RARF_RC5_8821C 0x1f +#define BIT_RARF_RC5_8821C(x) (((x) & BIT_MASK_RARF_RC5_8821C) << BIT_SHIFT_RARF_RC5_8821C) +#define BIT_GET_RARF_RC5_8821C(x) (((x) >> BIT_SHIFT_RARF_RC5_8821C) & BIT_MASK_RARF_RC5_8821C) + +#define BIT_SHIFT_RARF_RC4_8821C 24 +#define BIT_MASK_RARF_RC4_8821C 0x1f +#define BIT_RARF_RC4_8821C(x) (((x) & BIT_MASK_RARF_RC4_8821C) << BIT_SHIFT_RARF_RC4_8821C) +#define BIT_GET_RARF_RC4_8821C(x) (((x) >> BIT_SHIFT_RARF_RC4_8821C) & BIT_MASK_RARF_RC4_8821C) + +#define BIT_SHIFT_RARF_RC3_8821C 16 +#define BIT_MASK_RARF_RC3_8821C 0x1f +#define BIT_RARF_RC3_8821C(x) (((x) & BIT_MASK_RARF_RC3_8821C) << BIT_SHIFT_RARF_RC3_8821C) +#define BIT_GET_RARF_RC3_8821C(x) (((x) >> BIT_SHIFT_RARF_RC3_8821C) & BIT_MASK_RARF_RC3_8821C) + +#define BIT_SHIFT_RARF_RC2_8821C 8 +#define BIT_MASK_RARF_RC2_8821C 0x1f +#define BIT_RARF_RC2_8821C(x) (((x) & BIT_MASK_RARF_RC2_8821C) << BIT_SHIFT_RARF_RC2_8821C) +#define BIT_GET_RARF_RC2_8821C(x) (((x) >> BIT_SHIFT_RARF_RC2_8821C) & BIT_MASK_RARF_RC2_8821C) + +#define BIT_SHIFT_RARF_RC1_8821C 0 +#define BIT_MASK_RARF_RC1_8821C 0x1f +#define BIT_RARF_RC1_8821C(x) (((x) & BIT_MASK_RARF_RC1_8821C) << BIT_SHIFT_RARF_RC1_8821C) +#define BIT_GET_RARF_RC1_8821C(x) (((x) >> BIT_SHIFT_RARF_RC1_8821C) & BIT_MASK_RARF_RC1_8821C) + +/* 2 REG_RRSR_8821C */ + +#define BIT_SHIFT_RRSR_RSC_8821C 21 +#define BIT_MASK_RRSR_RSC_8821C 0x3 +#define BIT_RRSR_RSC_8821C(x) (((x) & BIT_MASK_RRSR_RSC_8821C) << BIT_SHIFT_RRSR_RSC_8821C) +#define BIT_GET_RRSR_RSC_8821C(x) (((x) >> BIT_SHIFT_RRSR_RSC_8821C) & BIT_MASK_RRSR_RSC_8821C) + +#define BIT_RRSR_BW_8821C BIT(20) + +#define BIT_SHIFT_RRSC_BITMAP_8821C 0 +#define BIT_MASK_RRSC_BITMAP_8821C 0xfffff +#define BIT_RRSC_BITMAP_8821C(x) (((x) & BIT_MASK_RRSC_BITMAP_8821C) << BIT_SHIFT_RRSC_BITMAP_8821C) +#define BIT_GET_RRSC_BITMAP_8821C(x) (((x) >> BIT_SHIFT_RRSC_BITMAP_8821C) & BIT_MASK_RRSC_BITMAP_8821C) + +/* 2 REG_ARFR0_8821C */ + +#define BIT_SHIFT_ARFR0_V1_8821C 0 +#define BIT_MASK_ARFR0_V1_8821C 0xffffffffffffffffL +#define BIT_ARFR0_V1_8821C(x) (((x) & BIT_MASK_ARFR0_V1_8821C) << BIT_SHIFT_ARFR0_V1_8821C) +#define BIT_GET_ARFR0_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR0_V1_8821C) & BIT_MASK_ARFR0_V1_8821C) + +/* 2 REG_ARFR1_V1_8821C */ + +#define BIT_SHIFT_ARFR1_V1_8821C 0 +#define BIT_MASK_ARFR1_V1_8821C 0xffffffffffffffffL +#define BIT_ARFR1_V1_8821C(x) (((x) & BIT_MASK_ARFR1_V1_8821C) << BIT_SHIFT_ARFR1_V1_8821C) +#define BIT_GET_ARFR1_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR1_V1_8821C) & BIT_MASK_ARFR1_V1_8821C) + +/* 2 REG_CCK_CHECK_8821C */ +#define BIT_CHECK_CCK_EN_8821C BIT(7) +#define BIT_EN_BCN_PKT_REL_8821C BIT(6) +#define BIT_BCN_PORT_SEL_8821C BIT(5) +#define BIT_MOREDATA_BYPASS_8821C BIT(4) +#define BIT_EN_CLR_CMD_REL_BCN_PKT_8821C BIT(3) +#define BIT_R_EN_SET_MOREDATA_8821C BIT(2) +#define BIT__R_DIS_CLEAR_MACID_RELEASE_8821C BIT(1) +#define BIT__R_MACID_RELEASE_EN_8821C BIT(0) + +/* 2 REG_AMPDU_MAX_TIME_V1_8821C */ + +#define BIT_SHIFT_AMPDU_MAX_TIME_8821C 0 +#define BIT_MASK_AMPDU_MAX_TIME_8821C 0xff +#define BIT_AMPDU_MAX_TIME_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_TIME_8821C) << BIT_SHIFT_AMPDU_MAX_TIME_8821C) +#define BIT_GET_AMPDU_MAX_TIME_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_TIME_8821C) & BIT_MASK_AMPDU_MAX_TIME_8821C) + +/* 2 REG_BCNQ1_BDNY_V1_8821C */ + +#define BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C 0 +#define BIT_MASK_BCNQ1_PGBNDY_V1_8821C 0xfff +#define BIT_BCNQ1_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) << BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) +#define BIT_GET_BCNQ1_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1_8821C) & BIT_MASK_BCNQ1_PGBNDY_V1_8821C) + +/* 2 REG_AMPDU_MAX_LENGTH_8821C */ + +#define BIT_SHIFT_AMPDU_MAX_LENGTH_8821C 0 +#define BIT_MASK_AMPDU_MAX_LENGTH_8821C 0xffffffffL +#define BIT_AMPDU_MAX_LENGTH_8821C(x) (((x) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) << BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) +#define BIT_GET_AMPDU_MAX_LENGTH_8821C(x) (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH_8821C) & BIT_MASK_AMPDU_MAX_LENGTH_8821C) + +/* 2 REG_ACQ_STOP_8821C */ +#define BIT_AC7Q_STOP_8821C BIT(7) +#define BIT_AC6Q_STOP_8821C BIT(6) +#define BIT_AC5Q_STOP_8821C BIT(5) +#define BIT_AC4Q_STOP_8821C BIT(4) +#define BIT_AC3Q_STOP_8821C BIT(3) +#define BIT_AC2Q_STOP_8821C BIT(2) +#define BIT_AC1Q_STOP_8821C BIT(1) +#define BIT_AC0Q_STOP_8821C BIT(0) + +/* 2 REG_NDPA_RATE_8821C */ + +#define BIT_SHIFT_R_NDPA_RATE_V1_8821C 0 +#define BIT_MASK_R_NDPA_RATE_V1_8821C 0xff +#define BIT_R_NDPA_RATE_V1_8821C(x) (((x) & BIT_MASK_R_NDPA_RATE_V1_8821C) << BIT_SHIFT_R_NDPA_RATE_V1_8821C) +#define BIT_GET_R_NDPA_RATE_V1_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_RATE_V1_8821C) & BIT_MASK_R_NDPA_RATE_V1_8821C) + +/* 2 REG_TX_HANG_CTRL_8821C */ +#define BIT_R_EN_GNT_BT_AWAKE_8821C BIT(3) +#define BIT_EN_EOF_V1_8821C BIT(2) +#define BIT_DIS_OQT_BLOCK_8821C BIT(1) +#define BIT_SEARCH_QUEUE_EN_8821C BIT(0) + +/* 2 REG_NDPA_OPT_CTRL_8821C */ +#define BIT_R_DIS_MACID_RELEASE_RTY_8821C BIT(5) + +#define BIT_SHIFT_BW_SIGTA_8821C 3 +#define BIT_MASK_BW_SIGTA_8821C 0x3 +#define BIT_BW_SIGTA_8821C(x) (((x) & BIT_MASK_BW_SIGTA_8821C) << BIT_SHIFT_BW_SIGTA_8821C) +#define BIT_GET_BW_SIGTA_8821C(x) (((x) >> BIT_SHIFT_BW_SIGTA_8821C) & BIT_MASK_BW_SIGTA_8821C) + +#define BIT_EN_BAR_SIGTA_8821C BIT(2) + +#define BIT_SHIFT_R_NDPA_BW_8821C 0 +#define BIT_MASK_R_NDPA_BW_8821C 0x3 +#define BIT_R_NDPA_BW_8821C(x) (((x) & BIT_MASK_R_NDPA_BW_8821C) << BIT_SHIFT_R_NDPA_BW_8821C) +#define BIT_GET_R_NDPA_BW_8821C(x) (((x) >> BIT_SHIFT_R_NDPA_BW_8821C) & BIT_MASK_R_NDPA_BW_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_RD_RESP_PKT_TH_8821C */ + +#define BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C 0 +#define BIT_MASK_RD_RESP_PKT_TH_V1_8821C 0x3f +#define BIT_RD_RESP_PKT_TH_V1_8821C(x) (((x) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) << BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) +#define BIT_GET_RD_RESP_PKT_TH_V1_8821C(x) (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1_8821C) & BIT_MASK_RD_RESP_PKT_TH_V1_8821C) + +/* 2 REG_CMDQ_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_CMDQ_V1_8821C 0x7f +#define BIT_QUEUEMACID_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) +#define BIT_GET_QUEUEMACID_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1_8821C) & BIT_MASK_QUEUEMACID_CMDQ_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C 23 +#define BIT_MASK_QUEUEAC_CMDQ_V1_8821C 0x3 +#define BIT_QUEUEAC_CMDQ_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) << BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) +#define BIT_GET_QUEUEAC_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1_8821C) & BIT_MASK_QUEUEAC_CMDQ_V1_8821C) + +#define BIT_TIDEMPTY_CMDQ_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_CMDQ_V2_8821C 0x7ff +#define BIT_TAIL_PKT_CMDQ_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) << BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) +#define BIT_GET_TAIL_PKT_CMDQ_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2_8821C) & BIT_MASK_TAIL_PKT_CMDQ_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_CMDQ_V1_8821C 0x7ff +#define BIT_HEAD_PKT_CMDQ_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) << BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) +#define BIT_GET_HEAD_PKT_CMDQ_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1_8821C) & BIT_MASK_HEAD_PKT_CMDQ_V1_8821C) + +/* 2 REG_Q4_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q4_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q4_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) +#define BIT_GET_QUEUEMACID_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1_8821C) & BIT_MASK_QUEUEMACID_Q4_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q4_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q4_V1_8821C 0x3 +#define BIT_QUEUEAC_Q4_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q4_V1_8821C) << BIT_SHIFT_QUEUEAC_Q4_V1_8821C) +#define BIT_GET_QUEUEAC_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1_8821C) & BIT_MASK_QUEUEAC_Q4_V1_8821C) + +#define BIT_TIDEMPTY_Q4_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q4_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q4_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q4_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) +#define BIT_GET_TAIL_PKT_Q4_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2_8821C) & BIT_MASK_TAIL_PKT_Q4_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q4_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q4_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q4_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) +#define BIT_GET_HEAD_PKT_Q4_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1_8821C) & BIT_MASK_HEAD_PKT_Q4_V1_8821C) + +/* 2 REG_Q5_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q5_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q5_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) +#define BIT_GET_QUEUEMACID_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1_8821C) & BIT_MASK_QUEUEMACID_Q5_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q5_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q5_V1_8821C 0x3 +#define BIT_QUEUEAC_Q5_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q5_V1_8821C) << BIT_SHIFT_QUEUEAC_Q5_V1_8821C) +#define BIT_GET_QUEUEAC_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1_8821C) & BIT_MASK_QUEUEAC_Q5_V1_8821C) + +#define BIT_TIDEMPTY_Q5_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q5_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q5_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q5_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) +#define BIT_GET_TAIL_PKT_Q5_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2_8821C) & BIT_MASK_TAIL_PKT_Q5_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q5_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q5_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q5_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) +#define BIT_GET_HEAD_PKT_Q5_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1_8821C) & BIT_MASK_HEAD_PKT_Q5_V1_8821C) + +/* 2 REG_Q6_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q6_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q6_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) +#define BIT_GET_QUEUEMACID_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1_8821C) & BIT_MASK_QUEUEMACID_Q6_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q6_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q6_V1_8821C 0x3 +#define BIT_QUEUEAC_Q6_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q6_V1_8821C) << BIT_SHIFT_QUEUEAC_Q6_V1_8821C) +#define BIT_GET_QUEUEAC_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1_8821C) & BIT_MASK_QUEUEAC_Q6_V1_8821C) + +#define BIT_TIDEMPTY_Q6_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q6_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q6_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q6_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) +#define BIT_GET_TAIL_PKT_Q6_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2_8821C) & BIT_MASK_TAIL_PKT_Q6_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q6_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q6_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q6_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) +#define BIT_GET_HEAD_PKT_Q6_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1_8821C) & BIT_MASK_HEAD_PKT_Q6_V1_8821C) + +/* 2 REG_Q7_INFO_8821C */ + +#define BIT_SHIFT_QUEUEMACID_Q7_V1_8821C 25 +#define BIT_MASK_QUEUEMACID_Q7_V1_8821C 0x7f +#define BIT_QUEUEMACID_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) << BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) +#define BIT_GET_QUEUEMACID_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1_8821C) & BIT_MASK_QUEUEMACID_Q7_V1_8821C) + +#define BIT_SHIFT_QUEUEAC_Q7_V1_8821C 23 +#define BIT_MASK_QUEUEAC_Q7_V1_8821C 0x3 +#define BIT_QUEUEAC_Q7_V1_8821C(x) (((x) & BIT_MASK_QUEUEAC_Q7_V1_8821C) << BIT_SHIFT_QUEUEAC_Q7_V1_8821C) +#define BIT_GET_QUEUEAC_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1_8821C) & BIT_MASK_QUEUEAC_Q7_V1_8821C) + +#define BIT_TIDEMPTY_Q7_V1_8821C BIT(22) + +#define BIT_SHIFT_TAIL_PKT_Q7_V2_8821C 11 +#define BIT_MASK_TAIL_PKT_Q7_V2_8821C 0x7ff +#define BIT_TAIL_PKT_Q7_V2_8821C(x) (((x) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) << BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) +#define BIT_GET_TAIL_PKT_Q7_V2_8821C(x) (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2_8821C) & BIT_MASK_TAIL_PKT_Q7_V2_8821C) + +#define BIT_SHIFT_HEAD_PKT_Q7_V1_8821C 0 +#define BIT_MASK_HEAD_PKT_Q7_V1_8821C 0x7ff +#define BIT_HEAD_PKT_Q7_V1_8821C(x) (((x) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) << BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) +#define BIT_GET_HEAD_PKT_Q7_V1_8821C(x) (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1_8821C) & BIT_MASK_HEAD_PKT_Q7_V1_8821C) + +/* 2 REG_WMAC_LBK_BUF_HD_V1_8821C */ + +#define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C 0 +#define BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C 0xfff +#define BIT_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) +#define BIT_GET_WMAC_LBK_BUF_HEAD_V1_8821C(x) (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1_8821C) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1_8821C) + +/* 2 REG_MGQ_BDNY_V1_8821C */ + +#define BIT_SHIFT_MGQ_PGBNDY_V1_8821C 0 +#define BIT_MASK_MGQ_PGBNDY_V1_8821C 0xfff +#define BIT_MGQ_PGBNDY_V1_8821C(x) (((x) & BIT_MASK_MGQ_PGBNDY_V1_8821C) << BIT_SHIFT_MGQ_PGBNDY_V1_8821C) +#define BIT_GET_MGQ_PGBNDY_V1_8821C(x) (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1_8821C) & BIT_MASK_MGQ_PGBNDY_V1_8821C) + +/* 2 REG_TXRPT_CTRL_8821C */ + +#define BIT_SHIFT_TRXRPT_TIMER_TH_8821C 24 +#define BIT_MASK_TRXRPT_TIMER_TH_8821C 0xff +#define BIT_TRXRPT_TIMER_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_TIMER_TH_8821C) << BIT_SHIFT_TRXRPT_TIMER_TH_8821C) +#define BIT_GET_TRXRPT_TIMER_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH_8821C) & BIT_MASK_TRXRPT_TIMER_TH_8821C) + +#define BIT_SHIFT_TRXRPT_LEN_TH_8821C 16 +#define BIT_MASK_TRXRPT_LEN_TH_8821C 0xff +#define BIT_TRXRPT_LEN_TH_8821C(x) (((x) & BIT_MASK_TRXRPT_LEN_TH_8821C) << BIT_SHIFT_TRXRPT_LEN_TH_8821C) +#define BIT_GET_TRXRPT_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_LEN_TH_8821C) & BIT_MASK_TRXRPT_LEN_TH_8821C) + +#define BIT_SHIFT_TRXRPT_READ_PTR_8821C 8 +#define BIT_MASK_TRXRPT_READ_PTR_8821C 0xff +#define BIT_TRXRPT_READ_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_READ_PTR_8821C) << BIT_SHIFT_TRXRPT_READ_PTR_8821C) +#define BIT_GET_TRXRPT_READ_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_READ_PTR_8821C) & BIT_MASK_TRXRPT_READ_PTR_8821C) + +#define BIT_SHIFT_TRXRPT_WRITE_PTR_8821C 0 +#define BIT_MASK_TRXRPT_WRITE_PTR_8821C 0xff +#define BIT_TRXRPT_WRITE_PTR_8821C(x) (((x) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) << BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) +#define BIT_GET_TRXRPT_WRITE_PTR_8821C(x) (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR_8821C) & BIT_MASK_TRXRPT_WRITE_PTR_8821C) + +/* 2 REG_INIRTS_RATE_SEL_8821C */ +#define BIT_LEAG_RTS_BW_DUP_8821C BIT(5) + +/* 2 REG_BASIC_CFEND_RATE_8821C */ + +#define BIT_SHIFT_BASIC_CFEND_RATE_8821C 0 +#define BIT_MASK_BASIC_CFEND_RATE_8821C 0x1f +#define BIT_BASIC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_BASIC_CFEND_RATE_8821C) << BIT_SHIFT_BASIC_CFEND_RATE_8821C) +#define BIT_GET_BASIC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_BASIC_CFEND_RATE_8821C) & BIT_MASK_BASIC_CFEND_RATE_8821C) + +/* 2 REG_STBC_CFEND_RATE_8821C */ + +#define BIT_SHIFT_STBC_CFEND_RATE_8821C 0 +#define BIT_MASK_STBC_CFEND_RATE_8821C 0x1f +#define BIT_STBC_CFEND_RATE_8821C(x) (((x) & BIT_MASK_STBC_CFEND_RATE_8821C) << BIT_SHIFT_STBC_CFEND_RATE_8821C) +#define BIT_GET_STBC_CFEND_RATE_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_RATE_8821C) & BIT_MASK_STBC_CFEND_RATE_8821C) + +/* 2 REG_DATA_SC_8821C */ + +#define BIT_SHIFT_TXSC_40M_8821C 4 +#define BIT_MASK_TXSC_40M_8821C 0xf +#define BIT_TXSC_40M_8821C(x) (((x) & BIT_MASK_TXSC_40M_8821C) << BIT_SHIFT_TXSC_40M_8821C) +#define BIT_GET_TXSC_40M_8821C(x) (((x) >> BIT_SHIFT_TXSC_40M_8821C) & BIT_MASK_TXSC_40M_8821C) + +#define BIT_SHIFT_TXSC_20M_8821C 0 +#define BIT_MASK_TXSC_20M_8821C 0xf +#define BIT_TXSC_20M_8821C(x) (((x) & BIT_MASK_TXSC_20M_8821C) << BIT_SHIFT_TXSC_20M_8821C) +#define BIT_GET_TXSC_20M_8821C(x) (((x) >> BIT_SHIFT_TXSC_20M_8821C) & BIT_MASK_TXSC_20M_8821C) + +/* 2 REG_MACID_SLEEP3_8821C */ + +#define BIT_SHIFT_MACID127_96_PKTSLEEP_8821C 0 +#define BIT_MASK_MACID127_96_PKTSLEEP_8821C 0xffffffffL +#define BIT_MACID127_96_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) << BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) +#define BIT_GET_MACID127_96_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP_8821C) & BIT_MASK_MACID127_96_PKTSLEEP_8821C) + +/* 2 REG_MACID_SLEEP1_8821C */ + +#define BIT_SHIFT_MACID63_32_PKTSLEEP_8821C 0 +#define BIT_MASK_MACID63_32_PKTSLEEP_8821C 0xffffffffL +#define BIT_MACID63_32_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) << BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) +#define BIT_GET_MACID63_32_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP_8821C) & BIT_MASK_MACID63_32_PKTSLEEP_8821C) + +/* 2 REG_ARFR2_V1_8821C */ + +#define BIT_SHIFT_ARFR2_V1_8821C 0 +#define BIT_MASK_ARFR2_V1_8821C 0xffffffffffffffffL +#define BIT_ARFR2_V1_8821C(x) (((x) & BIT_MASK_ARFR2_V1_8821C) << BIT_SHIFT_ARFR2_V1_8821C) +#define BIT_GET_ARFR2_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR2_V1_8821C) & BIT_MASK_ARFR2_V1_8821C) + +/* 2 REG_ARFR3_V1_8821C */ + +#define BIT_SHIFT_ARFR3_V1_8821C 0 +#define BIT_MASK_ARFR3_V1_8821C 0xffffffffffffffffL +#define BIT_ARFR3_V1_8821C(x) (((x) & BIT_MASK_ARFR3_V1_8821C) << BIT_SHIFT_ARFR3_V1_8821C) +#define BIT_GET_ARFR3_V1_8821C(x) (((x) >> BIT_SHIFT_ARFR3_V1_8821C) & BIT_MASK_ARFR3_V1_8821C) + +/* 2 REG_ARFR4_8821C */ + +#define BIT_SHIFT_ARFR4_8821C 0 +#define BIT_MASK_ARFR4_8821C 0xffffffffffffffffL +#define BIT_ARFR4_8821C(x) (((x) & BIT_MASK_ARFR4_8821C) << BIT_SHIFT_ARFR4_8821C) +#define BIT_GET_ARFR4_8821C(x) (((x) >> BIT_SHIFT_ARFR4_8821C) & BIT_MASK_ARFR4_8821C) + +/* 2 REG_ARFR5_8821C */ + +#define BIT_SHIFT_ARFR5_8821C 0 +#define BIT_MASK_ARFR5_8821C 0xffffffffffffffffL +#define BIT_ARFR5_8821C(x) (((x) & BIT_MASK_ARFR5_8821C) << BIT_SHIFT_ARFR5_8821C) +#define BIT_GET_ARFR5_8821C(x) (((x) >> BIT_SHIFT_ARFR5_8821C) & BIT_MASK_ARFR5_8821C) + +/* 2 REG_TXRPT_START_OFFSET_8821C */ + +#define BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C 24 +#define BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C 0xff +#define BIT_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) << BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) +#define BIT_GET_R_MUTAB_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MUTAB_TXRPT_OFFSET_8821C) & BIT_MASK_R_MUTAB_TXRPT_OFFSET_8821C) + +#define BIT__R_RPTFIFO_1K_8821C BIT(16) + +#define BIT_SHIFT_MACID_CTRL_OFFSET_8821C 8 +#define BIT_MASK_MACID_CTRL_OFFSET_8821C 0xff +#define BIT_MACID_CTRL_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_CTRL_OFFSET_8821C) << BIT_SHIFT_MACID_CTRL_OFFSET_8821C) +#define BIT_GET_MACID_CTRL_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET_8821C) & BIT_MASK_MACID_CTRL_OFFSET_8821C) + +#define BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C 0 +#define BIT_MASK_AMPDU_TXRPT_OFFSET_8821C 0xff +#define BIT_AMPDU_TXRPT_OFFSET_8821C(x) (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) << BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) +#define BIT_GET_AMPDU_TXRPT_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET_8821C) & BIT_MASK_AMPDU_TXRPT_OFFSET_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_POWER_STAGE1_8821C */ +#define BIT_PTA_WL_PRI_MASK_CPU_MGQ_8821C BIT(31) +#define BIT_PTA_WL_PRI_MASK_BCNQ_8821C BIT(30) +#define BIT_PTA_WL_PRI_MASK_HIQ_8821C BIT(29) +#define BIT_PTA_WL_PRI_MASK_MGQ_8821C BIT(28) +#define BIT_PTA_WL_PRI_MASK_BK_8821C BIT(27) +#define BIT_PTA_WL_PRI_MASK_BE_8821C BIT(26) +#define BIT_PTA_WL_PRI_MASK_VI_8821C BIT(25) +#define BIT_PTA_WL_PRI_MASK_VO_8821C BIT(24) + +#define BIT_SHIFT_POWER_STAGE1_8821C 0 +#define BIT_MASK_POWER_STAGE1_8821C 0xffffff +#define BIT_POWER_STAGE1_8821C(x) (((x) & BIT_MASK_POWER_STAGE1_8821C) << BIT_SHIFT_POWER_STAGE1_8821C) +#define BIT_GET_POWER_STAGE1_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE1_8821C) & BIT_MASK_POWER_STAGE1_8821C) + +/* 2 REG_POWER_STAGE2_8821C */ +#define BIT__R_CTRL_PKT_POW_ADJ_8821C BIT(24) + +#define BIT_SHIFT_POWER_STAGE2_8821C 0 +#define BIT_MASK_POWER_STAGE2_8821C 0xffffff +#define BIT_POWER_STAGE2_8821C(x) (((x) & BIT_MASK_POWER_STAGE2_8821C) << BIT_SHIFT_POWER_STAGE2_8821C) +#define BIT_GET_POWER_STAGE2_8821C(x) (((x) >> BIT_SHIFT_POWER_STAGE2_8821C) & BIT_MASK_POWER_STAGE2_8821C) + +/* 2 REG_SW_AMPDU_BURST_MODE_CTRL_8821C */ + +#define BIT_SHIFT_PAD_NUM_THRES_8821C 24 +#define BIT_MASK_PAD_NUM_THRES_8821C 0x3f +#define BIT_PAD_NUM_THRES_8821C(x) (((x) & BIT_MASK_PAD_NUM_THRES_8821C) << BIT_SHIFT_PAD_NUM_THRES_8821C) +#define BIT_GET_PAD_NUM_THRES_8821C(x) (((x) >> BIT_SHIFT_PAD_NUM_THRES_8821C) & BIT_MASK_PAD_NUM_THRES_8821C) + +#define BIT_R_DMA_THIS_QUEUE_BK_8821C BIT(23) +#define BIT_R_DMA_THIS_QUEUE_BE_8821C BIT(22) +#define BIT_R_DMA_THIS_QUEUE_VI_8821C BIT(21) +#define BIT_R_DMA_THIS_QUEUE_VO_8821C BIT(20) + +#define BIT_SHIFT_R_TOTAL_LEN_TH_8821C 8 +#define BIT_MASK_R_TOTAL_LEN_TH_8821C 0xfff +#define BIT_R_TOTAL_LEN_TH_8821C(x) (((x) & BIT_MASK_R_TOTAL_LEN_TH_8821C) << BIT_SHIFT_R_TOTAL_LEN_TH_8821C) +#define BIT_GET_R_TOTAL_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH_8821C) & BIT_MASK_R_TOTAL_LEN_TH_8821C) + +#define BIT_EN_NEW_EARLY_8821C BIT(7) +#define BIT_PRE_TX_CMD_8821C BIT(6) + +#define BIT_SHIFT_NUM_SCL_EN_8821C 4 +#define BIT_MASK_NUM_SCL_EN_8821C 0x3 +#define BIT_NUM_SCL_EN_8821C(x) (((x) & BIT_MASK_NUM_SCL_EN_8821C) << BIT_SHIFT_NUM_SCL_EN_8821C) +#define BIT_GET_NUM_SCL_EN_8821C(x) (((x) >> BIT_SHIFT_NUM_SCL_EN_8821C) & BIT_MASK_NUM_SCL_EN_8821C) + +#define BIT_BK_EN_8821C BIT(3) +#define BIT_BE_EN_8821C BIT(2) +#define BIT_VI_EN_8821C BIT(1) +#define BIT_VO_EN_8821C BIT(0) + +/* 2 REG_PKT_LIFE_TIME_8821C */ + +#define BIT_SHIFT_PKT_LIFTIME_BEBK_8821C 16 +#define BIT_MASK_PKT_LIFTIME_BEBK_8821C 0xffff +#define BIT_PKT_LIFTIME_BEBK_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) << BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) +#define BIT_GET_PKT_LIFTIME_BEBK_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK_8821C) & BIT_MASK_PKT_LIFTIME_BEBK_8821C) + +#define BIT_SHIFT_PKT_LIFTIME_VOVI_8821C 0 +#define BIT_MASK_PKT_LIFTIME_VOVI_8821C 0xffff +#define BIT_PKT_LIFTIME_VOVI_8821C(x) (((x) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) << BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) +#define BIT_GET_PKT_LIFTIME_VOVI_8821C(x) (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI_8821C) & BIT_MASK_PKT_LIFTIME_VOVI_8821C) + +/* 2 REG_STBC_SETTING_8821C */ + +#define BIT_SHIFT_CDEND_TXTIME_L_8821C 4 +#define BIT_MASK_CDEND_TXTIME_L_8821C 0xf +#define BIT_CDEND_TXTIME_L_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_L_8821C) << BIT_SHIFT_CDEND_TXTIME_L_8821C) +#define BIT_GET_CDEND_TXTIME_L_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_L_8821C) & BIT_MASK_CDEND_TXTIME_L_8821C) + +#define BIT_SHIFT_NESS_8821C 2 +#define BIT_MASK_NESS_8821C 0x3 +#define BIT_NESS_8821C(x) (((x) & BIT_MASK_NESS_8821C) << BIT_SHIFT_NESS_8821C) +#define BIT_GET_NESS_8821C(x) (((x) >> BIT_SHIFT_NESS_8821C) & BIT_MASK_NESS_8821C) + +#define BIT_SHIFT_STBC_CFEND_8821C 0 +#define BIT_MASK_STBC_CFEND_8821C 0x3 +#define BIT_STBC_CFEND_8821C(x) (((x) & BIT_MASK_STBC_CFEND_8821C) << BIT_SHIFT_STBC_CFEND_8821C) +#define BIT_GET_STBC_CFEND_8821C(x) (((x) >> BIT_SHIFT_STBC_CFEND_8821C) & BIT_MASK_STBC_CFEND_8821C) + +/* 2 REG_STBC_SETTING2_8821C */ + +#define BIT_SHIFT_CDEND_TXTIME_H_8821C 0 +#define BIT_MASK_CDEND_TXTIME_H_8821C 0x1f +#define BIT_CDEND_TXTIME_H_8821C(x) (((x) & BIT_MASK_CDEND_TXTIME_H_8821C) << BIT_SHIFT_CDEND_TXTIME_H_8821C) +#define BIT_GET_CDEND_TXTIME_H_8821C(x) (((x) >> BIT_SHIFT_CDEND_TXTIME_H_8821C) & BIT_MASK_CDEND_TXTIME_H_8821C) + +/* 2 REG_QUEUE_CTRL_8821C */ +#define BIT_PTA_EDCCA_EN_8821C BIT(5) +#define BIT_PTA_WL_TX_EN_8821C BIT(4) +#define BIT_R_USE_DATA_BW_8821C BIT(3) +#define BIT_TRI_PKT_INT_MODE1_8821C BIT(2) +#define BIT_TRI_PKT_INT_MODE0_8821C BIT(1) +#define BIT_ACQ_MODE_SEL_8821C BIT(0) + +/* 2 REG_SINGLE_AMPDU_CTRL_8821C */ +#define BIT_EN_SINGLE_APMDU_8821C BIT(7) + +/* 2 REG_PROT_MODE_CTRL_8821C */ + +#define BIT_SHIFT_RTS_MAX_AGG_NUM_8821C 24 +#define BIT_MASK_RTS_MAX_AGG_NUM_8821C 0x3f +#define BIT_RTS_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) << BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) +#define BIT_GET_RTS_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM_8821C) & BIT_MASK_RTS_MAX_AGG_NUM_8821C) + +#define BIT_SHIFT_MAX_AGG_NUM_8821C 16 +#define BIT_MASK_MAX_AGG_NUM_8821C 0x3f +#define BIT_MAX_AGG_NUM_8821C(x) (((x) & BIT_MASK_MAX_AGG_NUM_8821C) << BIT_SHIFT_MAX_AGG_NUM_8821C) +#define BIT_GET_MAX_AGG_NUM_8821C(x) (((x) >> BIT_SHIFT_MAX_AGG_NUM_8821C) & BIT_MASK_MAX_AGG_NUM_8821C) + +#define BIT_SHIFT_RTS_TXTIME_TH_8821C 8 +#define BIT_MASK_RTS_TXTIME_TH_8821C 0xff +#define BIT_RTS_TXTIME_TH_8821C(x) (((x) & BIT_MASK_RTS_TXTIME_TH_8821C) << BIT_SHIFT_RTS_TXTIME_TH_8821C) +#define BIT_GET_RTS_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_TXTIME_TH_8821C) & BIT_MASK_RTS_TXTIME_TH_8821C) + +#define BIT_SHIFT_RTS_LEN_TH_8821C 0 +#define BIT_MASK_RTS_LEN_TH_8821C 0xff +#define BIT_RTS_LEN_TH_8821C(x) (((x) & BIT_MASK_RTS_LEN_TH_8821C) << BIT_SHIFT_RTS_LEN_TH_8821C) +#define BIT_GET_RTS_LEN_TH_8821C(x) (((x) >> BIT_SHIFT_RTS_LEN_TH_8821C) & BIT_MASK_RTS_LEN_TH_8821C) + +/* 2 REG_BAR_MODE_CTRL_8821C */ + +#define BIT_SHIFT_BAR_RTY_LMT_8821C 16 +#define BIT_MASK_BAR_RTY_LMT_8821C 0x3 +#define BIT_BAR_RTY_LMT_8821C(x) (((x) & BIT_MASK_BAR_RTY_LMT_8821C) << BIT_SHIFT_BAR_RTY_LMT_8821C) +#define BIT_GET_BAR_RTY_LMT_8821C(x) (((x) >> BIT_SHIFT_BAR_RTY_LMT_8821C) & BIT_MASK_BAR_RTY_LMT_8821C) + +#define BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C 8 +#define BIT_MASK_BAR_PKT_TXTIME_TH_8821C 0xff +#define BIT_BAR_PKT_TXTIME_TH_8821C(x) (((x) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) << BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) +#define BIT_GET_BAR_PKT_TXTIME_TH_8821C(x) (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH_8821C) & BIT_MASK_BAR_PKT_TXTIME_TH_8821C) + +#define BIT_BAR_EN_V1_8821C BIT(6) + +#define BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C 0 +#define BIT_MASK_BAR_PKTNUM_TH_V1_8821C 0x3f +#define BIT_BAR_PKTNUM_TH_V1_8821C(x) (((x) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) << BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) +#define BIT_GET_BAR_PKTNUM_TH_V1_8821C(x) (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1_8821C) & BIT_MASK_BAR_PKTNUM_TH_V1_8821C) + +/* 2 REG_RA_TRY_RATE_AGG_LMT_8821C */ + +#define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C 0 +#define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C 0x3f +#define BIT_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) +#define BIT_GET_RA_TRY_RATE_AGG_LMT_V1_8821C(x) (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1_8821C) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1_8821C) + +/* 2 REG_MACID_SLEEP2_8821C */ + +#define BIT_SHIFT_MACID95_64PKTSLEEP_8821C 0 +#define BIT_MASK_MACID95_64PKTSLEEP_8821C 0xffffffffL +#define BIT_MACID95_64PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID95_64PKTSLEEP_8821C) << BIT_SHIFT_MACID95_64PKTSLEEP_8821C) +#define BIT_GET_MACID95_64PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP_8821C) & BIT_MASK_MACID95_64PKTSLEEP_8821C) + +/* 2 REG_MACID_SLEEP_8821C */ + +#define BIT_SHIFT_MACID31_0_PKTSLEEP_8821C 0 +#define BIT_MASK_MACID31_0_PKTSLEEP_8821C 0xffffffffL +#define BIT_MACID31_0_PKTSLEEP_8821C(x) (((x) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) << BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) +#define BIT_GET_MACID31_0_PKTSLEEP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP_8821C) & BIT_MASK_MACID31_0_PKTSLEEP_8821C) + +/* 2 REG_HW_SEQ0_8821C */ + +#define BIT_SHIFT_HW_SSN_SEQ0_8821C 0 +#define BIT_MASK_HW_SSN_SEQ0_8821C 0xfff +#define BIT_HW_SSN_SEQ0_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ0_8821C) << BIT_SHIFT_HW_SSN_SEQ0_8821C) +#define BIT_GET_HW_SSN_SEQ0_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ0_8821C) & BIT_MASK_HW_SSN_SEQ0_8821C) + +/* 2 REG_HW_SEQ1_8821C */ + +#define BIT_SHIFT_HW_SSN_SEQ1_8821C 0 +#define BIT_MASK_HW_SSN_SEQ1_8821C 0xfff +#define BIT_HW_SSN_SEQ1_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ1_8821C) << BIT_SHIFT_HW_SSN_SEQ1_8821C) +#define BIT_GET_HW_SSN_SEQ1_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ1_8821C) & BIT_MASK_HW_SSN_SEQ1_8821C) + +/* 2 REG_HW_SEQ2_8821C */ + +#define BIT_SHIFT_HW_SSN_SEQ2_8821C 0 +#define BIT_MASK_HW_SSN_SEQ2_8821C 0xfff +#define BIT_HW_SSN_SEQ2_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ2_8821C) << BIT_SHIFT_HW_SSN_SEQ2_8821C) +#define BIT_GET_HW_SSN_SEQ2_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ2_8821C) & BIT_MASK_HW_SSN_SEQ2_8821C) + +/* 2 REG_HW_SEQ3_8821C */ + +#define BIT_SHIFT_HW_SSN_SEQ3_8821C 0 +#define BIT_MASK_HW_SSN_SEQ3_8821C 0xfff +#define BIT_HW_SSN_SEQ3_8821C(x) (((x) & BIT_MASK_HW_SSN_SEQ3_8821C) << BIT_SHIFT_HW_SSN_SEQ3_8821C) +#define BIT_GET_HW_SSN_SEQ3_8821C(x) (((x) >> BIT_SHIFT_HW_SSN_SEQ3_8821C) & BIT_MASK_HW_SSN_SEQ3_8821C) + +/* 2 REG_NULL_PKT_STATUS_V1_8821C */ + +#define BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C 2 +#define BIT_MASK_PTCL_TOTAL_PG_V2_8821C 0x3fff +#define BIT_PTCL_TOTAL_PG_V2_8821C(x) (((x) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) << BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) +#define BIT_GET_PTCL_TOTAL_PG_V2_8821C(x) (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2_8821C) & BIT_MASK_PTCL_TOTAL_PG_V2_8821C) + +#define BIT_TX_NULL_1_8821C BIT(1) +#define BIT_TX_NULL_0_8821C BIT(0) + +/* 2 REG_PTCL_ERR_STATUS_8821C */ +#define BIT_PTCL_RATE_TABLE_INVALID_8821C BIT(7) +#define BIT_FTM_T2R_ERROR_8821C BIT(6) +#define BIT_PTCL_ERR0_8821C BIT(5) +#define BIT_PTCL_ERR1_8821C BIT(4) +#define BIT_PTCL_ERR2_8821C BIT(3) +#define BIT_PTCL_ERR3_8821C BIT(2) +#define BIT_PTCL_ERR4_8821C BIT(1) +#define BIT_PTCL_ERR5_8821C BIT(0) + +/* 2 REG_NULL_PKT_STATUS_EXTEND_8821C */ +#define BIT_CLI3_TX_NULL_1_8821C BIT(7) +#define BIT_CLI3_TX_NULL_0_8821C BIT(6) +#define BIT_CLI2_TX_NULL_1_8821C BIT(5) +#define BIT_CLI2_TX_NULL_0_8821C BIT(4) +#define BIT_CLI1_TX_NULL_1_8821C BIT(3) +#define BIT_CLI1_TX_NULL_0_8821C BIT(2) +#define BIT_CLI0_TX_NULL_1_8821C BIT(1) +#define BIT_CLI0_TX_NULL_0_8821C BIT(0) + +/* 2 REG_VIDEO_ENHANCEMENT_FUN_8821C */ +#define BIT_VIDEO_JUST_DROP_8821C BIT(1) +#define BIT_VIDEO_ENHANCEMENT_FUN_EN_8821C BIT(0) + +/* 2 REG_BT_POLLUTE_PKT_CNT_8821C */ + +#define BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C 0 +#define BIT_MASK_BT_POLLUTE_PKT_CNT_8821C 0xffff +#define BIT_BT_POLLUTE_PKT_CNT_8821C(x) (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) << BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) +#define BIT_GET_BT_POLLUTE_PKT_CNT_8821C(x) (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT_8821C) & BIT_MASK_BT_POLLUTE_PKT_CNT_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_PTCL_DBG_8821C */ + +#define BIT_SHIFT_PTCL_DBG_8821C 0 +#define BIT_MASK_PTCL_DBG_8821C 0xffffffffL +#define BIT_PTCL_DBG_8821C(x) (((x) & BIT_MASK_PTCL_DBG_8821C) << BIT_SHIFT_PTCL_DBG_8821C) +#define BIT_GET_PTCL_DBG_8821C(x) (((x) >> BIT_SHIFT_PTCL_DBG_8821C) & BIT_MASK_PTCL_DBG_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_CPUMGQ_TIMER_CTRL2_8821C */ + +#define BIT_SHIFT_TRI_HEAD_ADDR_8821C 16 +#define BIT_MASK_TRI_HEAD_ADDR_8821C 0xfff +#define BIT_TRI_HEAD_ADDR_8821C(x) (((x) & BIT_MASK_TRI_HEAD_ADDR_8821C) << BIT_SHIFT_TRI_HEAD_ADDR_8821C) +#define BIT_GET_TRI_HEAD_ADDR_8821C(x) (((x) >> BIT_SHIFT_TRI_HEAD_ADDR_8821C) & BIT_MASK_TRI_HEAD_ADDR_8821C) + +#define BIT_DROP_TH_EN_8821C BIT(8) + +#define BIT_SHIFT_DROP_TH_8821C 0 +#define BIT_MASK_DROP_TH_8821C 0xff +#define BIT_DROP_TH_8821C(x) (((x) & BIT_MASK_DROP_TH_8821C) << BIT_SHIFT_DROP_TH_8821C) +#define BIT_GET_DROP_TH_8821C(x) (((x) >> BIT_SHIFT_DROP_TH_8821C) & BIT_MASK_DROP_TH_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_DUMMY_PAGE4_V1_8821C */ + +/* 2 REG_MOREDATA_8821C */ +#define BIT_MOREDATA_CTRL2_EN_V1_8821C BIT(3) +#define BIT_MOREDATA_CTRL1_EN_V1_8821C BIT(2) +#define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_Q0_Q1_INFO_8821C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8821C 28 +#define BIT_MASK_GTAB_ID_8821C 0x7 +#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + +#define BIT_SHIFT_AC1_PKT_INFO_8821C 16 +#define BIT_MASK_AC1_PKT_INFO_8821C 0xfff +#define BIT_AC1_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC1_PKT_INFO_8821C) << BIT_SHIFT_AC1_PKT_INFO_8821C) +#define BIT_GET_AC1_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC1_PKT_INFO_8821C) & BIT_MASK_AC1_PKT_INFO_8821C) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8821C 12 +#define BIT_MASK_GTAB_ID_V1_8821C 0x7 +#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + +#define BIT_SHIFT_AC0_PKT_INFO_8821C 0 +#define BIT_MASK_AC0_PKT_INFO_8821C 0xfff +#define BIT_AC0_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC0_PKT_INFO_8821C) << BIT_SHIFT_AC0_PKT_INFO_8821C) +#define BIT_GET_AC0_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC0_PKT_INFO_8821C) & BIT_MASK_AC0_PKT_INFO_8821C) + +/* 2 REG_Q2_Q3_INFO_8821C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8821C 28 +#define BIT_MASK_GTAB_ID_8821C 0x7 +#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + +#define BIT_SHIFT_AC3_PKT_INFO_8821C 16 +#define BIT_MASK_AC3_PKT_INFO_8821C 0xfff +#define BIT_AC3_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC3_PKT_INFO_8821C) << BIT_SHIFT_AC3_PKT_INFO_8821C) +#define BIT_GET_AC3_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC3_PKT_INFO_8821C) & BIT_MASK_AC3_PKT_INFO_8821C) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8821C 12 +#define BIT_MASK_GTAB_ID_V1_8821C 0x7 +#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + +#define BIT_SHIFT_AC2_PKT_INFO_8821C 0 +#define BIT_MASK_AC2_PKT_INFO_8821C 0xfff +#define BIT_AC2_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC2_PKT_INFO_8821C) << BIT_SHIFT_AC2_PKT_INFO_8821C) +#define BIT_GET_AC2_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC2_PKT_INFO_8821C) & BIT_MASK_AC2_PKT_INFO_8821C) + +/* 2 REG_Q4_Q5_INFO_8821C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8821C 28 +#define BIT_MASK_GTAB_ID_8821C 0x7 +#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + +#define BIT_SHIFT_AC5_PKT_INFO_8821C 16 +#define BIT_MASK_AC5_PKT_INFO_8821C 0xfff +#define BIT_AC5_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC5_PKT_INFO_8821C) << BIT_SHIFT_AC5_PKT_INFO_8821C) +#define BIT_GET_AC5_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC5_PKT_INFO_8821C) & BIT_MASK_AC5_PKT_INFO_8821C) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8821C 12 +#define BIT_MASK_GTAB_ID_V1_8821C 0x7 +#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + +#define BIT_SHIFT_AC4_PKT_INFO_8821C 0 +#define BIT_MASK_AC4_PKT_INFO_8821C 0xfff +#define BIT_AC4_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC4_PKT_INFO_8821C) << BIT_SHIFT_AC4_PKT_INFO_8821C) +#define BIT_GET_AC4_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC4_PKT_INFO_8821C) & BIT_MASK_AC4_PKT_INFO_8821C) + +/* 2 REG_Q6_Q7_INFO_8821C */ +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_8821C BIT(31) + +#define BIT_SHIFT_GTAB_ID_8821C 28 +#define BIT_MASK_GTAB_ID_8821C 0x7 +#define BIT_GTAB_ID_8821C(x) (((x) & BIT_MASK_GTAB_ID_8821C) << BIT_SHIFT_GTAB_ID_8821C) +#define BIT_GET_GTAB_ID_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_8821C) & BIT_MASK_GTAB_ID_8821C) + +#define BIT_SHIFT_AC7_PKT_INFO_8821C 16 +#define BIT_MASK_AC7_PKT_INFO_8821C 0xfff +#define BIT_AC7_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC7_PKT_INFO_8821C) << BIT_SHIFT_AC7_PKT_INFO_8821C) +#define BIT_GET_AC7_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC7_PKT_INFO_8821C) & BIT_MASK_AC7_PKT_INFO_8821C) + +#define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1_8821C BIT(15) + +#define BIT_SHIFT_GTAB_ID_V1_8821C 12 +#define BIT_MASK_GTAB_ID_V1_8821C 0x7 +#define BIT_GTAB_ID_V1_8821C(x) (((x) & BIT_MASK_GTAB_ID_V1_8821C) << BIT_SHIFT_GTAB_ID_V1_8821C) +#define BIT_GET_GTAB_ID_V1_8821C(x) (((x) >> BIT_SHIFT_GTAB_ID_V1_8821C) & BIT_MASK_GTAB_ID_V1_8821C) + +#define BIT_SHIFT_AC6_PKT_INFO_8821C 0 +#define BIT_MASK_AC6_PKT_INFO_8821C 0xfff +#define BIT_AC6_PKT_INFO_8821C(x) (((x) & BIT_MASK_AC6_PKT_INFO_8821C) << BIT_SHIFT_AC6_PKT_INFO_8821C) +#define BIT_GET_AC6_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_AC6_PKT_INFO_8821C) & BIT_MASK_AC6_PKT_INFO_8821C) + +/* 2 REG_MGQ_HIQ_INFO_8821C */ + +#define BIT_SHIFT_HIQ_PKT_INFO_8821C 16 +#define BIT_MASK_HIQ_PKT_INFO_8821C 0xfff +#define BIT_HIQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_HIQ_PKT_INFO_8821C) << BIT_SHIFT_HIQ_PKT_INFO_8821C) +#define BIT_GET_HIQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_HIQ_PKT_INFO_8821C) & BIT_MASK_HIQ_PKT_INFO_8821C) + +#define BIT_SHIFT_MGQ_PKT_INFO_8821C 0 +#define BIT_MASK_MGQ_PKT_INFO_8821C 0xfff +#define BIT_MGQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_MGQ_PKT_INFO_8821C) << BIT_SHIFT_MGQ_PKT_INFO_8821C) +#define BIT_GET_MGQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_MGQ_PKT_INFO_8821C) & BIT_MASK_MGQ_PKT_INFO_8821C) + +/* 2 REG_CMDQ_BCNQ_INFO_8821C */ + +#define BIT_SHIFT_CMDQ_PKT_INFO_8821C 16 +#define BIT_MASK_CMDQ_PKT_INFO_8821C 0xfff +#define BIT_CMDQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_CMDQ_PKT_INFO_8821C) << BIT_SHIFT_CMDQ_PKT_INFO_8821C) +#define BIT_GET_CMDQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_CMDQ_PKT_INFO_8821C) & BIT_MASK_CMDQ_PKT_INFO_8821C) + +#define BIT_SHIFT_BCNQ_PKT_INFO_8821C 0 +#define BIT_MASK_BCNQ_PKT_INFO_8821C 0xfff +#define BIT_BCNQ_PKT_INFO_8821C(x) (((x) & BIT_MASK_BCNQ_PKT_INFO_8821C) << BIT_SHIFT_BCNQ_PKT_INFO_8821C) +#define BIT_GET_BCNQ_PKT_INFO_8821C(x) (((x) >> BIT_SHIFT_BCNQ_PKT_INFO_8821C) & BIT_MASK_BCNQ_PKT_INFO_8821C) + +/* 2 REG_USEREG_SETTING_8821C */ +#define BIT_NDPA_USEREG_8821C BIT(21) + +#define BIT_SHIFT_RETRY_USEREG_8821C 19 +#define BIT_MASK_RETRY_USEREG_8821C 0x3 +#define BIT_RETRY_USEREG_8821C(x) (((x) & BIT_MASK_RETRY_USEREG_8821C) << BIT_SHIFT_RETRY_USEREG_8821C) +#define BIT_GET_RETRY_USEREG_8821C(x) (((x) >> BIT_SHIFT_RETRY_USEREG_8821C) & BIT_MASK_RETRY_USEREG_8821C) + +#define BIT_SHIFT_TRYPKT_USEREG_8821C 17 +#define BIT_MASK_TRYPKT_USEREG_8821C 0x3 +#define BIT_TRYPKT_USEREG_8821C(x) (((x) & BIT_MASK_TRYPKT_USEREG_8821C) << BIT_SHIFT_TRYPKT_USEREG_8821C) +#define BIT_GET_TRYPKT_USEREG_8821C(x) (((x) >> BIT_SHIFT_TRYPKT_USEREG_8821C) & BIT_MASK_TRYPKT_USEREG_8821C) + +#define BIT_CTLPKT_USEREG_8821C BIT(16) + +/* 2 REG_AESIV_SETTING_8821C */ + +#define BIT_SHIFT_AESIV_OFFSET_8821C 0 +#define BIT_MASK_AESIV_OFFSET_8821C 0xfff +#define BIT_AESIV_OFFSET_8821C(x) (((x) & BIT_MASK_AESIV_OFFSET_8821C) << BIT_SHIFT_AESIV_OFFSET_8821C) +#define BIT_GET_AESIV_OFFSET_8821C(x) (((x) >> BIT_SHIFT_AESIV_OFFSET_8821C) & BIT_MASK_AESIV_OFFSET_8821C) + +/* 2 REG_BF0_TIME_SETTING_8821C */ +#define BIT_BF0_TIMER_SET_8821C BIT(31) +#define BIT_BF0_TIMER_CLR_8821C BIT(30) +#define BIT_BF0_UPDATE_EN_8821C BIT(29) +#define BIT_BF0_TIMER_EN_8821C BIT(28) + +#define BIT_SHIFT_BF0_PRETIME_OVER_8821C 16 +#define BIT_MASK_BF0_PRETIME_OVER_8821C 0xfff +#define BIT_BF0_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF0_PRETIME_OVER_8821C) << BIT_SHIFT_BF0_PRETIME_OVER_8821C) +#define BIT_GET_BF0_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF0_PRETIME_OVER_8821C) & BIT_MASK_BF0_PRETIME_OVER_8821C) + +#define BIT_SHIFT_BF0_LIFETIME_8821C 0 +#define BIT_MASK_BF0_LIFETIME_8821C 0xffff +#define BIT_BF0_LIFETIME_8821C(x) (((x) & BIT_MASK_BF0_LIFETIME_8821C) << BIT_SHIFT_BF0_LIFETIME_8821C) +#define BIT_GET_BF0_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF0_LIFETIME_8821C) & BIT_MASK_BF0_LIFETIME_8821C) + +/* 2 REG_BF1_TIME_SETTING_8821C */ +#define BIT_BF1_TIMER_SET_8821C BIT(31) +#define BIT_BF1_TIMER_CLR_8821C BIT(30) +#define BIT_BF1_UPDATE_EN_8821C BIT(29) +#define BIT_BF1_TIMER_EN_8821C BIT(28) + +#define BIT_SHIFT_BF1_PRETIME_OVER_8821C 16 +#define BIT_MASK_BF1_PRETIME_OVER_8821C 0xfff +#define BIT_BF1_PRETIME_OVER_8821C(x) (((x) & BIT_MASK_BF1_PRETIME_OVER_8821C) << BIT_SHIFT_BF1_PRETIME_OVER_8821C) +#define BIT_GET_BF1_PRETIME_OVER_8821C(x) (((x) >> BIT_SHIFT_BF1_PRETIME_OVER_8821C) & BIT_MASK_BF1_PRETIME_OVER_8821C) + +#define BIT_SHIFT_BF1_LIFETIME_8821C 0 +#define BIT_MASK_BF1_LIFETIME_8821C 0xffff +#define BIT_BF1_LIFETIME_8821C(x) (((x) & BIT_MASK_BF1_LIFETIME_8821C) << BIT_SHIFT_BF1_LIFETIME_8821C) +#define BIT_GET_BF1_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_BF1_LIFETIME_8821C) & BIT_MASK_BF1_LIFETIME_8821C) + +/* 2 REG_BF_TIMEOUT_EN_8821C */ +#define BIT_EN_VHT_LDPC_8821C BIT(9) +#define BIT_EN_HT_LDPC_8821C BIT(8) +#define BIT_BF1_TIMEOUT_EN_8821C BIT(1) +#define BIT_BF0_TIMEOUT_EN_8821C BIT(0) + +/* 2 REG_MACID_RELEASE0_8821C */ + +#define BIT_SHIFT_MACID31_0_RELEASE_8821C 0 +#define BIT_MASK_MACID31_0_RELEASE_8821C 0xffffffffL +#define BIT_MACID31_0_RELEASE_8821C(x) (((x) & BIT_MASK_MACID31_0_RELEASE_8821C) << BIT_SHIFT_MACID31_0_RELEASE_8821C) +#define BIT_GET_MACID31_0_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_RELEASE_8821C) & BIT_MASK_MACID31_0_RELEASE_8821C) + +/* 2 REG_MACID_RELEASE1_8821C */ + +#define BIT_SHIFT_MACID63_32_RELEASE_8821C 0 +#define BIT_MASK_MACID63_32_RELEASE_8821C 0xffffffffL +#define BIT_MACID63_32_RELEASE_8821C(x) (((x) & BIT_MASK_MACID63_32_RELEASE_8821C) << BIT_SHIFT_MACID63_32_RELEASE_8821C) +#define BIT_GET_MACID63_32_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_RELEASE_8821C) & BIT_MASK_MACID63_32_RELEASE_8821C) + +/* 2 REG_MACID_RELEASE2_8821C */ + +#define BIT_SHIFT_MACID95_64_RELEASE_8821C 0 +#define BIT_MASK_MACID95_64_RELEASE_8821C 0xffffffffL +#define BIT_MACID95_64_RELEASE_8821C(x) (((x) & BIT_MASK_MACID95_64_RELEASE_8821C) << BIT_SHIFT_MACID95_64_RELEASE_8821C) +#define BIT_GET_MACID95_64_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_RELEASE_8821C) & BIT_MASK_MACID95_64_RELEASE_8821C) + +/* 2 REG_MACID_RELEASE3_8821C */ + +#define BIT_SHIFT_MACID127_96_RELEASE_8821C 0 +#define BIT_MASK_MACID127_96_RELEASE_8821C 0xffffffffL +#define BIT_MACID127_96_RELEASE_8821C(x) (((x) & BIT_MASK_MACID127_96_RELEASE_8821C) << BIT_SHIFT_MACID127_96_RELEASE_8821C) +#define BIT_GET_MACID127_96_RELEASE_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_RELEASE_8821C) & BIT_MASK_MACID127_96_RELEASE_8821C) + +/* 2 REG_MACID_RELEASE_SETTING_8821C */ +#define BIT_MACID_VALUE_8821C BIT(7) + +#define BIT_SHIFT_MACID_OFFSET_8821C 0 +#define BIT_MASK_MACID_OFFSET_8821C 0x7f +#define BIT_MACID_OFFSET_8821C(x) (((x) & BIT_MASK_MACID_OFFSET_8821C) << BIT_SHIFT_MACID_OFFSET_8821C) +#define BIT_GET_MACID_OFFSET_8821C(x) (((x) >> BIT_SHIFT_MACID_OFFSET_8821C) & BIT_MASK_MACID_OFFSET_8821C) + +/* 2 REG_FAST_EDCA_VOVI_SETTING_8821C */ + +#define BIT_SHIFT_VI_FAST_EDCA_TO_8821C 24 +#define BIT_MASK_VI_FAST_EDCA_TO_8821C 0xff +#define BIT_VI_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_TO_8821C) << BIT_SHIFT_VI_FAST_EDCA_TO_8821C) +#define BIT_GET_VI_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO_8821C) & BIT_MASK_VI_FAST_EDCA_TO_8821C) + +#define BIT_VI_THRESHOLD_SEL_8821C BIT(23) + +#define BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C 16 +#define BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C 0x7f +#define BIT_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) +#define BIT_GET_VI_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VI_FAST_EDCA_PKT_TH_8821C) + +#define BIT_SHIFT_VO_FAST_EDCA_TO_8821C 8 +#define BIT_MASK_VO_FAST_EDCA_TO_8821C 0xff +#define BIT_VO_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_TO_8821C) << BIT_SHIFT_VO_FAST_EDCA_TO_8821C) +#define BIT_GET_VO_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO_8821C) & BIT_MASK_VO_FAST_EDCA_TO_8821C) + +#define BIT_VO_THRESHOLD_SEL_8821C BIT(7) + +#define BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C 0 +#define BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C 0x7f +#define BIT_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) +#define BIT_GET_VO_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_VO_FAST_EDCA_PKT_TH_8821C) + +/* 2 REG_FAST_EDCA_BEBK_SETTING_8821C */ + +#define BIT_SHIFT_BK_FAST_EDCA_TO_8821C 24 +#define BIT_MASK_BK_FAST_EDCA_TO_8821C 0xff +#define BIT_BK_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_TO_8821C) << BIT_SHIFT_BK_FAST_EDCA_TO_8821C) +#define BIT_GET_BK_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO_8821C) & BIT_MASK_BK_FAST_EDCA_TO_8821C) + +#define BIT_BK_THRESHOLD_SEL_8821C BIT(23) + +#define BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C 16 +#define BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C 0x7f +#define BIT_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) +#define BIT_GET_BK_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BK_FAST_EDCA_PKT_TH_8821C) + +#define BIT_SHIFT_BE_FAST_EDCA_TO_8821C 8 +#define BIT_MASK_BE_FAST_EDCA_TO_8821C 0xff +#define BIT_BE_FAST_EDCA_TO_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_TO_8821C) << BIT_SHIFT_BE_FAST_EDCA_TO_8821C) +#define BIT_GET_BE_FAST_EDCA_TO_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO_8821C) & BIT_MASK_BE_FAST_EDCA_TO_8821C) + +#define BIT_BE_THRESHOLD_SEL_8821C BIT(7) + +#define BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C 0 +#define BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C 0x7f +#define BIT_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) +#define BIT_GET_BE_FAST_EDCA_PKT_TH_8821C(x) (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH_8821C) & BIT_MASK_BE_FAST_EDCA_PKT_TH_8821C) + +/* 2 REG_MACID_DROP0_8821C */ + +#define BIT_SHIFT_MACID31_0_DROP_8821C 0 +#define BIT_MASK_MACID31_0_DROP_8821C 0xffffffffL +#define BIT_MACID31_0_DROP_8821C(x) (((x) & BIT_MASK_MACID31_0_DROP_8821C) << BIT_SHIFT_MACID31_0_DROP_8821C) +#define BIT_GET_MACID31_0_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID31_0_DROP_8821C) & BIT_MASK_MACID31_0_DROP_8821C) + +/* 2 REG_MACID_DROP1_8821C */ + +#define BIT_SHIFT_MACID63_32_DROP_8821C 0 +#define BIT_MASK_MACID63_32_DROP_8821C 0xffffffffL +#define BIT_MACID63_32_DROP_8821C(x) (((x) & BIT_MASK_MACID63_32_DROP_8821C) << BIT_SHIFT_MACID63_32_DROP_8821C) +#define BIT_GET_MACID63_32_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID63_32_DROP_8821C) & BIT_MASK_MACID63_32_DROP_8821C) + +/* 2 REG_MACID_DROP2_8821C */ + +#define BIT_SHIFT_MACID95_64_DROP_8821C 0 +#define BIT_MASK_MACID95_64_DROP_8821C 0xffffffffL +#define BIT_MACID95_64_DROP_8821C(x) (((x) & BIT_MASK_MACID95_64_DROP_8821C) << BIT_SHIFT_MACID95_64_DROP_8821C) +#define BIT_GET_MACID95_64_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID95_64_DROP_8821C) & BIT_MASK_MACID95_64_DROP_8821C) + +/* 2 REG_MACID_DROP3_8821C */ + +#define BIT_SHIFT_MACID127_96_DROP_8821C 0 +#define BIT_MASK_MACID127_96_DROP_8821C 0xffffffffL +#define BIT_MACID127_96_DROP_8821C(x) (((x) & BIT_MASK_MACID127_96_DROP_8821C) << BIT_SHIFT_MACID127_96_DROP_8821C) +#define BIT_GET_MACID127_96_DROP_8821C(x) (((x) >> BIT_SHIFT_MACID127_96_DROP_8821C) & BIT_MASK_MACID127_96_DROP_8821C) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_0_8821C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_0_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0_8821C) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_1_8821C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_1_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1_8821C) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_2_8821C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_2_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2_8821C) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_3_8821C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C 0xffffffffL +#define BIT_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_3_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3_8821C) + +/* 2 REG_MGG_FIFO_CRTL_8821C */ +#define BIT_R_MGG_FIFO_EN_8821C BIT(31) + +#define BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C 28 +#define BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C 0x7 +#define BIT_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) +#define BIT_GET_R_MGG_FIFO_PG_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_PG_SIZE_8821C) + +#define BIT_SHIFT_R_MGG_FIFO_START_PG_8821C 16 +#define BIT_MASK_R_MGG_FIFO_START_PG_8821C 0xfff +#define BIT_R_MGG_FIFO_START_PG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) << BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) +#define BIT_GET_R_MGG_FIFO_START_PG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG_8821C) & BIT_MASK_R_MGG_FIFO_START_PG_8821C) + +#define BIT_SHIFT_R_MGG_FIFO_SIZE_8821C 14 +#define BIT_MASK_R_MGG_FIFO_SIZE_8821C 0x3 +#define BIT_R_MGG_FIFO_SIZE_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) << BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) +#define BIT_GET_R_MGG_FIFO_SIZE_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE_8821C) & BIT_MASK_R_MGG_FIFO_SIZE_8821C) + +#define BIT_R_MGG_FIFO_PAUSE_8821C BIT(13) + +#define BIT_SHIFT_R_MGG_FIFO_RPTR_8821C 8 +#define BIT_MASK_R_MGG_FIFO_RPTR_8821C 0x1f +#define BIT_R_MGG_FIFO_RPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) +#define BIT_GET_R_MGG_FIFO_RPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR_8821C) & BIT_MASK_R_MGG_FIFO_RPTR_8821C) + +#define BIT_R_MGG_FIFO_OV_8821C BIT(7) +#define BIT_R_MGG_FIFO_WPTR_ERROR_8821C BIT(6) +#define BIT_R_EN_CPU_LIFETIME_8821C BIT(5) + +#define BIT_SHIFT_R_MGG_FIFO_WPTR_8821C 0 +#define BIT_MASK_R_MGG_FIFO_WPTR_8821C 0x1f +#define BIT_R_MGG_FIFO_WPTR_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) << BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) +#define BIT_GET_R_MGG_FIFO_WPTR_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR_8821C) & BIT_MASK_R_MGG_FIFO_WPTR_8821C) + +/* 2 REG_MGG_FIFO_INT_8821C */ + +#define BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C 16 +#define BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C 0xffff +#define BIT_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) +#define BIT_GET_R_MGG_FIFO_INT_FLAG_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG_8821C) & BIT_MASK_R_MGG_FIFO_INT_FLAG_8821C) + +#define BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C 0 +#define BIT_MASK_R_MGG_FIFO_INT_MASK_8821C 0xffff +#define BIT_R_MGG_FIFO_INT_MASK_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) << BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) +#define BIT_GET_R_MGG_FIFO_INT_MASK_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK_8821C) & BIT_MASK_R_MGG_FIFO_INT_MASK_8821C) + +/* 2 REG_MGG_FIFO_LIFETIME_8821C */ + +#define BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C 16 +#define BIT_MASK_R_MGG_FIFO_LIFETIME_8821C 0xffff +#define BIT_R_MGG_FIFO_LIFETIME_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) << BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) +#define BIT_GET_R_MGG_FIFO_LIFETIME_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME_8821C) & BIT_MASK_R_MGG_FIFO_LIFETIME_8821C) + +#define BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C 0 +#define BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C 0xffff +#define BIT_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) << BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) +#define BIT_GET_R_MGG_FIFO_VALID_MAP_8821C(x) (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP_8821C) & BIT_MASK_R_MGG_FIFO_VALID_MAP_8821C) + +/* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C */ + +#define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0 +#define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x7f +#define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) +#define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C) + +/* 2 REG_MU_TX_CTL_8821C (NOT SUPPORT) */ +#define BIT_R_FORCE_P1_RATEDOWN_8821C BIT(11) + +#define BIT_SHIFT_R_MU_TAB_SEL_8821C 8 +#define BIT_MASK_R_MU_TAB_SEL_8821C 0x7 +#define BIT_R_MU_TAB_SEL_8821C(x) (((x) & BIT_MASK_R_MU_TAB_SEL_8821C) << BIT_SHIFT_R_MU_TAB_SEL_8821C) +#define BIT_GET_R_MU_TAB_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MU_TAB_SEL_8821C) & BIT_MASK_R_MU_TAB_SEL_8821C) + +#define BIT_R_EN_MU_MIMO_8821C BIT(7) +#define BIT_R_EN_REVERS_GTAB_8821C BIT(6) + +#define BIT_SHIFT_R_MU_TABLE_VALID_8821C 0 +#define BIT_MASK_R_MU_TABLE_VALID_8821C 0x3f +#define BIT_R_MU_TABLE_VALID_8821C(x) (((x) & BIT_MASK_R_MU_TABLE_VALID_8821C) << BIT_SHIFT_R_MU_TABLE_VALID_8821C) +#define BIT_GET_R_MU_TABLE_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_TABLE_VALID_8821C) & BIT_MASK_R_MU_TABLE_VALID_8821C) + +/* 2 REG_MU_STA_GID_VLD_8821C (NOT SUPPORT) */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) +#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) + +#define BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_VALID_8821C 0xffffffffL +#define BIT_R_MU_STA_GTAB_VALID_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) << BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) +#define BIT_GET_R_MU_STA_GTAB_VALID_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID_8821C) & BIT_MASK_R_MU_STA_GTAB_VALID_8821C) + +/* 2 REG_MU_STA_USER_POS_INFO_8821C (NOT SUPPORT) */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) + +#define BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C 0 +#define BIT_MASK_R_MU_STA_GTAB_POSITION_8821C 0xffffffffffffffffL +#define BIT_R_MU_STA_GTAB_POSITION_8821C(x) (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) << BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) +#define BIT_GET_R_MU_STA_GTAB_POSITION_8821C(x) (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION_8821C) & BIT_MASK_R_MU_STA_GTAB_POSITION_8821C) + +/* 2 REG_MU_TRX_DBG_CNT_8821C (NOT SUPPORT) */ +#define BIT_MU_DNGCNT_RST_8821C BIT(20) + +#define BIT_SHIFT_MU_DBGCNT_SEL_8821C 16 +#define BIT_MASK_MU_DBGCNT_SEL_8821C 0xf +#define BIT_MU_DBGCNT_SEL_8821C(x) (((x) & BIT_MASK_MU_DBGCNT_SEL_8821C) << BIT_SHIFT_MU_DBGCNT_SEL_8821C) +#define BIT_GET_MU_DBGCNT_SEL_8821C(x) (((x) >> BIT_SHIFT_MU_DBGCNT_SEL_8821C) & BIT_MASK_MU_DBGCNT_SEL_8821C) + +#define BIT_SHIFT_MU_DNGCNT_8821C 0 +#define BIT_MASK_MU_DNGCNT_8821C 0xffff +#define BIT_MU_DNGCNT_8821C(x) (((x) & BIT_MASK_MU_DNGCNT_8821C) << BIT_SHIFT_MU_DNGCNT_8821C) +#define BIT_GET_MU_DNGCNT_8821C(x) (((x) >> BIT_SHIFT_MU_DNGCNT_8821C) & BIT_MASK_MU_DNGCNT_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_EDCA_VO_PARAM_8821C */ + +#define BIT_SHIFT_TXOPLIMIT_8821C 16 +#define BIT_MASK_TXOPLIMIT_8821C 0x7ff +#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + +#define BIT_SHIFT_CW_8821C 8 +#define BIT_MASK_CW_8821C 0xff +#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + +#define BIT_SHIFT_AIFS_8821C 0 +#define BIT_MASK_AIFS_8821C 0xff +#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) +#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + +/* 2 REG_EDCA_VI_PARAM_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TXOPLIMIT_8821C 16 +#define BIT_MASK_TXOPLIMIT_8821C 0x7ff +#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + +#define BIT_SHIFT_CW_8821C 8 +#define BIT_MASK_CW_8821C 0xff +#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + +#define BIT_SHIFT_AIFS_8821C 0 +#define BIT_MASK_AIFS_8821C 0xff +#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) +#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + +/* 2 REG_EDCA_BE_PARAM_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TXOPLIMIT_8821C 16 +#define BIT_MASK_TXOPLIMIT_8821C 0x7ff +#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + +#define BIT_SHIFT_CW_8821C 8 +#define BIT_MASK_CW_8821C 0xff +#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + +#define BIT_SHIFT_AIFS_8821C 0 +#define BIT_MASK_AIFS_8821C 0xff +#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) +#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + +/* 2 REG_EDCA_BK_PARAM_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_TXOPLIMIT_8821C 16 +#define BIT_MASK_TXOPLIMIT_8821C 0x7ff +#define BIT_TXOPLIMIT_8821C(x) (((x) & BIT_MASK_TXOPLIMIT_8821C) << BIT_SHIFT_TXOPLIMIT_8821C) +#define BIT_GET_TXOPLIMIT_8821C(x) (((x) >> BIT_SHIFT_TXOPLIMIT_8821C) & BIT_MASK_TXOPLIMIT_8821C) + +#define BIT_SHIFT_CW_8821C 8 +#define BIT_MASK_CW_8821C 0xff +#define BIT_CW_8821C(x) (((x) & BIT_MASK_CW_8821C) << BIT_SHIFT_CW_8821C) +#define BIT_GET_CW_8821C(x) (((x) >> BIT_SHIFT_CW_8821C) & BIT_MASK_CW_8821C) + +#define BIT_SHIFT_AIFS_8821C 0 +#define BIT_MASK_AIFS_8821C 0xff +#define BIT_AIFS_8821C(x) (((x) & BIT_MASK_AIFS_8821C) << BIT_SHIFT_AIFS_8821C) +#define BIT_GET_AIFS_8821C(x) (((x) >> BIT_SHIFT_AIFS_8821C) & BIT_MASK_AIFS_8821C) + +/* 2 REG_BCNTCFG_8821C */ + +#define BIT_SHIFT_BCNCW_MAX_8821C 12 +#define BIT_MASK_BCNCW_MAX_8821C 0xf +#define BIT_BCNCW_MAX_8821C(x) (((x) & BIT_MASK_BCNCW_MAX_8821C) << BIT_SHIFT_BCNCW_MAX_8821C) +#define BIT_GET_BCNCW_MAX_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MAX_8821C) & BIT_MASK_BCNCW_MAX_8821C) + +#define BIT_SHIFT_BCNCW_MIN_8821C 8 +#define BIT_MASK_BCNCW_MIN_8821C 0xf +#define BIT_BCNCW_MIN_8821C(x) (((x) & BIT_MASK_BCNCW_MIN_8821C) << BIT_SHIFT_BCNCW_MIN_8821C) +#define BIT_GET_BCNCW_MIN_8821C(x) (((x) >> BIT_SHIFT_BCNCW_MIN_8821C) & BIT_MASK_BCNCW_MIN_8821C) + +#define BIT_SHIFT_BCNIFS_8821C 0 +#define BIT_MASK_BCNIFS_8821C 0xff +#define BIT_BCNIFS_8821C(x) (((x) & BIT_MASK_BCNIFS_8821C) << BIT_SHIFT_BCNIFS_8821C) +#define BIT_GET_BCNIFS_8821C(x) (((x) >> BIT_SHIFT_BCNIFS_8821C) & BIT_MASK_BCNIFS_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_PIFS_8821C */ + +#define BIT_SHIFT_PIFS_8821C 0 +#define BIT_MASK_PIFS_8821C 0xff +#define BIT_PIFS_8821C(x) (((x) & BIT_MASK_PIFS_8821C) << BIT_SHIFT_PIFS_8821C) +#define BIT_GET_PIFS_8821C(x) (((x) >> BIT_SHIFT_PIFS_8821C) & BIT_MASK_PIFS_8821C) + +/* 2 REG_RDG_PIFS_8821C */ + +#define BIT_SHIFT_RDG_PIFS_8821C 0 +#define BIT_MASK_RDG_PIFS_8821C 0xff +#define BIT_RDG_PIFS_8821C(x) (((x) & BIT_MASK_RDG_PIFS_8821C) << BIT_SHIFT_RDG_PIFS_8821C) +#define BIT_GET_RDG_PIFS_8821C(x) (((x) >> BIT_SHIFT_RDG_PIFS_8821C) & BIT_MASK_RDG_PIFS_8821C) + +/* 2 REG_SIFS_8821C */ + +#define BIT_SHIFT_SIFS_OFDM_TRX_8821C 24 +#define BIT_MASK_SIFS_OFDM_TRX_8821C 0xff +#define BIT_SIFS_OFDM_TRX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_TRX_8821C) << BIT_SHIFT_SIFS_OFDM_TRX_8821C) +#define BIT_GET_SIFS_OFDM_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_TRX_8821C) & BIT_MASK_SIFS_OFDM_TRX_8821C) + +#define BIT_SHIFT_SIFS_CCK_TRX_8821C 16 +#define BIT_MASK_SIFS_CCK_TRX_8821C 0xff +#define BIT_SIFS_CCK_TRX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_TRX_8821C) << BIT_SHIFT_SIFS_CCK_TRX_8821C) +#define BIT_GET_SIFS_CCK_TRX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_TRX_8821C) & BIT_MASK_SIFS_CCK_TRX_8821C) + +#define BIT_SHIFT_SIFS_OFDM_CTX_8821C 8 +#define BIT_MASK_SIFS_OFDM_CTX_8821C 0xff +#define BIT_SIFS_OFDM_CTX_8821C(x) (((x) & BIT_MASK_SIFS_OFDM_CTX_8821C) << BIT_SHIFT_SIFS_OFDM_CTX_8821C) +#define BIT_GET_SIFS_OFDM_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_OFDM_CTX_8821C) & BIT_MASK_SIFS_OFDM_CTX_8821C) + +#define BIT_SHIFT_SIFS_CCK_CTX_8821C 0 +#define BIT_MASK_SIFS_CCK_CTX_8821C 0xff +#define BIT_SIFS_CCK_CTX_8821C(x) (((x) & BIT_MASK_SIFS_CCK_CTX_8821C) << BIT_SHIFT_SIFS_CCK_CTX_8821C) +#define BIT_GET_SIFS_CCK_CTX_8821C(x) (((x) >> BIT_SHIFT_SIFS_CCK_CTX_8821C) & BIT_MASK_SIFS_CCK_CTX_8821C) + +/* 2 REG_TSFTR_SYN_OFFSET_8821C */ + +#define BIT_SHIFT_TSFTR_SNC_OFFSET_8821C 0 +#define BIT_MASK_TSFTR_SNC_OFFSET_8821C 0xffff +#define BIT_TSFTR_SNC_OFFSET_8821C(x) (((x) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) << BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) +#define BIT_GET_TSFTR_SNC_OFFSET_8821C(x) (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET_8821C) & BIT_MASK_TSFTR_SNC_OFFSET_8821C) + +/* 2 REG_AGGR_BREAK_TIME_8821C */ + +#define BIT_SHIFT_AGGR_BK_TIME_8821C 0 +#define BIT_MASK_AGGR_BK_TIME_8821C 0xff +#define BIT_AGGR_BK_TIME_8821C(x) (((x) & BIT_MASK_AGGR_BK_TIME_8821C) << BIT_SHIFT_AGGR_BK_TIME_8821C) +#define BIT_GET_AGGR_BK_TIME_8821C(x) (((x) >> BIT_SHIFT_AGGR_BK_TIME_8821C) & BIT_MASK_AGGR_BK_TIME_8821C) + +/* 2 REG_SLOT_8821C */ + +#define BIT_SHIFT_SLOT_8821C 0 +#define BIT_MASK_SLOT_8821C 0xff +#define BIT_SLOT_8821C(x) (((x) & BIT_MASK_SLOT_8821C) << BIT_SHIFT_SLOT_8821C) +#define BIT_GET_SLOT_8821C(x) (((x) >> BIT_SHIFT_SLOT_8821C) & BIT_MASK_SLOT_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_TX_PTCL_CTRL_8821C */ +#define BIT_DIS_EDCCA_8821C BIT(15) +#define BIT_DIS_CCA_8821C BIT(14) +#define BIT_LSIG_TXOP_TXCMD_NAV_8821C BIT(13) +#define BIT_SIFS_BK_EN_8821C BIT(12) + +#define BIT_SHIFT_TXQ_NAV_MSK_8821C 8 +#define BIT_MASK_TXQ_NAV_MSK_8821C 0xf +#define BIT_TXQ_NAV_MSK_8821C(x) (((x) & BIT_MASK_TXQ_NAV_MSK_8821C) << BIT_SHIFT_TXQ_NAV_MSK_8821C) +#define BIT_GET_TXQ_NAV_MSK_8821C(x) (((x) >> BIT_SHIFT_TXQ_NAV_MSK_8821C) & BIT_MASK_TXQ_NAV_MSK_8821C) + +#define BIT_DIS_CW_8821C BIT(7) +#define BIT_NAV_END_TXOP_8821C BIT(6) +#define BIT_RDG_END_TXOP_8821C BIT(5) +#define BIT_AC_INBCN_HOLD_8821C BIT(4) +#define BIT_MGTQ_TXOP_EN_8821C BIT(3) +#define BIT_MGTQ_RTSMF_EN_8821C BIT(2) +#define BIT_HIQ_RTSMF_EN_8821C BIT(1) +#define BIT_BCN_RTSMF_EN_8821C BIT(0) + +/* 2 REG_TXPAUSE_8821C */ +#define BIT_STOP_BCN_HI_MGT_8821C BIT(7) +#define BIT_MAC_STOPBCNQ_8821C BIT(6) +#define BIT_MAC_STOPHIQ_8821C BIT(5) +#define BIT_MAC_STOPMGQ_8821C BIT(4) +#define BIT_MAC_STOPBK_8821C BIT(3) +#define BIT_MAC_STOPBE_8821C BIT(2) +#define BIT_MAC_STOPVI_8821C BIT(1) +#define BIT_MAC_STOPVO_8821C BIT(0) + +/* 2 REG_DIS_TXREQ_CLR_8821C */ +#define BIT_DIS_BT_CCA_8821C BIT(7) +#define BIT_DIS_TXREQ_CLR_HI_8821C BIT(5) +#define BIT_DIS_TXREQ_CLR_MGQ_8821C BIT(4) +#define BIT_DIS_TXREQ_CLR_VO_8821C BIT(3) +#define BIT_DIS_TXREQ_CLR_VI_8821C BIT(2) +#define BIT_DIS_TXREQ_CLR_BE_8821C BIT(1) +#define BIT_DIS_TXREQ_CLR_BK_8821C BIT(0) + +/* 2 REG_RD_CTRL_8821C */ +#define BIT_EN_CLR_TXREQ_INCCA_8821C BIT(15) +#define BIT_DIS_TX_OVER_BCNQ_8821C BIT(14) +#define BIT_EN_BCNERR_INCCCA_8821C BIT(13) +#define BIT_EDCCA_MSK_CNTDOWN_EN_8821C BIT(11) +#define BIT_DIS_TXOP_CFE_8821C BIT(10) +#define BIT_DIS_LSIG_CFE_8821C BIT(9) +#define BIT_DIS_STBC_CFE_8821C BIT(8) +#define BIT_BKQ_RD_INIT_EN_8821C BIT(7) +#define BIT_BEQ_RD_INIT_EN_8821C BIT(6) +#define BIT_VIQ_RD_INIT_EN_8821C BIT(5) +#define BIT_VOQ_RD_INIT_EN_8821C BIT(4) +#define BIT_BKQ_RD_RESP_EN_8821C BIT(3) +#define BIT_BEQ_RD_RESP_EN_8821C BIT(2) +#define BIT_VIQ_RD_RESP_EN_8821C BIT(1) +#define BIT_VOQ_RD_RESP_EN_8821C BIT(0) + +/* 2 REG_MBSSID_CTRL_8821C */ +#define BIT_MBID_BCNQ7_EN_8821C BIT(7) +#define BIT_MBID_BCNQ6_EN_8821C BIT(6) +#define BIT_MBID_BCNQ5_EN_8821C BIT(5) +#define BIT_MBID_BCNQ4_EN_8821C BIT(4) +#define BIT_MBID_BCNQ3_EN_8821C BIT(3) +#define BIT_MBID_BCNQ2_EN_8821C BIT(2) +#define BIT_MBID_BCNQ1_EN_8821C BIT(1) +#define BIT_MBID_BCNQ0_EN_8821C BIT(0) + +/* 2 REG_P2PPS_CTRL_8821C */ +#define BIT_P2P_CTW_ALLSTASLEEP_8821C BIT(7) +#define BIT_P2P_OFF_DISTX_EN_8821C BIT(6) +#define BIT_PWR_MGT_EN_8821C BIT(5) +#define BIT_P2P_NOA1_EN_8821C BIT(2) +#define BIT_P2P_NOA0_EN_8821C BIT(1) + +/* 2 REG_PKT_LIFETIME_CTRL_8821C */ +#define BIT_EN_P2P_CTWND1_8821C BIT(23) +#define BIT_EN_BKF_CLR_TXREQ_8821C BIT(22) +#define BIT_EN_TSFBIT32_RST_P2P_8821C BIT(21) +#define BIT_EN_BCN_TX_BTCCA_8821C BIT(20) +#define BIT_DIS_PKT_TX_ATIM_8821C BIT(19) +#define BIT_DIS_BCN_DIS_CTN_8821C BIT(18) +#define BIT_EN_NAVEND_RST_TXOP_8821C BIT(17) +#define BIT_EN_FILTER_CCA_8821C BIT(16) + +#define BIT_SHIFT_CCA_FILTER_THRS_8821C 8 +#define BIT_MASK_CCA_FILTER_THRS_8821C 0xff +#define BIT_CCA_FILTER_THRS_8821C(x) (((x) & BIT_MASK_CCA_FILTER_THRS_8821C) << BIT_SHIFT_CCA_FILTER_THRS_8821C) +#define BIT_GET_CCA_FILTER_THRS_8821C(x) (((x) >> BIT_SHIFT_CCA_FILTER_THRS_8821C) & BIT_MASK_CCA_FILTER_THRS_8821C) + +#define BIT_SHIFT_EDCCA_THRS_8821C 0 +#define BIT_MASK_EDCCA_THRS_8821C 0xff +#define BIT_EDCCA_THRS_8821C(x) (((x) & BIT_MASK_EDCCA_THRS_8821C) << BIT_SHIFT_EDCCA_THRS_8821C) +#define BIT_GET_EDCCA_THRS_8821C(x) (((x) >> BIT_SHIFT_EDCCA_THRS_8821C) & BIT_MASK_EDCCA_THRS_8821C) + +/* 2 REG_P2PPS_SPEC_STATE_8821C */ +#define BIT_SPEC_POWER_STATE_8821C BIT(7) +#define BIT_SPEC_CTWINDOW_ON_8821C BIT(6) +#define BIT_SPEC_BEACON_AREA_ON_8821C BIT(5) +#define BIT_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4) +#define BIT_SPEC_NOA1_OFF_PERIOD_8821C BIT(3) +#define BIT_SPEC_FORCE_DOZE1_8821C BIT(2) +#define BIT_SPEC_NOA0_OFF_PERIOD_8821C BIT(1) +#define BIT_SPEC_FORCE_DOZE0_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_BAR_TX_CTRL_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +#define BIT_SHIFT_P2PON_DIS_TXTIME_8821C 0 +#define BIT_MASK_P2PON_DIS_TXTIME_8821C 0xff +#define BIT_P2PON_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2PON_DIS_TXTIME_8821C) << BIT_SHIFT_P2PON_DIS_TXTIME_8821C) +#define BIT_GET_P2PON_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME_8821C) & BIT_MASK_P2PON_DIS_TXTIME_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_TBTT_PROHIBIT_8821C */ + +#define BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C 8 +#define BIT_MASK_TBTT_HOLD_TIME_AP_8821C 0xfff +#define BIT_TBTT_HOLD_TIME_AP_8821C(x) (((x) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) << BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) +#define BIT_GET_TBTT_HOLD_TIME_AP_8821C(x) (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP_8821C) & BIT_MASK_TBTT_HOLD_TIME_AP_8821C) + +#define BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C 0 +#define BIT_MASK_TBTT_PROHIBIT_SETUP_8821C 0xf +#define BIT_TBTT_PROHIBIT_SETUP_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) << BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) +#define BIT_GET_TBTT_PROHIBIT_SETUP_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP_8821C) & BIT_MASK_TBTT_PROHIBIT_SETUP_8821C) + +/* 2 REG_P2PPS_STATE_8821C */ +#define BIT_POWER_STATE_8821C BIT(7) +#define BIT_CTWINDOW_ON_8821C BIT(6) +#define BIT_BEACON_AREA_ON_8821C BIT(5) +#define BIT_CTWIN_EARLY_DISTX_8821C BIT(4) +#define BIT_NOA1_OFF_PERIOD_8821C BIT(3) +#define BIT_FORCE_DOZE1_8821C BIT(2) +#define BIT_NOA0_OFF_PERIOD_8821C BIT(1) +#define BIT_FORCE_DOZE0_8821C BIT(0) + +/* 2 REG_RD_NAV_NXT_8821C */ + +#define BIT_SHIFT_RD_NAV_PROT_NXT_8821C 0 +#define BIT_MASK_RD_NAV_PROT_NXT_8821C 0xffff +#define BIT_RD_NAV_PROT_NXT_8821C(x) (((x) & BIT_MASK_RD_NAV_PROT_NXT_8821C) << BIT_SHIFT_RD_NAV_PROT_NXT_8821C) +#define BIT_GET_RD_NAV_PROT_NXT_8821C(x) (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT_8821C) & BIT_MASK_RD_NAV_PROT_NXT_8821C) + +/* 2 REG_NAV_PROT_LEN_8821C */ + +#define BIT_SHIFT_NAV_PROT_LEN_8821C 0 +#define BIT_MASK_NAV_PROT_LEN_8821C 0xffff +#define BIT_NAV_PROT_LEN_8821C(x) (((x) & BIT_MASK_NAV_PROT_LEN_8821C) << BIT_SHIFT_NAV_PROT_LEN_8821C) +#define BIT_GET_NAV_PROT_LEN_8821C(x) (((x) >> BIT_SHIFT_NAV_PROT_LEN_8821C) & BIT_MASK_NAV_PROT_LEN_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_BCN_CTRL_8821C */ +#define BIT_DIS_RX_BSSID_FIT_8821C BIT(6) +#define BIT_P0_EN_TXBCN_RPT_8821C BIT(5) +#define BIT_DIS_TSF_UDT_8821C BIT(4) +#define BIT_EN_BCN_FUNCTION_8821C BIT(3) +#define BIT_P0_EN_RXBCN_RPT_8821C BIT(2) +#define BIT_EN_P2P_CTWINDOW_8821C BIT(1) +#define BIT_EN_P2P_BCNQ_AREA_8821C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT0_8821C */ +#define BIT_CLI0_DIS_RX_BSSID_FIT_8821C BIT(6) +#define BIT_CLI0_DIS_TSF_UDT_8821C BIT(4) +#define BIT_CLI0_EN_BCN_FUNCTION_8821C BIT(3) +#define BIT_CLI0_EN_RXBCN_RPT_8821C BIT(2) +#define BIT_CLI0_ENP2P_CTWINDOW_8821C BIT(1) +#define BIT_CLI0_ENP2P_BCNQ_AREA_8821C BIT(0) + +/* 2 REG_MBID_NUM_8821C */ +#define BIT_EN_PRE_DL_BEACON_8821C BIT(3) + +#define BIT_SHIFT_MBID_BCN_NUM_8821C 0 +#define BIT_MASK_MBID_BCN_NUM_8821C 0x7 +#define BIT_MBID_BCN_NUM_8821C(x) (((x) & BIT_MASK_MBID_BCN_NUM_8821C) << BIT_SHIFT_MBID_BCN_NUM_8821C) +#define BIT_GET_MBID_BCN_NUM_8821C(x) (((x) >> BIT_SHIFT_MBID_BCN_NUM_8821C) & BIT_MASK_MBID_BCN_NUM_8821C) + +/* 2 REG_DUAL_TSF_RST_8821C */ +#define BIT_FREECNT_RST_8821C BIT(5) +#define BIT_TSFTR_CLI3_RST_8821C BIT(4) +#define BIT_TSFTR_CLI2_RST_8821C BIT(3) +#define BIT_TSFTR_CLI1_RST_8821C BIT(2) +#define BIT_TSFTR_CLI0_RST_8821C BIT(1) +#define BIT_TSFTR_RST_8821C BIT(0) + +/* 2 REG_MBSSID_BCN_SPACE_8821C */ + +#define BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C 28 +#define BIT_MASK_BCN_TIMER_SEL_FWRD_8821C 0x7 +#define BIT_BCN_TIMER_SEL_FWRD_8821C(x) (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) << BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) +#define BIT_GET_BCN_TIMER_SEL_FWRD_8821C(x) (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD_8821C) & BIT_MASK_BCN_TIMER_SEL_FWRD_8821C) + +#define BIT_SHIFT_BCN_SPACE_CLINT0_8821C 16 +#define BIT_MASK_BCN_SPACE_CLINT0_8821C 0xfff +#define BIT_BCN_SPACE_CLINT0_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT0_8821C) << BIT_SHIFT_BCN_SPACE_CLINT0_8821C) +#define BIT_GET_BCN_SPACE_CLINT0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0_8821C) & BIT_MASK_BCN_SPACE_CLINT0_8821C) + +#define BIT_SHIFT_BCN_SPACE0_8821C 0 +#define BIT_MASK_BCN_SPACE0_8821C 0xffff +#define BIT_BCN_SPACE0_8821C(x) (((x) & BIT_MASK_BCN_SPACE0_8821C) << BIT_SHIFT_BCN_SPACE0_8821C) +#define BIT_GET_BCN_SPACE0_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE0_8821C) & BIT_MASK_BCN_SPACE0_8821C) + +/* 2 REG_DRVERLYINT_8821C */ + +#define BIT_SHIFT_DRVERLYITV_8821C 0 +#define BIT_MASK_DRVERLYITV_8821C 0xff +#define BIT_DRVERLYITV_8821C(x) (((x) & BIT_MASK_DRVERLYITV_8821C) << BIT_SHIFT_DRVERLYITV_8821C) +#define BIT_GET_DRVERLYITV_8821C(x) (((x) >> BIT_SHIFT_DRVERLYITV_8821C) & BIT_MASK_DRVERLYITV_8821C) + +/* 2 REG_BCNDMATIM_8821C */ + +#define BIT_SHIFT_BCNDMATIM_8821C 0 +#define BIT_MASK_BCNDMATIM_8821C 0xff +#define BIT_BCNDMATIM_8821C(x) (((x) & BIT_MASK_BCNDMATIM_8821C) << BIT_SHIFT_BCNDMATIM_8821C) +#define BIT_GET_BCNDMATIM_8821C(x) (((x) >> BIT_SHIFT_BCNDMATIM_8821C) & BIT_MASK_BCNDMATIM_8821C) + +/* 2 REG_ATIMWND_8821C */ + +#define BIT_SHIFT_ATIMWND0_8821C 0 +#define BIT_MASK_ATIMWND0_8821C 0xffff +#define BIT_ATIMWND0_8821C(x) (((x) & BIT_MASK_ATIMWND0_8821C) << BIT_SHIFT_ATIMWND0_8821C) +#define BIT_GET_ATIMWND0_8821C(x) (((x) >> BIT_SHIFT_ATIMWND0_8821C) & BIT_MASK_ATIMWND0_8821C) + +/* 2 REG_USTIME_TSF_8821C */ + +#define BIT_SHIFT_USTIME_TSF_V1_8821C 0 +#define BIT_MASK_USTIME_TSF_V1_8821C 0xff +#define BIT_USTIME_TSF_V1_8821C(x) (((x) & BIT_MASK_USTIME_TSF_V1_8821C) << BIT_SHIFT_USTIME_TSF_V1_8821C) +#define BIT_GET_USTIME_TSF_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_TSF_V1_8821C) & BIT_MASK_USTIME_TSF_V1_8821C) + +/* 2 REG_BCN_MAX_ERR_8821C */ + +#define BIT_SHIFT_BCN_MAX_ERR_8821C 0 +#define BIT_MASK_BCN_MAX_ERR_8821C 0xff +#define BIT_BCN_MAX_ERR_8821C(x) (((x) & BIT_MASK_BCN_MAX_ERR_8821C) << BIT_SHIFT_BCN_MAX_ERR_8821C) +#define BIT_GET_BCN_MAX_ERR_8821C(x) (((x) >> BIT_SHIFT_BCN_MAX_ERR_8821C) & BIT_MASK_BCN_MAX_ERR_8821C) + +/* 2 REG_RXTSF_OFFSET_CCK_8821C */ + +#define BIT_SHIFT_CCK_RXTSF_OFFSET_8821C 0 +#define BIT_MASK_CCK_RXTSF_OFFSET_8821C 0xff +#define BIT_CCK_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) << BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) +#define BIT_GET_CCK_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET_8821C) & BIT_MASK_CCK_RXTSF_OFFSET_8821C) + +/* 2 REG_RXTSF_OFFSET_OFDM_8821C */ + +#define BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C 0 +#define BIT_MASK_OFDM_RXTSF_OFFSET_8821C 0xff +#define BIT_OFDM_RXTSF_OFFSET_8821C(x) (((x) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) << BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) +#define BIT_GET_OFDM_RXTSF_OFFSET_8821C(x) (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET_8821C) & BIT_MASK_OFDM_RXTSF_OFFSET_8821C) + +/* 2 REG_TSFTR_8821C */ + +#define BIT_SHIFT_TSF_TIMER_V1_8821C 0 +#define BIT_MASK_TSF_TIMER_V1_8821C 0xffffffffL +#define BIT_TSF_TIMER_V1_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V1_8821C) << BIT_SHIFT_TSF_TIMER_V1_8821C) +#define BIT_GET_TSF_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V1_8821C) & BIT_MASK_TSF_TIMER_V1_8821C) + +/* 2 REG_TSFTR_1_8821C */ + +#define BIT_SHIFT_TSF_TIMER_V2_8821C 0 +#define BIT_MASK_TSF_TIMER_V2_8821C 0xffffffffL +#define BIT_TSF_TIMER_V2_8821C(x) (((x) & BIT_MASK_TSF_TIMER_V2_8821C) << BIT_SHIFT_TSF_TIMER_V2_8821C) +#define BIT_GET_TSF_TIMER_V2_8821C(x) (((x) >> BIT_SHIFT_TSF_TIMER_V2_8821C) & BIT_MASK_TSF_TIMER_V2_8821C) + +/* 2 REG_FREERUN_CNT_8821C */ + +#define BIT_SHIFT_FREERUN_CNT_V1_8821C 0 +#define BIT_MASK_FREERUN_CNT_V1_8821C 0xffffffffL +#define BIT_FREERUN_CNT_V1_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V1_8821C) << BIT_SHIFT_FREERUN_CNT_V1_8821C) +#define BIT_GET_FREERUN_CNT_V1_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V1_8821C) & BIT_MASK_FREERUN_CNT_V1_8821C) + +/* 2 REG_FREERUN_CNT_1_8821C */ + +#define BIT_SHIFT_FREERUN_CNT_V2_8821C 0 +#define BIT_MASK_FREERUN_CNT_V2_8821C 0xffffffffL +#define BIT_FREERUN_CNT_V2_8821C(x) (((x) & BIT_MASK_FREERUN_CNT_V2_8821C) << BIT_SHIFT_FREERUN_CNT_V2_8821C) +#define BIT_GET_FREERUN_CNT_V2_8821C(x) (((x) >> BIT_SHIFT_FREERUN_CNT_V2_8821C) & BIT_MASK_FREERUN_CNT_V2_8821C) + +/* 2 REG_ATIMWND1_V1_8821C */ + +#define BIT_SHIFT_ATIMWND1_V1_8821C 0 +#define BIT_MASK_ATIMWND1_V1_8821C 0xff +#define BIT_ATIMWND1_V1_8821C(x) (((x) & BIT_MASK_ATIMWND1_V1_8821C) << BIT_SHIFT_ATIMWND1_V1_8821C) +#define BIT_GET_ATIMWND1_V1_8821C(x) (((x) >> BIT_SHIFT_ATIMWND1_V1_8821C) & BIT_MASK_ATIMWND1_V1_8821C) + +/* 2 REG_TBTT_PROHIBIT_INFRA_8821C */ + +#define BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C 0 +#define BIT_MASK_TBTT_PROHIBIT_INFRA_8821C 0xff +#define BIT_TBTT_PROHIBIT_INFRA_8821C(x) (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) << BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) +#define BIT_GET_TBTT_PROHIBIT_INFRA_8821C(x) (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA_8821C) & BIT_MASK_TBTT_PROHIBIT_INFRA_8821C) + +/* 2 REG_CTWND_8821C */ + +#define BIT_SHIFT_CTWND_8821C 0 +#define BIT_MASK_CTWND_8821C 0xff +#define BIT_CTWND_8821C(x) (((x) & BIT_MASK_CTWND_8821C) << BIT_SHIFT_CTWND_8821C) +#define BIT_GET_CTWND_8821C(x) (((x) >> BIT_SHIFT_CTWND_8821C) & BIT_MASK_CTWND_8821C) + +/* 2 REG_BCNIVLCUNT_8821C */ + +#define BIT_SHIFT_BCNIVLCUNT_8821C 0 +#define BIT_MASK_BCNIVLCUNT_8821C 0x7f +#define BIT_BCNIVLCUNT_8821C(x) (((x) & BIT_MASK_BCNIVLCUNT_8821C) << BIT_SHIFT_BCNIVLCUNT_8821C) +#define BIT_GET_BCNIVLCUNT_8821C(x) (((x) >> BIT_SHIFT_BCNIVLCUNT_8821C) & BIT_MASK_BCNIVLCUNT_8821C) + +/* 2 REG_BCNDROPCTRL_8821C */ +#define BIT_BEACON_DROP_EN_8821C BIT(7) + +#define BIT_SHIFT_BEACON_DROP_IVL_8821C 0 +#define BIT_MASK_BEACON_DROP_IVL_8821C 0x7f +#define BIT_BEACON_DROP_IVL_8821C(x) (((x) & BIT_MASK_BEACON_DROP_IVL_8821C) << BIT_SHIFT_BEACON_DROP_IVL_8821C) +#define BIT_GET_BEACON_DROP_IVL_8821C(x) (((x) >> BIT_SHIFT_BEACON_DROP_IVL_8821C) & BIT_MASK_BEACON_DROP_IVL_8821C) + +/* 2 REG_HGQ_TIMEOUT_PERIOD_8821C */ + +#define BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C 0 +#define BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C 0xff +#define BIT_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) +#define BIT_GET_HGQ_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD_8821C) & BIT_MASK_HGQ_TIMEOUT_PERIOD_8821C) + +/* 2 REG_TXCMD_TIMEOUT_PERIOD_8821C */ + +#define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C 0 +#define BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C 0xff +#define BIT_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) +#define BIT_GET_TXCMD_TIMEOUT_PERIOD_8821C(x) (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD_8821C) & BIT_MASK_TXCMD_TIMEOUT_PERIOD_8821C) + +/* 2 REG_MISC_CTRL_8821C */ +#define BIT_DIS_TRX_CAL_BCN_8821C BIT(5) +#define BIT_DIS_TX_CAL_TBTT_8821C BIT(4) +#define BIT_EN_FREECNT_8821C BIT(3) +#define BIT_BCN_AGGRESSION_8821C BIT(2) + +#define BIT_SHIFT_DIS_SECONDARY_CCA_8821C 0 +#define BIT_MASK_DIS_SECONDARY_CCA_8821C 0x3 +#define BIT_DIS_SECONDARY_CCA_8821C(x) (((x) & BIT_MASK_DIS_SECONDARY_CCA_8821C) << BIT_SHIFT_DIS_SECONDARY_CCA_8821C) +#define BIT_GET_DIS_SECONDARY_CCA_8821C(x) (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA_8821C) & BIT_MASK_DIS_SECONDARY_CCA_8821C) + +/* 2 REG_BCN_CTRL_CLINT1_8821C */ +#define BIT_CLI1_DIS_RX_BSSID_FIT_8821C BIT(6) +#define BIT_CLI1_DIS_TSF_UDT_8821C BIT(4) +#define BIT_CLI1_EN_BCN_FUNCTION_8821C BIT(3) +#define BIT_CLI1_EN_RXBCN_RPT_8821C BIT(2) +#define BIT_CLI1_ENP2P_CTWINDOW_8821C BIT(1) +#define BIT_CLI1_ENP2P_BCNQ_AREA_8821C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT2_8821C */ +#define BIT_CLI2_DIS_RX_BSSID_FIT_8821C BIT(6) +#define BIT_CLI2_DIS_TSF_UDT_8821C BIT(4) +#define BIT_CLI2_EN_BCN_FUNCTION_8821C BIT(3) +#define BIT_CLI2_EN_RXBCN_RPT_8821C BIT(2) +#define BIT_CLI2_ENP2P_CTWINDOW_8821C BIT(1) +#define BIT_CLI2_ENP2P_BCNQ_AREA_8821C BIT(0) + +/* 2 REG_BCN_CTRL_CLINT3_8821C */ +#define BIT_CLI3_DIS_RX_BSSID_FIT_8821C BIT(6) +#define BIT_CLI3_DIS_TSF_UDT_8821C BIT(4) +#define BIT_CLI3_EN_BCN_FUNCTION_8821C BIT(3) +#define BIT_CLI3_EN_RXBCN_RPT_8821C BIT(2) +#define BIT_CLI3_ENP2P_CTWINDOW_8821C BIT(1) +#define BIT_CLI3_ENP2P_BCNQ_AREA_8821C BIT(0) + +/* 2 REG_EXTEND_CTRL_8821C */ +#define BIT_EN_TSFBIT32_RST_P2P2_8821C BIT(5) +#define BIT_EN_TSFBIT32_RST_P2P1_8821C BIT(4) + +#define BIT_SHIFT_PORT_SEL_8821C 0 +#define BIT_MASK_PORT_SEL_8821C 0x7 +#define BIT_PORT_SEL_8821C(x) (((x) & BIT_MASK_PORT_SEL_8821C) << BIT_SHIFT_PORT_SEL_8821C) +#define BIT_GET_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_PORT_SEL_8821C) & BIT_MASK_PORT_SEL_8821C) + +/* 2 REG_P2PPS1_SPEC_STATE_8821C */ +#define BIT_P2P1_SPEC_POWER_STATE_8821C BIT(7) +#define BIT_P2P1_SPEC_CTWINDOW_ON_8821C BIT(6) +#define BIT_P2P1_SPEC_BCN_AREA_ON_8821C BIT(5) +#define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4) +#define BIT_P2P1_SPEC_NOA1_OFF_PERIOD_8821C BIT(3) +#define BIT_P2P1_SPEC_FORCE_DOZE1_8821C BIT(2) +#define BIT_P2P1_SPEC_NOA0_OFF_PERIOD_8821C BIT(1) +#define BIT_P2P1_SPEC_FORCE_DOZE0_8821C BIT(0) + +/* 2 REG_P2PPS1_STATE_8821C */ +#define BIT_P2P1_POWER_STATE_8821C BIT(7) +#define BIT_P2P1_CTWINDOW_ON_8821C BIT(6) +#define BIT_P2P1_BEACON_AREA_ON_8821C BIT(5) +#define BIT_P2P1_CTWIN_EARLY_DISTX_8821C BIT(4) +#define BIT_P2P1_NOA1_OFF_PERIOD_8821C BIT(3) +#define BIT_P2P1_FORCE_DOZE1_8821C BIT(2) +#define BIT_P2P1_NOA0_OFF_PERIOD_8821C BIT(1) +#define BIT_P2P1_FORCE_DOZE0_8821C BIT(0) + +/* 2 REG_P2PPS2_SPEC_STATE_8821C */ +#define BIT_P2P2_SPEC_POWER_STATE_8821C BIT(7) +#define BIT_P2P2_SPEC_CTWINDOW_ON_8821C BIT(6) +#define BIT_P2P2_SPEC_BCN_AREA_ON_8821C BIT(5) +#define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX_8821C BIT(4) +#define BIT_P2P2_SPEC_NOA1_OFF_PERIOD_8821C BIT(3) +#define BIT_P2P2_SPEC_FORCE_DOZE1_8821C BIT(2) +#define BIT_P2P2_SPEC_NOA0_OFF_PERIOD_8821C BIT(1) +#define BIT_P2P2_SPEC_FORCE_DOZE0_8821C BIT(0) + +/* 2 REG_P2PPS2_STATE_8821C */ +#define BIT_P2P2_POWER_STATE_8821C BIT(7) +#define BIT_P2P2_CTWINDOW_ON_8821C BIT(6) +#define BIT_P2P2_BEACON_AREA_ON_8821C BIT(5) +#define BIT_P2P2_CTWIN_EARLY_DISTX_8821C BIT(4) +#define BIT_P2P2_NOA1_OFF_PERIOD_8821C BIT(3) +#define BIT_P2P2_FORCE_DOZE1_8821C BIT(2) +#define BIT_P2P2_NOA0_OFF_PERIOD_8821C BIT(1) +#define BIT_P2P2_FORCE_DOZE0_8821C BIT(0) + +/* 2 REG_PS_TIMER0_8821C */ + +#define BIT_SHIFT_PSTIMER0_INT_8821C 5 +#define BIT_MASK_PSTIMER0_INT_8821C 0x7ffffff +#define BIT_PSTIMER0_INT_8821C(x) (((x) & BIT_MASK_PSTIMER0_INT_8821C) << BIT_SHIFT_PSTIMER0_INT_8821C) +#define BIT_GET_PSTIMER0_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER0_INT_8821C) & BIT_MASK_PSTIMER0_INT_8821C) + +/* 2 REG_PS_TIMER1_8821C */ + +#define BIT_SHIFT_PSTIMER1_INT_8821C 5 +#define BIT_MASK_PSTIMER1_INT_8821C 0x7ffffff +#define BIT_PSTIMER1_INT_8821C(x) (((x) & BIT_MASK_PSTIMER1_INT_8821C) << BIT_SHIFT_PSTIMER1_INT_8821C) +#define BIT_GET_PSTIMER1_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER1_INT_8821C) & BIT_MASK_PSTIMER1_INT_8821C) + +/* 2 REG_PS_TIMER2_8821C */ + +#define BIT_SHIFT_PSTIMER2_INT_8821C 5 +#define BIT_MASK_PSTIMER2_INT_8821C 0x7ffffff +#define BIT_PSTIMER2_INT_8821C(x) (((x) & BIT_MASK_PSTIMER2_INT_8821C) << BIT_SHIFT_PSTIMER2_INT_8821C) +#define BIT_GET_PSTIMER2_INT_8821C(x) (((x) >> BIT_SHIFT_PSTIMER2_INT_8821C) & BIT_MASK_PSTIMER2_INT_8821C) + +/* 2 REG_TBTT_CTN_AREA_8821C */ + +#define BIT_SHIFT_TBTT_CTN_AREA_8821C 0 +#define BIT_MASK_TBTT_CTN_AREA_8821C 0xff +#define BIT_TBTT_CTN_AREA_8821C(x) (((x) & BIT_MASK_TBTT_CTN_AREA_8821C) << BIT_SHIFT_TBTT_CTN_AREA_8821C) +#define BIT_GET_TBTT_CTN_AREA_8821C(x) (((x) >> BIT_SHIFT_TBTT_CTN_AREA_8821C) & BIT_MASK_TBTT_CTN_AREA_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_FORCE_BCN_IFS_8821C */ + +#define BIT_SHIFT_FORCE_BCN_IFS_8821C 0 +#define BIT_MASK_FORCE_BCN_IFS_8821C 0xff +#define BIT_FORCE_BCN_IFS_8821C(x) (((x) & BIT_MASK_FORCE_BCN_IFS_8821C) << BIT_SHIFT_FORCE_BCN_IFS_8821C) +#define BIT_GET_FORCE_BCN_IFS_8821C(x) (((x) >> BIT_SHIFT_FORCE_BCN_IFS_8821C) & BIT_MASK_FORCE_BCN_IFS_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_TXOP_MIN_8821C */ + +#define BIT_SHIFT_TXOP_MIN_8821C 0 +#define BIT_MASK_TXOP_MIN_8821C 0x3fff +#define BIT_TXOP_MIN_8821C(x) (((x) & BIT_MASK_TXOP_MIN_8821C) << BIT_SHIFT_TXOP_MIN_8821C) +#define BIT_GET_TXOP_MIN_8821C(x) (((x) >> BIT_SHIFT_TXOP_MIN_8821C) & BIT_MASK_TXOP_MIN_8821C) + +/* 2 REG_PRE_BKF_TIME_8821C */ + +#define BIT_SHIFT_PRE_BKF_TIME_8821C 0 +#define BIT_MASK_PRE_BKF_TIME_8821C 0xff +#define BIT_PRE_BKF_TIME_8821C(x) (((x) & BIT_MASK_PRE_BKF_TIME_8821C) << BIT_SHIFT_PRE_BKF_TIME_8821C) +#define BIT_GET_PRE_BKF_TIME_8821C(x) (((x) >> BIT_SHIFT_PRE_BKF_TIME_8821C) & BIT_MASK_PRE_BKF_TIME_8821C) + +/* 2 REG_CROSS_TXOP_CTRL_8821C */ +#define BIT_TXFAIL_BREACK_TXOP_EN_8821C BIT(3) +#define BIT_DTIM_BYPASS_8821C BIT(2) +#define BIT_RTS_NAV_TXOP_8821C BIT(1) +#define BIT_NOT_CROSS_TXOP_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_ATIMWND2_8821C */ + +#define BIT_SHIFT_ATIMWND2_8821C 0 +#define BIT_MASK_ATIMWND2_8821C 0xff +#define BIT_ATIMWND2_8821C(x) (((x) & BIT_MASK_ATIMWND2_8821C) << BIT_SHIFT_ATIMWND2_8821C) +#define BIT_GET_ATIMWND2_8821C(x) (((x) >> BIT_SHIFT_ATIMWND2_8821C) & BIT_MASK_ATIMWND2_8821C) + +/* 2 REG_ATIMWND3_8821C */ + +#define BIT_SHIFT_ATIMWND3_8821C 0 +#define BIT_MASK_ATIMWND3_8821C 0xff +#define BIT_ATIMWND3_8821C(x) (((x) & BIT_MASK_ATIMWND3_8821C) << BIT_SHIFT_ATIMWND3_8821C) +#define BIT_GET_ATIMWND3_8821C(x) (((x) >> BIT_SHIFT_ATIMWND3_8821C) & BIT_MASK_ATIMWND3_8821C) + +/* 2 REG_ATIMWND4_8821C */ + +#define BIT_SHIFT_ATIMWND4_8821C 0 +#define BIT_MASK_ATIMWND4_8821C 0xff +#define BIT_ATIMWND4_8821C(x) (((x) & BIT_MASK_ATIMWND4_8821C) << BIT_SHIFT_ATIMWND4_8821C) +#define BIT_GET_ATIMWND4_8821C(x) (((x) >> BIT_SHIFT_ATIMWND4_8821C) & BIT_MASK_ATIMWND4_8821C) + +/* 2 REG_ATIMWND5_8821C */ + +#define BIT_SHIFT_ATIMWND5_8821C 0 +#define BIT_MASK_ATIMWND5_8821C 0xff +#define BIT_ATIMWND5_8821C(x) (((x) & BIT_MASK_ATIMWND5_8821C) << BIT_SHIFT_ATIMWND5_8821C) +#define BIT_GET_ATIMWND5_8821C(x) (((x) >> BIT_SHIFT_ATIMWND5_8821C) & BIT_MASK_ATIMWND5_8821C) + +/* 2 REG_ATIMWND6_8821C */ + +#define BIT_SHIFT_ATIMWND6_8821C 0 +#define BIT_MASK_ATIMWND6_8821C 0xff +#define BIT_ATIMWND6_8821C(x) (((x) & BIT_MASK_ATIMWND6_8821C) << BIT_SHIFT_ATIMWND6_8821C) +#define BIT_GET_ATIMWND6_8821C(x) (((x) >> BIT_SHIFT_ATIMWND6_8821C) & BIT_MASK_ATIMWND6_8821C) + +/* 2 REG_ATIMWND7_8821C */ + +#define BIT_SHIFT_ATIMWND7_8821C 0 +#define BIT_MASK_ATIMWND7_8821C 0xff +#define BIT_ATIMWND7_8821C(x) (((x) & BIT_MASK_ATIMWND7_8821C) << BIT_SHIFT_ATIMWND7_8821C) +#define BIT_GET_ATIMWND7_8821C(x) (((x) >> BIT_SHIFT_ATIMWND7_8821C) & BIT_MASK_ATIMWND7_8821C) + +/* 2 REG_ATIMUGT_8821C */ + +#define BIT_SHIFT_ATIM_URGENT_8821C 0 +#define BIT_MASK_ATIM_URGENT_8821C 0xff +#define BIT_ATIM_URGENT_8821C(x) (((x) & BIT_MASK_ATIM_URGENT_8821C) << BIT_SHIFT_ATIM_URGENT_8821C) +#define BIT_GET_ATIM_URGENT_8821C(x) (((x) >> BIT_SHIFT_ATIM_URGENT_8821C) & BIT_MASK_ATIM_URGENT_8821C) + +/* 2 REG_HIQ_NO_LMT_EN_8821C */ +#define BIT_HIQ_NO_LMT_EN_VAP7_8821C BIT(7) +#define BIT_HIQ_NO_LMT_EN_VAP6_8821C BIT(6) +#define BIT_HIQ_NO_LMT_EN_VAP5_8821C BIT(5) +#define BIT_HIQ_NO_LMT_EN_VAP4_8821C BIT(4) +#define BIT_HIQ_NO_LMT_EN_VAP3_8821C BIT(3) +#define BIT_HIQ_NO_LMT_EN_VAP2_8821C BIT(2) +#define BIT_HIQ_NO_LMT_EN_VAP1_8821C BIT(1) +#define BIT_HIQ_NO_LMT_EN_ROOT_8821C BIT(0) + +/* 2 REG_DTIM_COUNTER_ROOT_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_ROOT_8821C 0 +#define BIT_MASK_DTIM_COUNT_ROOT_8821C 0xff +#define BIT_DTIM_COUNT_ROOT_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_ROOT_8821C) << BIT_SHIFT_DTIM_COUNT_ROOT_8821C) +#define BIT_GET_DTIM_COUNT_ROOT_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT_8821C) & BIT_MASK_DTIM_COUNT_ROOT_8821C) + +/* 2 REG_DTIM_COUNTER_VAP1_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP1_8821C 0 +#define BIT_MASK_DTIM_COUNT_VAP1_8821C 0xff +#define BIT_DTIM_COUNT_VAP1_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP1_8821C) << BIT_SHIFT_DTIM_COUNT_VAP1_8821C) +#define BIT_GET_DTIM_COUNT_VAP1_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1_8821C) & BIT_MASK_DTIM_COUNT_VAP1_8821C) + +/* 2 REG_DTIM_COUNTER_VAP2_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP2_8821C 0 +#define BIT_MASK_DTIM_COUNT_VAP2_8821C 0xff +#define BIT_DTIM_COUNT_VAP2_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP2_8821C) << BIT_SHIFT_DTIM_COUNT_VAP2_8821C) +#define BIT_GET_DTIM_COUNT_VAP2_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2_8821C) & BIT_MASK_DTIM_COUNT_VAP2_8821C) + +/* 2 REG_DTIM_COUNTER_VAP3_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP3_8821C 0 +#define BIT_MASK_DTIM_COUNT_VAP3_8821C 0xff +#define BIT_DTIM_COUNT_VAP3_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP3_8821C) << BIT_SHIFT_DTIM_COUNT_VAP3_8821C) +#define BIT_GET_DTIM_COUNT_VAP3_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3_8821C) & BIT_MASK_DTIM_COUNT_VAP3_8821C) + +/* 2 REG_DTIM_COUNTER_VAP4_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP4_8821C 0 +#define BIT_MASK_DTIM_COUNT_VAP4_8821C 0xff +#define BIT_DTIM_COUNT_VAP4_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP4_8821C) << BIT_SHIFT_DTIM_COUNT_VAP4_8821C) +#define BIT_GET_DTIM_COUNT_VAP4_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4_8821C) & BIT_MASK_DTIM_COUNT_VAP4_8821C) + +/* 2 REG_DTIM_COUNTER_VAP5_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP5_8821C 0 +#define BIT_MASK_DTIM_COUNT_VAP5_8821C 0xff +#define BIT_DTIM_COUNT_VAP5_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP5_8821C) << BIT_SHIFT_DTIM_COUNT_VAP5_8821C) +#define BIT_GET_DTIM_COUNT_VAP5_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5_8821C) & BIT_MASK_DTIM_COUNT_VAP5_8821C) + +/* 2 REG_DTIM_COUNTER_VAP6_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP6_8821C 0 +#define BIT_MASK_DTIM_COUNT_VAP6_8821C 0xff +#define BIT_DTIM_COUNT_VAP6_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP6_8821C) << BIT_SHIFT_DTIM_COUNT_VAP6_8821C) +#define BIT_GET_DTIM_COUNT_VAP6_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6_8821C) & BIT_MASK_DTIM_COUNT_VAP6_8821C) + +/* 2 REG_DTIM_COUNTER_VAP7_8821C */ + +#define BIT_SHIFT_DTIM_COUNT_VAP7_8821C 0 +#define BIT_MASK_DTIM_COUNT_VAP7_8821C 0xff +#define BIT_DTIM_COUNT_VAP7_8821C(x) (((x) & BIT_MASK_DTIM_COUNT_VAP7_8821C) << BIT_SHIFT_DTIM_COUNT_VAP7_8821C) +#define BIT_GET_DTIM_COUNT_VAP7_8821C(x) (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7_8821C) & BIT_MASK_DTIM_COUNT_VAP7_8821C) + +/* 2 REG_DIS_ATIM_8821C */ +#define BIT_DIS_ATIM_VAP7_8821C BIT(7) +#define BIT_DIS_ATIM_VAP6_8821C BIT(6) +#define BIT_DIS_ATIM_VAP5_8821C BIT(5) +#define BIT_DIS_ATIM_VAP4_8821C BIT(4) +#define BIT_DIS_ATIM_VAP3_8821C BIT(3) +#define BIT_DIS_ATIM_VAP2_8821C BIT(2) +#define BIT_DIS_ATIM_VAP1_8821C BIT(1) +#define BIT_DIS_ATIM_ROOT_8821C BIT(0) + +/* 2 REG_EARLY_128US_8821C */ + +#define BIT_SHIFT_TSFT_SEL_TIMER1_8821C 3 +#define BIT_MASK_TSFT_SEL_TIMER1_8821C 0x7 +#define BIT_TSFT_SEL_TIMER1_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER1_8821C) << BIT_SHIFT_TSFT_SEL_TIMER1_8821C) +#define BIT_GET_TSFT_SEL_TIMER1_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1_8821C) & BIT_MASK_TSFT_SEL_TIMER1_8821C) + +#define BIT_SHIFT_EARLY_128US_8821C 0 +#define BIT_MASK_EARLY_128US_8821C 0x7 +#define BIT_EARLY_128US_8821C(x) (((x) & BIT_MASK_EARLY_128US_8821C) << BIT_SHIFT_EARLY_128US_8821C) +#define BIT_GET_EARLY_128US_8821C(x) (((x) >> BIT_SHIFT_EARLY_128US_8821C) & BIT_MASK_EARLY_128US_8821C) + +/* 2 REG_P2PPS1_CTRL_8821C */ +#define BIT_P2P1_CTW_ALLSTASLEEP_8821C BIT(7) +#define BIT_P2P1_OFF_DISTX_EN_8821C BIT(6) +#define BIT_P2P1_PWR_MGT_EN_8821C BIT(5) +#define BIT_P2P1_NOA1_EN_8821C BIT(2) +#define BIT_P2P1_NOA0_EN_8821C BIT(1) + +/* 2 REG_P2PPS2_CTRL_8821C */ +#define BIT_P2P2_CTW_ALLSTASLEEP_8821C BIT(7) +#define BIT_P2P2_OFF_DISTX_EN_8821C BIT(6) +#define BIT_P2P2_PWR_MGT_EN_8821C BIT(5) +#define BIT_P2P2_NOA1_EN_8821C BIT(2) +#define BIT_P2P2_NOA0_EN_8821C BIT(1) + +/* 2 REG_TIMER0_SRC_SEL_8821C */ + +#define BIT_SHIFT_SYNC_CLI_SEL_8821C 4 +#define BIT_MASK_SYNC_CLI_SEL_8821C 0x7 +#define BIT_SYNC_CLI_SEL_8821C(x) (((x) & BIT_MASK_SYNC_CLI_SEL_8821C) << BIT_SHIFT_SYNC_CLI_SEL_8821C) +#define BIT_GET_SYNC_CLI_SEL_8821C(x) (((x) >> BIT_SHIFT_SYNC_CLI_SEL_8821C) & BIT_MASK_SYNC_CLI_SEL_8821C) + +#define BIT_SHIFT_TSFT_SEL_TIMER0_8821C 0 +#define BIT_MASK_TSFT_SEL_TIMER0_8821C 0x7 +#define BIT_TSFT_SEL_TIMER0_8821C(x) (((x) & BIT_MASK_TSFT_SEL_TIMER0_8821C) << BIT_SHIFT_TSFT_SEL_TIMER0_8821C) +#define BIT_GET_TSFT_SEL_TIMER0_8821C(x) (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0_8821C) & BIT_MASK_TSFT_SEL_TIMER0_8821C) + +/* 2 REG_NOA_UNIT_SEL_8821C */ + +#define BIT_SHIFT_NOA_UNIT2_SEL_8821C 8 +#define BIT_MASK_NOA_UNIT2_SEL_8821C 0x7 +#define BIT_NOA_UNIT2_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT2_SEL_8821C) << BIT_SHIFT_NOA_UNIT2_SEL_8821C) +#define BIT_GET_NOA_UNIT2_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT2_SEL_8821C) & BIT_MASK_NOA_UNIT2_SEL_8821C) + +#define BIT_SHIFT_NOA_UNIT1_SEL_8821C 4 +#define BIT_MASK_NOA_UNIT1_SEL_8821C 0x7 +#define BIT_NOA_UNIT1_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT1_SEL_8821C) << BIT_SHIFT_NOA_UNIT1_SEL_8821C) +#define BIT_GET_NOA_UNIT1_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT1_SEL_8821C) & BIT_MASK_NOA_UNIT1_SEL_8821C) + +#define BIT_SHIFT_NOA_UNIT0_SEL_8821C 0 +#define BIT_MASK_NOA_UNIT0_SEL_8821C 0x7 +#define BIT_NOA_UNIT0_SEL_8821C(x) (((x) & BIT_MASK_NOA_UNIT0_SEL_8821C) << BIT_SHIFT_NOA_UNIT0_SEL_8821C) +#define BIT_GET_NOA_UNIT0_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_UNIT0_SEL_8821C) & BIT_MASK_NOA_UNIT0_SEL_8821C) + +/* 2 REG_P2POFF_DIS_TXTIME_8821C */ + +#define BIT_SHIFT_P2POFF_DIS_TXTIME_8821C 0 +#define BIT_MASK_P2POFF_DIS_TXTIME_8821C 0xff +#define BIT_P2POFF_DIS_TXTIME_8821C(x) (((x) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) << BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) +#define BIT_GET_P2POFF_DIS_TXTIME_8821C(x) (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME_8821C) & BIT_MASK_P2POFF_DIS_TXTIME_8821C) + +/* 2 REG_MBSSID_BCN_SPACE2_8821C */ + +#define BIT_SHIFT_BCN_SPACE_CLINT2_8821C 16 +#define BIT_MASK_BCN_SPACE_CLINT2_8821C 0xfff +#define BIT_BCN_SPACE_CLINT2_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT2_8821C) << BIT_SHIFT_BCN_SPACE_CLINT2_8821C) +#define BIT_GET_BCN_SPACE_CLINT2_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2_8821C) & BIT_MASK_BCN_SPACE_CLINT2_8821C) + +#define BIT_SHIFT_BCN_SPACE_CLINT1_8821C 0 +#define BIT_MASK_BCN_SPACE_CLINT1_8821C 0xfff +#define BIT_BCN_SPACE_CLINT1_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT1_8821C) << BIT_SHIFT_BCN_SPACE_CLINT1_8821C) +#define BIT_GET_BCN_SPACE_CLINT1_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1_8821C) & BIT_MASK_BCN_SPACE_CLINT1_8821C) + +/* 2 REG_MBSSID_BCN_SPACE3_8821C */ + +#define BIT_SHIFT_SUB_BCN_SPACE_8821C 16 +#define BIT_MASK_SUB_BCN_SPACE_8821C 0xff +#define BIT_SUB_BCN_SPACE_8821C(x) (((x) & BIT_MASK_SUB_BCN_SPACE_8821C) << BIT_SHIFT_SUB_BCN_SPACE_8821C) +#define BIT_GET_SUB_BCN_SPACE_8821C(x) (((x) >> BIT_SHIFT_SUB_BCN_SPACE_8821C) & BIT_MASK_SUB_BCN_SPACE_8821C) + +#define BIT_SHIFT_BCN_SPACE_CLINT3_8821C 0 +#define BIT_MASK_BCN_SPACE_CLINT3_8821C 0xfff +#define BIT_BCN_SPACE_CLINT3_8821C(x) (((x) & BIT_MASK_BCN_SPACE_CLINT3_8821C) << BIT_SHIFT_BCN_SPACE_CLINT3_8821C) +#define BIT_GET_BCN_SPACE_CLINT3_8821C(x) (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3_8821C) & BIT_MASK_BCN_SPACE_CLINT3_8821C) + +/* 2 REG_ACMHWCTRL_8821C */ +#define BIT_BEQ_ACM_STATUS_8821C BIT(7) +#define BIT_VIQ_ACM_STATUS_8821C BIT(6) +#define BIT_VOQ_ACM_STATUS_8821C BIT(5) +#define BIT_BEQ_ACM_EN_8821C BIT(3) +#define BIT_VIQ_ACM_EN_8821C BIT(2) +#define BIT_VOQ_ACM_EN_8821C BIT(1) +#define BIT_ACMHWEN_8821C BIT(0) + +/* 2 REG_ACMRSTCTRL_8821C */ +#define BIT_BE_ACM_RESET_USED_TIME_8821C BIT(2) +#define BIT_VI_ACM_RESET_USED_TIME_8821C BIT(1) +#define BIT_VO_ACM_RESET_USED_TIME_8821C BIT(0) + +/* 2 REG_ACMAVG_8821C */ + +#define BIT_SHIFT_AVGPERIOD_8821C 0 +#define BIT_MASK_AVGPERIOD_8821C 0xffff +#define BIT_AVGPERIOD_8821C(x) (((x) & BIT_MASK_AVGPERIOD_8821C) << BIT_SHIFT_AVGPERIOD_8821C) +#define BIT_GET_AVGPERIOD_8821C(x) (((x) >> BIT_SHIFT_AVGPERIOD_8821C) & BIT_MASK_AVGPERIOD_8821C) + +/* 2 REG_VO_ADMTIME_8821C */ + +#define BIT_SHIFT_VO_ADMITTED_TIME_8821C 0 +#define BIT_MASK_VO_ADMITTED_TIME_8821C 0xffff +#define BIT_VO_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VO_ADMITTED_TIME_8821C) << BIT_SHIFT_VO_ADMITTED_TIME_8821C) +#define BIT_GET_VO_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VO_ADMITTED_TIME_8821C) & BIT_MASK_VO_ADMITTED_TIME_8821C) + +/* 2 REG_VI_ADMTIME_8821C */ + +#define BIT_SHIFT_VI_ADMITTED_TIME_8821C 0 +#define BIT_MASK_VI_ADMITTED_TIME_8821C 0xffff +#define BIT_VI_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_VI_ADMITTED_TIME_8821C) << BIT_SHIFT_VI_ADMITTED_TIME_8821C) +#define BIT_GET_VI_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_VI_ADMITTED_TIME_8821C) & BIT_MASK_VI_ADMITTED_TIME_8821C) + +/* 2 REG_BE_ADMTIME_8821C */ + +#define BIT_SHIFT_BE_ADMITTED_TIME_8821C 0 +#define BIT_MASK_BE_ADMITTED_TIME_8821C 0xffff +#define BIT_BE_ADMITTED_TIME_8821C(x) (((x) & BIT_MASK_BE_ADMITTED_TIME_8821C) << BIT_SHIFT_BE_ADMITTED_TIME_8821C) +#define BIT_GET_BE_ADMITTED_TIME_8821C(x) (((x) >> BIT_SHIFT_BE_ADMITTED_TIME_8821C) & BIT_MASK_BE_ADMITTED_TIME_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_EDCA_RANDOM_GEN_8821C */ + +#define BIT_SHIFT_RANDOM_GEN_8821C 0 +#define BIT_MASK_RANDOM_GEN_8821C 0xffffff +#define BIT_RANDOM_GEN_8821C(x) (((x) & BIT_MASK_RANDOM_GEN_8821C) << BIT_SHIFT_RANDOM_GEN_8821C) +#define BIT_GET_RANDOM_GEN_8821C(x) (((x) >> BIT_SHIFT_RANDOM_GEN_8821C) & BIT_MASK_RANDOM_GEN_8821C) + +/* 2 REG_TXCMD_NOA_SEL_8821C */ + +#define BIT_SHIFT_NOA_SEL_8821C 4 +#define BIT_MASK_NOA_SEL_8821C 0x7 +#define BIT_NOA_SEL_8821C(x) (((x) & BIT_MASK_NOA_SEL_8821C) << BIT_SHIFT_NOA_SEL_8821C) +#define BIT_GET_NOA_SEL_8821C(x) (((x) >> BIT_SHIFT_NOA_SEL_8821C) & BIT_MASK_NOA_SEL_8821C) + +#define BIT_SHIFT_TXCMD_SEG_SEL_8821C 0 +#define BIT_MASK_TXCMD_SEG_SEL_8821C 0xf +#define BIT_TXCMD_SEG_SEL_8821C(x) (((x) & BIT_MASK_TXCMD_SEG_SEL_8821C) << BIT_SHIFT_TXCMD_SEG_SEL_8821C) +#define BIT_GET_TXCMD_SEG_SEL_8821C(x) (((x) >> BIT_SHIFT_TXCMD_SEG_SEL_8821C) & BIT_MASK_TXCMD_SEG_SEL_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOA_PARAM_8821C */ + +#define BIT_SHIFT_NOA_DURATION_V1_8821C 0 +#define BIT_MASK_NOA_DURATION_V1_8821C 0xffffffffL +#define BIT_NOA_DURATION_V1_8821C(x) (((x) & BIT_MASK_NOA_DURATION_V1_8821C) << BIT_SHIFT_NOA_DURATION_V1_8821C) +#define BIT_GET_NOA_DURATION_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_DURATION_V1_8821C) & BIT_MASK_NOA_DURATION_V1_8821C) + +/* 2 REG_NOA_PARAM_1_8821C */ + +#define BIT_SHIFT_NOA_INTERVAL_V1_8821C 0 +#define BIT_MASK_NOA_INTERVAL_V1_8821C 0xffffffffL +#define BIT_NOA_INTERVAL_V1_8821C(x) (((x) & BIT_MASK_NOA_INTERVAL_V1_8821C) << BIT_SHIFT_NOA_INTERVAL_V1_8821C) +#define BIT_GET_NOA_INTERVAL_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_INTERVAL_V1_8821C) & BIT_MASK_NOA_INTERVAL_V1_8821C) + +/* 2 REG_NOA_PARAM_2_8821C */ + +#define BIT_SHIFT_NOA_START_TIME_V1_8821C 0 +#define BIT_MASK_NOA_START_TIME_V1_8821C 0xffffffffL +#define BIT_NOA_START_TIME_V1_8821C(x) (((x) & BIT_MASK_NOA_START_TIME_V1_8821C) << BIT_SHIFT_NOA_START_TIME_V1_8821C) +#define BIT_GET_NOA_START_TIME_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_START_TIME_V1_8821C) & BIT_MASK_NOA_START_TIME_V1_8821C) + +/* 2 REG_NOA_PARAM_3_8821C */ + +#define BIT_SHIFT_NOA_COUNT_V1_8821C 0 +#define BIT_MASK_NOA_COUNT_V1_8821C 0xffffffffL +#define BIT_NOA_COUNT_V1_8821C(x) (((x) & BIT_MASK_NOA_COUNT_V1_8821C) << BIT_SHIFT_NOA_COUNT_V1_8821C) +#define BIT_GET_NOA_COUNT_V1_8821C(x) (((x) >> BIT_SHIFT_NOA_COUNT_V1_8821C) & BIT_MASK_NOA_COUNT_V1_8821C) + +/* 2 REG_P2P_RST_8821C */ +#define BIT_P2P2_PWR_RST1_8821C BIT(5) +#define BIT_P2P2_PWR_RST0_8821C BIT(4) +#define BIT_P2P1_PWR_RST1_8821C BIT(3) +#define BIT_P2P1_PWR_RST0_8821C BIT(2) +#define BIT_P2P_PWR_RST1_V1_8821C BIT(1) +#define BIT_P2P_PWR_RST0_V1_8821C BIT(0) + +/* 2 REG_SCHEDULER_RST_8821C */ +#define BIT_SYNC_CLI_8821C BIT(1) +#define BIT_SCHEDULER_RST_V1_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_SCH_TXCMD_8821C */ + +#define BIT_SHIFT_SCH_TXCMD_8821C 0 +#define BIT_MASK_SCH_TXCMD_8821C 0xffffffffL +#define BIT_SCH_TXCMD_8821C(x) (((x) & BIT_MASK_SCH_TXCMD_8821C) << BIT_SHIFT_SCH_TXCMD_8821C) +#define BIT_GET_SCH_TXCMD_8821C(x) (((x) >> BIT_SHIFT_SCH_TXCMD_8821C) & BIT_MASK_SCH_TXCMD_8821C) + +/* 2 REG_PAGE5_DUMMY_8821C */ + +/* 2 REG_CPUMGQ_TX_TIMER_8821C */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C 0xffffffffL +#define BIT_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) +#define BIT_GET_CPUMGQ_TX_TIMER_V1_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_V1_8821C) + +/* 2 REG_PS_TIMER_A_8821C */ + +#define BIT_SHIFT_PS_TIMER_A_V1_8821C 0 +#define BIT_MASK_PS_TIMER_A_V1_8821C 0xffffffffL +#define BIT_PS_TIMER_A_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_V1_8821C) << BIT_SHIFT_PS_TIMER_A_V1_8821C) +#define BIT_GET_PS_TIMER_A_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_V1_8821C) & BIT_MASK_PS_TIMER_A_V1_8821C) + +/* 2 REG_PS_TIMER_B_8821C */ + +#define BIT_SHIFT_PS_TIMER_B_V1_8821C 0 +#define BIT_MASK_PS_TIMER_B_V1_8821C 0xffffffffL +#define BIT_PS_TIMER_B_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_V1_8821C) << BIT_SHIFT_PS_TIMER_B_V1_8821C) +#define BIT_GET_PS_TIMER_B_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_V1_8821C) & BIT_MASK_PS_TIMER_B_V1_8821C) + +/* 2 REG_PS_TIMER_C_8821C */ + +#define BIT_SHIFT_PS_TIMER_C_V1_8821C 0 +#define BIT_MASK_PS_TIMER_C_V1_8821C 0xffffffffL +#define BIT_PS_TIMER_C_V1_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_V1_8821C) << BIT_SHIFT_PS_TIMER_C_V1_8821C) +#define BIT_GET_PS_TIMER_C_V1_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_V1_8821C) & BIT_MASK_PS_TIMER_C_V1_8821C) + +/* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C */ +#define BIT_CPUMGQ_TIMER_EN_8821C BIT(31) +#define BIT_CPUMGQ_TX_EN_8821C BIT(28) + +#define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C 24 +#define BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C 0x7 +#define BIT_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) +#define BIT_GET_CPUMGQ_TIMER_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL_8821C) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL_8821C) + +#define BIT_PS_TIMER_C_EN_8821C BIT(23) + +#define BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C 16 +#define BIT_MASK_PS_TIMER_C_TSF_SEL_8821C 0x7 +#define BIT_PS_TIMER_C_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) +#define BIT_GET_PS_TIMER_C_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_C_TSF_SEL_8821C) + +#define BIT_PS_TIMER_B_EN_8821C BIT(15) + +#define BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C 8 +#define BIT_MASK_PS_TIMER_B_TSF_SEL_8821C 0x7 +#define BIT_PS_TIMER_B_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) +#define BIT_GET_PS_TIMER_B_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_B_TSF_SEL_8821C) + +#define BIT_PS_TIMER_A_EN_8821C BIT(7) + +#define BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C 0 +#define BIT_MASK_PS_TIMER_A_TSF_SEL_8821C 0x7 +#define BIT_PS_TIMER_A_TSF_SEL_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) << BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) +#define BIT_GET_PS_TIMER_A_TSF_SEL_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL_8821C) & BIT_MASK_PS_TIMER_A_TSF_SEL_8821C) + +/* 2 REG_CPUMGQ_TX_TIMER_EARLY_8821C */ + +#define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C 0 +#define BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C 0xff +#define BIT_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) +#define BIT_GET_CPUMGQ_TX_TIMER_EARLY_8821C(x) (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY_8821C) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY_8821C) + +/* 2 REG_PS_TIMER_A_EARLY_8821C */ + +#define BIT_SHIFT_PS_TIMER_A_EARLY_8821C 0 +#define BIT_MASK_PS_TIMER_A_EARLY_8821C 0xff +#define BIT_PS_TIMER_A_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_A_EARLY_8821C) << BIT_SHIFT_PS_TIMER_A_EARLY_8821C) +#define BIT_GET_PS_TIMER_A_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY_8821C) & BIT_MASK_PS_TIMER_A_EARLY_8821C) + +/* 2 REG_PS_TIMER_B_EARLY_8821C */ + +#define BIT_SHIFT_PS_TIMER_B_EARLY_8821C 0 +#define BIT_MASK_PS_TIMER_B_EARLY_8821C 0xff +#define BIT_PS_TIMER_B_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_B_EARLY_8821C) << BIT_SHIFT_PS_TIMER_B_EARLY_8821C) +#define BIT_GET_PS_TIMER_B_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY_8821C) & BIT_MASK_PS_TIMER_B_EARLY_8821C) + +/* 2 REG_PS_TIMER_C_EARLY_8821C */ + +#define BIT_SHIFT_PS_TIMER_C_EARLY_8821C 0 +#define BIT_MASK_PS_TIMER_C_EARLY_8821C 0xff +#define BIT_PS_TIMER_C_EARLY_8821C(x) (((x) & BIT_MASK_PS_TIMER_C_EARLY_8821C) << BIT_SHIFT_PS_TIMER_C_EARLY_8821C) +#define BIT_GET_PS_TIMER_C_EARLY_8821C(x) (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY_8821C) & BIT_MASK_PS_TIMER_C_EARLY_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_RSVD_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_BWOPMODE_8821C (BW OPERATION MODE REGISTER) */ + +/* 2 REG_WMAC_FWPKT_CR_8821C */ +#define BIT_FWEN_8821C BIT(7) +#define BIT_PHYSTS_PKT_CTRL_8821C BIT(6) +#define BIT_APPHDR_MIDSRCH_FAIL_8821C BIT(4) +#define BIT_FWPARSING_EN_8821C BIT(3) + +#define BIT_SHIFT_APPEND_MHDR_LEN_8821C 0 +#define BIT_MASK_APPEND_MHDR_LEN_8821C 0x7 +#define BIT_APPEND_MHDR_LEN_8821C(x) (((x) & BIT_MASK_APPEND_MHDR_LEN_8821C) << BIT_SHIFT_APPEND_MHDR_LEN_8821C) +#define BIT_GET_APPEND_MHDR_LEN_8821C(x) (((x) >> BIT_SHIFT_APPEND_MHDR_LEN_8821C) & BIT_MASK_APPEND_MHDR_LEN_8821C) + +/* 2 REG_FW_STS_FILTER_8821C */ +#define BIT_DATA_FW_STS_FILTER_8821C BIT(2) +#define BIT_CTRL_FW_STS_FILTER_8821C BIT(1) +#define BIT_MGNT_FW_STS_FILTER_8821C BIT(0) + +/* 2 REG_WMAC_CR_8821C (WMAC CR AND APSD CONTROL REGISTER) */ +#define BIT_IC_MACPHY_M_8821C BIT(0) + +/* 2 REG_TCR_8821C (TRANSMISSION CONFIGURATION REGISTER) */ +#define BIT_WMAC_EN_RTS_ADDR_8821C BIT(31) +#define BIT_WMAC_DISABLE_CCK_8821C BIT(30) +#define BIT_WMAC_RAW_LEN_8821C BIT(29) +#define BIT_WMAC_NOTX_IN_RXNDP_8821C BIT(28) +#define BIT_WMAC_EN_EOF_8821C BIT(27) +#define BIT_WMAC_BF_SEL_8821C BIT(26) +#define BIT_WMAC_ANTMODE_SEL_8821C BIT(25) +#define BIT_WMAC_TCRPWRMGT_HWCTL_8821C BIT(24) +#define BIT_WMAC_SMOOTH_VAL_8821C BIT(23) +#define BIT_FETCH_MPDU_AFTER_WSEC_RDY_8821C BIT(20) +#define BIT_WMAC_TCR_EN_20MST_8821C BIT(19) +#define BIT_WMAC_DIS_SIGTA_8821C BIT(18) +#define BIT_WMAC_DIS_A2B0_8821C BIT(17) +#define BIT_WMAC_MSK_SIGBCRC_8821C BIT(16) +#define BIT_WMAC_TCR_ERRSTEN_3_8821C BIT(15) +#define BIT_WMAC_TCR_ERRSTEN_2_8821C BIT(14) +#define BIT_WMAC_TCR_ERRSTEN_1_8821C BIT(13) +#define BIT_WMAC_TCR_ERRSTEN_0_8821C BIT(12) +#define BIT_WMAC_TCR_TXSK_PERPKT_8821C BIT(11) +#define BIT_ICV_8821C BIT(10) +#define BIT_CFEND_FORMAT_8821C BIT(9) +#define BIT_CRC_8821C BIT(8) +#define BIT_PWRBIT_OW_EN_8821C BIT(7) +#define BIT_PWR_ST_8821C BIT(6) +#define BIT_WMAC_TCR_UPD_TIMIE_8821C BIT(5) +#define BIT_WMAC_TCR_UPD_HGQMD_8821C BIT(4) +#define BIT_VHTSIGA1_TXPS_8821C BIT(3) +#define BIT_PAD_SEL_8821C BIT(2) +#define BIT_DIS_GCLK_8821C BIT(1) + +/* 2 REG_RCR_8821C (RECEIVE CONFIGURATION REGISTER) */ +#define BIT_APP_FCS_8821C BIT(31) +#define BIT_APP_MIC_8821C BIT(30) +#define BIT_APP_ICV_8821C BIT(29) +#define BIT_APP_PHYSTS_8821C BIT(28) +#define BIT_APP_BASSN_8821C BIT(27) +#define BIT_VHT_DACK_8821C BIT(26) +#define BIT_TCPOFLD_EN_8821C BIT(25) +#define BIT_ENMBID_8821C BIT(24) +#define BIT_LSIGEN_8821C BIT(23) +#define BIT_MFBEN_8821C BIT(22) +#define BIT_DISCHKPPDLLEN_8821C BIT(21) +#define BIT_PKTCTL_DLEN_8821C BIT(20) +#define BIT_TIM_PARSER_EN_8821C BIT(18) +#define BIT_BC_MD_EN_8821C BIT(17) +#define BIT_UC_MD_EN_8821C BIT(16) +#define BIT_RXSK_PERPKT_8821C BIT(15) +#define BIT_HTC_LOC_CTRL_8821C BIT(14) +#define BIT_RPFM_CAM_ENABLE_8821C BIT(12) +#define BIT_TA_BCN_8821C BIT(11) +#define BIT_DISDECMYPKT_8821C BIT(10) +#define BIT_AICV_8821C BIT(9) +#define BIT_ACRC32_8821C BIT(8) +#define BIT_CBSSID_BCN_8821C BIT(7) +#define BIT_CBSSID_DATA_8821C BIT(6) +#define BIT_APWRMGT_8821C BIT(5) +#define BIT_ADD3_8821C BIT(4) +#define BIT_AB_8821C BIT(3) +#define BIT_AM_8821C BIT(2) +#define BIT_APM_8821C BIT(1) +#define BIT_AAP_8821C BIT(0) + +/* 2 REG_RX_DRVINFO_SZ_8821C (RX DRIVER INFO SIZE REGISTER) */ +#define BIT_PHYSTS_PER_PKT_MODE_8821C BIT(7) + +#define BIT_SHIFT_DRVINFO_SZ_V1_8821C 0 +#define BIT_MASK_DRVINFO_SZ_V1_8821C 0xf +#define BIT_DRVINFO_SZ_V1_8821C(x) (((x) & BIT_MASK_DRVINFO_SZ_V1_8821C) << BIT_SHIFT_DRVINFO_SZ_V1_8821C) +#define BIT_GET_DRVINFO_SZ_V1_8821C(x) (((x) >> BIT_SHIFT_DRVINFO_SZ_V1_8821C) & BIT_MASK_DRVINFO_SZ_V1_8821C) + +/* 2 REG_RX_DLK_TIME_8821C (RX DEADLOCK TIME REGISTER) */ + +#define BIT_SHIFT_RX_DLK_TIME_8821C 0 +#define BIT_MASK_RX_DLK_TIME_8821C 0xff +#define BIT_RX_DLK_TIME_8821C(x) (((x) & BIT_MASK_RX_DLK_TIME_8821C) << BIT_SHIFT_RX_DLK_TIME_8821C) +#define BIT_GET_RX_DLK_TIME_8821C(x) (((x) >> BIT_SHIFT_RX_DLK_TIME_8821C) & BIT_MASK_RX_DLK_TIME_8821C) + +/* 2 REG_RX_PKT_LIMIT_8821C (RX PACKET LENGTH LIMIT REGISTER) */ + +#define BIT_SHIFT_RXPKTLMT_8821C 0 +#define BIT_MASK_RXPKTLMT_8821C 0x3f +#define BIT_RXPKTLMT_8821C(x) (((x) & BIT_MASK_RXPKTLMT_8821C) << BIT_SHIFT_RXPKTLMT_8821C) +#define BIT_GET_RXPKTLMT_8821C(x) (((x) >> BIT_SHIFT_RXPKTLMT_8821C) & BIT_MASK_RXPKTLMT_8821C) + +/* 2 REG_MACID_8821C (MAC ID REGISTER) */ + +#define BIT_SHIFT_MACID_8821C 0 +#define BIT_MASK_MACID_8821C 0xffffffffffffL +#define BIT_MACID_8821C(x) (((x) & BIT_MASK_MACID_8821C) << BIT_SHIFT_MACID_8821C) +#define BIT_GET_MACID_8821C(x) (((x) >> BIT_SHIFT_MACID_8821C) & BIT_MASK_MACID_8821C) + +/* 2 REG_BSSID_8821C (BSSID REGISTER) */ + +#define BIT_SHIFT_BSSID_8821C 0 +#define BIT_MASK_BSSID_8821C 0xffffffffffffL +#define BIT_BSSID_8821C(x) (((x) & BIT_MASK_BSSID_8821C) << BIT_SHIFT_BSSID_8821C) +#define BIT_GET_BSSID_8821C(x) (((x) >> BIT_SHIFT_BSSID_8821C) & BIT_MASK_BSSID_8821C) + +/* 2 REG_MAR_8821C (MULTICAST ADDRESS REGISTER) */ + +#define BIT_SHIFT_MAR_8821C 0 +#define BIT_MASK_MAR_8821C 0xffffffffffffffffL +#define BIT_MAR_8821C(x) (((x) & BIT_MASK_MAR_8821C) << BIT_SHIFT_MAR_8821C) +#define BIT_GET_MAR_8821C(x) (((x) >> BIT_SHIFT_MAR_8821C) & BIT_MASK_MAR_8821C) + +/* 2 REG_MBIDCAMCFG_1_8821C (MBSSID CAM CONFIGURATION REGISTER) */ + +#define BIT_SHIFT_MBIDCAM_RWDATA_L_8821C 0 +#define BIT_MASK_MBIDCAM_RWDATA_L_8821C 0xffffffffL +#define BIT_MBIDCAM_RWDATA_L_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) +#define BIT_GET_MBIDCAM_RWDATA_L_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L_8821C) & BIT_MASK_MBIDCAM_RWDATA_L_8821C) + +/* 2 REG_MBIDCAMCFG_2_8821C (MBSSID CAM CONFIGURATION REGISTER) */ +#define BIT_MBIDCAM_POLL_8821C BIT(31) +#define BIT_MBIDCAM_WT_EN_8821C BIT(30) + +#define BIT_SHIFT_MBIDCAM_ADDR_8821C 24 +#define BIT_MASK_MBIDCAM_ADDR_8821C 0x1f +#define BIT_MBIDCAM_ADDR_8821C(x) (((x) & BIT_MASK_MBIDCAM_ADDR_8821C) << BIT_SHIFT_MBIDCAM_ADDR_8821C) +#define BIT_GET_MBIDCAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_ADDR_8821C) & BIT_MASK_MBIDCAM_ADDR_8821C) + +#define BIT_MBIDCAM_VALID_8821C BIT(23) +#define BIT_LSIC_TXOP_EN_8821C BIT(17) +#define BIT_CTS_EN_8821C BIT(16) + +#define BIT_SHIFT_MBIDCAM_RWDATA_H_8821C 0 +#define BIT_MASK_MBIDCAM_RWDATA_H_8821C 0xffff +#define BIT_MBIDCAM_RWDATA_H_8821C(x) (((x) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) << BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) +#define BIT_GET_MBIDCAM_RWDATA_H_8821C(x) (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H_8821C) & BIT_MASK_MBIDCAM_RWDATA_H_8821C) + +/* 2 REG_ZLD_NUM_8821C */ + +#define BIT_SHIFT_ZLD_NUM_8821C 0 +#define BIT_MASK_ZLD_NUM_8821C 0xff +#define BIT_ZLD_NUM_8821C(x) (((x) & BIT_MASK_ZLD_NUM_8821C) << BIT_SHIFT_ZLD_NUM_8821C) +#define BIT_GET_ZLD_NUM_8821C(x) (((x) >> BIT_SHIFT_ZLD_NUM_8821C) & BIT_MASK_ZLD_NUM_8821C) + +/* 2 REG_UDF_THSD_8821C */ + +#define BIT_SHIFT_UDF_THSD_8821C 0 +#define BIT_MASK_UDF_THSD_8821C 0xff +#define BIT_UDF_THSD_8821C(x) (((x) & BIT_MASK_UDF_THSD_8821C) << BIT_SHIFT_UDF_THSD_8821C) +#define BIT_GET_UDF_THSD_8821C(x) (((x) >> BIT_SHIFT_UDF_THSD_8821C) & BIT_MASK_UDF_THSD_8821C) + +/* 2 REG_WMAC_TCR_TSFT_OFS_8821C */ + +#define BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C 0 +#define BIT_MASK_WMAC_TCR_TSFT_OFS_8821C 0xffff +#define BIT_WMAC_TCR_TSFT_OFS_8821C(x) (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) << BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) +#define BIT_GET_WMAC_TCR_TSFT_OFS_8821C(x) (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS_8821C) & BIT_MASK_WMAC_TCR_TSFT_OFS_8821C) + +/* 2 REG_MCU_TEST_2_V1_8821C */ + +#define BIT_SHIFT_MCU_RSVD_2_V1_8821C 0 +#define BIT_MASK_MCU_RSVD_2_V1_8821C 0xffff +#define BIT_MCU_RSVD_2_V1_8821C(x) (((x) & BIT_MASK_MCU_RSVD_2_V1_8821C) << BIT_SHIFT_MCU_RSVD_2_V1_8821C) +#define BIT_GET_MCU_RSVD_2_V1_8821C(x) (((x) >> BIT_SHIFT_MCU_RSVD_2_V1_8821C) & BIT_MASK_MCU_RSVD_2_V1_8821C) + +/* 2 REG_WMAC_TXTIMEOUT_8821C */ + +#define BIT_SHIFT_WMAC_TXTIMEOUT_8821C 0 +#define BIT_MASK_WMAC_TXTIMEOUT_8821C 0xff +#define BIT_WMAC_TXTIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_TXTIMEOUT_8821C) << BIT_SHIFT_WMAC_TXTIMEOUT_8821C) +#define BIT_GET_WMAC_TXTIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT_8821C) & BIT_MASK_WMAC_TXTIMEOUT_8821C) + +/* 2 REG_STMP_THSD_8821C */ + +#define BIT_SHIFT_STMP_THSD_8821C 0 +#define BIT_MASK_STMP_THSD_8821C 0xff +#define BIT_STMP_THSD_8821C(x) (((x) & BIT_MASK_STMP_THSD_8821C) << BIT_SHIFT_STMP_THSD_8821C) +#define BIT_GET_STMP_THSD_8821C(x) (((x) >> BIT_SHIFT_STMP_THSD_8821C) & BIT_MASK_STMP_THSD_8821C) + +/* 2 REG_MAC_SPEC_SIFS_8821C (SPECIFICATION SIFS REGISTER) */ + +#define BIT_SHIFT_SPEC_SIFS_OFDM_8821C 8 +#define BIT_MASK_SPEC_SIFS_OFDM_8821C 0xff +#define BIT_SPEC_SIFS_OFDM_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_OFDM_8821C) << BIT_SHIFT_SPEC_SIFS_OFDM_8821C) +#define BIT_GET_SPEC_SIFS_OFDM_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_8821C) & BIT_MASK_SPEC_SIFS_OFDM_8821C) + +#define BIT_SHIFT_SPEC_SIFS_CCK_8821C 0 +#define BIT_MASK_SPEC_SIFS_CCK_8821C 0xff +#define BIT_SPEC_SIFS_CCK_8821C(x) (((x) & BIT_MASK_SPEC_SIFS_CCK_8821C) << BIT_SHIFT_SPEC_SIFS_CCK_8821C) +#define BIT_GET_SPEC_SIFS_CCK_8821C(x) (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_8821C) & BIT_MASK_SPEC_SIFS_CCK_8821C) + +/* 2 REG_ACKTO_CCK_8821C (ACK TIMEOUT REGISTER FOR CCK RATE) */ + +#define BIT_SHIFT_ACKTO_CCK_8821C 0 +#define BIT_MASK_ACKTO_CCK_8821C 0xff +#define BIT_ACKTO_CCK_8821C(x) (((x) & BIT_MASK_ACKTO_CCK_8821C) << BIT_SHIFT_ACKTO_CCK_8821C) +#define BIT_GET_ACKTO_CCK_8821C(x) (((x) >> BIT_SHIFT_ACKTO_CCK_8821C) & BIT_MASK_ACKTO_CCK_8821C) + +/* 2 REG_USTIME_EDCA_8821C (US TIME TUNING FOR EDCA REGISTER) */ + +#define BIT_SHIFT_USTIME_EDCA_V1_8821C 0 +#define BIT_MASK_USTIME_EDCA_V1_8821C 0x1ff +#define BIT_USTIME_EDCA_V1_8821C(x) (((x) & BIT_MASK_USTIME_EDCA_V1_8821C) << BIT_SHIFT_USTIME_EDCA_V1_8821C) +#define BIT_GET_USTIME_EDCA_V1_8821C(x) (((x) >> BIT_SHIFT_USTIME_EDCA_V1_8821C) & BIT_MASK_USTIME_EDCA_V1_8821C) + +/* 2 REG_RESP_SIFS_OFDM_8821C (RESPONSE SIFS FOR OFDM REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_OFDM_8821C 8 +#define BIT_MASK_SIFS_R2T_OFDM_8821C 0xff +#define BIT_SIFS_R2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_R2T_OFDM_8821C) << BIT_SHIFT_SIFS_R2T_OFDM_8821C) +#define BIT_GET_SIFS_R2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_OFDM_8821C) & BIT_MASK_SIFS_R2T_OFDM_8821C) + +#define BIT_SHIFT_SIFS_T2T_OFDM_8821C 0 +#define BIT_MASK_SIFS_T2T_OFDM_8821C 0xff +#define BIT_SIFS_T2T_OFDM_8821C(x) (((x) & BIT_MASK_SIFS_T2T_OFDM_8821C) << BIT_SHIFT_SIFS_T2T_OFDM_8821C) +#define BIT_GET_SIFS_T2T_OFDM_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_OFDM_8821C) & BIT_MASK_SIFS_T2T_OFDM_8821C) + +/* 2 REG_RESP_SIFS_CCK_8821C (RESPONSE SIFS FOR CCK REGISTER) */ + +#define BIT_SHIFT_SIFS_R2T_CCK_8821C 8 +#define BIT_MASK_SIFS_R2T_CCK_8821C 0xff +#define BIT_SIFS_R2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_R2T_CCK_8821C) << BIT_SHIFT_SIFS_R2T_CCK_8821C) +#define BIT_GET_SIFS_R2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_R2T_CCK_8821C) & BIT_MASK_SIFS_R2T_CCK_8821C) + +#define BIT_SHIFT_SIFS_T2T_CCK_8821C 0 +#define BIT_MASK_SIFS_T2T_CCK_8821C 0xff +#define BIT_SIFS_T2T_CCK_8821C(x) (((x) & BIT_MASK_SIFS_T2T_CCK_8821C) << BIT_SHIFT_SIFS_T2T_CCK_8821C) +#define BIT_GET_SIFS_T2T_CCK_8821C(x) (((x) >> BIT_SHIFT_SIFS_T2T_CCK_8821C) & BIT_MASK_SIFS_T2T_CCK_8821C) + +/* 2 REG_EIFS_8821C (EIFS REGISTER) */ + +#define BIT_SHIFT_EIFS_8821C 0 +#define BIT_MASK_EIFS_8821C 0xffff +#define BIT_EIFS_8821C(x) (((x) & BIT_MASK_EIFS_8821C) << BIT_SHIFT_EIFS_8821C) +#define BIT_GET_EIFS_8821C(x) (((x) >> BIT_SHIFT_EIFS_8821C) & BIT_MASK_EIFS_8821C) + +/* 2 REG_CTS2TO_8821C (CTS2 TIMEOUT REGISTER) */ + +#define BIT_SHIFT_CTS2TO_8821C 0 +#define BIT_MASK_CTS2TO_8821C 0xff +#define BIT_CTS2TO_8821C(x) (((x) & BIT_MASK_CTS2TO_8821C) << BIT_SHIFT_CTS2TO_8821C) +#define BIT_GET_CTS2TO_8821C(x) (((x) >> BIT_SHIFT_CTS2TO_8821C) & BIT_MASK_CTS2TO_8821C) + +/* 2 REG_ACKTO_8821C (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_ACKTO_8821C 0 +#define BIT_MASK_ACKTO_8821C 0xff +#define BIT_ACKTO_8821C(x) (((x) & BIT_MASK_ACKTO_8821C) << BIT_SHIFT_ACKTO_8821C) +#define BIT_GET_ACKTO_8821C(x) (((x) >> BIT_SHIFT_ACKTO_8821C) & BIT_MASK_ACKTO_8821C) + +/* 2 REG_RPFM_MAP0_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 0) */ +#define BIT_MGT_RPFM15EN_8821C BIT(15) +#define BIT_MGT_RPFM14EN_8821C BIT(14) +#define BIT_MGT_RPFM13EN_8821C BIT(13) +#define BIT_MGT_RPFM12EN_8821C BIT(12) +#define BIT_MGT_RPFM11EN_8821C BIT(11) +#define BIT_MGT_RPFM10EN_8821C BIT(10) +#define BIT_MGT_RPFM9EN_8821C BIT(9) +#define BIT_MGT_RPFM8EN_8821C BIT(8) +#define BIT_MGT_RPFM7EN_8821C BIT(7) +#define BIT_MGT_RPFM6EN_8821C BIT(6) +#define BIT_MGT_RPFM5EN_8821C BIT(5) +#define BIT_MGT_RPFM4EN_8821C BIT(4) +#define BIT_MGT_RPFM3EN_8821C BIT(3) +#define BIT_MGT_RPFM2EN_8821C BIT(2) +#define BIT_MGT_RPFM1EN_8821C BIT(1) +#define BIT_MGT_RPFM0EN_8821C BIT(0) + +/* 2 REG_RPFM_MAP1_8821C (RX PAYLOAD FILTER MAP FRAME TYPE CONTROL REGISTER GROUP 1) */ +#define BIT_DATA_RPFM15EN_8821C BIT(15) +#define BIT_DATA_RPFM14EN_8821C BIT(14) +#define BIT_DATA_RPFM13EN_8821C BIT(13) +#define BIT_DATA_RPFM12EN_8821C BIT(12) +#define BIT_DATA_RPFM11EN_8821C BIT(11) +#define BIT_DATA_RPFM10EN_8821C BIT(10) +#define BIT_DATA_RPFM9EN_8821C BIT(9) +#define BIT_DATA_RPFM8EN_8821C BIT(8) +#define BIT_DATA_RPFM7EN_8821C BIT(7) +#define BIT_DATA_RPFM6EN_8821C BIT(6) +#define BIT_DATA_RPFM5EN_8821C BIT(5) +#define BIT_DATA_RPFM4EN_8821C BIT(4) +#define BIT_DATA_RPFM3EN_8821C BIT(3) +#define BIT_DATA_RPFM2EN_8821C BIT(2) +#define BIT_DATA_RPFM1EN_8821C BIT(1) +#define BIT_DATA_RPFM0EN_8821C BIT(0) + +/* 2 REG_RPFM_CAM_CMD_8821C (RX PAYLOAD FRAME MASK CAM COMMAND REGISTER) */ +#define BIT_RPFM_CAM_POLLING_8821C BIT(31) +#define BIT_RPFM_CAM_CLR_8821C BIT(30) +#define BIT_RPFM_CAM_WE_8821C BIT(16) + +#define BIT_SHIFT_RPFM_CAM_ADDR_8821C 0 +#define BIT_MASK_RPFM_CAM_ADDR_8821C 0x7f +#define BIT_RPFM_CAM_ADDR_8821C(x) (((x) & BIT_MASK_RPFM_CAM_ADDR_8821C) << BIT_SHIFT_RPFM_CAM_ADDR_8821C) +#define BIT_GET_RPFM_CAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_ADDR_8821C) & BIT_MASK_RPFM_CAM_ADDR_8821C) + +/* 2 REG_RPFM_CAM_RWD_8821C (ACK TIMEOUT REGISTER) */ + +#define BIT_SHIFT_RPFM_CAM_RWD_8821C 0 +#define BIT_MASK_RPFM_CAM_RWD_8821C 0xffffffffL +#define BIT_RPFM_CAM_RWD_8821C(x) (((x) & BIT_MASK_RPFM_CAM_RWD_8821C) << BIT_SHIFT_RPFM_CAM_RWD_8821C) +#define BIT_GET_RPFM_CAM_RWD_8821C(x) (((x) >> BIT_SHIFT_RPFM_CAM_RWD_8821C) & BIT_MASK_RPFM_CAM_RWD_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NAV_CTRL_8821C (NAV CONTROL REGISTER) */ + +#define BIT_SHIFT_NAV_UPPER_8821C 16 +#define BIT_MASK_NAV_UPPER_8821C 0xff +#define BIT_NAV_UPPER_8821C(x) (((x) & BIT_MASK_NAV_UPPER_8821C) << BIT_SHIFT_NAV_UPPER_8821C) +#define BIT_GET_NAV_UPPER_8821C(x) (((x) >> BIT_SHIFT_NAV_UPPER_8821C) & BIT_MASK_NAV_UPPER_8821C) + +#define BIT_SHIFT_RXMYRTS_NAV_8821C 8 +#define BIT_MASK_RXMYRTS_NAV_8821C 0xf +#define BIT_RXMYRTS_NAV_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_8821C) << BIT_SHIFT_RXMYRTS_NAV_8821C) +#define BIT_GET_RXMYRTS_NAV_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_8821C) & BIT_MASK_RXMYRTS_NAV_8821C) + +#define BIT_SHIFT_RTSRST_8821C 0 +#define BIT_MASK_RTSRST_8821C 0xff +#define BIT_RTSRST_8821C(x) (((x) & BIT_MASK_RTSRST_8821C) << BIT_SHIFT_RTSRST_8821C) +#define BIT_GET_RTSRST_8821C(x) (((x) >> BIT_SHIFT_RTSRST_8821C) & BIT_MASK_RTSRST_8821C) + +/* 2 REG_BACAMCMD_8821C (BLOCK ACK CAM COMMAND REGISTER) */ +#define BIT_BACAM_POLL_8821C BIT(31) +#define BIT_BACAM_RST_8821C BIT(17) +#define BIT_BACAM_RW_8821C BIT(16) + +#define BIT_SHIFT_TXSBM_8821C 14 +#define BIT_MASK_TXSBM_8821C 0x3 +#define BIT_TXSBM_8821C(x) (((x) & BIT_MASK_TXSBM_8821C) << BIT_SHIFT_TXSBM_8821C) +#define BIT_GET_TXSBM_8821C(x) (((x) >> BIT_SHIFT_TXSBM_8821C) & BIT_MASK_TXSBM_8821C) + +#define BIT_SHIFT_BACAM_ADDR_8821C 0 +#define BIT_MASK_BACAM_ADDR_8821C 0x3f +#define BIT_BACAM_ADDR_8821C(x) (((x) & BIT_MASK_BACAM_ADDR_8821C) << BIT_SHIFT_BACAM_ADDR_8821C) +#define BIT_GET_BACAM_ADDR_8821C(x) (((x) >> BIT_SHIFT_BACAM_ADDR_8821C) & BIT_MASK_BACAM_ADDR_8821C) + +/* 2 REG_BACAMCONTENT_8821C (BLOCK ACK CAM CONTENT REGISTER) */ + +#define BIT_SHIFT_BA_CONTENT_H_8821C (32 & CPU_OPT_WIDTH) +#define BIT_MASK_BA_CONTENT_H_8821C 0xffffffffL +#define BIT_BA_CONTENT_H_8821C(x) (((x) & BIT_MASK_BA_CONTENT_H_8821C) << BIT_SHIFT_BA_CONTENT_H_8821C) +#define BIT_GET_BA_CONTENT_H_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_H_8821C) & BIT_MASK_BA_CONTENT_H_8821C) + +#define BIT_SHIFT_BA_CONTENT_L_8821C 0 +#define BIT_MASK_BA_CONTENT_L_8821C 0xffffffffL +#define BIT_BA_CONTENT_L_8821C(x) (((x) & BIT_MASK_BA_CONTENT_L_8821C) << BIT_SHIFT_BA_CONTENT_L_8821C) +#define BIT_GET_BA_CONTENT_L_8821C(x) (((x) >> BIT_SHIFT_BA_CONTENT_L_8821C) & BIT_MASK_BA_CONTENT_L_8821C) + +/* 2 REG_WMAC_BITMAP_CTL_8821C */ +#define BIT_BITMAP_VO_8821C BIT(7) +#define BIT_BITMAP_VI_8821C BIT(6) +#define BIT_BITMAP_BE_8821C BIT(5) +#define BIT_BITMAP_BK_8821C BIT(4) + +#define BIT_SHIFT_BITMAP_CONDITION_8821C 2 +#define BIT_MASK_BITMAP_CONDITION_8821C 0x3 +#define BIT_BITMAP_CONDITION_8821C(x) (((x) & BIT_MASK_BITMAP_CONDITION_8821C) << BIT_SHIFT_BITMAP_CONDITION_8821C) +#define BIT_GET_BITMAP_CONDITION_8821C(x) (((x) >> BIT_SHIFT_BITMAP_CONDITION_8821C) & BIT_MASK_BITMAP_CONDITION_8821C) + +#define BIT_BITMAP_SSNBK_COUNTER_CLR_8821C BIT(1) +#define BIT_BITMAP_FORCE_8821C BIT(0) + +/* 2 REG_TX_RX_8821C STATUS */ + +#define BIT_SHIFT_RXPKT_TYPE_8821C 2 +#define BIT_MASK_RXPKT_TYPE_8821C 0x3f +#define BIT_RXPKT_TYPE_8821C(x) (((x) & BIT_MASK_RXPKT_TYPE_8821C) << BIT_SHIFT_RXPKT_TYPE_8821C) +#define BIT_GET_RXPKT_TYPE_8821C(x) (((x) >> BIT_SHIFT_RXPKT_TYPE_8821C) & BIT_MASK_RXPKT_TYPE_8821C) + +#define BIT_TXACT_IND_8821C BIT(1) +#define BIT_RXACT_IND_8821C BIT(0) + +/* 2 REG_WMAC_BACAM_RPMEN_8821C */ + +#define BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C 2 +#define BIT_MASK_BITMAP_SSNBK_COUNTER_8821C 0x3f +#define BIT_BITMAP_SSNBK_COUNTER_8821C(x) (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) << BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) +#define BIT_GET_BITMAP_SSNBK_COUNTER_8821C(x) (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER_8821C) & BIT_MASK_BITMAP_SSNBK_COUNTER_8821C) + +#define BIT_BITMAP_EN_8821C BIT(1) +#define BIT_WMAC_BACAM_RPMEN_8821C BIT(0) + +/* 2 REG_LBDLY_8821C (LOOPBACK DELAY REGISTER) */ + +#define BIT_SHIFT_LBDLY_8821C 0 +#define BIT_MASK_LBDLY_8821C 0x1f +#define BIT_LBDLY_8821C(x) (((x) & BIT_MASK_LBDLY_8821C) << BIT_SHIFT_LBDLY_8821C) +#define BIT_GET_LBDLY_8821C(x) (((x) >> BIT_SHIFT_LBDLY_8821C) & BIT_MASK_LBDLY_8821C) + +/* 2 REG_RXERR_RPT_8821C (RX ERROR REPORT REGISTER) */ + +#define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C 28 +#define BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C 0xf +#define BIT_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) +#define BIT_GET_RXERR_RPT_SEL_V1_3_0_8821C(x) (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0_8821C) & BIT_MASK_RXERR_RPT_SEL_V1_3_0_8821C) + +#define BIT_RXERR_RPT_RST_8821C BIT(27) +#define BIT_RXERR_RPT_SEL_V1_4_8821C BIT(26) +#define BIT_W1S_8821C BIT(23) +#define BIT_UD_SELECT_BSSID_8821C BIT(22) + +#define BIT_SHIFT_UD_SUB_TYPE_8821C 18 +#define BIT_MASK_UD_SUB_TYPE_8821C 0xf +#define BIT_UD_SUB_TYPE_8821C(x) (((x) & BIT_MASK_UD_SUB_TYPE_8821C) << BIT_SHIFT_UD_SUB_TYPE_8821C) +#define BIT_GET_UD_SUB_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_SUB_TYPE_8821C) & BIT_MASK_UD_SUB_TYPE_8821C) + +#define BIT_SHIFT_UD_TYPE_8821C 16 +#define BIT_MASK_UD_TYPE_8821C 0x3 +#define BIT_UD_TYPE_8821C(x) (((x) & BIT_MASK_UD_TYPE_8821C) << BIT_SHIFT_UD_TYPE_8821C) +#define BIT_GET_UD_TYPE_8821C(x) (((x) >> BIT_SHIFT_UD_TYPE_8821C) & BIT_MASK_UD_TYPE_8821C) + +#define BIT_SHIFT_RPT_COUNTER_8821C 0 +#define BIT_MASK_RPT_COUNTER_8821C 0xffff +#define BIT_RPT_COUNTER_8821C(x) (((x) & BIT_MASK_RPT_COUNTER_8821C) << BIT_SHIFT_RPT_COUNTER_8821C) +#define BIT_GET_RPT_COUNTER_8821C(x) (((x) >> BIT_SHIFT_RPT_COUNTER_8821C) & BIT_MASK_RPT_COUNTER_8821C) + +/* 2 REG_WMAC_TRXPTCL_CTL_8821C (WMAC TX/RX PROTOCOL CONTROL REGISTER) */ + +#define BIT_SHIFT_ACKBA_TYPSEL_8821C (60 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBA_TYPSEL_8821C 0xf +#define BIT_ACKBA_TYPSEL_8821C(x) (((x) & BIT_MASK_ACKBA_TYPSEL_8821C) << BIT_SHIFT_ACKBA_TYPSEL_8821C) +#define BIT_GET_ACKBA_TYPSEL_8821C(x) (((x) >> BIT_SHIFT_ACKBA_TYPSEL_8821C) & BIT_MASK_ACKBA_TYPSEL_8821C) + +#define BIT_SHIFT_ACKBA_ACKPCHK_8821C (56 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBA_ACKPCHK_8821C 0xf +#define BIT_ACKBA_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBA_ACKPCHK_8821C) << BIT_SHIFT_ACKBA_ACKPCHK_8821C) +#define BIT_GET_ACKBA_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBA_ACKPCHK_8821C) & BIT_MASK_ACKBA_ACKPCHK_8821C) + +#define BIT_SHIFT_ACKBAR_TYPESEL_8821C (48 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBAR_TYPESEL_8821C 0xff +#define BIT_ACKBAR_TYPESEL_8821C(x) (((x) & BIT_MASK_ACKBAR_TYPESEL_8821C) << BIT_SHIFT_ACKBAR_TYPESEL_8821C) +#define BIT_GET_ACKBAR_TYPESEL_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_TYPESEL_8821C) & BIT_MASK_ACKBAR_TYPESEL_8821C) + +#define BIT_SHIFT_ACKBAR_ACKPCHK_8821C (44 & CPU_OPT_WIDTH) +#define BIT_MASK_ACKBAR_ACKPCHK_8821C 0xf +#define BIT_ACKBAR_ACKPCHK_8821C(x) (((x) & BIT_MASK_ACKBAR_ACKPCHK_8821C) << BIT_SHIFT_ACKBAR_ACKPCHK_8821C) +#define BIT_GET_ACKBAR_ACKPCHK_8821C(x) (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK_8821C) & BIT_MASK_ACKBAR_ACKPCHK_8821C) + +#define BIT_RXBA_IGNOREA2_8821C BIT(42) +#define BIT_EN_SAVE_ALL_TXOPADDR_8821C BIT(41) +#define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV_8821C BIT(40) +#define BIT_DIS_TXBA_AMPDUFCSERR_8821C BIT(39) +#define BIT_DIS_TXBA_RXBARINFULL_8821C BIT(38) +#define BIT_DIS_TXCFE_INFULL_8821C BIT(37) +#define BIT_DIS_TXCTS_INFULL_8821C BIT(36) +#define BIT_EN_TXACKBA_IN_TX_RDG_8821C BIT(35) +#define BIT_EN_TXACKBA_IN_TXOP_8821C BIT(34) +#define BIT_EN_TXCTS_IN_RXNAV_8821C BIT(33) +#define BIT_EN_TXCTS_INTXOP_8821C BIT(32) +#define BIT_BLK_EDCA_BBSLP_8821C BIT(31) +#define BIT_BLK_EDCA_BBSBY_8821C BIT(30) +#define BIT_ACKTO_BLOCK_SCH_EN_8821C BIT(27) +#define BIT_EIFS_BLOCK_SCH_EN_8821C BIT(26) +#define BIT_PLCPCHK_RST_EIFS_8821C BIT(25) +#define BIT_CCA_RST_EIFS_8821C BIT(24) +#define BIT_DIS_UPD_MYRXPKTNAV_8821C BIT(23) +#define BIT_EARLY_TXBA_8821C BIT(22) + +#define BIT_SHIFT_RESP_CHNBUSY_8821C 20 +#define BIT_MASK_RESP_CHNBUSY_8821C 0x3 +#define BIT_RESP_CHNBUSY_8821C(x) (((x) & BIT_MASK_RESP_CHNBUSY_8821C) << BIT_SHIFT_RESP_CHNBUSY_8821C) +#define BIT_GET_RESP_CHNBUSY_8821C(x) (((x) >> BIT_SHIFT_RESP_CHNBUSY_8821C) & BIT_MASK_RESP_CHNBUSY_8821C) + +#define BIT_RESP_DCTS_EN_8821C BIT(19) +#define BIT_RESP_DCFE_EN_8821C BIT(18) +#define BIT_RESP_SPLCPEN_8821C BIT(17) +#define BIT_RESP_SGIEN_8821C BIT(16) +#define BIT_RESP_LDPC_EN_8821C BIT(15) +#define BIT_DIS_RESP_ACKINCCA_8821C BIT(14) +#define BIT_DIS_RESP_CTSINCCA_8821C BIT(13) + +#define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C 10 +#define BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C 0x7 +#define BIT_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) +#define BIT_GET_R_WMAC_SECOND_CCA_TIMER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER_8821C) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER_8821C) + +#define BIT_SHIFT_RFMOD_8821C 7 +#define BIT_MASK_RFMOD_8821C 0x3 +#define BIT_RFMOD_8821C(x) (((x) & BIT_MASK_RFMOD_8821C) << BIT_SHIFT_RFMOD_8821C) +#define BIT_GET_RFMOD_8821C(x) (((x) >> BIT_SHIFT_RFMOD_8821C) & BIT_MASK_RFMOD_8821C) + +#define BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C 5 +#define BIT_MASK_RESP_CTS_DYNBW_SEL_8821C 0x3 +#define BIT_RESP_CTS_DYNBW_SEL_8821C(x) (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) << BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) +#define BIT_GET_RESP_CTS_DYNBW_SEL_8821C(x) (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL_8821C) & BIT_MASK_RESP_CTS_DYNBW_SEL_8821C) + +#define BIT_DLY_TX_WAIT_RXANTSEL_8821C BIT(4) +#define BIT_TXRESP_BY_RXANTSEL_8821C BIT(3) + +#define BIT_SHIFT_ORIG_DCTS_CHK_8821C 0 +#define BIT_MASK_ORIG_DCTS_CHK_8821C 0x3 +#define BIT_ORIG_DCTS_CHK_8821C(x) (((x) & BIT_MASK_ORIG_DCTS_CHK_8821C) << BIT_SHIFT_ORIG_DCTS_CHK_8821C) +#define BIT_GET_ORIG_DCTS_CHK_8821C(x) (((x) >> BIT_SHIFT_ORIG_DCTS_CHK_8821C) & BIT_MASK_ORIG_DCTS_CHK_8821C) + +/* 2 REG_CAMCMD_8821C (CAM COMMAND REGISTER) */ +#define BIT_SECCAM_POLLING_8821C BIT(31) +#define BIT_SECCAM_CLR_8821C BIT(30) +#define BIT_MFBCAM_CLR_8821C BIT(29) +#define BIT_SECCAM_WE_8821C BIT(16) + +#define BIT_SHIFT_SECCAM_ADDR_V2_8821C 0 +#define BIT_MASK_SECCAM_ADDR_V2_8821C 0x3ff +#define BIT_SECCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_SECCAM_ADDR_V2_8821C) << BIT_SHIFT_SECCAM_ADDR_V2_8821C) +#define BIT_GET_SECCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_SECCAM_ADDR_V2_8821C) & BIT_MASK_SECCAM_ADDR_V2_8821C) + +/* 2 REG_CAMWRITE_8821C (CAM WRITE REGISTER) */ + +#define BIT_SHIFT_CAMW_DATA_8821C 0 +#define BIT_MASK_CAMW_DATA_8821C 0xffffffffL +#define BIT_CAMW_DATA_8821C(x) (((x) & BIT_MASK_CAMW_DATA_8821C) << BIT_SHIFT_CAMW_DATA_8821C) +#define BIT_GET_CAMW_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMW_DATA_8821C) & BIT_MASK_CAMW_DATA_8821C) + +/* 2 REG_CAMREAD_8821C (CAM READ REGISTER) */ + +#define BIT_SHIFT_CAMR_DATA_8821C 0 +#define BIT_MASK_CAMR_DATA_8821C 0xffffffffL +#define BIT_CAMR_DATA_8821C(x) (((x) & BIT_MASK_CAMR_DATA_8821C) << BIT_SHIFT_CAMR_DATA_8821C) +#define BIT_GET_CAMR_DATA_8821C(x) (((x) >> BIT_SHIFT_CAMR_DATA_8821C) & BIT_MASK_CAMR_DATA_8821C) + +/* 2 REG_CAMDBG_8821C (CAM DEBUG REGISTER) */ +#define BIT_SECCAM_INFO_8821C BIT(31) +#define BIT_SEC_KEYFOUND_8821C BIT(15) + +#define BIT_SHIFT_CAMDBG_SEC_TYPE_8821C 12 +#define BIT_MASK_CAMDBG_SEC_TYPE_8821C 0x7 +#define BIT_CAMDBG_SEC_TYPE_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) << BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) +#define BIT_GET_CAMDBG_SEC_TYPE_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE_8821C) & BIT_MASK_CAMDBG_SEC_TYPE_8821C) + +#define BIT_CAMDBG_EXT_SECTYPE_8821C BIT(11) + +#define BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C 5 +#define BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C 0x1f +#define BIT_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) +#define BIT_GET_CAMDBG_MIC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_MIC_KEY_IDX_8821C) + +#define BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C 0 +#define BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C 0x1f +#define BIT_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) +#define BIT_GET_CAMDBG_SEC_KEY_IDX_8821C(x) (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX_8821C) & BIT_MASK_CAMDBG_SEC_KEY_IDX_8821C) + +/* 2 REG_RXFILTER_ACTION_1_8821C */ + +#define BIT_SHIFT_RXFILTER_ACTION_1_8821C 0 +#define BIT_MASK_RXFILTER_ACTION_1_8821C 0xff +#define BIT_RXFILTER_ACTION_1_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_1_8821C) << BIT_SHIFT_RXFILTER_ACTION_1_8821C) +#define BIT_GET_RXFILTER_ACTION_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_1_8821C) & BIT_MASK_RXFILTER_ACTION_1_8821C) + +/* 2 REG_RXFILTER_CATEGORY_1_8821C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_1_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_1_8821C 0xff +#define BIT_RXFILTER_CATEGORY_1_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) +#define BIT_GET_RXFILTER_CATEGORY_1_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1_8821C) & BIT_MASK_RXFILTER_CATEGORY_1_8821C) + +/* 2 REG_SECCFG_8821C (SECURITY CONFIGURATION REGISTER) */ +#define BIT_DIS_GCLK_WAPI_8821C BIT(15) +#define BIT_DIS_GCLK_AES_8821C BIT(14) +#define BIT_DIS_GCLK_TKIP_8821C BIT(13) +#define BIT_AES_SEL_QC_1_8821C BIT(12) +#define BIT_AES_SEL_QC_0_8821C BIT(11) +#define BIT_CHK_BMC_8821C BIT(9) +#define BIT_CHK_KEYID_8821C BIT(8) +#define BIT_RXBCUSEDK_8821C BIT(7) +#define BIT_TXBCUSEDK_8821C BIT(6) +#define BIT_NOSKMC_8821C BIT(5) +#define BIT_SKBYA2_8821C BIT(4) +#define BIT_RXDEC_8821C BIT(3) +#define BIT_TXENC_8821C BIT(2) +#define BIT_RXUHUSEDK_8821C BIT(1) +#define BIT_TXUHUSEDK_8821C BIT(0) + +/* 2 REG_RXFILTER_ACTION_3_8821C */ + +#define BIT_SHIFT_RXFILTER_ACTION_3_8821C 0 +#define BIT_MASK_RXFILTER_ACTION_3_8821C 0xff +#define BIT_RXFILTER_ACTION_3_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_3_8821C) << BIT_SHIFT_RXFILTER_ACTION_3_8821C) +#define BIT_GET_RXFILTER_ACTION_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_3_8821C) & BIT_MASK_RXFILTER_ACTION_3_8821C) + +/* 2 REG_RXFILTER_CATEGORY_3_8821C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_3_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_3_8821C 0xff +#define BIT_RXFILTER_CATEGORY_3_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) +#define BIT_GET_RXFILTER_CATEGORY_3_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3_8821C) & BIT_MASK_RXFILTER_CATEGORY_3_8821C) + +/* 2 REG_RXFILTER_ACTION_2_8821C */ + +#define BIT_SHIFT_RXFILTER_ACTION_2_8821C 0 +#define BIT_MASK_RXFILTER_ACTION_2_8821C 0xff +#define BIT_RXFILTER_ACTION_2_8821C(x) (((x) & BIT_MASK_RXFILTER_ACTION_2_8821C) << BIT_SHIFT_RXFILTER_ACTION_2_8821C) +#define BIT_GET_RXFILTER_ACTION_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_ACTION_2_8821C) & BIT_MASK_RXFILTER_ACTION_2_8821C) + +/* 2 REG_RXFILTER_CATEGORY_2_8821C */ + +#define BIT_SHIFT_RXFILTER_CATEGORY_2_8821C 0 +#define BIT_MASK_RXFILTER_CATEGORY_2_8821C 0xff +#define BIT_RXFILTER_CATEGORY_2_8821C(x) (((x) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) << BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) +#define BIT_GET_RXFILTER_CATEGORY_2_8821C(x) (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2_8821C) & BIT_MASK_RXFILTER_CATEGORY_2_8821C) + +/* 2 REG_RXFLTMAP4_8821C (RX FILTER MAP GROUP 4) */ +#define BIT_CTRLFLT15EN_FW_8821C BIT(15) +#define BIT_CTRLFLT14EN_FW_8821C BIT(14) +#define BIT_CTRLFLT13EN_FW_8821C BIT(13) +#define BIT_CTRLFLT12EN_FW_8821C BIT(12) +#define BIT_CTRLFLT11EN_FW_8821C BIT(11) +#define BIT_CTRLFLT10EN_FW_8821C BIT(10) +#define BIT_CTRLFLT9EN_FW_8821C BIT(9) +#define BIT_CTRLFLT8EN_FW_8821C BIT(8) +#define BIT_CTRLFLT7EN_FW_8821C BIT(7) +#define BIT_CTRLFLT6EN_FW_8821C BIT(6) +#define BIT_CTRLFLT5EN_FW_8821C BIT(5) +#define BIT_CTRLFLT4EN_FW_8821C BIT(4) +#define BIT_CTRLFLT3EN_FW_8821C BIT(3) +#define BIT_CTRLFLT2EN_FW_8821C BIT(2) +#define BIT_CTRLFLT1EN_FW_8821C BIT(1) +#define BIT_CTRLFLT0EN_FW_8821C BIT(0) + +/* 2 REG_RXFLTMAP3_8821C (RX FILTER MAP GROUP 3) */ +#define BIT_MGTFLT15EN_FW_8821C BIT(15) +#define BIT_MGTFLT14EN_FW_8821C BIT(14) +#define BIT_MGTFLT13EN_FW_8821C BIT(13) +#define BIT_MGTFLT12EN_FW_8821C BIT(12) +#define BIT_MGTFLT11EN_FW_8821C BIT(11) +#define BIT_MGTFLT10EN_FW_8821C BIT(10) +#define BIT_MGTFLT9EN_FW_8821C BIT(9) +#define BIT_MGTFLT8EN_FW_8821C BIT(8) +#define BIT_MGTFLT7EN_FW_8821C BIT(7) +#define BIT_MGTFLT6EN_FW_8821C BIT(6) +#define BIT_MGTFLT5EN_FW_8821C BIT(5) +#define BIT_MGTFLT4EN_FW_8821C BIT(4) +#define BIT_MGTFLT3EN_FW_8821C BIT(3) +#define BIT_MGTFLT2EN_FW_8821C BIT(2) +#define BIT_MGTFLT1EN_FW_8821C BIT(1) +#define BIT_MGTFLT0EN_FW_8821C BIT(0) + +/* 2 REG_RXFLTMAP6_8821C (RX FILTER MAP GROUP 3) */ +#define BIT_ACTIONFLT15EN_FW_8821C BIT(15) +#define BIT_ACTIONFLT14EN_FW_8821C BIT(14) +#define BIT_ACTIONFLT13EN_FW_8821C BIT(13) +#define BIT_ACTIONFLT12EN_FW_8821C BIT(12) +#define BIT_ACTIONFLT11EN_FW_8821C BIT(11) +#define BIT_ACTIONFLT10EN_FW_8821C BIT(10) +#define BIT_ACTIONFLT9EN_FW_8821C BIT(9) +#define BIT_ACTIONFLT8EN_FW_8821C BIT(8) +#define BIT_ACTIONFLT7EN_FW_8821C BIT(7) +#define BIT_ACTIONFLT6EN_FW_8821C BIT(6) +#define BIT_ACTIONFLT5EN_FW_8821C BIT(5) +#define BIT_ACTIONFLT4EN_FW_8821C BIT(4) +#define BIT_ACTIONFLT3EN_FW_8821C BIT(3) +#define BIT_ACTIONFLT2EN_FW_8821C BIT(2) +#define BIT_ACTIONFLT1EN_FW_8821C BIT(1) +#define BIT_ACTIONFLT0EN_FW_8821C BIT(0) + +/* 2 REG_RXFLTMAP5_8821C (RX FILTER MAP GROUP 3) */ +#define BIT_DATAFLT15EN_FW_8821C BIT(15) +#define BIT_DATAFLT14EN_FW_8821C BIT(14) +#define BIT_DATAFLT13EN_FW_8821C BIT(13) +#define BIT_DATAFLT12EN_FW_8821C BIT(12) +#define BIT_DATAFLT11EN_FW_8821C BIT(11) +#define BIT_DATAFLT10EN_FW_8821C BIT(10) +#define BIT_DATAFLT9EN_FW_8821C BIT(9) +#define BIT_DATAFLT8EN_FW_8821C BIT(8) +#define BIT_DATAFLT7EN_FW_8821C BIT(7) +#define BIT_DATAFLT6EN_FW_8821C BIT(6) +#define BIT_DATAFLT5EN_FW_8821C BIT(5) +#define BIT_DATAFLT4EN_FW_8821C BIT(4) +#define BIT_DATAFLT3EN_FW_8821C BIT(3) +#define BIT_DATAFLT2EN_FW_8821C BIT(2) +#define BIT_DATAFLT1EN_FW_8821C BIT(1) +#define BIT_DATAFLT0EN_FW_8821C BIT(0) + +/* 2 REG_WMMPS_UAPSD_TID_8821C (WMM POWER SAVE UAPSD TID REGISTER) */ +#define BIT_WMMPS_UAPSD_TID7_8821C BIT(7) +#define BIT_WMMPS_UAPSD_TID6_8821C BIT(6) +#define BIT_WMMPS_UAPSD_TID5_8821C BIT(5) +#define BIT_WMMPS_UAPSD_TID4_8821C BIT(4) +#define BIT_WMMPS_UAPSD_TID3_8821C BIT(3) +#define BIT_WMMPS_UAPSD_TID2_8821C BIT(2) +#define BIT_WMMPS_UAPSD_TID1_8821C BIT(1) +#define BIT_WMMPS_UAPSD_TID0_8821C BIT(0) + +/* 2 REG_PS_RX_INFO_8821C (POWER SAVE RX INFORMATION REGISTER) */ + +#define BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C 5 +#define BIT_MASK_PORTSEL__PS_RX_INFO_8821C 0x7 +#define BIT_PORTSEL__PS_RX_INFO_8821C(x) (((x) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) << BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) +#define BIT_GET_PORTSEL__PS_RX_INFO_8821C(x) (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO_8821C) & BIT_MASK_PORTSEL__PS_RX_INFO_8821C) + +#define BIT_RXCTRLIN0_8821C BIT(4) +#define BIT_RXMGTIN0_8821C BIT(3) +#define BIT_RXDATAIN2_8821C BIT(2) +#define BIT_RXDATAIN1_8821C BIT(1) +#define BIT_RXDATAIN0_8821C BIT(0) + +/* 2 REG_NAN_RX_TSF_FILTER_8821C(NAN_RX_TSF_ADDRESS_FILTER) */ +#define BIT_CHK_TSF_TA_8821C BIT(2) +#define BIT_CHK_TSF_CBSSID_8821C BIT(1) +#define BIT_CHK_TSF_EN_8821C BIT(0) + +/* 2 REG_WOW_CTRL_8821C (WAKE ON WLAN CONTROL REGISTER) */ + +#define BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C 6 +#define BIT_MASK_PSF_BSSIDSEL_B2B1_8821C 0x3 +#define BIT_PSF_BSSIDSEL_B2B1_8821C(x) (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) << BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) +#define BIT_GET_PSF_BSSIDSEL_B2B1_8821C(x) (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1_8821C) & BIT_MASK_PSF_BSSIDSEL_B2B1_8821C) + +#define BIT_WOWHCI_8821C BIT(5) +#define BIT_PSF_BSSIDSEL_B0_8821C BIT(4) +#define BIT_UWF_8821C BIT(3) +#define BIT_MAGIC_8821C BIT(2) +#define BIT_WOWEN_8821C BIT(1) +#define BIT_FORCE_WAKEUP_8821C BIT(0) + +/* 2 REG_LPNAV_CTRL_8821C (LOW POWER NAV CONTROL REGISTER) */ +#define BIT_LPNAV_EN_8821C BIT(31) + +#define BIT_SHIFT_LPNAV_EARLY_8821C 16 +#define BIT_MASK_LPNAV_EARLY_8821C 0x7fff +#define BIT_LPNAV_EARLY_8821C(x) (((x) & BIT_MASK_LPNAV_EARLY_8821C) << BIT_SHIFT_LPNAV_EARLY_8821C) +#define BIT_GET_LPNAV_EARLY_8821C(x) (((x) >> BIT_SHIFT_LPNAV_EARLY_8821C) & BIT_MASK_LPNAV_EARLY_8821C) + +#define BIT_SHIFT_LPNAV_TH_8821C 0 +#define BIT_MASK_LPNAV_TH_8821C 0xffff +#define BIT_LPNAV_TH_8821C(x) (((x) & BIT_MASK_LPNAV_TH_8821C) << BIT_SHIFT_LPNAV_TH_8821C) +#define BIT_GET_LPNAV_TH_8821C(x) (((x) >> BIT_SHIFT_LPNAV_TH_8821C) & BIT_MASK_LPNAV_TH_8821C) + +/* 2 REG_WKFMCAM_CMD_8821C (WAKEUP FRAME CAM COMMAND REGISTER) */ +#define BIT_WKFCAM_POLLING_V1_8821C BIT(31) +#define BIT_WKFCAM_CLR_V1_8821C BIT(30) +#define BIT_WKFCAM_WE_8821C BIT(16) + +#define BIT_SHIFT_WKFCAM_ADDR_V2_8821C 8 +#define BIT_MASK_WKFCAM_ADDR_V2_8821C 0xff +#define BIT_WKFCAM_ADDR_V2_8821C(x) (((x) & BIT_MASK_WKFCAM_ADDR_V2_8821C) << BIT_SHIFT_WKFCAM_ADDR_V2_8821C) +#define BIT_GET_WKFCAM_ADDR_V2_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2_8821C) & BIT_MASK_WKFCAM_ADDR_V2_8821C) + +#define BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C 0 +#define BIT_MASK_WKFCAM_CAM_NUM_V1_8821C 0xff +#define BIT_WKFCAM_CAM_NUM_V1_8821C(x) (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) << BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) +#define BIT_GET_WKFCAM_CAM_NUM_V1_8821C(x) (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1_8821C) & BIT_MASK_WKFCAM_CAM_NUM_V1_8821C) + +/* 2 REG_WKFMCAM_RWD_8821C (WAKEUP FRAME READ/WRITE DATA) */ + +#define BIT_SHIFT_WKFMCAM_RWD_8821C 0 +#define BIT_MASK_WKFMCAM_RWD_8821C 0xffffffffL +#define BIT_WKFMCAM_RWD_8821C(x) (((x) & BIT_MASK_WKFMCAM_RWD_8821C) << BIT_SHIFT_WKFMCAM_RWD_8821C) +#define BIT_GET_WKFMCAM_RWD_8821C(x) (((x) >> BIT_SHIFT_WKFMCAM_RWD_8821C) & BIT_MASK_WKFMCAM_RWD_8821C) + +/* 2 REG_RXFLTMAP1_8821C (RX FILTER MAP GROUP 1) */ +#define BIT_CTRLFLT15EN_8821C BIT(15) +#define BIT_CTRLFLT14EN_8821C BIT(14) +#define BIT_CTRLFLT13EN_8821C BIT(13) +#define BIT_CTRLFLT12EN_8821C BIT(12) +#define BIT_CTRLFLT11EN_8821C BIT(11) +#define BIT_CTRLFLT10EN_8821C BIT(10) +#define BIT_CTRLFLT9EN_8821C BIT(9) +#define BIT_CTRLFLT8EN_8821C BIT(8) +#define BIT_CTRLFLT7EN_8821C BIT(7) +#define BIT_CTRLFLT6EN_8821C BIT(6) +#define BIT_CTRLFLT5EN_8821C BIT(5) +#define BIT_CTRLFLT4EN_8821C BIT(4) +#define BIT_CTRLFLT3EN_8821C BIT(3) +#define BIT_CTRLFLT2EN_8821C BIT(2) +#define BIT_CTRLFLT1EN_8821C BIT(1) +#define BIT_CTRLFLT0EN_8821C BIT(0) + +/* 2 REG_RXFLTMAP0_8821C (RX FILTER MAP GROUP 0) */ +#define BIT_MGTFLT15EN_8821C BIT(15) +#define BIT_MGTFLT14EN_8821C BIT(14) +#define BIT_MGTFLT13EN_8821C BIT(13) +#define BIT_MGTFLT12EN_8821C BIT(12) +#define BIT_MGTFLT11EN_8821C BIT(11) +#define BIT_MGTFLT10EN_8821C BIT(10) +#define BIT_MGTFLT9EN_8821C BIT(9) +#define BIT_MGTFLT8EN_8821C BIT(8) +#define BIT_MGTFLT7EN_8821C BIT(7) +#define BIT_MGTFLT6EN_8821C BIT(6) +#define BIT_MGTFLT5EN_8821C BIT(5) +#define BIT_MGTFLT4EN_8821C BIT(4) +#define BIT_MGTFLT3EN_8821C BIT(3) +#define BIT_MGTFLT2EN_8821C BIT(2) +#define BIT_MGTFLT1EN_8821C BIT(1) +#define BIT_MGTFLT0EN_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_RXFLTMAP_8821C (RX FILTER MAP GROUP 2) */ +#define BIT_DATAFLT15EN_8821C BIT(15) +#define BIT_DATAFLT14EN_8821C BIT(14) +#define BIT_DATAFLT13EN_8821C BIT(13) +#define BIT_DATAFLT12EN_8821C BIT(12) +#define BIT_DATAFLT11EN_8821C BIT(11) +#define BIT_DATAFLT10EN_8821C BIT(10) +#define BIT_DATAFLT9EN_8821C BIT(9) +#define BIT_DATAFLT8EN_8821C BIT(8) +#define BIT_DATAFLT7EN_8821C BIT(7) +#define BIT_DATAFLT6EN_8821C BIT(6) +#define BIT_DATAFLT5EN_8821C BIT(5) +#define BIT_DATAFLT4EN_8821C BIT(4) +#define BIT_DATAFLT3EN_8821C BIT(3) +#define BIT_DATAFLT2EN_8821C BIT(2) +#define BIT_DATAFLT1EN_8821C BIT(1) +#define BIT_DATAFLT0EN_8821C BIT(0) + +/* 2 REG_BCN_PSR_RPT_8821C (BEACON PARSER REPORT REGISTER) */ + +#define BIT_SHIFT_DTIM_CNT_8821C 24 +#define BIT_MASK_DTIM_CNT_8821C 0xff +#define BIT_DTIM_CNT_8821C(x) (((x) & BIT_MASK_DTIM_CNT_8821C) << BIT_SHIFT_DTIM_CNT_8821C) +#define BIT_GET_DTIM_CNT_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT_8821C) & BIT_MASK_DTIM_CNT_8821C) + +#define BIT_SHIFT_DTIM_PERIOD_8821C 16 +#define BIT_MASK_DTIM_PERIOD_8821C 0xff +#define BIT_DTIM_PERIOD_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD_8821C) << BIT_SHIFT_DTIM_PERIOD_8821C) +#define BIT_GET_DTIM_PERIOD_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD_8821C) & BIT_MASK_DTIM_PERIOD_8821C) + +#define BIT_DTIM_8821C BIT(15) +#define BIT_TIM_8821C BIT(14) + +#define BIT_SHIFT_PS_AID_0_8821C 0 +#define BIT_MASK_PS_AID_0_8821C 0x7ff +#define BIT_PS_AID_0_8821C(x) (((x) & BIT_MASK_PS_AID_0_8821C) << BIT_SHIFT_PS_AID_0_8821C) +#define BIT_GET_PS_AID_0_8821C(x) (((x) >> BIT_SHIFT_PS_AID_0_8821C) & BIT_MASK_PS_AID_0_8821C) + +/* 2 REG_FLC_TRPC_8821C (TIMER OF FLC_RPC) */ +#define BIT_FLC_RPCT_V1_8821C BIT(7) +#define BIT_MODE_8821C BIT(6) + +#define BIT_SHIFT_TRPCD_8821C 0 +#define BIT_MASK_TRPCD_8821C 0x3f +#define BIT_TRPCD_8821C(x) (((x) & BIT_MASK_TRPCD_8821C) << BIT_SHIFT_TRPCD_8821C) +#define BIT_GET_TRPCD_8821C(x) (((x) >> BIT_SHIFT_TRPCD_8821C) & BIT_MASK_TRPCD_8821C) + +/* 2 REG_FLC_PTS_8821C (PKT TYPE SELECTION OF FLC_RPC T) */ +#define BIT_CMF_8821C BIT(2) +#define BIT_CCF_8821C BIT(1) +#define BIT_CDF_8821C BIT(0) + +/* 2 REG_FLC_RPCT_8821C (FLC_RPC THRESHOLD) */ + +#define BIT_SHIFT_FLC_RPCT_8821C 0 +#define BIT_MASK_FLC_RPCT_8821C 0xff +#define BIT_FLC_RPCT_8821C(x) (((x) & BIT_MASK_FLC_RPCT_8821C) << BIT_SHIFT_FLC_RPCT_8821C) +#define BIT_GET_FLC_RPCT_8821C(x) (((x) >> BIT_SHIFT_FLC_RPCT_8821C) & BIT_MASK_FLC_RPCT_8821C) + +/* 2 REG_FLC_RPC_8821C (FW LPS CONDITION -- RX PKT COUNTER) */ + +#define BIT_SHIFT_FLC_RPC_8821C 0 +#define BIT_MASK_FLC_RPC_8821C 0xff +#define BIT_FLC_RPC_8821C(x) (((x) & BIT_MASK_FLC_RPC_8821C) << BIT_SHIFT_FLC_RPC_8821C) +#define BIT_GET_FLC_RPC_8821C(x) (((x) >> BIT_SHIFT_FLC_RPC_8821C) & BIT_MASK_FLC_RPC_8821C) + +/* 2 REG_RXPKTMON_CTRL_8821C */ + +#define BIT_SHIFT_RXBKQPKT_SEQ_8821C 20 +#define BIT_MASK_RXBKQPKT_SEQ_8821C 0xf +#define BIT_RXBKQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBKQPKT_SEQ_8821C) << BIT_SHIFT_RXBKQPKT_SEQ_8821C) +#define BIT_GET_RXBKQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBKQPKT_SEQ_8821C) & BIT_MASK_RXBKQPKT_SEQ_8821C) + +#define BIT_SHIFT_RXBEQPKT_SEQ_8821C 16 +#define BIT_MASK_RXBEQPKT_SEQ_8821C 0xf +#define BIT_RXBEQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXBEQPKT_SEQ_8821C) << BIT_SHIFT_RXBEQPKT_SEQ_8821C) +#define BIT_GET_RXBEQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXBEQPKT_SEQ_8821C) & BIT_MASK_RXBEQPKT_SEQ_8821C) + +#define BIT_SHIFT_RXVIQPKT_SEQ_8821C 12 +#define BIT_MASK_RXVIQPKT_SEQ_8821C 0xf +#define BIT_RXVIQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVIQPKT_SEQ_8821C) << BIT_SHIFT_RXVIQPKT_SEQ_8821C) +#define BIT_GET_RXVIQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVIQPKT_SEQ_8821C) & BIT_MASK_RXVIQPKT_SEQ_8821C) + +#define BIT_SHIFT_RXVOQPKT_SEQ_8821C 8 +#define BIT_MASK_RXVOQPKT_SEQ_8821C 0xf +#define BIT_RXVOQPKT_SEQ_8821C(x) (((x) & BIT_MASK_RXVOQPKT_SEQ_8821C) << BIT_SHIFT_RXVOQPKT_SEQ_8821C) +#define BIT_GET_RXVOQPKT_SEQ_8821C(x) (((x) >> BIT_SHIFT_RXVOQPKT_SEQ_8821C) & BIT_MASK_RXVOQPKT_SEQ_8821C) + +#define BIT_RXBKQPKT_ERR_8821C BIT(7) +#define BIT_RXBEQPKT_ERR_8821C BIT(6) +#define BIT_RXVIQPKT_ERR_8821C BIT(5) +#define BIT_RXVOQPKT_ERR_8821C BIT(4) +#define BIT_RXDMA_MON_EN_8821C BIT(2) +#define BIT_RXPKT_MON_RST_8821C BIT(1) +#define BIT_RXPKT_MON_EN_8821C BIT(0) + +/* 2 REG_STATE_MON_8821C */ + +#define BIT_SHIFT_STATE_SEL_8821C 24 +#define BIT_MASK_STATE_SEL_8821C 0x1f +#define BIT_STATE_SEL_8821C(x) (((x) & BIT_MASK_STATE_SEL_8821C) << BIT_SHIFT_STATE_SEL_8821C) +#define BIT_GET_STATE_SEL_8821C(x) (((x) >> BIT_SHIFT_STATE_SEL_8821C) & BIT_MASK_STATE_SEL_8821C) + +#define BIT_SHIFT_STATE_INFO_8821C 8 +#define BIT_MASK_STATE_INFO_8821C 0xff +#define BIT_STATE_INFO_8821C(x) (((x) & BIT_MASK_STATE_INFO_8821C) << BIT_SHIFT_STATE_INFO_8821C) +#define BIT_GET_STATE_INFO_8821C(x) (((x) >> BIT_SHIFT_STATE_INFO_8821C) & BIT_MASK_STATE_INFO_8821C) + +#define BIT_UPD_NXT_STATE_8821C BIT(7) + +#define BIT_SHIFT_CUR_STATE_8821C 0 +#define BIT_MASK_CUR_STATE_8821C 0x7f +#define BIT_CUR_STATE_8821C(x) (((x) & BIT_MASK_CUR_STATE_8821C) << BIT_SHIFT_CUR_STATE_8821C) +#define BIT_GET_CUR_STATE_8821C(x) (((x) >> BIT_SHIFT_CUR_STATE_8821C) & BIT_MASK_CUR_STATE_8821C) + +/* 2 REG_ERROR_MON_8821C */ +#define BIT_MACRX_ERR_1_8821C BIT(17) +#define BIT_MACRX_ERR_0_8821C BIT(16) +#define BIT_MACTX_ERR_3_8821C BIT(3) +#define BIT_MACTX_ERR_2_8821C BIT(2) +#define BIT_MACTX_ERR_1_8821C BIT(1) +#define BIT_MACTX_ERR_0_8821C BIT(0) + +/* 2 REG_SEARCH_MACID_8821C */ +#define BIT_EN_TXRPTBUF_CLK_8821C BIT(31) + +#define BIT_SHIFT_INFO_INDEX_OFFSET_8821C 16 +#define BIT_MASK_INFO_INDEX_OFFSET_8821C 0x1fff +#define BIT_INFO_INDEX_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_INDEX_OFFSET_8821C) << BIT_SHIFT_INFO_INDEX_OFFSET_8821C) +#define BIT_GET_INFO_INDEX_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET_8821C) & BIT_MASK_INFO_INDEX_OFFSET_8821C) + +#define BIT_WMAC_SRCH_FIFOFULL_8821C BIT(15) +#define BIT_DIS_INFOSRCH_8821C BIT(14) +#define BIT_DISABLE_B0_8821C BIT(13) + +#define BIT_SHIFT_INFO_ADDR_OFFSET_8821C 0 +#define BIT_MASK_INFO_ADDR_OFFSET_8821C 0x1fff +#define BIT_INFO_ADDR_OFFSET_8821C(x) (((x) & BIT_MASK_INFO_ADDR_OFFSET_8821C) << BIT_SHIFT_INFO_ADDR_OFFSET_8821C) +#define BIT_GET_INFO_ADDR_OFFSET_8821C(x) (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET_8821C) & BIT_MASK_INFO_ADDR_OFFSET_8821C) + +/* 2 REG_BT_COEX_TABLE_8821C (BT-COEXISTENCE CONTROL REGISTER) */ +#define BIT_PRI_MASK_RX_RESP_8821C BIT(126) +#define BIT_PRI_MASK_RXOFDM_8821C BIT(125) +#define BIT_PRI_MASK_RXCCK_8821C BIT(124) + +#define BIT_SHIFT_PRI_MASK_TXAC_8821C (117 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_TXAC_8821C 0x7f +#define BIT_PRI_MASK_TXAC_8821C(x) (((x) & BIT_MASK_PRI_MASK_TXAC_8821C) << BIT_SHIFT_PRI_MASK_TXAC_8821C) +#define BIT_GET_PRI_MASK_TXAC_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TXAC_8821C) & BIT_MASK_PRI_MASK_TXAC_8821C) + +#define BIT_SHIFT_PRI_MASK_NAV_8821C (109 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_NAV_8821C 0xff +#define BIT_PRI_MASK_NAV_8821C(x) (((x) & BIT_MASK_PRI_MASK_NAV_8821C) << BIT_SHIFT_PRI_MASK_NAV_8821C) +#define BIT_GET_PRI_MASK_NAV_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NAV_8821C) & BIT_MASK_PRI_MASK_NAV_8821C) + +#define BIT_PRI_MASK_CCK_8821C BIT(108) +#define BIT_PRI_MASK_OFDM_8821C BIT(107) +#define BIT_PRI_MASK_RTY_8821C BIT(106) + +#define BIT_SHIFT_PRI_MASK_NUM_8821C (102 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_NUM_8821C 0xf +#define BIT_PRI_MASK_NUM_8821C(x) (((x) & BIT_MASK_PRI_MASK_NUM_8821C) << BIT_SHIFT_PRI_MASK_NUM_8821C) +#define BIT_GET_PRI_MASK_NUM_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_NUM_8821C) & BIT_MASK_PRI_MASK_NUM_8821C) + +#define BIT_SHIFT_PRI_MASK_TYPE_8821C (98 & CPU_OPT_WIDTH) +#define BIT_MASK_PRI_MASK_TYPE_8821C 0xf +#define BIT_PRI_MASK_TYPE_8821C(x) (((x) & BIT_MASK_PRI_MASK_TYPE_8821C) << BIT_SHIFT_PRI_MASK_TYPE_8821C) +#define BIT_GET_PRI_MASK_TYPE_8821C(x) (((x) >> BIT_SHIFT_PRI_MASK_TYPE_8821C) & BIT_MASK_PRI_MASK_TYPE_8821C) + +#define BIT_OOB_8821C BIT(97) +#define BIT_ANT_SEL_8821C BIT(96) + +#define BIT_SHIFT_BREAK_TABLE_2_8821C (80 & CPU_OPT_WIDTH) +#define BIT_MASK_BREAK_TABLE_2_8821C 0xffff +#define BIT_BREAK_TABLE_2_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_2_8821C) << BIT_SHIFT_BREAK_TABLE_2_8821C) +#define BIT_GET_BREAK_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_2_8821C) & BIT_MASK_BREAK_TABLE_2_8821C) + +#define BIT_SHIFT_BREAK_TABLE_1_8821C (64 & CPU_OPT_WIDTH) +#define BIT_MASK_BREAK_TABLE_1_8821C 0xffff +#define BIT_BREAK_TABLE_1_8821C(x) (((x) & BIT_MASK_BREAK_TABLE_1_8821C) << BIT_SHIFT_BREAK_TABLE_1_8821C) +#define BIT_GET_BREAK_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_BREAK_TABLE_1_8821C) & BIT_MASK_BREAK_TABLE_1_8821C) + +#define BIT_SHIFT_COEX_TABLE_2_8821C (32 & CPU_OPT_WIDTH) +#define BIT_MASK_COEX_TABLE_2_8821C 0xffffffffL +#define BIT_COEX_TABLE_2_8821C(x) (((x) & BIT_MASK_COEX_TABLE_2_8821C) << BIT_SHIFT_COEX_TABLE_2_8821C) +#define BIT_GET_COEX_TABLE_2_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_2_8821C) & BIT_MASK_COEX_TABLE_2_8821C) + +#define BIT_SHIFT_COEX_TABLE_1_8821C 0 +#define BIT_MASK_COEX_TABLE_1_8821C 0xffffffffL +#define BIT_COEX_TABLE_1_8821C(x) (((x) & BIT_MASK_COEX_TABLE_1_8821C) << BIT_SHIFT_COEX_TABLE_1_8821C) +#define BIT_GET_COEX_TABLE_1_8821C(x) (((x) >> BIT_SHIFT_COEX_TABLE_1_8821C) & BIT_MASK_COEX_TABLE_1_8821C) + +/* 2 REG_RXCMD_0_8821C */ +#define BIT_RXCMD_EN_8821C BIT(31) + +#define BIT_SHIFT_RXCMD_INFO_8821C 0 +#define BIT_MASK_RXCMD_INFO_8821C 0x7fffffffL +#define BIT_RXCMD_INFO_8821C(x) (((x) & BIT_MASK_RXCMD_INFO_8821C) << BIT_SHIFT_RXCMD_INFO_8821C) +#define BIT_GET_RXCMD_INFO_8821C(x) (((x) >> BIT_SHIFT_RXCMD_INFO_8821C) & BIT_MASK_RXCMD_INFO_8821C) + +/* 2 REG_RXCMD_1_8821C */ + +#define BIT_SHIFT_RXCMD_PRD_8821C 0 +#define BIT_MASK_RXCMD_PRD_8821C 0xffff +#define BIT_RXCMD_PRD_8821C(x) (((x) & BIT_MASK_RXCMD_PRD_8821C) << BIT_SHIFT_RXCMD_PRD_8821C) +#define BIT_GET_RXCMD_PRD_8821C(x) (((x) >> BIT_SHIFT_RXCMD_PRD_8821C) & BIT_MASK_RXCMD_PRD_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_WMAC_RESP_TXINFO_8821C (RESPONSE TXINFO REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_MFB_8821C 25 +#define BIT_MASK_WMAC_RESP_MFB_8821C 0x7f +#define BIT_WMAC_RESP_MFB_8821C(x) (((x) & BIT_MASK_WMAC_RESP_MFB_8821C) << BIT_SHIFT_WMAC_RESP_MFB_8821C) +#define BIT_GET_WMAC_RESP_MFB_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_MFB_8821C) & BIT_MASK_WMAC_RESP_MFB_8821C) + +#define BIT_SHIFT_WMAC_ANTINF_SEL_8821C 23 +#define BIT_MASK_WMAC_ANTINF_SEL_8821C 0x3 +#define BIT_WMAC_ANTINF_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTINF_SEL_8821C) << BIT_SHIFT_WMAC_ANTINF_SEL_8821C) +#define BIT_GET_WMAC_ANTINF_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL_8821C) & BIT_MASK_WMAC_ANTINF_SEL_8821C) + +#define BIT_SHIFT_WMAC_ANTSEL_SEL_8821C 21 +#define BIT_MASK_WMAC_ANTSEL_SEL_8821C 0x3 +#define BIT_WMAC_ANTSEL_SEL_8821C(x) (((x) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) << BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) +#define BIT_GET_WMAC_ANTSEL_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL_8821C) & BIT_MASK_WMAC_ANTSEL_SEL_8821C) + +#define BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C 18 +#define BIT_MASK_R_WMAC_RESP_TXPOWER_8821C 0x7 +#define BIT_R_WMAC_RESP_TXPOWER_8821C(x) (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) << BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) +#define BIT_GET_R_WMAC_RESP_TXPOWER_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER_8821C) & BIT_MASK_R_WMAC_RESP_TXPOWER_8821C) + +#define BIT_SHIFT_WMAC_RESP_TXANT_8821C 0 +#define BIT_MASK_WMAC_RESP_TXANT_8821C 0x3ffff +#define BIT_WMAC_RESP_TXANT_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXANT_8821C) << BIT_SHIFT_WMAC_RESP_TXANT_8821C) +#define BIT_GET_WMAC_RESP_TXANT_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXANT_8821C) & BIT_MASK_WMAC_RESP_TXANT_8821C) + +/* 2 REG_BBPSF_CTRL_8821C */ +#define BIT_CTL_IDLE_CLR_CSI_RPT_8821C BIT(31) +#define BIT_WMAC_USE_NDPARATE_8821C BIT(30) + +#define BIT_SHIFT_WMAC_CSI_RATE_8821C 24 +#define BIT_MASK_WMAC_CSI_RATE_8821C 0x3f +#define BIT_WMAC_CSI_RATE_8821C(x) (((x) & BIT_MASK_WMAC_CSI_RATE_8821C) << BIT_SHIFT_WMAC_CSI_RATE_8821C) +#define BIT_GET_WMAC_CSI_RATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_CSI_RATE_8821C) & BIT_MASK_WMAC_CSI_RATE_8821C) + +#define BIT_SHIFT_WMAC_RESP_TXRATE_8821C 16 +#define BIT_MASK_WMAC_RESP_TXRATE_8821C 0xff +#define BIT_WMAC_RESP_TXRATE_8821C(x) (((x) & BIT_MASK_WMAC_RESP_TXRATE_8821C) << BIT_SHIFT_WMAC_RESP_TXRATE_8821C) +#define BIT_GET_WMAC_RESP_TXRATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE_8821C) & BIT_MASK_WMAC_RESP_TXRATE_8821C) + +#define BIT_CSI_FORCE_RATE_EN_8821C BIT(15) + +#define BIT_SHIFT_CSI_RSC_8821C 13 +#define BIT_MASK_CSI_RSC_8821C 0x3 +#define BIT_CSI_RSC_8821C(x) (((x) & BIT_MASK_CSI_RSC_8821C) << BIT_SHIFT_CSI_RSC_8821C) +#define BIT_GET_CSI_RSC_8821C(x) (((x) >> BIT_SHIFT_CSI_RSC_8821C) & BIT_MASK_CSI_RSC_8821C) + +#define BIT_CSI_GID_SEL_8821C BIT(12) +#define BIT_RDCSIMD_FLAG_TRIG_SEL_8821C BIT(11) +#define BIT_NDPVLD_POS_RST_FFPTR_DIS_8821C BIT(10) +#define BIT_NDPVLD_PROTECT_RDRDY_DIS_8821C BIT(9) +#define BIT_RDCSI_EMPTY_APPZERO_8821C BIT(8) +#define BIT_BBPSF_MPDUCHKEN_8821C BIT(5) +#define BIT_BBPSF_MHCHKEN_8821C BIT(4) +#define BIT_BBPSF_ERRCHKEN_8821C BIT(3) + +#define BIT_SHIFT_BBPSF_ERRTHR_8821C 0 +#define BIT_MASK_BBPSF_ERRTHR_8821C 0x7 +#define BIT_BBPSF_ERRTHR_8821C(x) (((x) & BIT_MASK_BBPSF_ERRTHR_8821C) << BIT_SHIFT_BBPSF_ERRTHR_8821C) +#define BIT_GET_BBPSF_ERRTHR_8821C(x) (((x) >> BIT_SHIFT_BBPSF_ERRTHR_8821C) & BIT_MASK_BBPSF_ERRTHR_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_P2P_RX_BCN_NOA_8821C (P2P RX BEACON NOA REGISTER) */ +#define BIT_NOA_PARSER_EN_8821C BIT(15) +#define BIT_BSSID_SEL_8821C BIT(14) + +#define BIT_SHIFT_P2P_OUI_TYPE_8821C 0 +#define BIT_MASK_P2P_OUI_TYPE_8821C 0xff +#define BIT_P2P_OUI_TYPE_8821C(x) (((x) & BIT_MASK_P2P_OUI_TYPE_8821C) << BIT_SHIFT_P2P_OUI_TYPE_8821C) +#define BIT_GET_P2P_OUI_TYPE_8821C(x) (((x) >> BIT_SHIFT_P2P_OUI_TYPE_8821C) & BIT_MASK_P2P_OUI_TYPE_8821C) + +/* 2 REG_ASSOCIATED_BFMER0_INFO_8821C (ASSOCIATED BEAMFORMER0 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C (48 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_TXCSI_AID0_8821C 0x1ff +#define BIT_R_WMAC_TXCSI_AID0_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) +#define BIT_GET_R_WMAC_TXCSI_AID0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0_8821C) & BIT_MASK_R_WMAC_TXCSI_AID0_8821C) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0_8821C) + +/* 2 REG_ASSOCIATED_BFMER1_INFO_8821C (ASSOCIATED BEAMFORMER1 INFO REGISTER) */ + +#define BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C (48 & CPU_OPT_WIDTH) +#define BIT_MASK_R_WMAC_TXCSI_AID1_8821C 0x1ff +#define BIT_R_WMAC_TXCSI_AID1_8821C(x) (((x) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) << BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) +#define BIT_GET_R_WMAC_TXCSI_AID1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1_8821C) & BIT_MASK_R_WMAC_TXCSI_AID1_8821C) + +#define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C 0 +#define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C 0xffffffffffffL +#define BIT_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) +#define BIT_GET_R_WMAC_SOUNDING_RXADD_R1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1_8821C) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_TX_CSI_RPT_PARAM_BW20_8821C (TX CSI REPORT PARAMETER REGISTER) */ + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C 16 +#define BIT_MASK_R_WMAC_BFINFO_20M_1_8821C 0xfff +#define BIT_R_WMAC_BFINFO_20M_1_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) +#define BIT_GET_R_WMAC_BFINFO_20M_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_1_8821C) + +#define BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C 0 +#define BIT_MASK_R_WMAC_BFINFO_20M_0_8821C 0xfff +#define BIT_R_WMAC_BFINFO_20M_0_8821C(x) (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) << BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) +#define BIT_GET_R_WMAC_BFINFO_20M_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0_8821C) & BIT_MASK_R_WMAC_BFINFO_20M_0_8821C) + +/* 2 REG_TX_CSI_RPT_PARAM_BW40_8821C (TX CSI REPORT PARAMETER_BW40 REGISTER) */ + +#define BIT_SHIFT_WMAC_RESP_ANTCD_8821C 0 +#define BIT_MASK_WMAC_RESP_ANTCD_8821C 0xf +#define BIT_WMAC_RESP_ANTCD_8821C(x) (((x) & BIT_MASK_WMAC_RESP_ANTCD_8821C) << BIT_SHIFT_WMAC_RESP_ANTCD_8821C) +#define BIT_GET_WMAC_RESP_ANTCD_8821C(x) (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD_8821C) & BIT_MASK_WMAC_RESP_ANTCD_8821C) + +/* 2 REG_TX_CSI_RPT_PARAM_BW80_8821C (TX CSI REPORT PARAMETER_BW80 REGISTER) */ + +/* 2 REG_BCN_PSR_RPT2_8821C (BEACON PARSER REPORT REGISTER2) */ + +#define BIT_SHIFT_DTIM_CNT2_8821C 24 +#define BIT_MASK_DTIM_CNT2_8821C 0xff +#define BIT_DTIM_CNT2_8821C(x) (((x) & BIT_MASK_DTIM_CNT2_8821C) << BIT_SHIFT_DTIM_CNT2_8821C) +#define BIT_GET_DTIM_CNT2_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT2_8821C) & BIT_MASK_DTIM_CNT2_8821C) + +#define BIT_SHIFT_DTIM_PERIOD2_8821C 16 +#define BIT_MASK_DTIM_PERIOD2_8821C 0xff +#define BIT_DTIM_PERIOD2_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD2_8821C) << BIT_SHIFT_DTIM_PERIOD2_8821C) +#define BIT_GET_DTIM_PERIOD2_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD2_8821C) & BIT_MASK_DTIM_PERIOD2_8821C) + +#define BIT_DTIM2_8821C BIT(15) +#define BIT_TIM2_8821C BIT(14) + +#define BIT_SHIFT_PS_AID_2_8821C 0 +#define BIT_MASK_PS_AID_2_8821C 0x7ff +#define BIT_PS_AID_2_8821C(x) (((x) & BIT_MASK_PS_AID_2_8821C) << BIT_SHIFT_PS_AID_2_8821C) +#define BIT_GET_PS_AID_2_8821C(x) (((x) >> BIT_SHIFT_PS_AID_2_8821C) & BIT_MASK_PS_AID_2_8821C) + +/* 2 REG_BCN_PSR_RPT3_8821C (BEACON PARSER REPORT REGISTER3) */ + +#define BIT_SHIFT_DTIM_CNT3_8821C 24 +#define BIT_MASK_DTIM_CNT3_8821C 0xff +#define BIT_DTIM_CNT3_8821C(x) (((x) & BIT_MASK_DTIM_CNT3_8821C) << BIT_SHIFT_DTIM_CNT3_8821C) +#define BIT_GET_DTIM_CNT3_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT3_8821C) & BIT_MASK_DTIM_CNT3_8821C) + +#define BIT_SHIFT_DTIM_PERIOD3_8821C 16 +#define BIT_MASK_DTIM_PERIOD3_8821C 0xff +#define BIT_DTIM_PERIOD3_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD3_8821C) << BIT_SHIFT_DTIM_PERIOD3_8821C) +#define BIT_GET_DTIM_PERIOD3_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD3_8821C) & BIT_MASK_DTIM_PERIOD3_8821C) + +#define BIT_DTIM3_8821C BIT(15) +#define BIT_TIM3_8821C BIT(14) + +#define BIT_SHIFT_PS_AID_3_8821C 0 +#define BIT_MASK_PS_AID_3_8821C 0x7ff +#define BIT_PS_AID_3_8821C(x) (((x) & BIT_MASK_PS_AID_3_8821C) << BIT_SHIFT_PS_AID_3_8821C) +#define BIT_GET_PS_AID_3_8821C(x) (((x) >> BIT_SHIFT_PS_AID_3_8821C) & BIT_MASK_PS_AID_3_8821C) + +/* 2 REG_BCN_PSR_RPT4_8821C (BEACON PARSER REPORT REGISTER4) */ + +#define BIT_SHIFT_DTIM_CNT4_8821C 24 +#define BIT_MASK_DTIM_CNT4_8821C 0xff +#define BIT_DTIM_CNT4_8821C(x) (((x) & BIT_MASK_DTIM_CNT4_8821C) << BIT_SHIFT_DTIM_CNT4_8821C) +#define BIT_GET_DTIM_CNT4_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT4_8821C) & BIT_MASK_DTIM_CNT4_8821C) + +#define BIT_SHIFT_DTIM_PERIOD4_8821C 16 +#define BIT_MASK_DTIM_PERIOD4_8821C 0xff +#define BIT_DTIM_PERIOD4_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD4_8821C) << BIT_SHIFT_DTIM_PERIOD4_8821C) +#define BIT_GET_DTIM_PERIOD4_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD4_8821C) & BIT_MASK_DTIM_PERIOD4_8821C) + +#define BIT_DTIM4_8821C BIT(15) +#define BIT_TIM4_8821C BIT(14) + +#define BIT_SHIFT_PS_AID_4_8821C 0 +#define BIT_MASK_PS_AID_4_8821C 0x7ff +#define BIT_PS_AID_4_8821C(x) (((x) & BIT_MASK_PS_AID_4_8821C) << BIT_SHIFT_PS_AID_4_8821C) +#define BIT_GET_PS_AID_4_8821C(x) (((x) >> BIT_SHIFT_PS_AID_4_8821C) & BIT_MASK_PS_AID_4_8821C) + +/* 2 REG_A1_ADDR_MASK_8821C (A1 ADDR MASK REGISTER) */ + +#define BIT_SHIFT_A1_ADDR_MASK_8821C 0 +#define BIT_MASK_A1_ADDR_MASK_8821C 0xffffffffL +#define BIT_A1_ADDR_MASK_8821C(x) (((x) & BIT_MASK_A1_ADDR_MASK_8821C) << BIT_SHIFT_A1_ADDR_MASK_8821C) +#define BIT_GET_A1_ADDR_MASK_8821C(x) (((x) >> BIT_SHIFT_A1_ADDR_MASK_8821C) & BIT_MASK_A1_ADDR_MASK_8821C) + +/* 2 REG_MACID2_8821C (MAC ID2 REGISTER) */ + +#define BIT_SHIFT_MACID2_8821C 0 +#define BIT_MASK_MACID2_8821C 0xffffffffffffL +#define BIT_MACID2_8821C(x) (((x) & BIT_MASK_MACID2_8821C) << BIT_SHIFT_MACID2_8821C) +#define BIT_GET_MACID2_8821C(x) (((x) >> BIT_SHIFT_MACID2_8821C) & BIT_MASK_MACID2_8821C) + +/* 2 REG_BSSID2_8821C (BSSID2 REGISTER) */ + +#define BIT_SHIFT_BSSID2_8821C 0 +#define BIT_MASK_BSSID2_8821C 0xffffffffffffL +#define BIT_BSSID2_8821C(x) (((x) & BIT_MASK_BSSID2_8821C) << BIT_SHIFT_BSSID2_8821C) +#define BIT_GET_BSSID2_8821C(x) (((x) >> BIT_SHIFT_BSSID2_8821C) & BIT_MASK_BSSID2_8821C) + +/* 2 REG_MACID3_8821C (MAC ID3 REGISTER) */ + +#define BIT_SHIFT_MACID3_8821C 0 +#define BIT_MASK_MACID3_8821C 0xffffffffffffL +#define BIT_MACID3_8821C(x) (((x) & BIT_MASK_MACID3_8821C) << BIT_SHIFT_MACID3_8821C) +#define BIT_GET_MACID3_8821C(x) (((x) >> BIT_SHIFT_MACID3_8821C) & BIT_MASK_MACID3_8821C) + +/* 2 REG_BSSID3_8821C (BSSID3 REGISTER) */ + +#define BIT_SHIFT_BSSID3_8821C 0 +#define BIT_MASK_BSSID3_8821C 0xffffffffffffL +#define BIT_BSSID3_8821C(x) (((x) & BIT_MASK_BSSID3_8821C) << BIT_SHIFT_BSSID3_8821C) +#define BIT_GET_BSSID3_8821C(x) (((x) >> BIT_SHIFT_BSSID3_8821C) & BIT_MASK_BSSID3_8821C) + +/* 2 REG_MACID4_8821C (MAC ID4 REGISTER) */ + +#define BIT_SHIFT_MACID4_8821C 0 +#define BIT_MASK_MACID4_8821C 0xffffffffffffL +#define BIT_MACID4_8821C(x) (((x) & BIT_MASK_MACID4_8821C) << BIT_SHIFT_MACID4_8821C) +#define BIT_GET_MACID4_8821C(x) (((x) >> BIT_SHIFT_MACID4_8821C) & BIT_MASK_MACID4_8821C) + +/* 2 REG_BSSID4_8821C (BSSID4 REGISTER) */ + +#define BIT_SHIFT_BSSID4_8821C 0 +#define BIT_MASK_BSSID4_8821C 0xffffffffffffL +#define BIT_BSSID4_8821C(x) (((x) & BIT_MASK_BSSID4_8821C) << BIT_SHIFT_BSSID4_8821C) +#define BIT_GET_BSSID4_8821C(x) (((x) >> BIT_SHIFT_BSSID4_8821C) & BIT_MASK_BSSID4_8821C) + +/* 2 REG_NOA_REPORT_8821C */ + +/* 2 REG_PWRBIT_SETTING_8821C */ +#define BIT_CLI3_PWRBIT_OW_EN_8821C BIT(7) +#define BIT_CLI3_PWR_ST_8821C BIT(6) +#define BIT_CLI2_PWRBIT_OW_EN_8821C BIT(5) +#define BIT_CLI2_PWR_ST_8821C BIT(4) +#define BIT_CLI1_PWRBIT_OW_EN_8821C BIT(3) +#define BIT_CLI1_PWR_ST_8821C BIT(2) +#define BIT_CLI0_PWRBIT_OW_EN_8821C BIT(1) +#define BIT_CLI0_PWR_ST_8821C BIT(0) + +/* 2 REG_WMAC_MU_BF_OPTION_8821C */ +#define BIT_WMAC_RESP_NONSTA1_DIS_8821C BIT(7) +#define BIT_WMAC_TXMU_ACKPOLICY_EN_8821C BIT(6) + +#define BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C 4 +#define BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C 0x3 +#define BIT_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) +#define BIT_GET_WMAC_TXMU_ACKPOLICY_8821C(x) (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY_8821C) & BIT_MASK_WMAC_TXMU_ACKPOLICY_8821C) + +#define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C 1 +#define BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C 0x7 +#define BIT_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) +#define BIT_GET_WMAC_MU_BFEE_PORT_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL_8821C) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL_8821C) + +#define BIT_WMAC_MU_BFEE_DIS_8821C BIT(0) + +/* 2 REG_WMAC_PAUSE_BB_CLR_TH_8821C */ + +#define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C 0 +#define BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C 0xff +#define BIT_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) +#define BIT_GET_WMAC_PAUSE_BB_CLR_TH_8821C(x) (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH_8821C) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH_8821C) + +/* 2 REG_WMAC_MU_ARB_8821C */ +#define BIT_WMAC_ARB_HW_ADAPT_EN_8821C BIT(7) +#define BIT_WMAC_ARB_SW_EN_8821C BIT(6) + +#define BIT_SHIFT_WMAC_ARB_SW_STATE_8821C 0 +#define BIT_MASK_WMAC_ARB_SW_STATE_8821C 0x3f +#define BIT_WMAC_ARB_SW_STATE_8821C(x) (((x) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) << BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) +#define BIT_GET_WMAC_ARB_SW_STATE_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE_8821C) & BIT_MASK_WMAC_ARB_SW_STATE_8821C) + +/* 2 REG_WMAC_MU_OPTION_8821C */ + +#define BIT_SHIFT_WMAC_MU_DBGSEL_8821C 5 +#define BIT_MASK_WMAC_MU_DBGSEL_8821C 0x3 +#define BIT_WMAC_MU_DBGSEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_DBGSEL_8821C) << BIT_SHIFT_WMAC_MU_DBGSEL_8821C) +#define BIT_GET_WMAC_MU_DBGSEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL_8821C) & BIT_MASK_WMAC_MU_DBGSEL_8821C) + +#define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C 0 +#define BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C 0x1f +#define BIT_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) +#define BIT_GET_WMAC_MU_CPRD_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT_8821C) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT_8821C) + +/* 2 REG_WMAC_MU_BF_CTL_8821C */ +#define BIT_WMAC_INVLD_BFPRT_CHK_8821C BIT(15) +#define BIT_WMAC_RETXBFRPTSEQ_UPD_8821C BIT(14) + +#define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C 12 +#define BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C 0x3 +#define BIT_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) +#define BIT_GET_WMAC_MU_BFRPTSEG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL_8821C) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL_8821C) + +#define BIT_SHIFT_WMAC_MU_BF_MYAID_8821C 0 +#define BIT_MASK_WMAC_MU_BF_MYAID_8821C 0xfff +#define BIT_WMAC_MU_BF_MYAID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) << BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) +#define BIT_GET_WMAC_MU_BF_MYAID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID_8821C) & BIT_MASK_WMAC_MU_BF_MYAID_8821C) + +/* 2 REG_WMAC_MU_BIT_BFRPT_PARA_8821C */ + +#define BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C 12 +#define BIT_MASK_BFRPT_PARA_USERID_SEL_8821C 0x7 +#define BIT_BFRPT_PARA_USERID_SEL_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) << BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) +#define BIT_GET_BFRPT_PARA_USERID_SEL_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_USERID_SEL_8821C) & BIT_MASK_BFRPT_PARA_USERID_SEL_8821C) + +#define BIT_SHIFT_BFRPT_PARA_8821C 0 +#define BIT_MASK_BFRPT_PARA_8821C 0xfff +#define BIT_BFRPT_PARA_8821C(x) (((x) & BIT_MASK_BFRPT_PARA_8821C) << BIT_SHIFT_BFRPT_PARA_8821C) +#define BIT_GET_BFRPT_PARA_8821C(x) (((x) >> BIT_SHIFT_BFRPT_PARA_8821C) & BIT_MASK_BFRPT_PARA_8821C) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C */ +#define BIT_STATUS_BFEE2_8821C BIT(10) +#define BIT_WMAC_MU_BFEE2_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE2_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE2_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE2_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID_8821C) & BIT_MASK_WMAC_MU_BFEE2_AID_8821C) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C */ +#define BIT_STATUS_BFEE3_8821C BIT(10) +#define BIT_WMAC_MU_BFEE3_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE3_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE3_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE3_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID_8821C) & BIT_MASK_WMAC_MU_BFEE3_AID_8821C) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C */ +#define BIT_STATUS_BFEE4_8821C BIT(10) +#define BIT_WMAC_MU_BFEE4_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE4_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE4_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE4_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID_8821C) & BIT_MASK_WMAC_MU_BFEE4_AID_8821C) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C */ +#define BIT_BIT_STATUS_BFEE5_8821C BIT(10) +#define BIT_WMAC_MU_BFEE5_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE5_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE5_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE5_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID_8821C) & BIT_MASK_WMAC_MU_BFEE5_AID_8821C) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C */ +#define BIT_STATUS_BFEE6_8821C BIT(10) +#define BIT_WMAC_MU_BFEE6_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE6_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE6_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE6_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID_8821C) & BIT_MASK_WMAC_MU_BFEE6_AID_8821C) + +/* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C */ +#define BIT_BIT_STATUS_BFEE4_8821C BIT(10) +#define BIT_WMAC_MU_BFEE7_EN_8821C BIT(9) + +#define BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C 0 +#define BIT_MASK_WMAC_MU_BFEE7_AID_8821C 0x1ff +#define BIT_WMAC_MU_BFEE7_AID_8821C(x) (((x) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) << BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) +#define BIT_GET_WMAC_MU_BFEE7_AID_8821C(x) (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID_8821C) & BIT_MASK_WMAC_MU_BFEE7_AID_8821C) + +/* 2 REG_WMAC_BB_STOP_RX_COUNTER_8821C */ +#define BIT_RST_ALL_COUNTER_8821C BIT(31) + +#define BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C 16 +#define BIT_MASK_ABORT_RX_VBON_COUNTER_8821C 0xff +#define BIT_ABORT_RX_VBON_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) +#define BIT_GET_ABORT_RX_VBON_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER_8821C) & BIT_MASK_ABORT_RX_VBON_COUNTER_8821C) + +#define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C 8 +#define BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C 0xff +#define BIT_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) +#define BIT_GET_ABORT_RX_RDRDY_COUNTER_8821C(x) (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER_8821C) & BIT_MASK_ABORT_RX_RDRDY_COUNTER_8821C) + +#define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C 0 +#define BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C 0xff +#define BIT_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) +#define BIT_GET_VBON_EARLY_FALLING_COUNTER_8821C(x) (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER_8821C) & BIT_MASK_VBON_EARLY_FALLING_COUNTER_8821C) + +/* 2 REG_WMAC_PLCP_MONITOR_8821C */ +#define BIT_WMAC_PLCP_TRX_SEL_8821C BIT(31) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C 28 +#define BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C 0x7 +#define BIT_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) +#define BIT_GET_WMAC_PLCP_RDSIG_SEL_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_SEL_8821C) + +#define BIT_SHIFT_WMAC_RATE_IDX_8821C 24 +#define BIT_MASK_WMAC_RATE_IDX_8821C 0xf +#define BIT_WMAC_RATE_IDX_8821C(x) (((x) & BIT_MASK_WMAC_RATE_IDX_8821C) << BIT_SHIFT_WMAC_RATE_IDX_8821C) +#define BIT_GET_WMAC_RATE_IDX_8821C(x) (((x) >> BIT_SHIFT_WMAC_RATE_IDX_8821C) & BIT_MASK_WMAC_RATE_IDX_8821C) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) + +/* 2 REG_WMAC_PLCP_MONITOR_MUTX_8821C */ +#define BIT_WMAC_MUTX_IDX_8821C BIT(24) + +#define BIT_SHIFT_WMAC_PLCP_RDSIG_8821C 0 +#define BIT_MASK_WMAC_PLCP_RDSIG_8821C 0xffffff +#define BIT_WMAC_PLCP_RDSIG_8821C(x) (((x) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) << BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) +#define BIT_GET_WMAC_PLCP_RDSIG_8821C(x) (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_8821C) & BIT_MASK_WMAC_PLCP_RDSIG_8821C) + +/* 2 REG_TRANSMIT_ADDRSS_0_8821C (TA0 REGISTER) */ + +#define BIT_SHIFT_TA0_8821C 0 +#define BIT_MASK_TA0_8821C 0xffffffffffffL +#define BIT_TA0_8821C(x) (((x) & BIT_MASK_TA0_8821C) << BIT_SHIFT_TA0_8821C) +#define BIT_GET_TA0_8821C(x) (((x) >> BIT_SHIFT_TA0_8821C) & BIT_MASK_TA0_8821C) + +/* 2 REG_TRANSMIT_ADDRSS_1_8821C (TA1 REGISTER) */ + +#define BIT_SHIFT_TA1_8821C 0 +#define BIT_MASK_TA1_8821C 0xffffffffffffL +#define BIT_TA1_8821C(x) (((x) & BIT_MASK_TA1_8821C) << BIT_SHIFT_TA1_8821C) +#define BIT_GET_TA1_8821C(x) (((x) >> BIT_SHIFT_TA1_8821C) & BIT_MASK_TA1_8821C) + +/* 2 REG_TRANSMIT_ADDRSS_2_8821C (TA2 REGISTER) */ + +#define BIT_SHIFT_TA2_8821C 0 +#define BIT_MASK_TA2_8821C 0xffffffffffffL +#define BIT_TA2_8821C(x) (((x) & BIT_MASK_TA2_8821C) << BIT_SHIFT_TA2_8821C) +#define BIT_GET_TA2_8821C(x) (((x) >> BIT_SHIFT_TA2_8821C) & BIT_MASK_TA2_8821C) + +/* 2 REG_TRANSMIT_ADDRSS_3_8821C (TA3 REGISTER) */ + +#define BIT_SHIFT_TA3_8821C 0 +#define BIT_MASK_TA3_8821C 0xffffffffffffL +#define BIT_TA3_8821C(x) (((x) & BIT_MASK_TA3_8821C) << BIT_SHIFT_TA3_8821C) +#define BIT_GET_TA3_8821C(x) (((x) >> BIT_SHIFT_TA3_8821C) & BIT_MASK_TA3_8821C) + +/* 2 REG_TRANSMIT_ADDRSS_4_8821C (TA4 REGISTER) */ + +#define BIT_SHIFT_TA4_8821C 0 +#define BIT_MASK_TA4_8821C 0xffffffffffffL +#define BIT_TA4_8821C(x) (((x) & BIT_MASK_TA4_8821C) << BIT_SHIFT_TA4_8821C) +#define BIT_GET_TA4_8821C(x) (((x) >> BIT_SHIFT_TA4_8821C) & BIT_MASK_TA4_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_MACID1_8821C */ + +#define BIT_SHIFT_MACID1_0_8821C 0 +#define BIT_MASK_MACID1_0_8821C 0xffffffffL +#define BIT_MACID1_0_8821C(x) (((x) & BIT_MASK_MACID1_0_8821C) << BIT_SHIFT_MACID1_0_8821C) +#define BIT_GET_MACID1_0_8821C(x) (((x) >> BIT_SHIFT_MACID1_0_8821C) & BIT_MASK_MACID1_0_8821C) + +/* 2 REG_MACID1_1_8821C */ + +#define BIT_SHIFT_MACID1_1_8821C 0 +#define BIT_MASK_MACID1_1_8821C 0xffff +#define BIT_MACID1_1_8821C(x) (((x) & BIT_MASK_MACID1_1_8821C) << BIT_SHIFT_MACID1_1_8821C) +#define BIT_GET_MACID1_1_8821C(x) (((x) >> BIT_SHIFT_MACID1_1_8821C) & BIT_MASK_MACID1_1_8821C) + +/* 2 REG_BSSID1_8821C */ + +#define BIT_SHIFT_BSSID1_0_8821C 0 +#define BIT_MASK_BSSID1_0_8821C 0xffffffffL +#define BIT_BSSID1_0_8821C(x) (((x) & BIT_MASK_BSSID1_0_8821C) << BIT_SHIFT_BSSID1_0_8821C) +#define BIT_GET_BSSID1_0_8821C(x) (((x) >> BIT_SHIFT_BSSID1_0_8821C) & BIT_MASK_BSSID1_0_8821C) + +/* 2 REG_BSSID1_1_8821C */ + +#define BIT_SHIFT_BSSID1_1_8821C 0 +#define BIT_MASK_BSSID1_1_8821C 0xffff +#define BIT_BSSID1_1_8821C(x) (((x) & BIT_MASK_BSSID1_1_8821C) << BIT_SHIFT_BSSID1_1_8821C) +#define BIT_GET_BSSID1_1_8821C(x) (((x) >> BIT_SHIFT_BSSID1_1_8821C) & BIT_MASK_BSSID1_1_8821C) + +/* 2 REG_BCN_PSR_RPT1_8821C */ + +#define BIT_SHIFT_DTIM_CNT1_8821C 24 +#define BIT_MASK_DTIM_CNT1_8821C 0xff +#define BIT_DTIM_CNT1_8821C(x) (((x) & BIT_MASK_DTIM_CNT1_8821C) << BIT_SHIFT_DTIM_CNT1_8821C) +#define BIT_GET_DTIM_CNT1_8821C(x) (((x) >> BIT_SHIFT_DTIM_CNT1_8821C) & BIT_MASK_DTIM_CNT1_8821C) + +#define BIT_SHIFT_DTIM_PERIOD1_8821C 16 +#define BIT_MASK_DTIM_PERIOD1_8821C 0xff +#define BIT_DTIM_PERIOD1_8821C(x) (((x) & BIT_MASK_DTIM_PERIOD1_8821C) << BIT_SHIFT_DTIM_PERIOD1_8821C) +#define BIT_GET_DTIM_PERIOD1_8821C(x) (((x) >> BIT_SHIFT_DTIM_PERIOD1_8821C) & BIT_MASK_DTIM_PERIOD1_8821C) + +#define BIT_DTIM1_8821C BIT(15) +#define BIT_TIM1_8821C BIT(14) + +#define BIT_SHIFT_PS_AID_1_8821C 0 +#define BIT_MASK_PS_AID_1_8821C 0x7ff +#define BIT_PS_AID_1_8821C(x) (((x) & BIT_MASK_PS_AID_1_8821C) << BIT_SHIFT_PS_AID_1_8821C) +#define BIT_GET_PS_AID_1_8821C(x) (((x) >> BIT_SHIFT_PS_AID_1_8821C) & BIT_MASK_PS_AID_1_8821C) + +/* 2 REG_ASSOCIATED_BFMEE_SEL_8821C */ +#define BIT_TXUSER_ID1_8821C BIT(25) + +#define BIT_SHIFT_AID1_8821C 16 +#define BIT_MASK_AID1_8821C 0x1ff +#define BIT_AID1_8821C(x) (((x) & BIT_MASK_AID1_8821C) << BIT_SHIFT_AID1_8821C) +#define BIT_GET_AID1_8821C(x) (((x) >> BIT_SHIFT_AID1_8821C) & BIT_MASK_AID1_8821C) + +#define BIT_TXUSER_ID0_8821C BIT(9) + +#define BIT_SHIFT_AID0_8821C 0 +#define BIT_MASK_AID0_8821C 0x1ff +#define BIT_AID0_8821C(x) (((x) & BIT_MASK_AID0_8821C) << BIT_SHIFT_AID0_8821C) +#define BIT_GET_AID0_8821C(x) (((x) >> BIT_SHIFT_AID0_8821C) & BIT_MASK_AID0_8821C) + +/* 2 REG_SND_PTCL_CTRL_8821C */ + +#define BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C 24 +#define BIT_MASK_NDP_RX_STANDBY_TIMER_8821C 0xff +#define BIT_NDP_RX_STANDBY_TIMER_8821C(x) (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) << BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) +#define BIT_GET_NDP_RX_STANDBY_TIMER_8821C(x) (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER_8821C) & BIT_MASK_NDP_RX_STANDBY_TIMER_8821C) + +#define BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C 16 +#define BIT_MASK_CSI_RPT_OFFSET_HT_8821C 0xff +#define BIT_CSI_RPT_OFFSET_HT_8821C(x) (((x) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) << BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) +#define BIT_GET_CSI_RPT_OFFSET_HT_8821C(x) (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT_8821C) & BIT_MASK_CSI_RPT_OFFSET_HT_8821C) + +#define BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C 8 +#define BIT_MASK_R_WMAC_VHT_CATEGORY_8821C 0xff +#define BIT_R_WMAC_VHT_CATEGORY_8821C(x) (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) << BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) +#define BIT_GET_R_WMAC_VHT_CATEGORY_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY_8821C) & BIT_MASK_R_WMAC_VHT_CATEGORY_8821C) + +#define BIT_R_WMAC_USE_NSTS_8821C BIT(7) +#define BIT_R_DISABLE_CHECK_VHTSIGB_CRC_8821C BIT(6) +#define BIT_R_DISABLE_CHECK_VHTSIGA_CRC_8821C BIT(5) +#define BIT_R_WMAC_BFPARAM_SEL_8821C BIT(4) +#define BIT_R_WMAC_CSISEQ_SEL_8821C BIT(3) +#define BIT_R_WMAC_CSI_WITHHTC_EN_8821C BIT(2) +#define BIT_R_WMAC_HT_NDPA_EN_8821C BIT(1) +#define BIT_R_WMAC_VHT_NDPA_EN_8821C BIT(0) + +/* 2 REG_RX_CSI_RPT_INFO_8821C */ + +/* 2 REG_NS_ARP_CTRL_8821C */ +#define BIT_R_WMAC_NSARP_RSPEN_8821C BIT(15) +#define BIT_R_WMAC_NSARP_RARP_8821C BIT(9) +#define BIT_R_WMAC_NSARP_RIPV6_8821C BIT(8) + +#define BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C 6 +#define BIT_MASK_R_WMAC_NSARP_MODEN_8821C 0x3 +#define BIT_R_WMAC_NSARP_MODEN_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) << BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) +#define BIT_GET_R_WMAC_NSARP_MODEN_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN_8821C) & BIT_MASK_R_WMAC_NSARP_MODEN_8821C) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C 4 +#define BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C 0x3 +#define BIT_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) +#define BIT_GET_R_WMAC_NSARP_RSPFTP_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP_8821C) & BIT_MASK_R_WMAC_NSARP_RSPFTP_8821C) + +#define BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C 0 +#define BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C 0xf +#define BIT_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) +#define BIT_GET_R_WMAC_NSARP_RSPSEC_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC_8821C) & BIT_MASK_R_WMAC_NSARP_RSPSEC_8821C) + +/* 2 REG_NS_ARP_INFO_8821C */ +#define BIT_REQ_IS_MCNS_8821C BIT(23) +#define BIT_REQ_IS_UCNS_8821C BIT(22) +#define BIT_REQ_IS_USNS_8821C BIT(21) +#define BIT_REQ_IS_ARP_8821C BIT(20) +#define BIT_EXPRSP_MH_WITHQC_8821C BIT(19) + +#define BIT_SHIFT_EXPRSP_SECTYPE_8821C 16 +#define BIT_MASK_EXPRSP_SECTYPE_8821C 0x7 +#define BIT_EXPRSP_SECTYPE_8821C(x) (((x) & BIT_MASK_EXPRSP_SECTYPE_8821C) << BIT_SHIFT_EXPRSP_SECTYPE_8821C) +#define BIT_GET_EXPRSP_SECTYPE_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_SECTYPE_8821C) & BIT_MASK_EXPRSP_SECTYPE_8821C) + +#define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C 8 +#define BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C 0xff +#define BIT_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) +#define BIT_GET_EXPRSP_CHKSM_7_TO_0_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0_8821C) & BIT_MASK_EXPRSP_CHKSM_7_TO_0_8821C) + +#define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C 0 +#define BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C 0xff +#define BIT_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) +#define BIT_GET_EXPRSP_CHKSM_15_TO_8_8821C(x) (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8_8821C) & BIT_MASK_EXPRSP_CHKSM_15_TO_8_8821C) + +/* 2 REG_BEAMFORMING_INFO_NSARP_V1_8821C */ + +#define BIT_SHIFT_WMAC_ARPIP_8821C 0 +#define BIT_MASK_WMAC_ARPIP_8821C 0xffffffffL +#define BIT_WMAC_ARPIP_8821C(x) (((x) & BIT_MASK_WMAC_ARPIP_8821C) << BIT_SHIFT_WMAC_ARPIP_8821C) +#define BIT_GET_WMAC_ARPIP_8821C(x) (((x) >> BIT_SHIFT_WMAC_ARPIP_8821C) & BIT_MASK_WMAC_ARPIP_8821C) + +/* 2 REG_BEAMFORMING_INFO_NSARP_8821C */ + +#define BIT_SHIFT_BEAMFORMING_INFO_8821C 0 +#define BIT_MASK_BEAMFORMING_INFO_8821C 0xffffffffL +#define BIT_BEAMFORMING_INFO_8821C(x) (((x) & BIT_MASK_BEAMFORMING_INFO_8821C) << BIT_SHIFT_BEAMFORMING_INFO_8821C) +#define BIT_GET_BEAMFORMING_INFO_8821C(x) (((x) >> BIT_SHIFT_BEAMFORMING_INFO_8821C) & BIT_MASK_BEAMFORMING_INFO_8821C) + +/* 2 REG_IPV6_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_0_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_0_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_0_8821C) + +/* 2 REG_IPV6_1_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_1_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_1_8821C) + +/* 2 REG_IPV6_2_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_2_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_2_8821C) + +/* 2 REG_IPV6_3_8821C */ + +#define BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C 0 +#define BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C 0xffffffffL +#define BIT_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) +#define BIT_GET_R_WMAC_IPV6_MYIPAD_3_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD_3_8821C) & BIT_MASK_R_WMAC_IPV6_MYIPAD_3_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C */ + +#define BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C 4 +#define BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C 0xf +#define BIT_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) +#define BIT_GET_R_WMAC_CTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_CTX_SUBTYPE_8821C) + +#define BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C 0 +#define BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C 0xf +#define BIT_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) +#define BIT_GET_R_WMAC_RTX_SUBTYPE_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE_8821C) & BIT_MASK_R_WMAC_RTX_SUBTYPE_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_WMAC_SWAES_CFG_8821C */ + +/* 2 REG_BT_COEX_V2_8821C */ +#define BIT_GNT_BT_POLARITY_8821C BIT(12) +#define BIT_GNT_BT_BYPASS_PRIORITY_8821C BIT(8) + +#define BIT_SHIFT_TIMER_8821C 0 +#define BIT_MASK_TIMER_8821C 0xff +#define BIT_TIMER_8821C(x) (((x) & BIT_MASK_TIMER_8821C) << BIT_SHIFT_TIMER_8821C) +#define BIT_GET_TIMER_8821C(x) (((x) >> BIT_SHIFT_TIMER_8821C) & BIT_MASK_TIMER_8821C) + +/* 2 REG_BT_COEX_8821C */ +#define BIT_R_GNT_BT_RFC_SW_8821C BIT(12) +#define BIT_R_GNT_BT_RFC_SW_EN_8821C BIT(11) +#define BIT_R_GNT_BT_BB_SW_8821C BIT(10) +#define BIT_R_GNT_BT_BB_SW_EN_8821C BIT(9) +#define BIT_R_BT_CNT_THREN_8821C BIT(8) + +#define BIT_SHIFT_R_BT_CNT_THR_8821C 0 +#define BIT_MASK_R_BT_CNT_THR_8821C 0xff +#define BIT_R_BT_CNT_THR_8821C(x) (((x) & BIT_MASK_R_BT_CNT_THR_8821C) << BIT_SHIFT_R_BT_CNT_THR_8821C) +#define BIT_GET_R_BT_CNT_THR_8821C(x) (((x) >> BIT_SHIFT_R_BT_CNT_THR_8821C) & BIT_MASK_R_BT_CNT_THR_8821C) + +/* 2 REG_WLAN_ACT_MASK_CTRL_8821C */ + +#define BIT_SHIFT_RXMYRTS_NAV_V1_8821C 8 +#define BIT_MASK_RXMYRTS_NAV_V1_8821C 0xff +#define BIT_RXMYRTS_NAV_V1_8821C(x) (((x) & BIT_MASK_RXMYRTS_NAV_V1_8821C) << BIT_SHIFT_RXMYRTS_NAV_V1_8821C) +#define BIT_GET_RXMYRTS_NAV_V1_8821C(x) (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1_8821C) & BIT_MASK_RXMYRTS_NAV_V1_8821C) + +#define BIT_SHIFT_RTSRST_V1_8821C 0 +#define BIT_MASK_RTSRST_V1_8821C 0xff +#define BIT_RTSRST_V1_8821C(x) (((x) & BIT_MASK_RTSRST_V1_8821C) << BIT_SHIFT_RTSRST_V1_8821C) +#define BIT_GET_RTSRST_V1_8821C(x) (((x) >> BIT_SHIFT_RTSRST_V1_8821C) & BIT_MASK_RTSRST_V1_8821C) + +/* 2 REG_WLAN_ACT_MASK_CTRL_1_8821C */ +#define BIT_WLRX_TER_BY_CTL_1_8821C BIT(11) +#define BIT_WLRX_TER_BY_AD_1_8821C BIT(10) +#define BIT_ANT_DIVERSITY_SEL_1_8821C BIT(9) +#define BIT_ANTSEL_FOR_BT_CTRL_EN_1_8821C BIT(8) +#define BIT_WLACT_LOW_GNTWL_EN_1_8821C BIT(2) +#define BIT_WLACT_HIGH_GNTBT_EN_1_8821C BIT(1) +#define BIT_NAV_UPPER_1_V1_8821C BIT(0) + +/* 2 REG_BT_COEX_ENHANCED_INTR_CTRL_8821C */ + +#define BIT_SHIFT_BT_STAT_DELAY_8821C 12 +#define BIT_MASK_BT_STAT_DELAY_8821C 0xf +#define BIT_BT_STAT_DELAY_8821C(x) (((x) & BIT_MASK_BT_STAT_DELAY_8821C) << BIT_SHIFT_BT_STAT_DELAY_8821C) +#define BIT_GET_BT_STAT_DELAY_8821C(x) (((x) >> BIT_SHIFT_BT_STAT_DELAY_8821C) & BIT_MASK_BT_STAT_DELAY_8821C) + +#define BIT_SHIFT_BT_TRX_INIT_DETECT_8821C 8 +#define BIT_MASK_BT_TRX_INIT_DETECT_8821C 0xf +#define BIT_BT_TRX_INIT_DETECT_8821C(x) (((x) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) << BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) +#define BIT_GET_BT_TRX_INIT_DETECT_8821C(x) (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT_8821C) & BIT_MASK_BT_TRX_INIT_DETECT_8821C) + +#define BIT_SHIFT_BT_PRI_DETECT_TO_8821C 4 +#define BIT_MASK_BT_PRI_DETECT_TO_8821C 0xf +#define BIT_BT_PRI_DETECT_TO_8821C(x) (((x) & BIT_MASK_BT_PRI_DETECT_TO_8821C) << BIT_SHIFT_BT_PRI_DETECT_TO_8821C) +#define BIT_GET_BT_PRI_DETECT_TO_8821C(x) (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO_8821C) & BIT_MASK_BT_PRI_DETECT_TO_8821C) + +#define BIT_R_GRANTALL_WLMASK_8821C BIT(3) +#define BIT_STATIS_BT_EN_8821C BIT(2) +#define BIT_WL_ACT_MASK_ENABLE_8821C BIT(1) +#define BIT_ENHANCED_BT_8821C BIT(0) + +/* 2 REG_BT_ACT_STATISTICS_8821C */ + +#define BIT_SHIFT_STATIS_BT_HI_RX_8821C 16 +#define BIT_MASK_STATIS_BT_HI_RX_8821C 0xffff +#define BIT_STATIS_BT_HI_RX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_RX_8821C) << BIT_SHIFT_STATIS_BT_HI_RX_8821C) +#define BIT_GET_STATIS_BT_HI_RX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_RX_8821C) & BIT_MASK_STATIS_BT_HI_RX_8821C) + +#define BIT_SHIFT_STATIS_BT_HI_TX_8821C 0 +#define BIT_MASK_STATIS_BT_HI_TX_8821C 0xffff +#define BIT_STATIS_BT_HI_TX_8821C(x) (((x) & BIT_MASK_STATIS_BT_HI_TX_8821C) << BIT_SHIFT_STATIS_BT_HI_TX_8821C) +#define BIT_GET_STATIS_BT_HI_TX_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_HI_TX_8821C) & BIT_MASK_STATIS_BT_HI_TX_8821C) + +/* 2 REG_BT_ACT_STATISTICS_1_8821C */ + +#define BIT_SHIFT_STATIS_BT_LO_RX_1_8821C 16 +#define BIT_MASK_STATIS_BT_LO_RX_1_8821C 0xffff +#define BIT_STATIS_BT_LO_RX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) +#define BIT_GET_STATIS_BT_LO_RX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_RX_1_8821C) & BIT_MASK_STATIS_BT_LO_RX_1_8821C) + +#define BIT_SHIFT_STATIS_BT_LO_TX_1_8821C 0 +#define BIT_MASK_STATIS_BT_LO_TX_1_8821C 0xffff +#define BIT_STATIS_BT_LO_TX_1_8821C(x) (((x) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) << BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) +#define BIT_GET_STATIS_BT_LO_TX_1_8821C(x) (((x) >> BIT_SHIFT_STATIS_BT_LO_TX_1_8821C) & BIT_MASK_STATIS_BT_LO_TX_1_8821C) + +/* 2 REG_BT_STATISTICS_CONTROL_REGISTER_8821C */ + +#define BIT_SHIFT_R_BT_CMD_RPT_8821C 16 +#define BIT_MASK_R_BT_CMD_RPT_8821C 0xffff +#define BIT_R_BT_CMD_RPT_8821C(x) (((x) & BIT_MASK_R_BT_CMD_RPT_8821C) << BIT_SHIFT_R_BT_CMD_RPT_8821C) +#define BIT_GET_R_BT_CMD_RPT_8821C(x) (((x) >> BIT_SHIFT_R_BT_CMD_RPT_8821C) & BIT_MASK_R_BT_CMD_RPT_8821C) + +#define BIT_SHIFT_R_RPT_FROM_BT_8821C 8 +#define BIT_MASK_R_RPT_FROM_BT_8821C 0xff +#define BIT_R_RPT_FROM_BT_8821C(x) (((x) & BIT_MASK_R_RPT_FROM_BT_8821C) << BIT_SHIFT_R_RPT_FROM_BT_8821C) +#define BIT_GET_R_RPT_FROM_BT_8821C(x) (((x) >> BIT_SHIFT_R_RPT_FROM_BT_8821C) & BIT_MASK_R_RPT_FROM_BT_8821C) + +#define BIT_SHIFT_BT_HID_ISR_SET_8821C 6 +#define BIT_MASK_BT_HID_ISR_SET_8821C 0x3 +#define BIT_BT_HID_ISR_SET_8821C(x) (((x) & BIT_MASK_BT_HID_ISR_SET_8821C) << BIT_SHIFT_BT_HID_ISR_SET_8821C) +#define BIT_GET_BT_HID_ISR_SET_8821C(x) (((x) >> BIT_SHIFT_BT_HID_ISR_SET_8821C) & BIT_MASK_BT_HID_ISR_SET_8821C) + +#define BIT_TDMA_BT_START_NOTIFY_8821C BIT(5) +#define BIT_ENABLE_TDMA_FW_MODE_8821C BIT(4) +#define BIT_ENABLE_PTA_TDMA_MODE_8821C BIT(3) +#define BIT_ENABLE_COEXIST_TAB_IN_TDMA_8821C BIT(2) +#define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA_8821C BIT(1) +#define BIT_RTK_BT_ENABLE_8821C BIT(0) + +/* 2 REG_BT_STATUS_REPORT_REGISTER_8821C */ + +#define BIT_SHIFT_BT_PROFILE_8821C 24 +#define BIT_MASK_BT_PROFILE_8821C 0xff +#define BIT_BT_PROFILE_8821C(x) (((x) & BIT_MASK_BT_PROFILE_8821C) << BIT_SHIFT_BT_PROFILE_8821C) +#define BIT_GET_BT_PROFILE_8821C(x) (((x) >> BIT_SHIFT_BT_PROFILE_8821C) & BIT_MASK_BT_PROFILE_8821C) + +#define BIT_SHIFT_BT_POWER_8821C 16 +#define BIT_MASK_BT_POWER_8821C 0xff +#define BIT_BT_POWER_8821C(x) (((x) & BIT_MASK_BT_POWER_8821C) << BIT_SHIFT_BT_POWER_8821C) +#define BIT_GET_BT_POWER_8821C(x) (((x) >> BIT_SHIFT_BT_POWER_8821C) & BIT_MASK_BT_POWER_8821C) + +#define BIT_SHIFT_BT_PREDECT_STATUS_8821C 8 +#define BIT_MASK_BT_PREDECT_STATUS_8821C 0xff +#define BIT_BT_PREDECT_STATUS_8821C(x) (((x) & BIT_MASK_BT_PREDECT_STATUS_8821C) << BIT_SHIFT_BT_PREDECT_STATUS_8821C) +#define BIT_GET_BT_PREDECT_STATUS_8821C(x) (((x) >> BIT_SHIFT_BT_PREDECT_STATUS_8821C) & BIT_MASK_BT_PREDECT_STATUS_8821C) + +#define BIT_SHIFT_BT_CMD_INFO_8821C 0 +#define BIT_MASK_BT_CMD_INFO_8821C 0xff +#define BIT_BT_CMD_INFO_8821C(x) (((x) & BIT_MASK_BT_CMD_INFO_8821C) << BIT_SHIFT_BT_CMD_INFO_8821C) +#define BIT_GET_BT_CMD_INFO_8821C(x) (((x) >> BIT_SHIFT_BT_CMD_INFO_8821C) & BIT_MASK_BT_CMD_INFO_8821C) + +/* 2 REG_BT_INTERRUPT_CONTROL_REGISTER_8821C */ +#define BIT_EN_MAC_NULL_PKT_NOTIFY_8821C BIT(31) +#define BIT_EN_WLAN_RPT_AND_BT_QUERY_8821C BIT(30) +#define BIT_EN_BT_STSTUS_RPT_8821C BIT(29) +#define BIT_EN_BT_POWER_8821C BIT(28) +#define BIT_EN_BT_CHANNEL_8821C BIT(27) +#define BIT_EN_BT_SLOT_CHANGE_8821C BIT(26) +#define BIT_EN_BT_PROFILE_OR_HID_8821C BIT(25) +#define BIT_WLAN_RPT_NOTIFY_8821C BIT(24) + +#define BIT_SHIFT_WLAN_RPT_DATA_8821C 16 +#define BIT_MASK_WLAN_RPT_DATA_8821C 0xff +#define BIT_WLAN_RPT_DATA_8821C(x) (((x) & BIT_MASK_WLAN_RPT_DATA_8821C) << BIT_SHIFT_WLAN_RPT_DATA_8821C) +#define BIT_GET_WLAN_RPT_DATA_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_DATA_8821C) & BIT_MASK_WLAN_RPT_DATA_8821C) + +#define BIT_SHIFT_CMD_ID_8821C 8 +#define BIT_MASK_CMD_ID_8821C 0xff +#define BIT_CMD_ID_8821C(x) (((x) & BIT_MASK_CMD_ID_8821C) << BIT_SHIFT_CMD_ID_8821C) +#define BIT_GET_CMD_ID_8821C(x) (((x) >> BIT_SHIFT_CMD_ID_8821C) & BIT_MASK_CMD_ID_8821C) + +#define BIT_SHIFT_BT_DATA_8821C 0 +#define BIT_MASK_BT_DATA_8821C 0xff +#define BIT_BT_DATA_8821C(x) (((x) & BIT_MASK_BT_DATA_8821C) << BIT_SHIFT_BT_DATA_8821C) +#define BIT_GET_BT_DATA_8821C(x) (((x) >> BIT_SHIFT_BT_DATA_8821C) & BIT_MASK_BT_DATA_8821C) + +/* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C */ + +#define BIT_SHIFT_WLAN_RPT_TO_8821C 0 +#define BIT_MASK_WLAN_RPT_TO_8821C 0xff +#define BIT_WLAN_RPT_TO_8821C(x) (((x) & BIT_MASK_WLAN_RPT_TO_8821C) << BIT_SHIFT_WLAN_RPT_TO_8821C) +#define BIT_GET_WLAN_RPT_TO_8821C(x) (((x) >> BIT_SHIFT_WLAN_RPT_TO_8821C) & BIT_MASK_WLAN_RPT_TO_8821C) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C */ + +#define BIT_SHIFT_ISOLATION_CHK_0_8821C 1 +#define BIT_MASK_ISOLATION_CHK_0_8821C 0x7fffff +#define BIT_ISOLATION_CHK_0_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_0_8821C) << BIT_SHIFT_ISOLATION_CHK_0_8821C) +#define BIT_GET_ISOLATION_CHK_0_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_0_8821C) & BIT_MASK_ISOLATION_CHK_0_8821C) + +#define BIT_ISOLATION_EN_8821C BIT(0) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C */ + +#define BIT_SHIFT_ISOLATION_CHK_1_8821C 0 +#define BIT_MASK_ISOLATION_CHK_1_8821C 0xffffffffL +#define BIT_ISOLATION_CHK_1_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_1_8821C) << BIT_SHIFT_ISOLATION_CHK_1_8821C) +#define BIT_GET_ISOLATION_CHK_1_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_1_8821C) & BIT_MASK_ISOLATION_CHK_1_8821C) + +/* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C */ + +#define BIT_SHIFT_ISOLATION_CHK_2_8821C 0 +#define BIT_MASK_ISOLATION_CHK_2_8821C 0xffffff +#define BIT_ISOLATION_CHK_2_8821C(x) (((x) & BIT_MASK_ISOLATION_CHK_2_8821C) << BIT_SHIFT_ISOLATION_CHK_2_8821C) +#define BIT_GET_ISOLATION_CHK_2_8821C(x) (((x) >> BIT_SHIFT_ISOLATION_CHK_2_8821C) & BIT_MASK_ISOLATION_CHK_2_8821C) + +/* 2 REG_BT_INTERRUPT_STATUS_REGISTER_8821C */ +#define BIT_BT_HID_ISR_8821C BIT(7) +#define BIT_BT_QUERY_ISR_8821C BIT(6) +#define BIT_MAC_NULL_PKT_NOTIFY_ISR_8821C BIT(5) +#define BIT_WLAN_RPT_ISR_8821C BIT(4) +#define BIT_BT_POWER_ISR_8821C BIT(3) +#define BIT_BT_CHANNEL_ISR_8821C BIT(2) +#define BIT_BT_SLOT_CHANGE_ISR_8821C BIT(1) +#define BIT_BT_PROFILE_ISR_8821C BIT(0) + +/* 2 REG_BT_TDMA_TIME_REGISTER_8821C */ + +#define BIT_SHIFT_BT_TIME_8821C 6 +#define BIT_MASK_BT_TIME_8821C 0x3ffffff +#define BIT_BT_TIME_8821C(x) (((x) & BIT_MASK_BT_TIME_8821C) << BIT_SHIFT_BT_TIME_8821C) +#define BIT_GET_BT_TIME_8821C(x) (((x) >> BIT_SHIFT_BT_TIME_8821C) & BIT_MASK_BT_TIME_8821C) + +#define BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C 0 +#define BIT_MASK_BT_RPT_SAMPLE_RATE_8821C 0x3f +#define BIT_BT_RPT_SAMPLE_RATE_8821C(x) (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) << BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) +#define BIT_GET_BT_RPT_SAMPLE_RATE_8821C(x) (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE_8821C) & BIT_MASK_BT_RPT_SAMPLE_RATE_8821C) + +/* 2 REG_BT_ACT_REGISTER_8821C */ + +#define BIT_SHIFT_BT_EISR_EN_8821C 16 +#define BIT_MASK_BT_EISR_EN_8821C 0xff +#define BIT_BT_EISR_EN_8821C(x) (((x) & BIT_MASK_BT_EISR_EN_8821C) << BIT_SHIFT_BT_EISR_EN_8821C) +#define BIT_GET_BT_EISR_EN_8821C(x) (((x) >> BIT_SHIFT_BT_EISR_EN_8821C) & BIT_MASK_BT_EISR_EN_8821C) + +#define BIT_BT_ACT_FALLING_ISR_8821C BIT(10) +#define BIT_BT_ACT_RISING_ISR_8821C BIT(9) +#define BIT_TDMA_TO_ISR_8821C BIT(8) + +#define BIT_SHIFT_BT_CH_8821C 0 +#define BIT_MASK_BT_CH_8821C 0xff +#define BIT_BT_CH_8821C(x) (((x) & BIT_MASK_BT_CH_8821C) << BIT_SHIFT_BT_CH_8821C) +#define BIT_GET_BT_CH_8821C(x) (((x) >> BIT_SHIFT_BT_CH_8821C) & BIT_MASK_BT_CH_8821C) + +/* 2 REG_OBFF_CTRL_BASIC_8821C */ +#define BIT_OBFF_EN_V1_8821C BIT(31) + +#define BIT_SHIFT_OBFF_STATE_V1_8821C 28 +#define BIT_MASK_OBFF_STATE_V1_8821C 0x3 +#define BIT_OBFF_STATE_V1_8821C(x) (((x) & BIT_MASK_OBFF_STATE_V1_8821C) << BIT_SHIFT_OBFF_STATE_V1_8821C) +#define BIT_GET_OBFF_STATE_V1_8821C(x) (((x) >> BIT_SHIFT_OBFF_STATE_V1_8821C) & BIT_MASK_OBFF_STATE_V1_8821C) + +#define BIT_OBFF_ACT_RXDMA_EN_8821C BIT(27) +#define BIT_OBFF_BLOCK_INT_EN_8821C BIT(26) +#define BIT_OBFF_AUTOACT_EN_8821C BIT(25) +#define BIT_OBFF_AUTOIDLE_EN_8821C BIT(24) + +#define BIT_SHIFT_WAKE_MAX_PLS_8821C 20 +#define BIT_MASK_WAKE_MAX_PLS_8821C 0x7 +#define BIT_WAKE_MAX_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MAX_PLS_8821C) << BIT_SHIFT_WAKE_MAX_PLS_8821C) +#define BIT_GET_WAKE_MAX_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_PLS_8821C) & BIT_MASK_WAKE_MAX_PLS_8821C) + +#define BIT_SHIFT_WAKE_MIN_PLS_8821C 16 +#define BIT_MASK_WAKE_MIN_PLS_8821C 0x7 +#define BIT_WAKE_MIN_PLS_8821C(x) (((x) & BIT_MASK_WAKE_MIN_PLS_8821C) << BIT_SHIFT_WAKE_MIN_PLS_8821C) +#define BIT_GET_WAKE_MIN_PLS_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_PLS_8821C) & BIT_MASK_WAKE_MIN_PLS_8821C) + +#define BIT_SHIFT_WAKE_MAX_F2F_8821C 12 +#define BIT_MASK_WAKE_MAX_F2F_8821C 0x7 +#define BIT_WAKE_MAX_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MAX_F2F_8821C) << BIT_SHIFT_WAKE_MAX_F2F_8821C) +#define BIT_GET_WAKE_MAX_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MAX_F2F_8821C) & BIT_MASK_WAKE_MAX_F2F_8821C) + +#define BIT_SHIFT_WAKE_MIN_F2F_8821C 8 +#define BIT_MASK_WAKE_MIN_F2F_8821C 0x7 +#define BIT_WAKE_MIN_F2F_8821C(x) (((x) & BIT_MASK_WAKE_MIN_F2F_8821C) << BIT_SHIFT_WAKE_MIN_F2F_8821C) +#define BIT_GET_WAKE_MIN_F2F_8821C(x) (((x) >> BIT_SHIFT_WAKE_MIN_F2F_8821C) & BIT_MASK_WAKE_MIN_F2F_8821C) + +#define BIT_APP_CPU_ACT_V1_8821C BIT(3) +#define BIT_APP_OBFF_V1_8821C BIT(2) +#define BIT_APP_IDLE_V1_8821C BIT(1) +#define BIT_APP_INIT_V1_8821C BIT(0) + +/* 2 REG_OBFF_CTRL2_TIMER_8821C */ + +#define BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C 24 +#define BIT_MASK_RX_HIGH_TIMER_IDX_8821C 0x7 +#define BIT_RX_HIGH_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) << BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) +#define BIT_GET_RX_HIGH_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX_8821C) & BIT_MASK_RX_HIGH_TIMER_IDX_8821C) + +#define BIT_SHIFT_RX_MED_TIMER_IDX_8821C 16 +#define BIT_MASK_RX_MED_TIMER_IDX_8821C 0x7 +#define BIT_RX_MED_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TIMER_IDX_8821C) << BIT_SHIFT_RX_MED_TIMER_IDX_8821C) +#define BIT_GET_RX_MED_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX_8821C) & BIT_MASK_RX_MED_TIMER_IDX_8821C) + +#define BIT_SHIFT_RX_LOW_TIMER_IDX_8821C 8 +#define BIT_MASK_RX_LOW_TIMER_IDX_8821C 0x7 +#define BIT_RX_LOW_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) << BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) +#define BIT_GET_RX_LOW_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX_8821C) & BIT_MASK_RX_LOW_TIMER_IDX_8821C) + +#define BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C 0 +#define BIT_MASK_OBFF_INT_TIMER_IDX_8821C 0x7 +#define BIT_OBFF_INT_TIMER_IDX_8821C(x) (((x) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) << BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) +#define BIT_GET_OBFF_INT_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX_8821C) & BIT_MASK_OBFF_INT_TIMER_IDX_8821C) + +/* 2 REG_LTR_CTRL_BASIC_8821C */ +#define BIT_LTR_EN_V1_8821C BIT(31) +#define BIT_LTR_HW_EN_V1_8821C BIT(30) +#define BIT_LRT_ACT_CTS_EN_8821C BIT(29) +#define BIT_LTR_ACT_RXPKT_EN_8821C BIT(28) +#define BIT_LTR_ACT_RXDMA_EN_8821C BIT(27) +#define BIT_LTR_IDLE_NO_SNOOP_8821C BIT(26) +#define BIT_SPDUP_MGTPKT_8821C BIT(25) +#define BIT_RX_AGG_EN_8821C BIT(24) +#define BIT_APP_LTR_ACT_8821C BIT(23) +#define BIT_APP_LTR_IDLE_8821C BIT(22) + +#define BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C 20 +#define BIT_MASK_HIGH_RATE_TRIG_SEL_8821C 0x3 +#define BIT_HIGH_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) << BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) +#define BIT_GET_HIGH_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL_8821C) & BIT_MASK_HIGH_RATE_TRIG_SEL_8821C) + +#define BIT_SHIFT_MED_RATE_TRIG_SEL_8821C 18 +#define BIT_MASK_MED_RATE_TRIG_SEL_8821C 0x3 +#define BIT_MED_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) << BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) +#define BIT_GET_MED_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL_8821C) & BIT_MASK_MED_RATE_TRIG_SEL_8821C) + +#define BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C 16 +#define BIT_MASK_LOW_RATE_TRIG_SEL_8821C 0x3 +#define BIT_LOW_RATE_TRIG_SEL_8821C(x) (((x) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) << BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) +#define BIT_GET_LOW_RATE_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL_8821C) & BIT_MASK_LOW_RATE_TRIG_SEL_8821C) + +#define BIT_SHIFT_HIGH_RATE_BD_IDX_8821C 8 +#define BIT_MASK_HIGH_RATE_BD_IDX_8821C 0x7f +#define BIT_HIGH_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) << BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) +#define BIT_GET_HIGH_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX_8821C) & BIT_MASK_HIGH_RATE_BD_IDX_8821C) + +#define BIT_SHIFT_LOW_RATE_BD_IDX_8821C 0 +#define BIT_MASK_LOW_RATE_BD_IDX_8821C 0x7f +#define BIT_LOW_RATE_BD_IDX_8821C(x) (((x) & BIT_MASK_LOW_RATE_BD_IDX_8821C) << BIT_SHIFT_LOW_RATE_BD_IDX_8821C) +#define BIT_GET_LOW_RATE_BD_IDX_8821C(x) (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX_8821C) & BIT_MASK_LOW_RATE_BD_IDX_8821C) + +/* 2 REG_LTR_CTRL2_TIMER_THRESHOLD_8821C */ + +#define BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C 24 +#define BIT_MASK_RX_EMPTY_TIMER_IDX_8821C 0x7 +#define BIT_RX_EMPTY_TIMER_IDX_8821C(x) (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) << BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) +#define BIT_GET_RX_EMPTY_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX_8821C) & BIT_MASK_RX_EMPTY_TIMER_IDX_8821C) + +#define BIT_SHIFT_RX_AFULL_TH_IDX_8821C 20 +#define BIT_MASK_RX_AFULL_TH_IDX_8821C 0x7 +#define BIT_RX_AFULL_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_AFULL_TH_IDX_8821C) << BIT_SHIFT_RX_AFULL_TH_IDX_8821C) +#define BIT_GET_RX_AFULL_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX_8821C) & BIT_MASK_RX_AFULL_TH_IDX_8821C) + +#define BIT_SHIFT_RX_HIGH_TH_IDX_8821C 16 +#define BIT_MASK_RX_HIGH_TH_IDX_8821C 0x7 +#define BIT_RX_HIGH_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_HIGH_TH_IDX_8821C) << BIT_SHIFT_RX_HIGH_TH_IDX_8821C) +#define BIT_GET_RX_HIGH_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX_8821C) & BIT_MASK_RX_HIGH_TH_IDX_8821C) + +#define BIT_SHIFT_RX_MED_TH_IDX_8821C 12 +#define BIT_MASK_RX_MED_TH_IDX_8821C 0x7 +#define BIT_RX_MED_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_MED_TH_IDX_8821C) << BIT_SHIFT_RX_MED_TH_IDX_8821C) +#define BIT_GET_RX_MED_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_MED_TH_IDX_8821C) & BIT_MASK_RX_MED_TH_IDX_8821C) + +#define BIT_SHIFT_RX_LOW_TH_IDX_8821C 8 +#define BIT_MASK_RX_LOW_TH_IDX_8821C 0x7 +#define BIT_RX_LOW_TH_IDX_8821C(x) (((x) & BIT_MASK_RX_LOW_TH_IDX_8821C) << BIT_SHIFT_RX_LOW_TH_IDX_8821C) +#define BIT_GET_RX_LOW_TH_IDX_8821C(x) (((x) >> BIT_SHIFT_RX_LOW_TH_IDX_8821C) & BIT_MASK_RX_LOW_TH_IDX_8821C) + +#define BIT_SHIFT_LTR_SPACE_IDX_8821C 4 +#define BIT_MASK_LTR_SPACE_IDX_8821C 0x3 +#define BIT_LTR_SPACE_IDX_8821C(x) (((x) & BIT_MASK_LTR_SPACE_IDX_8821C) << BIT_SHIFT_LTR_SPACE_IDX_8821C) +#define BIT_GET_LTR_SPACE_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_SPACE_IDX_8821C) & BIT_MASK_LTR_SPACE_IDX_8821C) + +#define BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C 0 +#define BIT_MASK_LTR_IDLE_TIMER_IDX_8821C 0x7 +#define BIT_LTR_IDLE_TIMER_IDX_8821C(x) (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) << BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) +#define BIT_GET_LTR_IDLE_TIMER_IDX_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX_8821C) & BIT_MASK_LTR_IDLE_TIMER_IDX_8821C) + +/* 2 REG_LTR_IDLE_LATENCY_V1_8821C */ + +#define BIT_SHIFT_LTR_IDLE_L_8821C 0 +#define BIT_MASK_LTR_IDLE_L_8821C 0xffffffffL +#define BIT_LTR_IDLE_L_8821C(x) (((x) & BIT_MASK_LTR_IDLE_L_8821C) << BIT_SHIFT_LTR_IDLE_L_8821C) +#define BIT_GET_LTR_IDLE_L_8821C(x) (((x) >> BIT_SHIFT_LTR_IDLE_L_8821C) & BIT_MASK_LTR_IDLE_L_8821C) + +/* 2 REG_LTR_ACTIVE_LATENCY_V1_8821C */ + +#define BIT_SHIFT_LTR_ACT_L_8821C 0 +#define BIT_MASK_LTR_ACT_L_8821C 0xffffffffL +#define BIT_LTR_ACT_L_8821C(x) (((x) & BIT_MASK_LTR_ACT_L_8821C) << BIT_SHIFT_LTR_ACT_L_8821C) +#define BIT_GET_LTR_ACT_L_8821C(x) (((x) >> BIT_SHIFT_LTR_ACT_L_8821C) & BIT_MASK_LTR_ACT_L_8821C) + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C */ + +#define BIT_SHIFT_TRAIN_STA_ADDR_0_8821C 0 +#define BIT_MASK_TRAIN_STA_ADDR_0_8821C 0xffffffffL +#define BIT_TRAIN_STA_ADDR_0_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) +#define BIT_GET_TRAIN_STA_ADDR_0_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_0_8821C) & BIT_MASK_TRAIN_STA_ADDR_0_8821C) + +/* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C */ +#define BIT_APPEND_MACID_IN_RESP_EN_1_8821C BIT(18) +#define BIT_ADDR2_MATCH_EN_1_8821C BIT(17) +#define BIT_ANTTRN_EN_1_8821C BIT(16) + +#define BIT_SHIFT_TRAIN_STA_ADDR_1_8821C 0 +#define BIT_MASK_TRAIN_STA_ADDR_1_8821C 0xffff +#define BIT_TRAIN_STA_ADDR_1_8821C(x) (((x) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) << BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) +#define BIT_GET_TRAIN_STA_ADDR_1_8821C(x) (((x) >> BIT_SHIFT_TRAIN_STA_ADDR_1_8821C) & BIT_MASK_TRAIN_STA_ADDR_1_8821C) + +/* 2 REG_WMAC_PKTCNT_RWD_8821C */ + +#define BIT_SHIFT_PKTCNT_BSSIDMAP_8821C 4 +#define BIT_MASK_PKTCNT_BSSIDMAP_8821C 0xf +#define BIT_PKTCNT_BSSIDMAP_8821C(x) (((x) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) << BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) +#define BIT_GET_PKTCNT_BSSIDMAP_8821C(x) (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP_8821C) & BIT_MASK_PKTCNT_BSSIDMAP_8821C) + +#define BIT_PKTCNT_CNTRST_8821C BIT(1) +#define BIT_PKTCNT_CNTEN_8821C BIT(0) + +/* 2 REG_WMAC_PKTCNT_CTRL_8821C */ +#define BIT_WMAC_PKTCNT_TRST_8821C BIT(9) +#define BIT_WMAC_PKTCNT_FEN_8821C BIT(8) + +#define BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C 0 +#define BIT_MASK_WMAC_PKTCNT_CFGAD_8821C 0xff +#define BIT_WMAC_PKTCNT_CFGAD_8821C(x) (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) << BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) +#define BIT_GET_WMAC_PKTCNT_CFGAD_8821C(x) (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD_8821C) & BIT_MASK_WMAC_PKTCNT_CFGAD_8821C) + +/* 2 REG_IQ_DUMP_8821C */ + +#define BIT_SHIFT_DUMP_OK_ADDR_8821C 15 +#define BIT_MASK_DUMP_OK_ADDR_8821C 0x1ffff +#define BIT_DUMP_OK_ADDR_8821C(x) (((x) & BIT_MASK_DUMP_OK_ADDR_8821C) << BIT_SHIFT_DUMP_OK_ADDR_8821C) +#define BIT_GET_DUMP_OK_ADDR_8821C(x) (((x) >> BIT_SHIFT_DUMP_OK_ADDR_8821C) & BIT_MASK_DUMP_OK_ADDR_8821C) + +#define BIT_SHIFT_R_TRIG_TIME_SEL_8821C 8 +#define BIT_MASK_R_TRIG_TIME_SEL_8821C 0x7f +#define BIT_R_TRIG_TIME_SEL_8821C(x) (((x) & BIT_MASK_R_TRIG_TIME_SEL_8821C) << BIT_SHIFT_R_TRIG_TIME_SEL_8821C) +#define BIT_GET_R_TRIG_TIME_SEL_8821C(x) (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL_8821C) & BIT_MASK_R_TRIG_TIME_SEL_8821C) + +#define BIT_SHIFT_R_MAC_TRIG_SEL_8821C 6 +#define BIT_MASK_R_MAC_TRIG_SEL_8821C 0x3 +#define BIT_R_MAC_TRIG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_TRIG_SEL_8821C) << BIT_SHIFT_R_MAC_TRIG_SEL_8821C) +#define BIT_GET_R_MAC_TRIG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL_8821C) & BIT_MASK_R_MAC_TRIG_SEL_8821C) + +#define BIT_MAC_TRIG_REG_8821C BIT(5) + +#define BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C 3 +#define BIT_MASK_R_LEVEL_PULSE_SEL_8821C 0x3 +#define BIT_R_LEVEL_PULSE_SEL_8821C(x) (((x) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) << BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) +#define BIT_GET_R_LEVEL_PULSE_SEL_8821C(x) (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL_8821C) & BIT_MASK_R_LEVEL_PULSE_SEL_8821C) + +#define BIT_EN_LA_MAC_8821C BIT(2) +#define BIT_R_EN_IQDUMP_8821C BIT(1) +#define BIT_R_IQDATA_DUMP_8821C BIT(0) + +/* 2 REG_IQ_DUMP_1_8821C */ + +#define BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C 0 +#define BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C 0xffffffffL +#define BIT_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) << BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) +#define BIT_GET_R_WMAC_MASK_LA_MAC_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC_1_8821C) & BIT_MASK_R_WMAC_MASK_LA_MAC_1_8821C) + +/* 2 REG_IQ_DUMP_2_8821C */ + +#define BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C 0 +#define BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C 0xffffffffL +#define BIT_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) << BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) +#define BIT_GET_R_WMAC_MATCH_REF_MAC_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC_2_8821C) & BIT_MASK_R_WMAC_MATCH_REF_MAC_2_8821C) + +/* 2 REG_WMAC_FTM_CTL_8821C */ +#define BIT_RXFTM_TXACK_SC_8821C BIT(6) +#define BIT_RXFTM_TXACK_BW_8821C BIT(5) +#define BIT_RXFTM_EN_8821C BIT(3) +#define BIT_RXFTMREQ_BYDRV_8821C BIT(2) +#define BIT_RXFTMREQ_EN_8821C BIT(1) +#define BIT_FTM_EN_8821C BIT(0) + +/* 2 REG_WMAC_IQ_MDPK_FUNC_8821C */ + +/* 2 REG_WMAC_OPTION_FUNCTION_8821C */ + +#define BIT_SHIFT_R_OFDM_LEN_8821C 26 +#define BIT_MASK_R_OFDM_LEN_8821C 0x3f +#define BIT_R_OFDM_LEN_8821C(x) (((x) & BIT_MASK_R_OFDM_LEN_8821C) << BIT_SHIFT_R_OFDM_LEN_8821C) +#define BIT_GET_R_OFDM_LEN_8821C(x) (((x) >> BIT_SHIFT_R_OFDM_LEN_8821C) & BIT_MASK_R_OFDM_LEN_8821C) + +#define BIT_SHIFT_R_CCK_LEN_8821C 0 +#define BIT_MASK_R_CCK_LEN_8821C 0xffff +#define BIT_R_CCK_LEN_8821C(x) (((x) & BIT_MASK_R_CCK_LEN_8821C) << BIT_SHIFT_R_CCK_LEN_8821C) +#define BIT_GET_R_CCK_LEN_8821C(x) (((x) >> BIT_SHIFT_R_CCK_LEN_8821C) & BIT_MASK_R_CCK_LEN_8821C) + +/* 2 REG_WMAC_OPTION_FUNCTION_1_8821C */ + +#define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C 24 +#define BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C 0xff +#define BIT_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) +#define BIT_GET_R_WMAC_RXFIFO_FULL_TH_1_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH_1_8821C) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH_1_8821C) + +#define BIT_R_WMAC_RX_SYNCFIFO_SYNC_1_8821C BIT(23) +#define BIT_R_WMAC_RXRST_DLY_1_8821C BIT(22) +#define BIT_R_WMAC_SRCH_TXRPT_REF_DROP_1_8821C BIT(21) +#define BIT_R_WMAC_SRCH_TXRPT_UA1_1_8821C BIT(20) +#define BIT_R_WMAC_SRCH_TXRPT_TYPE_1_8821C BIT(19) +#define BIT_R_WMAC_NDP_RST_1_8821C BIT(18) +#define BIT_R_WMAC_POWINT_EN_1_8821C BIT(17) +#define BIT_R_WMAC_SRCH_TXRPT_PERPKT_1_8821C BIT(16) +#define BIT_R_WMAC_SRCH_TXRPT_MID_1_8821C BIT(15) +#define BIT_R_WMAC_PFIN_TOEN_1_8821C BIT(14) +#define BIT_R_WMAC_FIL_SECERR_1_8821C BIT(13) +#define BIT_R_WMAC_FIL_CTLPKTLEN_1_8821C BIT(12) +#define BIT_R_WMAC_FIL_FCTYPE_1_8821C BIT(11) +#define BIT_R_WMAC_FIL_FCPROVER_1_8821C BIT(10) +#define BIT_R_WMAC_PHYSTS_SNIF_1_8821C BIT(9) +#define BIT_R_WMAC_PHYSTS_PLCP_1_8821C BIT(8) +#define BIT_R_MAC_TCR_VBONF_RD_1_8821C BIT(7) +#define BIT_R_WMAC_TCR_MPAR_NDP_1_8821C BIT(6) +#define BIT_R_WMAC_NDP_FILTER_1_8821C BIT(5) +#define BIT_R_WMAC_RXLEN_SEL_1_8821C BIT(4) +#define BIT_R_WMAC_RXLEN_SEL1_1_8821C BIT(3) +#define BIT_R_OFDM_FILTER_1_8821C BIT(2) +#define BIT_R_WMAC_CHK_OFDM_LEN_1_8821C BIT(1) +#define BIT_R_WMAC_CHK_CCK_LEN_1_8821C BIT(0) + +/* 2 REG_WMAC_OPTION_FUNCTION_2_8821C */ + +#define BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C 0 +#define BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C 0xffff +#define BIT_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) << BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) +#define BIT_GET_R_WMAC_RX_FIL_LEN_2_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN_2_8821C) & BIT_MASK_R_WMAC_RX_FIL_LEN_2_8821C) + +/* 2 REG_RX_FILTER_FUNCTION_8821C */ +#define BIT_R_WMAC_MHRDDY_LATCH_8821C BIT(14) +#define BIT_R_WMAC_MHRDDY_CLR_8821C BIT(13) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1_8821C BIT(12) +#define BIT_WMAC_DIS_VHT_PLCP_CHK_MU_8821C BIT(11) +#define BIT_R_CHK_DELIMIT_LEN_8821C BIT(10) +#define BIT_R_REAPTER_ADDR_MATCH_8821C BIT(9) +#define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY_8821C BIT(8) +#define BIT_R_LATCH_MACHRDY_8821C BIT(7) +#define BIT_R_WMAC_RXFIL_REND_8821C BIT(6) +#define BIT_R_WMAC_MPDURDY_CLR_8821C BIT(5) +#define BIT_R_WMAC_CLRRXSEC_8821C BIT(4) +#define BIT_R_WMAC_RXFIL_RDEL_8821C BIT(3) +#define BIT_R_WMAC_RXFIL_FCSE_8821C BIT(2) +#define BIT_R_WMAC_RXFIL_MESH_DEL_8821C BIT(1) +#define BIT_R_WMAC_RXFIL_MASKM_8821C BIT(0) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NDP_SIG_8821C */ + +#define BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C 0 +#define BIT_MASK_R_WMAC_TXNDP_SIGB_8821C 0x1fffff +#define BIT_R_WMAC_TXNDP_SIGB_8821C(x) (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) << BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) +#define BIT_GET_R_WMAC_TXNDP_SIGB_8821C(x) (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB_8821C) & BIT_MASK_R_WMAC_TXNDP_SIGB_8821C) + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_8821C */ + +#define BIT_SHIFT_R_MAC_DBG_SHIFT_8821C 8 +#define BIT_MASK_R_MAC_DBG_SHIFT_8821C 0x7 +#define BIT_R_MAC_DBG_SHIFT_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) << BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) +#define BIT_GET_R_MAC_DBG_SHIFT_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT_8821C) & BIT_MASK_R_MAC_DBG_SHIFT_8821C) + +#define BIT_SHIFT_R_MAC_DBG_SEL_8821C 0 +#define BIT_MASK_R_MAC_DBG_SEL_8821C 0x3 +#define BIT_R_MAC_DBG_SEL_8821C(x) (((x) & BIT_MASK_R_MAC_DBG_SEL_8821C) << BIT_SHIFT_R_MAC_DBG_SEL_8821C) +#define BIT_GET_R_MAC_DBG_SEL_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DBG_SEL_8821C) & BIT_MASK_R_MAC_DBG_SEL_8821C) + +/* 2 REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C */ + +#define BIT_SHIFT_R_MAC_DEBUG_1_8821C 0 +#define BIT_MASK_R_MAC_DEBUG_1_8821C 0xffffffffL +#define BIT_R_MAC_DEBUG_1_8821C(x) (((x) & BIT_MASK_R_MAC_DEBUG_1_8821C) << BIT_SHIFT_R_MAC_DEBUG_1_8821C) +#define BIT_GET_R_MAC_DEBUG_1_8821C(x) (((x) >> BIT_SHIFT_R_MAC_DEBUG_1_8821C) & BIT_MASK_R_MAC_DEBUG_1_8821C) + +/* 2 REG_WSEC_OPTION_8821C */ +#define BIT_RXDEC_BM_MGNT_8821C BIT(22) +#define BIT_TXENC_BM_MGNT_8821C BIT(21) +#define BIT_RXDEC_UNI_MGNT_8821C BIT(20) +#define BIT_TXENC_UNI_MGNT_8821C BIT(19) + +/* 2 REG_RTS_ADDRESS_0_8821C */ + +/* 2 REG_RTS_ADDRESS_0_1_8821C */ + +/* 2 REG_RTS_ADDRESS_1_8821C */ + +/* 2 REG_RTS_ADDRESS_1_1_8821C */ + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C */ +#define BIT_LTECOEX_ACCESS_START_V1_8821C BIT(31) +#define BIT_LTECOEX_WRITE_MODE_V1_8821C BIT(30) +#define BIT_LTECOEX_READY_BIT_V1_8821C BIT(29) + +#define BIT_SHIFT_WRITE_BYTE_EN_V1_8821C 16 +#define BIT_MASK_WRITE_BYTE_EN_V1_8821C 0xf +#define BIT_WRITE_BYTE_EN_V1_8821C(x) (((x) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) << BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) +#define BIT_GET_WRITE_BYTE_EN_V1_8821C(x) (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1_8821C) & BIT_MASK_WRITE_BYTE_EN_V1_8821C) + +#define BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C 0 +#define BIT_MASK_LTECOEX_REG_ADDR_V1_8821C 0xffff +#define BIT_LTECOEX_REG_ADDR_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) << BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) +#define BIT_GET_LTECOEX_REG_ADDR_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1_8821C) & BIT_MASK_LTECOEX_REG_ADDR_V1_8821C) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C */ + +#define BIT_SHIFT_LTECOEX_W_DATA_V1_8821C 0 +#define BIT_MASK_LTECOEX_W_DATA_V1_8821C 0xffffffffL +#define BIT_LTECOEX_W_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) +#define BIT_GET_LTECOEX_W_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1_8821C) & BIT_MASK_LTECOEX_W_DATA_V1_8821C) + +/* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C */ + +#define BIT_SHIFT_LTECOEX_R_DATA_V1_8821C 0 +#define BIT_MASK_LTECOEX_R_DATA_V1_8821C 0xffffffffL +#define BIT_LTECOEX_R_DATA_V1_8821C(x) (((x) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) << BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) +#define BIT_GET_LTECOEX_R_DATA_V1_8821C(x) (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1_8821C) & BIT_MASK_LTECOEX_R_DATA_V1_8821C) + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_NOT_VALID_8821C */ + +/* 2 REG_SDIO_TX_CTRL_8821C */ + +#define BIT_SHIFT_SDIO_INT_TIMEOUT_8821C 16 +#define BIT_MASK_SDIO_INT_TIMEOUT_8821C 0xffff +#define BIT_SDIO_INT_TIMEOUT_8821C(x) (((x) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) << BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) +#define BIT_GET_SDIO_INT_TIMEOUT_8821C(x) (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT_8821C) & BIT_MASK_SDIO_INT_TIMEOUT_8821C) + +#define BIT_IO_ERR_STATUS_8821C BIT(15) +#define BIT_REPLY_ERRCRC_IN_DATA_8821C BIT(9) +#define BIT_EN_CMD53_OVERLAP_8821C BIT(8) +#define BIT_REPLY_ERR_IN_R5_8821C BIT(7) +#define BIT_R18A_EN_8821C BIT(6) +#define BIT_INIT_CMD_EN_8821C BIT(5) +#define BIT_EN_RXDMA_MASK_INT_8821C BIT(2) +#define BIT_EN_MASK_TIMER_8821C BIT(1) +#define BIT_CMD_ERR_STOP_INT_EN_8821C BIT(0) + +/* 2 REG_SDIO_HIMR_8821C */ +#define BIT_SDIO_CRCERR_MSK_8821C BIT(31) +#define BIT_SDIO_HSISR3_IND_MSK_8821C BIT(30) +#define BIT_SDIO_HSISR2_IND_MSK_8821C BIT(29) +#define BIT_SDIO_HEISR_IND_MSK_8821C BIT(28) +#define BIT_SDIO_CTWEND_MSK_8821C BIT(27) +#define BIT_SDIO_ATIMEND_E_MSK_8821C BIT(26) +#define BIT_SDIIO_ATIMEND_MSK_8821C BIT(25) +#define BIT_SDIO_OCPINT_MSK_8821C BIT(24) +#define BIT_SDIO_PSTIMEOUT_MSK_8821C BIT(23) +#define BIT_SDIO_GTINT4_MSK_8821C BIT(22) +#define BIT_SDIO_GTINT3_MSK_8821C BIT(21) +#define BIT_SDIO_HSISR_IND_MSK_8821C BIT(20) +#define BIT_SDIO_CPWM2_MSK_8821C BIT(19) +#define BIT_SDIO_CPWM1_MSK_8821C BIT(18) +#define BIT_SDIO_C2HCMD_INT_MSK_8821C BIT(17) +#define BIT_SDIO_BCNERLY_INT_MSK_8821C BIT(16) +#define BIT_SDIO_TXBCNERR_MSK_8821C BIT(7) +#define BIT_SDIO_TXBCNOK_MSK_8821C BIT(6) +#define BIT_SDIO_RXFOVW_MSK_8821C BIT(5) +#define BIT_SDIO_TXFOVW_MSK_8821C BIT(4) +#define BIT_SDIO_RXERR_MSK_8821C BIT(3) +#define BIT_SDIO_TXERR_MSK_8821C BIT(2) +#define BIT_SDIO_AVAL_MSK_8821C BIT(1) +#define BIT_RX_REQUEST_MSK_8821C BIT(0) + +/* 2 REG_SDIO_HISR_8821C */ +#define BIT_SDIO_CRCERR_8821C BIT(31) +#define BIT_SDIO_HSISR3_IND_8821C BIT(30) +#define BIT_SDIO_HSISR2_IND_8821C BIT(29) +#define BIT_SDIO_HEISR_IND_8821C BIT(28) +#define BIT_SDIO_CTWEND_8821C BIT(27) +#define BIT_SDIO_ATIMEND_E_8821C BIT(26) +#define BIT_SDIO_ATIMEND_8821C BIT(25) +#define BIT_SDIO_OCPINT_8821C BIT(24) +#define BIT_SDIO_PSTIMEOUT_8821C BIT(23) +#define BIT_SDIO_GTINT4_8821C BIT(22) +#define BIT_SDIO_GTINT3_8821C BIT(21) +#define BIT_SDIO_HSISR_IND_8821C BIT(20) +#define BIT_SDIO_CPWM2_8821C BIT(19) +#define BIT_SDIO_CPWM1_8821C BIT(18) +#define BIT_SDIO_C2HCMD_INT_8821C BIT(17) +#define BIT_SDIO_BCNERLY_INT_8821C BIT(16) +#define BIT_SDIO_TXBCNERR_8821C BIT(7) +#define BIT_SDIO_TXBCNOK_8821C BIT(6) +#define BIT_SDIO_RXFOVW_8821C BIT(5) +#define BIT_SDIO_TXFOVW_8821C BIT(4) +#define BIT_SDIO_RXERR_8821C BIT(3) +#define BIT_SDIO_TXERR_8821C BIT(2) +#define BIT_SDIO_AVAL_8821C BIT(1) +#define BIT_RX_REQUEST_8821C BIT(0) + +/* 2 REG_SDIO_RX_REQ_LEN_8821C */ + +#define BIT_SHIFT_RX_REQ_LEN_V1_8821C 0 +#define BIT_MASK_RX_REQ_LEN_V1_8821C 0x3ffff +#define BIT_RX_REQ_LEN_V1_8821C(x) (((x) & BIT_MASK_RX_REQ_LEN_V1_8821C) << BIT_SHIFT_RX_REQ_LEN_V1_8821C) +#define BIT_GET_RX_REQ_LEN_V1_8821C(x) (((x) >> BIT_SHIFT_RX_REQ_LEN_V1_8821C) & BIT_MASK_RX_REQ_LEN_V1_8821C) + +/* 2 REG_SDIO_FREE_TXPG_SEQ_V1_8821C */ + +#define BIT_SHIFT_FREE_TXPG_SEQ_8821C 0 +#define BIT_MASK_FREE_TXPG_SEQ_8821C 0xff +#define BIT_FREE_TXPG_SEQ_8821C(x) (((x) & BIT_MASK_FREE_TXPG_SEQ_8821C) << BIT_SHIFT_FREE_TXPG_SEQ_8821C) +#define BIT_GET_FREE_TXPG_SEQ_8821C(x) (((x) >> BIT_SHIFT_FREE_TXPG_SEQ_8821C) & BIT_MASK_FREE_TXPG_SEQ_8821C) + +/* 2 REG_SDIO_FREE_TXPG_8821C */ + +#define BIT_SHIFT_MID_FREEPG_V1_8821C 16 +#define BIT_MASK_MID_FREEPG_V1_8821C 0xfff +#define BIT_MID_FREEPG_V1_8821C(x) (((x) & BIT_MASK_MID_FREEPG_V1_8821C) << BIT_SHIFT_MID_FREEPG_V1_8821C) +#define BIT_GET_MID_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_MID_FREEPG_V1_8821C) & BIT_MASK_MID_FREEPG_V1_8821C) + +#define BIT_SHIFT_HIQ_FREEPG_V1_8821C 0 +#define BIT_MASK_HIQ_FREEPG_V1_8821C 0xfff +#define BIT_HIQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_HIQ_FREEPG_V1_8821C) << BIT_SHIFT_HIQ_FREEPG_V1_8821C) +#define BIT_GET_HIQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_HIQ_FREEPG_V1_8821C) & BIT_MASK_HIQ_FREEPG_V1_8821C) + +/* 2 REG_SDIO_FREE_TXPG2_8821C */ + +#define BIT_SHIFT_PUB_FREEPG_V1_8821C 16 +#define BIT_MASK_PUB_FREEPG_V1_8821C 0xfff +#define BIT_PUB_FREEPG_V1_8821C(x) (((x) & BIT_MASK_PUB_FREEPG_V1_8821C) << BIT_SHIFT_PUB_FREEPG_V1_8821C) +#define BIT_GET_PUB_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_PUB_FREEPG_V1_8821C) & BIT_MASK_PUB_FREEPG_V1_8821C) + +#define BIT_SHIFT_LOW_FREEPG_V1_8821C 0 +#define BIT_MASK_LOW_FREEPG_V1_8821C 0xfff +#define BIT_LOW_FREEPG_V1_8821C(x) (((x) & BIT_MASK_LOW_FREEPG_V1_8821C) << BIT_SHIFT_LOW_FREEPG_V1_8821C) +#define BIT_GET_LOW_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_LOW_FREEPG_V1_8821C) & BIT_MASK_LOW_FREEPG_V1_8821C) + +/* 2 REG_SDIO_OQT_FREE_TXPG_V1_8821C */ + +#define BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C 24 +#define BIT_MASK_NOAC_OQT_FREEPG_V1_8821C 0xff +#define BIT_NOAC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) +#define BIT_GET_NOAC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1_8821C) & BIT_MASK_NOAC_OQT_FREEPG_V1_8821C) + +#define BIT_SHIFT_AC_OQT_FREEPG_V1_8821C 16 +#define BIT_MASK_AC_OQT_FREEPG_V1_8821C 0xff +#define BIT_AC_OQT_FREEPG_V1_8821C(x) (((x) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) << BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) +#define BIT_GET_AC_OQT_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1_8821C) & BIT_MASK_AC_OQT_FREEPG_V1_8821C) + +#define BIT_SHIFT_EXQ_FREEPG_V1_8821C 0 +#define BIT_MASK_EXQ_FREEPG_V1_8821C 0xfff +#define BIT_EXQ_FREEPG_V1_8821C(x) (((x) & BIT_MASK_EXQ_FREEPG_V1_8821C) << BIT_SHIFT_EXQ_FREEPG_V1_8821C) +#define BIT_GET_EXQ_FREEPG_V1_8821C(x) (((x) >> BIT_SHIFT_EXQ_FREEPG_V1_8821C) & BIT_MASK_EXQ_FREEPG_V1_8821C) + +/* 2 REG_SDIO_HTSFR_INFO_8821C */ + +#define BIT_SHIFT_HTSFR1_8821C 16 +#define BIT_MASK_HTSFR1_8821C 0xffff +#define BIT_HTSFR1_8821C(x) (((x) & BIT_MASK_HTSFR1_8821C) << BIT_SHIFT_HTSFR1_8821C) +#define BIT_GET_HTSFR1_8821C(x) (((x) >> BIT_SHIFT_HTSFR1_8821C) & BIT_MASK_HTSFR1_8821C) + +#define BIT_SHIFT_HTSFR0_8821C 0 +#define BIT_MASK_HTSFR0_8821C 0xffff +#define BIT_HTSFR0_8821C(x) (((x) & BIT_MASK_HTSFR0_8821C) << BIT_SHIFT_HTSFR0_8821C) +#define BIT_GET_HTSFR0_8821C(x) (((x) >> BIT_SHIFT_HTSFR0_8821C) & BIT_MASK_HTSFR0_8821C) + +/* 2 REG_SDIO_HCPWM1_V2_8821C */ +#define BIT_TOGGLING_8821C BIT(7) +#define BIT_ACK_8821C BIT(6) +#define BIT_SYS_CLK_8821C BIT(0) + +/* 2 REG_SDIO_HCPWM2_V2_8821C */ + +/* 2 REG_SDIO_INDIRECT_REG_CFG_8821C */ +#define BIT_INDIRECT_REG_RDY_8821C BIT(20) +#define BIT_INDIRECT_REG_R_8821C BIT(19) +#define BIT_INDIRECT_REG_W_8821C BIT(18) + +#define BIT_SHIFT_INDIRECT_REG_SIZE_8821C 16 +#define BIT_MASK_INDIRECT_REG_SIZE_8821C 0x3 +#define BIT_INDIRECT_REG_SIZE_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_SIZE_8821C) << BIT_SHIFT_INDIRECT_REG_SIZE_8821C) +#define BIT_GET_INDIRECT_REG_SIZE_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE_8821C) & BIT_MASK_INDIRECT_REG_SIZE_8821C) + +#define BIT_SHIFT_INDIRECT_REG_ADDR_8821C 0 +#define BIT_MASK_INDIRECT_REG_ADDR_8821C 0xffff +#define BIT_INDIRECT_REG_ADDR_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_ADDR_8821C) << BIT_SHIFT_INDIRECT_REG_ADDR_8821C) +#define BIT_GET_INDIRECT_REG_ADDR_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR_8821C) & BIT_MASK_INDIRECT_REG_ADDR_8821C) + +/* 2 REG_SDIO_INDIRECT_REG_DATA_8821C */ + +#define BIT_SHIFT_INDIRECT_REG_DATA_8821C 0 +#define BIT_MASK_INDIRECT_REG_DATA_8821C 0xffffffffL +#define BIT_INDIRECT_REG_DATA_8821C(x) (((x) & BIT_MASK_INDIRECT_REG_DATA_8821C) << BIT_SHIFT_INDIRECT_REG_DATA_8821C) +#define BIT_GET_INDIRECT_REG_DATA_8821C(x) (((x) >> BIT_SHIFT_INDIRECT_REG_DATA_8821C) & BIT_MASK_INDIRECT_REG_DATA_8821C) + +/* 2 REG_SDIO_H2C_8821C */ + +#define BIT_SHIFT_SDIO_H2C_MSG_8821C 0 +#define BIT_MASK_SDIO_H2C_MSG_8821C 0xffffffffL +#define BIT_SDIO_H2C_MSG_8821C(x) (((x) & BIT_MASK_SDIO_H2C_MSG_8821C) << BIT_SHIFT_SDIO_H2C_MSG_8821C) +#define BIT_GET_SDIO_H2C_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_H2C_MSG_8821C) & BIT_MASK_SDIO_H2C_MSG_8821C) + +/* 2 REG_SDIO_C2H_8821C */ + +#define BIT_SHIFT_SDIO_C2H_MSG_8821C 0 +#define BIT_MASK_SDIO_C2H_MSG_8821C 0xffffffffL +#define BIT_SDIO_C2H_MSG_8821C(x) (((x) & BIT_MASK_SDIO_C2H_MSG_8821C) << BIT_SHIFT_SDIO_C2H_MSG_8821C) +#define BIT_GET_SDIO_C2H_MSG_8821C(x) (((x) >> BIT_SHIFT_SDIO_C2H_MSG_8821C) & BIT_MASK_SDIO_C2H_MSG_8821C) + +/* 2 REG_SDIO_HRPWM1_8821C */ +#define BIT_TOGGLING_8821C BIT(7) +#define BIT_ACK_8821C BIT(6) +#define BIT_32K_PERMISSION_8821C BIT(0) + +/* 2 REG_SDIO_HRPWM2_8821C */ + +/* 2 REG_SDIO_HPS_CLKR_8821C */ + +/* 2 REG_SDIO_BUS_CTRL_8821C */ +#define BIT_PAD_CLK_XHGE_EN_8821C BIT(3) +#define BIT_INTER_CLK_EN_8821C BIT(2) +#define BIT_EN_RPT_TXCRC_8821C BIT(1) +#define BIT_DIS_RXDMA_STS_8821C BIT(0) + +/* 2 REG_SDIO_HSUS_CTRL_8821C */ +#define BIT_INTR_CTRL_8821C BIT(4) +#define BIT_SDIO_VOLTAGE_8821C BIT(3) +#define BIT_BYPASS_INIT_8821C BIT(2) +#define BIT_HCI_RESUME_RDY_8821C BIT(1) +#define BIT_HCI_SUS_REQ_8821C BIT(0) + +/* 2 REG_SDIO_RESPONSE_TIMER_8821C */ + +#define BIT_SHIFT_CMDIN_2RESP_TIMER_8821C 0 +#define BIT_MASK_CMDIN_2RESP_TIMER_8821C 0xffff +#define BIT_CMDIN_2RESP_TIMER_8821C(x) (((x) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) << BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) +#define BIT_GET_CMDIN_2RESP_TIMER_8821C(x) (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER_8821C) & BIT_MASK_CMDIN_2RESP_TIMER_8821C) + +/* 2 REG_SDIO_CMD_CRC_8821C */ + +#define BIT_SHIFT_SDIO_CMD_CRC_V1_8821C 0 +#define BIT_MASK_SDIO_CMD_CRC_V1_8821C 0xff +#define BIT_SDIO_CMD_CRC_V1_8821C(x) (((x) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) << BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) +#define BIT_GET_SDIO_CMD_CRC_V1_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1_8821C) & BIT_MASK_SDIO_CMD_CRC_V1_8821C) + +/* 2 REG_SDIO_HSISR_8821C */ +#define BIT_DRV_WLAN_INT_CLR_8821C BIT(1) +#define BIT_DRV_WLAN_INT_8821C BIT(0) + +/* 2 REG_SDIO_HSIMR_8821C */ +#define BIT_HISR_MASK_8821C BIT(0) + +/* 2 REG_SDIO_ERR_RPT_8821C */ +#define BIT_HR_FF_OVF_8821C BIT(6) +#define BIT_HR_FF_UDN_8821C BIT(5) +#define BIT_TXDMA_BUSY_ERR_8821C BIT(4) +#define BIT_TXDMA_VLD_ERR_8821C BIT(3) +#define BIT_QSEL_UNKNOWN_ERR_8821C BIT(2) +#define BIT_QSEL_MIS_ERR_8821C BIT(1) +#define BIT_SDIO_OVERRD_ERR_8821C BIT(0) + +/* 2 REG_SDIO_CMD_ERRCNT_8821C */ + +#define BIT_SHIFT_CMD_CRC_ERR_CNT_8821C 0 +#define BIT_MASK_CMD_CRC_ERR_CNT_8821C 0xff +#define BIT_CMD_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) << BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) +#define BIT_GET_CMD_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT_8821C) & BIT_MASK_CMD_CRC_ERR_CNT_8821C) + +/* 2 REG_SDIO_DATA_ERRCNT_8821C */ + +#define BIT_SHIFT_DATA_CRC_ERR_CNT_8821C 0 +#define BIT_MASK_DATA_CRC_ERR_CNT_8821C 0xff +#define BIT_DATA_CRC_ERR_CNT_8821C(x) (((x) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) << BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) +#define BIT_GET_DATA_CRC_ERR_CNT_8821C(x) (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT_8821C) & BIT_MASK_DATA_CRC_ERR_CNT_8821C) + +/* 2 REG_SDIO_CMD_ERR_CONTENT_8821C */ + +#define BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C 0 +#define BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C 0xffffffffffL +#define BIT_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) << BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) +#define BIT_GET_SDIO_CMD_ERR_CONTENT_8821C(x) (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT_8821C) & BIT_MASK_SDIO_CMD_ERR_CONTENT_8821C) + +/* 2 REG_SDIO_CRC_ERR_IDX_8821C */ +#define BIT_D3_CRC_ERR_8821C BIT(4) +#define BIT_D2_CRC_ERR_8821C BIT(3) +#define BIT_D1_CRC_ERR_8821C BIT(2) +#define BIT_D0_CRC_ERR_8821C BIT(1) +#define BIT_CMD_CRC_ERR_8821C BIT(0) + +/* 2 REG_SDIO_DATA_CRC_8821C */ + +#define BIT_SHIFT_SDIO_DATA_CRC_8821C 0 +#define BIT_MASK_SDIO_DATA_CRC_8821C 0xff +#define BIT_SDIO_DATA_CRC_8821C(x) (((x) & BIT_MASK_SDIO_DATA_CRC_8821C) << BIT_SHIFT_SDIO_DATA_CRC_8821C) +#define BIT_GET_SDIO_DATA_CRC_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_CRC_8821C) & BIT_MASK_SDIO_DATA_CRC_8821C) + +/* 2 REG_SDIO_DATA_REPLY_TIME_8821C */ + +#define BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C 0 +#define BIT_MASK_SDIO_DATA_REPLY_TIME_8821C 0x7 +#define BIT_SDIO_DATA_REPLY_TIME_8821C(x) (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) << BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) +#define BIT_GET_SDIO_DATA_REPLY_TIME_8821C(x) (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME_8821C) & BIT_MASK_SDIO_DATA_REPLY_TIME_8821C) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_info.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_info.h new file mode 100644 index 000000000000..d1156b1916c1 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_info.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_FW_INFO_H_ +#define _HALMAC_FW_INFO_H_ + +#define H2C_FORMAT_VERSION 6 + +#define H2C_ACK_HDR_CONTENT_LENGTH 8 +#define CFG_PARAMETER_ACK_CONTENT_LENGTH 16 +#define SCAN_STATUS_RPT_CONTENT_LENGTH 4 +#define C2H_DBG_HEADER_LENGTH 4 +#define C2H_DBG_CONTENT_MAX_LENGTH 228 + +#define C2H_DBG_CONTENT_SEQ_OFFSET 1 + +/* Rename from FW SysHalCom_Debug_RAM.h */ +#define FW_REG_H2CPKT_DONE_SEQ 0x1C8 +#define FW_REG_WoW_REASON 0x1C7 + +typedef enum _HALMAC_DATA_TYPE { + HALMAC_DATA_TYPE_MAC_REG = 0x00, + HALMAC_DATA_TYPE_BB_REG = 0x01, + HALMAC_DATA_TYPE_RADIO_A = 0x02, + HALMAC_DATA_TYPE_RADIO_B = 0x03, + HALMAC_DATA_TYPE_RADIO_C = 0x04, + HALMAC_DATA_TYPE_RADIO_D = 0x05, + + HALMAC_DATA_TYPE_DRV_DEFINE_0 = 0x80, + HALMAC_DATA_TYPE_DRV_DEFINE_1 = 0x81, + HALMAC_DATA_TYPE_DRV_DEFINE_2 = 0x82, + HALMAC_DATA_TYPE_DRV_DEFINE_3 = 0x83, + HALMAC_DATA_TYPE_UNDEFINE = 0x7FFFFFFF, +} HALMAC_DATA_TYPE; + +typedef enum _HALMAC_PACKET_ID { + HALMAC_PACKET_PROBE_REQ = 0x00, + HALMAC_PACKET_SYNC_BCN = 0x01, + HALMAC_PACKET_DISCOVERY_BCN = 0x02, + + HALMAC_PACKET_UNDEFINE = 0x7FFFFFFF, +} HALMAC_PACKET_ID; + +/* Channel Switch Action ID */ +typedef enum _HALMAC_CS_ACTION_ID { + HALMAC_CS_ACTION_NONE = 0x00, + HALMAC_CS_ACTIVE_SCAN = 0x01, + HALMAC_CS_NAN_NONMASTER_DW = 0x02, + HALMAC_CS_NAN_NONMASTER_NONDW = 0x03, + HALMAC_CS_NAN_MASTER_NONDW = 0x04, + HALMAC_CS_NAN_MASTER_DW = 0x05, + + HALMAC_CS_ACTION_UNDEFINE = 0x7FFFFFFF, +} HALMAC_CS_ACTION_ID; + +/* Channel Switch Extra Action ID */ +typedef enum _HALMAC_CS_EXTRA_ACTION_ID { + HALMAC_CS_EXTRA_ACTION_NONE = 0x00, + HALMAC_CS_EXTRA_UPDATE_PROBE = 0x01, + HALMAC_CS_EXTRA_UPDATE_BEACON = 0x02, + + HALMAC_CS_EXTRA_ACTION_UNDEFINE = 0x7FFFFFFF, +} HALMAC_CS_EXTRA_ACTION_ID; + +typedef enum _HALMAC_H2C_RETURN_CODE { + HALMAC_H2C_RETURN_SUCCESS = 0x00, + HALMAC_H2C_RETURN_CFG_ERR_LEN = 0x01, + HALMAC_H2C_RETURN_CFG_ERR_CMD = 0x02, + + HALMAC_H2C_RETURN_EFUSE_ERR_DUMP = 0x03, + + HALMAC_H2C_RETURN_DATAPACK_ERR_FULL = 0x04, /* DMEM buffer full */ + HALMAC_H2C_RETURN_DATAPACK_ERR_ID = 0x05, /* Invalid pack id */ + + HALMAC_H2C_RETURN_RUN_ERR_EMPTY = 0x06, /* No data in dedicated buffer */ + HALMAC_H2C_RETURN_RUN_ERR_LEN = 0x07, + HALMAC_H2C_RETURN_RUN_ERR_CMD = 0x08, + HALMAC_H2C_RETURN_RUN_ERR_ID = 0x09, /* Invalid pack id */ + + HALMAC_H2C_RETURN_PACKET_ERR_FULL = 0x0A, /* DMEM buffer full */ + HALMAC_H2C_RETURN_PACKET_ERR_ID = 0x0B, /* Invalid packet id */ + + HALMAC_H2C_RETURN_SCAN_ERR_FULL = 0x0C, /* DMEM buffer full */ + HALMAC_H2C_RETURN_SCAN_ERR_PHYDM = 0x0D, /* PHYDM API return fail */ + + HALMAC_H2C_RETURN_ORIG_ERR_ID = 0x0E, /* Invalid original H2C cmd id */ + + HALMAC_H2C_RETURN_UNDEFINE = 0x7FFFFFFF, +} HALMAC_H2C_RETURN_CODE; + +typedef enum _HALMAC_SCAN_REPORT_CODE { + HALMAC_SCAN_REPORT_DONE = 0x00, + HALMAC_SCAN_REPORT_ERR_PHYDM = 0x01, /* PHYDM API return fail */ + HALMAC_SCAN_REPORT_ERR_ID = 0x02, /* Invalid ActionID */ + HALMAC_SCAN_REPORT_ERR_TX = 0x03, /* Tx RsvdPage fail */ + + HALMAC_SCAN_REPORT_UNDEFINE = 0x7FFFFFFF, +} HALMAC_SCAN_REPORT_CODE; + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h new file mode 100644 index 000000000000..db2663c644eb --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_ap.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ +#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_AP_H_ +#define C2H_SUB_CMD_ID_C2H_DBG 0X00 +#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 +#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 +#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 +#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01 +#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 +#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01 +#define C2H_SUB_CMD_ID_IQK_ACK 0X01 +#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_DATA 0X04 +#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D +#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER +#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX +#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE +#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET +#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK +#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK +#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH +#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK +#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING +#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD +#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT +#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF +#define H2C_CMD_ID_BT_COEX_ACK 0XFF +#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF +#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF +#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF +#define H2C_CMD_ID_IQK_ACK 0XFF +#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF +#define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF +#define C2H_HDR_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_HDR_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_HDR_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_HDR_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) +#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_HDR_SET_C2H_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_HDR_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) +#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_HDR_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_DBG_GET_DBG_MSG(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define C2H_DBG_SET_DBG_MSG_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define BT_COEX_INFO_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define BT_COEX_INFO_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) +#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) +#define SCAN_STATUS_RPT_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) +#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define H2C_ACK_HDR_SET_H2C_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) +#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 16) +#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 16, __Value) +#define H2C_ACK_HDR_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 16, __Value) +#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 32) +#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 32, __Value) +#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 32, __Value) +#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) GET_C2H_FIELD(__pC2H + 0X10, 0, 32) +#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X10, 0, 32, __Value) +#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X10, 0, 32, __Value) +#define BT_COEX_ACK_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0XC, 0, 8) +#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0XC, 0, 8, __Value) +#define BT_COEX_ACK_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0XC, 0, 8, __Value) +#define PSD_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) +#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) +#define PSD_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) +#define PSD_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) +#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) +#define PSD_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) +#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define PSD_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) +#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) +#define PSD_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) +#define PSD_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) +#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) +#define PSD_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) +#define PSD_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) +#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) +#define PSD_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) +#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) +#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) +#define EFUSE_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) +#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) +#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) +#define EFUSE_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) +#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define EFUSE_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) +#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) +#define EFUSE_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) +#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) +#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) +#define EFUSE_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) +#define EFUSE_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) +#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) +#define EFUSE_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) +#define IQK_DATA_GET_SEGMENT_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 7, __Value) +#define IQK_DATA_SET_SEGMENT_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 7, __Value) +#define IQK_DATA_GET_END_SEGMENT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 7, 1, __Value) +#define IQK_DATA_SET_END_SEGMENT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 7, 1, __Value) +#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define IQK_DATA_SET_SEGMENT_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 16, __Value) +#define IQK_DATA_SET_TOTAL_SIZE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 16, __Value) +#define IQK_DATA_GET_H2C_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 0, 16, __Value) +#define IQK_DATA_SET_H2C_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 0, 16, __Value) +#define IQK_DATA_GET_DATA_START(__pC2H) GET_C2H_FIELD(__pC2H + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X8, 16, 8, __Value) +#define IQK_DATA_SET_DATA_START_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X8, 16, 8, __Value) +#define CCX_RPT_GET_CCX RPT(__pC2H) GET_C2H_FIELD(__pC2H + 0X4, 0, 129) +#define CCX_RPT_SET_CCX RPT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X4, 0, 129, __Value) +#define CCX_RPT_SET_CCX RPT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X4, 0, 129, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h new file mode 100644 index 000000000000..bafb688812d7 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_c2h_nic.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ +#define _HAL_FWOFFLOADC2HFORMAT_H2C_C2H_NIC_H_ +#define C2H_SUB_CMD_ID_C2H_DBG 0X00 +#define C2H_SUB_CMD_ID_BT_COEX_INFO 0X02 +#define C2H_SUB_CMD_ID_SCAN_STATUS_RPT 0X03 +#define C2H_SUB_CMD_ID_H2C_ACK_HDR 0X01 +#define C2H_SUB_CMD_ID_CFG_PARAMETER_ACK 0X01 +#define C2H_SUB_CMD_ID_BT_COEX_ACK 0X01 +#define C2H_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_PACKET_ACK 0X01 +#define C2H_SUB_CMD_ID_UPDATE_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_RUN_DATAPACK_ACK 0X01 +#define C2H_SUB_CMD_ID_CHANNEL_SWITCH_ACK 0X01 +#define C2H_SUB_CMD_ID_IQK_ACK 0X01 +#define C2H_SUB_CMD_ID_POWER_TRACKING_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_ACK 0X01 +#define C2H_SUB_CMD_ID_PSD_DATA 0X04 +#define C2H_SUB_CMD_ID_EFUSE_DATA 0X05 +#define C2H_SUB_CMD_ID_IQK_DATA 0X06 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_DBG 0X07 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_2_DBG 0X08 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_3_DBG 0X09 +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_4_DBG 0X0A +#define C2H_SUB_CMD_ID_FTMACKRPT_HDL_DBG 0X0B +#define C2H_SUB_CMD_ID_FTMC2H_RPT 0X0C +#define C2H_SUB_CMD_ID_DRVFTMC2H_RPT 0X0D +#define C2H_SUB_CMD_ID_C2H_PKT_FTM_5_DBG 0X0E +#define C2H_SUB_CMD_ID_CCX_RPT 0X0F +#define C2H_SUB_CMD_ID_C2H_PKT_NAN_RPT 0X10 +#define C2H_SUB_CMD_ID_C2H_PKT_ATM_RPT 0X11 +#define C2H_SUB_CMD_ID_C2H_PKT_FTMSESSION_END 0X1C +#define C2H_SUB_CMD_ID_C2H_PKT_DETECT_THERMAL 0X1D +#define H2C_SUB_CMD_ID_CFG_PARAMETER_ACK SUB_CMD_ID_CFG_PARAMETER +#define H2C_SUB_CMD_ID_BT_COEX_ACK SUB_CMD_ID_BT_COEX +#define H2C_SUB_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK SUB_CMD_ID_DUMP_PHYSICAL_EFUSE +#define H2C_SUB_CMD_ID_UPDATE_PACKET_ACK SUB_CMD_ID_UPDATE_PACKET +#define H2C_SUB_CMD_ID_UPDATE_DATAPACK_ACK SUB_CMD_ID_UPDATE_DATAPACK +#define H2C_SUB_CMD_ID_RUN_DATAPACK_ACK SUB_CMD_ID_RUN_DATAPACK +#define H2C_SUB_CMD_ID_CHANNEL_SWITCH_ACK SUB_CMD_ID_CHANNEL_SWITCH +#define H2C_SUB_CMD_ID_IQK_ACK SUB_CMD_ID_IQK +#define H2C_SUB_CMD_ID_POWER_TRACKING_ACK SUB_CMD_ID_POWER_TRACKING +#define H2C_SUB_CMD_ID_PSD_ACK SUB_CMD_ID_PSD +#define H2C_SUB_CMD_ID_CCX_RPT SUB_CMD_ID_CCX_RPT +#define H2C_CMD_ID_CFG_PARAMETER_ACK 0XFF +#define H2C_CMD_ID_BT_COEX_ACK 0XFF +#define H2C_CMD_ID_DUMP_PHYSICAL_EFUSE_ACK 0XFF +#define H2C_CMD_ID_UPDATE_PACKET_ACK 0XFF +#define H2C_CMD_ID_UPDATE_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_RUN_DATAPACK_ACK 0XFF +#define H2C_CMD_ID_CHANNEL_SWITCH_ACK 0XFF +#define H2C_CMD_ID_IQK_ACK 0XFF +#define H2C_CMD_ID_POWER_TRACKING_ACK 0XFF +#define H2C_CMD_ID_PSD_ACK 0XFF +#define H2C_CMD_ID_CCX_RPT 0XFF +#define C2H_HDR_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_HDR_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_HDR_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_HDR_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_HDR_GET_C2H_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) +#define C2H_HDR_SET_C2H_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) +#define C2H_HDR_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) +#define C2H_HDR_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) +#define C2H_DBG_GET_DBG_MSG(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define C2H_DBG_SET_DBG_MSG(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define BT_COEX_INFO_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define BT_COEX_INFO_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define SCAN_STATUS_RPT_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define SCAN_STATUS_RPT_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define SCAN_STATUS_RPT_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) +#define SCAN_STATUS_RPT_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) +#define H2C_ACK_HDR_GET_H2C_RETURN_CODE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define H2C_ACK_HDR_SET_H2C_RETURN_CODE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define H2C_ACK_HDR_GET_H2C_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define H2C_ACK_HDR_SET_H2C_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define H2C_ACK_HDR_GET_H2C_SUB_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) +#define H2C_ACK_HDR_SET_H2C_SUB_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) +#define H2C_ACK_HDR_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 16) +#define H2C_ACK_HDR_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 16, __Value) +#define CFG_PARAMETER_ACK_GET_OFFSET_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 32) +#define CFG_PARAMETER_ACK_SET_OFFSET_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 32, __Value) +#define CFG_PARAMETER_ACK_GET_VALUE_ACCUMULATION(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X10, 0, 32) +#define CFG_PARAMETER_ACK_SET_VALUE_ACCUMULATION(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X10, 0, 32, __Value) +#define BT_COEX_ACK_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0XC, 0, 8) +#define BT_COEX_ACK_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0XC, 0, 8, __Value) +#define PSD_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) +#define PSD_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) +#define PSD_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) +#define PSD_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) +#define PSD_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define PSD_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define PSD_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) +#define PSD_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) +#define PSD_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) +#define PSD_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) +#define PSD_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) +#define PSD_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) +#define EFUSE_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) +#define EFUSE_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) +#define EFUSE_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) +#define EFUSE_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) +#define EFUSE_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define EFUSE_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define EFUSE_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) +#define EFUSE_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) +#define EFUSE_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) +#define EFUSE_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) +#define EFUSE_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) +#define EFUSE_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) +#define IQK_DATA_GET_SEGMENT_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 7) +#define IQK_DATA_SET_SEGMENT_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 7, __Value) +#define IQK_DATA_GET_END_SEGMENT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 7, 1) +#define IQK_DATA_SET_END_SEGMENT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 7, 1, __Value) +#define IQK_DATA_GET_SEGMENT_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define IQK_DATA_SET_SEGMENT_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define IQK_DATA_GET_TOTAL_SIZE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 16) +#define IQK_DATA_SET_TOTAL_SIZE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 16, __Value) +#define IQK_DATA_GET_H2C_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 0, 16) +#define IQK_DATA_SET_H2C_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 0, 16, __Value) +#define IQK_DATA_GET_DATA_START(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X8, 16, 8) +#define IQK_DATA_SET_DATA_START(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X8, 16, 8, __Value) +#define CCX_RPT_GET_CCX RPT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X4, 0, 129) +#define CCX_RPT_SET_CCX RPT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X4, 0, 129, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h new file mode 100644 index 000000000000..385d73c2addb --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_ap.h @@ -0,0 +1,421 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ +#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_AP_H_ +#define CMD_ID_FW_OFFLOAD_H2C 0XFF +#define CMD_ID_CHANNEL_SWITCH 0XFF +#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF +#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF +#define CMD_ID_CFG_PARAMETER 0XFF +#define CMD_ID_UPDATE_DATAPACK 0XFF +#define CMD_ID_RUN_DATAPACK 0XFF +#define CMD_ID_DOWNLOAD_FLASH 0XFF +#define CMD_ID_UPDATE_PACKET 0XFF +#define CMD_ID_GENERAL_INFO 0XFF +#define CMD_ID_IQK 0XFF +#define CMD_ID_POWER_TRACKING 0XFF +#define CMD_ID_PSD 0XFF +#define CMD_ID_P2PPS 0XFF +#define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF +#define CATEGORY_H2C_CMD_HEADER 0X00 +#define CATEGORY_FW_OFFLOAD_H2C 0X01 +#define CATEGORY_CHANNEL_SWITCH 0X01 +#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 +#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 +#define CATEGORY_CFG_PARAMETER 0X01 +#define CATEGORY_UPDATE_DATAPACK 0X01 +#define CATEGORY_RUN_DATAPACK 0X01 +#define CATEGORY_DOWNLOAD_FLASH 0X01 +#define CATEGORY_UPDATE_PACKET 0X01 +#define CATEGORY_GENERAL_INFO 0X01 +#define CATEGORY_IQK 0X01 +#define CATEGORY_POWER_TRACKING 0X01 +#define CATEGORY_PSD 0X01 +#define CATEGORY_P2PPS 0X01 +#define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 +#define SUB_CMD_ID_CHANNEL_SWITCH 0X02 +#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 +#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 +#define SUB_CMD_ID_CFG_PARAMETER 0X08 +#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 +#define SUB_CMD_ID_RUN_DATAPACK 0X0A +#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B +#define SUB_CMD_ID_UPDATE_PACKET 0X0C +#define SUB_CMD_ID_GENERAL_INFO 0X0D +#define SUB_CMD_ID_IQK 0X0E +#define SUB_CMD_ID_POWER_TRACKING 0X0F +#define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_P2PPS 0X24 +#define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 +#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7) +#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value) +#define H2C_CMD_HEADER_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value) +#define H2C_CMD_HEADER_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1) +#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value) +#define H2C_CMD_HEADER_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value) +#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16) +#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value) +#define H2C_CMD_HEADER_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value) +#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16) +#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value) +#define H2C_CMD_HEADER_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value) +#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 7) +#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 7, __Value) +#define FW_OFFLOAD_H2C_SET_CATEGORY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 7, __Value) +#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 7, 1) +#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 7, 1, __Value) +#define FW_OFFLOAD_H2C_SET_ACK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 7, 1, __Value) +#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define FW_OFFLOAD_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value) +#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 16) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 16, __Value) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 16, __Value) +#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 16) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 16, __Value) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 16, __Value) +#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) +#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) +#define CHANNEL_SWITCH_SET_SWITCH_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) +#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) +#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) +#define CHANNEL_SWITCH_SET_DEST_CH_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) +#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) +#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) +#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) +#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 2) +#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 2, __Value) +#define CHANNEL_SWITCH_SET_PERIODIC_OPTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 2, __Value) +#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define CHANNEL_SWITCH_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 4) +#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 4, __Value) +#define CHANNEL_SWITCH_SET_PRI_CH_IDX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 4, __Value) +#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 28, 4) +#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 28, 4, __Value) +#define CHANNEL_SWITCH_SET_DEST_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 28, 4, __Value) +#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) +#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define CHANNEL_SWITCH_SET_DEST_CH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8) +#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value) +#define CHANNEL_SWITCH_SET_NORMAL_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value) +#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8) +#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value) +#define CHANNEL_SWITCH_SET_SLOW_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value) +#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 24, 8) +#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 24, 8, __Value) +#define CHANNEL_SWITCH_SET_NORMAL_CYCLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 24, 8, __Value) +#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) +#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) +#define CHANNEL_SWITCH_SET_TSF_HIGH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) +#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) +#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) +#define CHANNEL_SWITCH_SET_TSF_LOW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) +#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 16) +#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 16, __Value) +#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 16, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 4, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 4, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 12, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 12, 4, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 12, 4, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value) +#define CFG_PARAMETER_GET_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) +#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) +#define CFG_PARAMETER_SET_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) +#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 1) +#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 1, __Value) +#define CFG_PARAMETER_SET_INIT_CASE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 1, __Value) +#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) +#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) +#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) +#define UPDATE_DATAPACK_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) +#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) +#define UPDATE_DATAPACK_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) +#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define UPDATE_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) +#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 1) +#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 1, __Value) +#define UPDATE_DATAPACK_SET_END_SEGMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 1, __Value) +#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define RUN_DATAPACK_SET_DATAPACK_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define DOWNLOAD_FLASH_SET_SPI_CMD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 16) +#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 16, __Value) +#define DOWNLOAD_FLASH_SET_LOCATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 16, __Value) +#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 32) +#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 32, __Value) +#define DOWNLOAD_FLASH_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 32, __Value) +#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) +#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) +#define DOWNLOAD_FLASH_SET_START_ADDR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) +#define UPDATE_PACKET_GET_SIZE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) +#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) +#define UPDATE_PACKET_SET_SIZE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) +#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define UPDATE_PACKET_SET_PACKET_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) +#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) +#define UPDATE_PACKET_SET_PACKET_LOC_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) +#define GENERAL_INFO_GET_REF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define GENERAL_INFO_SET_REF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define GENERAL_INFO_GET_RF_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 9) +#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 9, __Value) +#define GENERAL_INFO_SET_RF_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 9, __Value) +#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define IQK_GET_CLEAR(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) +#define IQK_SET_CLEAR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) +#define IQK_SET_CLEAR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) +#define IQK_GET_SEGMENT_IQK(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) +#define IQK_SET_SEGMENT_IQK_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) +#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) +#define POWER_TRACKING_SET_ENABLE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) +#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) +#define POWER_TRACKING_SET_ENABLE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) +#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) +#define POWER_TRACKING_SET_ENABLE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1) +#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value) +#define POWER_TRACKING_SET_ENABLE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value) +#define POWER_TRACKING_GET_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 3) +#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 3, __Value) +#define POWER_TRACKING_SET_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 3, __Value) +#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define POWER_TRACKING_SET_BBSWING_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define POWER_TRACKING_SET_TX_PWR_INDEX_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 8, 8, __Value) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 8, __Value) +#define POWER_TRACKING_SET_TSSI_VALUE_A_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) +#define POWER_TRACKING_SET_TX_PWR_INDEX_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 16, 8, __Value) +#define POWER_TRACKING_SET_TSSI_VALUE_B_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 16, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 8, __Value) +#define POWER_TRACKING_SET_TX_PWR_INDEX_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 8, 8, __Value) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 8, __Value) +#define POWER_TRACKING_SET_TSSI_VALUE_C_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) +#define POWER_TRACKING_SET_TX_PWR_INDEX_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 16, 8, __Value) +#define POWER_TRACKING_SET_TSSI_VALUE_D_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 16, 8, __Value) +#define PSD_GET_START_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 16) +#define PSD_SET_START_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 16, __Value) +#define PSD_SET_START_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 16, __Value) +#define PSD_GET_END_PSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 16) +#define PSD_SET_END_PSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 16, __Value) +#define PSD_SET_END_PSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 16, __Value) +#define P2PPS_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 1, __Value) +#define P2PPS_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 1, __Value) +#define P2PPS_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 1, 1) +#define P2PPS_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 1, 1, __Value) +#define P2PPS_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 1, 1, __Value) +#define P2PPS_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 2, 1, __Value) +#define P2PPS_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 2, 1, __Value) +#define P2PPS_GET_NOA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 3, 1, __Value) +#define P2PPS_SET_NOA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 3, 1, __Value) +#define P2PPS_GET_NOA_SEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 4, 1, __Value) +#define P2PPS_SET_NOA_SEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 4, 1, __Value) +#define P2PPS_GET_ALLSTASLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 5, 1, __Value) +#define P2PPS_SET_ALLSTASLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 5, 1, __Value) +#define P2PPS_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 6, 1, __Value) +#define P2PPS_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 6, 1, __Value) +#define P2PPS_GET_P2P_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define P2PPS_SET_P2P_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define P2PPS_GET_P2P_GROUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define P2PPS_SET_P2P_GROUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define P2PPS_GET_P2P_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) +#define P2PPS_SET_P2P_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) +#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define P2PPS_SET_CTWINDOW_LENGTH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 32, __Value) +#define P2PPS_SET_NOA_DURATION_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 32, __Value) +#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 32, __Value) +#define P2PPS_SET_NOA_INTERVAL_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 32, __Value) +#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 32, __Value) +#define P2PPS_SET_NOA_START_TIME_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 32, __Value) +#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 32, __Value) +#define P2PPS_SET_NOA_COUNT_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 32, __Value) +#define BT_COEX_GET_DATA_START(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define BT_COEX_SET_DATA_START_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CTRL_GET_NAN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 2, __Value) +#define NAN_CTRL_SET_NAN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 2, __Value) +#define NAN_CTRL_GET_SUPPORT_BAND (__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND (__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 2, __Value) +#define NAN_CTRL_SET_SUPPORT_BAND _NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 2, __Value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 10, 1, __Value) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 10, 1, __Value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 11, 1, __Value) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 11, 1, __Value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 16, 8, __Value) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 16, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 24, 8, __Value) +#define NAN_CTRL_SET_CHANNEL_2G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 24, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define NAN_CTRL_SET_CHANNEL_5G_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) GET_H2C_FIELD(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) GET_H2C_FIELD(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) GET_H2C_FIELD(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X1C, 16, 16, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h new file mode 100644 index 000000000000..621cfea1a05d --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_fw_offload_h2c_nic.h @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ +#define _HAL_FWOFFLOADH2CFORMAT_H2C_C2H_NIC_H_ +#define CMD_ID_FW_OFFLOAD_H2C 0XFF +#define CMD_ID_CHANNEL_SWITCH 0XFF +#define CMD_ID_DUMP_PHYSICAL_EFUSE 0XFF +#define CMD_ID_UPDATE_BEACON_PARSING_INFO 0XFF +#define CMD_ID_CFG_PARAMETER 0XFF +#define CMD_ID_UPDATE_DATAPACK 0XFF +#define CMD_ID_RUN_DATAPACK 0XFF +#define CMD_ID_DOWNLOAD_FLASH 0XFF +#define CMD_ID_UPDATE_PACKET 0XFF +#define CMD_ID_GENERAL_INFO 0XFF +#define CMD_ID_IQK 0XFF +#define CMD_ID_POWER_TRACKING 0XFF +#define CMD_ID_PSD 0XFF +#define CMD_ID_P2PPS 0XFF +#define CMD_ID_BT_COEX 0XFF +#define CMD_ID_NAN_CTRL 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_0 0XFF +#define CMD_ID_NAN_CHANNEL_PLAN_1 0XFF +#define CATEGORY_H2C_CMD_HEADER 0X00 +#define CATEGORY_FW_OFFLOAD_H2C 0X01 +#define CATEGORY_CHANNEL_SWITCH 0X01 +#define CATEGORY_DUMP_PHYSICAL_EFUSE 0X01 +#define CATEGORY_UPDATE_BEACON_PARSING_INFO 0X01 +#define CATEGORY_CFG_PARAMETER 0X01 +#define CATEGORY_UPDATE_DATAPACK 0X01 +#define CATEGORY_RUN_DATAPACK 0X01 +#define CATEGORY_DOWNLOAD_FLASH 0X01 +#define CATEGORY_UPDATE_PACKET 0X01 +#define CATEGORY_GENERAL_INFO 0X01 +#define CATEGORY_IQK 0X01 +#define CATEGORY_POWER_TRACKING 0X01 +#define CATEGORY_PSD 0X01 +#define CATEGORY_P2PPS 0X01 +#define CATEGORY_BT_COEX 0X01 +#define CATEGORY_NAN_CTRL 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_0 0X01 +#define CATEGORY_NAN_CHANNEL_PLAN_1 0X01 +#define SUB_CMD_ID_CHANNEL_SWITCH 0X02 +#define SUB_CMD_ID_DUMP_PHYSICAL_EFUSE 0X03 +#define SUB_CMD_ID_UPDATE_BEACON_PARSING_INFO 0X05 +#define SUB_CMD_ID_CFG_PARAMETER 0X08 +#define SUB_CMD_ID_UPDATE_DATAPACK 0X09 +#define SUB_CMD_ID_RUN_DATAPACK 0X0A +#define SUB_CMD_ID_DOWNLOAD_FLASH 0X0B +#define SUB_CMD_ID_UPDATE_PACKET 0X0C +#define SUB_CMD_ID_GENERAL_INFO 0X0D +#define SUB_CMD_ID_IQK 0X0E +#define SUB_CMD_ID_POWER_TRACKING 0X0F +#define SUB_CMD_ID_PSD 0X10 +#define SUB_CMD_ID_P2PPS 0X24 +#define SUB_CMD_ID_BT_COEX 0X60 +#define SUB_CMD_ID_NAN_CTRL 0XB2 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_0 0XB4 +#define SUB_CMD_ID_NAN_CHANNEL_PLAN_1 0XB5 +#define H2C_CMD_HEADER_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7) +#define H2C_CMD_HEADER_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value) +#define H2C_CMD_HEADER_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1) +#define H2C_CMD_HEADER_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value) +#define H2C_CMD_HEADER_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16) +#define H2C_CMD_HEADER_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value) +#define H2C_CMD_HEADER_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16) +#define H2C_CMD_HEADER_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value) +#define FW_OFFLOAD_H2C_GET_CATEGORY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 7) +#define FW_OFFLOAD_H2C_SET_CATEGORY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 7, __Value) +#define FW_OFFLOAD_H2C_GET_ACK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 7, 1) +#define FW_OFFLOAD_H2C_SET_ACK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 7, 1, __Value) +#define FW_OFFLOAD_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define FW_OFFLOAD_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define FW_OFFLOAD_H2C_GET_SUB_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16) +#define FW_OFFLOAD_H2C_SET_SUB_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value) +#define FW_OFFLOAD_H2C_GET_TOTAL_LEN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 16) +#define FW_OFFLOAD_H2C_SET_TOTAL_LEN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 16, __Value) +#define FW_OFFLOAD_H2C_GET_SEQ_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 16) +#define FW_OFFLOAD_H2C_SET_SEQ_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 16, __Value) +#define CHANNEL_SWITCH_GET_SWITCH_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) +#define CHANNEL_SWITCH_SET_SWITCH_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) +#define CHANNEL_SWITCH_GET_DEST_CH_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) +#define CHANNEL_SWITCH_SET_DEST_CH_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) +#define CHANNEL_SWITCH_GET_ABSOLUTE_TIME(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) +#define CHANNEL_SWITCH_SET_ABSOLUTE_TIME(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) +#define CHANNEL_SWITCH_GET_PERIODIC_OPTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 2) +#define CHANNEL_SWITCH_SET_PERIODIC_OPTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 2, __Value) +#define CHANNEL_SWITCH_GET_CHANNEL_INFO_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define CHANNEL_SWITCH_SET_CHANNEL_INFO_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define CHANNEL_SWITCH_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define CHANNEL_SWITCH_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define CHANNEL_SWITCH_GET_PRI_CH_IDX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 4) +#define CHANNEL_SWITCH_SET_PRI_CH_IDX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 4, __Value) +#define CHANNEL_SWITCH_GET_DEST_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 28, 4) +#define CHANNEL_SWITCH_SET_DEST_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 28, 4, __Value) +#define CHANNEL_SWITCH_GET_DEST_CH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) +#define CHANNEL_SWITCH_SET_DEST_CH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) +#define CHANNEL_SWITCH_GET_NORMAL_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8) +#define CHANNEL_SWITCH_SET_NORMAL_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value) +#define CHANNEL_SWITCH_GET_SLOW_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8) +#define CHANNEL_SWITCH_SET_SLOW_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value) +#define CHANNEL_SWITCH_GET_NORMAL_CYCLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 24, 8) +#define CHANNEL_SWITCH_SET_NORMAL_CYCLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 24, 8, __Value) +#define CHANNEL_SWITCH_GET_TSF_HIGH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) +#define CHANNEL_SWITCH_SET_TSF_HIGH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) +#define CHANNEL_SWITCH_GET_TSF_LOW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) +#define CHANNEL_SWITCH_SET_TSF_LOW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) +#define CHANNEL_SWITCH_GET_CHANNEL_INFO_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 16) +#define CHANNEL_SWITCH_SET_CHANNEL_INFO_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 16, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) +#define UPDATE_BEACON_PARSING_INFO_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_SIZE_TH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_SIZE_TH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 4, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 12, 4) +#define UPDATE_BEACON_PARSING_INFO_SET_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 12, 4, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value) +#define UPDATE_BEACON_PARSING_INFO_GET_IE_ID_BMP_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32) +#define UPDATE_BEACON_PARSING_INFO_SET_IE_ID_BMP_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value) +#define CFG_PARAMETER_GET_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) +#define CFG_PARAMETER_SET_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) +#define CFG_PARAMETER_GET_INIT_CASE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 1) +#define CFG_PARAMETER_SET_INIT_CASE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 1, __Value) +#define CFG_PARAMETER_GET_PHY_PARAMETER_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) +#define CFG_PARAMETER_SET_PHY_PARAMETER_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) +#define UPDATE_DATAPACK_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) +#define UPDATE_DATAPACK_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) +#define UPDATE_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define UPDATE_DATAPACK_GET_DATAPACK_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) +#define UPDATE_DATAPACK_GET_DATAPACK_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) +#define UPDATE_DATAPACK_SET_DATAPACK_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) +#define UPDATE_DATAPACK_GET_END_SEGMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 1) +#define UPDATE_DATAPACK_SET_END_SEGMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 1, __Value) +#define RUN_DATAPACK_GET_DATAPACK_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define RUN_DATAPACK_SET_DATAPACK_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define DOWNLOAD_FLASH_GET_SPI_CMD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define DOWNLOAD_FLASH_SET_SPI_CMD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define DOWNLOAD_FLASH_GET_LOCATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 16) +#define DOWNLOAD_FLASH_SET_LOCATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 16, __Value) +#define DOWNLOAD_FLASH_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 32) +#define DOWNLOAD_FLASH_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 32, __Value) +#define DOWNLOAD_FLASH_GET_START_ADDR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) +#define DOWNLOAD_FLASH_SET_START_ADDR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) +#define UPDATE_PACKET_GET_SIZE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) +#define UPDATE_PACKET_SET_SIZE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) +#define UPDATE_PACKET_GET_PACKET_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define UPDATE_PACKET_SET_PACKET_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define UPDATE_PACKET_GET_PACKET_LOC(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) +#define UPDATE_PACKET_SET_PACKET_LOC(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) +#define GENERAL_INFO_GET_REF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define GENERAL_INFO_SET_REF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define GENERAL_INFO_GET_RF_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 9) +#define GENERAL_INFO_SET_RF_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 9, __Value) +#define GENERAL_INFO_GET_FW_TX_BOUNDARY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define GENERAL_INFO_SET_FW_TX_BOUNDARY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define IQK_GET_CLEAR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) +#define IQK_SET_CLEAR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) +#define IQK_GET_SEGMENT_IQK(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) +#define IQK_SET_SEGMENT_IQK(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) +#define POWER_TRACKING_SET_ENABLE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) +#define POWER_TRACKING_SET_ENABLE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) +#define POWER_TRACKING_SET_ENABLE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) +#define POWER_TRACKING_GET_ENABLE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1) +#define POWER_TRACKING_SET_ENABLE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value) +#define POWER_TRACKING_GET_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 3) +#define POWER_TRACKING_SET_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 3, __Value) +#define POWER_TRACKING_GET_BBSWING_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define POWER_TRACKING_SET_BBSWING_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_A(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_A(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_B(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_B(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 16, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_C(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_C(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 8, __Value) +#define POWER_TRACKING_GET_TX_PWR_INDEX_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) +#define POWER_TRACKING_SET_TX_PWR_INDEX_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) +#define POWER_TRACKING_GET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) +#define POWER_TRACKING_SET_PWR_TRACKING_OFFSET_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) +#define POWER_TRACKING_GET_TSSI_VALUE_D(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 16, 8) +#define POWER_TRACKING_SET_TSSI_VALUE_D(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 16, 8, __Value) +#define PSD_GET_START_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 16) +#define PSD_SET_START_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 16, __Value) +#define PSD_GET_END_PSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 16) +#define PSD_SET_END_PSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 16, __Value) +#define P2PPS_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 1) +#define P2PPS_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 1, __Value) +#define P2PPS_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 1, 1) +#define P2PPS_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 1, 1, __Value) +#define P2PPS_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 2, 1) +#define P2PPS_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 2, 1, __Value) +#define P2PPS_GET_NOA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 3, 1) +#define P2PPS_SET_NOA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 3, 1, __Value) +#define P2PPS_GET_NOA_SEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 4, 1) +#define P2PPS_SET_NOA_SEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 4, 1, __Value) +#define P2PPS_GET_ALLSTASLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 5, 1) +#define P2PPS_SET_ALLSTASLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 5, 1, __Value) +#define P2PPS_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 6, 1) +#define P2PPS_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 6, 1, __Value) +#define P2PPS_GET_P2P_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define P2PPS_SET_P2P_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define P2PPS_GET_P2P_GROUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define P2PPS_SET_P2P_GROUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define P2PPS_GET_P2P_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) +#define P2PPS_SET_P2P_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) +#define P2PPS_GET_CTWINDOW_LENGTH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) +#define P2PPS_SET_CTWINDOW_LENGTH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) +#define P2PPS_GET_NOA_DURATION_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 32) +#define P2PPS_SET_NOA_DURATION_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 32, __Value) +#define P2PPS_GET_NOA_INTERVAL_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 32) +#define P2PPS_SET_NOA_INTERVAL_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 32, __Value) +#define P2PPS_GET_NOA_START_TIME_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 32) +#define P2PPS_SET_NOA_START_TIME_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 32, __Value) +#define P2PPS_GET_NOA_COUNT_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 32) +#define P2PPS_SET_NOA_COUNT_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 32, __Value) +#define BT_COEX_GET_DATA_START(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define BT_COEX_SET_DATA_START(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CTRL_GET_NAN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 2) +#define NAN_CTRL_SET_NAN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 2, __Value) +#define NAN_CTRL_GET_SUPPORT_BAND (__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 2) +#define NAN_CTRL_SET_SUPPORT_BAND (__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 2, __Value) +#define NAN_CTRL_GET_DISABLE_2G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 10, 1) +#define NAN_CTRL_SET_DISABLE_2G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 10, 1, __Value) +#define NAN_CTRL_GET_DISABLE_5G_DISC_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 11, 1) +#define NAN_CTRL_SET_DISABLE_5G_DISC_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 11, 1, __Value) +#define NAN_CTRL_GET_BCN_RSVD_PAGE_OFFSET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 16, 8) +#define NAN_CTRL_SET_BCN_RSVD_PAGE_OFFSET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 16, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_2G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 24, 8) +#define NAN_CTRL_SET_CHANNEL_2G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 24, 8, __Value) +#define NAN_CTRL_GET_CHANNEL_5G(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 8) +#define NAN_CTRL_SET_CHANNEL_5G(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_CHANNEL_NUMBER_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_0_SET_CHANNEL_NUMBER_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_UNPAUSE_MACID_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_0_SET_UNPAUSE_MACID_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_0_GET_START_TIME_SLOT_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_0_SET_START_TIME_SLOT_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_0_GET_DURATION_2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_0_SET_DURATION_2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X08, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X08, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X0C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X0C, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X10, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X10, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X14, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X14, 16, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_CHANNEL_NUMBER_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 0, 8) +#define NAN_CHANNEL_PLAN_1_SET_CHANNEL_NUMBER_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 0, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_UNPAUSE_MACID_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X18, 8, 8) +#define NAN_CHANNEL_PLAN_1_SET_UNPAUSE_MACID_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X18, 8, 8, __Value) +#define NAN_CHANNEL_PLAN_1_GET_START_TIME_SLOT_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 0, 16) +#define NAN_CHANNEL_PLAN_1_SET_START_TIME_SLOT_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 0, 16, __Value) +#define NAN_CHANNEL_PLAN_1_GET_DURATION_5(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X1C, 16, 16) +#define NAN_CHANNEL_PLAN_1_SET_DURATION_5(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X1C, 16, 16, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h new file mode 100644 index 000000000000..46ffe6340880 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_h2c_extra_info_ap.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ +#define _HAL_H2CEXTRAINFO_H2C_C2H_AP_H_ +#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8) +#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value) +#define PHY_PARAMETER_INFO_SET_LENGTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value) +#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 7) +#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 7, __Value) +#define PHY_PARAMETER_INFO_SET_IO_CMD_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 7, __Value) +#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 15, 1) +#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 15, 1, __Value) +#define PHY_PARAMETER_INFO_SET_MSK_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 15, 1, __Value) +#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_SET_RF_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16) +#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value) +#define PHY_PARAMETER_INFO_SET_IO_ADDR_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value) +#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 16) +#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 16, __Value) +#define PHY_PARAMETER_INFO_SET_DELAY_VALUE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 16, __Value) +#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 8) +#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 8, __Value) +#define PHY_PARAMETER_INFO_SET_RF_PATH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 8, __Value) +#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X04, 0, 32) +#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X04, 0, 32, __Value) +#define PHY_PARAMETER_INFO_SET_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X04, 0, 32, __Value) +#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X08, 0, 32) +#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X08, 0, 32, __Value) +#define PHY_PARAMETER_INFO_SET_MASK_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X08, 0, 32, __Value) +#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 8) +#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 8, __Value) +#define CHANNEL_INFO_SET_CHANNEL_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 8, __Value) +#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 4) +#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 4, __Value) +#define CHANNEL_INFO_SET_PRI_CH_IDX_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 4, __Value) +#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 12, 4) +#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 12, 4, __Value) +#define CHANNEL_INFO_SET_BANDWIDTH_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 12, 4, __Value) +#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 8) +#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define CHANNEL_INFO_SET_TIMEOUT_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 8, __Value) +#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 24, 7) +#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 24, 7, __Value) +#define CHANNEL_INFO_SET_ACTION_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 24, 7, __Value) +#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 31, 1) +#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 31, 1, __Value) +#define CHANNEL_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 31, 1, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 0, 7) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 0, 7, __Value) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 0, 7, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 7, 1) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 7, 1, __Value) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 7, 1, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 8, 8) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 8, 8, __Value) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 8, 8, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) GET_C2H_FIELD(__pExtraInfo + 0X00, 16, 1) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_C2H_FIELD_CLR(__pExtraInfo + 0X00, 16, 1, __Value) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA_NO_CLR(__pExtraInfo, __Value) SET_C2H_FIELD_NO_CLR(__pExtraInfo + 0X00, 16, 1, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h new file mode 100644 index 000000000000..5a0e3ae03d05 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_h2c_extra_info_nic.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ +#define _HAL_H2CEXTRAINFO_H2C_C2H_NIC_H_ +#define PHY_PARAMETER_INFO_GET_LENGTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8) +#define PHY_PARAMETER_INFO_SET_LENGTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value) +#define PHY_PARAMETER_INFO_GET_IO_CMD(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 7) +#define PHY_PARAMETER_INFO_SET_IO_CMD(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 7, __Value) +#define PHY_PARAMETER_INFO_GET_MSK_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 15, 1) +#define PHY_PARAMETER_INFO_SET_MSK_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 15, 1, __Value) +#define PHY_PARAMETER_INFO_GET_LLT_PG_BNDY(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_LLT_PG_BNDY(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_EFUSE_RSVDPAGE_LOC(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_EFUSE_RSVDPAGE_LOC(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_EFUSE_PATCH_EN(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_EFUSE_PATCH_EN(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_RF_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) +#define PHY_PARAMETER_INFO_SET_RF_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) +#define PHY_PARAMETER_INFO_GET_IO_ADDR(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16) +#define PHY_PARAMETER_INFO_SET_IO_ADDR(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value) +#define PHY_PARAMETER_INFO_GET_DELAY_VALUE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 16) +#define PHY_PARAMETER_INFO_SET_DELAY_VALUE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 16, __Value) +#define PHY_PARAMETER_INFO_GET_RF_PATH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 8) +#define PHY_PARAMETER_INFO_SET_RF_PATH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 8, __Value) +#define PHY_PARAMETER_INFO_GET_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X04, 0, 32) +#define PHY_PARAMETER_INFO_SET_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X04, 0, 32, __Value) +#define PHY_PARAMETER_INFO_GET_MASK(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X08, 0, 32) +#define PHY_PARAMETER_INFO_SET_MASK(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X08, 0, 32, __Value) +#define CHANNEL_INFO_GET_CHANNEL(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 8) +#define CHANNEL_INFO_SET_CHANNEL(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 8, __Value) +#define CHANNEL_INFO_GET_PRI_CH_IDX(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 4) +#define CHANNEL_INFO_SET_PRI_CH_IDX(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 4, __Value) +#define CHANNEL_INFO_GET_BANDWIDTH(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 12, 4) +#define CHANNEL_INFO_SET_BANDWIDTH(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 12, 4, __Value) +#define CHANNEL_INFO_GET_TIMEOUT(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 8) +#define CHANNEL_INFO_SET_TIMEOUT(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 8, __Value) +#define CHANNEL_INFO_GET_ACTION_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 24, 7) +#define CHANNEL_INFO_SET_ACTION_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 24, 7, __Value) +#define CHANNEL_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 31, 1) +#define CHANNEL_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 31, 1, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_ID(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 0, 7) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_ID(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 0, 7, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 7, 1) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 7, 1, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_SIZE(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 8, 8) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_SIZE(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 8, 8, __Value) +#define CH_EXTRA_INFO_GET_CH_EXTRA_INFO_DATA(__pExtraInfo) LE_BITS_TO_4BYTE(__pExtraInfo + 0X00, 16, 1) +#define CH_EXTRA_INFO_SET_CH_EXTRA_INFO_DATA(__pExtraInfo, __Value) SET_BITS_TO_LE_4BYTE(__pExtraInfo + 0X00, 16, 1, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h new file mode 100644 index 000000000000..30124c6615ed --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_intf_phy_cmd.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef HALMAC_INTF_PHY_CMD +#define HALMAC_INTF_PHY_CMD + +/* Cut mask */ +typedef enum _HALMAC_INTF_PHY_CUT { + HALMAC_INTF_PHY_CUT_TESTCHIP = BIT(0), + HALMAC_INTF_PHY_CUT_A = BIT(1), + HALMAC_INTF_PHY_CUT_B = BIT(2), + HALMAC_INTF_PHY_CUT_C = BIT(3), + HALMAC_INTF_PHY_CUT_D = BIT(4), + HALMAC_INTF_PHY_CUT_E = BIT(5), + HALMAC_INTF_PHY_CUT_F = BIT(6), + HALMAC_INTF_PHY_CUT_G = BIT(7), + HALMAC_INTF_PHY_CUT_ALL = 0x7FFF, +} HALMAC_INTF_PHY_CUT; + +/* IP selection */ +typedef enum _HALMAC_IP_SEL { + HALMAC_IP_SEL_INTF_PHY = 0, + HALMAC_IP_SEL_MAC = 1, + HALMAC_IP_SEL_PCIE_DBI = 2, + HALMAC_IP_SEL_UNDEFINE = 0x7FFF, +} HALMAC_IP_SEL; + +/* Platform mask */ +typedef enum _HALMAC_INTF_PHY_PLATFORM { + HALMAC_INTF_PHY_PLATFORM_ALL = 0x7FFF, +} HALMAC_INTF_PHY_PLATFORM; + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_module.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_module.h new file mode 100644 index 000000000000..717335c6f32a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_module.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_MODULE_H_ +#define _HALMAC_MODULE_H_ + +#define HALMAC_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) +#define HALMAC_CURRENT_VERSION HALMAC_VERSION(HALMAC_MAJOR_VER, HALMAC_PROTOTYPE_VER, HALMAC_MINOR_VER) + +#define MAX_ARG_NUM 10 + +#define TLP_TYPE_NONE 0x00000000 +#define TLP_TYPE_PU8 0x00000001 +#define TLP_TYPE_PU16 0x00000002 +#define TLP_TYPE_PU32 0x00000003 +#define TLP_TYPE_PU64 0x00000004 +#define TLP_TYPE_PS8 0x00000005 +#define TLP_TYPE_PS16 0x00000006 +#define TLP_TYPE_PS32 0x00000007 +#define TLP_TYPE_PS64 0x00000008 +#define TLP_TYPE_PVOID 0x00000009 +#define TLP_TYPE_PU8_BUFFER 0x0000000A +#define TLP_TYPE_POS_API_ENTRY 0x0000000B +#define TLP_TYPE_PHALMAC_WLAN_ADDR 0x0000000C +#define TLP_TYPE_PHALMAC_PHY_PARAMETER_INFO 0x0000000D +#define TLP_TYPE_PHALMAC_CH_INFO 0x0000000E +#define TLP_TYPE_PHALMAC_CH_SWITCH_OPTION 0x0000000F +#define TLP_TYPE_PHALMAC_GENERAL_INFO 0x00000010 +#define TLP_TYPE_PHALMAC_CMD_PROCESS_STATUS 0x00000011 +#define TLP_TYPE_PHALMAC_INTERFACE 0x00000012 +#define TLP_TYPE_PHALMAC_MAC_POWER 0x00000013 +#define TLP_TYPE_PHALMAC_RXAGG_CFG 0x00000014 +#define TLP_TYPE_PHALMAC_WIRELESS_MODE 0x00000015 +#define TLP_TYPE_PHALMAC_BW 0x00000016 +#define TLP_TYPE_PHALMAC_TRX_MODE 0x00000017 +#define TLP_TYPE_PHALMAC_EFUSE_READ_CFG 0x00000018 +#define TLP_TYPE_PHALMAC_PACKET_ID 0x00000019 +#define TLP_TYPE_PHALMAC_DRV_INFO 0x0000001A +#define TLP_TYPE_PHALMAC_FEATURE_ID 0x0000001B +#define TLP_TYPE_PHALMAC_HW_ID 0x0000001C +#define TLP_TYPE_PHALMAC_DRV_RSVD_PG_NUM 0x0000001D +#define TLP_TYPE_PHALMAC_LA_MODE 0x0000001E +#define TLP_TYPE_PHALMAC_PWR_TRACKING 0x0000001F +#define TLP_TYPE_PHALMAC_EFUSE_BANK 0x00000020 +#define TLP_TYPE_PHALMAC_IQK 0x00000021 +#define TLP_TYPE_PHALMAC_MU_BFER_INIT_PARA 0x00000022 +#define TLP_TYPE_PHALMAC_MU_BFEE_INIT_PARA 0x00000023 +#define TLP_TYPE_PHALMAC_SU_BFER_INIT_PARA 0x00000024 +#define TLP_TYPE_PHALMAC_SND_ROLE 0x00000025 +#define TLP_TYPE_PHALMAC_DATA_RATE 0x00000026 +#define TLP_TYPE_PHALMAC_CFG_MUMIMO_PARA 0x00000027 +#define TLP_TYPE_PU8_1 0x00000028 +#define TLP_TYPE_PHALMAC_PG_EFUSE_INFO 0x00000029 +#define TLP_TYPE_PU8_2 0x0000002A +#define TLP_TYPE_PHALMAC_INTF_PHY_PLATFORM 0x0000002B +#define TLP_TYPE_PHALMAC_API_REGISTRY 0x0000002C +#define TLP_TYPE_PHALMAC_DLFW_MEM 0x0000002D +#define TLP_TYPE_PHALMAC_FW_VERSION 0x0000002E +#define TLP_TYPE_PHALMAC_SIDEBAND_INT_CFG 0x0000002F +#define TLP_TYPE_PHALMAC_FIFO_SEL 0x00000030 +#define TLP_TYPE_PHALMAC_P2PPS 0x00000031 +#define TLP_TYPE_PHALMAC_RX_EXPAND_MODE 0x00000032 +#define TLP_TYPE_PHALMAC_PCIE_CFG 0x00000033 +#define TLP_TYPE_PHALMAC_SDIO_CMD53_4BYTE_MODE 0x00000034 +#define TLP_TYPE_PHALMAC_NETWORK_TYPE_SELECT 0x00000035 +#define TLP_TYPE_PHALMAC_BCN_CTRL 0x00000036 +#define TLP_TYPE_PHALMAC_SDIO_HW_INFO 0x00000037 + +typedef struct _HALMAC_TLP_STRUCT { + u32 type; + u32 length; + VOID *ptr; +} HALMAC_TLP_STRUCT, *PHALMAC_TLP_STRUCT; + +typedef struct _HALMAC_API_ARG { + HALMAC_API_ID api_id; + u32 arg_count; + u32 arg_type_seq[MAX_ARG_NUM]; +} HALMAC_API_ARG, *PHALMAC_API_ARG; + +typedef struct _HALMAC_OBJ { + u8 init; + u32 version; + PHALMAC_ADAPTER halmac_adapter; + PHALMAC_API halmac_api_entry; +} HALMAC_OBJ, *PHALMAC_OBJ; + +HALMAC_RET_STATUS +halmac_initialize_obj( + IN struct _HALMAC_OBJ *halmac_obj, + INOUT PHALMAC_TLP_STRUCT ptlp, + IN u32 tlpCount +); + +HALMAC_RET_STATUS +halmac_deinitialize_obj( + IN struct _HALMAC_OBJ *halmac_obj, + INOUT PHALMAC_TLP_STRUCT ptlp, + IN u32 tlpCount +); + +HALMAC_RET_STATUS +halmac_set_information( + IN struct _HALMAC_OBJ *halmac_obj, + IN HALMAC_API_ID api_id, + INOUT PHALMAC_TLP_STRUCT ptlp, + IN u32 tlpCount +); + +HALMAC_RET_STATUS +halmac_get_information( + IN struct _HALMAC_OBJ *halmac_obj, + IN HALMAC_API_ID api_id, + INOUT PHALMAC_TLP_STRUCT ptlp, + IN u32 tlpCount +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h new file mode 100644 index 000000000000..05f1a115ebf3 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_c2h_ap.h @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ +#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_AP_H_ +#define CMD_ID_C2H 0X00 +#define CMD_ID_DBG 0X00 +#define CMD_ID_C2H_LB 0X01 +#define CMD_ID_C2H_SND_TXBF 0X02 +#define CMD_ID_C2H_CCX_RPT 0X03 +#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 +#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 +#define CMD_ID_C2H_RA_RPT 0X0C +#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D +#define CMD_ID_C2H_RA_PARA_RPT 0X0E +#define CMD_ID_C2H_CUR_CHANNEL 0X10 +#define CMD_ID_C2H_GPIO_WAKEUP 0X14 +#define C2H_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define DBG_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define DBG_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define DBG_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define DBG_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define DBG_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define DBG_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define DBG_GET_DBG_STR1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) +#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) +#define DBG_SET_DBG_STR1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) +#define DBG_GET_DBG_STR2(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) +#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) +#define DBG_SET_DBG_STR2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) +#define DBG_GET_DBG_STR3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define DBG_SET_DBG_STR3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define DBG_GET_DBG_STR4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define DBG_SET_DBG_STR4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define DBG_GET_DBG_STR5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) +#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) +#define DBG_SET_DBG_STR5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) +#define DBG_GET_DBG_STR6(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) +#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) +#define DBG_SET_DBG_STR6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) +#define DBG_GET_DBG_STR7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) +#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) +#define DBG_SET_DBG_STR7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) +#define DBG_GET_DBG_STR8(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) +#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) +#define DBG_SET_DBG_STR8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) +#define DBG_GET_DBG_STR9(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) +#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) +#define DBG_SET_DBG_STR9_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) +#define DBG_GET_DBG_STR10(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8) +#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value) +#define DBG_SET_DBG_STR10_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value) +#define DBG_GET_DBG_STR11(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8) +#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value) +#define DBG_SET_DBG_STR11_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value) +#define DBG_GET_DBG_STR12(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8) +#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value) +#define DBG_SET_DBG_STR12_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value) +#define DBG_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define DBG_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define DBG_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define DBG_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define DBG_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define DBG_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_LB_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_LB_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_LB_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_LB_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_LB_GET_PAYLOAD1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 16) +#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 16, __Value) +#define C2H_LB_SET_PAYLOAD1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 16, __Value) +#define C2H_LB_GET_PAYLOAD2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 32) +#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 32, __Value) +#define C2H_LB_SET_PAYLOAD2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 32, __Value) +#define C2H_LB_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_LB_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_LB_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_LB_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_LB_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_SND_TXBF_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_SND_TXBF_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_SND_TXBF_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 1) +#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 1, __Value) +#define C2H_SND_TXBF_SET_SND_RESULT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 1, __Value) +#define C2H_SND_TXBF_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_SND_TXBF_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_SND_TXBF_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_CCX_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_CCX_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_CCX_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_CCX_RPT_GET_QSEL(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 5) +#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 5, __Value) +#define C2H_CCX_RPT_SET_QSEL_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 5, __Value) +#define C2H_CCX_RPT_GET_BMC(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 21, 1) +#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 21, 1, __Value) +#define C2H_CCX_RPT_SET_BMC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 21, 1, __Value) +#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 22, 1) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 22, 1, __Value) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 22, 1, __Value) +#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 23, 1) +#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 23, 1, __Value) +#define C2H_CCX_RPT_SET_RETRY_OVER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 23, 1, __Value) +#define C2H_CCX_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) +#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_CCX_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 6) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 6, __Value) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 6, __Value) +#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_CCX_RPT_SET_QUEUE7_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) +#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_CCX_RPT_SET_QUEUE15_8_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) +#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_CCX_RPT_SET_SW_DEFINE_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 4) +#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 4, __Value) +#define C2H_CCX_RPT_SET_SW_DEFINE_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 4, __Value) +#define C2H_CCX_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_CCX_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_CCX_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 7) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 7, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 7, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_RA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_RA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_RA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_RA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_RA_RPT_GET_RATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) +#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_RA_RPT_SET_RATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_RA_RPT_GET_MACID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) +#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_RA_RPT_SET_MACID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 1) +#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 1, __Value) +#define C2H_RA_RPT_SET_USE_LDPC_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 1, __Value) +#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 1, 1) +#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 1, 1, __Value) +#define C2H_RA_RPT_SET_USE_TXBF_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 1, 1, __Value) +#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_RA_RPT_SET_COLLISION_STATE_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_RA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_RA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_RA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_RA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA0_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA1_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA2_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA3_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) GET_C2H_FIELD(__pC2H + 0X04, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA4_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X04, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA5_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA6_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) GET_C2H_FIELD(__pC2H + 0X08, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X08, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_DATA7_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X08, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_RA_PARA_RPT_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_RA_PARA_RPT_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_RA_PARA_RPT_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_RA_PARA_RPT_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_CUR_CHANNEL_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_CUR_CHANNEL_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 16, 8) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 16, 8, __Value) +#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_CUR_CHANNEL_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_CUR_CHANNEL_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 0, 8) +#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_GPIO_WAKEUP_SET_CMD_ID_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 0, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) GET_C2H_FIELD(__pC2H + 0X00, 8, 8) +#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_GPIO_WAKEUP_SET_SEQ_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X00, 8, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 16, 8) +#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_GPIO_WAKEUP_SET_LEN_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) GET_C2H_FIELD(__pC2H + 0X0C, 24, 8) +#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_C2H_FIELD_CLR(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_GPIO_WAKEUP_SET_TRIGGER_NO_CLR(__pC2H, __Value) SET_C2H_FIELD_NO_CLR(__pC2H + 0X0C, 24, 8, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h new file mode 100644 index 000000000000..11933e4c5299 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_c2h_nic.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ +#define _HAL_ORIGINALC2HFORMAT_H2C_C2H_NIC_H_ +#define CMD_ID_C2H 0X00 +#define CMD_ID_DBG 0X00 +#define CMD_ID_C2H_LB 0X01 +#define CMD_ID_C2H_SND_TXBF 0X02 +#define CMD_ID_C2H_CCX_RPT 0X03 +#define CMD_ID_C2H_AP_REQ_TXRPT 0X04 +#define CMD_ID_C2H_INITIAL_RATE_COLLECTION 0X05 +#define CMD_ID_C2H_RA_RPT 0X0C +#define CMD_ID_C2H_SPECIAL_STATISTICS 0X0D +#define CMD_ID_C2H_RA_PARA_RPT 0X0E +#define CMD_ID_C2H_CUR_CHANNEL 0X10 +#define CMD_ID_C2H_GPIO_WAKEUP 0X14 +#define C2H_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define DBG_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define DBG_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define DBG_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define DBG_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define DBG_GET_DBG_STR1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) +#define DBG_SET_DBG_STR1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) +#define DBG_GET_DBG_STR2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) +#define DBG_SET_DBG_STR2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) +#define DBG_GET_DBG_STR3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define DBG_SET_DBG_STR3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define DBG_GET_DBG_STR4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define DBG_SET_DBG_STR4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define DBG_GET_DBG_STR5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) +#define DBG_SET_DBG_STR5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) +#define DBG_GET_DBG_STR6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) +#define DBG_SET_DBG_STR6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) +#define DBG_GET_DBG_STR7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) +#define DBG_SET_DBG_STR7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) +#define DBG_GET_DBG_STR8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) +#define DBG_SET_DBG_STR8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) +#define DBG_GET_DBG_STR9(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) +#define DBG_SET_DBG_STR9(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) +#define DBG_GET_DBG_STR10(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8) +#define DBG_SET_DBG_STR10(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value) +#define DBG_GET_DBG_STR11(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8) +#define DBG_SET_DBG_STR11(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value) +#define DBG_GET_DBG_STR12(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8) +#define DBG_SET_DBG_STR12(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value) +#define DBG_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define DBG_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define DBG_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define DBG_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_LB_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_LB_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_LB_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_LB_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_LB_GET_PAYLOAD1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 16) +#define C2H_LB_SET_PAYLOAD1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 16, __Value) +#define C2H_LB_GET_PAYLOAD2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 32) +#define C2H_LB_SET_PAYLOAD2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 32, __Value) +#define C2H_LB_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_LB_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_LB_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_LB_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_SND_TXBF_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_SND_TXBF_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_SND_TXBF_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_SND_TXBF_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_SND_TXBF_GET_SND_RESULT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 1) +#define C2H_SND_TXBF_SET_SND_RESULT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 1, __Value) +#define C2H_SND_TXBF_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_SND_TXBF_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_SND_TXBF_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_SND_TXBF_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_CCX_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_CCX_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_CCX_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_CCX_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_CCX_RPT_GET_QSEL(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 5) +#define C2H_CCX_RPT_SET_QSEL(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 5, __Value) +#define C2H_CCX_RPT_GET_BMC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 21, 1) +#define C2H_CCX_RPT_SET_BMC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 21, 1, __Value) +#define C2H_CCX_RPT_GET_LIFE_TIME_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 22, 1) +#define C2H_CCX_RPT_SET_LIFE_TIME_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 22, 1, __Value) +#define C2H_CCX_RPT_GET_RETRY_OVER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 23, 1) +#define C2H_CCX_RPT_SET_RETRY_OVER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 23, 1, __Value) +#define C2H_CCX_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) +#define C2H_CCX_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) +#define C2H_CCX_RPT_GET_DATA_RETRY_CNT(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 6) +#define C2H_CCX_RPT_SET_DATA_RETRY_CNT(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 6, __Value) +#define C2H_CCX_RPT_GET_QUEUE7_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define C2H_CCX_RPT_SET_QUEUE7_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define C2H_CCX_RPT_GET_QUEUE15_8(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) +#define C2H_CCX_RPT_SET_QUEUE15_8(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) +#define C2H_CCX_RPT_GET_FINAL_DATA_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) +#define C2H_CCX_RPT_SET_FINAL_DATA_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) +#define C2H_CCX_RPT_GET_SW_DEFINE_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) +#define C2H_CCX_RPT_SET_SW_DEFINE_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) +#define C2H_CCX_RPT_GET_SW_DEFINE_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 4) +#define C2H_CCX_RPT_SET_SW_DEFINE_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 4, __Value) +#define C2H_CCX_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_CCX_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_CCX_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_CCX_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_STA1_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_STA1_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL1_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL1_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_STA2_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_STA2_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_OK2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_OK2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 24, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TX_FAIL2_1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 0, 8) +#define C2H_AP_REQ_TXRPT_SET_TX_FAIL2_1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 0, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 8, 8) +#define C2H_AP_REQ_TXRPT_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 8, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_AP_REQ_TXRPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_AP_REQ_TXRPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_AP_REQ_TXRPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRYING_BITMAP(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 7) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRYING_BITMAP(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 7, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_INITIAL_RATE7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_INITIAL_RATE7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_INITIAL_RATE_COLLECTION_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_INITIAL_RATE_COLLECTION_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_RA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_RA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_RA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_RA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_RA_RPT_GET_RATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) +#define C2H_RA_RPT_SET_RATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) +#define C2H_RA_RPT_GET_MACID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) +#define C2H_RA_RPT_SET_MACID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) +#define C2H_RA_RPT_GET_USE_LDPC(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 1) +#define C2H_RA_RPT_SET_USE_LDPC(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 1, __Value) +#define C2H_RA_RPT_GET_USE_TXBF(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 1, 1) +#define C2H_RA_RPT_SET_USE_TXBF(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 1, 1, __Value) +#define C2H_RA_RPT_GET_COLLISION_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define C2H_RA_RPT_SET_COLLISION_STATE(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define C2H_RA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_RA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_RA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_RA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_STATISTICS_IDX(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_STATISTICS_IDX(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA0(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA0(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA1(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA1(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA2(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA2(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA3(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA3(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA4(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA4(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X04, 24, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA5(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 0, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA5(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 0, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA6(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 8, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA6(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 8, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_DATA7(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X08, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_DATA7(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X08, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_SPECIAL_STATISTICS_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_SPECIAL_STATISTICS_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_SPECIAL_STATISTICS_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_RA_PARA_RPT_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_RA_PARA_RPT_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_RA_PARA_RPT_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_RA_PARA_RPT_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_RA_PARA_RPT_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_RA_PARA_RPT_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_RA_PARA_RPT_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_RA_PARA_RPT_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_CUR_CHANNEL_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_CUR_CHANNEL_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_CUR_CHANNEL_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_CUR_CHANNEL_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_CUR_CHANNEL_GET_CHANNEL_NUM(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 16, 8) +#define C2H_CUR_CHANNEL_SET_CHANNEL_NUM(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 16, 8, __Value) +#define C2H_CUR_CHANNEL_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_CUR_CHANNEL_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_CUR_CHANNEL_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_CUR_CHANNEL_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_CMD_ID(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 0, 8) +#define C2H_GPIO_WAKEUP_SET_CMD_ID(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 0, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_SEQ(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X00, 8, 8) +#define C2H_GPIO_WAKEUP_SET_SEQ(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X00, 8, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_LEN(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 16, 8) +#define C2H_GPIO_WAKEUP_SET_LEN(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 16, 8, __Value) +#define C2H_GPIO_WAKEUP_GET_TRIGGER(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X0C, 24, 8) +#define C2H_GPIO_WAKEUP_SET_TRIGGER(__pC2H, __Value) SET_BITS_TO_LE_4BYTE(__pC2H + 0X0C, 24, 8, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h new file mode 100644 index 000000000000..50adb008b879 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_h2c_ap.h @@ -0,0 +1,879 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ +#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_AP_H_ +#define CMD_ID_ORIGINAL_H2C 0X00 +#define CMD_ID_H2C2H_LB 0X0 +#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 +#define CMD_ID_RSVD_PAGE 0X0 +#define CMD_ID_MEDIA_STATUS_RPT 0X01 +#define CMD_ID_KEEP_ALIVE 0X03 +#define CMD_ID_DISCONNECT_DECISION 0X04 +#define CMD_ID_AP_OFFLOAD 0X08 +#define CMD_ID_BCN_RSVDPAGE 0X09 +#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A +#define CMD_ID_SET_PWR_MODE 0X00 +#define CMD_ID_PS_TUNING_PARA 0X01 +#define CMD_ID_PS_TUNING_PARA_II 0X02 +#define CMD_ID_PS_LPS_PARA 0X03 +#define CMD_ID_P2P_PS_OFFLOAD 0X04 +#define CMD_ID_PS_SCAN_EN 0X05 +#define CMD_ID_SAP_PS 0X06 +#define CMD_ID_INACTIVE_PS 0X07 +#define CMD_ID_MACID_CFG 0X00 +#define CMD_ID_TXBF 0X01 +#define CMD_ID_RSSI_SETTING 0X02 +#define CMD_ID_AP_REQ_TXRPT 0X03 +#define CMD_ID_INIT_RATE_COLLECTION 0X04 +#define CMD_ID_IQK_OFFLOAD 0X05 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 +#define CMD_ID_WWLAN 0X00 +#define CMD_ID_REMOTE_WAKE_CTRL 0X01 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 +#define CMD_ID_AOAC_RSVD_PAGE 0X03 +#define CMD_ID_AOAC_RSVD_PAGE2 0X04 +#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 +#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 +#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CLASS_ORIGINAL_H2C 0X00 +#define CLASS_H2C2H_LB 0X07 +#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04 +#define CLASS_RSVD_PAGE 0X0 +#define CLASS_MEDIA_STATUS_RPT 0X0 +#define CLASS_KEEP_ALIVE 0X0 +#define CLASS_DISCONNECT_DECISION 0X0 +#define CLASS_AP_OFFLOAD 0X0 +#define CLASS_BCN_RSVDPAGE 0X0 +#define CLASS_PROBE_RSP_RSVDPAGE 0X0 +#define CLASS_SET_PWR_MODE 0X01 +#define CLASS_PS_TUNING_PARA 0X01 +#define CLASS_PS_TUNING_PARA_II 0X01 +#define CLASS_PS_LPS_PARA 0X01 +#define CLASS_P2P_PS_OFFLOAD 0X01 +#define CLASS_PS_SCAN_EN 0X1 +#define CLASS_SAP_PS 0X1 +#define CLASS_INACTIVE_PS 0X1 +#define CLASS_MACID_CFG 0X2 +#define CLASS_TXBF 0X2 +#define CLASS_RSSI_SETTING 0X2 +#define CLASS_AP_REQ_TXRPT 0X2 +#define CLASS_INIT_RATE_COLLECTION 0X2 +#define CLASS_IQK_OFFLOAD 0X2 +#define CLASS_MACID_CFG_3SS 0X2 +#define CLASS_RA_PARA_ADJUST 0X02 +#define CLASS_WWLAN 0X4 +#define CLASS_REMOTE_WAKE_CTRL 0X4 +#define CLASS_AOAC_GLOBAL_INFO 0X04 +#define CLASS_AOAC_RSVD_PAGE 0X04 +#define CLASS_AOAC_RSVD_PAGE2 0X04 +#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 +#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 +#define CLASS_AOAC_RSVD_PAGE3 0X04 +#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define ORIGINAL_H2C_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define ORIGINAL_H2C_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define ORIGINAL_H2C_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define H2C2H_LB_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define H2C2H_LB_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define H2C2H_LB_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define H2C2H_LB_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define H2C2H_LB_GET_SEQ(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define H2C2H_LB_SET_SEQ_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define H2C2H_LB_GET_PAYLOAD1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 16) +#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 16, __Value) +#define H2C2H_LB_SET_PAYLOAD1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 16, __Value) +#define H2C2H_LB_GET_PAYLOAD2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 32) +#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 32, __Value) +#define H2C2H_LB_SET_PAYLOAD2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 32, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 17) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 17, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 17, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define RSVD_PAGE_SET_LOC_PROBE_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define RSVD_PAGE_SET_LOC_PS_POLL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define RSVD_PAGE_SET_LOC_NULL_DATA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define RSVD_PAGE_SET_LOC_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) +#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) +#define RSVD_PAGE_SET_LOC_CTS2SELF_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) +#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MEDIA_STATUS_RPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MEDIA_STATUS_RPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define MEDIA_STATUS_RPT_SET_OP_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define MEDIA_STATUS_RPT_SET_MACID_IN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define MEDIA_STATUS_RPT_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define MEDIA_STATUS_RPT_SET_MACID_END_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define KEEP_ALIVE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define KEEP_ALIVE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define KEEP_ALIVE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define KEEP_ALIVE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define KEEP_ALIVE_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define KEEP_ALIVE_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define KEEP_ALIVE_SET_PKT_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define DISCONNECT_DECISION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define DISCONNECT_DECISION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define DISCONNECT_DECISION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define DISCONNECT_DECISION_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) +#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AP_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AP_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AP_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AP_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AP_OFFLOAD_GET_ON(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define AP_OFFLOAD_SET_ON_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define AP_OFFLOAD_GET_LINKED(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define AP_OFFLOAD_SET_LINKED_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) +#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) +#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) +#define AP_OFFLOAD_SET_WAKE_FLAG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1) +#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value) +#define AP_OFFLOAD_SET_HIDDEN_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value) +#define AP_OFFLOAD_SET_HIDDEN_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value) +#define AP_OFFLOAD_SET_HIDDEN_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 19, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 19, 1, __Value) +#define AP_OFFLOAD_SET_HIDDEN_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 19, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 1, __Value) +#define AP_OFFLOAD_SET_HIDDEN_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) +#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) +#define AP_OFFLOAD_SET_DENYANY_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value) +#define AP_OFFLOAD_SET_DENYANY_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value) +#define AP_OFFLOAD_SET_DENYANY_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value) +#define AP_OFFLOAD_SET_DENYANY_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value) +#define AP_OFFLOAD_SET_DENYANY_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value) +#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) +#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) +#define AP_OFFLOAD_SET_LEN_IV_PAIR_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) +#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) +#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) +#define AP_OFFLOAD_SET_LEN_IV_GRP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) +#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define BCN_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define BCN_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define BCN_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define BCN_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define BCN_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define BCN_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define BCN_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define BCN_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PROBE_RSP_RSVDPAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define SET_PWR_MODE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define SET_PWR_MODE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define SET_PWR_MODE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define SET_PWR_MODE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define SET_PWR_MODE_GET_MODE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) +#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) +#define SET_PWR_MODE_SET_MODE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) +#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) +#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) +#define SET_PWR_MODE_SET_CLK_REQUEST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) +#define SET_PWR_MODE_GET_RLBM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4) +#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value) +#define SET_PWR_MODE_SET_RLBM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value) +#define SET_PWR_MODE_GET_SMART_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 20, 4) +#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 20, 4, __Value) +#define SET_PWR_MODE_SET_SMART_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 20, 4, __Value) +#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value) +#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 2, 1) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 2, 1, __Value) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 2, 1, __Value) +#define SET_PWR_MODE_GET_PORT_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 5, 3) +#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 5, 3, __Value) +#define SET_PWR_MODE_SET_PORT_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 5, 3, __Value) +#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define SET_PWR_MODE_SET_PWR_STATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 1) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 1, __Value) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 1, __Value) +#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 17, 1) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 17, 1, __Value) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 17, 1, __Value) +#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 18, 1) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 18, 1, __Value) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 18, 1, __Value) +#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 19, 1) +#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 19, 1, __Value) +#define SET_PWR_MODE_SET_PROTECT_BCN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 19, 1, __Value) +#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 20, 1) +#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 20, 1, __Value) +#define SET_PWR_MODE_SET_SILENCE_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 20, 1, __Value) +#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 21, 1) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 21, 1, __Value) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 21, 1, __Value) +#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 22, 1) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 22, 1, __Value) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 22, 1, __Value) +#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 1) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 1, __Value) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 1, __Value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 25, 3) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 25, 3, __Value) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 25, 3, __Value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 28, 4) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 28, 4, __Value) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 28, 4, __Value) +#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_TUNING_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) +#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) +#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 4) +#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 4, __Value) +#define PS_TUNING_PARA_SET_PS_TIME_OUT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 4, __Value) +#define PS_TUNING_PARA_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define PS_TUNING_PARA_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_II_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_TUNING_PARA_II_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 7) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 7, __Value) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 7, __Value) +#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) +#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) +#define PS_TUNING_PARA_II_SET_ADOPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) +#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define PS_LPS_PARA_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_LPS_PARA_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_LPS_PARA_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_LPS_PARA_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define PS_LPS_PARA_SET_LPS_CONTROL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define P2P_PS_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define P2P_PS_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define P2P_PS_OFFLOAD_SET_ROLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) +#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) +#define P2P_PS_OFFLOAD_SET_NOA0_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) +#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) +#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) +#define P2P_PS_OFFLOAD_SET_NOA1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) +#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) +#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) +#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) +#define P2P_PS_OFFLOAD_SET_DISCOVERY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) +#define PS_SCAN_EN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_SCAN_EN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define PS_SCAN_EN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_SCAN_EN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define PS_SCAN_EN_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define PS_SCAN_EN_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define SAP_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define SAP_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define SAP_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define SAP_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define SAP_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define SAP_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define SAP_PS_GET_EN_PS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define SAP_PS_SET_EN_PS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define SAP_PS_GET_EN_LP_RX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define SAP_PS_SET_EN_LP_RX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define SAP_PS_GET_MANUAL_32K(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) +#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) +#define SAP_PS_SET_MANUAL_32K_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) +#define SAP_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define SAP_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define INACTIVE_PS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define INACTIVE_PS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define INACTIVE_PS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define INACTIVE_PS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define INACTIVE_PS_GET_ENABLE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define INACTIVE_PS_SET_ENABLE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define INACTIVE_PS_GET_FREQUENCY(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define INACTIVE_PS_SET_FREQUENCY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define INACTIVE_PS_GET_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define INACTIVE_PS_SET_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define MACID_CFG_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 5) +#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 5, __Value) +#define MACID_CFG_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 5, __Value) +#define MACID_CFG_GET_INIT_RATE_LV(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 21, 2) +#define MACID_CFG_SET_INIT_RATE_LV(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 21, 2, __Value) +#define MACID_CFG_SET_INIT_RATE_LV_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 21, 2, __Value) +#define MACID_CFG_GET_SGI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1) +#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value) +#define MACID_CFG_SET_SGI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value) +#define MACID_CFG_GET_BW(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 2) +#define MACID_CFG_SET_BW(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 2, __Value) +#define MACID_CFG_SET_BW_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 2, __Value) +#define MACID_CFG_GET_LDPC_CAP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 26, 1) +#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 26, 1, __Value) +#define MACID_CFG_SET_LDPC_CAP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 26, 1, __Value) +#define MACID_CFG_GET_NO_UPDATE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 27, 1) +#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 27, 1, __Value) +#define MACID_CFG_SET_NO_UPDATE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 27, 1, __Value) +#define MACID_CFG_GET_WHT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 2) +#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 2, __Value) +#define MACID_CFG_SET_WHT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 2, __Value) +#define MACID_CFG_GET_DISPT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 30, 1) +#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 30, 1, __Value) +#define MACID_CFG_SET_DISPT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 30, 1, __Value) +#define MACID_CFG_GET_DISRA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 31, 1) +#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 31, 1, __Value) +#define MACID_CFG_SET_DISRA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 31, 1, __Value) +#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_SET_RATE_MASK7_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define MACID_CFG_SET_RATE_MASK15_8_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) +#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) +#define MACID_CFG_SET_RATE_MASK23_16_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) +#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) +#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) +#define MACID_CFG_SET_RATE_MASK31_24_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) +#define TXBF_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define TXBF_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define TXBF_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define TXBF_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define TXBF_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define TXBF_SET_NDPA0_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define TXBF_SET_NDPA1_HEAD_PAGE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define TXBF_GET_PERIOD_0(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define TXBF_SET_PERIOD_0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define RSSI_SETTING_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RSSI_SETTING_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RSSI_SETTING_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define RSSI_SETTING_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define RSSI_SETTING_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define RSSI_SETTING_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define RSSI_SETTING_GET_RSSI(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 7) +#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 7, __Value) +#define RSSI_SETTING_SET_RSSI_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 7, __Value) +#define RSSI_SETTING_GET_RA_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define RSSI_SETTING_SET_RA_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AP_REQ_TXRPT_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AP_REQ_TXRPT_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AP_REQ_TXRPT_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AP_REQ_TXRPT_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AP_REQ_TXRPT_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) +#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 25, 1) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 25, 1, __Value) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 25, 1, __Value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define INIT_RATE_COLLECTION_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define INIT_RATE_COLLECTION_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define INIT_RATE_COLLECTION_SET_STA1_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define INIT_RATE_COLLECTION_SET_STA2_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define INIT_RATE_COLLECTION_SET_STA3_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define INIT_RATE_COLLECTION_SET_STA4_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define INIT_RATE_COLLECTION_SET_STA5_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) +#define INIT_RATE_COLLECTION_SET_STA6_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) +#define INIT_RATE_COLLECTION_SET_STA7_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) +#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define IQK_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define IQK_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define IQK_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define IQK_OFFLOAD_SET_CHANNEL_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define IQK_OFFLOAD_GET_BWBAND(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define IQK_OFFLOAD_SET_BWBAND_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define IQK_OFFLOAD_SET_EXTPALNA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_3SS_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_3SS_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_3SS_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_3SS_GET_MACID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_3SS_SET_MACID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RA_PARA_ADJUST_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define RA_PARA_ADJUST_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define RA_PARA_ADJUST_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define RA_PARA_ADJUST_SET_MAC_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define RA_PARA_ADJUST_SET_RATE_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) +#define WWLAN_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define WWLAN_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define WWLAN_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define WWLAN_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define WWLAN_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define WWLAN_GET_FUNC_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define WWLAN_SET_FUNC_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define WWLAN_SET_PATTERM_MAT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define WWLAN_SET_MAGIC_PKT_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) +#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) +#define WWLAN_SET_UNICAST_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) +#define WWLAN_GET_ALL_PKT_DROP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) +#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) +#define WWLAN_SET_ALL_PKT_DROP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) +#define WWLAN_GET_GPIO_ACTIVE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) +#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) +#define WWLAN_SET_GPIO_ACTIVE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) +#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) +#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) +#define WWLAN_SET_REKEY_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) +#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) +#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) +#define WWLAN_SET_DEAUTH_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) +#define WWLAN_GET_GPIO_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 7) +#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 7, __Value) +#define WWLAN_SET_GPIO_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 7, __Value) +#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 23, 1) +#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 23, 1, __Value) +#define WWLAN_SET_DATAPIN_WAKEUP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 23, 1, __Value) +#define WWLAN_GET_GPIO_DURATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define WWLAN_SET_GPIO_DURATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 1) +#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 1, __Value) +#define WWLAN_SET_GPIO_PLUS_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 1, __Value) +#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 1, 7) +#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 1, 7, __Value) +#define WWLAN_SET_GPIO_PULSE_COUNT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 1, 7, __Value) +#define WWLAN_GET_DISABLE_UPHY(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 1) +#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 1, __Value) +#define WWLAN_SET_DISABLE_UPHY_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 1, __Value) +#define WWLAN_GET_HST2DEV_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 9, 1) +#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 9, 1, __Value) +#define WWLAN_SET_HST2DEV_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 9, 1, __Value) +#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 10, 1) +#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 10, 1, __Value) +#define WWLAN_SET_GPIO_DURATION_MS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 10, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define REMOTE_WAKE_CTRL_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define REMOTE_WAKE_CTRL_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 1) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 9, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 9, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_ARP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 9, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 10, 1) +#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 10, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_NDP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 10, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 11, 1) +#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 11, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_GTK_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 11, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 12, 1) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 12, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 12, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 13, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 13, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 13, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 14, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 14, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 14, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 15, 1) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 15, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 15, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 1) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 17, 1) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 17, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 17, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 18, 1) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 18, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 18, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 28, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 28, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 28, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 29, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 29, 1, __Value) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 29, 1, __Value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_GLOBAL_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_GLOBAL_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE2_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE2_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 0, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 0, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 8, 8, __Value) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 8, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 16, 8, __Value) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 16, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) GET_H2C_FIELD(__pH2C + 0X04, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X04, 24, 8, __Value) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X04, 24, 8, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 24, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 24, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE3_SET_CMD_ID_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 5, 3) +#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE3_SET_CLASS_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 8, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) GET_H2C_FIELD(__pH2C + 0X00, 16, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_H2C_FIELD_CLR(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT_NO_CLR(__pH2C, __Value) SET_H2C_FIELD_NO_CLR(__pH2C + 0X00, 16, 8, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h new file mode 100644 index 000000000000..756166b78256 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_original_h2c_nic.h @@ -0,0 +1,610 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ +#define _HAL_ORIGINALH2CFORMAT_H2C_C2H_NIC_H_ +#define CMD_ID_ORIGINAL_H2C 0X00 +#define CMD_ID_H2C2H_LB 0X0 +#define CMD_ID_D0_SCAN_OFFLOAD_CTRL 0X06 +#define CMD_ID_RSVD_PAGE 0X0 +#define CMD_ID_MEDIA_STATUS_RPT 0X01 +#define CMD_ID_KEEP_ALIVE 0X03 +#define CMD_ID_DISCONNECT_DECISION 0X04 +#define CMD_ID_AP_OFFLOAD 0X08 +#define CMD_ID_BCN_RSVDPAGE 0X09 +#define CMD_ID_PROBE_RSP_RSVDPAGE 0X0A +#define CMD_ID_SET_PWR_MODE 0X00 +#define CMD_ID_PS_TUNING_PARA 0X01 +#define CMD_ID_PS_TUNING_PARA_II 0X02 +#define CMD_ID_PS_LPS_PARA 0X03 +#define CMD_ID_P2P_PS_OFFLOAD 0X04 +#define CMD_ID_PS_SCAN_EN 0X05 +#define CMD_ID_SAP_PS 0X06 +#define CMD_ID_INACTIVE_PS 0X07 +#define CMD_ID_MACID_CFG 0X00 +#define CMD_ID_TXBF 0X01 +#define CMD_ID_RSSI_SETTING 0X02 +#define CMD_ID_AP_REQ_TXRPT 0X03 +#define CMD_ID_INIT_RATE_COLLECTION 0X04 +#define CMD_ID_IQK_OFFLOAD 0X05 +#define CMD_ID_MACID_CFG_3SS 0X06 +#define CMD_ID_RA_PARA_ADJUST 0X07 +#define CMD_ID_WWLAN 0X00 +#define CMD_ID_REMOTE_WAKE_CTRL 0X01 +#define CMD_ID_AOAC_GLOBAL_INFO 0X02 +#define CMD_ID_AOAC_RSVD_PAGE 0X03 +#define CMD_ID_AOAC_RSVD_PAGE2 0X04 +#define CMD_ID_D0_SCAN_OFFLOAD_INFO 0X05 +#define CMD_ID_CHANNEL_SWITCH_OFFLOAD 0X07 +#define CMD_ID_AOAC_RSVD_PAGE3 0X08 +#define CLASS_ORIGINAL_H2C 0X00 +#define CLASS_H2C2H_LB 0X07 +#define CLASS_D0_SCAN_OFFLOAD_CTRL 0X04 +#define CLASS_RSVD_PAGE 0X0 +#define CLASS_MEDIA_STATUS_RPT 0X0 +#define CLASS_KEEP_ALIVE 0X0 +#define CLASS_DISCONNECT_DECISION 0X0 +#define CLASS_AP_OFFLOAD 0X0 +#define CLASS_BCN_RSVDPAGE 0X0 +#define CLASS_PROBE_RSP_RSVDPAGE 0X0 +#define CLASS_SET_PWR_MODE 0X01 +#define CLASS_PS_TUNING_PARA 0X01 +#define CLASS_PS_TUNING_PARA_II 0X01 +#define CLASS_PS_LPS_PARA 0X01 +#define CLASS_P2P_PS_OFFLOAD 0X01 +#define CLASS_PS_SCAN_EN 0X1 +#define CLASS_SAP_PS 0X1 +#define CLASS_INACTIVE_PS 0X1 +#define CLASS_MACID_CFG 0X2 +#define CLASS_TXBF 0X2 +#define CLASS_RSSI_SETTING 0X2 +#define CLASS_AP_REQ_TXRPT 0X2 +#define CLASS_INIT_RATE_COLLECTION 0X2 +#define CLASS_IQK_OFFLOAD 0X2 +#define CLASS_MACID_CFG_3SS 0X2 +#define CLASS_RA_PARA_ADJUST 0X02 +#define CLASS_WWLAN 0X4 +#define CLASS_REMOTE_WAKE_CTRL 0X4 +#define CLASS_AOAC_GLOBAL_INFO 0X04 +#define CLASS_AOAC_RSVD_PAGE 0X04 +#define CLASS_AOAC_RSVD_PAGE2 0X04 +#define CLASS_D0_SCAN_OFFLOAD_INFO 0X04 +#define CLASS_CHANNEL_SWITCH_OFFLOAD 0X04 +#define CLASS_AOAC_RSVD_PAGE3 0X04 +#define ORIGINAL_H2C_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define ORIGINAL_H2C_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define ORIGINAL_H2C_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define ORIGINAL_H2C_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define H2C2H_LB_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define H2C2H_LB_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define H2C2H_LB_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define H2C2H_LB_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define H2C2H_LB_GET_SEQ(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define H2C2H_LB_SET_SEQ(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define H2C2H_LB_GET_PAYLOAD1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 16) +#define H2C2H_LB_SET_PAYLOAD1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 16, __Value) +#define H2C2H_LB_GET_PAYLOAD2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 32) +#define H2C2H_LB_SET_PAYLOAD2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 32, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_D0_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_D0_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_RTD3FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_RTD3FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_U3_SCAN_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_U3_SCAN_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_NLO_FUN_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_NLO_FUN_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_IPS_DEPENDENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) +#define D0_SCAN_OFFLOAD_CTRL_SET_IPS_DEPENDENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_PROBE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 17) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_PROBE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 17, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SCAN_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SCAN_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define D0_SCAN_OFFLOAD_CTRL_GET_LOC_SSID_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define D0_SCAN_OFFLOAD_CTRL_SET_LOC_SSID_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define RSVD_PAGE_GET_LOC_PROBE_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define RSVD_PAGE_SET_LOC_PROBE_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define RSVD_PAGE_GET_LOC_PS_POLL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define RSVD_PAGE_SET_LOC_PS_POLL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define RSVD_PAGE_GET_LOC_NULL_DATA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define RSVD_PAGE_SET_LOC_NULL_DATA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define RSVD_PAGE_GET_LOC_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define RSVD_PAGE_SET_LOC_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define RSVD_PAGE_GET_LOC_BT_QOS_NULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define RSVD_PAGE_SET_LOC_BT_QOS_NULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define RSVD_PAGE_GET_LOC_CTS2SELF(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) +#define RSVD_PAGE_SET_LOC_CTS2SELF(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) +#define RSVD_PAGE_GET_LOC_LTECOEX_QOSNULL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) +#define RSVD_PAGE_SET_LOC_LTECOEX_QOSNULL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) +#define MEDIA_STATUS_RPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define MEDIA_STATUS_RPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define MEDIA_STATUS_RPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define MEDIA_STATUS_RPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define MEDIA_STATUS_RPT_GET_OP_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define MEDIA_STATUS_RPT_SET_OP_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define MEDIA_STATUS_RPT_GET_MACID_IN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define MEDIA_STATUS_RPT_SET_MACID_IN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define MEDIA_STATUS_RPT_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define MEDIA_STATUS_RPT_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define MEDIA_STATUS_RPT_GET_MACID_END(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define MEDIA_STATUS_RPT_SET_MACID_END(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define KEEP_ALIVE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define KEEP_ALIVE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define KEEP_ALIVE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define KEEP_ALIVE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define KEEP_ALIVE_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define KEEP_ALIVE_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define KEEP_ALIVE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define KEEP_ALIVE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define KEEP_ALIVE_GET_PKT_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define KEEP_ALIVE_SET_PKT_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define KEEP_ALIVE_GET_KEEP_ALIVE_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define KEEP_ALIVE_SET_KEEP_ALIVE_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define DISCONNECT_DECISION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define DISCONNECT_DECISION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define DISCONNECT_DECISION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define DISCONNECT_DECISION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define DISCONNECT_DECISION_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define DISCONNECT_DECISION_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define DISCONNECT_DECISION_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define DISCONNECT_DECISION_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define DISCONNECT_DECISION_GET_DISCONNECT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) +#define DISCONNECT_DECISION_SET_DISCONNECT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) +#define DISCONNECT_DECISION_GET_DISCON_DECISION_CHECK_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define DISCONNECT_DECISION_SET_DISCON_DECISION_CHECK_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define DISCONNECT_DECISION_GET_TRY_PKT_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define DISCONNECT_DECISION_SET_TRY_PKT_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define DISCONNECT_DECISION_GET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define DISCONNECT_DECISION_SET_TRY_OK_BCN_FAIL_COUNT_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define AP_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AP_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define AP_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define AP_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define AP_OFFLOAD_GET_ON(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define AP_OFFLOAD_SET_ON(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define AP_OFFLOAD_GET_CFG_MIFI_PLATFORM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define AP_OFFLOAD_SET_CFG_MIFI_PLATFORM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define AP_OFFLOAD_GET_LINKED(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define AP_OFFLOAD_SET_LINKED(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define AP_OFFLOAD_GET_EN_AUTO_WAKE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) +#define AP_OFFLOAD_SET_EN_AUTO_WAKE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) +#define AP_OFFLOAD_GET_WAKE_FLAG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) +#define AP_OFFLOAD_SET_WAKE_FLAG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1) +#define AP_OFFLOAD_SET_HIDDEN_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 19, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 19, 1, __Value) +#define AP_OFFLOAD_GET_HIDDEN_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 1) +#define AP_OFFLOAD_SET_HIDDEN_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) +#define AP_OFFLOAD_SET_DENYANY_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value) +#define AP_OFFLOAD_GET_DENYANY_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1) +#define AP_OFFLOAD_SET_DENYANY_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value) +#define AP_OFFLOAD_GET_WAIT_TBTT_CNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define AP_OFFLOAD_SET_WAIT_TBTT_CNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define AP_OFFLOAD_GET_WAKE_TIMEOUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define AP_OFFLOAD_SET_WAKE_TIMEOUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define AP_OFFLOAD_GET_LEN_IV_PAIR(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) +#define AP_OFFLOAD_SET_LEN_IV_PAIR(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) +#define AP_OFFLOAD_GET_LEN_IV_GRP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) +#define AP_OFFLOAD_SET_LEN_IV_GRP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) +#define BCN_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define BCN_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define BCN_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define BCN_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define BCN_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define BCN_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define BCN_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PROBE_RSP_RSVDPAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define PROBE_RSP_RSVDPAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define PROBE_RSP_RSVDPAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_ROOT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_ROOT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP3(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP3(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define PROBE_RSP_RSVDPAGE_GET_LOC_VAP4(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define PROBE_RSP_RSVDPAGE_SET_LOC_VAP4(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define SET_PWR_MODE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define SET_PWR_MODE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define SET_PWR_MODE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define SET_PWR_MODE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define SET_PWR_MODE_GET_MODE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) +#define SET_PWR_MODE_SET_MODE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) +#define SET_PWR_MODE_GET_CLK_REQUEST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) +#define SET_PWR_MODE_SET_CLK_REQUEST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) +#define SET_PWR_MODE_GET_RLBM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4) +#define SET_PWR_MODE_SET_RLBM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value) +#define SET_PWR_MODE_GET_SMART_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 20, 4) +#define SET_PWR_MODE_SET_SMART_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 20, 4, __Value) +#define SET_PWR_MODE_GET_AWAKE_INTERVAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define SET_PWR_MODE_SET_AWAKE_INTERVAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define SET_PWR_MODE_GET_B_ALL_QUEUE_UAPSD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1) +#define SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value) +#define SET_PWR_MODE_GET_BCN_EARLY_RPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 2, 1) +#define SET_PWR_MODE_SET_BCN_EARLY_RPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 2, 1, __Value) +#define SET_PWR_MODE_GET_PORT_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 5, 3) +#define SET_PWR_MODE_SET_PORT_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 5, 3, __Value) +#define SET_PWR_MODE_GET_PWR_STATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define SET_PWR_MODE_SET_PWR_STATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define SET_PWR_MODE_GET_LOW_POWER_RX_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 1) +#define SET_PWR_MODE_SET_LOW_POWER_RX_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 1, __Value) +#define SET_PWR_MODE_GET_ANT_AUTO_SWITCH(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 17, 1) +#define SET_PWR_MODE_SET_ANT_AUTO_SWITCH(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 17, 1, __Value) +#define SET_PWR_MODE_GET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 18, 1) +#define SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 18, 1, __Value) +#define SET_PWR_MODE_GET_PROTECT_BCN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 19, 1) +#define SET_PWR_MODE_SET_PROTECT_BCN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 19, 1, __Value) +#define SET_PWR_MODE_GET_SILENCE_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 20, 1) +#define SET_PWR_MODE_SET_SILENCE_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 20, 1, __Value) +#define SET_PWR_MODE_GET_FAST_BT_CONNECT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 21, 1) +#define SET_PWR_MODE_SET_FAST_BT_CONNECT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 21, 1, __Value) +#define SET_PWR_MODE_GET_TWO_ANTENNA_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 22, 1) +#define SET_PWR_MODE_SET_TWO_ANTENNA_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 22, 1, __Value) +#define SET_PWR_MODE_GET_ADOPT_USER_SETTING(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 1) +#define SET_PWR_MODE_SET_ADOPT_USER_SETTING(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 1, __Value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 25, 3) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 25, 3, __Value) +#define SET_PWR_MODE_GET_DRV_BCN_EARLY_SHIFT2(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 28, 4) +#define SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 28, 4, __Value) +#define PS_TUNING_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define PS_TUNING_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define PS_TUNING_PARA_GET_BCN_TO_LIMIT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) +#define PS_TUNING_PARA_SET_BCN_TO_LIMIT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) +#define PS_TUNING_PARA_GET_DTIM_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) +#define PS_TUNING_PARA_SET_DTIM_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) +#define PS_TUNING_PARA_GET_PS_TIME_OUT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 4) +#define PS_TUNING_PARA_SET_PS_TIME_OUT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 4, __Value) +#define PS_TUNING_PARA_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define PS_TUNING_PARA_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define PS_TUNING_PARA_II_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_TUNING_PARA_II_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define PS_TUNING_PARA_II_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define PS_TUNING_PARA_II_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define PS_TUNING_PARA_II_GET_BCN_TO_PERIOD(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 7) +#define PS_TUNING_PARA_II_SET_BCN_TO_PERIOD(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 7, __Value) +#define PS_TUNING_PARA_II_GET_ADOPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) +#define PS_TUNING_PARA_II_SET_ADOPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) +#define PS_TUNING_PARA_II_GET_DRV_EARLY_IVL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define PS_TUNING_PARA_II_SET_DRV_EARLY_IVL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define PS_LPS_PARA_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_LPS_PARA_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define PS_LPS_PARA_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define PS_LPS_PARA_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define PS_LPS_PARA_GET_LPS_CONTROL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define PS_LPS_PARA_SET_LPS_CONTROL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define P2P_PS_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define P2P_PS_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define P2P_PS_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define P2P_PS_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define P2P_PS_OFFLOAD_GET_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define P2P_PS_OFFLOAD_SET_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define P2P_PS_OFFLOAD_GET_ROLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define P2P_PS_OFFLOAD_SET_ROLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define P2P_PS_OFFLOAD_GET_CTWINDOW_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define P2P_PS_OFFLOAD_SET_CTWINDOW_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define P2P_PS_OFFLOAD_GET_NOA0_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) +#define P2P_PS_OFFLOAD_SET_NOA0_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) +#define P2P_PS_OFFLOAD_GET_NOA1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) +#define P2P_PS_OFFLOAD_SET_NOA1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) +#define P2P_PS_OFFLOAD_GET_ALL_STA_SLEEP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) +#define P2P_PS_OFFLOAD_SET_ALL_STA_SLEEP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) +#define P2P_PS_OFFLOAD_GET_DISCOVERY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) +#define P2P_PS_OFFLOAD_SET_DISCOVERY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) +#define PS_SCAN_EN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define PS_SCAN_EN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define PS_SCAN_EN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define PS_SCAN_EN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define PS_SCAN_EN_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define PS_SCAN_EN_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define SAP_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define SAP_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define SAP_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define SAP_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define SAP_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define SAP_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define SAP_PS_GET_EN_PS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define SAP_PS_SET_EN_PS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define SAP_PS_GET_EN_LP_RX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define SAP_PS_SET_EN_LP_RX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define SAP_PS_GET_MANUAL_32K(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) +#define SAP_PS_SET_MANUAL_32K(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) +#define SAP_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define SAP_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define INACTIVE_PS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define INACTIVE_PS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define INACTIVE_PS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define INACTIVE_PS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define INACTIVE_PS_GET_ENABLE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define INACTIVE_PS_SET_ENABLE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define INACTIVE_PS_GET_IGNORE_PS_CONDITION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define INACTIVE_PS_SET_IGNORE_PS_CONDITION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define INACTIVE_PS_GET_FREQUENCY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define INACTIVE_PS_SET_FREQUENCY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define INACTIVE_PS_GET_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define INACTIVE_PS_SET_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define MACID_CFG_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define MACID_CFG_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define MACID_CFG_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define MACID_CFG_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 5) +#define MACID_CFG_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 5, __Value) +#define MACID_CFG_GET_INIT_RATE_LV(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 21, 2) +#define MACID_CFG_SET_INIT_RATE_LV(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 21, 2, __Value) +#define MACID_CFG_GET_SGI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1) +#define MACID_CFG_SET_SGI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value) +#define MACID_CFG_GET_BW(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 2) +#define MACID_CFG_SET_BW(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 2, __Value) +#define MACID_CFG_GET_LDPC_CAP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 26, 1) +#define MACID_CFG_SET_LDPC_CAP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 26, 1, __Value) +#define MACID_CFG_GET_NO_UPDATE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 27, 1) +#define MACID_CFG_SET_NO_UPDATE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 27, 1, __Value) +#define MACID_CFG_GET_WHT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 2) +#define MACID_CFG_SET_WHT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 2, __Value) +#define MACID_CFG_GET_DISPT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 30, 1) +#define MACID_CFG_SET_DISPT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 30, 1, __Value) +#define MACID_CFG_GET_DISRA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 31, 1) +#define MACID_CFG_SET_DISRA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 31, 1, __Value) +#define MACID_CFG_GET_RATE_MASK7_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define MACID_CFG_SET_RATE_MASK7_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_GET_RATE_MASK15_8(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define MACID_CFG_SET_RATE_MASK15_8(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define MACID_CFG_GET_RATE_MASK23_16(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) +#define MACID_CFG_SET_RATE_MASK23_16(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) +#define MACID_CFG_GET_RATE_MASK31_24(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) +#define MACID_CFG_SET_RATE_MASK31_24(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) +#define TXBF_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define TXBF_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define TXBF_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define TXBF_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define TXBF_GET_NDPA0_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define TXBF_SET_NDPA0_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define TXBF_GET_NDPA1_HEAD_PAGE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define TXBF_SET_NDPA1_HEAD_PAGE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define TXBF_GET_PERIOD_0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define TXBF_SET_PERIOD_0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define RSSI_SETTING_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define RSSI_SETTING_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define RSSI_SETTING_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define RSSI_SETTING_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define RSSI_SETTING_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define RSSI_SETTING_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define RSSI_SETTING_GET_RSSI(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 7) +#define RSSI_SETTING_SET_RSSI(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 7, __Value) +#define RSSI_SETTING_GET_RA_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define RSSI_SETTING_SET_RA_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define AP_REQ_TXRPT_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AP_REQ_TXRPT_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define AP_REQ_TXRPT_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define AP_REQ_TXRPT_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define AP_REQ_TXRPT_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define AP_REQ_TXRPT_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define AP_REQ_TXRPT_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define AP_REQ_TXRPT_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define AP_REQ_TXRPT_GET_RTY_OK_TOTAL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) +#define AP_REQ_TXRPT_SET_RTY_OK_TOTAL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) +#define AP_REQ_TXRPT_GET_RTY_CNT_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 25, 1) +#define AP_REQ_TXRPT_SET_RTY_CNT_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 25, 1, __Value) +#define INIT_RATE_COLLECTION_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define INIT_RATE_COLLECTION_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define INIT_RATE_COLLECTION_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define INIT_RATE_COLLECTION_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define INIT_RATE_COLLECTION_GET_STA1_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA1_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA2_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA2_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA3_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA3_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA4_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define INIT_RATE_COLLECTION_SET_STA4_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA5_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define INIT_RATE_COLLECTION_SET_STA5_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA6_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) +#define INIT_RATE_COLLECTION_SET_STA6_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) +#define INIT_RATE_COLLECTION_GET_STA7_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) +#define INIT_RATE_COLLECTION_SET_STA7_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) +#define IQK_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define IQK_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define IQK_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define IQK_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define IQK_OFFLOAD_GET_CHANNEL(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define IQK_OFFLOAD_SET_CHANNEL(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define IQK_OFFLOAD_GET_BWBAND(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define IQK_OFFLOAD_SET_BWBAND(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define IQK_OFFLOAD_GET_EXTPALNA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define IQK_OFFLOAD_SET_EXTPALNA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define MACID_CFG_3SS_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define MACID_CFG_3SS_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define MACID_CFG_3SS_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define MACID_CFG_3SS_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define MACID_CFG_3SS_GET_MACID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define MACID_CFG_3SS_SET_MACID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_39_32(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_39_32(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define MACID_CFG_3SS_GET_RATE_MASK_47_40(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define MACID_CFG_3SS_SET_RATE_MASK_47_40(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define RA_PARA_ADJUST_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define RA_PARA_ADJUST_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define RA_PARA_ADJUST_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define RA_PARA_ADJUST_GET_MAC_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define RA_PARA_ADJUST_SET_MAC_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_PARAMETER_INDEX(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define RA_PARA_ADJUST_SET_PARAMETER_INDEX(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define RA_PARA_ADJUST_GET_RATE_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define RA_PARA_ADJUST_SET_RATE_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE0(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE0(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define RA_PARA_ADJUST_GET_VALUE_BYTE1(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define RA_PARA_ADJUST_SET_VALUE_BYTE1(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define RA_PARA_ADJUST_GET_ASK_FW_FOR_FW_PARA(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) +#define RA_PARA_ADJUST_SET_ASK_FW_FOR_FW_PARA(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) +#define WWLAN_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define WWLAN_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define WWLAN_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define WWLAN_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define WWLAN_GET_FUNC_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define WWLAN_SET_FUNC_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define WWLAN_GET_PATTERM_MAT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define WWLAN_SET_PATTERM_MAT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define WWLAN_GET_MAGIC_PKT_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define WWLAN_SET_MAGIC_PKT_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define WWLAN_GET_UNICAST_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) +#define WWLAN_SET_UNICAST_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) +#define WWLAN_GET_ALL_PKT_DROP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) +#define WWLAN_SET_ALL_PKT_DROP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) +#define WWLAN_GET_GPIO_ACTIVE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) +#define WWLAN_SET_GPIO_ACTIVE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) +#define WWLAN_GET_REKEY_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) +#define WWLAN_SET_REKEY_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) +#define WWLAN_GET_DEAUTH_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) +#define WWLAN_SET_DEAUTH_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) +#define WWLAN_GET_GPIO_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 7) +#define WWLAN_SET_GPIO_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 7, __Value) +#define WWLAN_GET_DATAPIN_WAKEUP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 23, 1) +#define WWLAN_SET_DATAPIN_WAKEUP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 23, 1, __Value) +#define WWLAN_GET_GPIO_DURATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define WWLAN_SET_GPIO_DURATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define WWLAN_GET_GPIO_PLUS_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 1) +#define WWLAN_SET_GPIO_PLUS_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 1, __Value) +#define WWLAN_GET_GPIO_PULSE_COUNT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 1, 7) +#define WWLAN_SET_GPIO_PULSE_COUNT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 1, 7, __Value) +#define WWLAN_GET_DISABLE_UPHY(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 1) +#define WWLAN_SET_DISABLE_UPHY(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 1, __Value) +#define WWLAN_GET_HST2DEV_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 9, 1) +#define WWLAN_SET_HST2DEV_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 9, 1, __Value) +#define WWLAN_GET_GPIO_DURATION_MS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 10, 1) +#define WWLAN_SET_GPIO_DURATION_MS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 10, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define REMOTE_WAKE_CTRL_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define REMOTE_WAKE_CTRL_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define REMOTE_WAKE_CTRL_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define REMOTE_WAKE_CTRL_GET_REMOTE_WAKE_CTRL_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 1) +#define REMOTE_WAKE_CTRL_SET_REMOTE_WAKE_CTRL_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_ARP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 9, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 9, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_NDP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 10, 1) +#define REMOTE_WAKE_CTRL_SET_NDP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 10, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_GTK_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 11, 1) +#define REMOTE_WAKE_CTRL_SET_GTK_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 11, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_NLO_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 12, 1) +#define REMOTE_WAKE_CTRL_SET_NLO_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 12, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V1_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 13, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V1_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 13, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_REAL_WOW_V2_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 14, 1) +#define REMOTE_WAKE_CTRL_SET_REAL_WOW_V2_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 14, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_FW_UNICAST(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 15, 1) +#define REMOTE_WAKE_CTRL_SET_FW_UNICAST(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 15, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_P2P_OFFLOAD_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 1) +#define REMOTE_WAKE_CTRL_SET_P2P_OFFLOAD_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_RUNTIME_PM_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 17, 1) +#define REMOTE_WAKE_CTRL_SET_RUNTIME_PM_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 17, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_NET_BIOS_DROP_EN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 18, 1) +#define REMOTE_WAKE_CTRL_SET_NET_BIOS_DROP_EN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 18, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_ARP_ACTION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 1) +#define REMOTE_WAKE_CTRL_SET_ARP_ACTION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_UNTIL_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 28, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_UNTIL_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 28, 1, __Value) +#define REMOTE_WAKE_CTRL_GET_FW_PARSING_AFTER_WAKEUP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 29, 1) +#define REMOTE_WAKE_CTRL_SET_FW_PARSING_AFTER_WAKEUP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 29, 1, __Value) +#define AOAC_GLOBAL_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_GLOBAL_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_GLOBAL_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define AOAC_GLOBAL_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_GLOBAL_INFO_GET_PAIR_WISE_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define AOAC_GLOBAL_INFO_SET_PAIR_WISE_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_GLOBAL_INFO_GET_GROUP_ENC_ALG(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define AOAC_GLOBAL_INFO_SET_GROUP_ENC_ALG(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define AOAC_RSVD_PAGE_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_REMOTE_CTRL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_REMOTE_CTRL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_ARP_RESPONSE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_ARP_RESPONSE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NEIGHBOR_ADVERTISEMENT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_RSP(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_RSP(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_GTK_EXT_MEM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) +#define AOAC_RSVD_PAGE_SET_LOC_GTK_EXT_MEM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) +#define AOAC_RSVD_PAGE_GET_LOC_NDP_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) +#define AOAC_RSVD_PAGE_SET_LOC_NDP_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE2_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE2_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define AOAC_RSVD_PAGE2_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_ROUTER_SOLICATION(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ROUTER_SOLICATION(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_BUBBLE_PACKET(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_BUBBLE_PACKET(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_TEREDO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_TEREDO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_REALWOW_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 0, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_REALWOW_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 0, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_KEEP_ALIVE_PKT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 8, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_KEEP_ALIVE_PKT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 8, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_ACK_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 16, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_ACK_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 16, 8, __Value) +#define AOAC_RSVD_PAGE2_GET_LOC_WAKEUP_PATTERN(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X04, 24, 8) +#define AOAC_RSVD_PAGE2_SET_LOC_WAKEUP_PATTERN(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X04, 24, 8, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define D0_SCAN_OFFLOAD_INFO_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define D0_SCAN_OFFLOAD_INFO_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define D0_SCAN_OFFLOAD_INFO_GET_LOC_CHANNEL_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define D0_SCAN_OFFLOAD_INFO_SET_LOC_CHANNEL_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define CHANNEL_SWITCH_OFFLOAD_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define CHANNEL_SWITCH_OFFLOAD_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_CHANNEL_NUM(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_CHANNEL_NUM(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_EN_RFE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_EN_RFE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#define CHANNEL_SWITCH_OFFLOAD_GET_RFE_TYPE(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 24, 8) +#define CHANNEL_SWITCH_OFFLOAD_SET_RFE_TYPE(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 24, 8, __Value) +#define AOAC_RSVD_PAGE3_GET_CMD_ID(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 0, 5) +#define AOAC_RSVD_PAGE3_SET_CMD_ID(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 0, 5, __Value) +#define AOAC_RSVD_PAGE3_GET_CLASS(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 5, 3) +#define AOAC_RSVD_PAGE3_SET_CLASS(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 5, 3, __Value) +#define AOAC_RSVD_PAGE3_GET_LOC_NLO_INFO(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 8, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_NLO_INFO(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 8, 8, __Value) +#define AOAC_RSVD_PAGE3_GET_LOC_AOAC_REPORT(__pH2C) LE_BITS_TO_4BYTE(__pH2C + 0X00, 16, 8) +#define AOAC_RSVD_PAGE3_SET_LOC_AOAC_REPORT(__pH2C, __Value) SET_BITS_TO_LE_4BYTE(__pH2C + 0X00, 16, 8, __Value) +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_pcie_reg.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_pcie_reg.h new file mode 100644 index 000000000000..30657bd6024e --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_pcie_reg.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HALMAC_PCIE_REG_H__ +#define __HALMAC_PCIE_REG_H__ + +#endif/* __HALMAC_PCIE_REG_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h new file mode 100644 index 000000000000..433100055358 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_pwr_seq_cmd.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef HALMAC_POWER_SEQUENCE_CMD +#define HALMAC_POWER_SEQUENCE_CMD + +#include "halmac_2_platform.h" +#include "halmac_type.h" + +#define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000 + +/* +* The value of cmd : 4 bits +*/ + +/* +* offset : the read register offset +* msk : the mask of the read value +* value : N/A, left by 0 +* Note : dirver shall implement this function by read & msk +*/ +#define HALMAC_PWR_CMD_READ 0x00 +/* +* offset: the read register offset +* msk: the mask of the write bits +* value: write value +* Note: driver shall implement this cmd by read & msk after write +*/ +#define HALMAC_PWR_CMD_WRITE 0x01 +/* +* offset: the read register offset +* msk: the mask of the polled value +* value: the value to be polled, masked by the msd field. +* Note: driver shall implement this cmd by +* do{ +* if( (Read(offset) & msk) == (value & msk) ) +* break; +* } while(not timeout); +*/ +#define HALMAC_PWR_CMD_POLLING 0x02 +/* +* offset: the value to delay +* msk: N/A +* value: the unit of delay, 0: us, 1: ms +*/ +#define HALMAC_PWR_CMD_DELAY 0x03 +/* +* offset: N/A +* msk: N/A +* value: N/A +*/ +#define HALMAC_PWR_CMD_END 0x04 + +/* +* The value of base : 4 bits +*/ + +/* define the base address of each block */ +#define HALMAC_PWR_BASEADDR_MAC 0x00 +#define HALMAC_PWR_BASEADDR_USB 0x01 +#define HALMAC_PWR_BASEADDR_PCIE 0x02 +#define HALMAC_PWR_BASEADDR_SDIO 0x03 + +/* +* The value of interface_msk : 4 bits +*/ +#define HALMAC_PWR_INTF_SDIO_MSK BIT(0) +#define HALMAC_PWR_INTF_USB_MSK BIT(1) +#define HALMAC_PWR_INTF_PCI_MSK BIT(2) +#define HALMAC_PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/* +* The value of fab_msk : 4 bits +*/ +#define HALMAC_PWR_FAB_TSMC_MSK BIT(0) +#define HALMAC_PWR_FAB_UMC_MSK BIT(1) +#define HALMAC_PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/* +* The value of cut_msk : 8 bits +*/ +#define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0) +#define HALMAC_PWR_CUT_A_MSK BIT(1) +#define HALMAC_PWR_CUT_B_MSK BIT(2) +#define HALMAC_PWR_CUT_C_MSK BIT(3) +#define HALMAC_PWR_CUT_D_MSK BIT(4) +#define HALMAC_PWR_CUT_E_MSK BIT(5) +#define HALMAC_PWR_CUT_F_MSK BIT(6) +#define HALMAC_PWR_CUT_G_MSK BIT(7) +#define HALMAC_PWR_CUT_ALL_MSK 0xFF + +typedef enum _HALMAC_PWRSEQ_CMD_DELAY_UNIT_ { + HALMAC_PWRSEQ_DELAY_US, + HALMAC_PWRSEQ_DELAY_MS, +} HALMAC_PWRSEQ_DELAY_UNIT; + +/* Don't care endian issue, because element of pwer seq vector is fixed address */ +typedef struct _HALMAC_WL_PWR_CFG_ { + u16 offset; + u8 cut_msk; + u8 fab_msk:4; + u8 interface_msk:4; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 value; +} HALMAC_WLAN_PWR_CFG, *PHALMAC_WLAN_PWR_CFG; + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_reg2.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_reg2.h new file mode 100644 index 000000000000..2a096e83eaf4 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_reg2.h @@ -0,0 +1,1116 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HALMAC_COM_REG_H__ +#define __HALMAC_COM_REG_H__ + +#define REG_SYS_ISO_CTRL 0x0000 + +#define REG_SDIO_TX_CTRL 0x10250000 + +#define REG_SYS_FUNC_EN 0x0002 +#define REG_SYS_PW_CTRL 0x0004 +#define REG_SYS_CLK_CTRL 0x0008 +#define REG_SYS_EEPROM_CTRL 0x000A +#define REG_EE_VPD 0x000C +#define REG_SYS_SWR_CTRL1 0x0010 +#define REG_SYS_SWR_CTRL2 0x0014 + +#define REG_SDIO_HIMR 0x10250014 + +#define REG_SYS_SWR_CTRL3 0x0018 + +#define REG_SDIO_HISR 0x10250018 + +#define REG_RSV_CTRL 0x001C + +#define REG_SDIO_RX_REQ_LEN 0x1025001C + +#define REG_RF_CTRL 0x001F + +#define REG_SDIO_FREE_TXPG_SEQ_V1 0x1025001F + +#define REG_AFE_LDO_CTRL 0x0020 + +#define REG_SDIO_FREE_TXPG 0x10250020 + +#define REG_AFE_CTRL1 0x0024 + +#define REG_SDIO_FREE_TXPG2 0x10250024 + +#define REG_AFE_CTRL2 0x0028 + +#define REG_SDIO_OQT_FREE_TXPG_V1 0x10250028 + +#define REG_AFE_CTRL3 0x002C +#define REG_EFUSE_CTRL 0x0030 + +#define REG_SDIO_HTSFR_INFO 0x10250030 + +#define REG_LDO_EFUSE_CTRL 0x0034 +#define REG_PWR_OPTION_CTRL 0x0038 + +#define REG_SDIO_HCPWM1_V2 0x10250038 +#define REG_SDIO_HCPWM2_V2 0x1025003A + +#define REG_CAL_TIMER 0x003C +#define REG_ACLK_MON 0x003E +#define REG_GPIO_MUXCFG 0x0040 + +#define REG_SDIO_INDIRECT_REG_CFG 0x10250040 + +#define REG_GPIO_PIN_CTRL 0x0044 + +#define REG_SDIO_INDIRECT_REG_DATA 0x10250044 + +#define REG_GPIO_INTM 0x0048 +#define REG_LED_CFG 0x004C +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005C +#define REG_GPIO_EXT_CTRL 0x0060 + +#define REG_SDIO_H2C 0x10250060 + +#define REG_PAD_CTRL1 0x0064 + +#define REG_SDIO_C2H 0x10250064 + +#define REG_WL_BT_PWR_CTRL 0x0068 + +#define REG_SDM_DEBUG 0x006C + +#define REG_SYS_SDIO_CTRL 0x0070 + +#define REG_HCI_OPT_CTRL 0x0074 + +#define REG_AFE_CTRL4 0x0078 + +#define REG_LDO_SWR_CTRL 0x007C + +#define REG_MCUFW_CTRL 0x0080 + +#define REG_SDIO_HRPWM1 0x10250080 +#define REG_SDIO_HRPWM2 0x10250082 + +#define REG_MCU_TST_CFG 0x0084 + +#define REG_SDIO_HPS_CLKR 0x10250084 +#define REG_SDIO_BUS_CTRL 0x10250085 + +#define REG_SDIO_HSUS_CTRL 0x10250086 + +#define REG_HMEBOX_E0_E1 0x0088 + +#define REG_SDIO_RESPONSE_TIMER 0x10250088 + +#define REG_SDIO_CMD_CRC 0x1025008A + +#define REG_HMEBOX_E2_E3 0x008C +#define REG_WLLPS_CTRL 0x0090 + +#define REG_SDIO_HSISR 0x10250090 +#define REG_SDIO_HSIMR 0x10250091 + +#define REG_AFE_CTRL5 0x0094 + +#define REG_GPIO_DEBOUNCE_CTRL 0x0098 +#define REG_RPWM2 0x009C +#define REG_SYSON_FSM_MON 0x00A0 + +#define REG_AFE_CTRL6 0x00A4 + +#define REG_PMC_DBG_CTRL1 0x00A8 + +#define REG_AFE_CTRL7 0x00AC + +#define REG_HIMR0 0x00B0 +#define REG_HISR0 0x00B4 +#define REG_HIMR1 0x00B8 +#define REG_HISR1 0x00BC +#define REG_DBG_PORT_SEL 0x00C0 + +#define REG_SDIO_ERR_RPT 0x102500C0 +#define REG_SDIO_CMD_ERRCNT 0x102500C1 +#define REG_SDIO_DATA_ERRCNT 0x102500C2 + +#define REG_PAD_CTRL2 0x00C4 + +#define REG_SDIO_CMD_ERR_CONTENT 0x102500C4 + +#define REG_SDIO_CRC_ERR_IDX 0x102500C9 +#define REG_SDIO_DATA_CRC 0x102500CA +#define REG_SDIO_DATA_REPLY_TIME 0x102500CB + +#define REG_PMC_DBG_CTRL2 0x00CC +#define REG_BIST_CTRL 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_MEM_CTRL 0x00D8 + +#define REG_AFE_CTRL8 0x00DC + +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 + +#define REG_WLRF1 0x00EC + +#define REG_SYS_CFG1 0x00F0 +#define REG_SYS_STATUS1 0x00F4 +#define REG_SYS_STATUS2 0x00F8 +#define REG_SYS_CFG2 0x00FC +#define REG_CR 0x0100 + +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 + +#define REG_TSF_CLK_STATE 0x0108 +#define REG_TXDMA_PQ_MAP 0x010C +#define REG_TRXFF_BNDY 0x0114 + +#define REG_PTA_I2C_MBOX 0x0118 + +#define REG_RXFF_BNDY 0x011C + +#define REG_FE1IMR 0x0120 + +#define REG_FE1ISR 0x0124 + +#define REG_CPWM 0x012C +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_FTISR 0x013C +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 +#define REG_CPWM2 0x014C +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_TC5_CTRL 0x0168 +#define REG_TC6_CTRL 0x016C +#define REG_MBIST_FAIL 0x0170 +#define REG_MBIST_START_PAUSE 0x0174 +#define REG_MBIST_DONE 0x0178 + +#define REG_MBIST_FAIL_NRML 0x017C + +#define REG_AES_DECRPT_DATA 0x0180 +#define REG_AES_DECRPT_CFG 0x0184 + +#define REG_TMETER 0x0190 +#define REG_OSC_32K_CTRL 0x0194 +#define REG_32K_CAL_REG1 0x0198 +#define REG_C2HEVT 0x01A0 + +#define REG_C2HEVT_1 0x01A4 +#define REG_C2HEVT_2 0x01A8 +#define REG_C2HEVT_3 0x01AC + +#define REG_SW_DEFINED_PAGE1 0x01B8 + +#define REG_SW_DEFINED_PAGE2 0x01BC + +#define REG_MCUTST_I 0x01C0 +#define REG_MCUTST_II 0x01C4 +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX0 0x01D0 +#define REG_HMEBOX1 0x01D4 +#define REG_HMEBOX2 0x01D8 +#define REG_HMEBOX3 0x01DC +#define REG_LLT_INIT 0x01E0 + +#define REG_LLT_INIT_ADDR 0x01E4 + +#define REG_BB_ACCESS_CTRL 0x01E8 +#define REG_BB_ACCESS_DATA 0x01EC +#define REG_HMEBOX_E0 0x01F0 +#define REG_HMEBOX_E1 0x01F4 +#define REG_HMEBOX_E2 0x01F8 +#define REG_HMEBOX_E3 0x01FC + +#define REG_FIFOPAGE_CTRL_1 0x0200 + +#define REG_FIFOPAGE_CTRL_2 0x0204 + +#define REG_AUTO_LLT_V1 0x0208 + +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 + +#define REG_TX_DMA_DBG 0x0214 + +#define REG_TQPNT1 0x0218 +#define REG_TQPNT2 0x021C + +#define REG_TQPNT3 0x0220 + +#define REG_TQPNT4 0x0224 + +#define REG_RQPN_CTRL_1 0x0228 +#define REG_RQPN_CTRL_2 0x022C +#define REG_FIFOPAGE_INFO_1 0x0230 +#define REG_FIFOPAGE_INFO_2 0x0234 +#define REG_FIFOPAGE_INFO_3 0x0238 +#define REG_FIFOPAGE_INFO_4 0x023C +#define REG_FIFOPAGE_INFO_5 0x0240 + +#define REG_H2C_HEAD 0x0244 +#define REG_H2C_TAIL 0x0248 +#define REG_H2C_READ_ADDR 0x024C +#define REG_H2C_WR_ADDR 0x0250 +#define REG_H2C_INFO 0x0254 + +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXPKT_NUM 0x0284 +#define REG_RXDMA_STATUS 0x0288 +#define REG_RXDMA_DPR 0x028C +#define REG_RXDMA_MODE 0x0290 +#define REG_C2H_PKT 0x0294 + +#define REG_FWFF_C2H 0x0298 +#define REG_FWFF_CTRL 0x029C +#define REG_FWFF_PKT_INFO 0x02A0 + +#define REG_PCIE_CTRL 0x0300 + +#define REG_INT_MIG 0x0304 +#define REG_BCNQ_TXBD_DESA 0x0308 +#define REG_MGQ_TXBD_DESA 0x0310 +#define REG_VOQ_TXBD_DESA 0x0318 +#define REG_VIQ_TXBD_DESA 0x0320 +#define REG_BEQ_TXBD_DESA 0x0328 +#define REG_BKQ_TXBD_DESA 0x0330 +#define REG_RXQ_RXBD_DESA 0x0338 +#define REG_HI0Q_TXBD_DESA 0x0340 +#define REG_HI1Q_TXBD_DESA 0x0348 +#define REG_HI2Q_TXBD_DESA 0x0350 +#define REG_HI3Q_TXBD_DESA 0x0358 +#define REG_HI4Q_TXBD_DESA 0x0360 +#define REG_HI5Q_TXBD_DESA 0x0368 +#define REG_HI6Q_TXBD_DESA 0x0370 +#define REG_HI7Q_TXBD_DESA 0x0378 +#define REG_MGQ_TXBD_NUM 0x0380 +#define REG_RX_RXBD_NUM 0x0382 +#define REG_VOQ_TXBD_NUM 0x0384 +#define REG_VIQ_TXBD_NUM 0x0386 +#define REG_BEQ_TXBD_NUM 0x0388 +#define REG_BKQ_TXBD_NUM 0x038A +#define REG_HI0Q_TXBD_NUM 0x038C +#define REG_HI1Q_TXBD_NUM 0x038E +#define REG_HI2Q_TXBD_NUM 0x0390 +#define REG_HI3Q_TXBD_NUM 0x0392 +#define REG_HI4Q_TXBD_NUM 0x0394 +#define REG_HI5Q_TXBD_NUM 0x0396 +#define REG_HI6Q_TXBD_NUM 0x0398 +#define REG_HI7Q_TXBD_NUM 0x039A +#define REG_TSFTIMER_HCI 0x039C +#define REG_BD_RWPTR_CLR 0x039C +#define REG_VOQ_TXBD_IDX 0x03A0 +#define REG_VIQ_TXBD_IDX 0x03A4 +#define REG_BEQ_TXBD_IDX 0x03A8 +#define REG_BKQ_TXBD_IDX 0x03AC +#define REG_MGQ_TXBD_IDX 0x03B0 +#define REG_RXQ_RXBD_IDX 0x03B4 +#define REG_HI0Q_TXBD_IDX 0x03B8 +#define REG_HI1Q_TXBD_IDX 0x03BC +#define REG_HI2Q_TXBD_IDX 0x03C0 +#define REG_HI3Q_TXBD_IDX 0x03C4 +#define REG_HI4Q_TXBD_IDX 0x03C8 +#define REG_HI5Q_TXBD_IDX 0x03CC +#define REG_HI6Q_TXBD_IDX 0x03D0 +#define REG_HI7Q_TXBD_IDX 0x03D4 + +#define REG_DBG_SEL_V1 0x03D8 + +#define REG_PCIE_HRPWM1_V1 0x03D9 + +#define REG_PCIE_HCPWM1_V1 0x03DA + +#define REG_PCIE_CTRL2 0x03DB + +#define REG_PCIE_HRPWM2_V1 0x03DC + +#define REG_PCIE_HCPWM2_V1 0x03DE + +#define REG_PCIE_H2C_MSG_V1 0x03E0 + +#define REG_PCIE_C2H_MSG_V1 0x03E4 + +#define REG_DBI_WDATA_V1 0x03E8 + +#define REG_DBI_RDATA_V1 0x03EC + +#define REG_DBI_FLAG_V1 0x03F0 + +#define REG_MDIO_V1 0x03F4 + +#define REG_PCIE_MIX_CFG 0x03F8 + +#define REG_HCI_MIX_CFG 0x03FC + +#define REG_Q0_INFO 0x0400 +#define REG_Q1_INFO 0x0404 +#define REG_Q2_INFO 0x0408 +#define REG_Q3_INFO 0x040C +#define REG_MGQ_INFO 0x0410 +#define REG_HIQ_INFO 0x0414 +#define REG_BCNQ_INFO 0x0418 +#define REG_TXPKT_EMPTY 0x041A +#define REG_CPU_MGQ_INFO 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 + +#define REG_DATAFB_SEL 0x0423 + +#define REG_BCNQ_BDNY_V1 0x0424 + +#define REG_LIFETIME_EN 0x0426 + +#define REG_SPEC_SIFS 0x0428 +#define REG_RETRY_LIMIT 0x042A +#define REG_TXBF_CTRL 0x042C +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1_V1 0x044C +#define REG_CCK_CHECK 0x0454 + +#define REG_AMPDU_MAX_TIME_V1 0x0455 + +#define REG_BCNQ1_BDNY_V1 0x0456 + +#define REG_AMPDU_MAX_LENGTH 0x0458 +#define REG_ACQ_STOP 0x045C + +#define REG_NDPA_RATE 0x045D + +#define REG_TX_HANG_CTRL 0x045E +#define REG_NDPA_OPT_CTRL 0x045F + +#define REG_RD_RESP_PKT_TH 0x0463 +#define REG_CMDQ_INFO 0x0464 +#define REG_Q4_INFO 0x0468 +#define REG_Q5_INFO 0x046C +#define REG_Q6_INFO 0x0470 +#define REG_Q7_INFO 0x0474 + +#define REG_WMAC_LBK_BUF_HD_V1 0x0478 +#define REG_MGQ_BDNY_V1 0x047A + +#define REG_TXRPT_CTRL 0x047C +#define REG_INIRTS_RATE_SEL 0x0480 +#define REG_BASIC_CFEND_RATE 0x0481 +#define REG_STBC_CFEND_RATE 0x0482 +#define REG_DATA_SC 0x0483 +#define REG_MACID_SLEEP3 0x0484 +#define REG_MACID_SLEEP1 0x0488 +#define REG_ARFR2_V1 0x048C +#define REG_ARFR3_V1 0x0494 +#define REG_ARFR4 0x049C +#define REG_ARFR5 0x04A4 +#define REG_TXRPT_START_OFFSET 0x04AC + +#define REG_POWER_STAGE1 0x04B4 + +#define REG_POWER_STAGE2 0x04B8 + +#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC +#define REG_PKT_LIFE_TIME 0x04C0 +#define REG_STBC_SETTING 0x04C4 +#define REG_STBC_SETTING2 0x04C5 +#define REG_QUEUE_CTRL 0x04C6 +#define REG_SINGLE_AMPDU_CTRL 0x04C7 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF +#define REG_MACID_SLEEP2 0x04D0 +#define REG_MACID_SLEEP 0x04D4 + +#define REG_HW_SEQ0 0x04D8 +#define REG_HW_SEQ1 0x04DA +#define REG_HW_SEQ2 0x04DC +#define REG_HW_SEQ3 0x04DE + +#define REG_NULL_PKT_STATUS_V1 0x04E0 + +#define REG_PTCL_ERR_STATUS 0x04E2 + +#define REG_NULL_PKT_STATUS_EXTEND 0x04E3 + +#define REG_VIDEO_ENHANCEMENT_FUN 0x04E4 + +#define REG_BT_POLLUTE_PKT_CNT 0x04E8 +#define REG_PTCL_DBG 0x04EC + +#define REG_CPUMGQ_TIMER_CTRL2 0x04F4 + +#define REG_DUMMY_PAGE4_V1 0x04FC +#define REG_MOREDATA 0x04FE + +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS 0x0514 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +#define REG_MBSSID_CTRL 0x0526 +#define REG_P2PPS_CTRL 0x0527 +#define REG_PKT_LIFETIME_CTRL 0x0528 +#define REG_P2PPS_SPEC_STATE 0x052B + +#define REG_BAR_TX_CTRL 0x0530 + +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_P2PPS_STATE 0x0543 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 + +#define REG_BCN_CTRL 0x0550 + +#define REG_BCN_CTRL_CLINT0 0x0551 + +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_MBSSID_BCN_SPACE 0x0554 +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_USTIME_TSF 0x055C +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 + +#define REG_TSFTR_1 0x0564 + +#define REG_FREERUN_CNT 0x0568 + +#define REG_FREERUN_CNT_1 0x056C + +#define REG_ATIMWND1_V1 0x0570 + +#define REG_TBTT_PROHIBIT_INFRA 0x0571 + +#define REG_CTWND 0x0572 +#define REG_BCNIVLCUNT 0x0573 +#define REG_BCNDROPCTRL 0x0574 +#define REG_HGQ_TIMEOUT_PERIOD 0x0575 + +#define REG_TXCMD_TIMEOUT_PERIOD 0x0576 +#define REG_MISC_CTRL 0x0577 +#define REG_BCN_CTRL_CLINT1 0x0578 +#define REG_BCN_CTRL_CLINT2 0x0579 +#define REG_BCN_CTRL_CLINT3 0x057A + +#define REG_EXTEND_CTRL 0x057B + +#define REG_P2PPS1_SPEC_STATE 0x057C +#define REG_P2PPS1_STATE 0x057D +#define REG_P2PPS2_SPEC_STATE 0x057E +#define REG_P2PPS2_STATE 0x057F + +#define REG_PS_TIMER0 0x0580 + +#define REG_PS_TIMER1 0x0584 + +#define REG_PS_TIMER2 0x0588 + +#define REG_TBTT_CTN_AREA 0x058C +#define REG_FORCE_BCN_IFS 0x058E +#define REG_TXOP_MIN 0x0590 +#define REG_PRE_BKF_TIME 0x0592 +#define REG_CROSS_TXOP_CTRL 0x0593 + +#define REG_ATIMWND2 0x05A0 +#define REG_ATIMWND3 0x05A1 +#define REG_ATIMWND4 0x05A2 +#define REG_ATIMWND5 0x05A3 +#define REG_ATIMWND6 0x05A4 +#define REG_ATIMWND7 0x05A5 +#define REG_ATIMUGT 0x05A6 +#define REG_HIQ_NO_LMT_EN 0x05A7 +#define REG_DTIM_COUNTER_ROOT 0x05A8 +#define REG_DTIM_COUNTER_VAP1 0x05A9 +#define REG_DTIM_COUNTER_VAP2 0x05AA +#define REG_DTIM_COUNTER_VAP3 0x05AB +#define REG_DTIM_COUNTER_VAP4 0x05AC +#define REG_DTIM_COUNTER_VAP5 0x05AD +#define REG_DTIM_COUNTER_VAP6 0x05AE +#define REG_DTIM_COUNTER_VAP7 0x05AF +#define REG_DIS_ATIM 0x05B0 + +#define REG_EARLY_128US 0x05B1 +#define REG_P2PPS1_CTRL 0x05B2 +#define REG_P2PPS2_CTRL 0x05B3 +#define REG_TIMER0_SRC_SEL 0x05B4 +#define REG_NOA_UNIT_SEL 0x05B5 +#define REG_P2POFF_DIS_TXTIME 0x05B7 +#define REG_MBSSID_BCN_SPACE2 0x05B8 +#define REG_MBSSID_BCN_SPACE3 0x05BC + +#define REG_ACMHWCTRL 0x05C0 +#define REG_ACMRSTCTRL 0x05C1 +#define REG_ACMAVG 0x05C2 +#define REG_VO_ADMTIME 0x05C4 +#define REG_VI_ADMTIME 0x05C6 +#define REG_BE_ADMTIME 0x05C8 +#define REG_EDCA_RANDOM_GEN 0x05CC +#define REG_TXCMD_NOA_SEL 0x05CF +#define REG_NOA_PARAM 0x05E0 + +#define REG_NOA_PARAM_1 0x05E4 +#define REG_NOA_PARAM_2 0x05E8 +#define REG_NOA_PARAM_3 0x05EC + +#define REG_P2P_RST 0x05F0 +#define REG_SCHEDULER_RST 0x05F1 + +#define REG_SCH_TXCMD 0x05F8 +#define REG_PAGE5_DUMMY 0x05FC +#define REG_WMAC_CR 0x0600 + +#define REG_WMAC_FWPKT_CR 0x0601 + +#define REG_FW_STS_FILTER 0x0602 + +#define REG_BWOPMODE 0x0603 + +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG_1 0x0628 +#define REG_MBIDCAMCFG_2 0x062C + +#define REG_WMAC_TCR_TSFT_OFS 0x0630 +#define REG_UDF_THSD 0x0632 +#define REG_ZLD_NUM 0x0633 + +#define REG_STMP_THSD 0x0634 +#define REG_WMAC_TXTIMEOUT 0x0635 +#define REG_MCU_TEST_2_V1 0x0636 + +#define REG_USTIME_EDCA 0x0638 + +#define REG_ACKTO_CCK 0x0639 + +#define REG_MAC_SPEC_SIFS 0x063A +#define REG_RESP_SIFS_CCK 0x063C +#define REG_RESP_SIFS_OFDM 0x063E +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + +#define REG_RPFM_MAP0 0x0644 +#define REG_RPFM_MAP1 0x0646 +#define REG_RPFM_CAM_CMD 0x0648 +#define REG_RPFM_CAM_RWD 0x064C + +#define REG_NAV_CTRL 0x0650 +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 + +#define REG_WMAC_BACAM_RPMEN 0x0661 + +#define REG_TX_RX 0x0662 + +#define REG_WMAC_BITMAP_CTL 0x0663 + +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +#define REG_RXFILTER_CATEGORY_1 0x0682 +#define REG_RXFILTER_ACTION_1 0x0683 +#define REG_RXFILTER_CATEGORY_2 0x0684 +#define REG_RXFILTER_ACTION_2 0x0685 +#define REG_RXFILTER_CATEGORY_3 0x0686 +#define REG_RXFILTER_ACTION_3 0x0687 +#define REG_RXFLTMAP3 0x0688 +#define REG_RXFLTMAP4 0x068A +#define REG_RXFLTMAP5 0x068C +#define REG_RXFLTMAP6 0x068E + +#define REG_WOW_CTRL 0x0690 + +#define REG_NAN_RX_TSF_FILTER 0x0691 + +#define REG_PS_RX_INFO 0x0692 +#define REG_WMMPS_UAPSD_TID 0x0693 +#define REG_LPNAV_CTRL 0x0694 + +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_RWD 0x069C + +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 + +#define REG_FLC_RPC 0x06AC +#define REG_FLC_RPCT 0x06AD +#define REG_FLC_PTS 0x06AE +#define REG_FLC_TRPC 0x06AF + +#define REG_RXPKTMON_CTRL 0x06B0 + +#define REG_STATE_MON 0x06B4 + +#define REG_ERROR_MON 0x06B8 +#define REG_SEARCH_MACID 0x06BC + +#define REG_BT_COEX_TABLE 0x06C0 + +#define REG_RXCMD_0 0x06D0 +#define REG_RXCMD_1 0x06D4 + +#define REG_WMAC_RESP_TXINFO 0x06D8 + +#define REG_BBPSF_CTRL 0x06DC + +#define REG_P2P_RX_BCN_NOA 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO 0x06E4 +#define REG_ASSOCIATED_BFMER1_INFO 0x06EC +#define REG_TX_CSI_RPT_PARAM_BW20 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40 0x06F8 +#define REG_TX_CSI_RPT_PARAM_BW80 0x06FC +#define REG_MACID1 0x0700 + +#define REG_MACID1_1 0x0704 + +#define REG_BSSID1 0x0708 + +#define REG_BSSID1_1 0x070C + +#define REG_BCN_PSR_RPT1 0x0710 +#define REG_ASSOCIATED_BFMEE_SEL 0x0714 +#define REG_SND_PTCL_CTRL 0x0718 +#define REG_RX_CSI_RPT_INFO 0x071C +#define REG_NS_ARP_CTRL 0x0720 +#define REG_NS_ARP_INFO 0x0724 + +#define REG_BEAMFORMING_INFO_NSARP_V1 0x0728 + +#define REG_BEAMFORMING_INFO_NSARP 0x072C + +#define REG_IPV6 0x0730 +#define REG_IPV6_1 0x0734 +#define REG_IPV6_2 0x0738 +#define REG_IPV6_3 0x073C + +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG 0x0750 + +#define REG_WMAC_SWAES_CFG 0x0760 + +#define REG_BT_COEX_V2 0x0762 + +#define REG_BT_COEX 0x0764 + +#define REG_WLAN_ACT_MASK_CTRL 0x0768 + +#define REG_WLAN_ACT_MASK_CTRL_1 0x076C + +#define REG_BT_COEX_ENHANCED_INTR_CTRL 0x076E + +#define REG_BT_ACT_STATISTICS 0x0770 + +#define REG_BT_ACT_STATISTICS_1 0x0774 + +#define REG_BT_STATISTICS_CONTROL_REGISTER 0x0778 + +#define REG_BT_STATUS_REPORT_REGISTER 0x077C + +#define REG_BT_INTERRUPT_CONTROL_REGISTER 0x0780 + +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER 0x0784 + +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER 0x0785 + +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2 0x078C + +#define REG_BT_INTERRUPT_STATUS_REGISTER 0x078F + +#define REG_BT_TDMA_TIME_REGISTER 0x0790 + +#define REG_BT_ACT_REGISTER 0x0794 + +#define REG_OBFF_CTRL_BASIC 0x0798 + +#define REG_OBFF_CTRL2_TIMER 0x079C + +#define REG_LTR_CTRL_BASIC 0x07A0 + +#define REG_LTR_CTRL2_TIMER_THRESHOLD 0x07A4 + +#define REG_LTR_IDLE_LATENCY_V1 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1 0x07AC + +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER 0x07B0 + +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1 0x07B4 + +#define REG_WMAC_PKTCNT_RWD 0x07B8 +#define REG_WMAC_PKTCNT_CTRL 0x07BC + +#define REG_IQ_DUMP 0x07C0 + +#define REG_IQ_DUMP_1 0x07C4 +#define REG_IQ_DUMP_2 0x07C8 + +#define REG_WMAC_FTM_CTL 0x07CC + +#define REG_WMAC_IQ_MDPK_FUNC 0x07CE + +#define REG_WMAC_OPTION_FUNCTION 0x07D0 + +#define REG_WMAC_OPTION_FUNCTION_1 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2 0x07D8 + +#define REG_RX_FILTER_FUNCTION 0x07DA + +#define REG_NDP_SIG 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT 0x07E4 + +#define REG_TXCMD_INFO_FOR_RSP_PKT_1 0x07E8 + +#define REG_WSEC_OPTION 0x07EC + +#define REG_RTS_ADDRESS_0 0x07F0 + +#define REG_RTS_ADDRESS_0_1 0x07F4 + +#define REG_RTS_ADDRESS_1 0x07F8 + +#define REG_RTS_ADDRESS_1_1 0x07FC + +#define REG_SYS_CFG3 0x1000 +#define REG_SYS_CFG4 0x1034 + +#define REG_SYS_CFG5 0x1070 + +#define REG_CPU_DMEM_CON 0x1080 + +#define REG_BOOT_REASON 0x1088 +#define REG_NFCPAD_CTRL 0x10A8 + +#define REG_HIMR2 0x10B0 +#define REG_HISR2 0x10B4 +#define REG_HIMR3 0x10B8 +#define REG_HISR3 0x10BC +#define REG_SW_MDIO 0x10C0 +#define REG_SW_FLUSH 0x10C4 + +#define REG_H2C_PKT_READADDR 0x10D0 +#define REG_H2C_PKT_WRITEADDR 0x10D4 + +#define REG_MEM_PWR_CRTL 0x10D8 + +#define REG_FW_DBG0 0x10E0 +#define REG_FW_DBG1 0x10E4 +#define REG_FW_DBG2 0x10E8 +#define REG_FW_DBG3 0x10EC +#define REG_FW_DBG4 0x10F0 +#define REG_FW_DBG5 0x10F4 +#define REG_FW_DBG6 0x10F8 +#define REG_FW_DBG7 0x10FC +#define REG_CR_EXT 0x1100 +#define REG_FWFF 0x1114 + +#define REG_RXFF_PTR_V1 0x1118 +#define REG_RXFF_WTR_V1 0x111C + +#define REG_FE2IMR 0x1120 +#define REG_FE2ISR 0x1124 +#define REG_FE3IMR 0x1128 +#define REG_FE3ISR 0x112C +#define REG_FE4IMR 0x1130 +#define REG_FE4ISR 0x1134 +#define REG_FT1IMR 0x1138 +#define REG_FT1ISR 0x113C +#define REG_SPWR0 0x1140 +#define REG_SPWR1 0x1144 +#define REG_SPWR2 0x1148 +#define REG_SPWR3 0x114C +#define REG_POWSEQ 0x1150 + +#define REG_TC7_CTRL_V1 0x1158 +#define REG_TC8_CTRL_V1 0x115C + +#define REG_FT2IMR 0x11E0 +#define REG_FT2ISR 0x11E4 + +#define REG_MSG2 0x11F0 +#define REG_MSG3 0x11F4 +#define REG_MSG4 0x11F8 +#define REG_MSG5 0x11FC +#define REG_DDMA_CH0SA 0x1200 +#define REG_DDMA_CH0DA 0x1204 +#define REG_DDMA_CH0CTRL 0x1208 +#define REG_DDMA_CH1SA 0x1210 +#define REG_DDMA_CH1DA 0x1214 +#define REG_DDMA_CH1CTRL 0x1218 +#define REG_DDMA_CH2SA 0x1220 +#define REG_DDMA_CH2DA 0x1224 +#define REG_DDMA_CH2CTRL 0x1228 +#define REG_DDMA_CH3SA 0x1230 +#define REG_DDMA_CH3DA 0x1234 +#define REG_DDMA_CH3CTRL 0x1238 +#define REG_DDMA_CH4SA 0x1240 +#define REG_DDMA_CH4DA 0x1244 +#define REG_DDMA_CH4CTRL 0x1248 +#define REG_DDMA_CH5SA 0x1250 +#define REG_DDMA_CH5DA 0x1254 + +#define REG_DDMA_CH5CTRL 0x1258 + +#define REG_DDMA_INT_MSK 0x12E0 +#define REG_DDMA_CHSTATUS 0x12E8 +#define REG_DDMA_CHKSUM 0x12F0 +#define REG_DDMA_MONITOR 0x12FC + +#define REG_STC_INT_CS 0x1300 +#define REG_ST_INT_CFG 0x1304 +#define REG_CMU_DLY_CTRL 0x1310 +#define REG_CMU_DLY_CFG 0x1314 +#define REG_H2CQ_TXBD_DESA 0x1320 +#define REG_H2CQ_TXBD_NUM 0x1328 +#define REG_H2CQ_TXBD_IDX 0x132C +#define REG_H2CQ_CSR 0x1330 + +#define REG_Q0_Q1_INFO 0x1400 +#define REG_Q2_Q3_INFO 0x1404 +#define REG_Q4_Q5_INFO 0x1408 +#define REG_Q6_Q7_INFO 0x140C +#define REG_MGQ_HIQ_INFO 0x1410 +#define REG_CMDQ_BCNQ_INFO 0x1414 +#define REG_USEREG_SETTING 0x1420 +#define REG_AESIV_SETTING 0x1424 +#define REG_BF0_TIME_SETTING 0x1428 +#define REG_BF1_TIME_SETTING 0x142C +#define REG_BF_TIMEOUT_EN 0x1430 +#define REG_MACID_RELEASE0 0x1434 +#define REG_MACID_RELEASE1 0x1438 +#define REG_MACID_RELEASE2 0x143C +#define REG_MACID_RELEASE3 0x1440 +#define REG_MACID_RELEASE_SETTING 0x1444 +#define REG_FAST_EDCA_VOVI_SETTING 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING 0x144C +#define REG_MACID_DROP0 0x1450 +#define REG_MACID_DROP1 0x1454 +#define REG_MACID_DROP2 0x1458 +#define REG_MACID_DROP3 0x145C + +#define REG_R_MACID_RELEASE_SUCCESS_0 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3 0x146C +#define REG_MGG_FIFO_CRTL 0x1470 +#define REG_MGG_FIFO_INT 0x1474 +#define REG_MGG_FIFO_LIFETIME 0x1478 +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x147C + +#define REG_MU_TX_CTL 0x14C0 +#define REG_MU_STA_GID_VLD 0x14C4 +#define REG_MU_STA_USER_POS_INFO 0x14C8 +#define REG_MU_TRX_DBG_CNT 0x14D0 + +#define REG_CPUMGQ_TX_TIMER 0x1500 +#define REG_PS_TIMER_A 0x1504 +#define REG_PS_TIMER_B 0x1508 +#define REG_PS_TIMER_C 0x150C +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL 0x1510 +#define REG_CPUMGQ_TX_TIMER_EARLY 0x1514 +#define REG_PS_TIMER_A_EARLY 0x1515 +#define REG_PS_TIMER_B_EARLY 0x1516 +#define REG_PS_TIMER_C_EARLY 0x1517 + +#define REG_BCN_PSR_RPT2 0x1600 +#define REG_BCN_PSR_RPT3 0x1604 +#define REG_BCN_PSR_RPT4 0x1608 +#define REG_A1_ADDR_MASK 0x160C +#define REG_MACID2 0x1620 +#define REG_BSSID2 0x1628 +#define REG_MACID3 0x1630 +#define REG_BSSID3 0x1638 +#define REG_MACID4 0x1640 +#define REG_BSSID4 0x1648 + +#define REG_NOA_REPORT 0x1650 +#define REG_PWRBIT_SETTING 0x1660 +#define REG_WMAC_MU_BF_OPTION 0x167C + +#define REG_WMAC_PAUSE_BB_CLR_TH 0x167D + +#define REG_WMAC_MU_ARB 0x167E +#define REG_WMAC_MU_OPTION 0x167F +#define REG_WMAC_MU_BF_CTL 0x1680 + +#define REG_WMAC_MU_BIT_BFRPT_PARA 0x1682 + +#define REG_WMAC_ASSOCIATED_MU_BFMEE2 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7 0x168E + +#define REG_WMAC_BB_STOP_RX_COUNTER 0x1690 +#define REG_WMAC_PLCP_MONITOR 0x1694 +#define REG_WMAC_PLCP_MONITOR_MUTX 0x1698 + +#define REG_TRANSMIT_ADDRSS_0 0x16A0 +#define REG_TRANSMIT_ADDRSS_1 0x16A8 +#define REG_TRANSMIT_ADDRSS_2 0x16B0 +#define REG_TRANSMIT_ADDRSS_3 0x16B8 +#define REG_TRANSMIT_ADDRSS_4 0x16C0 + +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708 + +/* ----------------------------------------------------- */ +/* */ +/* 0xFB00h ~ 0xFCFFh TX/RX packet buffer affress */ +/* */ +/* ----------------------------------------------------- */ +#define REG_RXPKTBUF_STARTADDR 0xFB00 +#define REG_TXPKTBUF_STARTADDR 0xFC00 + +/* ----------------------------------------------------- */ +/* */ +/* 0xFD00h ~ 0xFDFFh 8051 CPU Local REG */ +/* */ +/* ----------------------------------------------------- */ +#define REG_SYS_CTRL 0xFD00 +#define REG_PONSTS_RPT1 0xFD01 +#define REG_PONSTS_RPT2 0xFD02 +#define REG_PONSTS_RPT3 0xFD03 +#define REG_PONSTS_RPT4 0xFD04 /* 0x84 */ +#define REG_PONSTS_RPT5 0xFD05 /* 0x85 */ +#define REG_8051ERRFLAG 0xFD08 +#define REG_8051ERRFLAG_MASK 0xFD09 +#define REG_TXADDRH 0xFD10 /* Tx Packet High Address */ +#define REG_RXADDRH 0xFD11 /* Rx Packet High Address */ +#define REG_TXADDRH_EXT 0xFD12 /* 0xFD12[0] : for 8051 access txpktbuf high64k as external register */ + +#define REG_U3_STATE 0xFD48 /* (Read only) [7:4] : usb3 changed last state. [3:0] usb3 state */ + +/* for MAILBOX */ +#define REG_OUTDATA0 0xFD50 +#define REG_OUTDATA1 0xFD54 +#define REG_OUTRDY 0xFD58 /* bit[0] : OutReady, bit[1] : OutEmptyIntEn */ + +#define REG_INDATA0 0xFD60 +#define REG_INDATA1 0xFD64 +#define REG_INRDY 0xFD68 /* bit[0] : InReady, bit[1] : InRdyIntEn */ + +/* MCU ERROR debug REG */ +#define REG_MCUERR_PCLSB 0xFD90 /* PC[7:0] */ +#define REG_MCUERR_PCMSB 0xFD91 /* PC[15:8] */ +#define REG_MCUERR_ACC 0xFD92 +#define REG_MCUERR_B 0xFD93 +#define REG_MCUERR_DPTRLSB 0xFD94 /* DPTR[7:0] */ +#define REG_MCUERR_DPTRMSB 0xFD95 /* DPTR[15:8] */ +#define REG_MCUERR_SP 0xFD96 /* SP[7:0] */ +#define REG_MCUERR_IE 0xFD97 /* IE[7:0] */ +#define REG_MCUERR_EIE 0xFD98 /* EIE[7:0] */ +#define REG_VERA_SIM 0xFD9F +/* 0xFD99~0xFD9F are reserved.. */ + +/* ----------------------------------------------------- */ +/* */ +/* 0xFE00h ~ 0xFEFFh USB Configuration */ +/* */ +/* ----------------------------------------------------- */ + +/* RTS5101 USB Register Definition */ +#define REG_USB_SETUP_DEC_INT 0xFE00 +#define REG_USB_DMACTL 0xFE01 +#define REG_USB_IRQSTAT0 0xFE02 +#define REG_USB_IRQSTAT1 0xFE03 +#define REG_USB_IRQEN0 0xFE04 +#define REG_USB_IRQEN1 0xFE05 +#define REG_USB_AUTOPTRL 0xFE06 +#define REG_USB_AUTOPTRH 0xFE07 +#define REG_USB_AUTODAT 0xFE08 + +#define REG_USB_SCRATCH0 0xFE09 +#define REG_USB_SCRATCH1 0xFE0A +#define REG_USB_SEEPROM 0xFE0B +#define REG_USB_GPIO0 0xFE0C +#define REG_USB_GPIO0DIR 0xFE0D +#define REG_USB_CLKSEL 0xFE0E +#define REG_USB_BOOTCTL 0xFE0F + +#define REG_USB_USBCTL 0xFE10 +#define REG_USB_USBSTAT 0xFE11 +#define REG_USB_DEVADDR 0xFE12 +#define REG_USB_USBTEST 0xFE13 +#define REG_USB_FNUM0 0xFE14 +#define REG_USB_FNUM1 0xFE15 + +#define REG_USB_EP_IDX 0xFE20 +#define REG_USB_EP_CFG 0xFE21 +#define REG_USB_EP_CTL 0xFE22 +#define REG_USB_EP_STAT 0xFE23 +#define REG_USB_EP_IRQ 0xFE24 +#define REG_USB_EP_IRQEN 0xFE25 +#define REG_USB_EP_MAXPKT0 0xFE26 +#define REG_USB_EP_MAXPKT1 0xFE27 +#define REG_USB_EP_DAT 0xFE28 +#define REG_USB_EP_BC0 0xFE29 +#define REG_USB_EP_BC1 0xFE2A +#define REG_USB_EP_TC0 0xFE2B +#define REG_USB_EP_TC1 0xFE2C +#define REG_USB_EP_TC2 0xFE2D +#define REG_USB_EP_CTL2 0xFE2E + +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_VID 0xFE60 +#define REG_USB_PID 0xFE62 +#define REG_USB_OPT 0xFE64 +#define REG_USB_CONFIG 0xFE65 /* RX EP setting. 0xFE65 Bit[3:0] : RXQ, Bit[7:4] : INTQ */ + /* TX EP setting. 0xFE66 Bit[3:0] : TXQ0, Bit[7:4] : TXQ1, 0xFE67 Bit[3:0] : TXQ2 */ +#define REG_USB_PHY_PARA1 0xFE68 /* Bit[7:4]: XCVR_SEN (USB PHY 0xE2[7:4]), Bit[3:0]: XCVR_SH (USB PHY 0xE2[3:0]) */ +#define REG_USB_PHY_PARA2 0xFE69 /* Bit[7:5]: XCVR_BG (USB PHY 0xE3[5:3]), Bit[4:2]: XCVR_DR (USB PHY 0xE3[2:0]), Bit[1]: SE0_LVL (USB PHY 0xE5[7]), Bit[0]: FORCE_XTL_ON (USB PHY 0xE5[1]) */ +#define REG_USB_PHY_PARA3 0xFE6A /* Bit[7:5]: XCVR_SRC (USB PHY 0xE5[4:2]), Bit[4]: LATE_DLLEN (USB PHY 0xF0[4]), Bit[3]: HS_LP_MODE (USB PHY 0xF0[3]), Bit[2]: UTMI_POS_OUT (USB PHY 0xF1 [7]), Bit[1:0]: TX_DELAY (USB PHY 0xF1 [2:1]) */ +#define REG_USB_PHY_PARA4 0xFE6B /* (USB PHY 0xE7[7:0]) */ +#define REG_USB_OPT2 0xFE6C +#define REG_USB_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ +#define REG_USB_MANUFACTURE_SETTING 0xFE80 /* 0xFE80~0xFE90 Max : 32 bytes */ +#define REG_USB_PRODUCT_STRING 0xFEA0 /* 0xFEA0~0xFECF Max : 48 bytes */ +#define REG_USB_SERIAL_NUMBER_STRING 0xFED0 /* 0xFED0~0xFEDF Max : 12 bytes */ + +#define REG_USB_ALTERNATE_SETTING 0xFE4F +#define REG_USB_INT_BINTERVAL 0xFE6E +#define REG_USB_GPS_EP_CONFIG 0xFE6D + +#endif /* __HALMAC_COM_REG_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_reg_8821c.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_reg_8821c.h new file mode 100644 index 000000000000..f47f17246fd8 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_reg_8821c.h @@ -0,0 +1,737 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_HALMAC_REG_8821C_H +#define __INC_HALMAC_REG_8821C_H + +#define REG_SYS_ISO_CTRL_8821C 0x0000 +#define REG_SYS_FUNC_EN_8821C 0x0002 +#define REG_SYS_PW_CTRL_8821C 0x0004 +#define REG_SYS_CLK_CTRL_8821C 0x0008 +#define REG_SYS_EEPROM_CTRL_8821C 0x000A +#define REG_EE_VPD_8821C 0x000C +#define REG_SYS_SWR_CTRL1_8821C 0x0010 +#define REG_SYS_SWR_CTRL2_8821C 0x0014 +#define REG_SYS_SWR_CTRL3_8821C 0x0018 +#define REG_RSV_CTRL_8821C 0x001C +#define REG_RF_CTRL_8821C 0x001F +#define REG_AFE_LDO_CTRL_8821C 0x0020 +#define REG_AFE_CTRL1_8821C 0x0024 +#define REG_AFE_CTRL2_8821C 0x0028 +#define REG_AFE_CTRL3_8821C 0x002C +#define REG_EFUSE_CTRL_8821C 0x0030 +#define REG_LDO_EFUSE_CTRL_8821C 0x0034 +#define REG_PWR_OPTION_CTRL_8821C 0x0038 +#define REG_CAL_TIMER_8821C 0x003C +#define REG_ACLK_MON_8821C 0x003E +#define REG_GPIO_MUXCFG_8821C 0x0040 +#define REG_GPIO_PIN_CTRL_8821C 0x0044 +#define REG_GPIO_INTM_8821C 0x0048 +#define REG_LED_CFG_8821C 0x004C +#define REG_FSIMR_8821C 0x0050 +#define REG_FSISR_8821C 0x0054 +#define REG_HSIMR_8821C 0x0058 +#define REG_HSISR_8821C 0x005C +#define REG_GPIO_EXT_CTRL_8821C 0x0060 +#define REG_PAD_CTRL1_8821C 0x0064 +#define REG_WL_BT_PWR_CTRL_8821C 0x0068 +#define REG_SDM_DEBUG_8821C 0x006C +#define REG_SYS_SDIO_CTRL_8821C 0x0070 +#define REG_HCI_OPT_CTRL_8821C 0x0074 +#define REG_AFE_CTRL4_8821C 0x0078 +#define REG_LDO_SWR_CTRL_8821C 0x007C +#define REG_MCUFW_CTRL_8821C 0x0080 +#define REG_MCU_TST_CFG_8821C 0x0084 +#define REG_HMEBOX_E0_E1_8821C 0x0088 +#define REG_HMEBOX_E2_E3_8821C 0x008C +#define REG_WLLPS_CTRL_8821C 0x0090 +#define REG_AFE_CTRL5_8821C 0x0094 +#define REG_GPIO_DEBOUNCE_CTRL_8821C 0x0098 +#define REG_RPWM2_8821C 0x009C +#define REG_SYSON_FSM_MON_8821C 0x00A0 +#define REG_AFE_CTRL6_8821C 0x00A4 +#define REG_PMC_DBG_CTRL1_8821C 0x00A8 +#define REG_AFE_CTRL7_8821C 0x00AC +#define REG_HIMR0_8821C 0x00B0 +#define REG_HISR0_8821C 0x00B4 +#define REG_HIMR1_8821C 0x00B8 +#define REG_HISR1_8821C 0x00BC +#define REG_DBG_PORT_SEL_8821C 0x00C0 +#define REG_PAD_CTRL2_8821C 0x00C4 +#define REG_PMC_DBG_CTRL2_8821C 0x00CC +#define REG_BIST_CTRL_8821C 0x00D0 +#define REG_BIST_RPT_8821C 0x00D4 +#define REG_MEM_CTRL_8821C 0x00D8 +#define REG_AFE_CTRL8_8821C 0x00DC +#define REG_USB_SIE_INTF_8821C 0x00E0 +#define REG_PCIE_MIO_INTF_8821C 0x00E4 +#define REG_PCIE_MIO_INTD_8821C 0x00E8 +#define REG_WLRF1_8821C 0x00EC +#define REG_SYS_CFG1_8821C 0x00F0 +#define REG_SYS_STATUS1_8821C 0x00F4 +#define REG_SYS_STATUS2_8821C 0x00F8 +#define REG_SYS_CFG2_8821C 0x00FC +#define REG_SYS_CFG3_8821C 0x1000 +#define REG_SYS_CFG4_8821C 0x1034 +#define REG_SYS_CFG5_8821C 0x1070 +#define REG_CPU_DMEM_CON_8821C 0x1080 +#define REG_BOOT_REASON_8821C 0x1088 +#define REG_NFCPAD_CTRL_8821C 0x10A8 +#define REG_HIMR2_8821C 0x10B0 +#define REG_HISR2_8821C 0x10B4 +#define REG_HIMR3_8821C 0x10B8 +#define REG_HISR3_8821C 0x10BC +#define REG_SW_MDIO_8821C 0x10C0 +#define REG_SW_FLUSH_8821C 0x10C4 +#define REG_H2C_PKT_READADDR_8821C 0x10D0 +#define REG_H2C_PKT_WRITEADDR_8821C 0x10D4 +#define REG_MEM_PWR_CRTL_8821C 0x10D8 +#define REG_FW_DBG0_8821C 0x10E0 +#define REG_FW_DBG1_8821C 0x10E4 +#define REG_FW_DBG2_8821C 0x10E8 +#define REG_FW_DBG3_8821C 0x10EC +#define REG_FW_DBG4_8821C 0x10F0 +#define REG_FW_DBG5_8821C 0x10F4 +#define REG_FW_DBG6_8821C 0x10F8 +#define REG_FW_DBG7_8821C 0x10FC +#define REG_CR_8821C 0x0100 +#define REG_PKT_BUFF_ACCESS_CTRL_8821C 0x0106 +#define REG_TSF_CLK_STATE_8821C 0x0108 +#define REG_TXDMA_PQ_MAP_8821C 0x010C +#define REG_TRXFF_BNDY_8821C 0x0114 +#define REG_PTA_I2C_MBOX_8821C 0x0118 +#define REG_RXFF_BNDY_8821C 0x011C +#define REG_FE1IMR_8821C 0x0120 +#define REG_FE1ISR_8821C 0x0124 +#define REG_CPWM_8821C 0x012C +#define REG_FWIMR_8821C 0x0130 +#define REG_FWISR_8821C 0x0134 +#define REG_FTIMR_8821C 0x0138 +#define REG_FTISR_8821C 0x013C +#define REG_PKTBUF_DBG_CTRL_8821C 0x0140 +#define REG_PKTBUF_DBG_DATA_L_8821C 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8821C 0x0148 +#define REG_CPWM2_8821C 0x014C +#define REG_TC0_CTRL_8821C 0x0150 +#define REG_TC1_CTRL_8821C 0x0154 +#define REG_TC2_CTRL_8821C 0x0158 +#define REG_TC3_CTRL_8821C 0x015C +#define REG_TC4_CTRL_8821C 0x0160 +#define REG_TCUNIT_BASE_8821C 0x0164 +#define REG_TC5_CTRL_8821C 0x0168 +#define REG_TC6_CTRL_8821C 0x016C +#define REG_MBIST_FAIL_8821C 0x0170 +#define REG_MBIST_START_PAUSE_8821C 0x0174 +#define REG_MBIST_DONE_8821C 0x0178 +#define REG_MBIST_FAIL_NRML_8821C 0x017C +#define REG_AES_DECRPT_DATA_8821C 0x0180 +#define REG_AES_DECRPT_CFG_8821C 0x0184 +#define REG_TMETER_8821C 0x0190 +#define REG_OSC_32K_CTRL_8821C 0x0194 +#define REG_32K_CAL_REG1_8821C 0x0198 +#define REG_C2HEVT_8821C 0x01A0 +#define REG_C2HEVT_1_8821C 0x01A4 +#define REG_C2HEVT_2_8821C 0x01A8 +#define REG_C2HEVT_3_8821C 0x01AC +#define REG_SW_DEFINED_PAGE1_8821C 0x01B8 +#define REG_SW_DEFINED_PAGE2_8821C 0x01BC +#define REG_MCUTST_I_8821C 0x01C0 +#define REG_MCUTST_II_8821C 0x01C4 +#define REG_FMETHR_8821C 0x01C8 +#define REG_HMETFR_8821C 0x01CC +#define REG_HMEBOX0_8821C 0x01D0 +#define REG_HMEBOX1_8821C 0x01D4 +#define REG_HMEBOX2_8821C 0x01D8 +#define REG_HMEBOX3_8821C 0x01DC +#define REG_LLT_INIT_8821C 0x01E0 +#define REG_LLT_INIT_ADDR_8821C 0x01E4 +#define REG_BB_ACCESS_CTRL_8821C 0x01E8 +#define REG_BB_ACCESS_DATA_8821C 0x01EC +#define REG_HMEBOX_E0_8821C 0x01F0 +#define REG_HMEBOX_E1_8821C 0x01F4 +#define REG_HMEBOX_E2_8821C 0x01F8 +#define REG_HMEBOX_E3_8821C 0x01FC +#define REG_CR_EXT_8821C 0x1100 +#define REG_FWFF_8821C 0x1114 +#define REG_RXFF_PTR_V1_8821C 0x1118 +#define REG_RXFF_WTR_V1_8821C 0x111C +#define REG_FE2IMR_8821C 0x1120 +#define REG_FE2ISR_8821C 0x1124 +#define REG_FE3IMR_8821C 0x1128 +#define REG_FE3ISR_8821C 0x112C +#define REG_FE4IMR_8821C 0x1130 +#define REG_FE4ISR_8821C 0x1134 +#define REG_FT1IMR_8821C 0x1138 +#define REG_FT1ISR_8821C 0x113C +#define REG_SPWR0_8821C 0x1140 +#define REG_SPWR1_8821C 0x1144 +#define REG_SPWR2_8821C 0x1148 +#define REG_SPWR3_8821C 0x114C +#define REG_POWSEQ_8821C 0x1150 +#define REG_TC7_CTRL_V1_8821C 0x1158 +#define REG_TC8_CTRL_V1_8821C 0x115C +#define REG_FT2IMR_8821C 0x11E0 +#define REG_FT2ISR_8821C 0x11E4 +#define REG_MSG2_8821C 0x11F0 +#define REG_MSG3_8821C 0x11F4 +#define REG_MSG4_8821C 0x11F8 +#define REG_MSG5_8821C 0x11FC +#define REG_FIFOPAGE_CTRL_1_8821C 0x0200 +#define REG_FIFOPAGE_CTRL_2_8821C 0x0204 +#define REG_AUTO_LLT_V1_8821C 0x0208 +#define REG_TXDMA_OFFSET_CHK_8821C 0x020C +#define REG_TXDMA_STATUS_8821C 0x0210 +#define REG_TX_DMA_DBG_8821C 0x0214 +#define REG_TQPNT1_8821C 0x0218 +#define REG_TQPNT2_8821C 0x021C +#define REG_TQPNT3_8821C 0x0220 +#define REG_TQPNT4_8821C 0x0224 +#define REG_RQPN_CTRL_1_8821C 0x0228 +#define REG_RQPN_CTRL_2_8821C 0x022C +#define REG_FIFOPAGE_INFO_1_8821C 0x0230 +#define REG_FIFOPAGE_INFO_2_8821C 0x0234 +#define REG_FIFOPAGE_INFO_3_8821C 0x0238 +#define REG_FIFOPAGE_INFO_4_8821C 0x023C +#define REG_FIFOPAGE_INFO_5_8821C 0x0240 +#define REG_H2C_HEAD_8821C 0x0244 +#define REG_H2C_TAIL_8821C 0x0248 +#define REG_H2C_READ_ADDR_8821C 0x024C +#define REG_H2C_WR_ADDR_8821C 0x0250 +#define REG_H2C_INFO_8821C 0x0254 +#define REG_RXDMA_AGG_PG_TH_8821C 0x0280 +#define REG_RXPKT_NUM_8821C 0x0284 +#define REG_RXDMA_STATUS_8821C 0x0288 +#define REG_RXDMA_DPR_8821C 0x028C +#define REG_RXDMA_MODE_8821C 0x0290 +#define REG_C2H_PKT_8821C 0x0294 +#define REG_FWFF_C2H_8821C 0x0298 +#define REG_FWFF_CTRL_8821C 0x029C +#define REG_FWFF_PKT_INFO_8821C 0x02A0 +#define REG_DDMA_CH0SA_8821C 0x1200 +#define REG_DDMA_CH0DA_8821C 0x1204 +#define REG_DDMA_CH0CTRL_8821C 0x1208 +#define REG_DDMA_CH1SA_8821C 0x1210 +#define REG_DDMA_CH1DA_8821C 0x1214 +#define REG_DDMA_CH1CTRL_8821C 0x1218 +#define REG_DDMA_CH2SA_8821C 0x1220 +#define REG_DDMA_CH2DA_8821C 0x1224 +#define REG_DDMA_CH2CTRL_8821C 0x1228 +#define REG_DDMA_CH3SA_8821C 0x1230 +#define REG_DDMA_CH3DA_8821C 0x1234 +#define REG_DDMA_CH3CTRL_8821C 0x1238 +#define REG_DDMA_CH4SA_8821C 0x1240 +#define REG_DDMA_CH4DA_8821C 0x1244 +#define REG_DDMA_CH4CTRL_8821C 0x1248 +#define REG_DDMA_CH5SA_8821C 0x1250 +#define REG_DDMA_CH5DA_8821C 0x1254 +#define REG_DDMA_CH5CTRL_8821C 0x1258 +#define REG_DDMA_INT_MSK_8821C 0x12E0 +#define REG_DDMA_CHSTATUS_8821C 0x12E8 +#define REG_DDMA_CHKSUM_8821C 0x12F0 +#define REG_DDMA_MONITOR_8821C 0x12FC +#define REG_PCIE_CTRL_8821C 0x0300 +#define REG_INT_MIG_8821C 0x0304 +#define REG_BCNQ_TXBD_DESA_8821C 0x0308 +#define REG_MGQ_TXBD_DESA_8821C 0x0310 +#define REG_VOQ_TXBD_DESA_8821C 0x0318 +#define REG_VIQ_TXBD_DESA_8821C 0x0320 +#define REG_BEQ_TXBD_DESA_8821C 0x0328 +#define REG_BKQ_TXBD_DESA_8821C 0x0330 +#define REG_RXQ_RXBD_DESA_8821C 0x0338 +#define REG_HI0Q_TXBD_DESA_8821C 0x0340 +#define REG_HI1Q_TXBD_DESA_8821C 0x0348 +#define REG_HI2Q_TXBD_DESA_8821C 0x0350 +#define REG_HI3Q_TXBD_DESA_8821C 0x0358 +#define REG_HI4Q_TXBD_DESA_8821C 0x0360 +#define REG_HI5Q_TXBD_DESA_8821C 0x0368 +#define REG_HI6Q_TXBD_DESA_8821C 0x0370 +#define REG_HI7Q_TXBD_DESA_8821C 0x0378 +#define REG_MGQ_TXBD_NUM_8821C 0x0380 +#define REG_RX_RXBD_NUM_8821C 0x0382 +#define REG_VOQ_TXBD_NUM_8821C 0x0384 +#define REG_VIQ_TXBD_NUM_8821C 0x0386 +#define REG_BEQ_TXBD_NUM_8821C 0x0388 +#define REG_BKQ_TXBD_NUM_8821C 0x038A +#define REG_HI0Q_TXBD_NUM_8821C 0x038C +#define REG_HI1Q_TXBD_NUM_8821C 0x038E +#define REG_HI2Q_TXBD_NUM_8821C 0x0390 +#define REG_HI3Q_TXBD_NUM_8821C 0x0392 +#define REG_HI4Q_TXBD_NUM_8821C 0x0394 +#define REG_HI5Q_TXBD_NUM_8821C 0x0396 +#define REG_HI6Q_TXBD_NUM_8821C 0x0398 +#define REG_HI7Q_TXBD_NUM_8821C 0x039A +#define REG_TSFTIMER_HCI_8821C 0x039C +#define REG_BD_RWPTR_CLR_8821C 0x039C +#define REG_VOQ_TXBD_IDX_8821C 0x03A0 +#define REG_VIQ_TXBD_IDX_8821C 0x03A4 +#define REG_BEQ_TXBD_IDX_8821C 0x03A8 +#define REG_BKQ_TXBD_IDX_8821C 0x03AC +#define REG_MGQ_TXBD_IDX_8821C 0x03B0 +#define REG_RXQ_RXBD_IDX_8821C 0x03B4 +#define REG_HI0Q_TXBD_IDX_8821C 0x03B8 +#define REG_HI1Q_TXBD_IDX_8821C 0x03BC +#define REG_HI2Q_TXBD_IDX_8821C 0x03C0 +#define REG_HI3Q_TXBD_IDX_8821C 0x03C4 +#define REG_HI4Q_TXBD_IDX_8821C 0x03C8 +#define REG_HI5Q_TXBD_IDX_8821C 0x03CC +#define REG_HI6Q_TXBD_IDX_8821C 0x03D0 +#define REG_HI7Q_TXBD_IDX_8821C 0x03D4 +#define REG_DBG_SEL_V1_8821C 0x03D8 +#define REG_PCIE_HRPWM1_V1_8821C 0x03D9 +#define REG_PCIE_HCPWM1_V1_8821C 0x03DA +#define REG_PCIE_CTRL2_8821C 0x03DB +#define REG_PCIE_HRPWM2_V1_8821C 0x03DC +#define REG_PCIE_HCPWM2_V1_8821C 0x03DE +#define REG_PCIE_H2C_MSG_V1_8821C 0x03E0 +#define REG_PCIE_C2H_MSG_V1_8821C 0x03E4 +#define REG_DBI_WDATA_V1_8821C 0x03E8 +#define REG_DBI_RDATA_V1_8821C 0x03EC +#define REG_DBI_FLAG_V1_8821C 0x03F0 +#define REG_MDIO_V1_8821C 0x03F4 +#define REG_PCIE_MIX_CFG_8821C 0x03F8 +#define REG_HCI_MIX_CFG_8821C 0x03FC +#define REG_STC_INT_CS_8821C 0x1300 +#define REG_ST_INT_CFG_8821C 0x1304 +#define REG_CMU_DLY_CTRL_8821C 0x1310 +#define REG_CMU_DLY_CFG_8821C 0x1314 +#define REG_H2CQ_TXBD_DESA_8821C 0x1320 +#define REG_H2CQ_TXBD_NUM_8821C 0x1328 +#define REG_H2CQ_TXBD_IDX_8821C 0x132C +#define REG_H2CQ_CSR_8821C 0x1330 +#define REG_Q0_INFO_8821C 0x0400 +#define REG_Q1_INFO_8821C 0x0404 +#define REG_Q2_INFO_8821C 0x0408 +#define REG_Q3_INFO_8821C 0x040C +#define REG_MGQ_INFO_8821C 0x0410 +#define REG_HIQ_INFO_8821C 0x0414 +#define REG_BCNQ_INFO_8821C 0x0418 +#define REG_TXPKT_EMPTY_8821C 0x041A +#define REG_CPU_MGQ_INFO_8821C 0x041C +#define REG_FWHW_TXQ_CTRL_8821C 0x0420 +#define REG_DATAFB_SEL_8821C 0x0423 +#define REG_BCNQ_BDNY_V1_8821C 0x0424 +#define REG_LIFETIME_EN_8821C 0x0426 +#define REG_SPEC_SIFS_8821C 0x0428 +#define REG_RETRY_LIMIT_8821C 0x042A +#define REG_TXBF_CTRL_8821C 0x042C +#define REG_DARFRC_8821C 0x0430 +#define REG_RARFRC_8821C 0x0438 +#define REG_RRSR_8821C 0x0440 +#define REG_ARFR0_8821C 0x0444 +#define REG_ARFR1_V1_8821C 0x044C +#define REG_CCK_CHECK_8821C 0x0454 +#define REG_AMPDU_MAX_TIME_V1_8821C 0x0455 +#define REG_BCNQ1_BDNY_V1_8821C 0x0456 +#define REG_AMPDU_MAX_LENGTH_8821C 0x0458 +#define REG_ACQ_STOP_8821C 0x045C +#define REG_NDPA_RATE_8821C 0x045D +#define REG_TX_HANG_CTRL_8821C 0x045E +#define REG_NDPA_OPT_CTRL_8821C 0x045F +#define REG_RD_RESP_PKT_TH_8821C 0x0463 +#define REG_CMDQ_INFO_8821C 0x0464 +#define REG_Q4_INFO_8821C 0x0468 +#define REG_Q5_INFO_8821C 0x046C +#define REG_Q6_INFO_8821C 0x0470 +#define REG_Q7_INFO_8821C 0x0474 +#define REG_WMAC_LBK_BUF_HD_V1_8821C 0x0478 +#define REG_MGQ_BDNY_V1_8821C 0x047A +#define REG_TXRPT_CTRL_8821C 0x047C +#define REG_INIRTS_RATE_SEL_8821C 0x0480 +#define REG_BASIC_CFEND_RATE_8821C 0x0481 +#define REG_STBC_CFEND_RATE_8821C 0x0482 +#define REG_DATA_SC_8821C 0x0483 +#define REG_MACID_SLEEP3_8821C 0x0484 +#define REG_MACID_SLEEP1_8821C 0x0488 +#define REG_ARFR2_V1_8821C 0x048C +#define REG_ARFR3_V1_8821C 0x0494 +#define REG_ARFR4_8821C 0x049C +#define REG_ARFR5_8821C 0x04A4 +#define REG_TXRPT_START_OFFSET_8821C 0x04AC +#define REG_POWER_STAGE1_8821C 0x04B4 +#define REG_POWER_STAGE2_8821C 0x04B8 +#define REG_SW_AMPDU_BURST_MODE_CTRL_8821C 0x04BC +#define REG_PKT_LIFE_TIME_8821C 0x04C0 +#define REG_STBC_SETTING_8821C 0x04C4 +#define REG_STBC_SETTING2_8821C 0x04C5 +#define REG_QUEUE_CTRL_8821C 0x04C6 +#define REG_SINGLE_AMPDU_CTRL_8821C 0x04C7 +#define REG_PROT_MODE_CTRL_8821C 0x04C8 +#define REG_BAR_MODE_CTRL_8821C 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8821C 0x04CF +#define REG_MACID_SLEEP2_8821C 0x04D0 +#define REG_MACID_SLEEP_8821C 0x04D4 +#define REG_HW_SEQ0_8821C 0x04D8 +#define REG_HW_SEQ1_8821C 0x04DA +#define REG_HW_SEQ2_8821C 0x04DC +#define REG_HW_SEQ3_8821C 0x04DE +#define REG_NULL_PKT_STATUS_V1_8821C 0x04E0 +#define REG_PTCL_ERR_STATUS_8821C 0x04E2 +#define REG_NULL_PKT_STATUS_EXTEND_8821C 0x04E3 +#define REG_VIDEO_ENHANCEMENT_FUN_8821C 0x04E4 +#define REG_BT_POLLUTE_PKT_CNT_8821C 0x04E8 +#define REG_PTCL_DBG_8821C 0x04EC +#define REG_CPUMGQ_TIMER_CTRL2_8821C 0x04F4 +#define REG_DUMMY_PAGE4_V1_8821C 0x04FC +#define REG_MOREDATA_8821C 0x04FE +#define REG_Q0_Q1_INFO_8821C 0x1400 +#define REG_Q2_Q3_INFO_8821C 0x1404 +#define REG_Q4_Q5_INFO_8821C 0x1408 +#define REG_Q6_Q7_INFO_8821C 0x140C +#define REG_MGQ_HIQ_INFO_8821C 0x1410 +#define REG_CMDQ_BCNQ_INFO_8821C 0x1414 +#define REG_USEREG_SETTING_8821C 0x1420 +#define REG_AESIV_SETTING_8821C 0x1424 +#define REG_BF0_TIME_SETTING_8821C 0x1428 +#define REG_BF1_TIME_SETTING_8821C 0x142C +#define REG_BF_TIMEOUT_EN_8821C 0x1430 +#define REG_MACID_RELEASE0_8821C 0x1434 +#define REG_MACID_RELEASE1_8821C 0x1438 +#define REG_MACID_RELEASE2_8821C 0x143C +#define REG_MACID_RELEASE3_8821C 0x1440 +#define REG_MACID_RELEASE_SETTING_8821C 0x1444 +#define REG_FAST_EDCA_VOVI_SETTING_8821C 0x1448 +#define REG_FAST_EDCA_BEBK_SETTING_8821C 0x144C +#define REG_MACID_DROP0_8821C 0x1450 +#define REG_MACID_DROP1_8821C 0x1454 +#define REG_MACID_DROP2_8821C 0x1458 +#define REG_MACID_DROP3_8821C 0x145C +#define REG_R_MACID_RELEASE_SUCCESS_0_8821C 0x1460 +#define REG_R_MACID_RELEASE_SUCCESS_1_8821C 0x1464 +#define REG_R_MACID_RELEASE_SUCCESS_2_8821C 0x1468 +#define REG_R_MACID_RELEASE_SUCCESS_3_8821C 0x146C +#define REG_MGG_FIFO_CRTL_8821C 0x1470 +#define REG_MGG_FIFO_INT_8821C 0x1474 +#define REG_MGG_FIFO_LIFETIME_8821C 0x1478 +#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8821C 0x147C +#define REG_MU_TX_CTL_8821C 0x14C0 +#define REG_MU_STA_GID_VLD_8821C 0x14C4 +#define REG_MU_STA_USER_POS_INFO_8821C 0x14C8 +#define REG_MU_TRX_DBG_CNT_8821C 0x14D0 +#define REG_EDCA_VO_PARAM_8821C 0x0500 +#define REG_EDCA_VI_PARAM_8821C 0x0504 +#define REG_EDCA_BE_PARAM_8821C 0x0508 +#define REG_EDCA_BK_PARAM_8821C 0x050C +#define REG_BCNTCFG_8821C 0x0510 +#define REG_PIFS_8821C 0x0512 +#define REG_RDG_PIFS_8821C 0x0513 +#define REG_SIFS_8821C 0x0514 +#define REG_TSFTR_SYN_OFFSET_8821C 0x0518 +#define REG_AGGR_BREAK_TIME_8821C 0x051A +#define REG_SLOT_8821C 0x051B +#define REG_TX_PTCL_CTRL_8821C 0x0520 +#define REG_TXPAUSE_8821C 0x0522 +#define REG_DIS_TXREQ_CLR_8821C 0x0523 +#define REG_RD_CTRL_8821C 0x0524 +#define REG_MBSSID_CTRL_8821C 0x0526 +#define REG_P2PPS_CTRL_8821C 0x0527 +#define REG_PKT_LIFETIME_CTRL_8821C 0x0528 +#define REG_P2PPS_SPEC_STATE_8821C 0x052B +#define REG_BAR_TX_CTRL_8821C 0x0530 +#define REG_TBTT_PROHIBIT_8821C 0x0540 +#define REG_P2PPS_STATE_8821C 0x0543 +#define REG_RD_NAV_NXT_8821C 0x0544 +#define REG_NAV_PROT_LEN_8821C 0x0546 +#define REG_BCN_CTRL_8821C 0x0550 +#define REG_BCN_CTRL_CLINT0_8821C 0x0551 +#define REG_MBID_NUM_8821C 0x0552 +#define REG_DUAL_TSF_RST_8821C 0x0553 +#define REG_MBSSID_BCN_SPACE_8821C 0x0554 +#define REG_DRVERLYINT_8821C 0x0558 +#define REG_BCNDMATIM_8821C 0x0559 +#define REG_ATIMWND_8821C 0x055A +#define REG_USTIME_TSF_8821C 0x055C +#define REG_BCN_MAX_ERR_8821C 0x055D +#define REG_RXTSF_OFFSET_CCK_8821C 0x055E +#define REG_RXTSF_OFFSET_OFDM_8821C 0x055F +#define REG_TSFTR_8821C 0x0560 +#define REG_TSFTR_1_8821C 0x0564 +#define REG_FREERUN_CNT_8821C 0x0568 +#define REG_FREERUN_CNT_1_8821C 0x056C +#define REG_ATIMWND1_V1_8821C 0x0570 +#define REG_TBTT_PROHIBIT_INFRA_8821C 0x0571 +#define REG_CTWND_8821C 0x0572 +#define REG_BCNIVLCUNT_8821C 0x0573 +#define REG_BCNDROPCTRL_8821C 0x0574 +#define REG_HGQ_TIMEOUT_PERIOD_8821C 0x0575 +#define REG_TXCMD_TIMEOUT_PERIOD_8821C 0x0576 +#define REG_MISC_CTRL_8821C 0x0577 +#define REG_BCN_CTRL_CLINT1_8821C 0x0578 +#define REG_BCN_CTRL_CLINT2_8821C 0x0579 +#define REG_BCN_CTRL_CLINT3_8821C 0x057A +#define REG_EXTEND_CTRL_8821C 0x057B +#define REG_P2PPS1_SPEC_STATE_8821C 0x057C +#define REG_P2PPS1_STATE_8821C 0x057D +#define REG_P2PPS2_SPEC_STATE_8821C 0x057E +#define REG_P2PPS2_STATE_8821C 0x057F +#define REG_PS_TIMER0_8821C 0x0580 +#define REG_PS_TIMER1_8821C 0x0584 +#define REG_PS_TIMER2_8821C 0x0588 +#define REG_TBTT_CTN_AREA_8821C 0x058C +#define REG_FORCE_BCN_IFS_8821C 0x058E +#define REG_TXOP_MIN_8821C 0x0590 +#define REG_PRE_BKF_TIME_8821C 0x0592 +#define REG_CROSS_TXOP_CTRL_8821C 0x0593 +#define REG_ATIMWND2_8821C 0x05A0 +#define REG_ATIMWND3_8821C 0x05A1 +#define REG_ATIMWND4_8821C 0x05A2 +#define REG_ATIMWND5_8821C 0x05A3 +#define REG_ATIMWND6_8821C 0x05A4 +#define REG_ATIMWND7_8821C 0x05A5 +#define REG_ATIMUGT_8821C 0x05A6 +#define REG_HIQ_NO_LMT_EN_8821C 0x05A7 +#define REG_DTIM_COUNTER_ROOT_8821C 0x05A8 +#define REG_DTIM_COUNTER_VAP1_8821C 0x05A9 +#define REG_DTIM_COUNTER_VAP2_8821C 0x05AA +#define REG_DTIM_COUNTER_VAP3_8821C 0x05AB +#define REG_DTIM_COUNTER_VAP4_8821C 0x05AC +#define REG_DTIM_COUNTER_VAP5_8821C 0x05AD +#define REG_DTIM_COUNTER_VAP6_8821C 0x05AE +#define REG_DTIM_COUNTER_VAP7_8821C 0x05AF +#define REG_DIS_ATIM_8821C 0x05B0 +#define REG_EARLY_128US_8821C 0x05B1 +#define REG_P2PPS1_CTRL_8821C 0x05B2 +#define REG_P2PPS2_CTRL_8821C 0x05B3 +#define REG_TIMER0_SRC_SEL_8821C 0x05B4 +#define REG_NOA_UNIT_SEL_8821C 0x05B5 +#define REG_P2POFF_DIS_TXTIME_8821C 0x05B7 +#define REG_MBSSID_BCN_SPACE2_8821C 0x05B8 +#define REG_MBSSID_BCN_SPACE3_8821C 0x05BC +#define REG_ACMHWCTRL_8821C 0x05C0 +#define REG_ACMRSTCTRL_8821C 0x05C1 +#define REG_ACMAVG_8821C 0x05C2 +#define REG_VO_ADMTIME_8821C 0x05C4 +#define REG_VI_ADMTIME_8821C 0x05C6 +#define REG_BE_ADMTIME_8821C 0x05C8 +#define REG_EDCA_RANDOM_GEN_8821C 0x05CC +#define REG_TXCMD_NOA_SEL_8821C 0x05CF +#define REG_NOA_PARAM_8821C 0x05E0 +#define REG_NOA_PARAM_1_8821C 0x05E4 +#define REG_NOA_PARAM_2_8821C 0x05E8 +#define REG_NOA_PARAM_3_8821C 0x05EC +#define REG_P2P_RST_8821C 0x05F0 +#define REG_SCHEDULER_RST_8821C 0x05F1 +#define REG_SCH_TXCMD_8821C 0x05F8 +#define REG_PAGE5_DUMMY_8821C 0x05FC +#define REG_CPUMGQ_TX_TIMER_8821C 0x1500 +#define REG_PS_TIMER_A_8821C 0x1504 +#define REG_PS_TIMER_B_8821C 0x1508 +#define REG_PS_TIMER_C_8821C 0x150C +#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8821C 0x1510 +#define REG_CPUMGQ_TX_TIMER_EARLY_8821C 0x1514 +#define REG_PS_TIMER_A_EARLY_8821C 0x1515 +#define REG_PS_TIMER_B_EARLY_8821C 0x1516 +#define REG_PS_TIMER_C_EARLY_8821C 0x1517 +#define REG_WMAC_CR_8821C 0x0600 +#define REG_WMAC_FWPKT_CR_8821C 0x0601 +#define REG_FW_STS_FILTER_8821C 0x0602 +#define REG_BWOPMODE_8821C 0x0603 +#define REG_TCR_8821C 0x0604 +#define REG_RCR_8821C 0x0608 +#define REG_RX_PKT_LIMIT_8821C 0x060C +#define REG_RX_DLK_TIME_8821C 0x060D +#define REG_RX_DRVINFO_SZ_8821C 0x060F +#define REG_MACID_8821C 0x0610 +#define REG_BSSID_8821C 0x0618 +#define REG_MAR_8821C 0x0620 +#define REG_MBIDCAMCFG_1_8821C 0x0628 +#define REG_MBIDCAMCFG_2_8821C 0x062C +#define REG_WMAC_TCR_TSFT_OFS_8821C 0x0630 +#define REG_UDF_THSD_8821C 0x0632 +#define REG_ZLD_NUM_8821C 0x0633 +#define REG_STMP_THSD_8821C 0x0634 +#define REG_WMAC_TXTIMEOUT_8821C 0x0635 +#define REG_MCU_TEST_2_V1_8821C 0x0636 +#define REG_USTIME_EDCA_8821C 0x0638 +#define REG_ACKTO_CCK_8821C 0x0639 +#define REG_MAC_SPEC_SIFS_8821C 0x063A +#define REG_RESP_SIFS_CCK_8821C 0x063C +#define REG_RESP_SIFS_OFDM_8821C 0x063E +#define REG_ACKTO_8821C 0x0640 +#define REG_CTS2TO_8821C 0x0641 +#define REG_EIFS_8821C 0x0642 +#define REG_RPFM_MAP0_8821C 0x0644 +#define REG_RPFM_MAP1_8821C 0x0646 +#define REG_RPFM_CAM_CMD_8821C 0x0648 +#define REG_RPFM_CAM_RWD_8821C 0x064C +#define REG_NAV_CTRL_8821C 0x0650 +#define REG_BACAMCMD_8821C 0x0654 +#define REG_BACAMCONTENT_8821C 0x0658 +#define REG_LBDLY_8821C 0x0660 +#define REG_WMAC_BACAM_RPMEN_8821C 0x0661 +#define REG_TX_RX_8821C 0x0662 +#define REG_WMAC_BITMAP_CTL_8821C 0x0663 +#define REG_RXERR_RPT_8821C 0x0664 +#define REG_WMAC_TRXPTCL_CTL_8821C 0x0668 +#define REG_CAMCMD_8821C 0x0670 +#define REG_CAMWRITE_8821C 0x0674 +#define REG_CAMREAD_8821C 0x0678 +#define REG_CAMDBG_8821C 0x067C +#define REG_SECCFG_8821C 0x0680 +#define REG_RXFILTER_CATEGORY_1_8821C 0x0682 +#define REG_RXFILTER_ACTION_1_8821C 0x0683 +#define REG_RXFILTER_CATEGORY_2_8821C 0x0684 +#define REG_RXFILTER_ACTION_2_8821C 0x0685 +#define REG_RXFILTER_CATEGORY_3_8821C 0x0686 +#define REG_RXFILTER_ACTION_3_8821C 0x0687 +#define REG_RXFLTMAP3_8821C 0x0688 +#define REG_RXFLTMAP4_8821C 0x068A +#define REG_RXFLTMAP5_8821C 0x068C +#define REG_RXFLTMAP6_8821C 0x068E +#define REG_WOW_CTRL_8821C 0x0690 +#define REG_NAN_RX_TSF_FILTER_8821C 0x0691 +#define REG_PS_RX_INFO_8821C 0x0692 +#define REG_WMMPS_UAPSD_TID_8821C 0x0693 +#define REG_LPNAV_CTRL_8821C 0x0694 +#define REG_WKFMCAM_CMD_8821C 0x0698 +#define REG_WKFMCAM_RWD_8821C 0x069C +#define REG_RXFLTMAP0_8821C 0x06A0 +#define REG_RXFLTMAP1_8821C 0x06A2 +#define REG_RXFLTMAP_8821C 0x06A4 +#define REG_BCN_PSR_RPT_8821C 0x06A8 +#define REG_FLC_RPC_8821C 0x06AC +#define REG_FLC_RPCT_8821C 0x06AD +#define REG_FLC_PTS_8821C 0x06AE +#define REG_FLC_TRPC_8821C 0x06AF +#define REG_RXPKTMON_CTRL_8821C 0x06B0 +#define REG_STATE_MON_8821C 0x06B4 +#define REG_ERROR_MON_8821C 0x06B8 +#define REG_SEARCH_MACID_8821C 0x06BC +#define REG_BT_COEX_TABLE_8821C 0x06C0 +#define REG_RXCMD_0_8821C 0x06D0 +#define REG_RXCMD_1_8821C 0x06D4 +#define REG_WMAC_RESP_TXINFO_8821C 0x06D8 +#define REG_BBPSF_CTRL_8821C 0x06DC +#define REG_P2P_RX_BCN_NOA_8821C 0x06E0 +#define REG_ASSOCIATED_BFMER0_INFO_8821C 0x06E4 +#define REG_ASSOCIATED_BFMER1_INFO_8821C 0x06EC +#define REG_TX_CSI_RPT_PARAM_BW20_8821C 0x06F4 +#define REG_TX_CSI_RPT_PARAM_BW40_8821C 0x06F8 +#define REG_TX_CSI_RPT_PARAM_BW80_8821C 0x06FC +#define REG_BCN_PSR_RPT2_8821C 0x1600 +#define REG_BCN_PSR_RPT3_8821C 0x1604 +#define REG_BCN_PSR_RPT4_8821C 0x1608 +#define REG_A1_ADDR_MASK_8821C 0x160C +#define REG_MACID2_8821C 0x1620 +#define REG_BSSID2_8821C 0x1628 +#define REG_MACID3_8821C 0x1630 +#define REG_BSSID3_8821C 0x1638 +#define REG_MACID4_8821C 0x1640 +#define REG_BSSID4_8821C 0x1648 +#define REG_NOA_REPORT_8821C 0x1650 +#define REG_PWRBIT_SETTING_8821C 0x1660 +#define REG_WMAC_MU_BF_OPTION_8821C 0x167C +#define REG_WMAC_PAUSE_BB_CLR_TH_8821C 0x167D +#define REG_WMAC_MU_ARB_8821C 0x167E +#define REG_WMAC_MU_OPTION_8821C 0x167F +#define REG_WMAC_MU_BF_CTL_8821C 0x1680 +#define REG_WMAC_MU_BIT_BFRPT_PARA_8821C 0x1682 +#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8821C 0x1684 +#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8821C 0x1686 +#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8821C 0x1688 +#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8821C 0x168A +#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8821C 0x168C +#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8821C 0x168E +#define REG_WMAC_BB_STOP_RX_COUNTER_8821C 0x1690 +#define REG_WMAC_PLCP_MONITOR_8821C 0x1694 +#define REG_WMAC_PLCP_MONITOR_MUTX_8821C 0x1698 +#define REG_TRANSMIT_ADDRSS_0_8821C 0x16A0 +#define REG_TRANSMIT_ADDRSS_1_8821C 0x16A8 +#define REG_TRANSMIT_ADDRSS_2_8821C 0x16B0 +#define REG_TRANSMIT_ADDRSS_3_8821C 0x16B8 +#define REG_TRANSMIT_ADDRSS_4_8821C 0x16C0 +#define REG_MACID1_8821C 0x0700 +#define REG_MACID1_1_8821C 0x0704 +#define REG_BSSID1_8821C 0x0708 +#define REG_BSSID1_1_8821C 0x070C +#define REG_BCN_PSR_RPT1_8821C 0x0710 +#define REG_ASSOCIATED_BFMEE_SEL_8821C 0x0714 +#define REG_SND_PTCL_CTRL_8821C 0x0718 +#define REG_RX_CSI_RPT_INFO_8821C 0x071C +#define REG_NS_ARP_CTRL_8821C 0x0720 +#define REG_NS_ARP_INFO_8821C 0x0724 +#define REG_BEAMFORMING_INFO_NSARP_V1_8821C 0x0728 +#define REG_BEAMFORMING_INFO_NSARP_8821C 0x072C +#define REG_IPV6_8821C 0x0730 +#define REG_IPV6_1_8821C 0x0734 +#define REG_IPV6_2_8821C 0x0738 +#define REG_IPV6_3_8821C 0x073C +#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8821C 0x0750 +#define REG_WMAC_SWAES_CFG_8821C 0x0760 +#define REG_BT_COEX_V2_8821C 0x0762 +#define REG_BT_COEX_8821C 0x0764 +#define REG_WLAN_ACT_MASK_CTRL_8821C 0x0768 +#define REG_WLAN_ACT_MASK_CTRL_1_8821C 0x076C +#define REG_BT_COEX_ENHANCED_INTR_CTRL_8821C 0x076E +#define REG_BT_ACT_STATISTICS_8821C 0x0770 +#define REG_BT_ACT_STATISTICS_1_8821C 0x0774 +#define REG_BT_STATISTICS_CONTROL_REGISTER_8821C 0x0778 +#define REG_BT_STATUS_REPORT_REGISTER_8821C 0x077C +#define REG_BT_INTERRUPT_CONTROL_REGISTER_8821C 0x0780 +#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8821C 0x0784 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8821C 0x0785 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_1_8821C 0x0788 +#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_2_8821C 0x078C +#define REG_BT_INTERRUPT_STATUS_REGISTER_8821C 0x078F +#define REG_BT_TDMA_TIME_REGISTER_8821C 0x0790 +#define REG_BT_ACT_REGISTER_8821C 0x0794 +#define REG_OBFF_CTRL_BASIC_8821C 0x0798 +#define REG_OBFF_CTRL2_TIMER_8821C 0x079C +#define REG_LTR_CTRL_BASIC_8821C 0x07A0 +#define REG_LTR_CTRL2_TIMER_THRESHOLD_8821C 0x07A4 +#define REG_LTR_IDLE_LATENCY_V1_8821C 0x07A8 +#define REG_LTR_ACTIVE_LATENCY_V1_8821C 0x07AC +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8821C 0x07B0 +#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_1_8821C 0x07B4 +#define REG_WMAC_PKTCNT_RWD_8821C 0x07B8 +#define REG_WMAC_PKTCNT_CTRL_8821C 0x07BC +#define REG_IQ_DUMP_8821C 0x07C0 +#define REG_IQ_DUMP_1_8821C 0x07C4 +#define REG_IQ_DUMP_2_8821C 0x07C8 +#define REG_WMAC_FTM_CTL_8821C 0x07CC +#define REG_WMAC_IQ_MDPK_FUNC_8821C 0x07CE +#define REG_WMAC_OPTION_FUNCTION_8821C 0x07D0 +#define REG_WMAC_OPTION_FUNCTION_1_8821C 0x07D4 +#define REG_WMAC_OPTION_FUNCTION_2_8821C 0x07D8 +#define REG_RX_FILTER_FUNCTION_8821C 0x07DA +#define REG_NDP_SIG_8821C 0x07E0 +#define REG_TXCMD_INFO_FOR_RSP_PKT_8821C 0x07E4 +#define REG_TXCMD_INFO_FOR_RSP_PKT_1_8821C 0x07E8 +#define REG_WSEC_OPTION_8821C 0x07EC +#define REG_RTS_ADDRESS_0_8821C 0x07F0 +#define REG_RTS_ADDRESS_0_1_8821C 0x07F4 +#define REG_RTS_ADDRESS_1_8821C 0x07F8 +#define REG_RTS_ADDRESS_1_1_8821C 0x07FC +#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8821C 0x1700 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8821C 0x1704 +#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8821C 0x1708 +#define REG_SDIO_TX_CTRL_8821C 0x10250000 +#define REG_SDIO_HIMR_8821C 0x10250014 +#define REG_SDIO_HISR_8821C 0x10250018 +#define REG_SDIO_RX_REQ_LEN_8821C 0x1025001C +#define REG_SDIO_FREE_TXPG_SEQ_V1_8821C 0x1025001F +#define REG_SDIO_FREE_TXPG_8821C 0x10250020 +#define REG_SDIO_FREE_TXPG2_8821C 0x10250024 +#define REG_SDIO_OQT_FREE_TXPG_V1_8821C 0x10250028 +#define REG_SDIO_HTSFR_INFO_8821C 0x10250030 +#define REG_SDIO_HCPWM1_V2_8821C 0x10250038 +#define REG_SDIO_HCPWM2_V2_8821C 0x1025003A +#define REG_SDIO_INDIRECT_REG_CFG_8821C 0x10250040 +#define REG_SDIO_INDIRECT_REG_DATA_8821C 0x10250044 +#define REG_SDIO_H2C_8821C 0x10250060 +#define REG_SDIO_C2H_8821C 0x10250064 +#define REG_SDIO_HRPWM1_8821C 0x10250080 +#define REG_SDIO_HRPWM2_8821C 0x10250082 +#define REG_SDIO_HPS_CLKR_8821C 0x10250084 +#define REG_SDIO_BUS_CTRL_8821C 0x10250085 +#define REG_SDIO_HSUS_CTRL_8821C 0x10250086 +#define REG_SDIO_RESPONSE_TIMER_8821C 0x10250088 +#define REG_SDIO_CMD_CRC_8821C 0x1025008A +#define REG_SDIO_HSISR_8821C 0x10250090 +#define REG_SDIO_HSIMR_8821C 0x10250091 +#define REG_SDIO_ERR_RPT_8821C 0x102500C0 +#define REG_SDIO_CMD_ERRCNT_8821C 0x102500C1 +#define REG_SDIO_DATA_ERRCNT_8821C 0x102500C2 +#define REG_SDIO_CMD_ERR_CONTENT_8821C 0x102500C4 +#define REG_SDIO_CRC_ERR_IDX_8821C 0x102500C9 +#define REG_SDIO_DATA_CRC_8821C 0x102500CA +#define REG_SDIO_DATA_REPLY_TIME_8821C 0x102500CB + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h new file mode 100644 index 000000000000..b69addfa9279 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_ap.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_RX_BD_AP_H_ +#define _HALMAC_RX_BD_AP_H_ + +/*TXBD_DW0*/ + +#define GET_RX_BD_RXFAIL(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 31) +#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16) +#define GET_RX_BD_RXTAG(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1fff, 16) +#define GET_RX_BD_FS(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 15) +#define GET_RX_BD_LS(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x1, 14) +#define GET_RX_BD_RXBUFFSIZE(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword0, 0x3fff, 0) + +/*TXBD_DW1*/ + +#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword1, 0xffffffff, 0) + +/*TXBD_DW2*/ + +#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) HALMAC_GET_BD_FIELD(((PHALMAC_RX_BD)__pRxBd)->Dword2, 0xffffffff, 0) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h new file mode 100644 index 000000000000..eadb6c15fb5d --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_chip.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_RX_BD_CHIP_H_ +#define _HALMAC_RX_BD_CHIP_H_ + +/*TXBD_DW0*/ + +#define GET_RX_BD_RXFAIL_8821C(__pRxBd) GET_RX_BD_RXFAIL(__pRxBd) +#define GET_RX_BD_TOTALRXPKTSIZE_8821C(__pRxBd) GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) +#define GET_RX_BD_RXTAG_8821C(__pRxBd) GET_RX_BD_RXTAG(__pRxBd) +#define GET_RX_BD_FS_8821C(__pRxBd) GET_RX_BD_FS(__pRxBd) +#define GET_RX_BD_LS_8821C(__pRxBd) GET_RX_BD_LS(__pRxBd) +#define GET_RX_BD_RXBUFFSIZE_8821C(__pRxBd) GET_RX_BD_RXBUFFSIZE(__pRxBd) + +/*TXBD_DW1*/ + +#define GET_RX_BD_PHYSICAL_ADDR_LOW_8821C(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) + +/*TXBD_DW2*/ + +#define GET_RX_BD_PHYSICAL_ADDR_HIGH_8821C(__pRxBd) GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h new file mode 100644 index 000000000000..d5339daba1ce --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_bd_nic.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_RX_BD_NIC_H_ +#define _HALMAC_RX_BD_NIC_H_ + +/*TXBD_DW0*/ + +#define GET_RX_BD_RXFAIL(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 31, 1) +#define GET_RX_BD_TOTALRXPKTSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13) +#define GET_RX_BD_RXTAG(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 16, 13) +#define GET_RX_BD_FS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 15, 1) +#define GET_RX_BD_LS(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 14, 1) +#define GET_RX_BD_RXBUFFSIZE(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x00, 0, 14) + +/*TXBD_DW1*/ + +#define GET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x04, 0, 32) + +/*TXBD_DW2*/ + +#define GET_RX_BD_PHYSICAL_ADDR_HIGH(__pRxBd) LE_BITS_TO_4BYTE(__pRxBd + 0x08, 0, 32) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h new file mode 100644 index 000000000000..781ed145c994 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_ap.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_RX_DESC_AP_H_ +#define _HALMAC_RX_DESC_AP_H_ + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EOR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 30) +#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 28) +#define GET_RX_DESC_SWDEC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 27) +#define GET_RX_DESC_PHYST(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 26) +#define GET_RX_DESC_SHIFT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3, 24) +#define GET_RX_DESC_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 23) +#define GET_RX_DESC_SECURITY(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x7, 20) +#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0xf, 16) +#define GET_RX_DESC_ICV_ERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 15) +#define GET_RX_DESC_CRC32(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x1, 14) +#define GET_RX_DESC_PKT_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword0, 0x3fff, 0) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 31) +#define GET_RX_DESC_MC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 30) +#define GET_RX_DESC_TY_PE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x3, 28) +#define GET_RX_DESC_MF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 27) +#define GET_RX_DESC_MD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 26) +#define GET_RX_DESC_PWR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 25) +#define GET_RX_DESC_PAM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 24) +#define GET_RX_DESC_CHK_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 23) +#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 22) +#define GET_RX_DESC_RX_IPV(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 21) +#define GET_RX_DESC_CHKERR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 20) +#define GET_RX_DESC_PAGGR(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 15) +#define GET_RX_DESC_RXID_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 14) +#define GET_RX_DESC_AMSDU(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 13) +#define GET_RX_DESC_MACID_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 12) +#define GET_RX_DESC_TID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0xf, 8) + +#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x1, 7) + +#define GET_RX_DESC_MACID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword1, 0x7f, 0) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_FCS_OK(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 31) + +#define GET_RX_DESC_PPDU_CNT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3, 29) + +#define GET_RX_DESC_C2H(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 28) +#define GET_RX_DESC_HWRSVD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 24) +#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x3f, 18) +#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0x1, 16) +#define GET_RX_DESC_FRAG(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xf, 12) +#define GET_RX_DESC_SEQ(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword2, 0xfff, 0) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 31) +#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 30) +#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 29) + +#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 28) +#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xf, 24) + +#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0xff, 16) +#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x3, 12) +#define GET_RX_DESC_EOSP(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 11) +#define GET_RX_DESC_HTC(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x1, 10) + +#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7, 7) + +#define GET_RX_DESC_RX_RATE(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword3, 0x7f, 0) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_A1_FIT(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1f, 24) + +#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 17) +#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 16) +#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x7f, 9) +#define GET_RX_DESC_RX_EOF(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0x1, 8) + +#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword4, 0xff, 0) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_TSFL(__pRxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_RX_DESC)__pRxDesc)->Dword5, 0xffffffff, 0) + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h new file mode 100644 index 000000000000..9b0670e6f489 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_chip.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_RX_DESC_CHIP_H_ +#define _HALMAC_RX_DESC_CHIP_H_ + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EOR_8821C(__pRxDesc) GET_RX_DESC_EOR(__pRxDesc) +#define GET_RX_DESC_PHYPKTIDC_8821C(__pRxDesc) GET_RX_DESC_PHYPKTIDC(__pRxDesc) +#define GET_RX_DESC_SWDEC_8821C(__pRxDesc) GET_RX_DESC_SWDEC(__pRxDesc) +#define GET_RX_DESC_PHYST_8821C(__pRxDesc) GET_RX_DESC_PHYST(__pRxDesc) +#define GET_RX_DESC_SHIFT_8821C(__pRxDesc) GET_RX_DESC_SHIFT(__pRxDesc) +#define GET_RX_DESC_QOS_8821C(__pRxDesc) GET_RX_DESC_QOS(__pRxDesc) +#define GET_RX_DESC_SECURITY_8821C(__pRxDesc) GET_RX_DESC_SECURITY(__pRxDesc) +#define GET_RX_DESC_DRV_INFO_SIZE_8821C(__pRxDesc) GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) +#define GET_RX_DESC_ICV_ERR_8821C(__pRxDesc) GET_RX_DESC_ICV_ERR(__pRxDesc) +#define GET_RX_DESC_CRC32_8821C(__pRxDesc) GET_RX_DESC_CRC32(__pRxDesc) +#define GET_RX_DESC_PKT_LEN_8821C(__pRxDesc) GET_RX_DESC_PKT_LEN(__pRxDesc) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC_8821C(__pRxDesc) GET_RX_DESC_BC(__pRxDesc) +#define GET_RX_DESC_MC_8821C(__pRxDesc) GET_RX_DESC_MC(__pRxDesc) +#define GET_RX_DESC_TY_PE_8821C(__pRxDesc) GET_RX_DESC_TY_PE(__pRxDesc) +#define GET_RX_DESC_MF_8821C(__pRxDesc) GET_RX_DESC_MF(__pRxDesc) +#define GET_RX_DESC_MD_8821C(__pRxDesc) GET_RX_DESC_MD(__pRxDesc) +#define GET_RX_DESC_PWR_8821C(__pRxDesc) GET_RX_DESC_PWR(__pRxDesc) +#define GET_RX_DESC_PAM_8821C(__pRxDesc) GET_RX_DESC_PAM(__pRxDesc) +#define GET_RX_DESC_CHK_VLD_8821C(__pRxDesc) GET_RX_DESC_CHK_VLD(__pRxDesc) +#define GET_RX_DESC_RX_IS_TCP_UDP_8821C(__pRxDesc) GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) +#define GET_RX_DESC_RX_IPV_8821C(__pRxDesc) GET_RX_DESC_RX_IPV(__pRxDesc) +#define GET_RX_DESC_CHKERR_8821C(__pRxDesc) GET_RX_DESC_CHKERR(__pRxDesc) +#define GET_RX_DESC_PAGGR_8821C(__pRxDesc) GET_RX_DESC_PAGGR(__pRxDesc) +#define GET_RX_DESC_RXID_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXID_MATCH(__pRxDesc) +#define GET_RX_DESC_AMSDU_8821C(__pRxDesc) GET_RX_DESC_AMSDU(__pRxDesc) +#define GET_RX_DESC_MACID_VLD_8821C(__pRxDesc) GET_RX_DESC_MACID_VLD(__pRxDesc) +#define GET_RX_DESC_TID_8821C(__pRxDesc) GET_RX_DESC_TID(__pRxDesc) +#define GET_RX_DESC_EXT_SECTYPE_8821C(__pRxDesc) GET_RX_DESC_EXT_SECTYPE(__pRxDesc) +#define GET_RX_DESC_MACID_8821C(__pRxDesc) GET_RX_DESC_MACID(__pRxDesc) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_FCS_OK_8821C(__pRxDesc) GET_RX_DESC_FCS_OK(__pRxDesc) +#define GET_RX_DESC_PPDU_CNT_8821C(__pRxDesc) GET_RX_DESC_PPDU_CNT(__pRxDesc) +#define GET_RX_DESC_C2H_8821C(__pRxDesc) GET_RX_DESC_C2H(__pRxDesc) +#define GET_RX_DESC_HWRSVD_8821C(__pRxDesc) GET_RX_DESC_HWRSVD(__pRxDesc) +#define GET_RX_DESC_WLANHD_IV_LEN_8821C(__pRxDesc) GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) +#define GET_RX_DESC_RX_IS_QOS_8821C(__pRxDesc) GET_RX_DESC_RX_IS_QOS(__pRxDesc) +#define GET_RX_DESC_FRAG_8821C(__pRxDesc) GET_RX_DESC_FRAG(__pRxDesc) +#define GET_RX_DESC_SEQ_8821C(__pRxDesc) GET_RX_DESC_SEQ(__pRxDesc) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE_8821C(__pRxDesc) GET_RX_DESC_MAGIC_WAKE(__pRxDesc) +#define GET_RX_DESC_UNICAST_WAKE_8821C(__pRxDesc) GET_RX_DESC_UNICAST_WAKE(__pRxDesc) +#define GET_RX_DESC_PATTERN_MATCH_8821C(__pRxDesc) GET_RX_DESC_PATTERN_MATCH(__pRxDesc) +#define GET_RX_DESC_RXPAYLOAD_MATCH_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) +#define GET_RX_DESC_RXPAYLOAD_ID_8821C(__pRxDesc) GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) +#define GET_RX_DESC_DMA_AGG_NUM_8821C(__pRxDesc) GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) +#define GET_RX_DESC_BSSID_FIT_1_0_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) +#define GET_RX_DESC_EOSP_8821C(__pRxDesc) GET_RX_DESC_EOSP(__pRxDesc) +#define GET_RX_DESC_HTC_8821C(__pRxDesc) GET_RX_DESC_HTC(__pRxDesc) +#define GET_RX_DESC_BSSID_FIT_4_2_8821C(__pRxDesc) GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) +#define GET_RX_DESC_RX_RATE_8821C(__pRxDesc) GET_RX_DESC_RX_RATE(__pRxDesc) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_A1_FIT_8821C(__pRxDesc) GET_RX_DESC_A1_FIT(__pRxDesc) +#define GET_RX_DESC_MACID_RPT_BUFF_8821C(__pRxDesc) GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) +#define GET_RX_DESC_RX_PRE_NDP_VLD_8821C(__pRxDesc) GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) +#define GET_RX_DESC_RX_SCRAMBLER_8821C(__pRxDesc) GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) +#define GET_RX_DESC_RX_EOF_8821C(__pRxDesc) GET_RX_DESC_RX_EOF(__pRxDesc) +#define GET_RX_DESC_PATTERN_IDX_8821C(__pRxDesc) GET_RX_DESC_PATTERN_IDX(__pRxDesc) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_TSFL_8821C(__pRxDesc) GET_RX_DESC_TSFL(__pRxDesc) + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h new file mode 100644 index 000000000000..76033718e561 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_rx_desc_nic.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_RX_DESC_NIC_H_ +#define _HALMAC_RX_DESC_NIC_H_ + +/*RXDESC_WORD0*/ + +#define GET_RX_DESC_EOR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 30, 1) +#define GET_RX_DESC_PHYPKTIDC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 28, 1) +#define GET_RX_DESC_SWDEC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 27, 1) +#define GET_RX_DESC_PHYST(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 26, 1) +#define GET_RX_DESC_SHIFT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 24, 2) +#define GET_RX_DESC_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 23, 1) +#define GET_RX_DESC_SECURITY(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 20, 3) +#define GET_RX_DESC_DRV_INFO_SIZE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 16, 4) +#define GET_RX_DESC_ICV_ERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 15, 1) +#define GET_RX_DESC_CRC32(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 14, 1) +#define GET_RX_DESC_PKT_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x00, 0, 14) + +/*RXDESC_WORD1*/ + +#define GET_RX_DESC_BC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 31, 1) +#define GET_RX_DESC_MC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 30, 1) +#define GET_RX_DESC_TY_PE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 28, 2) +#define GET_RX_DESC_MF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 27, 1) +#define GET_RX_DESC_MD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 26, 1) +#define GET_RX_DESC_PWR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 25, 1) +#define GET_RX_DESC_PAM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 24, 1) +#define GET_RX_DESC_CHK_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 23, 1) +#define GET_RX_DESC_RX_IS_TCP_UDP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 22, 1) +#define GET_RX_DESC_RX_IPV(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 21, 1) +#define GET_RX_DESC_CHKERR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 20, 1) +#define GET_RX_DESC_PAGGR(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 15, 1) +#define GET_RX_DESC_RXID_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 14, 1) +#define GET_RX_DESC_AMSDU(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 13, 1) +#define GET_RX_DESC_MACID_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 12, 1) +#define GET_RX_DESC_TID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 8, 4) + +#define GET_RX_DESC_EXT_SECTYPE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 7, 1) + +#define GET_RX_DESC_MACID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x04, 0, 7) + +/*RXDESC_WORD2*/ + +#define GET_RX_DESC_FCS_OK(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 31, 1) + +#define GET_RX_DESC_PPDU_CNT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 29, 2) + +#define GET_RX_DESC_C2H(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 28, 1) +#define GET_RX_DESC_HWRSVD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 24, 4) +#define GET_RX_DESC_WLANHD_IV_LEN(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 18, 6) +#define GET_RX_DESC_RX_IS_QOS(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 16, 1) +#define GET_RX_DESC_FRAG(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 12, 4) +#define GET_RX_DESC_SEQ(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x08, 0, 12) + +/*RXDESC_WORD3*/ + +#define GET_RX_DESC_MAGIC_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 31, 1) +#define GET_RX_DESC_UNICAST_WAKE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 30, 1) +#define GET_RX_DESC_PATTERN_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 29, 1) + +#define GET_RX_DESC_RXPAYLOAD_MATCH(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 28, 1) +#define GET_RX_DESC_RXPAYLOAD_ID(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 24, 4) + +#define GET_RX_DESC_DMA_AGG_NUM(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 16, 8) +#define GET_RX_DESC_BSSID_FIT_1_0(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 12, 2) +#define GET_RX_DESC_EOSP(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 11, 1) +#define GET_RX_DESC_HTC(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 10, 1) + +#define GET_RX_DESC_BSSID_FIT_4_2(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 7, 3) + +#define GET_RX_DESC_RX_RATE(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x0C, 0, 7) + +/*RXDESC_WORD4*/ + +#define GET_RX_DESC_A1_FIT(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 24, 5) + +#define GET_RX_DESC_MACID_RPT_BUFF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 17, 7) +#define GET_RX_DESC_RX_PRE_NDP_VLD(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 16, 1) +#define GET_RX_DESC_RX_SCRAMBLER(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 9, 7) +#define GET_RX_DESC_RX_EOF(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 8, 1) + +#define GET_RX_DESC_PATTERN_IDX(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x10, 0, 8) + +/*RXDESC_WORD5*/ + +#define GET_RX_DESC_TSFL(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc + 0x14, 0, 32) + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h new file mode 100644 index 000000000000..f9b72e3bebf8 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_ap.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_TX_BD_AP_H_ +#define _HALMAC_TX_BD_AP_H_ + +/*TXBD_DW0*/ + +#define SET_TX_BD_OWN(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31) +#define SET_TX_BD_OWN_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0x1, 31) +#define GET_TX_BD_OWN(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0x1, 31) +#define SET_TX_BD_PSB(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16) +#define SET_TX_BD_PSB_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xff, 16) +#define GET_TX_BD_PSB(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xff, 16) +#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0) +#define SET_TX_BD_TX_BUFF_SIZE0_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword0, __Value, 0xffff, 0) +#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword0, 0xffff, 0) + +/*TXBD_DW1*/ + +#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR0_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword1, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword1, 0xffffffff, 0) + +/*TXBD_DW2*/ + +#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword2, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword2, 0xffffffff, 0) + +/*TXBD_DW4*/ + +#define SET_TX_BD_A1(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31) +#define SET_TX_BD_A1_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0x1, 31) +#define GET_TX_BD_A1(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0x1, 31) +#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0) +#define SET_TX_BD_TX_BUFF_SIZE1_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword4, __Value, 0xffff, 0) +#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword4, 0xffff, 0) + +/*TXBD_DW5*/ + +#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR1_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword5, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword5, 0xffffffff, 0) + +/*TXBD_DW6*/ + +#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword6, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword6, 0xffffffff, 0) + +/*TXBD_DW8*/ + +#define SET_TX_BD_A2(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31) +#define SET_TX_BD_A2_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0x1, 31) +#define GET_TX_BD_A2(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0x1, 31) +#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0) +#define SET_TX_BD_TX_BUFF_SIZE2_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword8, __Value, 0xffff, 0) +#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword8, 0xffff, 0) + +/*TXBD_DW9*/ + +#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR2_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword9, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword9, 0xffffffff, 0) + +/*TXBD_DW10*/ + +#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword10, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword10, 0xffffffff, 0) + +/*TXBD_DW12*/ + +#define SET_TX_BD_A3(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31) +#define SET_TX_BD_A3_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0x1, 31) +#define GET_TX_BD_A3(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0x1, 31) +#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0) +#define SET_TX_BD_TX_BUFF_SIZE3_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword12, __Value, 0xffff, 0) +#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword12, 0xffff, 0) + +/*TXBD_DW13*/ + +#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR3_LOW_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword13, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword13, 0xffffffff, 0) + +/*TXBD_DW14*/ + +#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) HALMAC_SET_BD_FIELD_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0) +#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_NO_CLR(__pTxBd, __Value) HALMAC_SET_BD_FIELD_NO_CLR(((PHALMAC_TX_BD)__pTxBd)->Dword14, __Value, 0xffffffff, 0) +#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) HALMAC_GET_BD_FIELD(((PHALMAC_TX_BD)__pTxBd)->Dword14, 0xffffffff, 0) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h new file mode 100644 index 000000000000..02e3d1a3aaf1 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_chip.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_TX_BD_CHIP_H_ +#define _HALMAC_TX_BD_CHIP_H_ + +/*TXBD_DW0*/ + +#define SET_TX_BD_OWN_8821C(__pTxBd, __Value) SET_TX_BD_OWN(__pTxBd, __Value) +#define GET_TX_BD_OWN_8821C(__pTxBd) GET_TX_BD_OWN(__pTxBd) +#define SET_TX_BD_PSB_8821C(__pTxBd, __Value) SET_TX_BD_PSB(__pTxBd, __Value) +#define GET_TX_BD_PSB_8821C(__pTxBd) GET_TX_BD_PSB(__pTxBd) +#define SET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) +#define GET_TX_BD_TX_BUFF_SIZE0_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) + +/*TXBD_DW1*/ + +#define SET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR0_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) + +/*TXBD_DW2*/ + +#define SET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR0_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) + +/*TXBD_DW4*/ + +#define SET_TX_BD_A1_8821C(__pTxBd, __Value) SET_TX_BD_A1(__pTxBd, __Value) +#define GET_TX_BD_A1_8821C(__pTxBd) GET_TX_BD_A1(__pTxBd) +#define SET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) +#define GET_TX_BD_TX_BUFF_SIZE1_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) + +/*TXBD_DW5*/ + +#define SET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR1_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) + +/*TXBD_DW6*/ + +#define SET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR1_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) + +/*TXBD_DW8*/ + +#define SET_TX_BD_A2_8821C(__pTxBd, __Value) SET_TX_BD_A2(__pTxBd, __Value) +#define GET_TX_BD_A2_8821C(__pTxBd) GET_TX_BD_A2(__pTxBd) +#define SET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) +#define GET_TX_BD_TX_BUFF_SIZE2_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) + +/*TXBD_DW9*/ + +#define SET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR2_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) + +/*TXBD_DW10*/ + +#define SET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR2_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) + +/*TXBD_DW12*/ + +#define SET_TX_BD_A3_8821C(__pTxBd, __Value) SET_TX_BD_A3(__pTxBd, __Value) +#define GET_TX_BD_A3_8821C(__pTxBd) GET_TX_BD_A3(__pTxBd) +#define SET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd, __Value) SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) +#define GET_TX_BD_TX_BUFF_SIZE3_8821C(__pTxBd) GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) + +/*TXBD_DW13*/ + +#define SET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR3_LOW_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) + +/*TXBD_DW14*/ + +#define SET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd, __Value) SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) +#define GET_TX_BD_PHYSICAL_ADDR3_HIGH_8821C(__pTxBd) GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h new file mode 100644 index 000000000000..28a885dc6218 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_bd_nic.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_TX_BD_NIC_H_ +#define _HALMAC_TX_BD_NIC_H_ + +/*TXBD_DW0*/ + +#define SET_TX_BD_OWN(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 31, 1, __Value) +#define GET_TX_BD_OWN(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 31, 1) +#define SET_TX_BD_PSB(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 16, 8, __Value) +#define GET_TX_BD_PSB(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 16, 8) +#define SET_TX_BD_TX_BUFF_SIZE0(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x00, 0, 16, __Value) +#define GET_TX_BD_TX_BUFF_SIZE0(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x00, 0, 16) + +/*TXBD_DW1*/ + +#define SET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x04, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR0_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x04, 0, 32) + +/*TXBD_DW2*/ + +#define SET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x08, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR0_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x08, 0, 32) + +/*TXBD_DW4*/ + +#define SET_TX_BD_A1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 31, 1, __Value) +#define GET_TX_BD_A1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE1(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x10, 0, 16, __Value) +#define GET_TX_BD_TX_BUFF_SIZE1(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x10, 0, 16) + +/*TXBD_DW5*/ + +#define SET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x14, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR1_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x14, 0, 32) + +/*TXBD_DW6*/ + +#define SET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x18, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR1_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x18, 0, 32) + +/*TXBD_DW8*/ + +#define SET_TX_BD_A2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 31, 1, __Value) +#define GET_TX_BD_A2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE2(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x20, 0, 16, __Value) +#define GET_TX_BD_TX_BUFF_SIZE2(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x20, 0, 16) + +/*TXBD_DW9*/ + +#define SET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x24, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR2_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x24, 0, 32) + +/*TXBD_DW10*/ + +#define SET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x28, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR2_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x28, 0, 32) + +/*TXBD_DW12*/ + +#define SET_TX_BD_A3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 31, 1, __Value) +#define GET_TX_BD_A3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 31, 1) +#define SET_TX_BD_TX_BUFF_SIZE3(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x30, 0, 16, __Value) +#define GET_TX_BD_TX_BUFF_SIZE3(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x30, 0, 16) + +/*TXBD_DW13*/ + +#define SET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x34, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR3_LOW(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x34, 0, 32) + +/*TXBD_DW14*/ + +#define SET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd, __Value) SET_BITS_TO_LE_4BYTE(__pTxBd + 0x38, 0, 32, __Value) +#define GET_TX_BD_PHYSICAL_ADDR3_HIGH(__pTxBd) LE_BITS_TO_4BYTE(__pTxBd + 0x38, 0, 32) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h new file mode 100644 index 000000000000..f6df8bb9b182 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_ap.h @@ -0,0 +1,408 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_TX_DESC_AP_H_ +#define _HALMAC_TX_DESC_AP_H_ + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31) +#define SET_TX_DESC_DISQSELSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 31) +#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 31) + +#define SET_TX_DESC_GF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30) +#define SET_TX_DESC_GF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 30) +#define GET_TX_DESC_GF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 30) +#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29) +#define SET_TX_DESC_NO_ACM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 29) +#define GET_TX_DESC_NO_ACM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 29) + +#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 28) +#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 28) + +#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27) +#define SET_TX_DESC_AMSDU_PAD_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 27) +#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 27) + +#define SET_TX_DESC_LS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26) +#define SET_TX_DESC_LS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 26) +#define GET_TX_DESC_LS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 26) +#define SET_TX_DESC_HTC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25) +#define SET_TX_DESC_HTC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 25) +#define GET_TX_DESC_HTC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 25) +#define SET_TX_DESC_BMC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24) +#define SET_TX_DESC_BMC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0x1, 24) +#define GET_TX_DESC_BMC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0x1, 24) +#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16) +#define SET_TX_DESC_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xff, 16) +#define GET_TX_DESC_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xff, 16) +#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0) +#define SET_TX_DESC_TXPKTSIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, __Value, 0xffff, 0) +#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword0, 0xffff, 0) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29) +#define SET_TX_DESC_MOREDATA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 29) +#define GET_TX_DESC_MOREDATA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 29) +#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24) +#define SET_TX_DESC_PKT_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 24) +#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 24) +#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22) +#define SET_TX_DESC_SEC_TYPE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x3, 22) +#define GET_TX_DESC_SEC_TYPE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x3, 22) +#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21) +#define SET_TX_DESC_EN_DESC_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 21) +#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 21) +#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16) +#define SET_TX_DESC_RATE_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 16) +#define GET_TX_DESC_RATE_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 16) +#define SET_TX_DESC_PIFS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15) +#define SET_TX_DESC_PIFS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 15) +#define GET_TX_DESC_PIFS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 15) +#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14) +#define SET_TX_DESC_LSIG_TXOP_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 14) +#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 14) +#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13) +#define SET_TX_DESC_RD_NAV_EXT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1, 13) +#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1, 13) +#define SET_TX_DESC_QSEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8) +#define SET_TX_DESC_QSEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x1f, 8) +#define GET_TX_DESC_QSEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x1f, 8) +#define SET_TX_DESC_MACID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0) +#define SET_TX_DESC_MACID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, __Value, 0x7f, 0) +#define GET_TX_DESC_MACID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword1, 0x7f, 0) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31) +#define SET_TX_DESC_HW_AES_IV_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 31) +#define GET_TX_DESC_HW_AES_IV(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 31) + +#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30) +#define SET_TX_DESC_FTM_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 30) +#define GET_TX_DESC_FTM_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 30) + +#define SET_TX_DESC_G_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24) +#define SET_TX_DESC_G_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3f, 24) +#define GET_TX_DESC_G_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3f, 24) +#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23) +#define SET_TX_DESC_BT_NULL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 23) +#define GET_TX_DESC_BT_NULL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 23) +#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20) +#define SET_TX_DESC_AMPDU_DENSITY_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x7, 20) +#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x7, 20) +#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19) +#define SET_TX_DESC_SPE_RPT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 19) +#define GET_TX_DESC_SPE_RPT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 19) +#define SET_TX_DESC_RAW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18) +#define SET_TX_DESC_RAW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 18) +#define GET_TX_DESC_RAW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 18) +#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17) +#define SET_TX_DESC_MOREFRAG_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 17) +#define GET_TX_DESC_MOREFRAG(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 17) +#define SET_TX_DESC_BK(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16) +#define SET_TX_DESC_BK_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 16) +#define GET_TX_DESC_BK(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 16) +#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15) +#define SET_TX_DESC_NULL_1_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 15) +#define GET_TX_DESC_NULL_1(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 15) +#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14) +#define SET_TX_DESC_NULL_0_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 14) +#define GET_TX_DESC_NULL_0(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 14) +#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13) +#define SET_TX_DESC_RDG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 13) +#define GET_TX_DESC_RDG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 13) +#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12) +#define SET_TX_DESC_AGG_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 12) +#define GET_TX_DESC_AGG_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 12) +#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10) +#define SET_TX_DESC_CCA_RTS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x3, 10) +#define GET_TX_DESC_CCA_RTS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x3, 10) + +#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9) +#define SET_TX_DESC_TRI_FRAME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1, 9) +#define GET_TX_DESC_TRI_FRAME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1, 9) + +#define SET_TX_DESC_P_AID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0) +#define SET_TX_DESC_P_AID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, __Value, 0x1ff, 0) +#define GET_TX_DESC_P_AID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword2, 0x1ff, 0) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24) +#define SET_TX_DESC_AMPDU_MAX_TIME_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0xff, 24) +#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0xff, 24) +#define SET_TX_DESC_NDPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22) +#define SET_TX_DESC_NDPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 22) +#define GET_TX_DESC_NDPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 22) +#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17) +#define SET_TX_DESC_MAX_AGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 17) +#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 17) +#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16) +#define SET_TX_DESC_USE_MAX_TIME_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 16) +#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 16) +#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15) +#define SET_TX_DESC_NAVUSEHDR_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 15) +#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 15) + +#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14) +#define SET_TX_DESC_CHK_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 14) +#define GET_TX_DESC_CHK_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 14) + +#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13) +#define SET_TX_DESC_HW_RTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 13) +#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 13) +#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12) +#define SET_TX_DESC_RTSEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 12) +#define GET_TX_DESC_RTSEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 12) +#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11) +#define SET_TX_DESC_CTS2SELF_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 11) +#define GET_TX_DESC_CTS2SELF(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 11) +#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10) +#define SET_TX_DESC_DISDATAFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 10) +#define GET_TX_DESC_DISDATAFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 10) +#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9) +#define SET_TX_DESC_DISRTSFB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 9) +#define GET_TX_DESC_DISRTSFB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 9) +#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8) +#define SET_TX_DESC_USE_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1, 8) +#define GET_TX_DESC_USE_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1, 8) +#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6) +#define SET_TX_DESC_HW_SSN_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x3, 6) +#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x3, 6) + +#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0) +#define SET_TX_DESC_WHEADER_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, __Value, 0x1f, 0) +#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword3, 0x1f, 0) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30) +#define SET_TX_DESC_PCTS_MASK_IDX_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3, 30) +#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3, 30) +#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29) +#define SET_TX_DESC_PCTS_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 29) +#define GET_TX_DESC_PCTS_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 29) +#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24) +#define SET_TX_DESC_RTSRATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 24) +#define GET_TX_DESC_RTSRATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 24) +#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x3f, 18) +#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x3f, 18) +#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17) +#define SET_TX_DESC_RTY_LMT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 17) +#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 17) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0xf, 13) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0xf, 13) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1f, 8) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1f, 8) +#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7) +#define SET_TX_DESC_TRY_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x1, 7) +#define GET_TX_DESC_TRY_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x1, 7) +#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0) +#define SET_TX_DESC_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, __Value, 0x7f, 0) +#define GET_TX_DESC_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword4, 0x7f, 0) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31) +#define SET_TX_DESC_POLLUTED_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 31) +#define GET_TX_DESC_POLLUTED(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 31) + +#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28) +#define SET_TX_DESC_TXPWR_OFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 28) +#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 28) +#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24) +#define SET_TX_DESC_TX_ANT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 24) +#define GET_TX_DESC_TX_ANT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 24) +#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21) +#define SET_TX_DESC_PORT_ID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 21) +#define GET_TX_DESC_PORT_ID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 21) + +#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18) +#define SET_TX_DESC_MULTIPLE_PORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x7, 18) +#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x7, 18) + +#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 17) +#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 17) + +#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13) +#define SET_TX_DESC_RTS_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 13) +#define GET_TX_DESC_RTS_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 13) +#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12) +#define SET_TX_DESC_RTS_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 12) +#define GET_TX_DESC_RTS_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 12) + +#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) +#define SET_TX_DESC_VCS_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 10) +#define GET_TX_DESC_VCS_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 10) + +#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8) +#define SET_TX_DESC_DATA_STBC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 8) +#define GET_TX_DESC_DATA_STBC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 8) + +#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7) +#define SET_TX_DESC_DATA_LDPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 7) +#define GET_TX_DESC_DATA_LDPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 7) + +#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5) +#define SET_TX_DESC_DATA_BW_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x3, 5) +#define GET_TX_DESC_DATA_BW(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x3, 5) +#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4) +#define SET_TX_DESC_DATA_SHORT_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0x1, 4) +#define GET_TX_DESC_DATA_SHORT(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0x1, 4) +#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0) +#define SET_TX_DESC_DATA_SC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, __Value, 0xf, 0) +#define GET_TX_DESC_DATA_SC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword5, 0xf, 0) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30) +#define SET_TX_DESC_ANTSEL_D_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 30) +#define GET_TX_DESC_ANTSEL_D(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 30) +#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28) +#define SET_TX_DESC_ANT_MAPD_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 28) +#define GET_TX_DESC_ANT_MAPD(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 28) +#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26) +#define SET_TX_DESC_ANT_MAPC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 26) +#define GET_TX_DESC_ANT_MAPC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 26) +#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24) +#define SET_TX_DESC_ANT_MAPB_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 24) +#define GET_TX_DESC_ANT_MAPB(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 24) +#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22) +#define SET_TX_DESC_ANT_MAPA_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 22) +#define GET_TX_DESC_ANT_MAPA(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 22) +#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20) +#define SET_TX_DESC_ANTSEL_C_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 20) +#define GET_TX_DESC_ANTSEL_C(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 20) +#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18) +#define SET_TX_DESC_ANTSEL_B_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 18) +#define GET_TX_DESC_ANTSEL_B(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 18) + +#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16) +#define SET_TX_DESC_ANTSEL_A_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0x3, 16) +#define GET_TX_DESC_ANTSEL_A(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0x3, 16) +#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12) +#define SET_TX_DESC_MBSSID_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xf, 12) +#define GET_TX_DESC_MBSSID(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xf, 12) +#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0) +#define SET_TX_DESC_SW_DEFINE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, __Value, 0xfff, 0) +#define GET_TX_DESC_SW_DEFINE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword6, 0xfff, 0) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) +#define SET_TX_DESC_DMA_TXAGG_NUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) +#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24) + +#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) +#define SET_TX_DESC_FINAL_DATA_RATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xff, 24) +#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xff, 24) +#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20) +#define SET_TX_DESC_NTX_MAP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xf, 20) +#define GET_TX_DESC_NTX_MAP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xf, 20) + +#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) +#define SET_TX_DESC_TX_BUFF_SIZE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) +#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) +#define SET_TX_DESC_TXDESC_CHECKSUM_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) +#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) +#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) +#define SET_TX_DESC_TIMESTAMP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, __Value, 0xffff, 0) +#define GET_TX_DESC_TIMESTAMP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword7, 0xffff, 0) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31) +#define SET_TX_DESC_TXWIFI_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 31) +#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 31) +#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30) +#define SET_TX_DESC_MAC_CP_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 30) +#define GET_TX_DESC_MAC_CP(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 30) +#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29) +#define SET_TX_DESC_STW_PKTRE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 29) +#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 29) +#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28) +#define SET_TX_DESC_STW_RB_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 28) +#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 28) +#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27) +#define SET_TX_DESC_STW_RATE_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 27) +#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 27) +#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26) +#define SET_TX_DESC_STW_ANT_DIS_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 26) +#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 26) +#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25) +#define SET_TX_DESC_STW_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 25) +#define GET_TX_DESC_STW_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 25) +#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24) +#define SET_TX_DESC_SMH_EN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 24) +#define GET_TX_DESC_SMH_EN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 24) + +#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24) +#define SET_TX_DESC_TAILPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 24) +#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 24) + +#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) +#define SET_TX_DESC_SDIO_DMASEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) +#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16) + +#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) +#define SET_TX_DESC_NEXTHEADPAGE_L_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0xff, 16) +#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0xff, 16) +#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15) +#define SET_TX_DESC_EN_HWSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 15) +#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 15) + +#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14) +#define SET_TX_DESC_EN_HWEXSEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x1, 14) +#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x1, 14) + +#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8) +#define SET_TX_DESC_DATA_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 8) +#define GET_TX_DESC_DATA_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 8) +#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6) +#define SET_TX_DESC_BAR_RTY_TH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3, 6) +#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3, 6) +#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0) +#define SET_TX_DESC_RTS_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, __Value, 0x3f, 0) +#define GET_TX_DESC_RTS_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword8, 0x3f, 0) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28) +#define SET_TX_DESC_TAILPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 28) +#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 28) +#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24) +#define SET_TX_DESC_NEXTHEADPAGE_H_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xf, 24) +#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xf, 24) + +#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12) +#define SET_TX_DESC_SW_SEQ_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xfff, 12) +#define GET_TX_DESC_SW_SEQ(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xfff, 12) +#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11) +#define SET_TX_DESC_TXBF_PATH_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x1, 11) +#define GET_TX_DESC_TXBF_PATH(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x1, 11) +#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0) +#define SET_TX_DESC_PADDING_LEN_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0x7ff, 0) +#define GET_TX_DESC_PADDING_LEN(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0x7ff, 0) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, __Value, 0xff, 0) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword9, 0xff, 0) + +/*WORD10*/ + +#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8) +#define SET_TX_DESC_MU_DATARATE_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xff, 8) +#define GET_TX_DESC_MU_DATARATE(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xff, 8) +#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4) +#define SET_TX_DESC_MU_RC_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0xf, 4) +#define GET_TX_DESC_MU_RC(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0xf, 4) +#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0) +#define SET_TX_DESC_SND_PKT_SEL_NO_CLR(__pTxDesc, __Value) HALMAC_SET_DESC_FIELD_NO_CLR(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, __Value, 0x3, 0) +#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) HALMAC_GET_DESC_FIELD(((PHALMAC_TX_DESC)__pTxDesc)->Dword10, 0x3, 0) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h new file mode 100644 index 000000000000..4bc093533021 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_chip.h @@ -0,0 +1,266 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_TX_DESC_CHIP_H_ +#define _HALMAC_TX_DESC_CHIP_H_ + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) +#define GET_TX_DESC_DISQSELSEQ_8821C(__pTxDesc) GET_TX_DESC_DISQSELSEQ(__pTxDesc) +#define SET_TX_DESC_GF_8821C(__pTxDesc, __Value) SET_TX_DESC_GF(__pTxDesc, __Value) +#define GET_TX_DESC_GF_8821C(__pTxDesc) GET_TX_DESC_GF(__pTxDesc) +#define SET_TX_DESC_NO_ACM_8821C(__pTxDesc, __Value) SET_TX_DESC_NO_ACM(__pTxDesc, __Value) +#define GET_TX_DESC_NO_ACM_8821C(__pTxDesc) GET_TX_DESC_NO_ACM(__pTxDesc) +#define SET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc, __Value) SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL_8821C(__pTxDesc) GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) +#define SET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) +#define GET_TX_DESC_AMSDU_PAD_EN_8821C(__pTxDesc) GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) +#define SET_TX_DESC_LS_8821C(__pTxDesc, __Value) SET_TX_DESC_LS(__pTxDesc, __Value) +#define GET_TX_DESC_LS_8821C(__pTxDesc) GET_TX_DESC_LS(__pTxDesc) +#define SET_TX_DESC_HTC_8821C(__pTxDesc, __Value) SET_TX_DESC_HTC(__pTxDesc, __Value) +#define GET_TX_DESC_HTC_8821C(__pTxDesc) GET_TX_DESC_HTC(__pTxDesc) +#define SET_TX_DESC_BMC_8821C(__pTxDesc, __Value) SET_TX_DESC_BMC(__pTxDesc, __Value) +#define GET_TX_DESC_BMC_8821C(__pTxDesc) GET_TX_DESC_BMC(__pTxDesc) +#define SET_TX_DESC_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_OFFSET(__pTxDesc, __Value) +#define GET_TX_DESC_OFFSET_8821C(__pTxDesc) GET_TX_DESC_OFFSET(__pTxDesc) +#define SET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) +#define GET_TX_DESC_TXPKTSIZE_8821C(__pTxDesc) GET_TX_DESC_TXPKTSIZE(__pTxDesc) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_MOREDATA_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREDATA(__pTxDesc, __Value) +#define GET_TX_DESC_MOREDATA_8821C(__pTxDesc) GET_TX_DESC_MOREDATA(__pTxDesc) +#define SET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) +#define GET_TX_DESC_PKT_OFFSET_8821C(__pTxDesc) GET_TX_DESC_PKT_OFFSET(__pTxDesc) +#define SET_TX_DESC_SEC_TYPE_8821C(__pTxDesc, __Value) SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) +#define GET_TX_DESC_SEC_TYPE_8821C(__pTxDesc) GET_TX_DESC_SEC_TYPE(__pTxDesc) +#define SET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) +#define GET_TX_DESC_EN_DESC_ID_8821C(__pTxDesc) GET_TX_DESC_EN_DESC_ID(__pTxDesc) +#define SET_TX_DESC_RATE_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_RATE_ID(__pTxDesc, __Value) +#define GET_TX_DESC_RATE_ID_8821C(__pTxDesc) GET_TX_DESC_RATE_ID(__pTxDesc) +#define SET_TX_DESC_PIFS_8821C(__pTxDesc, __Value) SET_TX_DESC_PIFS(__pTxDesc, __Value) +#define GET_TX_DESC_PIFS_8821C(__pTxDesc) GET_TX_DESC_PIFS(__pTxDesc) +#define SET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) +#define GET_TX_DESC_LSIG_TXOP_EN_8821C(__pTxDesc) GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) +#define SET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc, __Value) SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) +#define GET_TX_DESC_RD_NAV_EXT_8821C(__pTxDesc) GET_TX_DESC_RD_NAV_EXT(__pTxDesc) +#define SET_TX_DESC_QSEL_8821C(__pTxDesc, __Value) SET_TX_DESC_QSEL(__pTxDesc, __Value) +#define GET_TX_DESC_QSEL_8821C(__pTxDesc) GET_TX_DESC_QSEL(__pTxDesc) +#define SET_TX_DESC_MACID_8821C(__pTxDesc, __Value) SET_TX_DESC_MACID(__pTxDesc, __Value) +#define GET_TX_DESC_MACID_8821C(__pTxDesc) GET_TX_DESC_MACID(__pTxDesc) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_HW_AES_IV_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) +#define GET_TX_DESC_HW_AES_IV_8821C(__pTxDesc) GET_TX_DESC_HW_AES_IV(__pTxDesc) +#define SET_TX_DESC_FTM_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_FTM_EN(__pTxDesc, __Value) +#define GET_TX_DESC_FTM_EN_8821C(__pTxDesc) GET_TX_DESC_FTM_EN(__pTxDesc) +#define SET_TX_DESC_G_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_G_ID(__pTxDesc, __Value) +#define GET_TX_DESC_G_ID_8821C(__pTxDesc) GET_TX_DESC_G_ID(__pTxDesc) +#define SET_TX_DESC_BT_NULL_8821C(__pTxDesc, __Value) SET_TX_DESC_BT_NULL(__pTxDesc, __Value) +#define GET_TX_DESC_BT_NULL_8821C(__pTxDesc) GET_TX_DESC_BT_NULL(__pTxDesc) +#define SET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) +#define GET_TX_DESC_AMPDU_DENSITY_8821C(__pTxDesc) GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) +#define SET_TX_DESC_SPE_RPT_8821C(__pTxDesc, __Value) SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) +#define GET_TX_DESC_SPE_RPT_8821C(__pTxDesc) GET_TX_DESC_SPE_RPT(__pTxDesc) +#define SET_TX_DESC_RAW_8821C(__pTxDesc, __Value) SET_TX_DESC_RAW(__pTxDesc, __Value) +#define GET_TX_DESC_RAW_8821C(__pTxDesc) GET_TX_DESC_RAW(__pTxDesc) +#define SET_TX_DESC_MOREFRAG_8821C(__pTxDesc, __Value) SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) +#define GET_TX_DESC_MOREFRAG_8821C(__pTxDesc) GET_TX_DESC_MOREFRAG(__pTxDesc) +#define SET_TX_DESC_BK_8821C(__pTxDesc, __Value) SET_TX_DESC_BK(__pTxDesc, __Value) +#define GET_TX_DESC_BK_8821C(__pTxDesc) GET_TX_DESC_BK(__pTxDesc) +#define SET_TX_DESC_NULL_1_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_1(__pTxDesc, __Value) +#define GET_TX_DESC_NULL_1_8821C(__pTxDesc) GET_TX_DESC_NULL_1(__pTxDesc) +#define SET_TX_DESC_NULL_0_8821C(__pTxDesc, __Value) SET_TX_DESC_NULL_0(__pTxDesc, __Value) +#define GET_TX_DESC_NULL_0_8821C(__pTxDesc) GET_TX_DESC_NULL_0(__pTxDesc) +#define SET_TX_DESC_RDG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RDG_EN(__pTxDesc, __Value) +#define GET_TX_DESC_RDG_EN_8821C(__pTxDesc) GET_TX_DESC_RDG_EN(__pTxDesc) +#define SET_TX_DESC_AGG_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_AGG_EN(__pTxDesc, __Value) +#define GET_TX_DESC_AGG_EN_8821C(__pTxDesc) GET_TX_DESC_AGG_EN(__pTxDesc) +#define SET_TX_DESC_CCA_RTS_8821C(__pTxDesc, __Value) SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) +#define GET_TX_DESC_CCA_RTS_8821C(__pTxDesc) GET_TX_DESC_CCA_RTS(__pTxDesc) +#define SET_TX_DESC_TRI_FRAME_8821C(__pTxDesc, __Value) SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) +#define GET_TX_DESC_TRI_FRAME_8821C(__pTxDesc) GET_TX_DESC_TRI_FRAME(__pTxDesc) +#define SET_TX_DESC_P_AID_8821C(__pTxDesc, __Value) SET_TX_DESC_P_AID(__pTxDesc, __Value) +#define GET_TX_DESC_P_AID_8821C(__pTxDesc) GET_TX_DESC_P_AID(__pTxDesc) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc, __Value) SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) +#define GET_TX_DESC_AMPDU_MAX_TIME_8821C(__pTxDesc) GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) +#define SET_TX_DESC_NDPA_8821C(__pTxDesc, __Value) SET_TX_DESC_NDPA(__pTxDesc, __Value) +#define GET_TX_DESC_NDPA_8821C(__pTxDesc) GET_TX_DESC_NDPA(__pTxDesc) +#define SET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) +#define GET_TX_DESC_MAX_AGG_NUM_8821C(__pTxDesc) GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) +#define SET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) +#define GET_TX_DESC_USE_MAX_TIME_EN_8821C(__pTxDesc) GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) +#define SET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc, __Value) SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) +#define GET_TX_DESC_NAVUSEHDR_8821C(__pTxDesc) GET_TX_DESC_NAVUSEHDR(__pTxDesc) +#define SET_TX_DESC_CHK_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_CHK_EN(__pTxDesc, __Value) +#define GET_TX_DESC_CHK_EN_8821C(__pTxDesc) GET_TX_DESC_CHK_EN(__pTxDesc) +#define SET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) +#define GET_TX_DESC_HW_RTS_EN_8821C(__pTxDesc) GET_TX_DESC_HW_RTS_EN(__pTxDesc) +#define SET_TX_DESC_RTSEN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSEN(__pTxDesc, __Value) +#define GET_TX_DESC_RTSEN_8821C(__pTxDesc) GET_TX_DESC_RTSEN(__pTxDesc) +#define SET_TX_DESC_CTS2SELF_8821C(__pTxDesc, __Value) SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) +#define GET_TX_DESC_CTS2SELF_8821C(__pTxDesc) GET_TX_DESC_CTS2SELF(__pTxDesc) +#define SET_TX_DESC_DISDATAFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) +#define GET_TX_DESC_DISDATAFB_8821C(__pTxDesc) GET_TX_DESC_DISDATAFB(__pTxDesc) +#define SET_TX_DESC_DISRTSFB_8821C(__pTxDesc, __Value) SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) +#define GET_TX_DESC_DISRTSFB_8821C(__pTxDesc) GET_TX_DESC_DISRTSFB(__pTxDesc) +#define SET_TX_DESC_USE_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_USE_RATE(__pTxDesc, __Value) +#define GET_TX_DESC_USE_RATE_8821C(__pTxDesc) GET_TX_DESC_USE_RATE(__pTxDesc) +#define SET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) +#define GET_TX_DESC_HW_SSN_SEL_8821C(__pTxDesc) GET_TX_DESC_HW_SSN_SEL(__pTxDesc) +#define SET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) +#define GET_TX_DESC_WHEADER_LEN_8821C(__pTxDesc) GET_TX_DESC_WHEADER_LEN(__pTxDesc) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) +#define GET_TX_DESC_PCTS_MASK_IDX_8821C(__pTxDesc) GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) +#define SET_TX_DESC_PCTS_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) +#define GET_TX_DESC_PCTS_EN_8821C(__pTxDesc) GET_TX_DESC_PCTS_EN(__pTxDesc) +#define SET_TX_DESC_RTSRATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTSRATE(__pTxDesc, __Value) +#define GET_TX_DESC_RTSRATE_8821C(__pTxDesc) GET_TX_DESC_RTSRATE(__pTxDesc) +#define SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT_8821C(__pTxDesc) GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) +#define SET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) +#define GET_TX_DESC_RTY_LMT_EN_8821C(__pTxDesc) GET_TX_DESC_RTY_LMT_EN(__pTxDesc) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C(__pTxDesc) GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) +#define SET_TX_DESC_TRY_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) +#define GET_TX_DESC_TRY_RATE_8821C(__pTxDesc) GET_TX_DESC_TRY_RATE(__pTxDesc) +#define SET_TX_DESC_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_DATARATE(__pTxDesc, __Value) +#define GET_TX_DESC_DATARATE_8821C(__pTxDesc) GET_TX_DESC_DATARATE(__pTxDesc) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_POLLUTED_8821C(__pTxDesc, __Value) SET_TX_DESC_POLLUTED(__pTxDesc, __Value) +#define GET_TX_DESC_POLLUTED_8821C(__pTxDesc) GET_TX_DESC_POLLUTED(__pTxDesc) +#define SET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) +#define GET_TX_DESC_TXPWR_OFSET_8821C(__pTxDesc) GET_TX_DESC_TXPWR_OFSET(__pTxDesc) +#define SET_TX_DESC_TX_ANT_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_ANT(__pTxDesc, __Value) +#define GET_TX_DESC_TX_ANT_8821C(__pTxDesc) GET_TX_DESC_TX_ANT(__pTxDesc) +#define SET_TX_DESC_PORT_ID_8821C(__pTxDesc, __Value) SET_TX_DESC_PORT_ID(__pTxDesc, __Value) +#define GET_TX_DESC_PORT_ID_8821C(__pTxDesc) GET_TX_DESC_PORT_ID(__pTxDesc) +#define SET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc, __Value) SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) +#define GET_TX_DESC_MULTIPLE_PORT_8821C(__pTxDesc) GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) +#define SET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN_8821C(__pTxDesc) GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) +#define SET_TX_DESC_RTS_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SC(__pTxDesc, __Value) +#define GET_TX_DESC_RTS_SC_8821C(__pTxDesc) GET_TX_DESC_RTS_SC(__pTxDesc) +#define SET_TX_DESC_RTS_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) +#define GET_TX_DESC_RTS_SHORT_8821C(__pTxDesc) GET_TX_DESC_RTS_SHORT(__pTxDesc) +#define SET_TX_DESC_VCS_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) +#define GET_TX_DESC_VCS_STBC_8821C(__pTxDesc) GET_TX_DESC_VCS_STBC(__pTxDesc) +#define SET_TX_DESC_DATA_STBC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) +#define GET_TX_DESC_DATA_STBC_8821C(__pTxDesc) GET_TX_DESC_DATA_STBC(__pTxDesc) +#define SET_TX_DESC_DATA_LDPC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) +#define GET_TX_DESC_DATA_LDPC_8821C(__pTxDesc) GET_TX_DESC_DATA_LDPC(__pTxDesc) +#define SET_TX_DESC_DATA_BW_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_BW(__pTxDesc, __Value) +#define GET_TX_DESC_DATA_BW_8821C(__pTxDesc) GET_TX_DESC_DATA_BW(__pTxDesc) +#define SET_TX_DESC_DATA_SHORT_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) +#define GET_TX_DESC_DATA_SHORT_8821C(__pTxDesc) GET_TX_DESC_DATA_SHORT(__pTxDesc) +#define SET_TX_DESC_DATA_SC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_SC(__pTxDesc, __Value) +#define GET_TX_DESC_DATA_SC_8821C(__pTxDesc) GET_TX_DESC_DATA_SC(__pTxDesc) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_ANTSEL_D_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) +#define GET_TX_DESC_ANTSEL_D_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_D(__pTxDesc) +#define SET_TX_DESC_ANT_MAPD_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) +#define GET_TX_DESC_ANT_MAPD_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPD(__pTxDesc) +#define SET_TX_DESC_ANT_MAPC_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) +#define GET_TX_DESC_ANT_MAPC_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPC(__pTxDesc) +#define SET_TX_DESC_ANT_MAPB_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) +#define GET_TX_DESC_ANT_MAPB_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPB(__pTxDesc) +#define SET_TX_DESC_ANT_MAPA_8821C(__pTxDesc, __Value) SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) +#define GET_TX_DESC_ANT_MAPA_8821C(__pTxDesc) GET_TX_DESC_ANT_MAPA(__pTxDesc) +#define SET_TX_DESC_ANTSEL_C_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) +#define GET_TX_DESC_ANTSEL_C_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_C(__pTxDesc) +#define SET_TX_DESC_ANTSEL_B_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) +#define GET_TX_DESC_ANTSEL_B_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_B(__pTxDesc) +#define SET_TX_DESC_ANTSEL_A_8821C(__pTxDesc, __Value) SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) +#define GET_TX_DESC_ANTSEL_A_8821C(__pTxDesc) GET_TX_DESC_ANTSEL_A(__pTxDesc) +#define SET_TX_DESC_MBSSID_8821C(__pTxDesc, __Value) SET_TX_DESC_MBSSID(__pTxDesc, __Value) +#define GET_TX_DESC_MBSSID_8821C(__pTxDesc) GET_TX_DESC_MBSSID(__pTxDesc) +#define SET_TX_DESC_SW_DEFINE_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) +#define GET_TX_DESC_SW_DEFINE_8821C(__pTxDesc) GET_TX_DESC_SW_DEFINE(__pTxDesc) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc, __Value) SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) +#define GET_TX_DESC_DMA_TXAGG_NUM_8821C(__pTxDesc) GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) +#define SET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc, __Value) SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) +#define GET_TX_DESC_FINAL_DATA_RATE_8821C(__pTxDesc) GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) +#define SET_TX_DESC_NTX_MAP_8821C(__pTxDesc, __Value) SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) +#define GET_TX_DESC_NTX_MAP_8821C(__pTxDesc) GET_TX_DESC_NTX_MAP(__pTxDesc) +#define SET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc, __Value) SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) +#define GET_TX_DESC_TX_BUFF_SIZE_8821C(__pTxDesc) GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) +#define SET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc, __Value) SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) +#define GET_TX_DESC_TXDESC_CHECKSUM_8821C(__pTxDesc) GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) +#define SET_TX_DESC_TIMESTAMP_8821C(__pTxDesc, __Value) SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) +#define GET_TX_DESC_TIMESTAMP_8821C(__pTxDesc) GET_TX_DESC_TIMESTAMP(__pTxDesc) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) +#define GET_TX_DESC_TXWIFI_CP_8821C(__pTxDesc) GET_TX_DESC_TXWIFI_CP(__pTxDesc) +#define SET_TX_DESC_MAC_CP_8821C(__pTxDesc, __Value) SET_TX_DESC_MAC_CP(__pTxDesc, __Value) +#define GET_TX_DESC_MAC_CP_8821C(__pTxDesc) GET_TX_DESC_MAC_CP(__pTxDesc) +#define SET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) +#define GET_TX_DESC_STW_PKTRE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) +#define SET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) +#define GET_TX_DESC_STW_RB_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RB_DIS(__pTxDesc) +#define SET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) +#define GET_TX_DESC_STW_RATE_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_RATE_DIS(__pTxDesc) +#define SET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) +#define GET_TX_DESC_STW_ANT_DIS_8821C(__pTxDesc) GET_TX_DESC_STW_ANT_DIS(__pTxDesc) +#define SET_TX_DESC_STW_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_STW_EN(__pTxDesc, __Value) +#define GET_TX_DESC_STW_EN_8821C(__pTxDesc) GET_TX_DESC_STW_EN(__pTxDesc) +#define SET_TX_DESC_SMH_EN_8821C(__pTxDesc, __Value) SET_TX_DESC_SMH_EN(__pTxDesc, __Value) +#define GET_TX_DESC_SMH_EN_8821C(__pTxDesc) GET_TX_DESC_SMH_EN(__pTxDesc) +#define SET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) +#define GET_TX_DESC_TAILPAGE_L_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_L(__pTxDesc) +#define SET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) +#define GET_TX_DESC_SDIO_DMASEQ_8821C(__pTxDesc) GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) +#define SET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) +#define GET_TX_DESC_NEXTHEADPAGE_L_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) +#define SET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) +#define GET_TX_DESC_EN_HWSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWSEQ(__pTxDesc) +#define SET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) +#define GET_TX_DESC_EN_HWEXSEQ_8821C(__pTxDesc) GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) +#define SET_TX_DESC_DATA_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_DATA_RC(__pTxDesc, __Value) +#define GET_TX_DESC_DATA_RC_8821C(__pTxDesc) GET_TX_DESC_DATA_RC(__pTxDesc) +#define SET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc, __Value) SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) +#define GET_TX_DESC_BAR_RTY_TH_8821C(__pTxDesc) GET_TX_DESC_BAR_RTY_TH(__pTxDesc) +#define SET_TX_DESC_RTS_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_RTS_RC(__pTxDesc, __Value) +#define GET_TX_DESC_RTS_RC_8821C(__pTxDesc) GET_TX_DESC_RTS_RC(__pTxDesc) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) +#define GET_TX_DESC_TAILPAGE_H_8821C(__pTxDesc) GET_TX_DESC_TAILPAGE_H(__pTxDesc) +#define SET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc, __Value) SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) +#define GET_TX_DESC_NEXTHEADPAGE_H_8821C(__pTxDesc) GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) +#define SET_TX_DESC_SW_SEQ_8821C(__pTxDesc, __Value) SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) +#define GET_TX_DESC_SW_SEQ_8821C(__pTxDesc) GET_TX_DESC_SW_SEQ(__pTxDesc) +#define SET_TX_DESC_TXBF_PATH_8821C(__pTxDesc, __Value) SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) +#define GET_TX_DESC_TXBF_PATH_8821C(__pTxDesc) GET_TX_DESC_TXBF_PATH(__pTxDesc) +#define SET_TX_DESC_PADDING_LEN_8821C(__pTxDesc, __Value) SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) +#define GET_TX_DESC_PADDING_LEN_8821C(__pTxDesc) GET_TX_DESC_PADDING_LEN(__pTxDesc) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc, __Value) SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET_8821C(__pTxDesc) GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) + +/*WORD10*/ + +#define SET_TX_DESC_MU_DATARATE_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) +#define GET_TX_DESC_MU_DATARATE_8821C(__pTxDesc) GET_TX_DESC_MU_DATARATE(__pTxDesc) +#define SET_TX_DESC_MU_RC_8821C(__pTxDesc, __Value) SET_TX_DESC_MU_RC(__pTxDesc, __Value) +#define GET_TX_DESC_MU_RC_8821C(__pTxDesc) GET_TX_DESC_MU_RC(__pTxDesc) +#define SET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc, __Value) SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) +#define GET_TX_DESC_SND_PKT_SEL_8821C(__pTxDesc) GET_TX_DESC_SND_PKT_SEL(__pTxDesc) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h new file mode 100644 index 000000000000..8b11ca2b0693 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_tx_desc_nic.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_TX_DESC_NIC_H_ +#define _HALMAC_TX_DESC_NIC_H_ + +/*TXDESC_WORD0*/ + +#define SET_TX_DESC_DISQSELSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 31, 1, __Value) +#define GET_TX_DESC_DISQSELSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 31, 1) + +#define SET_TX_DESC_GF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 30, 1, __Value) +#define GET_TX_DESC_GF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 30, 1) +#define SET_TX_DESC_NO_ACM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 29, 1, __Value) +#define GET_TX_DESC_NO_ACM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 29, 1) + +#define SET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 28, 1, __Value) +#define GET_TX_DESC_BCNPKT_TSF_CTRL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 28, 1) + +#define SET_TX_DESC_AMSDU_PAD_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 27, 1, __Value) +#define GET_TX_DESC_AMSDU_PAD_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 27, 1) + +#define SET_TX_DESC_LS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 26, 1, __Value) +#define GET_TX_DESC_LS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 26, 1) +#define SET_TX_DESC_HTC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 25, 1, __Value) +#define GET_TX_DESC_HTC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 25, 1) +#define SET_TX_DESC_BMC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 24, 1, __Value) +#define GET_TX_DESC_BMC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 24, 1) +#define SET_TX_DESC_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 16, 8, __Value) +#define GET_TX_DESC_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 16, 8) +#define SET_TX_DESC_TXPKTSIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x00, 0, 16, __Value) +#define GET_TX_DESC_TXPKTSIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x00, 0, 16) + +/*TXDESC_WORD1*/ + +#define SET_TX_DESC_MOREDATA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 29, 1, __Value) +#define GET_TX_DESC_MOREDATA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 29, 1) +#define SET_TX_DESC_PKT_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 24, 5, __Value) +#define GET_TX_DESC_PKT_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 24, 5) +#define SET_TX_DESC_SEC_TYPE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 22, 2, __Value) +#define GET_TX_DESC_SEC_TYPE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 22, 2) +#define SET_TX_DESC_EN_DESC_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 21, 1, __Value) +#define GET_TX_DESC_EN_DESC_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 21, 1) +#define SET_TX_DESC_RATE_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 16, 5, __Value) +#define GET_TX_DESC_RATE_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 16, 5) +#define SET_TX_DESC_PIFS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 15, 1, __Value) +#define GET_TX_DESC_PIFS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 15, 1) +#define SET_TX_DESC_LSIG_TXOP_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 14, 1, __Value) +#define GET_TX_DESC_LSIG_TXOP_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 14, 1) +#define SET_TX_DESC_RD_NAV_EXT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 13, 1, __Value) +#define GET_TX_DESC_RD_NAV_EXT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 13, 1) +#define SET_TX_DESC_QSEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 8, 5, __Value) +#define GET_TX_DESC_QSEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 8, 5) +#define SET_TX_DESC_MACID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x04, 0, 7, __Value) +#define GET_TX_DESC_MACID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x04, 0, 7) + +/*TXDESC_WORD2*/ + +#define SET_TX_DESC_HW_AES_IV(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 31, 1, __Value) +#define GET_TX_DESC_HW_AES_IV(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 31, 1) + +#define SET_TX_DESC_FTM_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 30, 1, __Value) +#define GET_TX_DESC_FTM_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 30, 1) + +#define SET_TX_DESC_G_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 24, 6, __Value) +#define GET_TX_DESC_G_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 24, 6) +#define SET_TX_DESC_BT_NULL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 23, 1, __Value) +#define GET_TX_DESC_BT_NULL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 23, 1) +#define SET_TX_DESC_AMPDU_DENSITY(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 20, 3, __Value) +#define GET_TX_DESC_AMPDU_DENSITY(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 20, 3) +#define SET_TX_DESC_SPE_RPT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 19, 1, __Value) +#define GET_TX_DESC_SPE_RPT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 19, 1) +#define SET_TX_DESC_RAW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 18, 1, __Value) +#define GET_TX_DESC_RAW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 18, 1) +#define SET_TX_DESC_MOREFRAG(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 17, 1, __Value) +#define GET_TX_DESC_MOREFRAG(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 17, 1) +#define SET_TX_DESC_BK(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 16, 1, __Value) +#define GET_TX_DESC_BK(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 16, 1) +#define SET_TX_DESC_NULL_1(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 15, 1, __Value) +#define GET_TX_DESC_NULL_1(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 15, 1) +#define SET_TX_DESC_NULL_0(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 14, 1, __Value) +#define GET_TX_DESC_NULL_0(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 14, 1) +#define SET_TX_DESC_RDG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 13, 1, __Value) +#define GET_TX_DESC_RDG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 13, 1) +#define SET_TX_DESC_AGG_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 12, 1, __Value) +#define GET_TX_DESC_AGG_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 12, 1) +#define SET_TX_DESC_CCA_RTS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 10, 2, __Value) +#define GET_TX_DESC_CCA_RTS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 10, 2) + +#define SET_TX_DESC_TRI_FRAME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 9, 1, __Value) +#define GET_TX_DESC_TRI_FRAME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 9, 1) + +#define SET_TX_DESC_P_AID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x08, 0, 9, __Value) +#define GET_TX_DESC_P_AID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x08, 0, 9) + +/*TXDESC_WORD3*/ + +#define SET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 24, 8, __Value) +#define GET_TX_DESC_AMPDU_MAX_TIME(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 24, 8) +#define SET_TX_DESC_NDPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 22, 2, __Value) +#define GET_TX_DESC_NDPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 22, 2) +#define SET_TX_DESC_MAX_AGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 17, 5, __Value) +#define GET_TX_DESC_MAX_AGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 17, 5) +#define SET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 16, 1, __Value) +#define GET_TX_DESC_USE_MAX_TIME_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 16, 1) +#define SET_TX_DESC_NAVUSEHDR(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 15, 1, __Value) +#define GET_TX_DESC_NAVUSEHDR(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 15, 1) + +#define SET_TX_DESC_CHK_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 14, 1, __Value) +#define GET_TX_DESC_CHK_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 14, 1) + +#define SET_TX_DESC_HW_RTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 13, 1, __Value) +#define GET_TX_DESC_HW_RTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 13, 1) +#define SET_TX_DESC_RTSEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 12, 1, __Value) +#define GET_TX_DESC_RTSEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 12, 1) +#define SET_TX_DESC_CTS2SELF(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 11, 1, __Value) +#define GET_TX_DESC_CTS2SELF(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 11, 1) +#define SET_TX_DESC_DISDATAFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 10, 1, __Value) +#define GET_TX_DESC_DISDATAFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 10, 1) +#define SET_TX_DESC_DISRTSFB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 9, 1, __Value) +#define GET_TX_DESC_DISRTSFB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 9, 1) +#define SET_TX_DESC_USE_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 8, 1, __Value) +#define GET_TX_DESC_USE_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 8, 1) +#define SET_TX_DESC_HW_SSN_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 6, 2, __Value) +#define GET_TX_DESC_HW_SSN_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 6, 2) + +#define SET_TX_DESC_WHEADER_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x0C, 0, 5, __Value) +#define GET_TX_DESC_WHEADER_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x0C, 0, 5) + +/*TXDESC_WORD4*/ + +#define SET_TX_DESC_PCTS_MASK_IDX(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 30, 2, __Value) +#define GET_TX_DESC_PCTS_MASK_IDX(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 30, 2) +#define SET_TX_DESC_PCTS_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 29, 1, __Value) +#define GET_TX_DESC_PCTS_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 29, 1) +#define SET_TX_DESC_RTSRATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 24, 5, __Value) +#define GET_TX_DESC_RTSRATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 24, 5) +#define SET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 18, 6, __Value) +#define GET_TX_DESC_RTS_DATA_RTY_LMT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 18, 6) +#define SET_TX_DESC_RTY_LMT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 17, 1, __Value) +#define GET_TX_DESC_RTY_LMT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 17, 1) +#define SET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 13, 4, __Value) +#define GET_TX_DESC_RTS_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 13, 4) +#define SET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 8, 5, __Value) +#define GET_TX_DESC_DATA_RTY_LOWEST_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 8, 5) +#define SET_TX_DESC_TRY_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 7, 1, __Value) +#define GET_TX_DESC_TRY_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 7, 1) +#define SET_TX_DESC_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x10, 0, 7, __Value) +#define GET_TX_DESC_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x10, 0, 7) + +/*TXDESC_WORD5*/ + +#define SET_TX_DESC_POLLUTED(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 31, 1, __Value) +#define GET_TX_DESC_POLLUTED(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 31, 1) + +#define SET_TX_DESC_TXPWR_OFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 28, 3, __Value) +#define GET_TX_DESC_TXPWR_OFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 28, 3) +#define SET_TX_DESC_TX_ANT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 24, 4, __Value) +#define GET_TX_DESC_TX_ANT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 24, 4) +#define SET_TX_DESC_PORT_ID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 21, 3, __Value) +#define GET_TX_DESC_PORT_ID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 21, 3) + +#define SET_TX_DESC_MULTIPLE_PORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 18, 3, __Value) +#define GET_TX_DESC_MULTIPLE_PORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 18, 3) + +#define SET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 17, 1, __Value) +#define GET_TX_DESC_SIGNALING_TAPKT_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 17, 1) + +#define SET_TX_DESC_RTS_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 13, 4, __Value) +#define GET_TX_DESC_RTS_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 13, 4) +#define SET_TX_DESC_RTS_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 12, 1, __Value) +#define GET_TX_DESC_RTS_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 12, 1) + +#define SET_TX_DESC_VCS_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 10, 2, __Value) +#define GET_TX_DESC_VCS_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 10, 2) + +#define SET_TX_DESC_DATA_STBC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 8, 2, __Value) +#define GET_TX_DESC_DATA_STBC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 8, 2) + +#define SET_TX_DESC_DATA_LDPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 7, 1, __Value) +#define GET_TX_DESC_DATA_LDPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 7, 1) + +#define SET_TX_DESC_DATA_BW(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 5, 2, __Value) +#define GET_TX_DESC_DATA_BW(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 5, 2) +#define SET_TX_DESC_DATA_SHORT(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 4, 1, __Value) +#define GET_TX_DESC_DATA_SHORT(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 4, 1) +#define SET_TX_DESC_DATA_SC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x14, 0, 4, __Value) +#define GET_TX_DESC_DATA_SC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x14, 0, 4) + +/*TXDESC_WORD6*/ + +#define SET_TX_DESC_ANTSEL_D(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 30, 2, __Value) +#define GET_TX_DESC_ANTSEL_D(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 30, 2) +#define SET_TX_DESC_ANT_MAPD(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 28, 2, __Value) +#define GET_TX_DESC_ANT_MAPD(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 28, 2) +#define SET_TX_DESC_ANT_MAPC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 26, 2, __Value) +#define GET_TX_DESC_ANT_MAPC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 26, 2) +#define SET_TX_DESC_ANT_MAPB(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 24, 2, __Value) +#define GET_TX_DESC_ANT_MAPB(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 24, 2) +#define SET_TX_DESC_ANT_MAPA(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 22, 2, __Value) +#define GET_TX_DESC_ANT_MAPA(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 22, 2) +#define SET_TX_DESC_ANTSEL_C(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 20, 2, __Value) +#define GET_TX_DESC_ANTSEL_C(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 20, 2) +#define SET_TX_DESC_ANTSEL_B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 18, 2, __Value) +#define GET_TX_DESC_ANTSEL_B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 18, 2) + +#define SET_TX_DESC_ANTSEL_A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 16, 2, __Value) +#define GET_TX_DESC_ANTSEL_A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 16, 2) +#define SET_TX_DESC_MBSSID(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 12, 4, __Value) +#define GET_TX_DESC_MBSSID(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 12, 4) +#define SET_TX_DESC_SW_DEFINE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x18, 0, 12, __Value) +#define GET_TX_DESC_SW_DEFINE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x18, 0, 12) + +/*TXDESC_WORD7*/ + +#define SET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value) +#define GET_TX_DESC_DMA_TXAGG_NUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8) + +#define SET_TX_DESC_FINAL_DATA_RATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 24, 8, __Value) +#define GET_TX_DESC_FINAL_DATA_RATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 24, 8) +#define SET_TX_DESC_NTX_MAP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 20, 4, __Value) +#define GET_TX_DESC_NTX_MAP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 20, 4) + +#define SET_TX_DESC_TX_BUFF_SIZE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) +#define GET_TX_DESC_TX_BUFF_SIZE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) +#define SET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) +#define GET_TX_DESC_TXDESC_CHECKSUM(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) +#define SET_TX_DESC_TIMESTAMP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x1C, 0, 16, __Value) +#define GET_TX_DESC_TIMESTAMP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x1C, 0, 16) + +/*TXDESC_WORD8*/ + +#define SET_TX_DESC_TXWIFI_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 31, 1, __Value) +#define GET_TX_DESC_TXWIFI_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 31, 1) +#define SET_TX_DESC_MAC_CP(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 30, 1, __Value) +#define GET_TX_DESC_MAC_CP(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 30, 1) +#define SET_TX_DESC_STW_PKTRE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 29, 1, __Value) +#define GET_TX_DESC_STW_PKTRE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 29, 1) +#define SET_TX_DESC_STW_RB_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 28, 1, __Value) +#define GET_TX_DESC_STW_RB_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 28, 1) +#define SET_TX_DESC_STW_RATE_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 27, 1, __Value) +#define GET_TX_DESC_STW_RATE_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 27, 1) +#define SET_TX_DESC_STW_ANT_DIS(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 26, 1, __Value) +#define GET_TX_DESC_STW_ANT_DIS(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 26, 1) +#define SET_TX_DESC_STW_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 25, 1, __Value) +#define GET_TX_DESC_STW_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 25, 1) +#define SET_TX_DESC_SMH_EN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 1, __Value) +#define GET_TX_DESC_SMH_EN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 1) + +#define SET_TX_DESC_TAILPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 24, 8, __Value) +#define GET_TX_DESC_TAILPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 24, 8) + +#define SET_TX_DESC_SDIO_DMASEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value) +#define GET_TX_DESC_SDIO_DMASEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8) + +#define SET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 16, 8, __Value) +#define GET_TX_DESC_NEXTHEADPAGE_L(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 16, 8) +#define SET_TX_DESC_EN_HWSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 15, 1, __Value) +#define GET_TX_DESC_EN_HWSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 15, 1) + +#define SET_TX_DESC_EN_HWEXSEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 14, 1, __Value) +#define GET_TX_DESC_EN_HWEXSEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 14, 1) + +#define SET_TX_DESC_DATA_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 8, 6, __Value) +#define GET_TX_DESC_DATA_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 8, 6) +#define SET_TX_DESC_BAR_RTY_TH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 6, 2, __Value) +#define GET_TX_DESC_BAR_RTY_TH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 6, 2) +#define SET_TX_DESC_RTS_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x20, 0, 6, __Value) +#define GET_TX_DESC_RTS_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x20, 0, 6) + +/*TXDESC_WORD9*/ + +#define SET_TX_DESC_TAILPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 28, 4, __Value) +#define GET_TX_DESC_TAILPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 28, 4) +#define SET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 24, 4, __Value) +#define GET_TX_DESC_NEXTHEADPAGE_H(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 24, 4) + +#define SET_TX_DESC_SW_SEQ(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 12, 12, __Value) +#define GET_TX_DESC_SW_SEQ(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 12, 12) +#define SET_TX_DESC_TXBF_PATH(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 11, 1, __Value) +#define GET_TX_DESC_TXBF_PATH(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 11, 1) +#define SET_TX_DESC_PADDING_LEN(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 11, __Value) +#define GET_TX_DESC_PADDING_LEN(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 11) +#define SET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x24, 0, 8, __Value) +#define GET_TX_DESC_GROUP_BIT_IE_OFFSET(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x24, 0, 8) + +/*WORD10*/ + +#define SET_TX_DESC_MU_DATARATE(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 8, 8, __Value) +#define GET_TX_DESC_MU_DATARATE(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 8, 8) +#define SET_TX_DESC_MU_RC(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 4, 4, __Value) +#define GET_TX_DESC_MU_RC(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 4, 4) +#define SET_TX_DESC_SND_PKT_SEL(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc + 0x28, 0, 2, __Value) +#define GET_TX_DESC_SND_PKT_SEL(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc + 0x28, 0, 2) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/halmac/halmac_type.h b/drivers/staging/rtl8821ce/hal/halmac/halmac_type.h new file mode 100644 index 000000000000..0c84f8624e68 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/halmac/halmac_type.h @@ -0,0 +1,1905 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _HALMAC_TYPE_H_ +#define _HALMAC_TYPE_H_ + +#include "halmac_2_platform.h" +#include "halmac_fw_info.h" +#include "halmac_intf_phy_cmd.h" + +#define IN +#define OUT +#define INOUT +#define VOID void + +#define HALMAC_SCAN_CH_NUM_MAX 28 +#define HALMAC_BCN_IE_BMP_SIZE 24 /* ID0~ID191, 192/8=24 */ +#define HALMAC_PHY_PARAMETER_SIZE 12 +#define HALMAC_PHY_PARAMETER_MAX_NUM 128 +#define HALMAC_MAX_SSID_LEN 32 +#define HALMAC_SUPPORT_NLO_NUM 16 +#define HALMAC_SUPPORT_PROBE_REQ_NUM 8 +#define HALMC_DDMA_POLLING_COUNT 1000 +#define API_ARRAY_SIZE 32 + +#ifndef HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE +#define HALMAC_RX_FIFO_EXPANDING_MODE_PKT_SIZE 48 +#endif + +/* platform api */ +#define PLATFORM_SDIO_CMD52_READ pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_READ +#define PLATFORM_SDIO_CMD53_READ_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_8 +#define PLATFORM_SDIO_CMD53_READ_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_16 +#define PLATFORM_SDIO_CMD53_READ_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_32 +#define PLATFORM_SDIO_CMD53_READ_N pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_READ_N +#define PLATFORM_SDIO_CMD52_WRITE pHalmac_adapter->pHalmac_platform_api->SDIO_CMD52_WRITE +#define PLATFORM_SDIO_CMD53_WRITE_8 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_8 +#define PLATFORM_SDIO_CMD53_WRITE_16 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_16 +#define PLATFORM_SDIO_CMD53_WRITE_32 pHalmac_adapter->pHalmac_platform_api->SDIO_CMD53_WRITE_32 + +#define PLATFORM_REG_READ_8 pHalmac_adapter->pHalmac_platform_api->REG_READ_8 +#define PLATFORM_REG_READ_16 pHalmac_adapter->pHalmac_platform_api->REG_READ_16 +#define PLATFORM_REG_READ_32 pHalmac_adapter->pHalmac_platform_api->REG_READ_32 +#define PLATFORM_REG_WRITE_8 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_8 +#define PLATFORM_REG_WRITE_16 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_16 +#define PLATFORM_REG_WRITE_32 pHalmac_adapter->pHalmac_platform_api->REG_WRITE_32 + +#define PLATFORM_SEND_RSVD_PAGE pHalmac_adapter->pHalmac_platform_api->SEND_RSVD_PAGE +#define PLATFORM_SEND_H2C_PKT pHalmac_adapter->pHalmac_platform_api->SEND_H2C_PKT + +#define PLATFORM_RTL_FREE pHalmac_adapter->pHalmac_platform_api->RTL_FREE +#define PLATFORM_RTL_MALLOC pHalmac_adapter->pHalmac_platform_api->RTL_MALLOC +#define PLATFORM_RTL_MEMCPY pHalmac_adapter->pHalmac_platform_api->RTL_MEMCPY +#define PLATFORM_RTL_MEMSET pHalmac_adapter->pHalmac_platform_api->RTL_MEMSET +#define PLATFORM_RTL_DELAY_US pHalmac_adapter->pHalmac_platform_api->RTL_DELAY_US + +#define PLATFORM_MUTEX_INIT pHalmac_adapter->pHalmac_platform_api->MUTEX_INIT +#define PLATFORM_MUTEX_DEINIT pHalmac_adapter->pHalmac_platform_api->MUTEX_DEINIT +#define PLATFORM_MUTEX_LOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_LOCK +#define PLATFORM_MUTEX_UNLOCK pHalmac_adapter->pHalmac_platform_api->MUTEX_UNLOCK + +#define PLATFORM_EVENT_INDICATION pHalmac_adapter->pHalmac_platform_api->EVENT_INDICATION + +#if HALMAC_DBG_MSG_ENABLE +#define PLATFORM_MSG_PRINT pHalmac_adapter->pHalmac_platform_api->MSG_PRINT +#else +#define PLATFORM_MSG_PRINT(pDriver_adapter, msg_type, msg_level, fmt, ...) +#endif + +#define HALMAC_REG_READ_8 pHalmac_api->halmac_reg_read_8 +#define HALMAC_REG_READ_16 pHalmac_api->halmac_reg_read_16 +#define HALMAC_REG_READ_32 pHalmac_api->halmac_reg_read_32 +#define HALMAC_REG_WRITE_8 pHalmac_api->halmac_reg_write_8 +#define HALMAC_REG_WRITE_16 pHalmac_api->halmac_reg_write_16 +#define HALMAC_REG_WRITE_32 pHalmac_api->halmac_reg_write_32 +#define HALMAC_REG_SDIO_CMD53_READ_N pHalmac_api->halmac_reg_sdio_cmd53_read_n + +/* Swap Little-endian <-> Big-endia*/ +#define SWAP32(x) ((u32)( \ + (((u32)(x) & (u32)0x000000ff) << 24) | \ + (((u32)(x) & (u32)0x0000ff00) << 8) | \ + (((u32)(x) & (u32)0x00ff0000) >> 8) | \ + (((u32)(x) & (u32)0xff000000) >> 24))) + +#define SWAP16(x) ((u16)( \ + (((u16)(x) & (u16)0x00ff) << 8) | \ + (((u16)(x) & (u16)0xff00) >> 8))) + +/*1->Little endian 0->Big endian*/ +#if HALMAC_SYSTEM_ENDIAN +#ifndef rtk_le16_to_cpu +#define rtk_cpu_to_le32(x) ((u32)(x)) +#define rtk_le32_to_cpu(x) ((u32)(x)) +#define rtk_cpu_to_le16(x) ((u16)(x)) +#define rtk_le16_to_cpu(x) ((u16)(x)) +#define rtk_cpu_to_be32(x) SWAP32((x)) +#define rtk_be32_to_cpu(x) SWAP32((x)) +#define rtk_cpu_to_be16(x) SWAP16((x)) +#define rtk_be16_to_cpu(x) SWAP16((x)) +#endif +#else +#ifndef rtk_le16_to_cpu +#define rtk_cpu_to_le32(x) SWAP32((x)) +#define rtk_le32_to_cpu(x) SWAP32((x)) +#define rtk_cpu_to_le16(x) SWAP16((x)) +#define rtk_le16_to_cpu(x) SWAP16((x)) +#define rtk_cpu_to_be32(x) ((u32)(x)) +#define rtk_be32_to_cpu(x) ((u32)(x)) +#define rtk_cpu_to_be16(x) ((u16)(x)) +#define rtk_be16_to_cpu(x) ((u16)(x)) +#endif +#endif + +#define HALMAC_ALIGN(x, a) HALMAC_ALIGN_MASK(x, (a) - 1) +#define HALMAC_ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask)) + +/* #if !HALMAC_PLATFORM_WINDOWS */ +#if !((HALMAC_PLATFORM_WINDOWS == 1) && (HALMAC_PLATFORM_TESTPROGRAM == 0)) + +/* Byte Swapping routine */ +#ifndef EF1Byte +#define EF1Byte (u8) +#endif + +#ifndef EF2Byte +#define EF2Byte rtk_le16_to_cpu +#endif + +#ifndef EF4Byte +#define EF4Byte rtk_le32_to_cpu +#endif + +/* Example: + * BIT_LEN_MASK_32(0) => 0x00000000 + * BIT_LEN_MASK_32(1) => 0x00000001 + * BIT_LEN_MASK_32(2) => 0x00000003 + * BIT_LEN_MASK_32(32) => 0xFFFFFFFF + */ +#ifndef BIT_LEN_MASK_32 +#define BIT_LEN_MASK_32(__BitLen) \ + (0xFFFFFFFF >> (32 - (__BitLen))) +#endif + +/* Example: + * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 + * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 + */ +#ifndef BIT_OFFSET_LEN_MASK_32 +#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ + (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) +#endif + +/* Return 4-byte value in host byte ordering from + * 4-byte pointer in litten-endian system + */ +#ifndef LE_P4BYTE_TO_HOST_4BYTE +#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + (EF4Byte(*((u32 *)(__pStart)))) +#endif + +/* Translate subfield (continuous bits in little-endian) of + * 4-byte value in litten byte to 4-byte value in host byte ordering + */ +#ifndef LE_BITS_TO_4BYTE +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + (LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) \ + & \ + BIT_LEN_MASK_32(__BitLen) \ + ) +#endif + +/* Mask subfield (continuous bits in little-endian) of 4-byte + * value in litten byte oredering and return the result in 4-byte + * value in host byte ordering + */ +#ifndef LE_BITS_CLEARED_TO_4BYTE +#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ( \ + LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ + & \ + (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen)) \ + ) +#endif + +/* Set subfield of little-endian 4-byte value to specified value */ +#ifndef SET_BITS_TO_LE_4BYTE +#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + *((u32 *)(__pStart)) = \ + EF4Byte( \ + LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ + ); \ + } while (0) +#endif + +#ifndef HALMAC_BIT_OFFSET_VAL_MASK_32 +#define HALMAC_BIT_OFFSET_VAL_MASK_32(__BitVal, __BitOffset) \ + (__BitVal << (__BitOffset)) +#endif + +#ifndef SET_MEM_OP +#define SET_MEM_OP(Dw, Value32, Mask, Shift) \ + (((Dw) & ~((Mask) << (Shift))) | (((Value32) & (Mask)) << (Shift))) +#endif + +#ifndef HALMAC_SET_DESC_FIELD_CLR +#define HALMAC_SET_DESC_FIELD_CLR(Dw, Value32, Mask, Shift) \ + (Dw = (rtk_cpu_to_le32(SET_MEM_OP(rtk_cpu_to_le32(Dw), Value32, Mask, Shift)))) +#endif + +#ifndef HALMAC_SET_DESC_FIELD_NO_CLR +#define HALMAC_SET_DESC_FIELD_NO_CLR(Dw, Value32, Mask, Shift) \ + (Dw |= (rtk_cpu_to_le32(((Value32) & (Mask)) << (Shift)))) +#endif + +#ifndef HALMAC_GET_DESC_FIELD +#define HALMAC_GET_DESC_FIELD(Dw, Mask, Shift) \ + ((rtk_le32_to_cpu(Dw) >> (Shift)) & (Mask)) +#endif + +#define HALMAC_SET_BD_FIELD_CLR HALMAC_SET_DESC_FIELD_CLR +#define HALMAC_SET_BD_FIELD_NO_CLR HALMAC_SET_DESC_FIELD_NO_CLR +#define HALMAC_GET_BD_FIELD HALMAC_GET_DESC_FIELD + +#ifndef GET_H2C_FIELD +#define GET_H2C_FIELD LE_BITS_TO_4BYTE +#endif + +#ifndef SET_H2C_FIELD_CLR +#define SET_H2C_FIELD_CLR SET_BITS_TO_LE_4BYTE +#endif + +#ifndef SET_H2C_FIELD_NO_CLR +#define SET_H2C_FIELD_NO_CLR SET_BITS_TO_LE_4BYTE +#endif + +#ifndef GET_C2H_FIELD +#define GET_C2H_FIELD LE_BITS_TO_4BYTE +#endif + +#ifndef SET_C2H_FIELD_CLR +#define SET_C2H_FIELD_CLR SET_BITS_TO_LE_4BYTE +#endif + +#ifndef SET_C2H_FIELD_NO_CLR +#define SET_C2H_FIELD_NO_CLR SET_BITS_TO_LE_4BYTE +#endif + +#endif /* #if !HALMAC_PLATFORM_WINDOWS */ + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +/* HALMAC API return status*/ +typedef enum _HALMAC_RET_STATUS { + HALMAC_RET_SUCCESS = 0x00, + HALMAC_RET_SUCCESS_ENQUEUE = 0x01, + HALMAC_RET_PLATFORM_API_NULL = 0x02, + HALMAC_RET_EFUSE_SIZE_INCORRECT = 0x03, + HALMAC_RET_MALLOC_FAIL = 0x04, + HALMAC_RET_ADAPTER_INVALID = 0x05, + HALMAC_RET_ITF_INCORRECT = 0x06, + HALMAC_RET_DLFW_FAIL = 0x07, + HALMAC_RET_PORT_NOT_SUPPORT = 0x08, + HALMAC_RET_TRXMODE_NOT_SUPPORT = 0x09, + HALMAC_RET_INIT_LLT_FAIL = 0x0A, + HALMAC_RET_POWER_STATE_INVALID = 0x0B, + HALMAC_RET_H2C_ACK_NOT_RECEIVED = 0x0C, + HALMAC_RET_DL_RSVD_PAGE_FAIL = 0x0D, + HALMAC_RET_EFUSE_R_FAIL = 0x0E, + HALMAC_RET_EFUSE_W_FAIL = 0x0F, + HALMAC_RET_H2C_SW_RES_FAIL = 0x10, + HALMAC_RET_SEND_H2C_FAIL = 0x11, + HALMAC_RET_PARA_NOT_SUPPORT = 0x12, + HALMAC_RET_PLATFORM_API_INCORRECT = 0x13, + HALMAC_RET_ENDIAN_ERR = 0x14, + HALMAC_RET_FW_SIZE_ERR = 0x15, + HALMAC_RET_TRX_MODE_NOT_SUPPORT = 0x16, + HALMAC_RET_FAIL = 0x17, + HALMAC_RET_CHANGE_PS_FAIL = 0x18, + HALMAC_RET_CFG_PARA_FAIL = 0x19, + HALMAC_RET_UPDATE_PROBE_FAIL = 0x1A, + HALMAC_RET_SCAN_FAIL = 0x1B, + HALMAC_RET_STOP_SCAN_FAIL = 0x1C, + HALMAC_RET_BCN_PARSER_CMD_FAIL = 0x1D, + HALMAC_RET_POWER_ON_FAIL = 0x1E, + HALMAC_RET_POWER_OFF_FAIL = 0x1F, + HALMAC_RET_RX_AGG_MODE_FAIL = 0x20, + HALMAC_RET_DATA_BUF_NULL = 0x21, + HALMAC_RET_DATA_SIZE_INCORRECT = 0x22, + HALMAC_RET_QSEL_INCORRECT = 0x23, + HALMAC_RET_DMA_MAP_INCORRECT = 0x24, + HALMAC_RET_SEND_ORIGINAL_H2C_FAIL = 0x25, + HALMAC_RET_DDMA_FAIL = 0x26, + HALMAC_RET_FW_CHECKSUM_FAIL = 0x27, + HALMAC_RET_PWRSEQ_POLLING_FAIL = 0x28, + HALMAC_RET_PWRSEQ_CMD_INCORRECT = 0x29, + HALMAC_RET_WRITE_DATA_FAIL = 0x2A, + HALMAC_RET_DUMP_FIFOSIZE_INCORRECT = 0x2B, + HALMAC_RET_NULL_POINTER = 0x2C, + HALMAC_RET_PROBE_NOT_FOUND = 0x2D, + HALMAC_RET_FW_NO_MEMORY = 0x2E, + HALMAC_RET_H2C_STATUS_ERR = 0x2F, + HALMAC_RET_GET_H2C_SPACE_ERR = 0x30, + HALMAC_RET_H2C_SPACE_FULL = 0x31, + HALMAC_RET_DATAPACK_NO_FOUND = 0x32, + HALMAC_RET_CANNOT_FIND_H2C_RESOURCE = 0x33, + HALMAC_RET_TX_DMA_ERR = 0x34, + HALMAC_RET_RX_DMA_ERR = 0x35, + HALMAC_RET_CHIP_NOT_SUPPORT = 0x36, + HALMAC_RET_FREE_SPACE_NOT_ENOUGH = 0x37, + HALMAC_RET_CH_SW_SEQ_WRONG = 0x38, + HALMAC_RET_CH_SW_NO_BUF = 0x39, + HALMAC_RET_SW_CASE_NOT_SUPPORT = 0x3A, + HALMAC_RET_CONVERT_SDIO_OFFSET_FAIL = 0x3B, + HALMAC_RET_INVALID_SOUNDING_SETTING = 0x3C, + HALMAC_RET_GEN_INFO_NOT_SENT = 0x3D, + HALMAC_RET_STATE_INCORRECT = 0x3E, + HALMAC_RET_H2C_BUSY = 0x3F, + HALMAC_RET_INVALID_FEATURE_ID = 0x40, + HALMAC_RET_BUFFER_TOO_SMALL = 0x41, + HALMAC_RET_ZERO_LEN_RSVD_PACKET = 0x42, + HALMAC_RET_BUSY_STATE = 0x43, + HALMAC_RET_ERROR_STATE = 0x44, + HALMAC_RET_API_INVALID = 0x45, + HALMAC_RET_POLLING_BCN_VALID_FAIL = 0x46, + HALMAC_RET_SDIO_LEAVE_SUSPEND_FAIL = 0x47, + HALMAC_RET_EEPROM_PARSING_FAIL = 0x48, + HALMAC_RET_EFUSE_NOT_ENOUGH = 0x49, + HALMAC_RET_WRONG_ARGUMENT = 0x4A, + HALMAC_RET_NOT_SUPPORT = 0x4B, + HALMAC_RET_C2H_NOT_HANDLED = 0x4C, + HALMAC_RET_PARA_SENDING = 0x4D, + HALMAC_RET_CFG_DLFW_SIZE_FAIL = 0x4E, + HALMAC_RET_CFG_TXFIFO_PAGE_FAIL = 0x4F, + HALMAC_RET_SWITCH_CASE_ERROR = 0x50, + HALMAC_RET_EFUSE_BANK_INCORRECT = 0x51, + HALMAC_RET_SWITCH_EFUSE_BANK_FAIL = 0x52, + HALMAC_RET_USB_MODE_UNCHANGE = 0x53, + HALMAC_RET_NO_DLFW = 0x54, + HALMAC_RET_USB2_3_SWITCH_UNSUPPORT = 0x55, + HALMAC_RET_BIP_NO_SUPPORT = 0x56, + HALMAC_RET_ENTRY_INDEX_ERROR = 0x57, + HALMAC_RET_ENTRY_KEY_ID_ERROR = 0x58, + HALMAC_RET_DRV_DL_ERR = 0x59, + HALMAC_RET_OQT_NOT_ENOUGH = 0x5A, + HALMAC_RET_PWR_UNCHANGE = 0x5B, + HALMAC_RET_WRONG_INTF = 0x5C, + HALMAC_RET_FW_NO_SUPPORT = 0x60, + HALMAC_RET_TXFIFO_NO_EMPTY = 0x61, + HALMAC_RET_SDIO_CLOCK_ERR = 0x62, +} HALMAC_RET_STATUS; + +typedef enum _HALMAC_MAC_CLOCK_HW_DEF { + HALMAC_MAC_CLOCK_HW_DEF_80M = 0, + HALMAC_MAC_CLOCK_HW_DEF_40M = 1, + HALMAC_MAC_CLOCK_HW_DEF_20M = 2, +} HALMAC_MAC_CLOCK_HW_DEF; + +/* Rx aggregation parameters */ +typedef enum _HALMAC_NORMAL_RXAGG_TH_TO { + HALMAC_NORMAL_RXAGG_THRESHOLD = 0xFF, + HALMAC_NORMAL_RXAGG_TIMEOUT = 0x01, +} HALMAC_NORMAL_RXAGG_TH_TO; + +typedef enum _HALMAC_LOOPBACK_RXAGG_TH_TO { + HALMAC_LOOPBACK_RXAGG_THRESHOLD = 0xFF, + HALMAC_LOOPBACK_RXAGG_TIMEOUT = 0x01, +} HALMAC_LOOPBACK_RXAGG_TH_TO; + +/* Chip ID*/ +typedef enum _HALMAC_CHIP_ID { + HALMAC_CHIP_ID_8822B = 0, + HALMAC_CHIP_ID_8821C = 1, + HALMAC_CHIP_ID_8814B = 2, + HALMAC_CHIP_ID_8197F = 3, + HALMAC_CHIP_ID_UNDEFINE = 0x7F, +} HALMAC_CHIP_ID; + +typedef enum _HALMAC_CHIP_ID_HW_DEF { + HALMAC_CHIP_ID_HW_DEF_8723A = 0x01, + HALMAC_CHIP_ID_HW_DEF_8188E = 0x02, + HALMAC_CHIP_ID_HW_DEF_8881A = 0x03, + HALMAC_CHIP_ID_HW_DEF_8812A = 0x04, + HALMAC_CHIP_ID_HW_DEF_8821A = 0x05, + HALMAC_CHIP_ID_HW_DEF_8723B = 0x06, + HALMAC_CHIP_ID_HW_DEF_8192E = 0x07, + HALMAC_CHIP_ID_HW_DEF_8814A = 0x08, + HALMAC_CHIP_ID_HW_DEF_8821C = 0x09, + HALMAC_CHIP_ID_HW_DEF_8822B = 0x0A, + HALMAC_CHIP_ID_HW_DEF_8703B = 0x0B, + HALMAC_CHIP_ID_HW_DEF_8188F = 0x0C, + HALMAC_CHIP_ID_HW_DEF_8192F = 0x0D, + HALMAC_CHIP_ID_HW_DEF_8197F = 0x0E, + HALMAC_CHIP_ID_HW_DEF_8723D = 0x0F, + HALMAC_CHIP_ID_HW_DEF_8814B = 0x10, + HALMAC_CHIP_ID_HW_DEF_UNDEFINE = 0x7F, + HALMAC_CHIP_ID_HW_DEF_PS = 0xEA, +} HALMAC_CHIP_ID_HW_DEF; + +/* Chip Version*/ +typedef enum _HALMAC_CHIP_VER { + HALMAC_CHIP_VER_A_CUT = 0x00, + HALMAC_CHIP_VER_B_CUT = 0x01, + HALMAC_CHIP_VER_C_CUT = 0x02, + HALMAC_CHIP_VER_D_CUT = 0x03, + HALMAC_CHIP_VER_E_CUT = 0x04, + HALMAC_CHIP_VER_F_CUT = 0x05, + HALMAC_CHIP_VER_TEST = 0xFF, + HALMAC_CHIP_VER_UNDEFINE = 0x7FFF, +} HALMAC_CHIP_VER; + +/* Network type select */ +typedef enum _HALMAC_NETWORK_TYPE_SELECT { + HALMAC_NETWORK_NO_LINK = 0, + HALMAC_NETWORK_ADHOC = 1, + HALMAC_NETWORK_INFRASTRUCTURE = 2, + HALMAC_NETWORK_AP = 3, + HALMAC_NETWORK_UNDEFINE = 0x7F, +} HALMAC_NETWORK_TYPE_SELECT; + +/* Transfer mode select */ +typedef enum _HALMAC_TRNSFER_MODE_SELECT { + HALMAC_TRNSFER_NORMAL = 0x0, + HALMAC_TRNSFER_LOOPBACK_DIRECT = 0xB, + HALMAC_TRNSFER_LOOPBACK_DELAY = 0x3, + HALMAC_TRNSFER_UNDEFINE = 0x7F, +} HALMAC_TRNSFER_MODE_SELECT; + +/* Queue select */ +typedef enum _HALMAC_DMA_MAPPING { + HALMAC_DMA_MAPPING_EXTRA = 0, + HALMAC_DMA_MAPPING_LOW = 1, + HALMAC_DMA_MAPPING_NORMAL = 2, + HALMAC_DMA_MAPPING_HIGH = 3, + HALMAC_DMA_MAPPING_UNDEFINE = 0x7F, +} HALMAC_DMA_MAPPING; + +#define HALMAC_MAP2_HQ HALMAC_DMA_MAPPING_HIGH +#define HALMAC_MAP2_NQ HALMAC_DMA_MAPPING_NORMAL +#define HALMAC_MAP2_LQ HALMAC_DMA_MAPPING_LOW +#define HALMAC_MAP2_EXQ HALMAC_DMA_MAPPING_EXTRA +#define HALMAC_MAP2_UNDEF HALMAC_DMA_MAPPING_UNDEFINE + +/* TXDESC queue select TID */ +typedef enum _HALMAC_TXDESC_QUEUE_TID { + HALMAC_TXDESC_QSEL_TID0 = 0, + HALMAC_TXDESC_QSEL_TID1 = 1, + HALMAC_TXDESC_QSEL_TID2 = 2, + HALMAC_TXDESC_QSEL_TID3 = 3, + HALMAC_TXDESC_QSEL_TID4 = 4, + HALMAC_TXDESC_QSEL_TID5 = 5, + HALMAC_TXDESC_QSEL_TID6 = 6, + HALMAC_TXDESC_QSEL_TID7 = 7, + HALMAC_TXDESC_QSEL_TID8 = 8, + HALMAC_TXDESC_QSEL_TID9 = 9, + HALMAC_TXDESC_QSEL_TIDA = 10, + HALMAC_TXDESC_QSEL_TIDB = 11, + HALMAC_TXDESC_QSEL_TIDC = 12, + HALMAC_TXDESC_QSEL_TIDD = 13, + HALMAC_TXDESC_QSEL_TIDE = 14, + HALMAC_TXDESC_QSEL_TIDF = 15, + + HALMAC_TXDESC_QSEL_BEACON = 0x10, + HALMAC_TXDESC_QSEL_HIGH = 0x11, + HALMAC_TXDESC_QSEL_MGT = 0x12, + HALMAC_TXDESC_QSEL_H2C_CMD = 0x13, + + HALMAC_TXDESC_QSEL_UNDEFINE = 0x7F, +} HALMAC_TXDESC_QUEUE_TID; + +typedef enum _HALMAC_PTCL_QUEUE { + HALMAC_PTCL_QUEUE_VO = 0x0, + HALMAC_PTCL_QUEUE_VI = 0x1, + HALMAC_PTCL_QUEUE_BE = 0x2, + HALMAC_PTCL_QUEUE_BK = 0x3, + HALMAC_PTCL_QUEUE_MG = 0x4, + HALMAC_PTCL_QUEUE_HI = 0x5, + HALMAC_PTCL_QUEUE_NUM = 0x6, + HALMAC_PTCL_QUEUE_UNDEFINE = 0x7F, +} HALMAC_PTCL_QUEUE; + +typedef enum { + HALMAC_QUEUE_SELECT_VO = HALMAC_TXDESC_QSEL_TID6, + HALMAC_QUEUE_SELECT_VI = HALMAC_TXDESC_QSEL_TID4, + HALMAC_QUEUE_SELECT_BE = HALMAC_TXDESC_QSEL_TID0, + HALMAC_QUEUE_SELECT_BK = HALMAC_TXDESC_QSEL_TID1, + HALMAC_QUEUE_SELECT_VO_V2 = HALMAC_TXDESC_QSEL_TID7, + HALMAC_QUEUE_SELECT_VI_V2 = HALMAC_TXDESC_QSEL_TID5, + HALMAC_QUEUE_SELECT_BE_V2 = HALMAC_TXDESC_QSEL_TID3, + HALMAC_QUEUE_SELECT_BK_V2 = HALMAC_TXDESC_QSEL_TID2, + HALMAC_QUEUE_SELECT_BCN = HALMAC_TXDESC_QSEL_BEACON, + HALMAC_QUEUE_SELECT_HIGH = HALMAC_TXDESC_QSEL_HIGH, + HALMAC_QUEUE_SELECT_MGNT = HALMAC_TXDESC_QSEL_MGT, + HALMAC_QUEUE_SELECT_CMD = HALMAC_TXDESC_QSEL_H2C_CMD, + HALMAC_QUEUE_SELECT_UNDEFINE = 0x7F, +} HALMAC_QUEUE_SELECT; + +/* USB burst size */ +typedef enum _HALMAC_USB_BURST_SIZE { + HALMAC_USB_BURST_SIZE_3_0 = 0x0, + HALMAC_USB_BURST_SIZE_2_0_HSPEED = 0x1, + HALMAC_USB_BURST_SIZE_2_0_FSPEED = 0x2, + HALMAC_USB_BURST_SIZE_2_0_OTHERS = 0x3, + HALMAC_USB_BURST_SIZE_UNDEFINE = 0x7F, +} HALMAC_USB_BURST_SIZE; + +/* HAL API function parameters*/ +typedef enum _HALMAC_INTERFACE { + HALMAC_INTERFACE_PCIE = 0x0, + HALMAC_INTERFACE_USB = 0x1, + HALMAC_INTERFACE_SDIO = 0x2, + HALMAC_INTERFACE_AXI = 0x3, + HALMAC_INTERFACE_UNDEFINE = 0x7F, +} HALMAC_INTERFACE; + +typedef enum _HALMAC_RX_AGG_MODE { + HALMAC_RX_AGG_MODE_NONE = 0x0, + HALMAC_RX_AGG_MODE_DMA = 0x1, + HALMAC_RX_AGG_MODE_USB = 0x2, + HALMAC_RX_AGG_MODE_UNDEFINE = 0x7F, +} HALMAC_RX_AGG_MODE; +typedef struct _HALMAC_RXAGG_TH { + u8 drv_define; + u8 timeout; + u8 size; +} HALMAC_RXAGG_TH, *PHALMAC_RXAGG_TH; + +typedef struct _HALMAC_RXAGG_CFG { + HALMAC_RX_AGG_MODE mode; + HALMAC_RXAGG_TH threshold; +} HALMAC_RXAGG_CFG, *PHALMAC_RXAGG_CFG; + +typedef enum _HALMAC_MAC_POWER { + HALMAC_MAC_POWER_OFF = 0x0, + HALMAC_MAC_POWER_ON = 0x1, + HALMAC_MAC_POWER_UNDEFINE = 0x7F, +} HALMAC_MAC_POWER; + +typedef enum _HALMAC_PS_STATE { + HALMAC_PS_STATE_ACT = 0x0, + HALMAC_PS_STATE_LPS = 0x1, + HALMAC_PS_STATE_IPS = 0x2, + HALMAC_PS_STATE_UNDEFINE = 0x7F, +} HALMAC_PS_STATE; + +typedef enum _HALMAC_TRX_MODE { + HALMAC_TRX_MODE_NORMAL = 0x0, + HALMAC_TRX_MODE_TRXSHARE = 0x1, + HALMAC_TRX_MODE_WMM = 0x2, + HALMAC_TRX_MODE_P2P = 0x3, + HALMAC_TRX_MODE_LOOPBACK = 0x4, + HALMAC_TRX_MODE_DELAY_LOOPBACK = 0x5, + HALMAC_TRX_MODE_MAX = 0x6, + HALMAC_TRX_MODE_WMM_LINUX = 0x7E, + HALMAC_TRX_MODE_UNDEFINE = 0x7F, +} HALMAC_TRX_MODE; + +typedef enum _HALMAC_WIRELESS_MODE { + HALMAC_WIRELESS_MODE_B = 0x0, + HALMAC_WIRELESS_MODE_G = 0x1, + HALMAC_WIRELESS_MODE_N = 0x2, + HALMAC_WIRELESS_MODE_AC = 0x3, + HALMAC_WIRELESS_MODE_UNDEFINE = 0x7F, +} HALMAC_WIRELESS_MODE; + +typedef enum _HALMAC_BW { + HALMAC_BW_20 = 0x00, + HALMAC_BW_40 = 0x01, + HALMAC_BW_80 = 0x02, + HALMAC_BW_160 = 0x03, + HALMAC_BW_5 = 0x04, + HALMAC_BW_10 = 0x05, + HALMAC_BW_MAX = 0x06, + HALMAC_BW_UNDEFINE = 0x7F, +} HALMAC_BW; + +typedef enum _HALMAC_EFUSE_READ_CFG { + HALMAC_EFUSE_R_AUTO = 0x00, + HALMAC_EFUSE_R_DRV = 0x01, + HALMAC_EFUSE_R_FW = 0x02, + HALMAC_EFUSE_R_UNDEFINE = 0x7F, +} HALMAC_EFUSE_READ_CFG; + +typedef enum _HALMAC_DLFW_MEM { + HALMAC_DLFW_MEM_EMEM = 0x00, + HALMAC_DLFW_MEM_UNDEFINE = 0x7F, +} HALMAC_DLFW_MEM; + +typedef struct _HALMAC_TX_DESC { + u32 Dword0; + u32 Dword1; + u32 Dword2; + u32 Dword3; + u32 Dword4; + u32 Dword5; + u32 Dword6; + u32 Dword7; + u32 Dword8; + u32 Dword9; + u32 Dword10; + u32 Dword11; +} HALMAC_TX_DESC, *PHALMAC_TX_DESC; + +typedef struct _HALMAC_RX_DESC { + u32 Dword0; + u32 Dword1; + u32 Dword2; + u32 Dword3; + u32 Dword4; + u32 Dword5; +} HALMAC_RX_DESC, *PHALMAC_RX_DESC; + +typedef struct _HALMAC_FWLPS_OPTION { + u8 mode; + u8 clk_request; + u8 rlbm; + u8 smart_ps; + u8 awake_interval; + u8 all_queue_uapsd; + u8 pwr_state; + u8 low_pwr_rx_beacon; + u8 ant_auto_switch; + u8 ps_allow_bt_high_Priority; + u8 protect_bcn; + u8 silence_period; + u8 fast_bt_connect; + u8 two_antenna_en; + u8 adopt_user_Setting; + u8 drv_bcn_early_shift; + u8 enter_32K; +} HALMAC_FWLPS_OPTION, *PHALMAC_FWLPS_OPTION; + +typedef struct _HALMAC_FWIPS_OPTION { + u8 adopt_user_Setting; +} HALMAC_FWIPS_OPTION, *PHALMAC_FWIPS_OPTION; + +typedef struct _HALMAC_WOWLAN_OPTION { + u8 adopt_user_Setting; +} HALMAC_WOWLAN_OPTION, *PHALMAC_WOWLAN_OPTION; + +typedef struct _HALMAC_BCN_IE_INFO { + u8 func_en; + u8 size_th; + u8 timeout; + u8 ie_bmp[HALMAC_BCN_IE_BMP_SIZE]; +} HALMAC_BCN_IE_INFO, *PHALMAC_BCN_IE_INFO; + +typedef enum _HALMAC_REG_TYPE { + HALMAC_REG_TYPE_MAC = 0x0, + HALMAC_REG_TYPE_BB = 0x1, + HALMAC_REG_TYPE_RF = 0x2, + HALMAC_REG_TYPE_UNDEFINE = 0x7F, +} HALMAC_REG_TYPE; + +typedef enum _HALMAC_PARAMETER_CMD { + /* HALMAC_PARAMETER_CMD_LLT = 0x1, */ + /* HALMAC_PARAMETER_CMD_R_EFUSE = 0x2, */ + /* HALMAC_PARAMETER_CMD_EFUSE_PATCH = 0x3, */ + HALMAC_PARAMETER_CMD_MAC_W8 = 0x4, + HALMAC_PARAMETER_CMD_MAC_W16 = 0x5, + HALMAC_PARAMETER_CMD_MAC_W32 = 0x6, + HALMAC_PARAMETER_CMD_RF_W = 0x7, + HALMAC_PARAMETER_CMD_BB_W8 = 0x8, + HALMAC_PARAMETER_CMD_BB_W16 = 0x9, + HALMAC_PARAMETER_CMD_BB_W32 = 0XA, + HALMAC_PARAMETER_CMD_DELAY_US = 0X10, + HALMAC_PARAMETER_CMD_DELAY_MS = 0X11, + HALMAC_PARAMETER_CMD_END = 0XFF, +} HALMAC_PARAMETER_CMD; + +typedef union _HALMAC_PARAMETER_CONTENT { + struct _MAC_REG_W { + u32 value; + u32 msk; + u16 offset; + u8 msk_en; + } MAC_REG_W; + struct _BB_REG_W { + u32 value; + u32 msk; + u16 offset; + u8 msk_en; + } BB_REG_W; + struct _RF_REG_W { + u32 value; + u32 msk; + u8 offset; + u8 msk_en; + u8 rf_path; + } RF_REG_W; + struct _DELAY_TIME { + u32 rsvd1; + u32 rsvd2; + u16 delay_time; + u8 rsvd3; + } DELAY_TIME; +} HALMAC_PARAMETER_CONTENT, *PHALMAC_PARAMETER_CONTENT; + +typedef struct _HALMAC_PHY_PARAMETER_INFO { + HALMAC_PARAMETER_CMD cmd_id; + HALMAC_PARAMETER_CONTENT content; +} HALMAC_PHY_PARAMETER_INFO, *PHALMAC_PHY_PARAMETER_INFO; + +typedef struct _HALMAC_H2C_INFO { + u16 h2c_seq_num; /* H2C sequence number */ + u8 in_use; /* 0 : empty 1 : used */ + HALMAC_H2C_RETURN_CODE status; +} HALMAC_H2C_INFO, *PHALMAC_H2C_INFO; + +typedef struct _HALMAC_PG_EFUSE_INFO { + u8 *pEfuse_map; + u32 efuse_map_size; + u8 *pEfuse_mask; + u32 efuse_mask_size; +} HALMAC_PG_EFUSE_INFO, *PHALMAC_PG_EFUSE_INFO; + +typedef struct _HALMAC_TXAGG_BUFF_INFO { + u8 *pTx_agg_buf; + u8 *pCurr_pkt_buf; + u32 avai_buf_size; + u32 total_pkt_size; + u8 agg_num; +} HALMAC_TXAGG_BUFF_INFO, *PHALMAC_TXAGG_BUFF_INFO; + +typedef struct _HALMAC_CONFIG_PARA_INFO { + u32 para_buf_size; /* Parameter buffer size */ + u8 *pCfg_para_buf; /* Buffer for config parameter */ + u8 *pPara_buf_w; /* Write pointer of the parameter buffer */ + u32 para_num; /* Parameter numbers in parameter buffer */ + u32 avai_para_buf_size; /* Free size of parameter buffer */ + u32 offset_accumulation; + u32 value_accumulation; + HALMAC_DATA_TYPE data_type; /*DataType which is passed to FW*/ + u8 datapack_segment; /*DataPack Segment, from segment0...*/ + u8 full_fifo_mode; /* Used full tx fifo to save cfg parameter */ +} HALMAC_CONFIG_PARA_INFO, *PHALMAC_CONFIG_PARA_INFO; + +typedef struct _HALMAC_HW_CONFIG_INFO { + u32 efuse_size; /* Record efuse size */ + u32 eeprom_size; /* Record eeprom size */ + u32 bt_efuse_size; /* Record BT efuse size */ + u32 tx_fifo_size; /* Record tx fifo size */ + u32 rx_fifo_size; /* Record rx fifo size */ + u8 txdesc_size; /* Record tx desc size */ + u8 rxdesc_size; /* Record rx desc size */ + u32 page_size; /* Record page size */ + u16 tx_align_size; + u8 page_size_2_power; + u8 cam_entry_num; /* Record CAM entry number */ +} HALMAC_HW_CONFIG_INFO, *PHALMAC_HW_CONFIG_INFO; + +typedef struct _HALMAC_SDIO_FREE_SPACE { + u16 high_queue_number; /* Free space of HIQ */ + u16 normal_queue_number; /* Free space of MIDQ */ + u16 low_queue_number; /* Free space of LOWQ */ + u16 public_queue_number; /* Free space of PUBQ */ + u16 extra_queue_number; /* Free space of EXBQ */ + u8 ac_oqt_number; + u8 non_ac_oqt_number; + u8 ac_empty; +} HALMAC_SDIO_FREE_SPACE, *PHALMAC_SDIO_FREE_SPACE; + +typedef enum _HAL_FIFO_SEL { + HAL_FIFO_SEL_TX, + HAL_FIFO_SEL_RX, + HAL_FIFO_SEL_RSVD_PAGE, + HAL_FIFO_SEL_REPORT, + HAL_FIFO_SEL_LLT, +} HAL_FIFO_SEL; + +typedef enum _HALMAC_DRV_INFO { + HALMAC_DRV_INFO_NONE, /* No information is appended in rx_pkt */ + HALMAC_DRV_INFO_PHY_STATUS, /* PHY status is appended after rx_desc */ + HALMAC_DRV_INFO_PHY_SNIFFER, /* PHY status and sniffer info are appended after rx_desc */ + HALMAC_DRV_INFO_PHY_PLCP, /* PHY status and plcp header are appended after rx_desc */ + HALMAC_DRV_INFO_UNDEFINE, +} HALMAC_DRV_INFO; + +typedef struct _HALMAC_BT_COEX_CMD { + u8 element_id; + u8 op_code; + u8 op_code_ver; + u8 req_num; + u8 data0; + u8 data1; + u8 data2; + u8 data3; + u8 data4; +} HALMAC_BT_COEX_CMD, *PHALMAC_BT_COEX_CMD; + +typedef enum _HALMAC_PRI_CH_IDX { + HALMAC_CH_IDX_UNDEFINE = 0, + HALMAC_CH_IDX_1 = 1, + HALMAC_CH_IDX_2 = 2, + HALMAC_CH_IDX_3 = 3, + HALMAC_CH_IDX_4 = 4, + HALMAC_CH_IDX_MAX = 5, +} HALMAC_PRI_CH_IDX; + +typedef struct _HALMAC_CH_INFO { + HALMAC_CS_ACTION_ID action_id; + HALMAC_BW bw; + HALMAC_PRI_CH_IDX pri_ch_idx; + u8 channel; + u8 timeout; + u8 extra_info; +} HALMAC_CH_INFO, *PHALMAC_CH_INFO; + +typedef struct _HALMAC_CH_EXTRA_INFO { + u8 extra_info; + HALMAC_CS_EXTRA_ACTION_ID extra_action_id; + u8 extra_info_size; + u8 *extra_info_data; +} HALMAC_CH_EXTRA_INFO, *PHALMAC_CH_EXTRA_INFO; + +typedef enum _HALMAC_CS_PERIODIC_OPTION { + HALMAC_CS_PERIODIC_NONE, + HALMAC_CS_PERIODIC_NORMAL, + HALMAC_CS_PERIODIC_2_PHASE, + HALMAC_CS_PERIODIC_SEAMLESS, +} HALMAC_CS_PERIODIC_OPTION; + +typedef struct _HALMAC_CH_SWITCH_OPTION { + HALMAC_BW dest_bw; + HALMAC_CS_PERIODIC_OPTION periodic_option; + HALMAC_PRI_CH_IDX dest_pri_ch_idx; + /* u32 tsf_high; */ + u32 tsf_low; + u8 switch_en; + u8 dest_ch_en; + u8 absolute_time_en; + u8 dest_ch; + u8 normal_period; + u8 normal_cycle; + u8 phase_2_period; +} HALMAC_CH_SWITCH_OPTION, *PHALMAC_CH_SWITCH_OPTION; + +typedef struct _HALMAC_FW_BUILD_TIME { + u16 year; + u8 month; + u8 date; + u8 hour; + u8 min; +} HALMAC_FW_BUILD_TIME, *PHALMAC_FW_BUILD_TIME; + +typedef struct _HALMAC_FW_VERSION { + u16 version; + u8 sub_version; + u8 sub_index; + u16 h2c_version; + HALMAC_FW_BUILD_TIME build_time; +} HALMAC_FW_VERSION, *PHALMAC_FW_VERSION; + +typedef enum _HALMAC_RF_TYPE { + HALMAC_RF_1T2R = 0, + HALMAC_RF_2T4R = 1, + HALMAC_RF_2T2R = 2, + HALMAC_RF_2T3R = 3, + HALMAC_RF_1T1R = 4, + HALMAC_RF_2T2R_GREEN = 5, + HALMAC_RF_3T3R = 6, + HALMAC_RF_3T4R = 7, + HALMAC_RF_4T4R = 8, + HALMAC_RF_MAX_TYPE = 0xF, +} HALMAC_RF_TYPE; + +typedef struct _HALMAC_GENERAL_INFO { + u8 rfe_type; + HALMAC_RF_TYPE rf_type; +} HALMAC_GENERAL_INFO, *PHALMAC_GENERAL_INFO; + +typedef struct _HALMAC_PWR_TRACKING_PARA { + u8 enable; + u8 tx_pwr_index; + u8 pwr_tracking_offset_value; + u8 tssi_value; +} HALMAC_PWR_TRACKING_PARA, *PHALMAC_PWR_TRACKING_PARA; + +typedef struct _HALMAC_PWR_TRACKING_OPTION { + u8 type; + u8 bbswing_index; + HALMAC_PWR_TRACKING_PARA pwr_tracking_para[4]; /* pathA, pathB, pathC, pathD */ +} HALMAC_PWR_TRACKING_OPTION, *PHALMAC_PWR_TRACKING_OPTION; + +typedef struct _HALMAC_NLO_CFG { + u8 num_of_ssid; + u8 num_of_hidden_ap; + u8 rsvd[2]; + u32 pattern_check; + u32 rsvd1; + u32 rsvd2; + u8 ssid_len[HALMAC_SUPPORT_NLO_NUM]; + u8 ChiperType[HALMAC_SUPPORT_NLO_NUM]; + u8 rsvd3[HALMAC_SUPPORT_NLO_NUM]; + u8 loc_probeReq[HALMAC_SUPPORT_PROBE_REQ_NUM]; + u8 rsvd4[56]; + u8 ssid[HALMAC_SUPPORT_NLO_NUM][HALMAC_MAX_SSID_LEN]; +} HALMAC_NLO_CFG, *PHALMAC_NLO_CFG; + +typedef enum _HALMAC_DATA_RATE { + HALMAC_CCK1, + HALMAC_CCK2, + HALMAC_CCK5_5, + HALMAC_CCK11, + HALMAC_OFDM6, + HALMAC_OFDM9, + HALMAC_OFDM12, + HALMAC_OFDM18, + HALMAC_OFDM24, + HALMAC_OFDM36, + HALMAC_OFDM48, + HALMAC_OFDM54, + HALMAC_MCS0, + HALMAC_MCS1, + HALMAC_MCS2, + HALMAC_MCS3, + HALMAC_MCS4, + HALMAC_MCS5, + HALMAC_MCS6, + HALMAC_MCS7, + HALMAC_MCS8, + HALMAC_MCS9, + HALMAC_MCS10, + HALMAC_MCS11, + HALMAC_MCS12, + HALMAC_MCS13, + HALMAC_MCS14, + HALMAC_MCS15, + HALMAC_MCS16, + HALMAC_MCS17, + HALMAC_MCS18, + HALMAC_MCS19, + HALMAC_MCS20, + HALMAC_MCS21, + HALMAC_MCS22, + HALMAC_MCS23, + HALMAC_MCS24, + HALMAC_MCS25, + HALMAC_MCS26, + HALMAC_MCS27, + HALMAC_MCS28, + HALMAC_MCS29, + HALMAC_MCS30, + HALMAC_MCS31, + HALMAC_VHT_NSS1_MCS0, + HALMAC_VHT_NSS1_MCS1, + HALMAC_VHT_NSS1_MCS2, + HALMAC_VHT_NSS1_MCS3, + HALMAC_VHT_NSS1_MCS4, + HALMAC_VHT_NSS1_MCS5, + HALMAC_VHT_NSS1_MCS6, + HALMAC_VHT_NSS1_MCS7, + HALMAC_VHT_NSS1_MCS8, + HALMAC_VHT_NSS1_MCS9, + HALMAC_VHT_NSS2_MCS0, + HALMAC_VHT_NSS2_MCS1, + HALMAC_VHT_NSS2_MCS2, + HALMAC_VHT_NSS2_MCS3, + HALMAC_VHT_NSS2_MCS4, + HALMAC_VHT_NSS2_MCS5, + HALMAC_VHT_NSS2_MCS6, + HALMAC_VHT_NSS2_MCS7, + HALMAC_VHT_NSS2_MCS8, + HALMAC_VHT_NSS2_MCS9, + HALMAC_VHT_NSS3_MCS0, + HALMAC_VHT_NSS3_MCS1, + HALMAC_VHT_NSS3_MCS2, + HALMAC_VHT_NSS3_MCS3, + HALMAC_VHT_NSS3_MCS4, + HALMAC_VHT_NSS3_MCS5, + HALMAC_VHT_NSS3_MCS6, + HALMAC_VHT_NSS3_MCS7, + HALMAC_VHT_NSS3_MCS8, + HALMAC_VHT_NSS3_MCS9, + HALMAC_VHT_NSS4_MCS0, + HALMAC_VHT_NSS4_MCS1, + HALMAC_VHT_NSS4_MCS2, + HALMAC_VHT_NSS4_MCS3, + HALMAC_VHT_NSS4_MCS4, + HALMAC_VHT_NSS4_MCS5, + HALMAC_VHT_NSS4_MCS6, + HALMAC_VHT_NSS4_MCS7, + HALMAC_VHT_NSS4_MCS8, + HALMAC_VHT_NSS4_MCS9 +} HALMAC_DATA_RATE; + +typedef enum _HALMAC_RF_PATH { + HALMAC_RF_PATH_A, + HALMAC_RF_PATH_B, + HALMAC_RF_PATH_C, + HALMAC_RF_PATH_D +} HALMAC_RF_PATH; + +typedef enum _HALMAC_SND_PKT_SEL { + HALMAC_UNI_NDPA, + HALMAC_BMC_NDPA, + HALMAC_NON_FINAL_BFRPRPOLL, + HALMAC_FINAL_BFRPTPOLL, +} HALMAC_SND_PKT_SEL; + +typedef enum _HAL_SECURITY_TYPE { + HAL_SECURITY_TYPE_NONE = 0, + HAL_SECURITY_TYPE_WEP40 = 1, + HAL_SECURITY_TYPE_WEP104 = 2, + HAL_SECURITY_TYPE_TKIP = 3, + HAL_SECURITY_TYPE_AES128 = 4, + HAL_SECURITY_TYPE_WAPI = 5, + HAL_SECURITY_TYPE_AES256 = 6, + HAL_SECURITY_TYPE_GCMP128 = 7, + HAL_SECURITY_TYPE_GCMP256 = 8, + HAL_SECURITY_TYPE_GCMSMS4 = 9, + HAL_SECURITY_TYPE_BIP = 10, + HAL_SECURITY_TYPE_UNDEFINE = 0x7F, +} HAL_SECURITY_TYPE; + +typedef enum _HAL_INTF_PHY { + HAL_INTF_PHY_USB2 = 0, + HAL_INTF_PHY_USB3 = 1, + HAL_INTF_PHY_PCIE_GEN1 = 2, + HAL_INTF_PHY_PCIE_GEN2 = 3, + HAL_INTF_PHY_UNDEFINE = 0x7F, +} HAL_INTF_PHY; + +typedef enum _HALMAC_DBG_MSG_INFO { + HALMAC_DBG_ALWAYS, + HALMAC_DBG_ERR, + HALMAC_DBG_WARN, + HALMAC_DBG_TRACE, +} HALMAC_DBG_MSG_INFO; + +typedef enum _HALMAC_DBG_MSG_TYPE { + HALMAC_MSG_INIT, + HALMAC_MSG_EFUSE, + HALMAC_MSG_FW, + HALMAC_MSG_H2C, + HALMAC_MSG_PWR, + HALMAC_MSG_SND, + HALMAC_MSG_COMMON, + HALMAC_MSG_DBI, + HALMAC_MSG_MDIO, + HALMAC_MSG_USB +} HALMAC_DBG_MSG_TYPE; + +typedef enum _HALMAC_CMD_PROCESS_STATUS { + HALMAC_CMD_PROCESS_IDLE = 0x01, /* Init status */ + HALMAC_CMD_PROCESS_SENDING = 0x02, /* Wait ack */ + HALMAC_CMD_PROCESS_RCVD = 0x03, /* Rcvd ack */ + HALMAC_CMD_PROCESS_DONE = 0x04, /* Event done */ + HALMAC_CMD_PROCESS_ERROR = 0x05, /* Return code error */ + HALMAC_CMD_PROCESS_UNDEFINE = 0x7F, +} HALMAC_CMD_PROCESS_STATUS; + +typedef enum _HALMAC_FEATURE_ID { + HALMAC_FEATURE_CFG_PARA, /* Support */ + HALMAC_FEATURE_DUMP_PHYSICAL_EFUSE, /* Support */ + HALMAC_FEATURE_DUMP_LOGICAL_EFUSE, /* Support */ + HALMAC_FEATURE_UPDATE_PACKET, /* Support */ + HALMAC_FEATURE_UPDATE_DATAPACK, + HALMAC_FEATURE_RUN_DATAPACK, + HALMAC_FEATURE_CHANNEL_SWITCH, /* Support */ + HALMAC_FEATURE_IQK, /* Support */ + HALMAC_FEATURE_POWER_TRACKING, /* Support */ + HALMAC_FEATURE_PSD, /* Support */ + HALMAC_FEATURE_ALL, /* Support, only for reset */ +} HALMAC_FEATURE_ID; + +typedef enum _HALMAC_DRV_RSVD_PG_NUM { + HALMAC_RSVD_PG_NUM16, /* 2K */ + HALMAC_RSVD_PG_NUM24, /* 3K */ + HALMAC_RSVD_PG_NUM32, /* 4K */ +} HALMAC_DRV_RSVD_PG_NUM; + +typedef enum _HALMAC_PCIE_CFG { + HALMAC_PCIE_GEN1, + HALMAC_PCIE_GEN2, + HALMAC_PCIE_CFG_UNDEFINE, +} HALMAC_PCIE_CFG; + +typedef enum _HALMAC_PORTID { + HALMAC_PORTID0 = 0, + HALMAC_PORTID1 = 1, + HALMAC_PORTID2 = 2, + HALMAC_PORTID3 = 3, + HALMAC_PORTID4 = 4, + HALMAC_PORTIDMAX +} HALMAC_PORTID; + +typedef struct _HALMAC_P2PPS { + /*DW0*/ + u8 offload_en:1; + u8 role:1; + u8 ctwindow_en:1; + u8 noa_en:1; + u8 noa_sel:1; + u8 all_sta_sleep:1; + u8 discovery:1; + u8 rsvd2:1; + u8 p2p_port_id; + u8 p2p_group; + u8 p2p_macid; + + /*DW1*/ + u8 ctwindow_length; + u8 rsvd3; + u8 rsvd4; + u8 rsvd5; + + /*DW2*/ + u32 noa_duration_para; + + /*DW3*/ + u32 noa_interval_para; + + /*DW4*/ + u32 noa_start_time_para; + + /*DW5*/ + u32 noa_count_para; +} HALMAC_P2PPS, *PHALMAC_P2PPS; + +/* Platform API setting */ +typedef struct _HALMAC_PLATFORM_API { + /* R/W register */ + u8 (*SDIO_CMD52_READ)(VOID *pDriver_adapter, u32 offset); + u8 (*SDIO_CMD53_READ_8)(VOID *pDriver_adapter, u32 offset); + u16 (*SDIO_CMD53_READ_16)(VOID *pDriver_adapter, u32 offset); + u32 (*SDIO_CMD53_READ_32)(VOID *pDriver_adapter, u32 offset); + u8 (*SDIO_CMD53_READ_N)(VOID *pDriver_adapter, u32 offset, u32 size, u8 *data); + VOID (*SDIO_CMD52_WRITE)(VOID *pDriver_adapter, u32 offset, u8 value); + VOID (*SDIO_CMD53_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value); + VOID (*SDIO_CMD53_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value); + VOID (*SDIO_CMD53_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value); + u8 (*REG_READ_8)(VOID *pDriver_adapter, u32 offset); + u16 (*REG_READ_16)(VOID *pDriver_adapter, u32 offset); + u32 (*REG_READ_32)(VOID *pDriver_adapter, u32 offset); + VOID (*REG_WRITE_8)(VOID *pDriver_adapter, u32 offset, u8 value); + VOID (*REG_WRITE_16)(VOID *pDriver_adapter, u32 offset, u16 value); + VOID (*REG_WRITE_32)(VOID *pDriver_adapter, u32 offset, u32 value); + + /* send pBuf to reserved page, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = bcn */ + u8 (*SEND_RSVD_PAGE)(VOID *pDriver_adapter, u8 *pBuf, u32 size); + /* send pBuf to h2c queue, the tx_desc is not included in pBuf, driver need to fill tx_desc with qsel = h2c */ + u8 (*SEND_H2C_PKT)(VOID *pDriver_adapter, u8 *pBuf, u32 size); + + u8 (*RTL_FREE)(VOID *pDriver_adapter, VOID *pBuf, u32 size); + VOID* (*RTL_MALLOC)(VOID *pDriver_adapter, u32 size); + u8 (*RTL_MEMCPY)(VOID *pDriver_adapter, VOID *dest, VOID *src, u32 size); + u8 (*RTL_MEMSET)(VOID *pDriver_adapter, VOID *pAddress, u8 value, u32 size); + VOID (*RTL_DELAY_US)(VOID *pDriver_adapter, u32 us); + + u8 (*MUTEX_INIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); + u8 (*MUTEX_DEINIT)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); + u8 (*MUTEX_LOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); + u8 (*MUTEX_UNLOCK)(VOID *pDriver_adapter, HALMAC_MUTEX *pMutex); + + u8 (*MSG_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *fmt, ...); + u8 (*BUFF_PRINT)(VOID *pDriver_adapter, u32 msg_type, u8 msg_level, s8 *buf, u32 size); + + u8 (*EVENT_INDICATION)(VOID *pDriver_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS process_status, u8 *buf, u32 size); +} HALMAC_PLATFORM_API, *PHALMAC_PLATFORM_API; + +/*1->Little endian 0->Big endian*/ +#if HALMAC_SYSTEM_ENDIAN + +#else + +#endif + +/* User can not use members in Address_L_H, use Address[6] is mandatory */ +typedef union _HALMAC_WLAN_ADDR { + u8 Address[6]; /* WLAN address (MACID, BSSID, Brodcast ID). Address[0] is lowest, Address[5] is highest*/ + struct { + union { + u32 Address_Low; + u8 Address_Low_B[4]; + }; + union { + u16 Address_High; + u8 Address_High_B[2]; + }; + } Address_L_H; +} HALMAC_WLAN_ADDR, *PHALMAC_WLAN_ADDR; + +typedef enum _HALMAC_SND_ROLE { + HAL_BFER = 0, + HAL_BFEE = 1, +} HALMAC_SND_ROLE; + +typedef enum _HALMAC_CSI_SEG_LEN { + HAL_CSI_SEG_4K = 0, + HAL_CSI_SEG_8K = 1, + HAL_CSI_SEG_11K = 2, +} HALMAC_CSI_SEG_LEN; + +typedef struct _HALMAC_CFG_MUMIMO_PARA { + HALMAC_SND_ROLE role; + u8 sounding_sts[6]; + u16 grouping_bitmap; + u8 mu_tx_en; + u32 given_gid_tab[2]; + u32 given_user_pos[4]; +} HALMAC_CFG_MUMIMO_PARA, *PHALMAC_CFG_MUMIMO_PARA; + +typedef struct _HALMAC_SU_BFER_INIT_PARA { + u8 userid; + u16 paid; + u16 csi_para; + HALMAC_WLAN_ADDR bfer_address; +} HALMAC_SU_BFER_INIT_PARA, *PHALMAC_SU_BFER_INIT_PARA; + +typedef struct _HALMAC_MU_BFEE_INIT_PARA { + u8 userid; + u16 paid; + u32 user_position_l; + u32 user_position_h; +} HALMAC_MU_BFEE_INIT_PARA, *PHALMAC_MU_BFEE_INIT_PARA; + +typedef struct _HALMAC_MU_BFER_INIT_PARA { + u16 paid; + u16 csi_para; + u16 my_aid; + HALMAC_CSI_SEG_LEN csi_length_sel; + HALMAC_WLAN_ADDR bfer_address; +} HALMAC_MU_BFER_INIT_PARA, *PHALMAC_MU_BFER_INIT_PARA; + +typedef struct _HALMAC_SND_INFO { + u16 paid; + u8 userid; + HALMAC_DATA_RATE ndpa_rate; + u16 csi_para; + u16 my_aid; + HALMAC_DATA_RATE csi_rate; + HALMAC_CSI_SEG_LEN csi_length_sel; + HALMAC_SND_ROLE role; + HALMAC_WLAN_ADDR bfer_address; + HALMAC_BW bw; + u8 txbf_en; + PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init; + PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init; + PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init; +} HALMAC_SND_INFO, *PHALMAC_SND_INFO; + +typedef struct _HALMAC_CS_INFO { + u8 *ch_info_buf; + u8 *ch_info_buf_w; + u8 extra_info_en; + u32 buf_size; /* buffer size */ + u32 avai_buf_size; /* buffer size */ + u32 total_size; + u32 accu_timeout; + u32 ch_num; +} HALMAC_CS_INFO, *PHALMAC_CS_INFO; + +typedef struct _HALMAC_RESTORE_INFO { + u32 mac_register; + u32 value; + u8 length; +} HALMAC_RESTORE_INFO, *PHALMAC_RESTORE_INFO; + +typedef struct _HALMAC_EVENT_TRIGGER { + u32 physical_efuse_map : 1; + u32 logical_efuse_map : 1; + u32 rsvd1 : 28; +} HALMAC_EVENT_TRIGGER, *PHALMAC_EVENT_TRIGGER; + +typedef struct _HALMAC_H2C_HEADER_INFO { + u16 sub_cmd_id; + u16 content_size; + u8 ack; +} HALMAC_H2C_HEADER_INFO, *PHALMAC_H2C_HEADER_INFO; + +typedef enum _HALMAC_DLFW_STATE { + HALMAC_DLFW_NONE = 0, + HALMAC_DLFW_DONE = 1, + HALMAC_GEN_INFO_SENT = 2, + HALMAC_DLFW_UNDEFINED = 0x7F, +} HALMAC_DLFW_STATE; + +typedef enum _HALMAC_EFUSE_CMD_CONSTRUCT_STATE { + HALMAC_EFUSE_CMD_CONSTRUCT_IDLE = 0, + HALMAC_EFUSE_CMD_CONSTRUCT_BUSY = 1, + HALMAC_EFUSE_CMD_CONSTRUCT_H2C_SENT = 2, + HALMAC_EFUSE_CMD_CONSTRUCT_STATE_NUM = 3, + HALMAC_EFUSE_CMD_CONSTRUCT_UNDEFINED = 0x7F, +} HALMAC_EFUSE_CMD_CONSTRUCT_STATE; + +typedef enum _HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE { + HALMAC_CFG_PARA_CMD_CONSTRUCT_IDLE = 0, + HALMAC_CFG_PARA_CMD_CONSTRUCT_CONSTRUCTING = 1, + HALMAC_CFG_PARA_CMD_CONSTRUCT_H2C_SENT = 2, + HALMAC_CFG_PARA_CMD_CONSTRUCT_NUM = 3, + HALMAC_CFG_PARA_CMD_CONSTRUCT_UNDEFINED = 0x7F, +} HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE; + +typedef enum _HALMAC_SCAN_CMD_CONSTRUCT_STATE { + HALMAC_SCAN_CMD_CONSTRUCT_IDLE = 0, + HALMAC_SCAN_CMD_CONSTRUCT_BUFFER_CLEARED = 1, + HALMAC_SCAN_CMD_CONSTRUCT_CONSTRUCTING = 2, + HALMAC_SCAN_CMD_CONSTRUCT_H2C_SENT = 3, + HALMAC_SCAN_CMD_CONSTRUCT_STATE_NUM = 4, + HALMAC_SCAN_CMD_CONSTRUCT_UNDEFINED = 0x7F, +} HALMAC_SCAN_CMD_CONSTRUCT_STATE; + +typedef enum _HALMAC_API_STATE { + HALMAC_API_STATE_INIT = 0, + HALMAC_API_STATE_HALT = 1, + HALMAC_API_STATE_UNDEFINED = 0x7F, +} HALMAC_API_STATE; + +typedef struct _HALMAC_EFUSE_STATE_SET { + HALMAC_EFUSE_CMD_CONSTRUCT_STATE efuse_cmd_construct_state; + HALMAC_CMD_PROCESS_STATUS process_status; + u8 fw_return_code; + u16 seq_num; +} HALMAC_EFUSE_STATE_SET, *PHALMAC_EFUSE_STATE_SET; + +typedef struct _HALMAC_CFG_PARA_STATE_SET { + HALMAC_CFG_PARA_CMD_CONSTRUCT_STATE cfg_para_cmd_construct_state; + HALMAC_CMD_PROCESS_STATUS process_status; + u8 fw_return_code; + u16 seq_num; +} HALMAC_CFG_PARA_STATE_SET, *PHALMAC_CFG_PARA_STATE_SET; + +typedef struct _HALMAC_SCAN_STATE_SET { + HALMAC_SCAN_CMD_CONSTRUCT_STATE scan_cmd_construct_state; + HALMAC_CMD_PROCESS_STATUS process_status; + u8 fw_return_code; + u16 seq_num; +} HALMAC_SCAN_STATE_SET, *PHALMAC_SCAN_STATE_SET; + +typedef struct _HALMAC_UPDATE_PACKET_STATE_SET { + HALMAC_CMD_PROCESS_STATUS process_status; + u8 fw_return_code; + u16 seq_num; +} HALMAC_UPDATE_PACKET_STATE_SET, *PHALMAC_UPDATE_PACKET_STATE_SET; + +typedef struct _HALMAC_IQK_STATE_SET { + HALMAC_CMD_PROCESS_STATUS process_status; + u8 fw_return_code; + u16 seq_num; +} HALMAC_IQK_STATE_SET, *PHALMAC_IQK_STATE_SET; + +typedef struct _HALMAC_POWER_TRACKING_STATE_SET { + HALMAC_CMD_PROCESS_STATUS process_status; + u8 fw_return_code; + u16 seq_num; +} HALMAC_POWER_TRACKING_STATE_SET, *PHALMAC_POWER_TRACKING_STATE_SET; + +typedef struct _HALMAC_PSD_STATE_SET { + HALMAC_CMD_PROCESS_STATUS process_status; + u16 data_size; + u16 segment_size; + u8 *pData; + u8 fw_return_code; + u16 seq_num; +} HALMAC_PSD_STATE_SET, *PHALMAC_PSD_STATE_SET; + +typedef struct _HALMAC_STATE { + HALMAC_EFUSE_STATE_SET efuse_state_set; /* State machine + cmd process status */ + HALMAC_CFG_PARA_STATE_SET cfg_para_state_set; /* State machine + cmd process status */ + HALMAC_SCAN_STATE_SET scan_state_set; /* State machine + cmd process status */ + HALMAC_UPDATE_PACKET_STATE_SET update_packet_set; /* cmd process status */ + HALMAC_IQK_STATE_SET iqk_set; /* cmd process status */ + HALMAC_POWER_TRACKING_STATE_SET power_tracking_set; /* cmd process status */ + HALMAC_PSD_STATE_SET psd_set; /* cmd process status */ + HALMAC_API_STATE api_state; /* Halmac api state */ + HALMAC_MAC_POWER mac_power; /* 0 : power off, 1 : power on*/ + HALMAC_PS_STATE ps_state; /* power saving state */ + HALMAC_DLFW_STATE dlfw_state; /* download FW state */ +} HALMAC_STATE, *PHALMAC_STATE; + +typedef struct _HALMAC_VER { + u8 major_ver; + u8 prototype_ver; + u8 minor_ver; +} HALMAC_VER, *PHALMAC_VER; + +typedef enum _HALMAC_API_ID { + /*stuff, need to be the 1st*/ + HALMAC_API_STUFF = 0x0, + /*stuff, need to be the 1st*/ + HALMAC_API_MAC_POWER_SWITCH = 0x1, + HALMAC_API_DOWNLOAD_FIRMWARE = 0x2, + HALMAC_API_CFG_MAC_ADDR = 0x3, + HALMAC_API_CFG_BSSID = 0x4, + HALMAC_API_CFG_MULTICAST_ADDR = 0x5, + HALMAC_API_PRE_INIT_SYSTEM_CFG = 0x6, + HALMAC_API_INIT_SYSTEM_CFG = 0x7, + HALMAC_API_INIT_TRX_CFG = 0x8, + HALMAC_API_CFG_RX_AGGREGATION = 0x9, + HALMAC_API_INIT_PROTOCOL_CFG = 0xA, + HALMAC_API_INIT_EDCA_CFG = 0xB, + HALMAC_API_CFG_OPERATION_MODE = 0xC, + HALMAC_API_CFG_CH_BW = 0xD, + HALMAC_API_CFG_BW = 0xE, + HALMAC_API_INIT_WMAC_CFG = 0xF, + HALMAC_API_INIT_MAC_CFG = 0x10, + HALMAC_API_INIT_SDIO_CFG = 0x11, + HALMAC_API_INIT_USB_CFG = 0x12, + HALMAC_API_INIT_PCIE_CFG = 0x13, + HALMAC_API_INIT_INTERFACE_CFG = 0x14, + HALMAC_API_DEINIT_SDIO_CFG = 0x15, + HALMAC_API_DEINIT_USB_CFG = 0x16, + HALMAC_API_DEINIT_PCIE_CFG = 0x17, + HALMAC_API_DEINIT_INTERFACE_CFG = 0x18, + HALMAC_API_GET_EFUSE_SIZE = 0x19, + HALMAC_API_DUMP_EFUSE_MAP = 0x1A, + HALMAC_API_WRITE_EFUSE = 0x1B, + HALMAC_API_READ_EFUSE = 0x1C, + HALMAC_API_GET_LOGICAL_EFUSE_SIZE = 0x1D, + HALMAC_API_DUMP_LOGICAL_EFUSE_MAP = 0x1E, + HALMAC_API_WRITE_LOGICAL_EFUSE = 0x1F, + HALMAC_API_READ_LOGICAL_EFUSE = 0x20, + HALMAC_API_PG_EFUSE_BY_MAP = 0x21, + HALMAC_API_GET_C2H_INFO = 0x22, + HALMAC_API_CFG_FWLPS_OPTION = 0x23, + HALMAC_API_CFG_FWIPS_OPTION = 0x24, + HALMAC_API_ENTER_WOWLAN = 0x25, + HALMAC_API_LEAVE_WOWLAN = 0x26, + HALMAC_API_ENTER_PS = 0x27, + HALMAC_API_LEAVE_PS = 0x28, + HALMAC_API_H2C_LB = 0x29, + HALMAC_API_DEBUG = 0x2A, + HALMAC_API_CFG_PARAMETER = 0x2B, + HALMAC_API_UPDATE_PACKET = 0x2C, + HALMAC_API_BCN_IE_FILTER = 0x2D, + HALMAC_API_REG_READ_8 = 0x2E, + HALMAC_API_REG_WRITE_8 = 0x2F, + HALMAC_API_REG_READ_16 = 0x30, + HALMAC_API_REG_WRITE_16 = 0x31, + HALMAC_API_REG_READ_32 = 0x32, + HALMAC_API_REG_WRITE_32 = 0x33, + HALMAC_API_TX_ALLOWED_SDIO = 0x34, + HALMAC_API_SET_BULKOUT_NUM = 0x35, + HALMAC_API_GET_SDIO_TX_ADDR = 0x36, + HALMAC_API_GET_USB_BULKOUT_ID = 0x37, + HALMAC_API_TIMER_2S = 0x38, + HALMAC_API_FILL_TXDESC_CHECKSUM = 0x39, + HALMAC_API_SEND_ORIGINAL_H2C = 0x3A, + HALMAC_API_UPDATE_DATAPACK = 0x3B, + HALMAC_API_RUN_DATAPACK = 0x3C, + HALMAC_API_CFG_DRV_INFO = 0x3D, + HALMAC_API_SEND_BT_COEX = 0x3E, + HALMAC_API_VERIFY_PLATFORM_API = 0x3F, + HALMAC_API_GET_FIFO_SIZE = 0x40, + HALMAC_API_DUMP_FIFO = 0x41, + HALMAC_API_CFG_TXBF = 0x42, + HALMAC_API_CFG_MUMIMO = 0x43, + HALMAC_API_CFG_SOUNDING = 0x44, + HALMAC_API_DEL_SOUNDING = 0x45, + HALMAC_API_SU_BFER_ENTRY_INIT = 0x46, + HALMAC_API_SU_BFEE_ENTRY_INIT = 0x47, + HALMAC_API_MU_BFER_ENTRY_INIT = 0x48, + HALMAC_API_MU_BFEE_ENTRY_INIT = 0x49, + HALMAC_API_SU_BFER_ENTRY_DEL = 0x4A, + HALMAC_API_SU_BFEE_ENTRY_DEL = 0x4B, + HALMAC_API_MU_BFER_ENTRY_DEL = 0x4C, + HALMAC_API_MU_BFEE_ENTRY_DEL = 0x4D, + HALMAC_API_ADD_CH_INFO = 0x4E, + HALMAC_API_ADD_EXTRA_CH_INFO = 0x4F, + HALMAC_API_CTRL_CH_SWITCH = 0x50, + HALMAC_API_CLEAR_CH_INFO = 0x51, + HALMAC_API_SEND_GENERAL_INFO = 0x52, + HALMAC_API_START_IQK = 0x53, + HALMAC_API_CTRL_PWR_TRACKING = 0x54, + HALMAC_API_PSD = 0x55, + HALMAC_API_CFG_TX_AGG_ALIGN = 0x56, + HALMAC_API_QUERY_STATE = 0x57, + HALMAC_API_RESET_FEATURE = 0x58, + HALMAC_API_CHECK_FW_STATUS = 0x59, + HALMAC_API_DUMP_FW_DMEM = 0x5A, + HALMAC_API_CFG_MAX_DL_SIZE = 0x5B, + HALMAC_API_INIT_OBJ = 0x5C, + HALMAC_API_DEINIT_OBJ = 0x5D, + HALMAC_API_CFG_LA_MODE = 0x5E, + HALMAC_API_GET_HW_VALUE = 0x5F, + HALMAC_API_SET_HW_VALUE = 0x60, + HALMAC_API_CFG_DRV_RSVD_PG_NUM = 0x61, + HALMAC_API_SWITCH_EFUSE_BANK = 0x62, + HALMAC_API_WRITE_EFUSE_BT = 0x63, + HALMAC_API_DUMP_EFUSE_MAP_BT = 0x64, + HALMAC_API_DL_DRV_RSVD_PG = 0x65, + HALMAC_API_PCIE_SWITCH = 0x66, + HALMAC_API_PHY_CFG = 0x67, + HALMAC_API_CFG_RX_FIFO_EXPANDING_MODE = 0x68, + HALMAC_API_CFG_CSI_RATE = 0x69, + HALMAC_API_P2PPS = 0x6A, + HALMAC_API_CFG_TX_ADDR = 0x6B, + HALMAC_API_CFG_NET_TYPE = 0x6C, + HALMAC_API_CFG_TSF_RESET = 0x6D, + HALMAC_API_CFG_BCN_SPACE = 0x6E, + HALMAC_API_CFG_BCN_CTRL = 0x6F, + HALMAC_API_CFG_SIDEBAND_INT = 0x70, + HALMAC_API_REGISTER_API = 0x71, + HALMAC_API_FREE_DOWNLOAD_FIRMWARE = 0x72, + HALMAC_API_GET_FW_VERSION = 0x73, + HALMAC_API_GET_EFUSE_AVAL_SIZE = 0x74, + HALMAC_API_CHK_TXDESC = 0x75, + HALMAC_API_SDIO_CMD53_4BYTE = 0x76, + HALMAC_API_CFG_TRANS_ADDR = 0x77, + HALMAC_API_INTF_INTEGRA_TUNING = 0x78, + HALMAC_API_TXFIFO_IS_EMPTY = 0x79, + HALMAC_API_SDIO_HW_INFO = 0x80, + HALMAC_API_MAX +} HALMAC_API_ID; + +typedef struct _HALMAC_API_RECORD { + HALMAC_API_ID api_array[API_ARRAY_SIZE]; + u8 array_wptr; +} HALMAC_API_RECORD, *PHALMAC_API_RECORD; + +typedef enum _HALMAC_LA_MODE { + HALMAC_LA_MODE_DISABLE = 0, + HALMAC_LA_MODE_PARTIAL = 1, + HALMAC_LA_MODE_FULL = 2, + HALMAC_LA_MODE_UNDEFINE = 0x7F, +} HALMAC_LA_MODE; + +typedef enum _HALMAC_RX_FIFO_EXPANDING_MODE { + HALMAC_RX_FIFO_EXPANDING_MODE_DISABLE = 0, + HALMAC_RX_FIFO_EXPANDING_MODE_1_BLOCK = 1, + HALMAC_RX_FIFO_EXPANDING_MODE_2_BLOCK = 2, + HALMAC_RX_FIFO_EXPANDING_MODE_3_BLOCK = 3, + HALMAC_RX_FIFO_EXPANDING_MODE_UNDEFINE = 0x7F, +} HALMAC_RX_FIFO_EXPANDING_MODE; + +typedef enum _HALMAC_SDIO_CMD53_4BYTE_MODE { + HALMAC_SDIO_CMD53_4BYTE_MODE_DISABLE = 0, + HALMAC_SDIO_CMD53_4BYTE_MODE_RW = 1, + HALMAC_SDIO_CMD53_4BYTE_MODE_R = 2, + HALMAC_SDIO_CMD53_4BYTE_MODE_W = 3, + HALMAC_SDIO_CMD53_4BYTE_MODE_UNDEFINE = 0x7F, +} HALMAC_SDIO_CMD53_4BYTE_MODE; + +typedef enum _HALMAC_USB_MODE { + HALMAC_USB_MODE_U2 = 1, + HALMAC_USB_MODE_U3 = 2, +} HALMAC_USB_MODE; + +typedef enum _HALMAC_HW_ID { + /* Get HW value */ + HALMAC_HW_RQPN_MAPPING = 0x00, + HALMAC_HW_EFUSE_SIZE = 0x01, + HALMAC_HW_EEPROM_SIZE = 0x02, + HALMAC_HW_BT_BANK_EFUSE_SIZE = 0x03, + HALMAC_HW_BT_BANK1_EFUSE_SIZE = 0x04, + HALMAC_HW_BT_BANK2_EFUSE_SIZE = 0x05, + HALMAC_HW_TXFIFO_SIZE = 0x06, + HALMAC_HW_RSVD_PG_BNDY = 0x07, + HALMAC_HW_CAM_ENTRY_NUM = 0x08, + HALMAC_HW_IC_VERSION = 0x09, + HALMAC_HW_PAGE_SIZE = 0x0A, + HALMAC_HW_TX_AGG_ALIGN_SIZE = 0x0B, + HALMAC_HW_RX_AGG_ALIGN_SIZE = 0x0C, + HALMAC_HW_DRV_INFO_SIZE = 0x0D, + HALMAC_HW_TXFF_ALLOCATION = 0x0E, + HALMAC_HW_RSVD_EFUSE_SIZE = 0x0F, + HALMAC_HW_FW_HDR_SIZE = 0x10, + HALMAC_HW_TX_DESC_SIZE = 0x11, + HALMAC_HW_RX_DESC_SIZE = 0x12, + HALMAC_HW_WLAN_EFUSE_AVAILABLE_SIZE = 0x13, + /* Set HW value */ + HALMAC_HW_USB_MODE = 0x60, + HALMAC_HW_SEQ_EN = 0x61, + HALMAC_HW_BANDWIDTH = 0x62, + HALMAC_HW_CHANNEL = 0x63, + HALMAC_HW_PRI_CHANNEL_IDX = 0x64, + HALMAC_HW_EN_BB_RF = 0x65, + HALMAC_HW_SDIO_TX_PAGE_THRESHOLD = 0x66, + HALMAC_HW_AMPDU_CONFIG = 0x67, + + HALMAC_HW_ID_UNDEFINE = 0x7F, +} HALMAC_HW_ID; +typedef enum _HALMAC_EFUSE_BANK { + HALMAC_EFUSE_BANK_WIFI = 0, + HALMAC_EFUSE_BANK_BT = 1, + HALMAC_EFUSE_BANK_BT_1 = 2, + HALMAC_EFUSE_BANK_BT_2 = 3, + HALMAC_EFUSE_BANK_MAX, + HALMAC_EFUSE_BANK_UNDEFINE = 0X7F, +} HALMAC_EFUSE_BANK; + +typedef enum _HALMAC_SDIO_SPEC_VER { + HALMAC_SDIO_SPEC_VER_2_00 = 0, + HALMAC_SDIO_SPEC_VER_3_00 = 1, + HALMAC_SDIO_SPEC_VER_UNDEFINE = 0X7F, +} HALMAC_SDIO_SPEC_VER; + +typedef struct _HALMAC_TXFF_ALLOCATION { + u16 tx_fifo_pg_num; + u16 rsvd_pg_num; + u16 rsvd_drv_pg_num; + u16 ac_q_pg_num; + u16 high_queue_pg_num; + u16 low_queue_pg_num; + u16 normal_queue_pg_num; + u16 extra_queue_pg_num; + u16 pub_queue_pg_num; + u16 rsvd_pg_bndy; + u16 rsvd_drv_pg_bndy; + u16 rsvd_h2c_extra_info_pg_bndy; + u16 rsvd_h2c_queue_pg_bndy; + u16 rsvd_cpu_instr_pg_bndy; + u16 rsvd_fw_txbuff_pg_bndy; + HALMAC_LA_MODE la_mode; + HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode; +} HALMAC_TXFF_ALLOCATION, *PHALMAC_TXFF_ALLOCATION; + +typedef struct _HALMAC_RQPN_MAP { + HALMAC_DMA_MAPPING dma_map_vo; + HALMAC_DMA_MAPPING dma_map_vi; + HALMAC_DMA_MAPPING dma_map_be; + HALMAC_DMA_MAPPING dma_map_bk; + HALMAC_DMA_MAPPING dma_map_mg; + HALMAC_DMA_MAPPING dma_map_hi; +} HALMAC_RQPN_MAP, *PHALMAC_RQPN_MAP; + +typedef struct _HALMAC_SECURITY_SETTING { + u8 tx_encryption; + u8 rx_decryption; + u8 bip_enable; +} HALMAC_SECURITY_SETTING, *PHALMAC_SECURITY_SETTING; + +typedef struct _HALMAC_CAM_ENTRY_INFO { + HAL_SECURITY_TYPE security_type; + u32 key[4]; + u32 key_ext[4]; + u8 mac_address[6]; + u8 unicast; + u8 key_id; + u8 valid; +} HALMAC_CAM_ENTRY_INFO, *PHALMAC_CAM_ENTRY_INFO; + +typedef struct _HALMAC_CAM_ENTRY_FORMAT { + u16 key_id : 2; + u16 type : 3; + u16 mic : 1; + u16 grp : 1; + u16 spp_mode : 1; + u16 rpt_md : 1; + u16 ext_sectype : 1; + u16 mgnt : 1; + u16 rsvd1 : 4; + u16 valid : 1; + u8 mac_address[6]; + u32 key[4]; + u32 rsvd[2]; +} HALMAC_CAM_ENTRY_FORMAT, *PHALMAC_CAM_ENTRY_FORMAT; + +typedef struct _HALMAC_TX_PAGE_THRESHOLD_INFO { + u32 threshold; + HALMAC_DMA_MAPPING dma_queue_sel; +} HALMAC_TX_PAGE_THRESHOLD_INFO, *PHALMAC_TX_PAGE_THRESHOLD_INFO; + +typedef struct _HALMAC_AMPDU_CONFIG { + u8 max_agg_num; +} HALMAC_AMPDU_CONFIG, *PHALMAC_AMPDU_CONFIG; + +typedef struct _HALMAC_PORT_CFG { + u8 port0_sync_tsf; + u8 port1_sync_tsf; +} HALMAC_PORT_CFG, *PHALMAC_PORT_CFG; + +typedef struct _HALMAC_RQPN_ { + HALMAC_TRX_MODE mode; + HALMAC_DMA_MAPPING dma_map_vo; + HALMAC_DMA_MAPPING dma_map_vi; + HALMAC_DMA_MAPPING dma_map_be; + HALMAC_DMA_MAPPING dma_map_bk; + HALMAC_DMA_MAPPING dma_map_mg; + HALMAC_DMA_MAPPING dma_map_hi; +} HALMAC_RQPN, *PHALMAC_RQPN; + +typedef struct _HALMAC_PG_NUM_ { + HALMAC_TRX_MODE mode; + u16 hq_num; + u16 nq_num; + u16 lq_num; + u16 exq_num; + u16 gap_num;/*used for loopback mode*/ +} HALMAC_PG_NUM, *PHALMAC_PG_NUM; + +typedef struct _HALMAC_INTF_PHY_PARA_ { + u16 offset; + u16 value; + u16 ip_sel; + u16 cut; + u16 plaform; +} HALMAC_INTF_PHY_PARA, *PHALMAC_INTF_PHY_PARA; + +typedef struct _HALMAC_IQK_PARA_ { + u8 clear; + u8 segment_iqk; +} HALMAC_IQK_PARA, *PHALMAC_IQK_PARA; + +typedef struct _HALMAC_SDIO_HW_INFO { + HALMAC_SDIO_SPEC_VER spec_ver; + u32 clock_speed; + u8 io_hi_speed_flag; /* Halmac internal use */ +} HALMAC_SDIO_HW_INFO, *PHALMAC_SDIO_HW_INFO; + +/* Hal mac adapter */ +typedef struct _HALMAC_ADAPTER { + HALMAC_DMA_MAPPING halmac_ptcl_queue[HALMAC_PTCL_QUEUE_NUM]; /* Dma mapping of protocol queues */ + HALMAC_FWLPS_OPTION fwlps_option; /* low power state option */ + HALMAC_WLAN_ADDR pHal_mac_addr[HALMAC_PORTIDMAX]; /* mac address information, suppot 2 ports */ + HALMAC_WLAN_ADDR pHal_bss_addr[HALMAC_PORTIDMAX]; /* bss address information, suppot 2 ports */ + HALMAC_MUTEX h2c_seq_mutex; /* Protect h2c_packet_seq packet*/ + HALMAC_MUTEX EfuseMutex; /* Protect Efuse map memory of halmac_adapter */ + HALMAC_CONFIG_PARA_INFO config_para_info; + HALMAC_CS_INFO ch_sw_info; + HALMAC_EVENT_TRIGGER event_trigger; + HALMAC_HW_CONFIG_INFO hw_config_info; /* HW related information */ + HALMAC_SDIO_FREE_SPACE sdio_free_space; + HALMAC_SND_INFO snd_info; + VOID *pHalAdapter_backup; /* Backup HalAdapter address */ + VOID *pDriver_adapter; /* Driver or FW adapter address. Do not write this memory*/ + u8 *pHalEfuse_map; + VOID *pHalmac_api; /* Record function pointer of halmac api */ + PHALMAC_PLATFORM_API pHalmac_platform_api; /* Record function pointer of platform api */ + u32 efuse_end; /* Record efuse used memory */ + u32 h2c_buf_free_space; + u32 h2c_buff_size; + u32 max_download_size; + HALMAC_CHIP_ID chip_id; /* Chip ID, 8822B, 8821C... */ + HALMAC_CHIP_VER chip_version; /* A cut, B cut... */ + HALMAC_FW_VERSION fw_version; + HALMAC_STATE halmac_state; + HALMAC_INTERFACE halmac_interface; /* Interface information, get from driver */ + HALMAC_TRX_MODE trx_mode; /* Noraml, WMM, P2P, LoopBack... */ + HALMAC_TXFF_ALLOCATION txff_allocation; + u8 h2c_packet_seq; /* current h2c packet sequence number */ + u16 ack_h2c_packet_seq; /*the acked h2c packet sequence number */ + u8 hal_efuse_map_valid; + u8 efuse_segment_size; + u8 rpwm_record; /* record rpwm value */ + u8 low_clk; /*LPS 32K or IPS 32K*/ + u8 halmac_bulkout_num; /* USB bulkout num */ + HALMAC_API_RECORD api_record; /* API record */ + u8 gen_info_valid; + HALMAC_GENERAL_INFO general_info; + u8 drv_info_size; + HALMAC_SDIO_CMD53_4BYTE_MODE sdio_cmd53_4byte; + HALMAC_SDIO_HW_INFO sdio_hw_info; +} HALMAC_ADAPTER, *PHALMAC_ADAPTER; + +/* Function pointer of Hal mac API */ +typedef struct _HALMAC_API { + HALMAC_RET_STATUS(*halmac_mac_power_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_MAC_POWER halmac_power); + HALMAC_RET_STATUS(*halmac_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHamacl_fw, u32 halmac_fw_size); + HALMAC_RET_STATUS (*halmac_free_download_firmware)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DLFW_MEM dlfw_mem, u8 *pHamacl_fw, u32 halmac_fw_size); + HALMAC_RET_STATUS(*halmac_get_fw_version)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FW_VERSION pFw_version); + HALMAC_RET_STATUS(*halmac_cfg_mac_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); + HALMAC_RET_STATUS(*halmac_cfg_bssid)(PHALMAC_ADAPTER pHalmac_adapter, u8 halmac_port, PHALMAC_WLAN_ADDR pHal_address); + HALMAC_RET_STATUS(*halmac_cfg_multicast_addr)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WLAN_ADDR pHal_address); + HALMAC_RET_STATUS(*halmac_pre_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_init_system_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_init_trx_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode); + HALMAC_RET_STATUS(*halmac_init_h2c)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_cfg_rx_aggregation)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_RXAGG_CFG phalmac_rxagg_cfg); + HALMAC_RET_STATUS(*halmac_init_protocol_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_init_edca_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_cfg_operation_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_WIRELESS_MODE wireless_mode); + HALMAC_RET_STATUS(*halmac_cfg_ch_bw)(PHALMAC_ADAPTER pHalmac_adapter, u8 channel, HALMAC_PRI_CH_IDX pri_ch_idx, HALMAC_BW bw); + HALMAC_RET_STATUS(*halmac_cfg_bw)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_BW bw); + HALMAC_RET_STATUS(*halmac_init_wmac_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_init_mac_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_TRX_MODE Mode); + HALMAC_RET_STATUS(*halmac_init_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_init_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_init_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_deinit_usb_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_deinit_pcie_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_deinit_interface_cfg)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_get_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); + HALMAC_RET_STATUS(*halmac_get_efuse_available_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); + HALMAC_RET_STATUS(*halmac_dump_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); + HALMAC_RET_STATUS(*halmac_dump_efuse_map_bt)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank, u32 bt_efuse_map_size, u8 *pBT_efuse_map); + HALMAC_RET_STATUS(*halmac_write_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); + HALMAC_RET_STATUS(*halmac_read_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); + HALMAC_RET_STATUS(*halmac_switch_efuse_bank)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_BANK halmac_efues_bank); + HALMAC_RET_STATUS(*halmac_write_efuse_bt)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value, HALMAC_EFUSE_BANK halmac_efues_bank); + HALMAC_RET_STATUS(*halmac_get_logical_efuse_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 *halmac_size); + HALMAC_RET_STATUS(*halmac_dump_logical_efuse_map)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_EFUSE_READ_CFG cfg); + HALMAC_RET_STATUS(*halmac_write_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_value); + HALMAC_RET_STATUS(*halmac_read_logical_efuse)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 *pValue); + HALMAC_RET_STATUS(*halmac_pg_efuse_by_map)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PG_EFUSE_INFO pPg_efuse_info, HALMAC_EFUSE_READ_CFG cfg); + HALMAC_RET_STATUS(*halmac_get_c2h_info)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size); + HALMAC_RET_STATUS(*halmac_cfg_fwlps_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWLPS_OPTION pLps_option); + HALMAC_RET_STATUS(*halmac_cfg_fwips_option)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_FWIPS_OPTION pIps_option); + HALMAC_RET_STATUS(*halmac_enter_wowlan)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_WOWLAN_OPTION pWowlan_option); + HALMAC_RET_STATUS(*halmac_leave_wowlan)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_enter_ps)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PS_STATE ps_state); + HALMAC_RET_STATUS(*halmac_leave_ps)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_h2c_lb)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_debug)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_cfg_parameter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PHY_PARAMETER_INFO para_info, u8 full_fifo); + HALMAC_RET_STATUS(*halmac_update_packet)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PACKET_ID pkt_id, u8 *pkt, u32 pkt_size); + HALMAC_RET_STATUS(*halmac_bcn_ie_filter)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_BCN_IE_INFO pBcn_ie_info); + u8 (*halmac_reg_read_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); + HALMAC_RET_STATUS(*halmac_reg_write_8)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u8 halmac_data); + u16 (*halmac_reg_read_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); + HALMAC_RET_STATUS(*halmac_reg_write_16)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u16 halmac_data); + u32 (*halmac_reg_read_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); + u32 (*halmac_reg_read_indirect_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset); + u8 (*halmac_reg_sdio_cmd53_read_n)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_size, u8 *halmac_data); + HALMAC_RET_STATUS(*halmac_reg_write_32)(PHALMAC_ADAPTER pHalmac_adapter, u32 halmac_offset, u32 halmac_data); + HALMAC_RET_STATUS(*halmac_tx_allowed_sdio)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); + HALMAC_RET_STATUS(*halmac_set_bulkout_num)(PHALMAC_ADAPTER pHalmac_adapter, u8 bulkout_num); + HALMAC_RET_STATUS(*halmac_get_sdio_tx_addr)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u32 *pcmd53_addr); + HALMAC_RET_STATUS(*halmac_get_usb_bulkout_id)(PHALMAC_ADAPTER pHalmac_adapter, u8 *halmac_buf, u32 halmac_size, u8 *bulkout_id); + HALMAC_RET_STATUS(*halmac_timer_2s)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_fill_txdesc_checksum)(PHALMAC_ADAPTER pHalmac_adapter, u8 *cur_desc); + HALMAC_RET_STATUS(*halmac_update_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type, PHALMAC_PHY_PARAMETER_INFO para_info); + HALMAC_RET_STATUS(*halmac_run_datapack)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DATA_TYPE halmac_data_type); + HALMAC_RET_STATUS(*halmac_cfg_drv_info)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_INFO halmac_drv_info); + HALMAC_RET_STATUS(*halmac_send_bt_coex)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pBt_buf, u32 bt_size, u8 ack); + HALMAC_RET_STATUS(*halmac_verify_platform_api)(PHALMAC_ADAPTER pHalmac_adapte); + u32 (*halmac_get_fifo_size)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel); + HALMAC_RET_STATUS(*halmac_dump_fifo)(PHALMAC_ADAPTER pHalmac_adapter, HAL_FIFO_SEL halmac_fifo_sel, u32 halmac_start_addr, u32 halmac_fifo_dump_size, u8 *pFifo_map); + HALMAC_RET_STATUS(*halmac_cfg_txbf)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, HALMAC_BW bw, u8 txbf_en); + HALMAC_RET_STATUS(*halmac_cfg_mumimo)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CFG_MUMIMO_PARA pCfgmu); + HALMAC_RET_STATUS(*halmac_cfg_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role, HALMAC_DATA_RATE datarate); + HALMAC_RET_STATUS(*halmac_del_sounding)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_SND_ROLE role); + HALMAC_RET_STATUS(*halmac_su_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SU_BFER_INIT_PARA pSu_bfer_init); + HALMAC_RET_STATUS(*halmac_su_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid, u16 paid); + HALMAC_RET_STATUS(*halmac_mu_bfer_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFER_INIT_PARA pMu_bfer_init); + HALMAC_RET_STATUS(*halmac_mu_bfee_entry_init)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_MU_BFEE_INIT_PARA pMu_bfee_init); + HALMAC_RET_STATUS(*halmac_su_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); + HALMAC_RET_STATUS(*halmac_su_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); + HALMAC_RET_STATUS(*halmac_mu_bfer_entry_del)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_mu_bfee_entry_del)(PHALMAC_ADAPTER pHalmac_adapter, u8 userid); + HALMAC_RET_STATUS(*halmac_add_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_INFO pCh_info); + HALMAC_RET_STATUS(*halmac_add_extra_ch_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_EXTRA_INFO pCh_extra_info); + HALMAC_RET_STATUS(*halmac_ctrl_ch_switch)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_CH_SWITCH_OPTION pCs_option); + HALMAC_RET_STATUS (*halmac_p2pps)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_P2PPS pP2PPS); + HALMAC_RET_STATUS(*halmac_clear_ch_info)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS(*halmac_send_general_info)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_GENERAL_INFO pgGeneral_info); + HALMAC_RET_STATUS (*halmac_start_iqk)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_IQK_PARA pIqk_para); + HALMAC_RET_STATUS(*halmac_ctrl_pwr_tracking)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_PWR_TRACKING_OPTION pPwr_tracking_opt); + HALMAC_RET_STATUS(*halmac_psd)(PHALMAC_ADAPTER pHalmac_adapter, u16 start_psd, u16 end_psd); + HALMAC_RET_STATUS(*halmac_cfg_tx_agg_align)(PHALMAC_ADAPTER pHalmac_adapter, u8 enable, u16 align_size); + HALMAC_RET_STATUS(*halmac_query_status)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id, HALMAC_CMD_PROCESS_STATUS *pProcess_status, u8 *data, u32 *size); + HALMAC_RET_STATUS(*halmac_reset_feature)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_FEATURE_ID feature_id); + HALMAC_RET_STATUS(*halmac_check_fw_status)(PHALMAC_ADAPTER pHalmac_adapter, u8 *fw_status); + HALMAC_RET_STATUS(*halmac_dump_fw_dmem)(PHALMAC_ADAPTER pHalmac_adapter, u8 *dmem, u32 *size); + HALMAC_RET_STATUS(*halmac_cfg_max_dl_size)(PHALMAC_ADAPTER pHalmac_adapter, u32 size); + HALMAC_RET_STATUS(*halmac_cfg_la_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_LA_MODE la_mode); + HALMAC_RET_STATUS(*halmac_cfg_rx_fifo_expanding_mode)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_RX_FIFO_EXPANDING_MODE rx_fifo_expanding_mode); + HALMAC_RET_STATUS(*halmac_config_security)(PHALMAC_ADAPTER pHalmac_adapter, PHALMAC_SECURITY_SETTING pSec_setting); + u8 (*halmac_get_used_cam_entry_num)(PHALMAC_ADAPTER pHalmac_adapter, HAL_SECURITY_TYPE sec_type); + HALMAC_RET_STATUS(*halmac_write_cam)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_INFO pCam_entry_info); + HALMAC_RET_STATUS(*halmac_read_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index, PHALMAC_CAM_ENTRY_FORMAT pContent); + HALMAC_RET_STATUS(*halmac_clear_cam_entry)(PHALMAC_ADAPTER pHalmac_adapter, u32 entry_index); + HALMAC_RET_STATUS(*halmac_get_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); + HALMAC_RET_STATUS(*halmac_set_hw_value)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_HW_ID hw_id, VOID *pvalue); + HALMAC_RET_STATUS(*halmac_cfg_drv_rsvd_pg_num)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_DRV_RSVD_PG_NUM pg_num); + HALMAC_RET_STATUS(*halmac_get_chip_version)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_VER *version); + HALMAC_RET_STATUS(*halmac_chk_txdesc)(PHALMAC_ADAPTER pHalmac_adapter, u8 *pHalmac_buf, u32 halmac_size); + HALMAC_RET_STATUS(*halmac_dl_drv_rsvd_page)(PHALMAC_ADAPTER pHalmac_adapter, u8 pg_offset, u8 *pHal_buf, u32 size); + HALMAC_RET_STATUS(*halmac_pcie_switch)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_PCIE_CFG pcie_cfg); + HALMAC_RET_STATUS(*halmac_phy_cfg)(PHALMAC_ADAPTER pHalmac_adapter, HALMAC_INTF_PHY_PLATFORM platform); + HALMAC_RET_STATUS(*halmac_cfg_csi_rate)(PHALMAC_ADAPTER pHalmac_adapter, u8 rssi, u8 current_rate, u8 fixrate_en, u8 *new_rate); + HALMAC_RET_STATUS (*halmac_interface_integration_tuning)(PHALMAC_ADAPTER pHalmac_adapter); + HALMAC_RET_STATUS (*halmac_txfifo_is_empty)(PHALMAC_ADAPTER pHalmac_adapter, u32 chk_num); +} HALMAC_API, *PHALMAC_API; + +#define HALMAC_GET_API(phalmac_adapter) ((PHALMAC_API)phalmac_adapter->pHalmac_api) + +static HALMAC_INLINE HALMAC_RET_STATUS +halmac_adapter_validate( + PHALMAC_ADAPTER pHalmac_adapter +) +{ + if ((NULL == pHalmac_adapter) || (pHalmac_adapter->pHalAdapter_backup != pHalmac_adapter)) + return HALMAC_RET_ADAPTER_INVALID; + + return HALMAC_RET_SUCCESS; +} + +static HALMAC_INLINE HALMAC_RET_STATUS +halmac_api_validate( + PHALMAC_ADAPTER pHalmac_adapter +) +{ + if (HALMAC_API_STATE_INIT != pHalmac_adapter->halmac_state.api_state) + return HALMAC_RET_API_INVALID; + + return HALMAC_RET_SUCCESS; +} + +static HALMAC_INLINE HALMAC_RET_STATUS +halmac_fw_validate( + PHALMAC_ADAPTER pHalmac_adapter +) +{ + if (HALMAC_DLFW_DONE != pHalmac_adapter->halmac_state.dlfw_state && HALMAC_GEN_INFO_SENT != pHalmac_adapter->halmac_state.dlfw_state) + return HALMAC_RET_NO_DLFW; + + return HALMAC_RET_SUCCESS; +} + +#endif diff --git a/drivers/staging/rtl8821ce/hal/led/hal_pci_led.c b/drivers/staging/rtl8821ce/hal/led/hal_pci_led.c new file mode 100644 index 000000000000..c023f6a4751f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/led/hal_pci_led.c @@ -0,0 +1,1214 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <hal_data.h> + +/* + * Description: + * Turn on LED according to LedPin specified. + * */ +VOID +HwLedBlink( + IN PADAPTER Adapter, + IN PLED_PCIE pLed +) +{ + + switch (pLed->LedPin) { + case LED_PIN_GPIO0: + break; + + case LED_PIN_LED0: + /* rtw_write8(Adapter, LED0Cfg, 0x2); */ + break; + + case LED_PIN_LED1: + /* rtw_write8(Adapter, LED1Cfg, 0x2); */ + break; + + default: + break; + } + + pLed->bLedOn = _TRUE; +} + +VOID +SwLedBlink6( + IN PLED_PCIE pLed +) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + /* Change LED according to BlinkingLedState specified. */ + if (pLed->BlinkingLedState == RTW_LED_ON) { + SwLedOn(Adapter, pLed); + } else { + SwLedOff(Adapter, pLed); + } + + switch (pLed->CurrLedState) { + case RTW_LED_OFF: + SwLedOff(Adapter, pLed); + break; + + case LED_BLINK_SLOWLY: + if (pLed->bLedOn) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET); + break; + + case LED_BLINK_NORMAL: + pLed->BlinkTimes--; + if (pLed->BlinkTimes == 0) + bStopBlinking = _TRUE; + if (bStopBlinking) { + if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on) + SwLedOff(Adapter, pLed); + else { + pLed->bLedSlowBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if (pLed->bLedOn) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL_PORNET); + } + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } else { + if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on) + SwLedOff(Adapter, pLed); + else { + if (pLed->bLedOn) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL_PORNET); + } + } + break; + + default: + break; + } + +} + +VOID +SwLedBlink7( + IN PLED_PCIE pLed +) +{ + PADAPTER Adapter = pLed->padapter; + + SwLedOn(Adapter, pLed); +} + +/* + * Description: + * Implement LED blinking behavior for SW_LED_MODE8. + * It toggle off LED and schedule corresponding timer if necessary. + * */ +VOID +SwLedBlink8( + IN PLED_PCIE pLed +) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + /* Change LED according to BlinkingLedState specified. */ + if (pLed->BlinkingLedState == RTW_LED_ON) { + SwLedOn(Adapter, pLed); + } else { + SwLedOff(Adapter, pLed); + } + + /* Determine if we shall change LED state again. */ + if (pLed->CurrLedState != LED_BLINK_NO_LINK) + pLed->BlinkTimes--; + + switch (pLed->CurrLedState) { + case LED_BLINK_NORMAL: + case LED_BLINK_SCAN: + if (pLed->BlinkTimes == 0) + bStopBlinking = _TRUE; + break; + + default: + break; + } + + if (bStopBlinking) { + if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) { + pLed->CurrLedState = RTW_LED_OFF; + SwLedOff(Adapter, pLed); + } else { + pLed->CurrLedState = RTW_LED_ON; + SwLedOn(Adapter, pLed); + } + + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } else { + /* Assign LED state to toggle. */ + if (pLed->BlinkingLedState == RTW_LED_ON) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + /* Schedule a timer to toggle LED state. */ + switch (pLed->CurrLedState) { + case LED_BLINK_NORMAL: + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + break; + + default: + /* RTW_INFO("SwLedCm8Blink(): unexpected state!\n"); */ + break; + } + } +} + +VOID +SwLedBlink9( + IN PLED_PCIE pLed +) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + /* Change LED according to BlinkingLedState specified. */ + if (pLed->BlinkingLedState == RTW_LED_ON) { + SwLedOn(Adapter, pLed); + } else { + SwLedOff(Adapter, pLed); + } + + /* Determine if we shall change LED state again. */ + if (pLed->CurrLedState != LED_BLINK_NO_LINK) + pLed->BlinkTimes--; + + switch (pLed->CurrLedState) { + case LED_BLINK_NORMAL: + case LED_BLINK_SCAN: + if (pLed->BlinkTimes == 0) + bStopBlinking = _TRUE; + break; + + case LED_BLINK_NO_LINK: + if (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + bStopBlinking = _TRUE; + else if (check_fwstate(pmlmepriv, _FW_LINKED) && + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))) + bStopBlinking = _TRUE; + break; + + default: + break; + } + + if (bStopBlinking) { + if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) { + pLed->CurrLedState = RTW_LED_OFF; + SwLedOff(Adapter, pLed); + } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + pLed->CurrLedState = RTW_LED_ON; + SwLedOn(Adapter, pLed); + } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { + pLed->CurrLedState = LED_BLINK_NO_LINK; + if (pLed->bLedOn) + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + + pLed->BlinkTimes = 0; + if (pLed->CurrLedState != LED_BLINK_NO_LINK) + pLed->bLedBlinkInProgress = _FALSE; + } else { + /* Assign LED state to toggle. */ + if (pLed->BlinkingLedState == RTW_LED_ON) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + /* Schedule a timer to toggle LED state. */ + switch (pLed->CurrLedState) { + case LED_BLINK_NORMAL: + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND); + break; + + case LED_BLINK_SCAN: + case LED_BLINK_NO_LINK: + if (pLed->bLedOn) + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + break; + + default: + /* RTW_INFO("SwLedCm2Blink(): unexpected state!\n"); */ + break; + } + } + +} + +VOID +SwLedBlink10( + IN PLED_PCIE pLed +) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + /* Change LED according to BlinkingLedState specified. */ + if (pLed->BlinkingLedState == RTW_LED_ON) { + SwLedOn(Adapter, pLed); + } else { + SwLedOff(Adapter, pLed); + } + + /* Determine if we shall change LED state again. */ + if (pLed->CurrLedState != LED_BLINK_NO_LINK) + pLed->BlinkTimes--; + + switch (pLed->CurrLedState) { + case LED_BLINK_NORMAL: + case LED_BLINK_SCAN: + if (pLed->BlinkTimes == 0) + bStopBlinking = _TRUE; + break; + default: + break; + } + + if (bStopBlinking) { + pLed->CurrLedState = RTW_LED_OFF; + SwLedOff(Adapter, pLed); + + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } else { + /* Assign LED state to toggle. */ + if (pLed->BlinkingLedState == RTW_LED_ON) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + /* Schedule a timer to toggle LED state. */ + switch (pLed->CurrLedState) { + case LED_BLINK_NORMAL: + case LED_BLINK_SCAN: + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND); + break; + + default: + /* RT_ASSERT(_FALSE, ("SwLedCm2Blink(): unexpected state!\n")); */ + break; + } + } + +} + +VOID +SwLedBlink11( + IN PLED_PCIE pLed +) +{ + PADAPTER Adapter = pLed->padapter; + BOOLEAN bStopBlinking = _FALSE; + + /* Change LED according to BlinkingLedState specified. */ + if (pLed->bLedBlinkInProgress == _TRUE) { + if (pLed->BlinkingLedState == RTW_LED_ON) { + SwLedOn(Adapter, pLed); + } else { + SwLedOff(Adapter, pLed); + } + } + + /* Determine if we shall change LED state again. */ + if (pLed->CurrLedState != LED_BLINK_NO_LINK) + pLed->BlinkTimes--; + + switch (pLed->CurrLedState) { + case RTW_LED_ON: + bStopBlinking = _TRUE; /* LED on for 3 seconds */ + default: + break; + } + + if (bStopBlinking) { + pLed->CurrLedState = RTW_LED_OFF; + SwLedOff(Adapter, pLed); + + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } else { + /* Assign LED state to toggle. */ + if (pLed->BlinkingLedState == RTW_LED_ON) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + /* Schedule a timer to toggle LED state. */ + switch (pLed->CurrLedState) { + case LED_BLINK_XAVI: + _set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL); + break; + + default: + /* RT_ASSERT(_FALSE, ("SwLedCm11Blink(): unexpected state!\n")); */ + break; + } + } + +} + +VOID +SwLedBlink12( + IN PLED_PCIE pLed +) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + /* Change LED according to BlinkingLedState specified. */ + if (pLed->BlinkingLedState == RTW_LED_ON) { + SwLedOn(Adapter, pLed); + } else { + SwLedOff(Adapter, pLed); + } + + /* Determine if we shall change LED state again. */ + if (pLed->CurrLedState != LED_BLINK_NO_LINK && pLed->CurrLedState != LED_BLINK_Azurewave_5Mbps + && pLed->CurrLedState != LED_BLINK_Azurewave_10Mbps && pLed->CurrLedState != LED_BLINK_Azurewave_20Mbps + && pLed->CurrLedState != LED_BLINK_Azurewave_40Mbps && pLed->CurrLedState != LED_BLINK_Azurewave_80Mbps + && pLed->CurrLedState != LED_BLINK_Azurewave_MAXMbps) + pLed->BlinkTimes--; + + switch (pLed->CurrLedState) { + case LED_BLINK_NORMAL: + case LED_BLINK_SCAN: + if (pLed->BlinkTimes == 0) + bStopBlinking = _TRUE; + break; + + case LED_BLINK_NO_LINK: + if (check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + bStopBlinking = _TRUE; + else if (check_fwstate(pmlmepriv, _FW_LINKED) && + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE))) + bStopBlinking = _TRUE; + break; + + case LED_BLINK_Azurewave_5Mbps: + case LED_BLINK_Azurewave_10Mbps: + case LED_BLINK_Azurewave_20Mbps: + case LED_BLINK_Azurewave_40Mbps: + case LED_BLINK_Azurewave_80Mbps: + case LED_BLINK_Azurewave_MAXMbps: + /* if(pTurboCa->TxThroughput + pTurboCa->RxThroughput == 0) */ + /* bStopBlinking = _TRUE; */ + + default: + break; + } + + if (bStopBlinking) { + if (adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + SwLedOff(Adapter, pLed); + } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + SwLedOn(Adapter, pLed); + } else if (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) { + pLed->CurrLedState = LED_BLINK_NO_LINK; + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + } + + pLed->BlinkTimes = 0; + if (pLed->CurrLedState != LED_BLINK_NO_LINK) + pLed->bLedBlinkInProgress = _FALSE; + } else { + /* Assign LED state to toggle. */ + if (pLed->BlinkingLedState == RTW_LED_ON) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + /* Schedule a timer to toggle LED state. */ + switch (pLed->CurrLedState) { + case LED_BLINK_Azurewave_5Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_5Mbps); + break; + + case LED_BLINK_Azurewave_10Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_10Mbps); + break; + + case LED_BLINK_Azurewave_20Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_20Mbps); + break; + + case LED_BLINK_Azurewave_40Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_40Mbps); + break; + + case LED_BLINK_Azurewave_80Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_80Mbps); + break; + + case LED_BLINK_Azurewave_MAXMbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_MAXMbps); + break; + + case LED_BLINK_SCAN: + case LED_BLINK_NO_LINK: + if (pLed->bLedOn) + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + break; + + default: + /* RT_ASSERT(_FALSE, ("SwLedCm12Blink(): unexpected state!\n")); */ + break; + } + } + +} + +/* + * Description: + * Handler function of LED Blinking. + * We dispatch acture LED blink action according to LedStrategy. + * */ +void BlinkHandler(PLED_PCIE pLed) +{ + _adapter *padapter = pLed->padapter; + struct led_priv *ledpriv = &(padapter->ledpriv); + + if (RTW_CANNOT_RUN(padapter)) + return; + + if (IS_HARDWARE_TYPE_8188E(padapter) || + IS_HARDWARE_TYPE_JAGUAR(padapter) || + IS_HARDWARE_TYPE_8723B(padapter) || + IS_HARDWARE_TYPE_8192E(padapter)) + return; + + switch (ledpriv->LedStrategy) { + case SW_LED_MODE1: + /* SwLedBlink(pLed); */ + break; + case SW_LED_MODE2: + /* SwLedBlink(pLed); */ + break; + case SW_LED_MODE3: + /* SwLedBlink(pLed); */ + break; + case SW_LED_MODE5: + /* SwLedBlink5(pLed); */ + break; + case SW_LED_MODE6: + /* SwLedBlink6(pLed); */ + break; + case SW_LED_MODE7: + SwLedBlink7(pLed); + break; + case SW_LED_MODE8: + SwLedBlink8(pLed); + break; + + case SW_LED_MODE9: + SwLedBlink9(pLed); + break; + + case SW_LED_MODE10: + SwLedBlink10(pLed); + break; + + case SW_LED_MODE11: + SwLedBlink11(pLed); + break; + + case SW_LED_MODE12: + SwLedBlink12(pLed); + break; + + default: + /* SwLedBlink(pLed); */ + break; + } +} + +/* + * Description: + * Callback function of LED BlinkTimer, + * it just schedules to corresponding BlinkWorkItem/led_blink_hdl + * */ +void BlinkTimerCallback(void *data) +{ + PLED_PCIE pLed = (PLED_PCIE)data; + _adapter *padapter = pLed->padapter; + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) { + /*RTW_INFO("%s bDriverStopped:%s, bSurpriseRemoved:%s\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" ); + */ + return; + } + + BlinkHandler(pLed); +} + +/* added by chiyokolin, for Lenovo */ +VOID +SwLedControlMode7( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + PLED_PCIE pLed0 = &(ledpriv->SwLed0); + + switch (LedAction) { + case LED_CTL_POWER_ON: + case LED_CTL_LINK: + case LED_CTL_NO_LINK: + SwLedOn(Adapter, pLed0); + break; + + case LED_CTL_POWER_OFF: + SwLedOff(Adapter, pLed0); + break; + + default: + break; + } +} + +/* added by chiyokolin, for QMI */ +VOID +SwLedControlMode8( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + PLED_PCIE pLed = &(ledpriv->SwLed0); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + /* Decide led state */ + switch (LedAction) { + case LED_CTL_TX: + case LED_CTL_RX: + if (pLed->bLedBlinkInProgress == _FALSE && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_NORMAL; + pLed->BlinkTimes = 2; + + if (pLed->bLedOn) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_CTL_SITE_SURVEY: + case LED_CTL_POWER_ON: + case LED_CTL_NO_LINK: + case LED_CTL_LINK: + pLed->CurrLedState = RTW_LED_ON; + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOn(Adapter, pLed); + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed); + break; + + default: + break; + } +} + +/* added by chiyokolin, for MSI */ +VOID +SwLedControlMode9( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + PLED_PCIE pLed = &(ledpriv->SwLed0); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + /* Decide led state */ + switch (LedAction) { + case LED_CTL_TX: + case LED_CTL_RX: + if (pLed->bLedBlinkInProgress == _FALSE && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_NORMAL; + pLed->BlinkTimes = 2; + + if (pLed->bLedOn) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FAST_INTERVAL_BITLAND); + } + break; + + case LED_CTL_SITE_SURVEY: + if (pLed->bLedBlinkInProgress == _FALSE) { + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 2; + + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + } else if (pLed->CurrLedState != LED_BLINK_SCAN) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 2; + + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + } + break; + + case LED_CTL_POWER_ON: + case LED_CTL_NO_LINK: + if (pLed->bLedBlinkInProgress == _FALSE) { + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_NO_LINK; + pLed->BlinkTimes = 24; + + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + } else if (pLed->CurrLedState != LED_BLINK_SCAN && pLed->CurrLedState != LED_BLINK_NO_LINK) { + pLed->CurrLedState = LED_BLINK_NO_LINK; + pLed->BlinkTimes = 24; + + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + } + break; + + case LED_CTL_LINK: + pLed->CurrLedState = RTW_LED_ON; + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOn(Adapter, pLed); + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed); + break; + + default: + break; + } + +} + +/* added by chiyokolin, for Edimax-ASUS */ +VOID +SwLedControlMode10( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct led_priv *ledpriv = &(Adapter->ledpriv); + PLED_PCIE pLed0 = &(ledpriv->SwLed0); + PLED_PCIE pLed1 = &(ledpriv->SwLed1); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + /* Decide led state */ + switch (LedAction) { + case LED_CTL_TX: + case LED_CTL_RX: + if (pLed1->bLedBlinkInProgress == _FALSE && pLed1->bLedWPSBlinkInProgress == _FALSE && + (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { + pLed1->bLedBlinkInProgress = _TRUE; + + pLed1->CurrLedState = LED_BLINK_NORMAL; + pLed1->BlinkTimes = 2; + + if (pLed1->bLedOn) + pLed1->BlinkingLedState = RTW_LED_OFF; + else + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_CTL_SITE_SURVEY: + if (pLed1->bLedBlinkInProgress == _FALSE && pLed1->bLedWPSBlinkInProgress == _FALSE) { + pLed1->bLedBlinkInProgress = _TRUE; + pLed1->CurrLedState = LED_BLINK_SCAN; + pLed1->BlinkTimes = 12; + + if (pLed1->bLedOn) { + pLed1->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } else { + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + } else if (pLed1->CurrLedState != LED_BLINK_SCAN && pLed1->bLedWPSBlinkInProgress == _FALSE) { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->CurrLedState = LED_BLINK_SCAN; + pLed1->BlinkTimes = 24; + + if (pLed1->bLedOn) { + pLed1->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } else { + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + } + break; + + case LED_CTL_START_WPS: + case LED_CTL_START_WPS_BOTTON: + pLed1->CurrLedState = RTW_LED_ON; + if (pLed1->bLedBlinkInProgress == _TRUE) { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedBlinkInProgress = _FALSE; + } + + if (pLed1->bLedWPSBlinkInProgress == _FALSE) { + pLed1->bLedWPSBlinkInProgress = _TRUE; + SwLedOn(Adapter, pLed1); + } + break; + + case LED_CTL_STOP_WPS: + case LED_CTL_STOP_WPS_FAIL: + case LED_CTL_STOP_WPS_FAIL_OVERLAP: + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + pLed0->CurrLedState = RTW_LED_ON; + if (pLed0->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->bLedBlinkInProgress = _FALSE; + } + SwLedOn(Adapter, pLed0); + } else { + pLed0->CurrLedState = RTW_LED_OFF; + if (pLed0->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed0); + } + + pLed1->CurrLedState = RTW_LED_OFF; + if (pLed1->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed1); + + pLed1->bLedWPSBlinkInProgress = _FALSE; + + break; + + case LED_CTL_LINK: + pLed0->CurrLedState = RTW_LED_ON; + if (pLed0->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->bLedBlinkInProgress = _FALSE; + } + SwLedOn(Adapter, pLed0); + break; + + case LED_CTL_NO_LINK: + if (pLed1->bLedWPSBlinkInProgress == _TRUE) { + SwLedOn(Adapter, pLed1); + break; + } + + if (pLed1->CurrLedState == LED_BLINK_SCAN) + break; + + pLed0->CurrLedState = RTW_LED_OFF; + if (pLed0->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed0); + + pLed1->CurrLedState = RTW_LED_OFF; + if (pLed1->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed1); + + break; + + case LED_CTL_POWER_ON: + case LED_CTL_POWER_OFF: + if (pLed1->bLedWPSBlinkInProgress == _TRUE) { + SwLedOn(Adapter, pLed1); + break; + } + pLed0->CurrLedState = RTW_LED_OFF; + if (pLed0->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed0); + + pLed1->CurrLedState = RTW_LED_OFF; + if (pLed1->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed1); + + break; + + default: + break; + + } + +} + +/* added by hpfan, for Xavi */ +VOID +SwLedControlMode11( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + PLED_PCIE pLed = &(ledpriv->SwLed0); + + /* Decide led state */ + switch (LedAction) { + case LED_CTL_START_WPS: + case LED_CTL_START_WPS_BOTTON: + pLed->bLedWPSBlinkInProgress = _TRUE; + if (pLed->bLedBlinkInProgress == _FALSE) { + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_XAVI; + + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL); + } + } + break; + + case LED_CTL_STOP_WPS: + case LED_CTL_STOP_WPS_FAIL: + case LED_CTL_STOP_WPS_FAIL_OVERLAP: + pLed->bLedWPSBlinkInProgress = _FALSE; + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + pLed->CurrLedState = RTW_LED_OFF; + } + SwLedOff(Adapter, pLed); + break; + + case LED_CTL_LINK: + if (pLed->bLedWPSBlinkInProgress) + break; + + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + pLed->CurrLedState = RTW_LED_ON; + + if (!pLed->bLedOn) + SwLedOn(Adapter, pLed); + } else { + pLed->CurrLedState = RTW_LED_ON; + SwLedOn(Adapter, pLed); + } + + _set_timer(&(pLed->BlinkTimer), LED_CM11_LINK_ON_INTERVEL); + pLed->BlinkingLedState = RTW_LED_OFF; + break; + + case LED_CTL_NO_LINK: + if (pLed->bLedWPSBlinkInProgress) + break; + + if (pLed->bLedBlinkInProgress == _TRUE) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->CurrLedState = RTW_LED_OFF; + SwLedOff(Adapter, pLed); + break; + + case LED_CTL_POWER_ON: + case LED_CTL_POWER_OFF: + if (pLed->bLedBlinkInProgress == _TRUE) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + pLed->CurrLedState = RTW_LED_OFF; + SwLedOff(Adapter, pLed); + break; + + default: + break; + + } + +} + +/* added by chiyokolin, for Azurewave */ +VOID +SwLedControlMode12( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + PLED_PCIE pLed = &(ledpriv->SwLed0); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + LED_STATE LedState = LED_UNKNOWN; + + /* Decide led state */ + switch (LedAction) { + case LED_CTL_TX: + case LED_CTL_RX: + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + if (pLed->CurrLedState == LED_BLINK_SCAN) + break; + + pLed->BlinkTimes = 0; + + if (pLed->bLedOn) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + /*if(pTurboCa->TotalThroughput <= 5) + LedState = LED_BLINK_Azurewave_5Mbps; + else if(pTurboCa->TotalThroughput <= 10) + LedState = LED_BLINK_Azurewave_10Mbps; + else if(pTurboCa->TotalThroughput <=20) + LedState = LED_BLINK_Azurewave_20Mbps; + else if(pTurboCa->TotalThroughput <=40) + LedState = LED_BLINK_Azurewave_40Mbps; + else if(pTurboCa->TotalThroughput <=80) + LedState = LED_BLINK_Azurewave_80Mbps; + else*/ + LedState = LED_BLINK_Azurewave_MAXMbps; + + if (pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState != LedState) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->CurrLedState = LedState; + pLed->bLedBlinkInProgress = _TRUE; + + switch (LedState) { + case LED_BLINK_Azurewave_5Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_5Mbps); + break; + + case LED_BLINK_Azurewave_10Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_10Mbps); + break; + + case LED_BLINK_Azurewave_20Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_20Mbps); + break; + + case LED_BLINK_Azurewave_40Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_40Mbps); + break; + + case LED_BLINK_Azurewave_80Mbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_80Mbps); + break; + + case LED_BLINK_Azurewave_MAXMbps: + _set_timer(&(pLed->BlinkTimer), LED_CM12_BLINK_INTERVAL_MAXMbps); + break; + + default: + break; + } + } + } + + break; + + case LED_CTL_SITE_SURVEY: + case LED_CTL_START_WPS: + case LED_CTL_START_WPS_BOTTON: + if (pLed->bLedBlinkInProgress == _FALSE) + pLed->bLedBlinkInProgress = _TRUE; + else if (pLed->CurrLedState != LED_BLINK_SCAN) + _cancel_timer_ex(&(pLed->BlinkTimer)); + + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 2; + + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + break; + + case LED_CTL_LINK: + pLed->CurrLedState = RTW_LED_ON; + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOn(Adapter, pLed); + break; + + case LED_CTL_NO_LINK: + case LED_CTL_POWER_ON: + if (pLed->CurrLedState == LED_BLINK_SCAN) + break; + + pLed->CurrLedState = LED_BLINK_NO_LINK; + pLed->bLedBlinkInProgress = _TRUE; + + if (pLed->bLedOn) { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM2_BLINK_ON_INTERVAL); + } else { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM8_BLINK_OFF_INTERVAL); + } + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + if (pLed->bLedBlinkInProgress) { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed); + break; + + default: + break; + + } + +} + +/* + * Description: + * Reset status of LED_871x object. + * */ +void ResetLedStatus(PLED_PCIE pLed) +{ + + pLed->CurrLedState = RTW_LED_OFF; /* Current LED state. */ + pLed->bLedOn = _FALSE; /* true if LED is ON, false if LED is OFF. */ + + pLed->bLedBlinkInProgress = _FALSE; /* true if it is blinking, false o.w.. */ + pLed->bLedWPSBlinkInProgress = _FALSE; + pLed->bLedSlowBlinkInProgress = _FALSE; + + pLed->BlinkTimes = 0; /* Number of times to toggle led state for blinking. */ + pLed->BlinkingLedState = LED_UNKNOWN; /* Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. */ +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ap.h b/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ap.h new file mode 100644 index 000000000000..77f4b05e432a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ap.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_H__ +#define __HAL_PHY_RF_H__ + +#include "phydm_powertracking_ap.h" +#include "rtl8822b/phydm_iqk_8821c.h" + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +}; + +typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void (*func_lck)(void *); +/* refine by YuChen for 8814A */ +typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_all_swing)(void *, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **, u8 **); + +struct _TXPWRTRACK_CFG { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_all_swing get_delta_all_swing_table; +}; + +void +configure_txpower_track( + void *p_dm_void, + struct _TXPWRTRACK_CFG *p_config +); + +void +odm_txpowertracking_callback_thermal_meter( + struct _ADAPTER *adapter +); + +void +odm_txpowertracking_callback_thermal_meter_jaguar_series( + struct _ADAPTER *adapter +); + + +#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M) + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + +void +odm_reset_iqk_result( + void *p_dm_void +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void phydm_rf_init(void *p_dm_void); +void phydm_rf_watchdog(void *p_dm_void); + +#endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ce.c b/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ce.c new file mode 100644 index 000000000000..a837813f62a9 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ce.c @@ -0,0 +1,705 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _delta_thermal) \ + do {\ + for (_offset = 0; _offset < _size; _offset++) { \ + \ + if (_delta_thermal < thermal_threshold[_direction][_offset]) { \ + \ + if (_offset != 0)\ + _offset--;\ + break;\ + } \ + } \ + if (_offset >= _size)\ + _offset = _size-1;\ + } while (0) + +void configure_txpower_track( + void *p_dm_void, + struct _TXPWRTRACK_CFG *p_config +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + + + + +/* JJ ADD 20161014 */ + + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + configure_txpower_track_8821c(p_config); + +} + +/* ********************************************************************** + * <20121113, Kordan> This function should be called when tx_agc changed. + * Otherwise the previous compensation is gone, because we record the + * delta of temperature between two TxPowerTracking watch dogs. + * + * NOTE: If Tx BB swing or Tx scaling is varified during run-time, still + * need to call this function. + * ********************************************************************** */ +void +odm_clear_txpowertracking_state( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + PHAL_DATA_TYPE p_hal_data = GET_HAL_DATA(p_dm_odm->adapter); + u8 p = 0; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; + p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->default_cck_index; + p_dm_odm->rf_calibrate_info.CCK_index = 0; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + + p_rf_calibrate_info->power_index_offset[p] = 0; + p_rf_calibrate_info->delta_power_index[p] = 0; + p_rf_calibrate_info->delta_power_index_last[p] = 0; + + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = 0; /* Initial Mix mode power tracking*/ + p_rf_calibrate_info->remnant_ofdm_swing_idx[p] = 0; + p_rf_calibrate_info->kfree_offset[p] = 0; + } + + p_rf_calibrate_info->modify_tx_agc_flag_path_a = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_b = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_c = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->modify_tx_agc_flag_path_d = false; /*Initial at Modify Tx Scaling mode*/ + p_rf_calibrate_info->remnant_cck_swing_idx = 0; + p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; + + p_rf_calibrate_info->modify_tx_agc_value_cck = 0; /* modify by Mingzhi.Guo */ + p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; /* modify by Mingzhi.Guo */ + +} + +void +odm_txpowertracking_callback_thermal_meter( + struct _ADAPTER *adapter +) +{ + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; + + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + u8 thermal_value = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + s8 diff_DPK[4] = {0}; + u8 thermal_value_avg_count = 0; + u32 thermal_value_avg = 0, regc80, regcd0, regcd4, regab4; + + u8 OFDM_min_index = 0; /* OFDM BB Swing should be less than +3.0dB, which is required by Arthur */ + u8 indexforchannel = 0; /* get_right_chnl_place_for_iqk(p_hal_data->current_channel) */ + u8 power_tracking_type = p_hal_data->rf_power_tracking_type; + u8 xtal_offset_eanble = 0; + s8 thermal_value_temp = 0; + + struct _TXPWRTRACK_CFG c; + + /* 4 1. The following TWO tables decide the final index of OFDM/CCK swing table. */ + u8 *delta_swing_table_idx_tup_a = NULL; + u8 *delta_swing_table_idx_tdown_a = NULL; + u8 *delta_swing_table_idx_tup_b = NULL; + u8 *delta_swing_table_idx_tdown_b = NULL; + /*for 8814 add by Yu Chen*/ + u8 *delta_swing_table_idx_tup_c = NULL; + u8 *delta_swing_table_idx_tdown_c = NULL; + u8 *delta_swing_table_idx_tup_d = NULL; + u8 *delta_swing_table_idx_tdown_d = NULL; + /*for Xtal Offset by James.Tung*/ + s8 *delta_swing_table_xtal_up = NULL; + s8 *delta_swing_table_xtal_down = NULL; + + /* 4 2. Initilization ( 7 steps in total ) */ + + configure_txpower_track(p_dm_odm, &c); + + (*c.get_delta_swing_table)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_a, (u8 **)&delta_swing_table_idx_tdown_a, + (u8 **)&delta_swing_table_idx_tup_b, (u8 **)&delta_swing_table_idx_tdown_b); + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.get_delta_swing_table8814only)(p_dm_odm, (u8 **)&delta_swing_table_idx_tup_c, (u8 **)&delta_swing_table_idx_tdown_c, + (u8 **)&delta_swing_table_idx_tup_d, (u8 **)&delta_swing_table_idx_tdown_d); + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) /*for Xtal Offset*/ + (*c.get_delta_swing_xtal_table)(p_dm_odm, (s8 **)&delta_swing_table_xtal_up, (s8 **)&delta_swing_table_xtal_down); + + p_rf_calibrate_info->txpowertracking_callback_cnt++; /*cosa add for debug*/ + p_rf_calibrate_info->is_txpowertracking_init = true; + + /*p_rf_calibrate_info->txpowertrack_control = p_hal_data->txpowertrack_control; + <Kordan> We should keep updating the control variable according to HalData. + <Kordan> rf_calibrate_info.rega24 will be initialized when ODM HW configuring, but MP configures with para files. */ + if (p_dm_odm->mp_mode == true) + p_rf_calibrate_info->rega24 = 0x090e1317; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("===>odm_txpowertracking_callback_thermal_meter\n p_rf_calibrate_info->bb_swing_idx_cck_base: %d, p_rf_calibrate_info->bb_swing_idx_ofdm_base[A]: %d, p_rf_calibrate_info->default_ofdm_index: %d\n", + p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->bb_swing_idx_ofdm_base[ODM_RF_PATH_A], p_rf_calibrate_info->default_ofdm_index)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("p_rf_calibrate_info->txpowertrack_control=%d, p_hal_data->eeprom_thermal_meter %d\n", p_rf_calibrate_info->txpowertrack_control, p_hal_data->eeprom_thermal_meter)); + thermal_value = (u8)odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, c.thermal_reg_addr, 0xfc00); /* 0x42: RF Reg[15:10] 88E */ + + thermal_value_temp = thermal_value + phydm_get_thermal_offset(p_dm_odm); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("thermal_value_temp(%d) thermal_value(%d) power_time_thermal(%d)\n", thermal_value_temp, thermal_value, phydm_get_thermal_offset(p_dm_odm))); + + if (thermal_value_temp > 63) + thermal_value = 63; + else if (thermal_value_temp < 0) + thermal_value = 0; + else + thermal_value = thermal_value_temp; + + /*add log by zhao he, check c80/c94/c14/ca0 value*/ + if (p_dm_odm->support_ic_type == ODM_RTL8723D) { + regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type == ODM_RTL8710B) { + regc80 = odm_get_bb_reg(p_dm_odm, 0xc80, MASKDWORD); + regcd0 = odm_get_bb_reg(p_dm_odm, 0xcd0, MASKDWORD); + regcd4 = odm_get_bb_reg(p_dm_odm, 0xcd4, MASKDWORD); + regab4 = odm_get_bb_reg(p_dm_odm, 0xab4, 0x000007FF); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc80 = 0x%x 0xcd0 = 0x%x 0xcd4 = 0x%x 0xab4 = 0x%x\n", regc80, regcd0, regcd4, regab4)); + } + + if (!p_rf_calibrate_info->txpowertrack_control) + return; + + if (p_hal_data->eeprom_thermal_meter == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no pg, p_hal_data->eeprom_thermal_meter = 0x%x\n", p_hal_data->eeprom_thermal_meter)); + return; + } + + /*4 3. Initialize ThermalValues of rf_calibrate_info*/ + + if (p_rf_calibrate_info->is_reloadtxpowerindex) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("reload ofdm index for band switch\n")); + + /*4 4. Calculate average thermal meter*/ + + p_rf_calibrate_info->thermal_value_avg[p_rf_calibrate_info->thermal_value_avg_index] = thermal_value; + p_rf_calibrate_info->thermal_value_avg_index++; + if (p_rf_calibrate_info->thermal_value_avg_index == c.average_thermal_num) /*Average times = c.average_thermal_num*/ + p_rf_calibrate_info->thermal_value_avg_index = 0; + + for (i = 0; i < c.average_thermal_num; i++) { + if (p_rf_calibrate_info->thermal_value_avg[i]) { + thermal_value_avg += p_rf_calibrate_info->thermal_value_avg[i]; + thermal_value_avg_count++; + } + } + + if (thermal_value_avg_count) { /* Calculate Average thermal_value after average enough times */ + thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count); + p_rf_calibrate_info->thermal_value_delta = thermal_value - p_hal_data->eeprom_thermal_meter; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal base = 0x%X\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + } + + /* 4 5. Calculate delta, delta_LCK, delta_IQK. */ + + /* "delta" here is used to determine whether thermal value changes or not. */ + delta = (thermal_value > p_rf_calibrate_info->thermal_value) ? (thermal_value - p_rf_calibrate_info->thermal_value) : (p_rf_calibrate_info->thermal_value - thermal_value); + delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); + + if (p_rf_calibrate_info->thermal_value_iqk == 0xff) { /*no PG, use thermal value for IQK*/ + p_rf_calibrate_info->thermal_value_iqk = thermal_value; + delta_IQK = (thermal_value > p_rf_calibrate_info->thermal_value_iqk) ? (thermal_value - p_rf_calibrate_info->thermal_value_iqk) : (p_rf_calibrate_info->thermal_value_iqk - thermal_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use thermal_value for IQK\n")); + } + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + diff_DPK[p] = (s8)thermal_value - (s8)p_rf_calibrate_info->dpk_thermal[p]; + + /*4 6. If necessary, do LCK.*/ + + if (!(p_dm_odm->support_ic_type & ODM_RTL8821)) { /*no PG, do LCK at initial status*/ + if (p_rf_calibrate_info->thermal_value_lck == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); + p_rf_calibrate_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if ((!(p_dm_odm->support_ic_type & ODM_RTL8814A)) && (!(p_dm_odm->support_ic_type & ODM_RTL8822B))) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + } + + delta_LCK = (thermal_value > p_rf_calibrate_info->thermal_value_lck) ? (thermal_value - p_rf_calibrate_info->thermal_value_lck) : (p_rf_calibrate_info->thermal_value_lck - thermal_value); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + + /* Wait sacn to do LCK by RF Jenyu*/ + if (*p_dm_odm->p_is_scan_in_process == false) { + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.threshold_iqk) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= threshold_iqk(%d)\n", delta_LCK, c.threshold_iqk)); + p_rf_calibrate_info->thermal_value_lck = thermal_value; + + /*Use RTLCK, so close power tracking driver LCK*/ + if ((!(p_dm_odm->support_ic_type & ODM_RTL8814A)) && (!(p_dm_odm->support_ic_type & ODM_RTL8822B))) { + if (c.phy_lc_calibrate) + (*c.phy_lc_calibrate)(p_dm_odm); + } + } + } + } + + /*3 7. If necessary, move the index of swing table to adjust Tx power.*/ + + if (delta > 0 && p_rf_calibrate_info->txpowertrack_control) { + /* "delta" here is used to record the absolute value of differrence. */ + delta = thermal_value > p_hal_data->eeprom_thermal_meter ? (thermal_value - p_hal_data->eeprom_thermal_meter) : (p_hal_data->eeprom_thermal_meter - thermal_value); + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + /*4 7.1 The Final Power index = BaseIndex + power_index_offset*/ + + if (thermal_value > p_hal_data->eeprom_thermal_meter) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_b[%d] = %d\n", delta, delta_swing_table_idx_tup_b[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_b[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_b[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_c[%d] = %d\n", delta, delta_swing_table_idx_tup_c[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_c[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_c[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_d[%d] = %d\n", delta, delta_swing_table_idx_tup_d[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_d[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_d[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tup_a[%d] = %d\n", delta, delta_swing_table_idx_tup_a[delta])); + + p_rf_calibrate_info->delta_power_index[p] = delta_swing_table_idx_tup_a[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = delta_swing_table_idx_tup_a[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + /*Save xtal_offset from Xtal table*/ + p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] delta_swing_table_xtal_up[%d] = %d\n", delta, delta_swing_table_xtal_up[delta])); + p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_up[delta]; + + if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset) + xtal_offset_eanble = 0; + else + xtal_offset_eanble = 1; + } + + } else { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + p_rf_calibrate_info->delta_power_index_last[p] = p_rf_calibrate_info->delta_power_index[p]; /*recording poer index offset*/ + + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_b[%d] = %d\n", delta, delta_swing_table_idx_tdown_b[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_b[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_b[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_B] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_c[%d] = %d\n", delta, delta_swing_table_idx_tdown_c[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_c[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_c[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_C] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_d[%d] = %d\n", delta, delta_swing_table_idx_tdown_d[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_d[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_d[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_D] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("delta_swing_table_idx_tdown_a[%d] = %d\n", delta, delta_swing_table_idx_tdown_a[delta])); + p_rf_calibrate_info->delta_power_index[p] = -1 * delta_swing_table_idx_tdown_a[delta]; + p_rf_calibrate_info->absolute_ofdm_swing_idx[p] = -1 * delta_swing_table_idx_tdown_a[delta]; /*Record delta swing for mix mode power tracking*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and p_rf_calibrate_info->absolute_ofdm_swing_idx[ODM_RF_PATH_A] = %d\n", p_rf_calibrate_info->absolute_ofdm_swing_idx[p])); + break; + } + } + /* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8710B)) { + /*Save xtal_offset from Xtal table*/ + p_rf_calibrate_info->xtal_offset_last = p_rf_calibrate_info->xtal_offset; /*recording last Xtal offset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Xtal] delta_swing_table_xtal_down[%d] = %d\n", delta, delta_swing_table_xtal_down[delta])); + p_rf_calibrate_info->xtal_offset = delta_swing_table_xtal_down[delta]; + + if (p_rf_calibrate_info->xtal_offset_last == p_rf_calibrate_info->xtal_offset) + xtal_offset_eanble = 0; + else + xtal_offset_eanble = 1; + } + + } + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n=========================== [path-%d] Calculating power_index_offset===========================\n", p)); + + if (p_rf_calibrate_info->delta_power_index[p] == p_rf_calibrate_info->delta_power_index_last[p]) /*If Thermal value changes but lookup table value still the same*/ + p_rf_calibrate_info->power_index_offset[p] = 0; + else + p_rf_calibrate_info->power_index_offset[p] = p_rf_calibrate_info->delta_power_index[p] - p_rf_calibrate_info->delta_power_index_last[p]; /*Power index diff between 2 times Power Tracking*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[path-%d] power_index_offset(%d) = delta_power_index(%d) - delta_power_index_last(%d)\n", p, p_rf_calibrate_info->power_index_offset[p], p_rf_calibrate_info->delta_power_index[p], p_rf_calibrate_info->delta_power_index_last[p])); + + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] + p_rf_calibrate_info->power_index_offset[p]; + p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->bb_swing_idx_cck_base + p_rf_calibrate_info->power_index_offset[p]; + + p_rf_calibrate_info->bb_swing_idx_cck = p_rf_calibrate_info->CCK_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[p] = p_rf_calibrate_info->OFDM_index[p]; + + /*************Print BB Swing base and index Offset*************/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'CCK' final index(%d) = BaseIndex(%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_cck, p_rf_calibrate_info->bb_swing_idx_cck_base, p_rf_calibrate_info->power_index_offset[p])); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + power_index_offset(%d)\n", p_rf_calibrate_info->bb_swing_idx_ofdm[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p], p_rf_calibrate_info->power_index_offset[p])); + + /*4 7.1 Handle boundary conditions of index.*/ + + if (p_rf_calibrate_info->OFDM_index[p] > c.swing_table_size_ofdm - 1) + p_rf_calibrate_info->OFDM_index[p] = c.swing_table_size_ofdm - 1; + else if (p_rf_calibrate_info->OFDM_index[p] <= OFDM_min_index) + p_rf_calibrate_info->OFDM_index[p] = OFDM_min_index; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n========================================================================================================\n")); + + if (p_rf_calibrate_info->CCK_index > c.swing_table_size_cck - 1) + p_rf_calibrate_info->CCK_index = c.swing_table_size_cck - 1; + else if (p_rf_calibrate_info->CCK_index <= 0) + p_rf_calibrate_info->CCK_index = 0; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF(%d): thermal_value: %d, p_rf_calibrate_info->thermal_value: %d\n", + p_rf_calibrate_info->txpowertrack_control, thermal_value, p_rf_calibrate_info->thermal_value)); + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + p_rf_calibrate_info->power_index_offset[p] = 0; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current index: %d, Swing base index: %d\n", + p_rf_calibrate_info->CCK_index, p_rf_calibrate_info->bb_swing_idx_cck_base)); /*Print Swing base & current*/ + + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current index: %d, Swing base index[%d]: %d\n", + p_rf_calibrate_info->OFDM_index[p], p, p_rf_calibrate_info->bb_swing_idx_ofdm_base[p])); + } + + if ((p_dm_odm->support_ic_type & ODM_RTL8814A)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("power_tracking_type=%d\n", power_tracking_type)); + + if (power_tracking_type == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } else if (power_tracking_type == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(2G) TSSI(5G) MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_2G_TSSI_5G_MODE, p, 0); + } else if (power_tracking_type == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX(5G) TSSI(2G)MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_5G_TSSI_2G_MODE, p, 0); + } else if (power_tracking_type == 3) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, TSSI_MODE, p, 0); + } + p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } else if ((p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_A] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_B] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_C] != 0 || + p_rf_calibrate_info->power_index_offset[ODM_RF_PATH_D] != 0) && + p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + /* 4 7.2 Configure the Swing Table to adjust Tx Power. */ + + p_rf_calibrate_info->is_tx_power_changed = true; /*Always true after Tx Power is adjusted by power tracking.*/ + /* */ + /* 2012/04/23 MH According to Luke's suggestion, we can not write BB digital */ + /* to increase TX power. Otherwise, EVM will be bad. */ + /* */ + /* 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. */ + if (thermal_value > p_rf_calibrate_info->thermal_value) { + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + } + } else if (thermal_value < p_rf_calibrate_info->thermal_value) { /*Low temperature*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d, delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, p_rf_calibrate_info->power_index_offset[p], delta, thermal_value, p_hal_data->eeprom_thermal_meter, p_rf_calibrate_info->thermal_value)); + } + } + + if (thermal_value > p_hal_data->eeprom_thermal_meter) + { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || + p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || + p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || + p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, 0); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + } + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8821 || + p_dm_odm->support_ic_type == ODM_RTL8812 || p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8814A || + p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8822B || + p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8821C || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, MIX_MODE, p, indexforchannel); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + (*c.odm_tx_pwr_track_set_pwr)(p_dm_odm, BBSWING, p, indexforchannel); + } + + } + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->bb_swing_idx_cck; /*Record last time Power Tracking result as base.*/ + for (p = ODM_RF_PATH_A; p < c.rf_path_count; p++) + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->bb_swing_idx_ofdm[p]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("p_rf_calibrate_info->thermal_value = %d thermal_value= %d\n", p_rf_calibrate_info->thermal_value, thermal_value)); + + p_rf_calibrate_info->thermal_value = thermal_value; /*Record last Power Tracking Thermal value*/ + + } + + if (p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {/* JJ ADD 20161014 */ + + if (xtal_offset_eanble != 0 && p_rf_calibrate_info->txpowertrack_control && (p_hal_data->eeprom_thermal_meter != 0xff)) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter Xtal Tracking**********\n")); + + if (thermal_value > p_hal_data->eeprom_thermal_meter) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", thermal_value, p_hal_data->eeprom_thermal_meter)); + (*c.odm_txxtaltrack_set_xtal)(p_dm_odm); + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********End Xtal Tracking**********\n")); + } + + /* Wait sacn to do IQK by RF Jenyu*/ + if (*p_dm_odm->p_is_scan_in_process == false) { + if (!IS_HARDWARE_TYPE_8723B(adapter)) { + /*Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.threshold_iqk) { + p_rf_calibrate_info->thermal_value_iqk = thermal_value; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= threshold_iqk(%d)\n", delta_IQK, c.threshold_iqk)); + if (!p_rf_calibrate_info->is_iqk_in_progress) + (*c.do_iqk)(p_dm_odm, delta_IQK, thermal_value, 8); + } + } + } + if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_A] != 0) { + if (diff_DPK[ODM_RF_PATH_A] >= c.threshold_dpk) { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk)); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.threshold_dpk); + + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xcc4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } + } + if (p_rf_calibrate_info->dpk_thermal[ODM_RF_PATH_B] != 0) { + if (diff_DPK[ODM_RF_PATH_B] >= c.threshold_dpk) { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk)); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.threshold_dpk)) { + s32 value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.threshold_dpk); + + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), value); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } else { + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0xec4, BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10), 0); + odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); + } + } + + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===odm_txpowertracking_callback_thermal_meter\n")); + + p_rf_calibrate_info->tx_powercount = 0; +} + +/* 3============================================================ + * 3 IQ Calibration + * 3============================================================ */ + +u8 odm_get_right_chnl_place_for_iqk(u8 chnl) +{ + u8 channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165 + }; + u8 place = chnl; + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place - 13; + } + } + return 0; + +} + +void +odm_iq_calibrate( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (p_dm_odm->is_linked) { + if ((*p_dm_odm->p_channel != p_dm_odm->pre_channel) && (!*p_dm_odm->p_is_scan_in_process)) { + p_dm_odm->pre_channel = *p_dm_odm->p_channel; + p_dm_odm->linked_interval = 0; + } + + if (p_dm_odm->linked_interval < 3) + p_dm_odm->linked_interval++; + + if (p_dm_odm->linked_interval == 2) { + if (IS_HARDWARE_TYPE_8814A(adapter)) { + } + + + else if (IS_HARDWARE_TYPE_8821C(adapter)) + phy_iq_calibrate_8821c(p_dm_odm, false); + + } + } else + p_dm_odm->linked_interval = 0; +} + +void phydm_rf_init(void *p_dm_void) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + odm_txpowertracking_init(p_dm_odm); + + odm_clear_txpowertracking_state(p_dm_odm); +} + +void phydm_rf_watchdog(void *p_dm_void) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + odm_txpowertracking_check(p_dm_odm); +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ce.h b/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ce.h new file mode 100644 index 000000000000..0ead7f4b5033 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/halphyrf_ce.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_H__ +#define __HAL_PHY_RF_H__ + +#include "phydm_kfree.h" + + + #include "rtl8821c/phydm_iqk_8821c.h" + +#include "phydm_powertracking_ce.h" + +enum spur_cal_method { + PLL_RESET, + AFE_PHASE_SEL +}; + +enum pwrtrack_method { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE, + MIX_2G_TSSI_5G_MODE, + MIX_5G_TSSI_2G_MODE +}; + +typedef void (*func_set_pwr)(void *, enum pwrtrack_method, u8, u8); +typedef void(*func_iqk)(void *, u8, u8, u8); +typedef void (*func_lck)(void *); +typedef void (*func_swing)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void (*func_swing8814only)(void *, u8 **, u8 **, u8 **, u8 **); +typedef void(*func_swing_xtal)(void *, s8 **, s8 **); +typedef void(*func_set_xtal)(void *); + +struct _TXPWRTRACK_CFG { + u8 swing_table_size_cck; + u8 swing_table_size_ofdm; + u8 threshold_iqk; + u8 threshold_dpk; + u8 average_thermal_num; + u8 rf_path_count; + u32 thermal_reg_addr; + func_set_pwr odm_tx_pwr_track_set_pwr; + func_iqk do_iqk; + func_lck phy_lc_calibrate; + func_swing get_delta_swing_table; + func_swing8814only get_delta_swing_table8814only; + func_swing_xtal get_delta_swing_xtal_table; + func_set_xtal odm_txxtaltrack_set_xtal; +}; + +void +configure_txpower_track( + void *p_dm_void, + struct _TXPWRTRACK_CFG *p_config +); + +void +odm_clear_txpowertracking_state( + void *p_dm_void +); + +void +odm_txpowertracking_callback_thermal_meter( + struct _ADAPTER *adapter +); + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + +void +odm_reset_iqk_result( + void *p_dm_void +); +u8 +odm_get_right_chnl_place_for_iqk( + u8 chnl +); + +void phydm_rf_init(void *p_dm_void); +void phydm_rf_watchdog(void *p_dm_void); + +#endif /* #ifndef __HAL_PHY_RF_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/mp_precomp.h b/drivers/staging/rtl8821ce/hal/phydm/mp_precomp.h new file mode 100644 index 000000000000..ba4b4c21290e --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/mp_precomp.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm.c b/drivers/staging/rtl8821ce/hal/phydm/phydm.c new file mode 100644 index 000000000000..c1d7a88e36a4 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm.c @@ -0,0 +1,2147 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +const u16 db_invert_table[12][8] = { + { 1, 1, 1, 2, 2, 2, 2, 3}, + { 3, 3, 4, 4, 4, 5, 6, 6}, + { 7, 8, 9, 10, 11, 13, 14, 16}, + { 18, 20, 22, 25, 28, 32, 35, 40}, + { 45, 50, 56, 63, 71, 79, 89, 100}, + { 112, 126, 141, 158, 178, 200, 224, 251}, + { 282, 316, 355, 398, 447, 501, 562, 631}, + { 708, 794, 891, 1000, 1122, 1259, 1413, 1585}, + { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, + { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, + { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, + { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} +}; + +/* ************************************************************ + * Local Function predefine. + * ************************************************************ */ + +/* START------------COMMON INFO RELATED--------------- */ + +void +odm_global_adapter_check( + void +); + +/* move to odm_PowerTacking.h by YuChen */ + +void +odm_update_power_training_state( + struct PHY_DM_STRUCT *p_dm_odm +); + +/* ************************************************************ + * 3 Export Interface + * ************************************************************ */ + +/*Y = 10*log(X)*/ +s32 +odm_pwdb_conversion( + s32 X, + u32 total_bit, + u32 decimal_bit +) +{ + s32 Y, integer = 0, decimal = 0; + u32 i; + + if (X == 0) + X = 1; /* log2(x), x can't be 0 */ + + for (i = (total_bit - 1); i > 0; i--) { + if (X & BIT(i)) { + integer = i; + if (i > 0) + decimal = (X & BIT(i - 1)) ? 2 : 0; /* decimal is 0.5dB*3=1.5dB~=2dB */ + break; + } + } + + Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */ + + return Y; +} + +s32 +odm_sign_conversion( + s32 value, + u32 total_bit +) +{ + if (value & BIT(total_bit - 1)) + value -= BIT(total_bit); + return value; +} + +void +phydm_seq_sorting( + void *p_dm_void, + u32 *p_value, + u32 *rank_idx, + u32 *p_idx_out, + u8 seq_length +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 i = 0, j = 0; + u32 tmp_a, tmp_b; + u32 tmp_idx_a, tmp_idx_b; + + for (i = 0; i < seq_length; i++) { + rank_idx[i] = i; + /**/ + } + + for (i = 0; i < (seq_length - 1); i++) { + + for (j = 0; j < (seq_length - 1 - i); j++) { + + tmp_a = p_value[j]; + tmp_b = p_value[j + 1]; + + tmp_idx_a = rank_idx[j]; + tmp_idx_b = rank_idx[j + 1]; + + if (tmp_a < tmp_b) { + p_value[j] = tmp_b; + p_value[j + 1] = tmp_a; + + rank_idx[j] = tmp_idx_b; + rank_idx[j + 1] = tmp_idx_a; + } + } + } + + for (i = 0; i < seq_length; i++) { + p_idx_out[rank_idx[i]] = i + 1; + /**/ + } + +} + +void +odm_init_mp_driver_status( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + + /* Update information every period */ + p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode; +} + +void +odm_update_mp_driver_status( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + + /* Update information erery period */ + p_dm_odm->mp_mode = (boolean)adapter->registrypriv.mp_mode; +} + +void +phydm_init_trx_antenna_setting( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + /*#if (RTL8814A_SUPPORT == 1)*/ + + if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) { + u8 rx_ant = 0, tx_ant = 0; + + rx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); + tx_ant = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_TX_PATH, p_dm_odm), ODM_BIT(BB_TX_PATH, p_dm_odm)); + p_dm_odm->tx_ant_status = (tx_ant & 0xf); + p_dm_odm->rx_ant_status = (rx_ant & 0xf); + } else if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B)) {/* JJ ADD 20161014 */ + p_dm_odm->tx_ant_status = 0x1; + p_dm_odm->rx_ant_status = 0x1; + + } + /*#endif*/ +} + +void +phydm_traffic_load_decision( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _sw_antenna_switch_ *p_dm_swat_table = &p_dm_odm->dm_swat_table; + + /*---TP & Trafic-load calculation---*/ + + if (p_dm_odm->last_tx_ok_cnt > (*(p_dm_odm->p_num_tx_bytes_unicast))) + p_dm_odm->last_tx_ok_cnt = (*(p_dm_odm->p_num_tx_bytes_unicast)); + + if (p_dm_odm->last_rx_ok_cnt > (*(p_dm_odm->p_num_rx_bytes_unicast))) + p_dm_odm->last_rx_ok_cnt = (*(p_dm_odm->p_num_rx_bytes_unicast)); + + p_dm_odm->cur_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast) - p_dm_odm->last_tx_ok_cnt; + p_dm_odm->cur_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast) - p_dm_odm->last_rx_ok_cnt; + p_dm_odm->last_tx_ok_cnt = *(p_dm_odm->p_num_tx_bytes_unicast); + p_dm_odm->last_rx_ok_cnt = *(p_dm_odm->p_num_rx_bytes_unicast); + + p_dm_odm->tx_tp = ((p_dm_odm->tx_tp) >> 1) + (u32)(((p_dm_odm->cur_tx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ + p_dm_odm->rx_tp = ((p_dm_odm->rx_tp) >> 1) + (u32)(((p_dm_odm->cur_rx_ok_cnt) >> 18) >> 1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/ + p_dm_odm->total_tp = p_dm_odm->tx_tp + p_dm_odm->rx_tp; + + if (p_dm_odm->total_tp == 0) + p_dm_odm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD; + else + p_dm_odm->consecutive_idlel_time = 0; + /* + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n", + p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->last_tx_ok_cnt, p_dm_odm->last_rx_ok_cnt)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("tx_tp = %d, rx_tp = %d\n", + p_dm_odm->tx_tp, p_dm_odm->rx_tp)); + */ + + p_dm_odm->pre_traffic_load = p_dm_odm->traffic_load; + + if (p_dm_odm->cur_tx_ok_cnt > 1875000 || p_dm_odm->cur_rx_ok_cnt > 1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/ + + p_dm_odm->traffic_load = TRAFFIC_HIGH; + /**/ + } else if (p_dm_odm->cur_tx_ok_cnt > 500000 || p_dm_odm->cur_rx_ok_cnt > 500000) { /*( 0.5M * 8bit ) / 2sec = 2M bits /sec )*/ + + p_dm_odm->traffic_load = TRAFFIC_MID; + /**/ + } else if (p_dm_odm->cur_tx_ok_cnt > 100000 || p_dm_odm->cur_rx_ok_cnt > 100000) { /*( 0.1M * 8bit ) / 2sec = 0.4M bits /sec )*/ + + p_dm_odm->traffic_load = TRAFFIC_LOW; + /**/ + } else { + + p_dm_odm->traffic_load = TRAFFIC_ULTRA_LOW; + /**/ + } +} + +void +phydm_config_ofdm_tx_path( + struct PHY_DM_STRUCT *p_dm_odm, + u32 path +) +{ + u8 ofdm_tx_path = 0x33; + + +} + +void +phydm_config_ofdm_rx_path( + struct PHY_DM_STRUCT *p_dm_odm, + u32 path +) +{ + u8 ofdm_rx_path = 0; + + if (p_dm_odm->support_ic_type & (ODM_RTL8192E)) { + } +} + +void +phydm_config_cck_rx_antenna_init( + struct PHY_DM_STRUCT *p_dm_odm +) +{ +} + +void +phydm_config_cck_rx_path( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 path_div_en +) +{ + u8 path_div_select = 0; + u8 cck_1_path = 0, cck_2_path = 0; + +} + +void +phydm_config_trx_path( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 pre_support_ability; + u32 used = *_used; + u32 out_len = *_out_len; + + /* CCK */ + if (dm_value[0] == 0) { + + if (dm_value[1] == 1) { /*TX*/ + if (dm_value[2] == 1) + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x8); + else if (dm_value[2] == 2) + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0x4); + else if (dm_value[2] == 3) + odm_set_bb_reg(p_dm_odm, 0xa04, 0xf0000000, 0xc); + } else if (dm_value[1] == 2) { /*RX*/ + + phydm_config_cck_rx_antenna_init(p_dm_odm); + + if (dm_value[2] == 1) + phydm_config_cck_rx_path(p_dm_odm, PHYDM_A, CCA_PATHDIV_DISABLE); + else if (dm_value[2] == 2) + phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); + else if (dm_value[2] == 3) { + if (dm_value[3] == 1) /*enable path diversity*/ + phydm_config_cck_rx_path(p_dm_odm, PHYDM_AB, CCA_PATHDIV_ENABLE); + else + phydm_config_cck_rx_path(p_dm_odm, PHYDM_B, CCA_PATHDIV_DISABLE); + } + } + } + /* OFDM */ + else if (dm_value[0] == 1) { + + if (dm_value[1] == 1) { /*TX*/ + phydm_config_ofdm_tx_path(p_dm_odm, dm_value[2]); + /**/ + } else if (dm_value[1] == 2) { /*RX*/ + phydm_config_ofdm_rx_path(p_dm_odm, dm_value[2]); + /**/ + } + } + + PHYDM_SNPRINTF((output + used, out_len - used, "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n", + (dm_value[0] == 1) ? "OFDM" : "CCK", + (dm_value[1] == 1) ? "TX" : "RX", + (dm_value[2] & 0x1) ? "A" : "", + (dm_value[2] & 0x2) ? "B" : "", + (dm_value[2] & 0x4) ? "C" : "", + (dm_value[2] & 0x8) ? "D" : "" + )); + +} + +void +phydm_init_cck_setting( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value_824, value_82c; + + p_dm_odm->is_cck_high_power = (boolean) odm_get_bb_reg(p_dm_odm, ODM_REG(CCK_RPT_FORMAT, p_dm_odm), ODM_BIT(CCK_RPT_FORMAT, p_dm_odm)); + +/* JJ ADD 20161014 */ +/* JJ ADD 20161014 */ + if (p_dm_odm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8710B)) + p_dm_odm->cck_new_agc = odm_get_bb_reg(p_dm_odm, 0xa9c, BIT(17)) ? true : false; /*1: new agc 0: old agc*/ + else + p_dm_odm->cck_new_agc = false; + +} + +void +phydm_dynamicsoftmletting( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + + u32 ret_val; + + +} + +void +phydm_init_soft_ml_setting( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + if (p_dm_odm->mp_mode == false) { + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(p_dm_odm, 0x19a8, BIT(31)|BIT(30)|BIT(29)|BIT(28), 0xd); + } +} + +void +phydm_init_hw_info_by_rfe( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + phydm_init_hw_info_by_rfe_type_8821c(p_dm_odm); +} + +void +odm_common_info_self_init( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + phydm_init_cck_setting(p_dm_odm); + p_dm_odm->rf_path_rx_enable = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(BB_RX_PATH, p_dm_odm), ODM_BIT(BB_RX_PATH, p_dm_odm)); + odm_init_mp_driver_status(p_dm_odm); + phydm_init_trx_antenna_setting(p_dm_odm); + phydm_init_soft_ml_setting(p_dm_odm); + + p_dm_odm->phydm_period = PHYDM_WATCH_DOG_PERIOD; + p_dm_odm->phydm_sys_up_time = 0; + + if (p_dm_odm->support_ic_type & ODM_IC_1SS) + p_dm_odm->num_rf_path = 1; + else if (p_dm_odm->support_ic_type & ODM_IC_2SS) + p_dm_odm->num_rf_path = 2; + else if (p_dm_odm->support_ic_type & ODM_IC_3SS) + p_dm_odm->num_rf_path = 3; + else if (p_dm_odm->support_ic_type & ODM_IC_4SS) + p_dm_odm->num_rf_path = 4; + + p_dm_odm->tx_rate = 0xFF; + + p_dm_odm->number_linked_client = 0; + p_dm_odm->pre_number_linked_client = 0; + p_dm_odm->number_active_client = 0; + p_dm_odm->pre_number_active_client = 0; + + p_dm_odm->last_tx_ok_cnt = 0; + p_dm_odm->last_rx_ok_cnt = 0; + p_dm_odm->tx_tp = 0; + p_dm_odm->rx_tp = 0; + p_dm_odm->total_tp = 0; + p_dm_odm->traffic_load = TRAFFIC_LOW; + + p_dm_odm->nbi_set_result = 0; + p_dm_odm->is_init_hw_info_by_rfe = false; + p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; + +} + +void +odm_common_info_self_update( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u8 entry_cnt = 0, num_active_client = 0; + u32 i, one_entry_macid = 0, ma_rx_tp = 0; + struct sta_info *p_entry; + + /* THis variable cannot be used because it is wrong*/ + if (*(p_dm_odm->p_band_width) == ODM_BW40M) { + if (*(p_dm_odm->p_sec_ch_offset) == 1) + p_dm_odm->control_channel = *(p_dm_odm->p_channel) - 2; + else if (*(p_dm_odm->p_sec_ch_offset) == 2) + p_dm_odm->control_channel = *(p_dm_odm->p_channel) + 2; + } else + p_dm_odm->control_channel = *(p_dm_odm->p_channel); + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + entry_cnt++; + if (entry_cnt == 1) + one_entry_macid = i; + } + } + + if (entry_cnt == 1) { + p_dm_odm->is_one_entry_only = true; + p_dm_odm->one_entry_macid = one_entry_macid; + } else + p_dm_odm->is_one_entry_only = false; + + p_dm_odm->pre_number_linked_client = p_dm_odm->number_linked_client; + p_dm_odm->pre_number_active_client = p_dm_odm->number_active_client; + + p_dm_odm->number_linked_client = entry_cnt; + p_dm_odm->number_active_client = num_active_client; + + /* Update MP driver status*/ + odm_update_mp_driver_status(p_dm_odm); + + /*Traffic load information update*/ + phydm_traffic_load_decision(p_dm_odm); + + p_dm_odm->phydm_sys_up_time += p_dm_odm->phydm_period; +} + +void +odm_common_info_self_reset( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt = 0; +} + +void * +phydm_get_structure( + struct PHY_DM_STRUCT *p_dm_odm, + u8 structure_type +) + +{ + void *p_struct = NULL; + switch (structure_type) { + case PHYDM_FALSEALMCNT: + p_struct = &(p_dm_odm->false_alm_cnt); + break; + + case PHYDM_CFOTRACK: + p_struct = &(p_dm_odm->dm_cfo_track); + break; + + case PHYDM_ADAPTIVITY: + p_struct = &(p_dm_odm->adaptivity); + break; + + case PHYDM_DFS: + p_struct = &(p_dm_odm->dfs); + break; + + default: + break; + } + + return p_struct; +} + +void +odm_hw_setting( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + + + +} +void +phydm_supportability_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 support_ability = 0; + if (p_dm_odm->support_ic_type != ODM_RTL8821C) + return; + + switch (p_dm_odm->support_ic_type) { + + /*---------------N Series--------------------*/ + case ODM_RTL8188E: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_RF_TX_PWR_TRACK | + ODM_RF_RX_GAIN_TRACK | + ODM_RF_CALIBRATION | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_BB_PRIMARY_CCA; + break; + + case ODM_RTL8192E: + support_ability |= + ODM_BB_DIG | + ODM_RF_TX_PWR_TRACK | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CFO_TRACKING | + /* ODM_BB_PWR_TRAIN |*/ + ODM_BB_NHM_CNT | + ODM_BB_PRIMARY_CCA; + break; + + case ODM_RTL8723B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_RF_TX_PWR_TRACK | + ODM_RF_RX_GAIN_TRACK | + ODM_RF_CALIBRATION | + ODM_BB_CFO_TRACKING | + /* ODM_BB_PWR_TRAIN |*/ + ODM_BB_NHM_CNT; + break; + + case ODM_RTL8703B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_CFO_TRACKING | + /* ODM_BB_PWR_TRAIN | */ + ODM_BB_NHM_CNT | + ODM_RF_TX_PWR_TRACK | + /* ODM_RF_RX_GAIN_TRACK | */ + ODM_RF_CALIBRATION; + break; + + case ODM_RTL8723D: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_CFO_TRACKING | + /* ODM_BB_PWR_TRAIN | */ + ODM_BB_NHM_CNT | + ODM_RF_TX_PWR_TRACK; + /* ODM_RF_RX_GAIN_TRACK | */ + /* ODM_RF_CALIBRATION | */ + break; +/* JJ ADD 20161014 */ + case ODM_RTL8710B: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_CFO_TRACKING | + /* ODM_BB_PWR_TRAIN | */ + ODM_BB_NHM_CNT | + ODM_RF_TX_PWR_TRACK; + /* ODM_RF_RX_GAIN_TRACK | */ + /* ODM_RF_CALIBRATION | */ + break; + + case ODM_RTL8188F: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_CCK_PD | + ODM_BB_CFO_TRACKING | + ODM_BB_NHM_CNT | + ODM_RF_TX_PWR_TRACK | + ODM_RF_CALIBRATION; + break; + + /*---------------AC Series-------------------*/ + + case ODM_RTL8812: + case ODM_RTL8821: + case ODM_RTL8881A: + support_ability |= + ODM_BB_DIG | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_RA_MASK | + ODM_RF_TX_PWR_TRACK | + ODM_BB_CFO_TRACKING | + /* ODM_BB_PWR_TRAIN |*/ + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_NHM_CNT; + break; + + case ODM_RTL8814B: + case ODM_RTL8814A: + support_ability |= + ODM_BB_DIG | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_RA_MASK | + ODM_RF_TX_PWR_TRACK | + ODM_BB_CCK_PD | + ODM_BB_CFO_TRACKING | + ODM_BB_DYNAMIC_TXPWR | + ODM_BB_NHM_CNT; + break; + + case ODM_RTL8822B: + support_ability |= + ODM_BB_DIG | + ODM_BB_FA_CNT | + ODM_BB_CCK_PD | + ODM_BB_CFO_TRACKING | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_RSSI_MONITOR | + ODM_BB_RA_MASK | + ODM_RF_TX_PWR_TRACK; + break; + + case ODM_RTL8821C: + support_ability |= + ODM_BB_DIG | + ODM_BB_RA_MASK | + ODM_BB_CCK_PD | + ODM_BB_FA_CNT | + ODM_BB_RSSI_MONITOR | + ODM_BB_RATE_ADAPTIVE | + ODM_RF_TX_PWR_TRACK | + ODM_BB_CFO_TRACKING; /* | + * ODM_BB_DYNAMIC_TXPWR | + * ODM_BB_NHM_CNT;*/ + break; + + default: + support_ability |= + ODM_BB_DIG | + ODM_BB_FA_CNT | + ODM_BB_CCK_PD | + ODM_BB_CFO_TRACKING | + ODM_BB_RATE_ADAPTIVE | + ODM_BB_RSSI_MONITOR | + ODM_BB_RA_MASK | + ODM_RF_TX_PWR_TRACK; + + dbg_print("[Warning] Supportability Init Warning !!!\n"); + break; + + } + + if (*(p_dm_odm->p_enable_antdiv)) + support_ability |= ODM_BB_ANT_DIV; + + if (*(p_dm_odm->p_enable_adaptivity)) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to Enabled!!!\n")); + + support_ability |= ODM_BB_ADAPTIVITY; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM adaptivity is set to disnabled!!!\n")); + /**/ + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHYDM support_ability = ((0x%x))\n", support_ability)); + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_ABILITY, support_ability); +} + +/* + * 2011/09/21 MH Add to describe different team necessary resource allocate?? + * */ +void +odm_dm_init( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + phydm_supportability_init(p_dm_odm); + odm_common_info_self_init(p_dm_odm); + odm_dig_init(p_dm_odm); + phydm_nhm_counter_statistics_init(p_dm_odm); + phydm_adaptivity_init(p_dm_odm); + phydm_ra_info_init(p_dm_odm); + odm_rate_adaptive_mask_init(p_dm_odm); + odm_cfo_tracking_init(p_dm_odm); + odm_rssi_monitor_init(p_dm_odm); + phydm_rf_init(p_dm_odm); + odm_txpowertracking_init(p_dm_odm); + + + odm_antenna_diversity_init(p_dm_odm); + odm_auto_channel_select_init(p_dm_odm); + odm_path_diversity_init(p_dm_odm); + phydm_init_ra_info(p_dm_odm); + adc_smp_init(p_dm_odm); + + phydm_beamforming_init(p_dm_odm); + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_dynamic_bb_power_saving_init(p_dm_odm); + + phydm_psd_init(p_dm_odm); +} + +void +odm_dm_reset( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + odm_ant_div_reset(p_dm_odm); + phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value); +} + +void +phydm_support_ability_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 pre_support_ability; + u32 used = *_used; + u32 out_len = *_out_len; + + pre_support_ability = p_dm_odm->support_ability ; + PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "[Supportability] PhyDM Selection\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((p_dm_odm->support_ability & ODM_BB_DIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((p_dm_odm->support_ability & ODM_BB_RA_MASK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_TXPWR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((p_dm_odm->support_ability & ODM_BB_FA_CNT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((p_dm_odm->support_ability & ODM_BB_CCK_PD) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((p_dm_odm->support_ability & ODM_BB_ANT_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((p_dm_odm->support_ability & ODM_BB_PWR_TRAIN) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((p_dm_odm->support_ability & ODM_BB_RATE_ADAPTIVE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((p_dm_odm->support_ability & ODM_BB_PATH_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))ADAPTIVITY\n", ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))struct _CFO_TRACKING_\n", ((p_dm_odm->support_ability & ODM_BB_CFO_TRACKING) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))NHM_CNT\n", ((p_dm_odm->support_ability & ODM_BB_NHM_CNT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))PRIMARY_CCA\n", ((p_dm_odm->support_ability & ODM_BB_PRIMARY_CCA) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))TXBF\n", ((p_dm_odm->support_ability & ODM_BB_TXBF) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))DYNAMIC_ARFR\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((p_dm_odm->support_ability & ODM_MAC_EDCA_TURBO) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))DYNAMIC_RX_PATH\n", ((p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))RX_GAIN_TRACK\n", ((p_dm_odm->support_ability & ODM_RF_RX_GAIN_TRACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))RF_CALIBRATION\n", ((p_dm_odm->support_ability & ODM_RF_CALIBRATION) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + } + /* + else if(dm_value[0] == 101) + { + p_dm_odm->support_ability = 0 ; + dbg_print("Disable all support_ability components\n"); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all support_ability components")); + } + */ + else { + + if (dm_value[1] == 1) { /* enable */ + p_dm_odm->support_ability |= BIT(dm_value[0]) ; + if (BIT(dm_value[0]) & ODM_BB_PATH_DIV) + odm_path_diversity_init(p_dm_odm); + } else if (dm_value[1] == 2) /* disable */ + p_dm_odm->support_ability &= ~(BIT(dm_value[0])) ; + else { + /* dbg_print("\n[Warning!!!] 1:enable, 2:disable \n\n"); */ + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + } + PHYDM_SNPRINTF((output + used, out_len - used, "pre-support_ability = 0x%x\n", pre_support_ability)); + PHYDM_SNPRINTF((output + used, out_len - used, "Curr-support_ability = 0x%x\n", p_dm_odm->support_ability)); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); +} + +void +phydm_watchdog_mp( + struct PHY_DM_STRUCT *p_dm_odm +) +{ +} +/* + * 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. + * You can not add any dummy function here, be care, you can only use DM structure + * to perform any new ODM_DM. + * */ +void +odm_dm_watchdog( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + odm_common_info_self_update(p_dm_odm); + phydm_basic_dbg_message(p_dm_odm); + phydm_receiver_blocking(p_dm_odm); + odm_hw_setting(p_dm_odm); + + odm_false_alarm_counter_statistics(p_dm_odm); + phydm_noisy_detection(p_dm_odm); + + odm_rssi_monitor_check(p_dm_odm); + + if (*(p_dm_odm->p_is_power_saving) == true) { + odm_dig_by_rssi_lps(p_dm_odm); + phydm_adaptivity(p_dm_odm); + odm_antenna_diversity(p_dm_odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); + return; + } + + phydm_check_adaptivity(p_dm_odm); + odm_update_power_training_state(p_dm_odm); + odm_DIG(p_dm_odm); + phydm_adaptivity(p_dm_odm); + odm_cck_packet_detection_thresh(p_dm_odm); + + phydm_ra_info_watchdog(p_dm_odm); + odm_path_diversity(p_dm_odm); + odm_cfo_tracking(p_dm_odm); + odm_antenna_diversity(p_dm_odm); + + phydm_beamforming_watchdog(p_dm_odm); + + phydm_rf_watchdog(p_dm_odm); + + odm_common_info_self_reset(p_dm_odm); +} + +/* + * Init /.. Fixed HW value. Only init time. + * */ +void +odm_cmn_info_init( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u32 value +) +{ + /* */ + /* This section is used for init value */ + /* */ + switch (cmn_info) { + /* */ + /* Fixed ODM value. */ + /* */ + case ODM_CMNINFO_ABILITY: + p_dm_odm->support_ability = (u32)value; + break; + + case ODM_CMNINFO_RF_TYPE: + p_dm_odm->rf_type = (u8)value; + break; + + case ODM_CMNINFO_PLATFORM: + p_dm_odm->support_platform = (u8)value; + break; + + case ODM_CMNINFO_INTERFACE: + p_dm_odm->support_interface = (u8)value; + break; + + case ODM_CMNINFO_MP_TEST_CHIP: + p_dm_odm->is_mp_chip = (u8)value; + break; + + case ODM_CMNINFO_IC_TYPE: + p_dm_odm->support_ic_type = value; + break; + + case ODM_CMNINFO_CUT_VER: + p_dm_odm->cut_version = (u8)value; + break; + + case ODM_CMNINFO_FAB_VER: + p_dm_odm->fab_version = (u8)value; + break; + + case ODM_CMNINFO_RFE_TYPE: + p_dm_odm->rfe_type = (u8)value; + phydm_init_hw_info_by_rfe(p_dm_odm); + break; + + case ODM_CMNINFO_DPK_EN: + p_dm_odm->dpk_en = (u1Byte)value; + break; + case ODM_CMNINFO_RF_ANTENNA_TYPE: + p_dm_odm->ant_div_type = (u8)value; + break; + + case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH: + p_dm_odm->with_extenal_ant_switch = (u8)value; + break; + + case ODM_CMNINFO_BE_FIX_TX_ANT: + p_dm_odm->dm_fat_table.b_fix_tx_ant = (u8)value; + break; + + case ODM_CMNINFO_BOARD_TYPE: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->board_type = (u8)value; + break; + + case ODM_CMNINFO_PACKAGE_TYPE: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->package_type = (u8)value; + break; + + case ODM_CMNINFO_EXT_LNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_lna = (u8)value; + break; + + case ODM_CMNINFO_5G_EXT_LNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_lna_5g = (u8)value; + break; + + case ODM_CMNINFO_EXT_PA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_pa = (u8)value; + break; + + case ODM_CMNINFO_5G_EXT_PA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_pa_5g = (u8)value; + break; + + case ODM_CMNINFO_GPA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_gpa = (u16)value; + break; + + case ODM_CMNINFO_APA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_apa = (u16)value; + break; + + case ODM_CMNINFO_GLNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_glna = (u16)value; + break; + + case ODM_CMNINFO_ALNA: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->type_alna = (u16)value; + break; + + case ODM_CMNINFO_EXT_TRSW: + if (!p_dm_odm->is_init_hw_info_by_rfe) + p_dm_odm->ext_trsw = (u8)value; + break; + case ODM_CMNINFO_EXT_LNA_GAIN: + p_dm_odm->ext_lna_gain = (u8)value; + break; + case ODM_CMNINFO_PATCH_ID: + p_dm_odm->patch_id = (u8)value; + break; + case ODM_CMNINFO_BINHCT_TEST: + p_dm_odm->is_in_hct_test = (boolean)value; + break; + case ODM_CMNINFO_BWIFI_TEST: + p_dm_odm->wifi_test = (u8)value; + break; + case ODM_CMNINFO_SMART_CONCURRENT: + p_dm_odm->is_dual_mac_smart_concurrent = (boolean)value; + break; + case ODM_CMNINFO_DOMAIN_CODE_2G: + p_dm_odm->odm_regulation_2_4g = (u8)value; + break; + case ODM_CMNINFO_DOMAIN_CODE_5G: + p_dm_odm->odm_regulation_5g = (u8)value; + break; + case ODM_CMNINFO_CONFIG_BB_RF: + p_dm_odm->config_bbrf = (boolean)value; + break; + case ODM_CMNINFO_IQKFWOFFLOAD: + p_dm_odm->iqk_fw_offload = (u8)value; + break; + case ODM_CMNINFO_IQKPAOFF: + p_dm_odm->rf_calibrate_info.is_iqk_pa_off = (boolean)value; + break; + case ODM_CMNINFO_REGRFKFREEENABLE: + p_dm_odm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value; + break; + case ODM_CMNINFO_RFKFREEENABLE: + p_dm_odm->rf_calibrate_info.rf_kfree_enable = (u8)value; + break; + case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE: + p_dm_odm->normal_rx_path = (u8)value; + break; + case ODM_CMNINFO_EFUSE0X3D8: + p_dm_odm->efuse0x3d8 = (u8)value; + break; + case ODM_CMNINFO_EFUSE0X3D7: + p_dm_odm->efuse0x3d7 = (u8)value; + break; + case ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING: + p_dm_odm->soft_ap_special_setting = (u32)value; + break; + case ODM_CMNINFO_HALMAC_ABILITY: + p_dm_odm->halmac_ability = (u32)value; + break; + /* To remove the compiler warning, must add an empty default statement to handle the other values. */ + default: + /* do nothing */ + break; + + } + +} + +void +odm_cmn_info_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + void *p_value +) +{ + /* */ + /* Hook call by reference pointer. */ + /* */ + switch (cmn_info) { + /* */ + /* Dynamic call by reference pointer. */ + /* */ + case ODM_CMNINFO_MAC_PHY_MODE: + p_dm_odm->p_mac_phy_mode = (u8 *)p_value; + break; + + case ODM_CMNINFO_TX_UNI: + p_dm_odm->p_num_tx_bytes_unicast = (u64 *)p_value; + break; + + case ODM_CMNINFO_RX_UNI: + p_dm_odm->p_num_rx_bytes_unicast = (u64 *)p_value; + break; + + case ODM_CMNINFO_WM_MODE: + p_dm_odm->p_wireless_mode = (u8 *)p_value; + break; + + case ODM_CMNINFO_BAND: + p_dm_odm->p_band_type = (u8 *)p_value; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + p_dm_odm->p_sec_ch_offset = (u8 *)p_value; + break; + + case ODM_CMNINFO_SEC_MODE: + p_dm_odm->p_security = (u8 *)p_value; + break; + + case ODM_CMNINFO_BW: + p_dm_odm->p_band_width = (u8 *)p_value; + break; + + case ODM_CMNINFO_CHNL: + p_dm_odm->p_channel = (u8 *)p_value; + break; + + case ODM_CMNINFO_DMSP_GET_VALUE: + p_dm_odm->p_is_get_value_from_other_mac = (boolean *)p_value; + break; + + case ODM_CMNINFO_BUDDY_ADAPTOR: + p_dm_odm->p_buddy_adapter = (struct _ADAPTER **)p_value; + break; + + case ODM_CMNINFO_DMSP_IS_MASTER: + p_dm_odm->p_is_master_of_dmsp = (boolean *)p_value; + break; + + case ODM_CMNINFO_SCAN: + p_dm_odm->p_is_scan_in_process = (boolean *)p_value; + break; + + case ODM_CMNINFO_POWER_SAVING: + p_dm_odm->p_is_power_saving = (boolean *)p_value; + break; + + case ODM_CMNINFO_ONE_PATH_CCA: + p_dm_odm->p_one_path_cca = (u8 *)p_value; + break; + + case ODM_CMNINFO_DRV_STOP: + p_dm_odm->p_is_driver_stopped = (boolean *)p_value; + break; + + case ODM_CMNINFO_PNP_IN: + p_dm_odm->p_is_driver_is_going_to_pnp_set_power_sleep = (boolean *)p_value; + break; + + case ODM_CMNINFO_INIT_ON: + p_dm_odm->pinit_adpt_in_progress = (boolean *)p_value; + break; + + case ODM_CMNINFO_ANT_TEST: + p_dm_odm->p_antenna_test = (u8 *)p_value; + break; + + case ODM_CMNINFO_NET_CLOSED: + p_dm_odm->p_is_net_closed = (boolean *)p_value; + break; + + case ODM_CMNINFO_FORCED_RATE: + p_dm_odm->p_forced_data_rate = (u16 *)p_value; + break; + case ODM_CMNINFO_ANT_DIV: + p_dm_odm->p_enable_antdiv = (u8 *)p_value; + break; + case ODM_CMNINFO_ADAPTIVITY: + p_dm_odm->p_enable_adaptivity = (u8 *)p_value; + break; + case ODM_CMNINFO_FORCED_IGI_LB: + p_dm_odm->pu1_forced_igi_lb = (u8 *)p_value; + break; + + case ODM_CMNINFO_P2P_LINK: + p_dm_odm->dm_dig_table.is_p2p_in_process = (u8 *)p_value; + break; + + case ODM_CMNINFO_IS1ANTENNA: + p_dm_odm->p_is_1_antenna = (boolean *)p_value; + break; + + case ODM_CMNINFO_RFDEFAULTPATH: + p_dm_odm->p_rf_default_path = (u8 *)p_value; + break; + + case ODM_CMNINFO_FCS_MODE: + p_dm_odm->p_is_fcs_mode_enable = (boolean *)p_value; + break; + /*add by YuChen for beamforming PhyDM*/ + case ODM_CMNINFO_HUBUSBMODE: + p_dm_odm->hub_usb_mode = (u8 *)p_value; + break; + case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: + p_dm_odm->p_is_fw_dw_rsvd_page_in_progress = (boolean *)p_value; + break; + case ODM_CMNINFO_TX_TP: + p_dm_odm->p_current_tx_tp = (u32 *)p_value; + break; + case ODM_CMNINFO_RX_TP: + p_dm_odm->p_current_rx_tp = (u32 *)p_value; + break; + case ODM_CMNINFO_SOUNDING_SEQ: + p_dm_odm->p_sounding_seq = (u8 *)p_value; + break; + case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC: + p_dm_odm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)p_value; + break; + case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA: + p_dm_odm->dm_fat_table.p_default_s0_s1 = (u8 *)p_value; + break; + case ODM_CMNINFO_SOFT_AP_MODE: + p_dm_odm->p_soft_ap_mode = (u32 *)p_value; + break; + default: + /*do nothing*/ + break; + + } + +} + +void +odm_cmn_info_ptr_array_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u16 index, + void *p_value +) +{ + /*Hook call by reference pointer.*/ + switch (cmn_info) { + /*Dynamic call by reference pointer. */ + case ODM_CMNINFO_STA_STATUS: + p_dm_odm->p_odm_sta_info[index] = (struct sta_info *)p_value; + + if (IS_STA_VALID(p_dm_odm->p_odm_sta_info[index])) + p_dm_odm->platform2phydm_macid_table[((struct sta_info *)p_value)->mac_id] = index; + + break; + /* To remove the compiler warning, must add an empty default statement to handle the other values. */ + default: + /* do nothing */ + break; + } + +} + +/* + * Update band/CHannel/.. The values are dynamic but non-per-packet. + * */ +void +odm_cmn_info_update( + struct PHY_DM_STRUCT *p_dm_odm, + u32 cmn_info, + u64 value +) +{ + /* */ + /* This init variable may be changed in run time. */ + /* */ + switch (cmn_info) { + case ODM_CMNINFO_LINK_IN_PROGRESS: + p_dm_odm->is_link_in_process = (boolean)value; + break; + + case ODM_CMNINFO_ABILITY: + p_dm_odm->support_ability = (u32)value; + break; + + case ODM_CMNINFO_RF_TYPE: + p_dm_odm->rf_type = (u8)value; + break; + + case ODM_CMNINFO_WIFI_DIRECT: + p_dm_odm->is_wifi_direct = (boolean)value; + break; + + case ODM_CMNINFO_WIFI_DISPLAY: + p_dm_odm->is_wifi_display = (boolean)value; + break; + + case ODM_CMNINFO_LINK: + p_dm_odm->is_linked = (boolean)value; + break; + + case ODM_CMNINFO_CMW500LINK: + p_dm_odm->bLinkedcmw500 = (boolean)value; + break; + + case ODM_CMNINFO_LPSPG: + p_dm_odm->is_in_lps_pg = (boolean)value; + break; + + case ODM_CMNINFO_STATION_STATE: + p_dm_odm->bsta_state = (boolean)value; + break; + + case ODM_CMNINFO_RSSI_MIN: + p_dm_odm->rssi_min = (u8)value; + break; + + case ODM_CMNINFO_DBG_COMP: + p_dm_odm->debug_components = (u32)value; + break; + + case ODM_CMNINFO_DBG_LEVEL: + p_dm_odm->debug_level = (u32)value; + break; + case ODM_CMNINFO_RA_THRESHOLD_HIGH: + p_dm_odm->rate_adaptive.high_rssi_thresh = (u8)value; + break; + + case ODM_CMNINFO_RA_THRESHOLD_LOW: + p_dm_odm->rate_adaptive.low_rssi_thresh = (u8)value; + break; + /* The following is for BT HS mode and BT coexist mechanism. */ + case ODM_CMNINFO_BT_ENABLED: + p_dm_odm->is_bt_enabled = (boolean)value; + break; + + case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: + p_dm_odm->is_bt_connect_process = (boolean)value; + break; + + case ODM_CMNINFO_BT_HS_RSSI: + p_dm_odm->bt_hs_rssi = (u8)value; + break; + + case ODM_CMNINFO_BT_OPERATION: + p_dm_odm->is_bt_hs_operation = (boolean)value; + break; + + case ODM_CMNINFO_BT_LIMITED_DIG: + p_dm_odm->is_bt_limited_dig = (boolean)value; + break; + + case ODM_CMNINFO_BT_DIG: + p_dm_odm->bt_hs_dig_val = (u8)value; + break; + + case ODM_CMNINFO_BT_BUSY: + p_dm_odm->is_bt_busy = (boolean)value; + break; + + case ODM_CMNINFO_BT_DISABLE_EDCA: + p_dm_odm->is_bt_disable_edca_turbo = (boolean)value; + break; + + case ODM_CMNINFO_AP_TOTAL_NUM: + p_dm_odm->ap_total_num = (u8)value; + break; + + case ODM_CMNINFO_POWER_TRAINING: + p_dm_odm->is_disable_power_training = (boolean)value; + break; + + default: + /* do nothing */ + break; + } + +} + +u32 +phydm_cmn_info_query( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_info_query_e info_type +) +{ + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + + switch (info_type) { + case PHYDM_INFO_FA_OFDM: + return false_alm_cnt->cnt_ofdm_fail; + + case PHYDM_INFO_FA_CCK: + return false_alm_cnt->cnt_cck_fail; + + case PHYDM_INFO_FA_TOTAL: + return false_alm_cnt->cnt_all; + + case PHYDM_INFO_CCA_OFDM: + return false_alm_cnt->cnt_ofdm_cca; + + case PHYDM_INFO_CCA_CCK: + return false_alm_cnt->cnt_cck_cca; + + case PHYDM_INFO_CCA_ALL: + return false_alm_cnt->cnt_cca_all; + + case PHYDM_INFO_CRC32_OK_VHT: + return false_alm_cnt->cnt_vht_crc32_ok; + + case PHYDM_INFO_CRC32_OK_HT: + return false_alm_cnt->cnt_ht_crc32_ok; + + case PHYDM_INFO_CRC32_OK_LEGACY: + return false_alm_cnt->cnt_ofdm_crc32_ok; + + case PHYDM_INFO_CRC32_OK_CCK: + return false_alm_cnt->cnt_cck_crc32_ok; + + case PHYDM_INFO_CRC32_ERROR_VHT: + return false_alm_cnt->cnt_vht_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_HT: + return false_alm_cnt->cnt_ht_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_LEGACY: + return false_alm_cnt->cnt_ofdm_crc32_error; + + case PHYDM_INFO_CRC32_ERROR_CCK: + return false_alm_cnt->cnt_cck_crc32_error; + + case PHYDM_INFO_EDCCA_FLAG: + return false_alm_cnt->edcca_flag; + + case PHYDM_INFO_OFDM_ENABLE: + return false_alm_cnt->ofdm_block_enable; + + case PHYDM_INFO_CCK_ENABLE: + return false_alm_cnt->cck_block_enable; + + case PHYDM_INFO_DBG_PORT_0: + return false_alm_cnt->dbg_port0; + + default: + return 0xffffffff; + + } +} + +/* 3============================================================ + * 3 Tx Power Tracking + * 3============================================================ */ + +/* need to ODM CE Platform + * move to here for ANT detection mechanism using */ + +u32 +odm_convert_to_db( + u32 value) +{ + u8 i; + u8 j; + u32 dB; + + value = value & 0xFFFF; + + for (i = 0; i < 12; i++) { + if (value <= db_invert_table[i][7]) + break; + } + + if (i >= 12) { + return 96; /* maximum 96 dB */ + } + + for (j = 0; j < 8; j++) { + if (value <= db_invert_table[i][j]) + break; + } + + dB = (i << 3) + j + 1; + + return dB; +} + +u32 +odm_convert_to_linear( + u32 value) +{ + u8 i; + u8 j; + u32 linear; + + /* 1dB~96dB */ + + value = value & 0xFF; + + i = (u8)((value - 1) >> 3); + j = (u8)(value - 1) - (i << 3); + + linear = db_invert_table[i][j]; + + return linear; +} + +void +odm_update_power_training_state( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u32 score = 0; + + if (!(p_dm_odm->support_ability & ODM_BB_PWR_TRAIN)) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state()============>\n")); + p_dm_odm->is_change_state = false; + + /* Debug command */ + if (p_dm_odm->force_power_training_state) { + if (p_dm_odm->force_power_training_state == 1 && !p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = true; + } else if (p_dm_odm->force_power_training_state == 2 && p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = false; + } + + p_dm_odm->PT_score = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): force_power_training_state = %d\n", + p_dm_odm->force_power_training_state)); + return; + } + + if (!p_dm_odm->is_linked) + return; + + /* First connect */ + if ((p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false)) { + p_dm_odm->PT_score = 0; + p_dm_odm->is_change_state = true; + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): First Connect\n")); + return; + } + + /* Compute score */ + if (p_dm_odm->nhm_cnt_0 >= 215) + score = 2; + else if (p_dm_odm->nhm_cnt_0 >= 190) + score = 1; /* unknow state */ + else { + u32 rx_pkt_cnt; + + rx_pkt_cnt = (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm) + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck); + + if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) && (false_alm_cnt->cnt_cca_all >= rx_pkt_cnt)) { + if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <= false_alm_cnt->cnt_cca_all) + score = 0; + else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <= false_alm_cnt->cnt_cca_all) + score = 1; + else + score = 2; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): rx_pkt_cnt = %d, cnt_cca_all = %d\n", + rx_pkt_cnt, false_alm_cnt->cnt_cca_all)); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n", + (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm), (u32)(p_dm_odm->phy_dbg_info.num_qry_phy_status_cck))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): nhm_cnt_0 = %d, score = %d\n", + p_dm_odm->nhm_cnt_0, score)); + + /* smoothing */ + p_dm_odm->PT_score = (score << 4) + (p_dm_odm->PT_score >> 1) + (p_dm_odm->PT_score >> 2); + score = (p_dm_odm->PT_score + 32) >> 6; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): PT_score = %d, score after smoothing = %d\n", + p_dm_odm->PT_score, score)); + + /* mode decision */ + if (score == 2) { + if (p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Enable Power Training\n")); + } else if (score == 0) { + if (!p_dm_odm->is_disable_power_training) { + p_dm_odm->is_change_state = true; + p_dm_odm->is_disable_power_training = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Change state\n")); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_update_power_training_state(): Disable Power Training\n")); + } + + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm = 0; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck = 0; +} + +void +phydm_noisy_detection( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 total_fa_cnt, total_cca_cnt; + u32 score = 0, i, score_smooth; + + total_cca_cnt = p_dm_odm->false_alm_cnt.cnt_cca_all; + total_fa_cnt = p_dm_odm->false_alm_cnt.cnt_all; + + for (i = 0; i <= 16; i++) { + if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) { + score = 16 - i; + break; + } + } + + /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */ + p_dm_odm->noisy_decision_smooth = (p_dm_odm->noisy_decision_smooth >> 1) + (score << 2); + + /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */ + score_smooth = (total_cca_cnt >= 300) ? ((p_dm_odm->noisy_decision_smooth + 3) >> 3) : 0; + + p_dm_odm->noisy_decision = (score_smooth >= 3) ? 1 : 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, + ("[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, p_dm_odm->noisy_decision=%d\n", + total_cca_cnt, total_fa_cnt, p_dm_odm->noisy_decision_smooth, score, score_smooth, p_dm_odm->noisy_decision)); + +} + +void +phydm_csi_mask_enable( + void *p_dm_void, + u32 enable +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 reg_value = 0; + + reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0xD2C, BIT(28), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0xD2C[28] = ((0x%x))\n", reg_value)); + + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x874, BIT(0), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable CSI Mask: Reg 0x874[0] = ((0x%x))\n", reg_value)); + } + +} + +void +phydm_clean_all_csi_mask( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0xD40, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0xD44, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0xD48, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0xD4c, MASKDWORD, 0); + + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x880, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x884, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x888, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x88c, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x890, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x894, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x898, MASKDWORD, 0); + odm_set_bb_reg(p_dm_odm, 0x89c, MASKDWORD, 0); + } +} + +void +phydm_set_csi_mask_reg( + void *p_dm_void, + u32 tone_idx_tmp, + u8 tone_direction +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 byte_offset, bit_offset; + u32 target_reg; + u8 reg_tmp_value; + u32 tone_num = 64; + u32 tone_num_shift = 0; + u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0; + + /* calculate real tone idx*/ + if ((tone_idx_tmp % 10) >= 5) + tone_idx_tmp += 10; + + tone_idx_tmp = (tone_idx_tmp / 10); + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + tone_num = 64; + csi_mask_reg_p = 0xD40; + csi_mask_reg_n = 0xD48; + + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + tone_num = 128; + csi_mask_reg_p = 0x880; + csi_mask_reg_n = 0x890; + } + + if (tone_direction == FREQ_POSITIVE) { + + if (tone_idx_tmp >= (tone_num - 1)) + tone_idx_tmp = (tone_num - 1); + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_p + byte_offset; + + } else { + tone_num_shift = tone_num; + + if (tone_idx_tmp >= tone_num) + tone_idx_tmp = tone_num; + + tone_idx_tmp = tone_num - tone_idx_tmp; + + byte_offset = (u8)(tone_idx_tmp >> 3); + bit_offset = (u8)(tone_idx_tmp & 0x7); + target_reg = csi_mask_reg_n + byte_offset; + } + + reg_tmp_value = odm_read_1byte(p_dm_odm, target_reg); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Pre Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); + reg_tmp_value |= BIT(bit_offset); + odm_write_1byte(p_dm_odm, target_reg, reg_tmp_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("New Mask tone idx[%d]: Reg0x%x = ((0x%x))\n", (tone_idx_tmp + tone_num_shift), target_reg, reg_tmp_value)); +} + +void +phydm_set_nbi_reg( + void *p_dm_void, + u32 tone_idx_tmp, + u32 bw +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 nbi_table_128[NBI_TABLE_SIZE_128] = {25, 55, 85, 115, 135, 155, 185, 205, 225, 245, /*1~10*/ /*tone_idx X 10*/ + 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/ + 485, 505, 525, 555, 585, 615, 635 + }; /*21~27*/ + + u32 nbi_table_256[NBI_TABLE_SIZE_256] = { 25, 55, 85, 115, 135, 155, 175, 195, 225, 245, /*1~10*/ + 265, 285, 305, 325, 345, 365, 385, 405, 425, 445, /*11~20*/ + 465, 485, 505, 525, 545, 565, 585, 605, 625, 645, /*21~30*/ + 665, 695, 715, 735, 755, 775, 795, 815, 835, 855, /*31~40*/ + 875, 895, 915, 935, 955, 975, 995, 1015, 1035, 1055, /*41~50*/ + 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275 + }; /*51~59*/ + + u32 reg_idx = 0; + u32 i; + u8 nbi_table_idx = FFT_128_TYPE; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + + nbi_table_idx = FFT_128_TYPE; + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_1_SERIES) + + nbi_table_idx = FFT_256_TYPE; + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_2_SERIES) { + + if (bw == 80) + nbi_table_idx = FFT_256_TYPE; + else /*20M, 40M*/ + nbi_table_idx = FFT_128_TYPE; + } + + if (nbi_table_idx == FFT_128_TYPE) { + + for (i = 0; i < NBI_TABLE_SIZE_128; i++) { + if (tone_idx_tmp < nbi_table_128[i]) { + reg_idx = i + 1; + break; + } + } + + } else if (nbi_table_idx == FFT_256_TYPE) { + + for (i = 0; i < NBI_TABLE_SIZE_256; i++) { + if (tone_idx_tmp < nbi_table_256[i]) { + reg_idx = i + 1; + break; + } + } + } + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, reg_idx); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0xC40[28:24] = ((0x%x))\n", reg_idx)); + /**/ + } else { + odm_set_bb_reg(p_dm_odm, 0x87c, 0xfc000, reg_idx); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Set tone idx: Reg0x87C[19:14] = ((0x%x))\n", reg_idx)); + /**/ + } +} + +void +phydm_nbi_enable( + void *p_dm_void, + u32 enable +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 reg_value = 0; + + reg_value = (enable == NBI_ENABLE) ? 1 : 0; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0xc40, BIT(9), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value)); + + } else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x87c, BIT(13), reg_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value)); + } +} + +u8 +phydm_calculate_fc( + void *p_dm_void, + u32 channel, + u32 bw, + u32 second_ch, + u32 *fc_in +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 fc = *fc_in; + u32 start_ch_per_40m[NUM_START_CH_40M] = {36, 44, 52, 60, 100, 108, 116, 124, 132, 140, 149, 157, 165, 173}; + u32 start_ch_per_80m[NUM_START_CH_80M] = {36, 52, 100, 116, 132, 149, 165}; + u32 *p_start_ch = &(start_ch_per_40m[0]); + u32 num_start_channel = NUM_START_CH_40M; + u32 channel_offset = 0; + u32 i; + + /*2.4G*/ + if (channel <= 14 && channel > 0) { + + if (bw == 80) + return SET_ERROR; + + fc = 2412 + (channel - 1) * 5; + + if (bw == 40 && (second_ch == PHYDM_ABOVE)) { + + if (channel >= 10) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); + return SET_ERROR; + } + fc += 10; + } else if (bw == 40 && (second_ch == PHYDM_BELOW)) { + + if (channel <= 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)), Scnd_CH = ((%d)) Error setting\n", channel, second_ch)); + return SET_ERROR; + } + fc -= 10; + } + } + /*5G*/ + else if (channel >= 36 && channel <= 177) { + + if (bw != 20) { + + if (bw == 40) { + num_start_channel = NUM_START_CH_40M; + p_start_ch = &(start_ch_per_40m[0]); + channel_offset = CH_OFFSET_40M; + } else if (bw == 80) { + num_start_channel = NUM_START_CH_80M; + p_start_ch = &(start_ch_per_80m[0]); + channel_offset = CH_OFFSET_80M; + } + + for (i = 0; i < num_start_channel; i++) { + + if (channel < p_start_ch[i + 1]) { + channel = p_start_ch[i] + channel_offset; + break; + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Mod_CH = ((%d))\n", channel)); + } + + fc = 5180 + (channel - 36) * 5; + + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("CH = ((%d)) Error setting\n", channel)); + return SET_ERROR; + } + + *fc_in = fc; + + return SET_SUCCESS; +} + +u8 +phydm_calculate_intf_distance( + void *p_dm_void, + u32 bw, + u32 fc, + u32 f_interference, + u32 *p_tone_idx_tmp_in +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 bw_up, bw_low; + u32 int_distance; + u32 tone_idx_tmp; + u8 set_result = SET_NO_NEED; + + bw_up = fc + bw / 2; + bw_low = fc - bw / 2; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low, fc, bw_up, f_interference)); + + if ((f_interference >= bw_low) && (f_interference <= bw_up)) { + + int_distance = (fc >= f_interference) ? (fc - f_interference) : (f_interference - fc); + tone_idx_tmp = (int_distance << 5); /* =10*(int_distance /0.3125) */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n", int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10))); + *p_tone_idx_tmp_in = tone_idx_tmp; + set_result = SET_SUCCESS; + } + + return set_result; + +} + +u8 +phydm_csi_mask_setting( + void *p_dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 fc; + u32 int_distance; + u8 tone_direction; + u32 tone_idx_tmp; + u8 set_result = SET_SUCCESS; + + if (enable == CSI_MASK_DISABLE) { + set_result = SET_SUCCESS; + phydm_clean_all_csi_mask(p_dm_odm); + + } else { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); + + /*calculate fc*/ + if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) + set_result = SET_ERROR; + + else { + /*calculate interference distance*/ + if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { + + tone_direction = (f_interference >= fc) ? FREQ_POSITIVE : FREQ_NEGATIVE; + phydm_set_csi_mask_reg(p_dm_odm, tone_idx_tmp, tone_direction); + set_result = SET_SUCCESS; + } else + set_result = SET_NO_NEED; + } + } + + if (set_result == SET_SUCCESS) + phydm_csi_mask_enable(p_dm_odm, enable); + else + phydm_csi_mask_enable(p_dm_odm, CSI_MASK_DISABLE); + + return set_result; +} + +u8 +phydm_nbi_setting( + void *p_dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 fc; + u32 int_distance; + u32 tone_idx_tmp; + u8 set_result = SET_SUCCESS; + u32 bw_max = 40; + + if (enable == NBI_DISABLE) + set_result = SET_SUCCESS; + + else { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : (second_ch == PHYDM_ABOVE) ? "H" : "L"))); + + /*calculate fc*/ + if (phydm_calculate_fc(p_dm_odm, channel, bw, second_ch, &fc) == SET_ERROR) + set_result = SET_ERROR; + + else { + /*calculate interference distance*/ + if (phydm_calculate_intf_distance(p_dm_odm, bw, fc, f_interference, &tone_idx_tmp) == SET_SUCCESS) { + + phydm_set_nbi_reg(p_dm_odm, tone_idx_tmp, bw); + set_result = SET_SUCCESS; + } else + set_result = SET_NO_NEED; + } + } + + if (set_result == SET_SUCCESS) + phydm_nbi_enable(p_dm_odm, enable); + else + phydm_nbi_enable(p_dm_odm, NBI_DISABLE); + + return set_result; +} + +void +phydm_api_debug( + void *p_dm_void, + u32 function_map, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 used = *_used; + u32 out_len = *_out_len; + u32 channel = dm_value[1]; + u32 bw = dm_value[2]; + u32 f_interference = dm_value[3]; + u32 second_ch = dm_value[4]; + u8 set_result = 0; + + /*PHYDM_API_NBI*/ + /*-------------------------------------------------------------------------------------------------------------------------------*/ + if (function_map == PHYDM_API_NBI) { + + if (dm_value[0] == 100) { + + PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-NBI] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); + return; + + } else if (dm_value[0] == NBI_ENABLE) { + + PHYDM_SNPRINTF((output + used, out_len - used, "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, ((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "Don't care" : ((second_ch == PHYDM_ABOVE) ? "H" : "L"))); + set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, bw, f_interference, second_ch); + + } else if (dm_value[0] == NBI_DISABLE) { + + PHYDM_SNPRINTF((output + used, out_len - used, "[Disable NBI]\n")); + set_result = phydm_nbi_setting(p_dm_odm, NBI_DISABLE, channel, bw, f_interference, second_ch); + + } else + + set_result = SET_ERROR; + PHYDM_SNPRINTF((output + used, out_len - used, "[NBI set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); + + } + + /*PHYDM_CSI_MASK*/ + /*-------------------------------------------------------------------------------------------------------------------------------*/ + else if (function_map == PHYDM_API_CSI_MASK) { + + if (dm_value[0] == 100) { + + PHYDM_SNPRINTF((output + used, out_len - used, "[HELP-CSI MASK] EN(on=1, off=2) CH BW(20/40/80) f_intf(Mhz) Scnd_CH(L=1, H=2)\n")); + return; + + } else if (dm_value[0] == CSI_MASK_ENABLE) { + + PHYDM_SNPRINTF((output + used, out_len - used, "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n", + channel, bw, f_interference, (channel > 14) ? "Don't care" : (((second_ch == PHYDM_DONT_CARE) || (bw == 20) || (channel > 14)) ? "H" : "L"))); + set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_ENABLE, channel, bw, f_interference, second_ch); + + } else if (dm_value[0] == CSI_MASK_DISABLE) { + + PHYDM_SNPRINTF((output + used, out_len - used, "[Disable CSI MASK]\n")); + set_result = phydm_csi_mask_setting(p_dm_odm, CSI_MASK_DISABLE, channel, bw, f_interference, second_ch); + + } else + + set_result = SET_ERROR; + PHYDM_SNPRINTF((output + used, out_len - used, "[CSI MASK set result: %s]\n", (set_result == SET_SUCCESS) ? "Success" : ((set_result == SET_NO_NEED) ? "No need" : "Error"))); + } +} + +void +phydm_receiver_blocking( + void *p_dm_void +) +{ +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm.h b/drivers/staging/rtl8821ce/hal/phydm/phydm.h new file mode 100644 index 000000000000..f5e22c0f4068 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm.h @@ -0,0 +1,1036 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ +#include "phydm_pre_define.h" +#include "phydm_dig.h" +#include "phydm_pathdiv.h" +#include "phydm_antdiv.h" +#include "phydm_dynamicbbpowersaving.h" +#include "phydm_rainfo.h" +#include "phydm_cfotracking.h" +#include "phydm_acs.h" +#include "phydm_adaptivity.h" +#include "phydm_iqk.h" +#include "phydm_dfs.h" +#include "phydm_ccx.h" + +#include "phydm_adc_sampling.h" +#include "phydm_dynamic_rx_path.h" +#include "phydm_psd.h" + +#include "phydm_beamforming.h" + +#include "phydm_noisemonitor.h" +#include "halphyrf_ce.h" + +/*============================================================*/ +/*Definition */ +/*============================================================*/ + +/* Traffic load decision */ +#define TRAFFIC_ULTRA_LOW 1 +#define TRAFFIC_LOW 2 +#define TRAFFIC_MID 3 +#define TRAFFIC_HIGH 4 + +#define NONE 0 + +/*NBI API------------------------------------*/ +#define NBI_ENABLE 1 +#define NBI_DISABLE 2 + +#define NBI_TABLE_SIZE_128 27 +#define NBI_TABLE_SIZE_256 59 + +#define NUM_START_CH_80M 7 +#define NUM_START_CH_40M 14 + +#define CH_OFFSET_40M 2 +#define CH_OFFSET_80M 6 + +/*CSI MASK API------------------------------------*/ +#define CSI_MASK_ENABLE 1 +#define CSI_MASK_DISABLE 2 + +/*------------------------------------------------*/ + +#define FFT_128_TYPE 1 +#define FFT_256_TYPE 2 + +#define SET_SUCCESS 1 +#define SET_ERROR 2 +#define SET_NO_NEED 3 + +#define FREQ_POSITIVE 1 +#define FREQ_NEGATIVE 2 + +#define MAX_2(_x_, _y_) (((_x_)>(_y_))? (_x_) : (_y_)) +#define MIN_2(_x_, _y_) (((_x_)<(_y_))? (_x_) : (_y_)) + +#define PHYDM_WATCH_DOG_PERIOD 2 + +/*============================================================*/ +/*structure and define*/ +/*============================================================*/ + +/*2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.*/ +/*We need to remove to other position???*/ + +struct rtl8192cd_priv { + u8 temp; + }; + +struct _dynamic_primary_cca { + u8 pri_cca_flag; + u8 intf_flag; + u8 intf_type; + u8 dup_rts_flag; + u8 monitor_flag; + u8 CH_offset; + u8 MF_state; +}; + +#define dm_type_by_fw 0 +#define dm_type_by_driver 1 + +/*Declare for common info*/ + +#define IQK_THRESHOLD 8 +#define DPK_THRESHOLD 4 + +struct _odm_phy_status_info_ { + /* */ + /* Be care, if you want to add any element please insert between */ + /* rx_pwdb_all & signal_strength. */ + /* */ + u8 rx_pwdb_all; + u8 signal_quality; /* in 0-100 index. */ + s8 rx_mimo_signal_quality[4]; /* per-path's EVM translate to 0~100% */ + u8 rx_mimo_evm_dbm[4]; /* per-path's original EVM (dbm) */ + u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ + s16 cfo_short[4]; /* per-path's cfo_short */ + s16 cfo_tail[4]; /* per-path's cfo_tail */ + s8 rx_power; /* in dBm Translate from PWdB */ + s8 recv_signal_power; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u8 bt_rx_rssi_percentage; + u8 signal_strength; /* in 0-100 index. */ + s8 rx_pwr[4]; /* per-path's pwdb */ + s8 rx_snr[4]; /* per-path's SNR */ + /* s8 BB_Backup[13]; backup reg. */ + u8 rx_count:2; /* RX path counter---*/ + u8 band_width:2; + u8 rxsc:4; /* sub-channel---*/ + u8 bt_coex_pwr_adjust; + u8 channel; /* channel number---*/ + boolean is_mu_packet; /* is MU packet or not---*/ + boolean is_beamformed; /* BF packet---*/ +}; + +struct _odm_per_pkt_info_ { + u8 data_rate; + u8 station_id; + boolean is_packet_match_bssid; + boolean is_packet_to_self; + boolean is_packet_beacon; + boolean is_to_self; + u8 ppdu_cnt; +}; + +struct _odm_phy_dbg_info_ { + /*ODM Write,debug info*/ + s8 rx_snr_db[4]; + u32 num_qry_phy_status; + u32 num_qry_phy_status_cck; + u32 num_qry_phy_status_ofdm; + u32 num_qry_mu_pkt; + u32 num_qry_bf_pkt; + u32 num_qry_mu_vht_pkt[40]; + u32 num_qry_vht_pkt[40]; + boolean is_ldpc_pkt; + boolean is_stbc_pkt; + u8 num_of_ppdu[4]; + u8 gid_num[4]; + u8 num_qry_beacon_pkt; + /* Others */ + s32 rx_evm[4]; + +}; + +/*2011/20/20 MH For MP driver RT_WLAN_STA = struct sta_info*/ +/*Please declare below ODM relative info in your STA info structure.*/ + +struct _ODM_STA_INFO { + /*Driver Write*/ + boolean is_used; /*record the sta status link or not?*/ + u8 iot_peer; /*Enum value. HT_IOT_PEER_E*/ + + /*ODM Write*/ + /*PHY_STATUS_INFO*/ + u8 rssi_path[4]; + u8 rssi_ave; + u8 RXEVM[4]; + u8 RXSNR[4]; + +}; + +enum odm_cmninfo_e { + /*Fixed value*/ + /*-----------HOOK BEFORE REG INIT-----------*/ + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, + ODM_CMNINFO_INTERFACE, + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, + ODM_CMNINFO_CUT_VER, + ODM_CMNINFO_FAB_VER, + ODM_CMNINFO_RF_TYPE, + ODM_CMNINFO_RFE_TYPE, + ODM_CMNINFO_DPK_EN, + ODM_CMNINFO_BOARD_TYPE, + ODM_CMNINFO_PACKAGE_TYPE, + ODM_CMNINFO_EXT_LNA, + ODM_CMNINFO_5G_EXT_LNA, + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_5G_EXT_PA, + ODM_CMNINFO_GPA, + ODM_CMNINFO_APA, + ODM_CMNINFO_GLNA, + ODM_CMNINFO_ALNA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_EXT_LNA_GAIN, + ODM_CMNINFO_PATCH_ID, + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + ODM_CMNINFO_CONFIG_BB_RF, + ODM_CMNINFO_DOMAIN_CODE_2G, + ODM_CMNINFO_DOMAIN_CODE_5G, + ODM_CMNINFO_IQKFWOFFLOAD, + ODM_CMNINFO_IQKPAOFF, + ODM_CMNINFO_HUBUSBMODE, + ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, + ODM_CMNINFO_TX_TP, + ODM_CMNINFO_RX_TP, + ODM_CMNINFO_SOUNDING_SEQ, + ODM_CMNINFO_REGRFKFREEENABLE, + ODM_CMNINFO_RFKFREEENABLE, + ODM_CMNINFO_NORMAL_RX_PATH_CHANGE, + ODM_CMNINFO_EFUSE0X3D8, + ODM_CMNINFO_EFUSE0X3D7, + ODM_CMNINFO_SOFT_AP_SPECIAL_SETTING, + ODM_CMNINFO_HALMAC_ABILITY, + /*-----------HOOK BEFORE REG INIT-----------*/ + + /*Dynamic value:*/ + + /*--------- POINTER REFERENCE-----------*/ + ODM_CMNINFO_MAC_PHY_MODE, + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, + ODM_CMNINFO_BAND, + ODM_CMNINFO_SEC_CHNL_OFFSET, + ODM_CMNINFO_SEC_MODE, + ODM_CMNINFO_BW, + ODM_CMNINFO_CHNL, + ODM_CMNINFO_FORCED_RATE, + ODM_CMNINFO_ANT_DIV, + ODM_CMNINFO_ADAPTIVITY, + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + ODM_CMNINFO_FORCED_IGI_LB, + ODM_CMNINFO_P2P_LINK, + ODM_CMNINFO_FCS_MODE, + ODM_CMNINFO_IS1ANTENNA, + ODM_CMNINFO_RFDEFAULTPATH, + ODM_CMNINFO_DFS_MASTER_ENABLE, + ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC, + ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA, + ODM_CMNINFO_SOFT_AP_MODE, + /*--------- POINTER REFERENCE-----------*/ + + /*------------CALL BY VALUE-------------*/ + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK_IN_PROGRESS, + ODM_CMNINFO_LINK, + ODM_CMNINFO_CMW500LINK, + ODM_CMNINFO_LPSPG, + ODM_CMNINFO_STATION_STATE, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_DBG_COMP, + ODM_CMNINFO_DBG_LEVEL, + ODM_CMNINFO_RA_THRESHOLD_HIGH, + ODM_CMNINFO_RA_THRESHOLD_LOW, + ODM_CMNINFO_RF_ANTENNA_TYPE, + ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH, + ODM_CMNINFO_BE_FIX_TX_ANT, + ODM_CMNINFO_BT_ENABLED, + ODM_CMNINFO_BT_HS_CONNECT_PROCESS, + ODM_CMNINFO_BT_HS_RSSI, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_LIMITED_DIG, + ODM_CMNINFO_BT_DIG, + ODM_CMNINFO_BT_BUSY, + ODM_CMNINFO_BT_DISABLE_EDCA, + ODM_CMNINFO_AP_TOTAL_NUM, + ODM_CMNINFO_POWER_TRAINING, + ODM_CMNINFO_DFS_REGION_DOMAIN, + /*------------CALL BY VALUE-------------*/ + + /*Dynamic ptr array hook itms.*/ + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_MAX, + +}; + +enum phydm_info_query_e { + PHYDM_INFO_FA_OFDM, + PHYDM_INFO_FA_CCK, + PHYDM_INFO_FA_TOTAL, + PHYDM_INFO_CCA_OFDM, + PHYDM_INFO_CCA_CCK, + PHYDM_INFO_CCA_ALL, + PHYDM_INFO_CRC32_OK_VHT, + PHYDM_INFO_CRC32_OK_HT, + PHYDM_INFO_CRC32_OK_LEGACY, + PHYDM_INFO_CRC32_OK_CCK, + PHYDM_INFO_CRC32_ERROR_VHT, + PHYDM_INFO_CRC32_ERROR_HT, + PHYDM_INFO_CRC32_ERROR_LEGACY, + PHYDM_INFO_CRC32_ERROR_CCK, + PHYDM_INFO_EDCCA_FLAG, + PHYDM_INFO_OFDM_ENABLE, + PHYDM_INFO_CCK_ENABLE, + PHYDM_INFO_DBG_PORT_0 +}; + +enum phydm_api_e { + + PHYDM_API_NBI = 1, + PHYDM_API_CSI_MASK, + +}; + +/*2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY*/ +enum odm_ability_e { + + /*BB ODM section BIT 0-19*/ + ODM_BB_DIG = BIT(0), + ODM_BB_RA_MASK = BIT(1), + ODM_BB_DYNAMIC_TXPWR = BIT(2), + ODM_BB_FA_CNT = BIT(3), + ODM_BB_RSSI_MONITOR = BIT(4), + ODM_BB_CCK_PD = BIT(5), + ODM_BB_ANT_DIV = BIT(6), + ODM_BB_PWR_TRAIN = BIT(8), + ODM_BB_RATE_ADAPTIVE = BIT(9), + ODM_BB_PATH_DIV = BIT(10), + ODM_BB_ADAPTIVITY = BIT(13), + ODM_BB_CFO_TRACKING = BIT(14), + ODM_BB_NHM_CNT = BIT(15), + ODM_BB_PRIMARY_CCA = BIT(16), + ODM_BB_TXBF = BIT(17), + ODM_BB_DYNAMIC_ARFR = BIT(18), + + ODM_MAC_EDCA_TURBO = BIT(20), + ODM_BB_DYNAMIC_RX_PATH = BIT(21), + + /*RF ODM section BIT 24-31*/ + ODM_RF_TX_PWR_TRACK = BIT(24), + ODM_RF_RX_GAIN_TRACK = BIT(25), + ODM_RF_CALIBRATION = BIT(26), + +}; + +enum odm_halmac_ability { + ODM_PHY_PARAM_OFFLOAD = BIT(0) +}; + +/*ODM_CMNINFO_ONE_PATH_CCA*/ +enum odm_cca_path_e { + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}; + +enum cca_pathdiv_en_e { + CCA_PATHDIV_DISABLE = 0, + CCA_PATHDIV_ENABLE = 1, + +}; + +enum phy_reg_pg_type { + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +}; + +/*2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.*/ + +struct PHY_DM_STRUCT +{ + /*Add for different team use temporarily*/ + struct _ADAPTER *adapter; /*For CE/NIC team*/ + struct rtl8192cd_priv *priv; /*For AP/ADSL team*/ + /*WHen you use adapter or priv pointer, you must make sure the pointer is ready.*/ + boolean odm_ready; + struct rtl8192cd_priv fake_priv; + + enum phy_reg_pg_type phy_reg_pg_value_type; + u8 phy_reg_pg_version; + + u32 debug_components; + u32 fw_debug_components; + u32 debug_level; + + u32 num_qry_phy_status_all; /*CCK + OFDM*/ + u32 last_num_qry_phy_status_all; + u32 rx_pwdb_ave; + boolean MPDIG_2G; /*off MPDIG*/ + u8 times_2g; + boolean is_init_hw_info_by_rfe; + + /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + boolean is_cck_high_power; + u8 rf_path_rx_enable; + u8 control_channel; + /*------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------*/ + + /* 1 COMMON INFORMATION */ + + /*Init value*/ + /*-----------HOOK BEFORE REG INIT-----------*/ + /*ODM Platform info AP/ADSL/CE/MP = 1/2/3/4*/ + u8 support_platform; + /* ODM Platform info WIN/AP/CE = 1/2/3 */ + u8 normal_rx_path; + /*ODM Support Ability DIG/RATR/TX_PWR_TRACK/ �K�K = 1/2/3/�K*/ + u32 support_ability; + /*ODM PCIE/USB/SDIO = 1/2/3*/ + u8 support_interface; + /*ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...*/ + u32 support_ic_type; + /*cut version TestChip/A-cut/B-cut... = 0/1/2/3/...*/ + u8 cut_version; + /*Fab version TSMC/UMC = 0/1*/ + u8 fab_version; + /*RF type 4T4R/3T3R/2T2R/1T2R/1T1R/...*/ + u8 rf_type; + u8 rfe_type; + /*Board type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...*/ + /*Enable Function DPK OFF/ON = 0/1*/ + u8 dpk_en; + u8 board_type; + u8 package_type; + u16 type_glna; + u16 type_gpa; + u16 type_alna; + u16 type_apa; + /*with external LNA NO/Yes = 0/1*/ + u8 ext_lna; /*2G*/ + u8 ext_lna_5g; /*5G*/ + /*with external PA NO/Yes = 0/1*/ + u8 ext_pa; /*2G*/ + u8 ext_pa_5g; /*5G*/ + /*with Efuse number*/ + u8 efuse0x3d7; + u8 efuse0x3d8; + /*with external TRSW NO/Yes = 0/1*/ + u8 ext_trsw; + u8 ext_lna_gain; /*2G*/ + u8 patch_id; /*Customer ID*/ + boolean is_in_hct_test; + u8 wifi_test; + + boolean is_dual_mac_smart_concurrent; + u32 bk_support_ability; + u8 ant_div_type; + u8 with_extenal_ant_switch; + boolean config_bbrf; + u8 odm_regulation_2_4g; + u8 odm_regulation_5g; + u8 iqk_fw_offload; + boolean cck_new_agc; + u8 phydm_period; + u32 phydm_sys_up_time; + u8 num_rf_path; + u32 soft_ap_special_setting; + u32 halmac_ability; + u8 is_receiver_blocking_en; + /*-----------HOOK BEFORE REG INIT-----------*/ + + /*Dynamic value*/ + + /*--------- POINTER REFERENCE-----------*/ + + u8 u1_byte_temp; + boolean BOOLEAN_temp; + struct _ADAPTER *PADAPTER_temp; + + /*MAC PHY mode SMSP/DMSP/DMDP = 0/1/2*/ + u8 *p_mac_phy_mode; + /*TX Unicast byte count*/ + u64 *p_num_tx_bytes_unicast; + /*RX Unicast byte count*/ + u64 *p_num_rx_bytes_unicast; + /*Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3*/ + u8 *p_wireless_mode; + /*Frequence band 2.4G/5G = 0/1*/ + u8 *p_band_type; + /*Secondary channel offset don't_care/below/above = 0/1/2*/ + u8 *p_sec_ch_offset; + /*security mode Open/WEP/AES/TKIP = 0/1/2/3*/ + u8 *p_security; + /*BW info 20M/40M/80M = 0/1/2*/ + u8 *p_band_width; + /*Central channel location Ch1/Ch2/....*/ + u8 *p_channel; /*central channel number*/ + boolean dpk_done; + /*Common info for 92D DMSP*/ + + boolean *p_is_get_value_from_other_mac; + struct _ADAPTER **p_buddy_adapter; + boolean *p_is_master_of_dmsp; /* MAC0: master, MAC1: slave */ + /*Common info for status*/ + boolean *p_is_scan_in_process; + boolean *p_is_power_saving; + /*CCA path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path_e.*/ + u8 *p_one_path_cca; + u8 *p_antenna_test; + boolean *p_is_net_closed; + u8 *pu1_forced_igi_lb; + boolean *p_is_fcs_mode_enable; + /*--------- For 8723B IQK-----------*/ + boolean *p_is_1_antenna; + u8 *p_rf_default_path; + /* 0:S1, 1:S0 */ + + /*--------- POINTER REFERENCE-----------*/ + u16 *p_forced_data_rate; + u8 *p_enable_antdiv; + u8 *p_enable_adaptivity; + u8 *hub_usb_mode; /*1: USB 2.0, 2: USB 3.0*/ + boolean *p_is_fw_dw_rsvd_page_in_progress; + u32 *p_current_tx_tp; + u32 *p_current_rx_tp; + u8 *p_sounding_seq; + u32 *p_soft_ap_mode; + /*------------CALL BY VALUE-------------*/ + boolean is_link_in_process; + boolean is_wifi_direct; + boolean is_wifi_display; + boolean is_linked; + boolean bLinkedcmw500; + boolean is_in_lps_pg; + boolean bsta_state; + u8 rssi_min; + u8 interface_index; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ + boolean is_mp_chip; + boolean is_one_entry_only; + boolean mp_mode; + u32 one_entry_macid; + u8 pre_number_linked_client; + u8 number_linked_client; + u8 pre_number_active_client; + u8 number_active_client; + /*Common info for BTDM*/ + boolean is_bt_enabled; /*BT is enabled*/ + boolean is_bt_connect_process; /*BT HS is under connection progress.*/ + u8 bt_hs_rssi; /*BT HS mode wifi rssi value.*/ + boolean is_bt_hs_operation; /*BT HS mode is under progress*/ + u8 bt_hs_dig_val; /*use BT rssi to decide the DIG value*/ + boolean is_bt_disable_edca_turbo; /*Under some condition, don't enable the EDCA Turbo*/ + boolean is_bt_busy; /*BT is busy.*/ + boolean is_bt_limited_dig; /*BT is busy.*/ + boolean is_disable_phy_api; + /*------------CALL BY VALUE-------------*/ + u8 RSSI_A; + u8 RSSI_B; + u8 RSSI_C; + u8 RSSI_D; + u64 RSSI_TRSW; + u64 RSSI_TRSW_H; + u64 RSSI_TRSW_L; + u64 RSSI_TRSW_iso; + u8 tx_ant_status; + u8 rx_ant_status; + u8 cck_lna_idx; + u8 cck_vga_idx; + u8 curr_station_id; + u8 ofdm_agc_idx[4]; + + u8 rx_rate; + boolean is_noisy_state; + u8 tx_rate; + u8 linked_interval; + u8 pre_channel; + u32 txagc_offset_value_a; + boolean is_txagc_offset_positive_a; + u32 txagc_offset_value_b; + boolean is_txagc_offset_positive_b; + u32 tx_tp; + u32 rx_tp; + u32 total_tp; + u64 cur_tx_ok_cnt; + u64 cur_rx_ok_cnt; + u64 last_tx_ok_cnt; + u64 last_rx_ok_cnt; + u16 consecutive_idlel_time; /*unit: second*/ + u32 bb_swing_offset_a; + boolean is_bb_swing_offset_positive_a; + u32 bb_swing_offset_b; + boolean is_bb_swing_offset_positive_b; + u8 igi_lower_bound; + u8 igi_upper_bound; + u8 antdiv_rssi; + u8 fat_comb_a; + u8 fat_comb_b; + u8 antdiv_intvl; + u8 ant_type; + u8 pre_ant_type; + u8 antdiv_period; + u8 evm_antdiv_period; + u8 antdiv_select; + u8 path_select; + u8 antdiv_evm_en; + u8 bdc_holdstate; + u8 ndpa_period; + boolean h2c_rarpt_connect; + boolean cck_agc_report_type; + + u8 dm_dig_max_TH; + u8 dm_dig_min_TH; + u8 print_agc; + u8 traffic_load; + u8 pre_traffic_load; + /*8821C Antenna and RF Set BTG/WLG/WLA Select*/ + u8 current_rf_set_8821c; + u8 default_rf_set_8821c; + u8 current_ant_num_8821c; + u8 default_ant_num_8821c; + /*For Adaptivtiy*/ + u16 nhm_cnt_0; + u16 nhm_cnt_1; + s8 TH_L2H_default; + s8 th_edcca_hl_diff_default; + s8 th_l2h_ini; + s8 th_edcca_hl_diff; + s8 th_l2h_ini_mode2; + s8 th_edcca_hl_diff_mode2; + boolean carrier_sense_enable; + u8 adaptivity_igi_upper; + boolean adaptivity_flag; + u8 dc_backoff; + boolean adaptivity_enable; + u8 ap_total_num; + boolean edcca_enable; + u8 pre_dbg_priority; + struct _ADAPTIVITY_STATISTICS adaptivity; + /*For Adaptivtiy*/ + u8 last_usb_hub; + u8 tx_bf_data_rate; + + u8 nbi_set_result; + + u8 c2h_cmd_start; + u8 fw_debug_trace[60]; + u8 pre_c2h_seq; + boolean fw_buff_is_enpty; + u32 data_frame_num; + + /*for noise detection*/ + boolean noisy_decision; /*b_noisy*/ + boolean pre_b_noisy; + u32 noisy_decision_smooth; + boolean is_disable_dym_ecs; + + struct _ODM_NOISE_MONITOR_ noise_level; + /*Define STA info.*/ + /*_ODM_STA_INFO*/ + /*2012/01/12 MH For MP, we need to reduce one array pointer for default port.??*/ + struct sta_info *p_odm_sta_info[ODM_ASSOCIATE_ENTRY_NUM]; + u16 platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; + /* platform_macid_table[platform_macid] = phydm_macid */ + s32 accumulate_pwdb[ODM_ASSOCIATE_ENTRY_NUM]; + + + /*2012/02/14 MH Add to share 88E ra with other SW team.*/ + /*We need to colelct all support abilit to a proper area.*/ + + boolean ra_support88e; + + struct _odm_phy_dbg_info_ phy_dbg_info; + + /*ODM Structure*/ + struct _DFS_STATISTICS dfs; + struct _FAST_ANTENNA_TRAINNING_ dm_fat_table; + struct _dynamic_initial_gain_threshold_ dm_dig_table; + struct _dynamic_power_saving dm_ps_table; + struct _dynamic_primary_cca dm_pri_cca; + struct _rate_adaptive_table_ dm_ra_table; + struct _FALSE_ALARM_STATISTICS false_alm_cnt; + struct _FALSE_ALARM_STATISTICS flase_alm_cnt_buddy_adapter; + struct _sw_antenna_switch_ dm_swat_table; + struct _CFO_TRACKING_ dm_cfo_track; + struct _ACS_ dm_acs; + struct _CCX_INFO dm_ccx_info; + struct _PHYDM_PSD_ dm_psd_table; + + struct _RT_ADCSMP adcsmp; + + struct _IQK_INFORMATION IQK_info; + + boolean *p_is_driver_stopped; + boolean *p_is_driver_is_going_to_pnp_set_power_sleep; + boolean *pinit_adpt_in_progress; + + /*PSD*/ + boolean is_user_assign_level; + u8 RSSI_BT; /*come from BT*/ + boolean is_psd_in_process; + boolean is_psd_active; + boolean is_dm_initial_gain_enable; + + /*MPT DIG*/ + struct timer_list mpt_dig_timer; + + /*for rate adaptive, in fact, 88c/92c fw will handle this*/ + u8 is_use_ra_mask; + + /* for dynamic SoML control */ + boolean bsomlenabled; + + /* for dynamic HTSTF gain control */ + boolean bhtstfenabled; + + struct _ODM_RATE_ADAPTIVE rate_adaptive; + struct odm_rf_calibration_structure rf_calibrate_info; + struct odm_power_trim_data power_trim_data; + + u32 n_iqk_cnt; + u32 n_iqk_ok_cnt; + u32 n_iqk_fail_cnt; + + /*Power Training*/ + u8 force_power_training_state; + boolean is_change_state; + u32 PT_score; + u64 ofdm_rx_cnt; + u64 cck_rx_cnt; + boolean is_disable_power_training; + u8 dynamic_tx_high_power_lvl; + u8 last_dtp_lvl; + u32 tx_agc_ofdm_18_6; + u8 rx_pkt_type; + + /*ODM relative time.*/ + struct phydm_timer_list path_div_switch_timer; + /*2011.09.27 add for path Diversity*/ + struct phydm_timer_list cck_path_diversity_timer; + struct phydm_timer_list fast_ant_training_timer; + struct phydm_timer_list sbdcnt_timer; +}; + +enum phydm_structure_type { + PHYDM_FALSEALMCNT, + PHYDM_CFOTRACK, + PHYDM_ADAPTIVITY, + PHYDM_DFS, + PHYDM_ROMINFO, + +}; + +enum odm_rf_content { + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +}; + +enum odm_bb_config_type { + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, + CONFIG_BB_PHY_REG_MP, + CONFIG_BB_AGC_TAB_DIFF, +}; + +enum odm_rf_config_type { + CONFIG_RF_RADIO, + CONFIG_RF_TXPWR_LMT, +}; + +enum odm_fw_config_type { + CONFIG_FW_NIC, + CONFIG_FW_NIC_2, + CONFIG_FW_AP, + CONFIG_FW_AP_2, + CONFIG_FW_MP, + CONFIG_FW_WOWLAN, + CONFIG_FW_WOWLAN_2, + CONFIG_FW_AP_WOWLAN, + CONFIG_FW_BT, +}; + +/*status code*/ +enum rt_status { + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}; + +#ifdef REMOVE_PACK + #pragma pack() +#endif + +/*===========================================================*/ +/*AGC RX High Power mode*/ +/*===========================================================*/ +#define lna_low_gain_1 0x64 +#define lna_low_gain_2 0x5A +#define lna_low_gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +enum dm_1r_cca_e { + CCA_1R = 0, + CCA_2R = 1, + CCA_MAX = 2, +}; + +enum dm_rf_e { + rf_save = 0, + rf_normal = 1, + RF_MAX = 2, +}; + +/*check Sta pointer valid or not*/ + +#define IS_STA_VALID(p_sta) (p_sta) + +u32 odm_convert_to_db(u32 value); + +u32 odm_convert_to_linear(u32 value); + +s32 +odm_pwdb_conversion( + s32 X, + u32 total_bit, + u32 decimal_bit +); + +s32 +odm_sign_conversion( + s32 value, + u32 total_bit +); + +void +odm_init_mp_driver_status( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +phydm_txcurrentcalibration( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +phydm_seq_sorting( + void *p_dm_void, + u32 *p_value, + u32 *rank_idx, + u32 *p_idx_out, + u8 seq_length +); + +void +odm_dm_init( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_dm_reset( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +phydm_support_ability_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +phydm_config_ofdm_rx_path( + struct PHY_DM_STRUCT *p_dm_odm, + u32 path +); + +void +phydm_config_trx_path( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +void +odm_dm_watchdog( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +phydm_watchdog_mp( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_cmn_info_init( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u32 value +); + +void +odm_cmn_info_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + void *p_value +); + +void +odm_cmn_info_ptr_array_hook( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_cmninfo_e cmn_info, + u16 index, + void *p_value +); + +void +odm_cmn_info_update( + struct PHY_DM_STRUCT *p_dm_odm, + u32 cmn_info, + u64 value +); + +u32 +phydm_cmn_info_query( + struct PHY_DM_STRUCT *p_dm_odm, + enum phydm_info_query_e info_type +); + +void +odm_init_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_cancel_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_release_all_timers( + struct PHY_DM_STRUCT *p_dm_odm +); + +void * +phydm_get_structure( + struct PHY_DM_STRUCT *p_dm_odm, + u8 structure_type +); + +/*===========================================================*/ +/* The following is for compile only*/ +/*===========================================================*/ + +#define IS_HARDWARE_TYPE_8723A(_adapter) false +#define IS_HARDWARE_TYPE_8723AE(_adapter) false +#define IS_HARDWARE_TYPE_8192C(_adapter) false +#define IS_HARDWARE_TYPE_8192D(_adapter) false +#define RF_T_METER_92D 0x42 + +#define GET_RX_STATUS_DESC_RX_MCS(__prx_status_desc) LE_BITS_TO_1BYTE(__prx_status_desc+12, 0, 6) + +#define REG_CONFIG_RAM64X16 0xb2c + +#define TARGET_CHNL_NUM_2G_5G 59 + +/* *********************************************************** */ + +void phydm_noisy_detection(struct PHY_DM_STRUCT *p_dm_odm); + +void +phydm_api_debug( + void *p_dm_void, + u32 function_map, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +u8 +phydm_nbi_setting( + void *p_dm_void, + u32 enable, + u32 channel, + u32 bw, + u32 f_interference, + u32 second_ch +); + +void +phydm_receiver_blocking( + void *p_dm_void +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_acs.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_acs.c new file mode 100644 index 000000000000..6d7b9813b3cb --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_acs.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +u8 +odm_get_auto_channel_select_result( + void *p_dm_void, + u8 band +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + + if (band == ODM_BAND_2_4G) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_2g(%d)\n", p_acs->clean_channel_2g)); + return (u8)p_acs->clean_channel_2g; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[struct _ACS_] odm_get_auto_channel_select_result(): clean_channel_5g(%d)\n", p_acs->clean_channel_5g)); + return (u8)p_acs->clean_channel_5g; + } +} + +void +odm_auto_channel_select_setting( + void *p_dm_void, + boolean is_enable +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 period = 0x2710;/* 40ms in default */ + u16 nhm_type = 0x7; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_setting()=========>\n")); + + if (is_enable) { + /* 20 ms */ + period = 0x1388; + nhm_type = 0x1; + } + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + /* PHY parameters initialize for ac series */ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, period); /* 0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms */ + /* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8)|BIT9|BIT10, nhm_type); */ /* 0x994[9:8]=3 enable CCX */ + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /* PHY parameters initialize for n series */ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, period); /* 0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms */ + /* odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)|BIT9|BIT8, nhm_type); */ /* 0x890[9:8]=3 enable CCX */ + } +} + +void +odm_auto_channel_select_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + u8 i; + + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) + return; + + if (p_acs->is_force_acs_result) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_init()=========>\n")); + + p_acs->clean_channel_2g = 1; + p_acs->clean_channel_5g = 36; + + for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) { + p_acs->channel_info_2g[0][i] = 0; + p_acs->channel_info_2g[1][i] = 0; + } + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) { + p_acs->channel_info_5g[0][i] = 0; + p_acs->channel_info_5g[1][i] = 0; + } + } +} + +void +odm_auto_channel_select_reset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) + return; + + if (p_acs->is_force_acs_result) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select_reset()=========>\n")); + + odm_auto_channel_select_setting(p_dm_odm, true); /* for 20ms measurement */ + phydm_nhm_counter_statistics_reset(p_dm_odm); +} + +void +odm_auto_channel_select( + void *p_dm_void, + u8 channel +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ACS_ *p_acs = &p_dm_odm->dm_acs; + u8 channel_idx = 0, search_idx = 0; + u16 max_score = 0; + + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Return: support_ability ODM_BB_NHM_CNT is disabled\n")); + return; + } + + if (p_acs->is_force_acs_result) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_auto_channel_select(): Force 2G clean channel = %d, 5G clean channel = %d\n", + p_acs->clean_channel_2g, p_acs->clean_channel_5g)); + return; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): channel = %d=========>\n", channel)); + + phydm_get_nhm_counter_statistics(p_dm_odm); + odm_auto_channel_select_setting(p_dm_odm, false); + + if (channel >= 1 && channel <= 14) { + channel_idx = channel - 1; + p_acs->channel_info_2g[1][channel_idx]++; + + if (p_acs->channel_info_2g[1][channel_idx] >= 2) + p_acs->channel_info_2g[0][channel_idx] = (p_acs->channel_info_2g[0][channel_idx] >> 1) + + (p_acs->channel_info_2g[0][channel_idx] >> 2) + (p_dm_odm->nhm_cnt_0 >> 2); + else + p_acs->channel_info_2g[0][channel_idx] = p_dm_odm->nhm_cnt_0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): nhm_cnt_0 = %d\n", p_dm_odm->nhm_cnt_0)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_auto_channel_select(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", channel_idx, p_acs->channel_info_2g[0][channel_idx], channel_idx, p_acs->channel_info_2g[1][channel_idx])); + + for (search_idx = 0; search_idx < ODM_MAX_CHANNEL_2G; search_idx++) { + if (p_acs->channel_info_2g[1][search_idx] != 0) { + if (p_acs->channel_info_2g[0][search_idx] >= max_score) { + max_score = p_acs->channel_info_2g[0][search_idx]; + p_acs->clean_channel_2g = search_idx + 1; + } + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_auto_channel_select(): 2G: clean_channel_2g = %d, max_score = %d\n", + p_acs->clean_channel_2g, max_score)); + + } else if (channel >= 36) { + /* Need to do */ + p_acs->clean_channel_5g = channel; + } +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_acs.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_acs.h new file mode 100644 index 000000000000..4821da041d3a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_acs.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMACS_H__ +#define __PHYDMACS_H__ + +#define ACS_VERSION "1.1" /*20150729 by YuChen*/ +#define CLM_VERSION "1.0" + +#define ODM_MAX_CHANNEL_2G 14 +#define ODM_MAX_CHANNEL_5G 24 + +/* For phydm_auto_channel_select_setting_ap() */ +#define STORE_DEFAULT_NHM_SETTING 0 +#define RESTORE_DEFAULT_NHM_SETTING 1 +#define ACS_NHM_SETTING 2 + +struct _ACS_ { + boolean is_force_acs_result; + u8 clean_channel_2g; + u8 clean_channel_5g; + u16 channel_info_2g[2][ODM_MAX_CHANNEL_2G]; /* Channel_Info[1]: channel score, Channel_Info[2]:Channel_Scan_Times */ + u16 channel_info_5g[2][ODM_MAX_CHANNEL_5G]; +}; + +void +odm_auto_channel_select_init( + void *p_dm_void +); + +void +odm_auto_channel_select_reset( + void *p_dm_void +); + +void +odm_auto_channel_select( + void *p_dm_void, + u8 channel +); + +u8 +odm_get_auto_channel_select_result( + void *p_dm_void, + u8 band +); + +#endif /* #ifndef __PHYDMACS_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_adaptivity.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_adaptivity.c new file mode 100644 index 000000000000..6e8cab8146fc --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_adaptivity.c @@ -0,0 +1,863 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +phydm_check_adaptivity( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + + if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { + { + if (adaptivity->dynamic_link_adaptivity || adaptivity->acs_for_adaptivity) { + if (p_dm_odm->is_linked && adaptivity->is_check == false) { + phydm_nhm_counter_statistics(p_dm_odm); + phydm_check_environment(p_dm_odm); + } else if (!p_dm_odm->is_linked) + adaptivity->is_check = false; + } else { + p_dm_odm->adaptivity_enable = true; + + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + p_dm_odm->adaptivity_flag = false; + else + p_dm_odm->adaptivity_flag = true; + } + } + } else { + p_dm_odm->adaptivity_enable = false; + p_dm_odm->adaptivity_flag = false; + } + +} + +void +phydm_nhm_counter_statistics_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + /*PHY parameters initialize for n series*/ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ + odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff); /*0xe28[7:0]=0xff th_8*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10) | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1); /*0xc0c[7]=1 max power among all RX ants*/ + } + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + /*PHY parameters initialize for ac series*/ + odm_write_2byte(p_dm_odm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ + odm_write_2byte(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/ + odm_write_4byte(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff); /*0x9a0[7:0]=0xff th_8*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8) | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1); /*0x9e8[7]=1 max power among all RX ants*/ + + } +} + +void +phydm_nhm_counter_statistics( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (!(p_dm_odm->support_ability & ODM_BB_NHM_CNT)) + return; + + /*Get NHM report*/ + phydm_get_nhm_counter_statistics(p_dm_odm); + + /*Reset NHM counter*/ + phydm_nhm_counter_statistics_reset(p_dm_odm); +} + +void +phydm_get_nhm_counter_statistics( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32 = 0; + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11AC, MASKDWORD); + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_CNT_11N, MASKDWORD); + + p_dm_odm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0); + p_dm_odm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8); + +} + +void +phydm_nhm_counter_statistics_reset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); + } + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); + } + + +} + +void +phydm_set_edcca_threshold( + void *p_dm_void, + s8 H2L, + s8 L2H +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)L2H | (u8)H2L << 16)); + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)L2H | (u8)H2L << 8)); + +} + +void +phydm_set_lna( + void *p_dm_void, + enum phydm_set_lna type +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) { + if (type == phydm_disable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } else if (type == phydm_enable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } + } else if (p_dm_odm->support_ic_type & ODM_RTL8723B) { + if (type == phydm_disable_lna) { + /*S0*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + /*S1*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + } else if (type == phydm_enable_lna) { + /*S0*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + /*S1*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + } + + } else if (p_dm_odm->support_ic_type & ODM_RTL8812) { + if (type == phydm_disable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } else if (type == phydm_enable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } + } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { + if (type == phydm_disable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + } else if (type == phydm_enable_lna) { + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + } + } +} + +void +phydm_set_trx_mux( + void *p_dm_void, + enum phydm_trx_mux_type tx_mode, + enum phydm_trx_mux_type rx_mode +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(3) | BIT2 | BIT1, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT(22) | BIT21 | BIT20, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(3) | BIT2 | BIT1, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT(22) | BIT21 | BIT20, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + } + } + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(11) | BIT10 | BIT9 | BIT8, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC, BIT(7) | BIT6 | BIT5 | BIT4, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + if (p_dm_odm->rf_type > ODM_1T1R) { + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(11) | BIT10 | BIT9 | BIT8, tx_mode); /*set TXmod to standby mode to remove outside noise affect*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_TRMUX_11AC_B, BIT(7) | BIT6 | BIT5 | BIT4, rx_mode); /*set RXmod to standby mode to remove outside noise affect*/ + } + } + +} + +void +phydm_mac_edcca_state( + void *p_dm_void, + enum phydm_mac_edcca_type state +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (state == phydm_ignore_edcca) { + odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 1); /*ignore EDCCA reg520[15]=1*/ + /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 0); */ /*reg524[11]=0*/ + } else { /*don't set MAC ignore EDCCA signal*/ + odm_set_mac_reg(p_dm_odm, REG_TX_PTCL_CTRL, BIT(15), 0); /*don't ignore EDCCA reg520[15]=0*/ + /* odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); */ /*reg524[11]=1 */ + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable state = %d\n", state)); + +} + +boolean +phydm_cal_nhm_cnt( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u16 base = 0; + + base = p_dm_odm->nhm_cnt_0 + p_dm_odm->nhm_cnt_1; + + if (base != 0) { + p_dm_odm->nhm_cnt_0 = ((p_dm_odm->nhm_cnt_0) << 8) / base; + p_dm_odm->nhm_cnt_1 = ((p_dm_odm->nhm_cnt_1) << 8) / base; + } + if ((p_dm_odm->nhm_cnt_0 - p_dm_odm->nhm_cnt_1) >= 100) + return true; /*clean environment*/ + else + return false; /*noisy environment*/ + +} + +void +phydm_check_environment( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + boolean is_clean_environment = false; + + if (adaptivity->is_first_link == true) { + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + p_dm_odm->adaptivity_flag = false; + else + p_dm_odm->adaptivity_flag = true; + + adaptivity->is_first_link = false; + return; + } else { + if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/ + adaptivity->nhm_wait++; + phydm_nhm_counter_statistics(p_dm_odm); + return; + } else { + phydm_nhm_counter_statistics(p_dm_odm); + is_clean_environment = phydm_cal_nhm_cnt(p_dm_odm); + if (is_clean_environment == true) { + p_dm_odm->th_l2h_ini = adaptivity->th_l2h_ini_backup; /*adaptivity mode*/ + p_dm_odm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup; + + p_dm_odm->adaptivity_enable = true; + + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + p_dm_odm->adaptivity_flag = false; + else + p_dm_odm->adaptivity_flag = true; + } else { + if (!adaptivity->acs_for_adaptivity) { + p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; /*mode2*/ + p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; + + p_dm_odm->adaptivity_flag = false; + p_dm_odm->adaptivity_enable = false; + } + } + adaptivity->nhm_wait = 0; + adaptivity->is_first_link = true; + adaptivity->is_check = true; + } + + } + +} + +void +phydm_search_pwdb_lower_bound( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + u32 value32 = 0, reg_value32 = 0; + u8 cnt, try_count = 0; + u8 tx_edcca1 = 0, tx_edcca0 = 0; + boolean is_adjust = true; + s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32; + s8 diff; + u8 IGI = adaptivity->igi_base + 30 + (u8)p_dm_odm->th_l2h_ini - (u8)p_dm_odm->th_edcca_hl_diff; + + if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + phydm_set_lna(p_dm_odm, phydm_disable_lna); + else { + phydm_set_trx_mux(p_dm_odm, phydm_standby_mode, phydm_standby_mode); + odm_pause_dig(p_dm_odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e); + } + + diff = igi_target - (s8)IGI; + th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + if (th_l2h_dmc > 10) + th_l2h_dmc = 10; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + ODM_delay_ms(30); + + while (is_adjust) { + + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ + reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + + while (reg_value32 & BIT(3) && try_count < 3) { + ODM_delay_ms(3); + try_count = try_count + 1; + reg_value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + } + phydm_release_bb_dbg_port(p_dm_odm); + try_count = 0; + } + + for (cnt = 0; cnt < 20; cnt++) { + + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { + value32 = phydm_get_bb_dbg_port_value(p_dm_odm); + phydm_release_bb_dbg_port(p_dm_odm); + } + + if (value32 & BIT(30) && (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))) + tx_edcca1 = tx_edcca1 + 1; + else if (value32 & BIT(29)) + tx_edcca1 = tx_edcca1 + 1; + else + tx_edcca0 = tx_edcca0 + 1; + } + + if (tx_edcca1 > 1) { + IGI = IGI - 1; + th_l2h_dmc = th_l2h_dmc + 1; + if (th_l2h_dmc > 10) + th_l2h_dmc = 10; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + if (th_l2h_dmc == 10) { + is_adjust = false; + adaptivity->h2l_lb = th_h2l_dmc; + adaptivity->l2h_lb = th_l2h_dmc; + p_dm_odm->adaptivity_igi_upper = IGI; + } + + tx_edcca1 = 0; + tx_edcca0 = 0; + + } else { + is_adjust = false; + adaptivity->h2l_lb = th_h2l_dmc; + adaptivity->l2h_lb = th_l2h_dmc; + p_dm_odm->adaptivity_igi_upper = IGI; + tx_edcca1 = 0; + tx_edcca0 = 0; + } + } + + p_dm_odm->adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper - p_dm_odm->dc_backoff; + adaptivity->h2l_lb = adaptivity->h2l_lb + p_dm_odm->dc_backoff; + adaptivity->l2h_lb = adaptivity->l2h_lb + p_dm_odm->dc_backoff; + + if (p_dm_odm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + phydm_set_lna(p_dm_odm, phydm_enable_lna); + else { + phydm_set_trx_mux(p_dm_odm, phydm_tx_mode, phydm_rx_mode); + odm_pause_dig(p_dm_odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE); + } + + phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ +} + +boolean +phydm_re_search_condition( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + /*struct _ADAPTIVITY_STATISTICS* adaptivity = (struct _ADAPTIVITY_STATISTICS*)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);*/ + u8 adaptivity_igi_upper; + u8 count = 0; + /*s8 TH_L2H_dmc, IGI_target = 0x32;*/ + /*s8 diff;*/ + + adaptivity_igi_upper = p_dm_odm->adaptivity_igi_upper + p_dm_odm->dc_backoff; + + /*TH_L2H_dmc = 10;*/ + + /*diff = TH_L2H_dmc - p_dm_odm->TH_L2H_ini;*/ + /*lowest_IGI_upper = IGI_target - diff;*/ + + /*if ((adaptivity_igi_upper - lowest_IGI_upper) <= 5)*/ + if (adaptivity_igi_upper <= 0x26 && count < 3) { + count = count + 1; + return true; + } + else + return false; + +} + +void +phydm_adaptivity_info_init( + void *p_dm_void, + enum phydm_adapinfo_e cmn_info, + u32 value +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + + switch (cmn_info) { + case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE: + p_dm_odm->carrier_sense_enable = (boolean)value; + break; + + case PHYDM_ADAPINFO_DCBACKOFF: + p_dm_odm->dc_backoff = (u8)value; + break; + + case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY: + adaptivity->dynamic_link_adaptivity = (boolean)value; + break; + + case PHYDM_ADAPINFO_TH_L2H_INI: + p_dm_odm->th_l2h_ini = (s8)value; + break; + + case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF: + p_dm_odm->th_edcca_hl_diff = (s8)value; + break; + + case PHYDM_ADAPINFO_AP_NUM_TH: + adaptivity->ap_num_th = (u8)value; + break; + + default: + break; + + } + +} + +void +phydm_adaptivity_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + s8 igi_target = 0x32; + /*struct _dynamic_initial_gain_threshold_* p_dm_dig_table = &p_dm_odm->dm_dig_table;*/ + + if (p_dm_odm->carrier_sense_enable == false) { + if (p_dm_odm->th_l2h_ini == 0) + phydm_set_l2h_th_ini(p_dm_odm); + } else + p_dm_odm->th_l2h_ini = 0xa; + + if (p_dm_odm->th_edcca_hl_diff == 0) + p_dm_odm->th_edcca_hl_diff = 7; + if (p_dm_odm->wifi_test == true || p_dm_odm->mp_mode == true) + p_dm_odm->edcca_enable = false; /*even no adaptivity, we still enable EDCCA, AP side use mib control*/ + else + p_dm_odm->edcca_enable = true; + + p_dm_odm->adaptivity_igi_upper = 0; + p_dm_odm->adaptivity_enable = false; /*use this flag to decide enable or disable*/ + + p_dm_odm->th_l2h_ini_mode2 = 20; + p_dm_odm->th_edcca_hl_diff_mode2 = 8; + adaptivity->th_l2h_ini_backup = p_dm_odm->th_l2h_ini; + adaptivity->th_edcca_hl_diff_backup = p_dm_odm->th_edcca_hl_diff; + + adaptivity->igi_base = 0x32; + adaptivity->igi_target = 0x1c; + adaptivity->h2l_lb = 0; + adaptivity->l2h_lb = 0; + adaptivity->nhm_wait = 0; + adaptivity->is_check = false; + adaptivity->is_first_link = true; + adaptivity->adajust_igi_level = 0; + adaptivity->is_stop_edcca = false; + adaptivity->backup_h2l = 0; + adaptivity->backup_l2h = 0; + adaptivity->adaptivity_dbg_port = (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) ? 0x208 : 0x209; + + phydm_mac_edcca_state(p_dm_odm, phydm_dont_ignore_edcca); + + if (p_dm_odm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) { + /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT(12) | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1); /*set to page B1*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_97F, BIT(27) | BIT26, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0); + } else + odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DCNF_11N, BIT(21) | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + } + if (p_dm_odm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/ + /*odm_set_bb_reg(p_dm_odm, ODM_REG_EDCCA_DOWN_OPT, BIT(30) | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT(29) | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + } + + if (!(p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) { + phydm_search_pwdb_lower_bound(p_dm_odm); + if (phydm_re_search_condition(p_dm_odm)) + phydm_search_pwdb_lower_bound(p_dm_odm); + } else + phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); /*resume to no link state*/ + /*forgetting factor setting*/ + phydm_set_forgetting_factor(p_dm_odm); + + /*we need to consider PwdB upper bound for 8814 later IC*/ + adaptivity->adajust_igi_level = (u8)((p_dm_odm->th_l2h_ini + igi_target) - pwdb_upper_bound + dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/ + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n", p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff, adaptivity->adajust_igi_level)); + + /*Check this later on Windows*/ + /*phydm_set_edcca_threshold_api(p_dm_odm, p_dm_dig_table->cur_ig_value);*/ + +} + +void +phydm_adaptivity( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 IGI = p_dm_dig_table->cur_ig_value; + s8 th_l2h_dmc, th_h2l_dmc; + s8 diff = 0, igi_target; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + + if ((p_dm_odm->edcca_enable == false) || (adaptivity->is_stop_edcca == true)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n")); + return; + } + + if (!(p_dm_odm->support_ability & ODM_BB_ADAPTIVITY)) { + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n")); + p_dm_odm->th_l2h_ini = p_dm_odm->th_l2h_ini_mode2; + p_dm_odm->th_edcca_hl_diff = p_dm_odm->th_edcca_hl_diff_mode2; + } + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n")); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n", + adaptivity->igi_base, p_dm_odm->th_l2h_ini, p_dm_odm->th_edcca_hl_diff)); + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + /*fix AC series when enable EDCCA hang issue*/ + odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 1); /*ADC_mask disable*/ + odm_set_bb_reg(p_dm_odm, 0x800, BIT(10), 0); /*ADC_mask enable*/ + } + + igi_target = adaptivity->igi_base; + adaptivity->igi_target = (u8) igi_target; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n", + (*p_dm_odm->p_band_width == ODM_BW80M) ? "80M" : ((*p_dm_odm->p_band_width == ODM_BW40M) ? "40M" : "20M"), igi_target, adaptivity->dynamic_link_adaptivity, adaptivity->acs_for_adaptivity)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n", + p_dm_odm->rssi_min, adaptivity->adajust_igi_level, p_dm_odm->adaptivity_flag, p_dm_odm->adaptivity_enable)); + + if ((adaptivity->dynamic_link_adaptivity == true) && (!p_dm_odm->is_linked) && (p_dm_odm->adaptivity_enable == false)) { + phydm_set_edcca_threshold(p_dm_odm, 0x7f, 0x7f); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n")); + return; + } + + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if ((adaptivity->adajust_igi_level > IGI) && (p_dm_odm->adaptivity_enable == true)) + diff = adaptivity->adajust_igi_level - IGI; + + th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + } + else { + diff = igi_target - (s8)IGI; + th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + if (th_l2h_dmc > 10 && (p_dm_odm->adaptivity_enable == true)) + th_l2h_dmc = 10; + + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + + /*replace lower bound to prevent EDCCA always equal 1*/ + if (th_h2l_dmc < adaptivity->h2l_lb) + th_h2l_dmc = adaptivity->h2l_lb; + if (th_l2h_dmc < adaptivity->l2h_lb) + th_l2h_dmc = adaptivity->l2h_lb; + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); + + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + + if (p_dm_odm->adaptivity_enable == true) + odm_set_mac_reg(p_dm_odm, REG_RD_CTRL, BIT(11), 1); + + return; +} + +/*This API is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/ +void +phydm_pause_edcca( + void *p_dm_void, + boolean is_pasue_edcca +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 IGI = p_dm_dig_table->cur_ig_value; + s8 diff = 0; + + if (is_pasue_edcca) { + adaptivity->is_stop_edcca = true; + + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if (adaptivity->adajust_igi_level > IGI) + diff = adaptivity->adajust_igi_level - IGI; + + adaptivity->backup_l2h = p_dm_odm->th_l2h_ini - diff + adaptivity->igi_target; + adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; + } + else { + diff = adaptivity->igi_target - (s8)IGI; + adaptivity->backup_l2h = p_dm_odm->th_l2h_ini + diff; + if (adaptivity->backup_l2h > 10) + adaptivity->backup_l2h = 10; + + adaptivity->backup_h2l = adaptivity->backup_l2h - p_dm_odm->th_edcca_hl_diff; + + /*replace lower bound to prevent EDCCA always equal 1*/ + if (adaptivity->backup_h2l < adaptivity->h2l_lb) + adaptivity->backup_h2l = adaptivity->h2l_lb; + if (adaptivity->backup_l2h < adaptivity->l2h_lb) + adaptivity->backup_l2h = adaptivity->l2h_lb; + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); + + /*Disable EDCCA*/ + phydm_pause_edcca_work_item_callback(p_dm_odm); + + } else { + + adaptivity->is_stop_edcca = false; + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n", adaptivity->backup_l2h, adaptivity->backup_h2l, IGI)); + /*Resume EDCCA*/ + phydm_resume_edcca_work_item_callback(p_dm_odm); + } + +} + +void +phydm_pause_edcca_work_item_callback( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16)); + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)(0x7f | 0x7f << 8)); + +} + +void +phydm_resume_edcca_work_item_callback( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + + if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + odm_set_bb_reg(p_dm_odm, REG_OFDM_0_ECCA_THRESHOLD, MASKBYTE2 | MASKBYTE0, (u32)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 16)); + else if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_set_bb_reg(p_dm_odm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD, (u16)((u8)adaptivity->backup_l2h | (u8)adaptivity->backup_h2l << 8)); + +} + +void +phydm_set_edcca_threshold_api( + void *p_dm_void, + u8 IGI +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + s8 th_l2h_dmc, th_h2l_dmc; + s8 diff = 0, igi_target = 0x32; + + if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) { + if (p_dm_odm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if (adaptivity->adajust_igi_level > IGI) + diff = adaptivity->adajust_igi_level - IGI; + + th_l2h_dmc = p_dm_odm->th_l2h_ini - diff + igi_target; + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + } + else { + diff = igi_target - (s8)IGI; + th_l2h_dmc = p_dm_odm->th_l2h_ini + diff; + if (th_l2h_dmc > 10) + th_l2h_dmc = 10; + + th_h2l_dmc = th_l2h_dmc - p_dm_odm->th_edcca_hl_diff; + + /*replace lower bound to prevent EDCCA always equal 1*/ + if (th_h2l_dmc < adaptivity->h2l_lb) + th_h2l_dmc = adaptivity->h2l_lb; + if (th_l2h_dmc < adaptivity->l2h_lb) + th_l2h_dmc = adaptivity->l2h_lb; + } + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI, th_l2h_dmc, th_h2l_dmc)); + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n", p_dm_odm->adaptivity_igi_upper, adaptivity->h2l_lb, adaptivity->l2h_lb)); + + phydm_set_edcca_threshold(p_dm_odm, th_h2l_dmc, th_l2h_dmc); + } + +} + +void +phydm_set_l2h_th_ini( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + p_dm_odm->th_l2h_ini = 0xf2; + else + p_dm_odm->th_l2h_ini = 0xef; + } else + p_dm_odm->th_l2h_ini = 0xf5; +} + +void +phydm_set_forgetting_factor( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A)) + odm_set_bb_reg(p_dm_odm, 0x8a0, BIT(1) | BIT(0), 0); +} + diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_adaptivity.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_adaptivity.h new file mode 100644 index 000000000000..d62acdd42fa5 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_adaptivity.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMADAPTIVITY_H__ +#define __PHYDMADAPTIVITY_H__ + +#define ADAPTIVITY_VERSION "9.5.2" /*20170420 changed by Kevin, change th_l2h_ini setting for 5G: v2.1.0*/ + +#define pwdb_upper_bound 7 +#define dfir_loss 7 + +enum phydm_adapinfo_e { + PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE = 0, + PHYDM_ADAPINFO_DCBACKOFF, + PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY, + PHYDM_ADAPINFO_TH_L2H_INI, + PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF, + PHYDM_ADAPINFO_AP_NUM_TH + +}; + +enum phydm_set_lna { + phydm_disable_lna = 0, + phydm_enable_lna = 1, +}; + +enum phydm_trx_mux_type { + phydm_shutdown = 0, + phydm_standby_mode = 1, + phydm_tx_mode = 2, + phydm_rx_mode = 3 +}; + +enum phydm_mac_edcca_type { + phydm_ignore_edcca = 0, + phydm_dont_ignore_edcca = 1 +}; + +struct _ADAPTIVITY_STATISTICS { + s8 th_l2h_ini_backup; + s8 th_edcca_hl_diff_backup; + s8 igi_base; + u8 igi_target; + u8 nhm_wait; + s8 h2l_lb; + s8 l2h_lb; + boolean is_first_link; + boolean is_check; + boolean dynamic_link_adaptivity; + u8 ap_num_th; + u8 adajust_igi_level; + boolean acs_for_adaptivity; + s8 backup_l2h; + s8 backup_h2l; + boolean is_stop_edcca; + u32 adaptivity_dbg_port; /*N:0x208, AC:0x209*/ +}; + +void +phydm_pause_edcca( + void *p_dm_void, + boolean is_pasue_edcca +); + +void +phydm_check_adaptivity( + void *p_dm_void +); + +void +phydm_check_environment( + void *p_dm_void +); + +void +phydm_nhm_counter_statistics_init( + void *p_dm_void +); + +void +phydm_nhm_counter_statistics( + void *p_dm_void +); + +void +phydm_nhm_counter_statistics_reset( + void *p_dm_void +); + +void +phydm_get_nhm_counter_statistics( + void *p_dm_void +); + +void +phydm_mac_edcca_state( + void *p_dm_void, + enum phydm_mac_edcca_type state +); + +void +phydm_set_edcca_threshold( + void *p_dm_void, + s8 H2L, + s8 L2H +); + +void +phydm_set_trx_mux( + void *p_dm_void, + enum phydm_trx_mux_type tx_mode, + enum phydm_trx_mux_type rx_mode +); + +boolean +phydm_cal_nhm_cnt( + void *p_dm_void +); + +void +phydm_search_pwdb_lower_bound( + void *p_dm_void +); + +void +phydm_adaptivity_info_init( + void *p_dm_void, + enum phydm_adapinfo_e cmn_info, + u32 value +); + +void +phydm_adaptivity_init( + void *p_dm_void +); + +void +phydm_adaptivity( + void *p_dm_void +); + +void +phydm_set_edcca_threshold_api( + void *p_dm_void, + u8 IGI +); + +void +phydm_pause_edcca_work_item_callback( + void *p_dm_void +); + +void +phydm_resume_edcca_work_item_callback( + void *p_dm_void +); + +void +phydm_set_l2h_th_ini( + void *p_dm_void +); + +void +phydm_set_forgetting_factor( + void *p_dm_void +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_adc_sampling.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_adc_sampling.c new file mode 100644 index 000000000000..b687bea59ff2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_adc_sampling.c @@ -0,0 +1,591 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +boolean +phydm_la_buffer_allocate( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + boolean ret = false; + + dbg_print("[LA mode BufferAllocate]\n"); + + if (adc_smp_buf->length == 0) { + odm_allocate_memory(p_dm_odm, (void **)&adc_smp_buf->octet, adc_smp_buf->buffer_size); + if (!adc_smp_buf->octet) + ret = false; + else { + adc_smp_buf->length = adc_smp_buf->buffer_size; + ret = true; + } + } + + return ret; +} + +void +phydm_la_get_tx_pkt_buf( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + u32 i = 0, value32, data_l = 0, data_h = 0; + u32 addr, finish_addr; + u32 end_addr = (adc_smp_buf->start_pos + adc_smp_buf->buffer_size) - 1; /*end_addr = 0x3ffff;*/ + boolean is_round_up; + static u32 page = 0xFF; + u32 smp_cnt = 0, smp_number = 0, addr_8byte = 0; + + odm_memory_set(p_dm_odm, adc_smp_buf->octet, 0, adc_smp_buf->length); + odm_write_1byte(p_dm_odm, 0x0106, 0x69); + + dbg_print("GetTxPktBuf\n"); + + value32 = odm_read_4byte(p_dm_odm, 0x7c0); + is_round_up = (boolean)((value32 & BIT(31)) >> 31); + finish_addr = (value32 & 0x7FFF0000) >> 16; /*Reg7C0[30:16]: finish addr (unit: 8byte)*/ + + if (is_round_up) { + addr = (finish_addr + 1) << 3; + dbg_print("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0=((0x%x))\n", is_round_up, finish_addr, value32); + smp_number = ((adc_smp_buf->buffer_size) >> 3); /*Byte to 64Byte*/ + } else { + addr = adc_smp_buf->start_pos; + + addr_8byte = addr >> 3; + if (addr_8byte > finish_addr) + smp_number = addr_8byte - finish_addr; + else + smp_number = finish_addr - addr_8byte; + + dbg_print("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n", is_round_up, finish_addr, addr_8byte, smp_number); + + } + /* + dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n", is_round_up, finish_addr, value32); + dbg_print("end_addr = %x, adc_smp_buf->start_pos = 0x%x, adc_smp_buf->buffer_size = 0x%x\n", end_addr, adc_smp_buf->start_pos, adc_smp_buf->buffer_size); + */ + + if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + for (addr = 0x0, i = 0; addr < end_addr; addr += 8, i += 2) { /*64K byte*/ + if ((addr & 0xfff) == 0) + odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + (addr >> 12)); + data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); + data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); + + dbg_print("%08x%08x\n", data_h, data_l); + } + } else { + while (addr != (finish_addr << 3)) { + if (page != (addr >> 12)) { + /*Reg140=0x780+(addr>>12), addr=0x30~0x3F, total 16 pages*/ + page = (addr >> 12); + } + odm_set_bb_reg(p_dm_odm, 0x0140, MASKLWORD, 0x780 + page); + + /*pDataL = 0x8000+(addr&0xfff);*/ + data_l = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff), MASKDWORD); + data_h = odm_get_bb_reg(p_dm_odm, 0x8000 + (addr & 0xfff) + 4, MASKDWORD); + + adc_smp_buf->octet[i] = data_h; + adc_smp_buf->octet[i + 1] = data_l; + + dbg_print("%08x%08x\n", data_h, data_l); + + i = i + 2; + + if ((addr + 8) >= end_addr) + addr = adc_smp_buf->start_pos; + else + addr = addr + 8; + + smp_cnt++; + if (smp_cnt >= (smp_number - 1)) + break; + } + dbg_print("smp_cnt = ((%d))\n", smp_cnt); + } +} + +void +phydm_la_mode_set_mac_iq_dump( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + u32 reg_value; + + odm_write_1byte(p_dm_odm, 0x7c0, 0); /*clear all 0x7c0*/ + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(0), 1); /*Enable LA mode HW block*/ + + if (adc_smp->la_trig_mode == PHYDM_MAC_TRIG) { + + adc_smp->is_bb_trigger = 0; + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(2), 1); /*polling bit for MAC mode*/ + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(4) | BIT3, adc_smp->la_trigger_edge); /*trigger mode for MAC*/ + + dbg_print("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n", adc_smp->la_mac_ref_mask, adc_smp->la_trig_sig_sel, adc_smp->la_dbg_port); + /*[Set MAC Debug Port]*/ + odm_set_mac_reg(p_dm_odm, 0xF4, BIT(16), 1); + odm_set_mac_reg(p_dm_odm, 0x38, 0xff0000, adc_smp->la_dbg_port); + odm_set_mac_reg(p_dm_odm, 0x7c4, MASKDWORD, adc_smp->la_mac_ref_mask); + odm_set_mac_reg(p_dm_odm, 0x7c8, MASKDWORD, adc_smp->la_trig_sig_sel); + + } else { + + adc_smp->is_bb_trigger = 1; + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(1), 1); /*polling bit for BB ADC mode*/ + + if (adc_smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) { + + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(3), 1); /*polling bit for MAC trigger event*/ + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(7) | BIT(6), adc_smp->la_trig_sig_sel); + + if (adc_smp->la_trig_sig_sel == ADCSMP_TRIG_REG) + odm_set_mac_reg(p_dm_odm, 0x7c0, BIT(5), 1); /* manual trigger 0x7C0[5] = 0->1*/ + } + } + + reg_value = odm_get_bb_reg(p_dm_odm, 0x7c0, 0xff); + dbg_print("4. [Set MAC IQ dump] 0x7c0[7:0] = ((0x%x))\n", reg_value); +} + +void +phydm_la_mode_set_dma_type( + void *p_dm_void, + u8 la_dma_type +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + dbg_print("2. [LA mode DMA setting] Dma_type = ((%d))\n", la_dma_type); + + if (p_dm_odm->support_ic_type & ODM_N_ANTDIV_SUPPORT) + odm_set_bb_reg(p_dm_odm, 0x9a0, 0xf00, la_dma_type); /*0x9A0[11:8]*/ + else + odm_set_bb_reg(p_dm_odm, odm_adc_trigger_jaguar2, 0xf00, la_dma_type); /*0x95C[11:8]*/ +} + +void +phydm_adc_smp_start( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + u8 tmp_u1b; + u8 backup_DMA, while_cnt = 0; + u8 polling_ok = false, target_polling_bit; + + phydm_la_mode_bb_setting(p_dm_odm); + phydm_la_mode_set_dma_type(p_dm_odm, adc_smp->la_dma_type); + phydm_la_mode_set_trigger_time(p_dm_odm, adc_smp->la_trigger_time); + + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(p_dm_odm, 0xd00, BIT(26), 0x1); + else { /*for 8814A and 8822B?*/ + odm_write_1byte(p_dm_odm, 0x8b4, 0x80); + /* odm_set_bb_reg(p_dm_odm, 0x8b4, BIT7, 1); */ + } + + phydm_la_mode_set_mac_iq_dump(p_dm_odm); + + target_polling_bit = (adc_smp->is_bb_trigger) ? BIT(1) : BIT(2); + do { /*Polling time always use 100ms, when it exceed 2s, break while loop*/ + tmp_u1b = odm_read_1byte(p_dm_odm, 0x7c0); + + if (adc_smp->adc_smp_state != ADCSMP_STATE_SET) { + dbg_print("[state Error] adc_smp_state != ADCSMP_STATE_SET\n"); + break; + + } else if (tmp_u1b & target_polling_bit) { + ODM_delay_ms(100); + while_cnt = while_cnt + 1; + continue; + } else { + dbg_print("[LA Query OK] polling_bit=((0x%x))\n", target_polling_bit); + polling_ok = true; + if (p_dm_odm->support_ic_type & ODM_RTL8197F) + odm_set_bb_reg(p_dm_odm, 0x7c0, BIT(0), 0x0); + break; + } + } while (while_cnt < 20); + + if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) { + + if (polling_ok) + phydm_la_get_tx_pkt_buf(p_dm_odm); + else + dbg_print("[Polling timeout]\n"); + } + + if (adc_smp->adc_smp_state == ADCSMP_STATE_SET) + adc_smp->adc_smp_state = ADCSMP_STATE_QUERY; + + dbg_print("[LA mode] LA_pattern_count = ((%d))\n", adc_smp->la_count); + + adc_smp_stop(p_dm_odm); + + if (adc_smp->la_count == 0) { + dbg_print("LA Dump finished ---------->\n\n\n"); + phydm_release_bb_dbg_port(p_dm_odm); + + if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { + odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 0); + } + + } else { + adc_smp->la_count--; + dbg_print("LA Dump more ---------->\n\n\n"); + adc_smp_set(p_dm_odm, adc_smp->la_trig_mode, adc_smp->la_trig_sig_sel, adc_smp->la_dma_type, adc_smp->la_trigger_time, 0); + } + +} + +void +adc_smp_set( + void *p_dm_void, + u8 trig_mode, + u32 trig_sig_sel, + u8 dma_data_sig_sel, + u32 trigger_time, + u16 polling_time +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean is_set_success = true; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + + adc_smp->la_trig_mode = trig_mode; + adc_smp->la_trig_sig_sel = trig_sig_sel; + adc_smp->la_dma_type = dma_data_sig_sel; + adc_smp->la_trigger_time = trigger_time; + + if (adc_smp->adc_smp_state != ADCSMP_STATE_IDLE) + is_set_success = false; + else if (adc_smp->adc_smp_buf.length == 0) + is_set_success = phydm_la_buffer_allocate(p_dm_odm); + + if (is_set_success) { + adc_smp->adc_smp_state = ADCSMP_STATE_SET; + + dbg_print("[LA Set Success] LA_State=((%d))\n", adc_smp->adc_smp_state); + + phydm_adc_smp_start(p_dm_odm); + } else + dbg_print("[LA Set Fail] LA_State=((%d))\n", adc_smp->adc_smp_state); +} + +void +adc_smp_query( + void *p_dm_void, + void *output, + u32 out_len, + u32 *pused +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + u32 used = *pused; + u32 i; + /* struct timespec t; */ + /* rtw_get_current_timespec(&t); */ + + dbg_print("%s adc_smp_state %d", __func__, adc_smp->adc_smp_state); + + for (i = 0; i < (adc_smp_buf->length >> 2) - 2; i += 2) { + PHYDM_SNPRINTF((output + used, out_len - used, + "%08x%08x\n", adc_smp_buf->octet[i], adc_smp_buf->octet[i + 1])); + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\n")); + /* PHYDM_SNPRINTF((output+used, out_len-used, "\n[%lu.%06lu]\n", t.tv_sec, t.tv_nsec)); */ + *pused = used; +} + +s32 +adc_smp_get_sample_counts( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + + return (adc_smp_buf->length >> 2) - 2; +} + +s32 +adc_smp_query_single_data( + void *p_dm_void, + void *output, + u32 out_len, + u32 index +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + u32 used = 0; + + /* dbg_print("%s adc_smp_state %d\n", __func__, adc_smp->adc_smp_state); */ + if (adc_smp->adc_smp_state != ADCSMP_STATE_QUERY) { + PHYDM_SNPRINTF((output + used, out_len - used, + "Error: la data is not ready yet ...\n")); + return -1; + } + + if (index < ((adc_smp_buf->length >> 2) - 2)) { + PHYDM_SNPRINTF((output + used, out_len - used, "%08x%08x\n", + adc_smp_buf->octet[index], adc_smp_buf->octet[index + 1])); + } + return 0; +} + +void +adc_smp_stop( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + + adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; + dbg_print("[LA_Stop] LA_state = ((%d))\n", adc_smp->adc_smp_state); +} + +void +adc_smp_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + + adc_smp->adc_smp_state = ADCSMP_STATE_IDLE; + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + adc_smp_buf->start_pos = 0x30000; + adc_smp_buf->buffer_size = 0x10000; + } else if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + adc_smp_buf->start_pos = 0x20000; + adc_smp_buf->buffer_size = 0x20000; + } else if (p_dm_odm->support_ic_type & ODM_RTL8197F) { + adc_smp_buf->start_pos = 0x00000; + adc_smp_buf->buffer_size = 0x10000; + } else if (p_dm_odm->support_ic_type & ODM_RTL8821C) { + adc_smp_buf->start_pos = 0x8000; + adc_smp_buf->buffer_size = 0x8000; + } + +} + +void +adc_smp_de_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + struct _RT_ADCSMP_STRING *adc_smp_buf = &(adc_smp->adc_smp_buf); + + adc_smp_stop(p_dm_odm); + + if (adc_smp_buf->length != 0x0) { + odm_free_memory(p_dm_odm, adc_smp_buf->octet, adc_smp_buf->length); + adc_smp_buf->length = 0x0; + } +} + + +void +phydm_la_mode_bb_setting( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + + u8 trig_mode = adc_smp->la_trig_mode; + u32 trig_sig_sel = adc_smp->la_trig_sig_sel; + u32 dbg_port = adc_smp->la_dbg_port; + u8 is_trigger_edge = adc_smp->la_trigger_edge; + u8 sampling_rate = adc_smp->la_smp_rate; + u32 dbg_port_header_sel = 0; + + dbg_print("1. [LA mode bb_setting] trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x))\n", + trig_mode, dbg_port, is_trigger_edge, sampling_rate, trig_sig_sel); + + if (trig_mode == PHYDM_MAC_TRIG) + trig_sig_sel = 0; /*ignore this setting*/ + + /*set BB debug port*/ + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, dbg_port)) { + dbg_print("Set dbg_port((0x%x)) success\n", dbg_port); + } + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + if (trig_mode == PHYDM_ADC_RF0_TRIG) + dbg_port_header_sel = 9; /*DBGOUT_RFC_a[31:0]*/ + else if (trig_mode == PHYDM_ADC_RF1_TRIG) + dbg_port_header_sel = 8; /*DBGOUT_RFC_b[31:0]*/ + else + dbg_port_header_sel = 0; + + phydm_bb_dbg_port_header_sel(p_dm_odm, dbg_port_header_sel); + + + odm_set_bb_reg(p_dm_odm, 0x95C, 0x1f, trig_sig_sel); /*0x95C[4:0], BB debug port bit*/ + odm_set_bb_reg(p_dm_odm, 0x95C, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ + odm_set_bb_reg(p_dm_odm, 0x95c, 0xe0, sampling_rate); + /* (0:) '80MHz' + (1:) '40MHz' + (2:) '20MHz' + (3:) '10MHz' + (4:) '5MHz' + (5:) '2.5MHz' + (6:) '1.25MHz' + (7:) '160MHz (for BW160 ic)' + */ + if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (p_dm_odm->cut_version >= ODM_CUT_B)) { + odm_set_bb_reg(p_dm_odm, 0x95c, BIT(23), 1); + } + } else { + odm_set_bb_reg(p_dm_odm, 0x9a0, 0x1f, trig_sig_sel); /*0x9A0[4:0], BB debug port bit*/ + + odm_set_bb_reg(p_dm_odm, 0x9A0, BIT(31), is_trigger_edge); /*0: posedge, 1: negedge*/ + odm_set_bb_reg(p_dm_odm, 0x9A0, 0xe0, sampling_rate); + /* (0:) '80MHz' + (1:) '40MHz' + (2:) '20MHz' + (3:) '10MHz' + (4:) '5MHz' + (5:) '2.5MHz' + (6:) '1.25MHz' + (7:) '160MHz (for BW160 ic)' + */ + } +} + +void +phydm_la_mode_set_trigger_time( + void *p_dm_void, + u32 trigger_time_mu_sec +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 trigger_time_unit_num; + u32 time_unit = 0; + + if (trigger_time_mu_sec < 128) { + time_unit = 0; /*unit: 1mu sec*/ + } else if (trigger_time_mu_sec < 256) { + time_unit = 1; /*unit: 2mu sec*/ + } else if (trigger_time_mu_sec < 512) { + time_unit = 2; /*unit: 4mu sec*/ + } else if (trigger_time_mu_sec < 1024) { + time_unit = 3; /*unit: 8mu sec*/ + } else if (trigger_time_mu_sec < 2048) { + time_unit = 4; /*unit: 16mu sec*/ + } else if (trigger_time_mu_sec < 4096) { + time_unit = 5; /*unit: 32mu sec*/ + } else if (trigger_time_mu_sec < 8192) { + time_unit = 6; /*unit: 64mu sec*/ + } + + trigger_time_unit_num = (u8)(trigger_time_mu_sec >> time_unit); + + dbg_print("3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n", trigger_time_unit_num, time_unit); + + odm_set_mac_reg(p_dm_odm, 0x7cc, BIT(20) | BIT(19) | BIT(18), time_unit); + odm_set_mac_reg(p_dm_odm, 0x7c0, 0x7f00, (trigger_time_unit_num & 0x7f)); +} + +void +phydm_lamode_trigger_setting( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _RT_ADCSMP *adc_smp = &(p_dm_odm->adcsmp); + u8 trig_mode, dma_data_sig_sel; + u32 trig_sig_sel; + boolean is_enable_la_mode, is_trigger_edge; + u32 dbg_port, trigger_time_mu_sec; + u32 mac_ref_signal_mask; + u8 sampling_rate = 0, i; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + + if (p_dm_odm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) { + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + is_enable_la_mode = (boolean)var1[0]; + /*dbg_print("echo cmd input_num = %d\n", input_num);*/ + + if ((strcmp(input[1], help) == 0)) { + PHYDM_SNPRINTF((output + used, out_len - used, "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {polling_time/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n")); + /**/ + } else if ((is_enable_la_mode == 1)) { + + PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]); + + trig_mode = (u8)var1[1]; + + if (trig_mode == PHYDM_MAC_TRIG) + PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]); + else + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + trig_sig_sel = var1[2]; + + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]); + PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]); + PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]); + PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]); + PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]); + PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]); + + dma_data_sig_sel = (u8)var1[3]; + trigger_time_mu_sec = var1[4]; /*unit: us*/ + + adc_smp->la_mac_ref_mask = var1[5]; + adc_smp->la_dbg_port = var1[6]; + adc_smp->la_trigger_edge = (u8) var1[7]; + adc_smp->la_smp_rate = (u8)(var1[8] & 0x7); + adc_smp->la_count = var1[9]; + + dbg_print("echo lamode %d %d %d %d %d %d %x %d %d %d\n", var1[0], var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], var1[7], var1[8], var1[9]); + + PHYDM_SNPRINTF((output + used, out_len - used, "a.En= ((1)), b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n", trig_mode, trig_sig_sel, dma_data_sig_sel)); + PHYDM_SNPRINTF((output + used, out_len - used, "e.Trig_Time = ((%dus)), f.mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n", trigger_time_mu_sec, adc_smp->la_mac_ref_mask, adc_smp->la_dbg_port)); + PHYDM_SNPRINTF((output + used, out_len - used, "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n", adc_smp->la_trigger_edge, (80 >> adc_smp->la_smp_rate), adc_smp->la_count)); + + adc_smp_set(p_dm_odm, trig_mode, trig_sig_sel, dma_data_sig_sel, trigger_time_mu_sec, 0); + + } else { + adc_smp_stop(p_dm_odm); + PHYDM_SNPRINTF((output + used, out_len - used, "Disable LA mode\n")); + } + } +} + diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_adc_sampling.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_adc_sampling.h new file mode 100644 index 000000000000..06e3d10c7d3b --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_adc_sampling.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_ADCSMP_H +#define __INC_ADCSMP_H + +#define DYNAMIC_LA_MODE "1.0" /*2016.07.15 Dino */ + + +struct _RT_ADCSMP_STRING { + u32 *octet; + u32 length; + u32 buffer_size; + u32 start_pos; +}; + +enum rt_adcsmp_trig_sel { + PHYDM_ADC_BB_TRIG = 0, + PHYDM_ADC_MAC_TRIG = 1, + PHYDM_ADC_RF0_TRIG = 2, + PHYDM_ADC_RF1_TRIG = 3, + PHYDM_MAC_TRIG = 4 +}; + +enum rt_adcsmp_trig_sig_sel { + ADCSMP_TRIG_CRCOK = 0, + ADCSMP_TRIG_CRCFAIL = 1, + ADCSMP_TRIG_CCA = 2, + ADCSMP_TRIG_REG = 3 +}; + +enum rt_adcsmp_state { + ADCSMP_STATE_IDLE = 0, + ADCSMP_STATE_SET = 1, + ADCSMP_STATE_QUERY = 2 +}; + +struct _RT_ADCSMP { + struct _RT_ADCSMP_STRING adc_smp_buf; + enum rt_adcsmp_state adc_smp_state; + u8 la_trig_mode; + u32 la_trig_sig_sel; + u8 la_dma_type; + u32 la_trigger_time; + u32 la_mac_ref_mask; + u32 la_dbg_port; + u8 la_trigger_edge; + u8 la_smp_rate; + u32 la_count; + u8 is_bb_trigger; + u8 la_work_item_index; +}; + +void +adc_smp_set( + void *p_dm_void, + u8 trig_mode, + u32 trig_sig_sel, + u8 dma_data_sig_sel, + u32 trigger_time, + u16 polling_time +); + +void +adc_smp_query( + void *p_dm_void, + void *output, + u32 out_len, + u32 *pused +); + +s32 +adc_smp_get_sample_counts( + void *p_dm_void +); + +s32 +adc_smp_query_single_data( + void *p_dm_void, + void *output, + u32 out_len, + u32 index +); + +void +adc_smp_stop( + void *p_dm_void +); + +void +adc_smp_init( + void *p_dm_void +); + +void +adc_smp_de_init( + void *p_dm_void +); + +void +phydm_la_mode_bb_setting( + void *p_dm_void +); + +void +phydm_la_mode_set_trigger_time( + void *p_dm_void, + u32 trigger_time_mu_sec +); + +void +phydm_lamode_trigger_setting( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_antdiv.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_antdiv.c new file mode 100644 index 000000000000..3cb26dd404d6 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_antdiv.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +odm_ant_div_reset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->ant_div_type == S0S1_SW_ANTDIV) { + } + +} + +void +odm_antenna_diversity_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +} + +void +odm_antenna_diversity( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + if (p_dm_odm->mp_mode == true) + return; + +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_antdiv.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_antdiv.h new file mode 100644 index 000000000000..69ae5fe0ad3a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_antdiv.h @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDIV_H__ +#define __PHYDMANTDIV_H__ + +/*#define ANTDIV_VERSION "2.0" //2014.11.04*/ +/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ +/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ +/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ +/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ +/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, + because antenna diversity only works when BT is disable or radio off*/ +/*#define ANTDIV_VERSION "3.4" 2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ +/*#define ANTDIV_VERSION "3.5" 2015.10.07 Stanley Always check antenna detection result from BT-coex. for 8723B, not from PHYDM*/ +/*#define ANTDIV_VERSION "3.6"*/ /*2015.11.16 Stanley */ +/*#define ANTDIV_VERSION "3.7"*/ /*2015.11.20 Dino Add SmartAnt FAT Patch */ +/*#define ANTDIV_VERSION "3.8" 2015.12.21 Dino, Add SmartAnt dynamic training packet num */ +#define ANTDIV_VERSION "3.9" /*2016.01.05 Dino, Add SmartAnt cmd for converting single & two smtant, and add cmd for adjust truth table */ + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + +#define ANTDIV_INIT 0xff +#define MAIN_ANT 1 /*ant A or ant Main or S1*/ +#define AUX_ANT 2 /*AntB or ant Aux or S0*/ +#define MAX_ANT 3 /* 3 for AP using*/ + +#define ANT1_2G 0 /* = ANT2_5G for 8723D BTG S1 RX S0S1 diversity for 8723D, TX fixed at S1 */ +#define ANT2_2G 1 /* = ANT1_5G for 8723D BTG S0 RX S0S1 diversity for 8723D, TX fixed at S1 */ +/*smart antenna*/ +#define SUPPORT_RF_PATH_NUM 4 +#define SUPPORT_BEAM_PATTERN_NUM 4 +#define NUM_ANTENNA_8821A 2 + +#define SUPPORT_BEAM_SET_PATTERN_NUM 16 + +#define NO_FIX_TX_ANT 0 +#define FIX_TX_AT_MAIN 1 +#define FIX_AUX_AT_MAIN 2 + +/* Antenna Diversty Control type */ +#define ODM_AUTO_ANT 0 +#define ODM_FIX_MAIN_ANT 1 +#define ODM_FIX_AUX_ANT 2 + +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8195A) +#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814B) +#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT | ODM_AC_ANTDIV_SUPPORT) +#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E | ODM_RTL8192E) +#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821 | ODM_RTL8822B) + +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8881A | ODM_RTL8188F | ODM_RTL8723D) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821 | ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821C) + +#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E) + +#define ODM_ANTDIV_2G BIT(0) +#define ODM_ANTDIV_5G BIT(1) + +#define ANTDIV_ON 1 +#define ANTDIV_OFF 0 + +#define FAT_ON 1 +#define FAT_OFF 0 + +#define TX_BY_DESC 1 +#define TX_BY_REG 0 + +#define RSSI_METHOD 0 +#define EVM_METHOD 1 +#define CRC32_METHOD 2 + +#define INIT_ANTDIV_TIMMER 0 +#define CANCEL_ANTDIV_TIMMER 1 +#define RELEASE_ANTDIV_TIMMER 2 + +#define CRC32_FAIL 1 +#define CRC32_OK 0 + +#define evm_rssi_th_high 25 +#define evm_rssi_th_low 20 + +#define NORMAL_STATE_MIAN 1 +#define NORMAL_STATE_AUX 2 +#define TRAINING_STATE 3 + +#define FORCE_RSSI_DIFF 10 + +#define CSI_ON 1 +#define CSI_OFF 0 + +#define DIVON_CSIOFF 1 +#define DIVOFF_CSION 2 + +#define BDC_DIV_TRAIN_STATE 0 +#define bdc_bfer_train_state 1 +#define BDC_DECISION_STATE 2 +#define BDC_BF_HOLD_STATE 3 +#define BDC_DIV_HOLD_STATE 4 + +#define BDC_MODE_1 1 +#define BDC_MODE_2 2 +#define BDC_MODE_3 3 +#define BDC_MODE_4 4 +#define BDC_MODE_NULL 0xff + +/*SW S0S1 antenna diversity*/ +#define SWAW_STEP_INIT 0xff +#define SWAW_STEP_PEEK 0 +#define SWAW_STEP_DETERMINE 1 + +#define RSSI_CHECK_RESET_PERIOD 10 +#define RSSI_CHECK_THRESHOLD 50 + +/*Hong Lin Smart antenna*/ +#define HL_SMTANT_2WIRE_DATA_LEN 24 + +/* 1 ============================================================ + * 1 structure + * 1 ============================================================ */ + +struct _sw_antenna_switch_ { + u8 double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ + u8 try_flag; + s32 pre_rssi; + u8 cur_antenna; + u8 pre_antenna; + u8 rssi_trying; + u8 reset_idx; + u8 train_time; + u8 train_time_flag; /*base on RSSI difference between two antennas*/ + struct phydm_timer_list phydm_sw_antenna_switch_timer; + u32 pkt_cnt_sw_ant_div_by_ctrl_frame; + boolean is_sw_ant_div_by_ctrl_frame; + + /* AntDect (Before link Antenna Switch check) need to be moved*/ + u16 single_ant_counter; + u16 dual_ant_counter; + u16 aux_fail_detec_counter; + u16 retry_counter; + u8 swas_no_link_state; + u32 swas_no_link_bk_reg948; + boolean ANTA_ON; /*To indicate ant A is or not*/ + boolean ANTB_ON; /*To indicate ant B is on or not*/ + boolean pre_aux_fail_detec; + boolean rssi_ant_dect_result; + u8 ant_5g; + u8 ant_2g; + +}; + +struct _FAST_ANTENNA_TRAINNING_ { + u8 bssid[6]; + u8 antsel_rx_keep_0; + u8 antsel_rx_keep_1; + u8 antsel_rx_keep_2; + u8 antsel_rx_keep_3; + u32 ant_sum_rssi[7]; + u32 ant_rssi_cnt[7]; + u32 ant_ave_rssi[7]; + u8 fat_state; + u32 train_idx; + u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_sum[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_sum_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 main_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u16 aux_ant_cnt_cck[ODM_ASSOCIATE_ENTRY_NUM]; + u8 rx_idle_ant; + u8 ant_div_on_off; + boolean is_become_linked; + u32 min_max_rssi; + u8 idx_ant_div_counter_2g; + u8 idx_ant_div_counter_5g; + u8 ant_div_2g_5g; + + u32 cck_ctrl_frame_cnt_main; + u32 cck_ctrl_frame_cnt_aux; + u32 ofdm_ctrl_frame_cnt_main; + u32 ofdm_ctrl_frame_cnt_aux; + u32 main_ant_ctrl_frame_sum; + u32 aux_ant_ctrl_frame_sum; + u32 main_ant_ctrl_frame_cnt; + u32 aux_ant_ctrl_frame_cnt; + u8 b_fix_tx_ant; + boolean fix_ant_bfee; + boolean enable_ctrl_frame_antdiv; + boolean use_ctrl_frame_antdiv; + u8 hw_antsw_occur; + u8 *p_force_tx_ant_by_desc; + u8 force_tx_ant_by_desc; /*A temp value, will hook to driver team's outer parameter later*/ + u8 *p_default_s0_s1; + u8 default_s0_s1; +}; + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + +enum fat_state_e /*Fast antenna training*/ +{ + FAT_BEFORE_LINK_STATE = 0, + FAT_PREPARE_STATE = 1, + FAT_TRAINING_STATE = 2, + FAT_DECISION_STATE = 3 +}; + +enum ant_div_type_e { + NO_ANTDIV = 0xFF, + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + FIXED_HW_ANTDIV = 0x03, + CG_TRX_SMART_ANTDIV = 0x04, + CGCS_RX_SW_ANTDIV = 0x05, + S0S1_SW_ANTDIV = 0x06, /*8723B intrnal switch S0 S1*/ + S0S1_TRX_HW_ANTDIV = 0x07, /*TRX S0S1 diversity for 8723D*/ + HL_SW_SMART_ANT_TYPE1 = 0x10, /*Hong-Lin Smart antenna use for 8821AE which is a 2 ant. entitys, and each ant. is equipped with 4 antenna patterns*/ + HL_SW_SMART_ANT_TYPE2 = 0x11 /*Hong-Bo Smart antenna use for 8822B which is a 2 ant. entitys*/ +}; + +/* 1 ============================================================ + * 1 function prototype + * 1 ============================================================ */ + +void +odm_stop_antenna_switch_dm( + void *p_dm_void +); + +void +phydm_enable_antenna_diversity( + void *p_dm_void +); + +void +odm_set_ant_config( + void *p_dm_void, + u8 ant_setting /* 0=A, 1=B, 2=C, .... */ +); + +#define sw_ant_div_rest_after_link odm_sw_ant_div_rest_after_link + +void odm_sw_ant_div_rest_after_link( + void *p_dm_void +); + + +void +odm_ant_div_reset( + void *p_dm_void +); + +void +odm_antenna_diversity_init( + void *p_dm_void +); + +void +odm_antenna_diversity( + void *p_dm_void +); + +#endif /*#ifndef __ODMANTDIV_H__*/ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_beamforming.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_beamforming.h new file mode 100644 index 000000000000..cd6856b82f0a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_beamforming.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_PHYDM_BEAMFORMING_H +#define __INC_PHYDM_BEAMFORMING_H + +/*Beamforming Related*/ +#include "txbf/haltxbfjaguar.h" + +#define beamforming_gid_paid(adapter, p_tcb) +#define phydm_acting_determine(p_dm_odm, type) false +#define beamforming_enter(p_dm_odm, sta_idx) +#define beamforming_leave(p_dm_odm, RA) +#define beamforming_end_fw(p_dm_odm) +#define beamforming_control_v1(p_dm_odm, RA, AID, mode, BW, rate) true +#define beamforming_control_v2(p_dm_odm, idx, mode, BW, period) true +#define phydm_beamforming_end_sw(p_dm_odm, _status) +#define beamforming_timer_callback(p_dm_odm) +#define phydm_beamforming_init(p_dm_odm) +#define phydm_beamforming_control_v2(p_dm_odm, _idx, _mode, _BW, _period) false +#define beamforming_watchdog(p_dm_odm) +#define phydm_beamforming_watchdog(p_dm_odm) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_ccx.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_ccx.c new file mode 100644 index 000000000000..3184a69f6067 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_ccx.c @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/*Set NHM period, threshold, disable ignore cca or not, disable ignore txon or not*/ +void +phydm_nhm_setting( + void *p_dm_void, + u8 nhm_setting +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + if (nhm_setting == SET_NHM_SETTING) { + + /*Set inexclude_cca, inexclude_txon*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->nhm_inexclude_cca); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->nhm_inexclude_txon); + + /*Set NHM period*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); + + /*Set NHM threshold*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th[10]); + + /*CCX EN*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8), CCX_EN); + + } else if (nhm_setting == STORE_NHM_SETTING) { + + /*Store pervious disable_ignore_cca, disable_ignore_txon*/ + ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9)); + ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10)); + + /*Store pervious NHM period*/ + ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD); + + /*Store NHM threshold*/ + ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0); + ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1); + ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2); + ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3); + ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0); + ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1); + ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2); + ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3); + ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0); + ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2); + ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3); + } else if (nhm_setting == RESTORE_NHM_SETTING) { + + /*Set disable_ignore_cca, disable_ignore_txon*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9), ccx_info->NHM_inexclude_cca_restore); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10), ccx_info->NHM_inexclude_txon_restore); + + /*Set NHM period*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD, ccx_info->NHM_period); + + /*Set NHM threshold*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0, ccx_info->NHM_th_restore[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1, ccx_info->NHM_th_restore[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2, ccx_info->NHM_th_restore[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3, ccx_info->NHM_th_restore[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0, ccx_info->NHM_th_restore[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1, ccx_info->NHM_th_restore[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2, ccx_info->NHM_th_restore[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3, ccx_info->NHM_th_restore[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, ccx_info->NHM_th_restore[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2, ccx_info->NHM_th_restore[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3, ccx_info->NHM_th_restore[10]); + } else + return; + } + + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + if (nhm_setting == SET_NHM_SETTING) { + + /*Set disable_ignore_cca, disable_ignore_txon*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->nhm_inexclude_cca); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->nhm_inexclude_txon); + + /*Set NHM period*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period); + + /*Set NHM threshold*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th[10]); + + /*CCX EN*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(8), CCX_EN); + } else if (nhm_setting == STORE_NHM_SETTING) { + + /*Store pervious disable_ignore_cca, disable_ignore_txon*/ + ccx_info->NHM_inexclude_cca_restore = (enum nhm_inexclude_cca)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9)); + ccx_info->NHM_inexclude_txon_restore = (enum nhm_inexclude_txon)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10)); + + /*Store pervious NHM period*/ + ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD); + + /*Store NHM threshold*/ + ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0); + ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1); + ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2); + ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3); + ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0); + ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1); + ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2); + ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3); + ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0); + ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2); + ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3); + + } else if (nhm_setting == RESTORE_NHM_SETTING) { + + /*Set disable_ignore_cca, disable_ignore_txon*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(9), ccx_info->NHM_inexclude_cca_restore); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(10), ccx_info->NHM_inexclude_txon_restore); + + /*Set NHM period*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKHWORD, ccx_info->NHM_period_restore); + + /*Set NHM threshold*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0, ccx_info->NHM_th_restore[0]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1, ccx_info->NHM_th_restore[1]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2, ccx_info->NHM_th_restore[2]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3, ccx_info->NHM_th_restore[3]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0, ccx_info->NHM_th_restore[4]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1, ccx_info->NHM_th_restore[5]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2, ccx_info->NHM_th_restore[6]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3, ccx_info->NHM_th_restore[7]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH8_11N, MASKBYTE0, ccx_info->NHM_th_restore[8]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2, ccx_info->NHM_th_restore[9]); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3, ccx_info->NHM_th_restore[10]); + } else + return; + + } +} + +void +phydm_nhm_trigger( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + /*Trigger NHM*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1); + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + /*Trigger NHM*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1); + } +} + +void +phydm_get_nhm_result( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11AC); + ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT11_TO_CNT8_11AC); + ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + + /*Get NHM duration*/ + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC); + ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); + + } + + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT_11N); + ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0); + ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8); + ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT9_TO_CNT8_11N); + ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24); + + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16); + ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24); + + /*Get NHM duration*/ + value32 = odm_read_4byte(p_dm_odm, ODM_REG_NHM_CNT10_TO_CNT11_11N); + ccx_info->NHM_duration = (u16)(value32 & MASKLWORD); + + } + +} + +boolean +phydm_check_nhm_ready( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32 = 0; + u8 i; + boolean ret = false; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); + + for (i = 0; i < 200; i++) { + + ODM_delay_ms(1); + if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { + ret = 1; + break; + } + } + } + + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); + + for (i = 0; i < 200; i++) { + + ODM_delay_ms(1); + if (odm_get_bb_reg(p_dm_odm, ODM_REG_NHM_DUR_READY_11AC, BIT(17))) { + ret = 1; + break; + } + } + } + return ret; +} + +void +phydm_store_nhm_setting( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + } +} + +void +phydm_clm_setting( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(8), 0x1); /*Enable CCX for CLM*/ + + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + + odm_set_bb_reg(p_dm_odm, ODM_REG_CCX_PERIOD_11N, MASKLWORD, ccx_info->CLM_period); /*4us sample 1 time*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(8), 0x1); /*Enable CCX for CLM*/ + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM period = %dus\n", __func__, ccx_info->CLM_period * 4)); + +} + +void +phydm_clm_trigger( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x0); /*Trigger CLM*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11AC, BIT(0), 0x1); + } else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) { + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x0); /*Trigger CLM*/ + odm_set_bb_reg(p_dm_odm, ODM_REG_CLM_11N, BIT(0), 0x1); + } +} + +boolean +phydm_check_cl_mready( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 value32 = 0; + boolean ret = false; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*make sure CLM calc is ready*/ + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_READY_11N, MASKDWORD); /*make sure CLM calc is ready*/ + + if ((p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16))) + ret = true; + else if ((p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) && (value32 & BIT(16))) + ret = true; + else + ret = false; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); + + return ret; +} + +void +phydm_get_cl_mresult( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info; + + u32 value32 = 0; + u16 results = 0; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11AC, MASKDWORD); /*read CLM calc result*/ + else if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES) + value32 = odm_get_bb_reg(p_dm_odm, ODM_REG_CLM_RESULT_11N, MASKDWORD); /*read CLM calc result*/ + + ccx_info->CLM_result = (u16)(value32 & MASKLWORD); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CCX, ODM_DBG_LOUD, ("[%s] : CLM result = %dus\n", __func__, ccx_info->CLM_result * 4)); + +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_ccx.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_ccx.h new file mode 100644 index 000000000000..90955039dcab --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_ccx.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __PHYDMCCX_H__ +#define __PHYDMCCX_H__ + +#define CCX_EN 1 + +#define SET_NHM_SETTING 0 +#define STORE_NHM_SETTING 1 +#define RESTORE_NHM_SETTING 2 + +/* +#define NHM_EXCLUDE_CCA 0 +#define NHM_INCLUDE_CCA 1 +#define NHM_EXCLUDE_TXON 0 +#define NHM_INCLUDE_TXON 1 +*/ + +enum nhm_inexclude_cca { + NHM_EXCLUDE_CCA, + NHM_INCLUDE_CCA +}; + +enum nhm_inexclude_txon { + NHM_EXCLUDE_TXON, + NHM_INCLUDE_TXON +}; + +struct _CCX_INFO { + + /*Settings*/ + u8 NHM_th[11]; + u16 NHM_period; /* 4us per unit */ + u16 CLM_period; /* 4us per unit */ + enum nhm_inexclude_txon nhm_inexclude_txon; + enum nhm_inexclude_cca nhm_inexclude_cca; + + /*Previous Settings*/ + u8 NHM_th_restore[11]; + u16 NHM_period_restore; /* 4us per unit */ + u16 CLM_period_restore; /* 4us per unit */ + enum nhm_inexclude_txon NHM_inexclude_txon_restore; + enum nhm_inexclude_cca NHM_inexclude_cca_restore; + + /*Report*/ + u8 NHM_result[12]; + u16 NHM_duration; + u16 CLM_result; + + boolean echo_NHM_en; + boolean echo_CLM_en; + u8 echo_IGI; + +}; + +/*NHM*/ + +void +phydm_nhm_setting( + void *p_dm_void, + u8 nhm_setting +); + +void +phydm_nhm_trigger( + void *p_dm_void +); + +void +phydm_get_nhm_result( + void *p_dm_void +); + +boolean +phydm_check_nhm_ready( + void *p_dm_void +); + +/*CLM*/ + +void +phydm_clm_setting( + void *p_dm_void +); + +void +phydm_clm_trigger( + void *p_dm_void +); + +boolean +phydm_check_cl_mready( + void *p_dm_void +); + +void +phydm_get_cl_mresult( + void *p_dm_void +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_cfotracking.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_cfotracking.c new file mode 100644 index 000000000000..a8edb01ade91 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_cfotracking.c @@ -0,0 +1,317 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +odm_set_crystal_cap( + void *p_dm_void, + u8 crystal_cap +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct _ADAPTER *adapter = p_dm_odm->adapter;/* JJ modified 20161115 */ + + if (p_cfo_track->crystal_cap == crystal_cap) + return; + + p_cfo_track->crystal_cap = crystal_cap; + + if (p_dm_odm->support_ic_type & (ODM_RTL8188E | ODM_RTL8188F)) { + /* write 0x24[22:17] = 0x24[16:11] = crystal_cap */ + crystal_cap = crystal_cap & 0x3F; + odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x007ff800, (crystal_cap | (crystal_cap << 6))); + } else if (p_dm_odm->support_ic_type & ODM_RTL8812) { + /* write 0x2C[30:25] = 0x2C[24:19] = crystal_cap */ + crystal_cap = crystal_cap & 0x3F; + odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); + } else if ((p_dm_odm->support_ic_type & (ODM_RTL8703B | ODM_RTL8723B | ODM_RTL8192E | ODM_RTL8821 | ODM_RTL8723D))) { + /* 0x2C[23:18] = 0x2C[17:12] = crystal_cap */ + crystal_cap = crystal_cap & 0x3F; + odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); + } else if (p_dm_odm->support_ic_type & ODM_RTL8814A) { + /* write 0x2C[26:21] = 0x2C[20:15] = crystal_cap */ + crystal_cap = crystal_cap & 0x3F; + odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); + } else if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C)) { + /* write 0x24[30:25] = 0x28[6:1] = crystal_cap */ + crystal_cap = crystal_cap & 0x3F; + odm_set_bb_reg(p_dm_odm, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); + odm_set_bb_reg(p_dm_odm, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_set_crystal_cap(): Use default setting.\n")); + odm_set_bb_reg(p_dm_odm, REG_MAC_PHY_CTRL, 0xFFF000, (crystal_cap | (crystal_cap << 6))); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_set_crystal_cap(): crystal_cap = 0x%x\n", crystal_cap)); +} + +u8 +odm_get_default_crytaltal_cap( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 crystal_cap = 0x20; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + crystal_cap = p_hal_data->crystal_cap; + crystal_cap = crystal_cap & 0x3f; + + return crystal_cap; +} + +void +odm_set_atc_status( + void *p_dm_void, + boolean atc_status +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + + if (p_cfo_track->is_atc_status == atc_status) + return; + + odm_set_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm), atc_status); + p_cfo_track->is_atc_status = atc_status; +} + +boolean +odm_get_atc_status( + void *p_dm_void +) +{ + boolean atc_status; + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + atc_status = (boolean)odm_get_bb_reg(p_dm_odm, ODM_REG(BB_ATC, p_dm_odm), ODM_BIT(BB_ATC, p_dm_odm)); + return atc_status; +} + +void +odm_cfo_tracking_reset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + + p_cfo_track->def_x_cap = odm_get_default_crytaltal_cap(p_dm_odm); + p_cfo_track->is_adjust = true; + + if (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) { + odm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap - 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); + } else if (p_cfo_track->crystal_cap < p_cfo_track->def_x_cap) { + odm_set_crystal_cap(p_dm_odm, p_cfo_track->crystal_cap + 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("odm_cfo_tracking_reset(): approch default value (0x%x)\n", p_cfo_track->crystal_cap)); + } + + odm_set_atc_status(p_dm_odm, true); +} + +void +odm_cfo_tracking_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + + p_cfo_track->def_x_cap = p_cfo_track->crystal_cap = odm_get_default_crytaltal_cap(p_dm_odm); + p_cfo_track->is_atc_status = odm_get_atc_status(p_dm_odm); + p_cfo_track->is_adjust = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========>\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): is_atc_status = %d, crystal_cap = 0x%x\n", p_cfo_track->is_atc_status, p_cfo_track->def_x_cap)); + + + /* Crystal cap. control by WiFi */ + if (p_dm_odm->support_ic_type & ODM_RTL8821C) + odm_set_bb_reg(p_dm_odm, 0x10, 0x40, 0x1); +} + +void +odm_cfo_tracking( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + s32 CFO_ave = 0; + u32 CFO_rpt_sum, cfo_khz_avg[4] = {0}; + s32 CFO_ave_diff; + s8 crystal_cap = p_cfo_track->crystal_cap; + u8 adjust_xtal = 1, i, valid_path_cnt = 0; + + /* 4 Support ability */ + if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Return: support_ability ODM_BB_CFO_TRACKING is disabled\n")); + return; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking()=========>\n")); + + if (!p_dm_odm->is_linked || !p_dm_odm->is_one_entry_only) { + /* 4 No link or more than one entry */ + odm_cfo_tracking_reset(p_dm_odm); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Reset: is_linked = %d, is_one_entry_only = %d\n", + p_dm_odm->is_linked, p_dm_odm->is_one_entry_only)); + } else { + /* 3 1. CFO Tracking */ + /* 4 1.1 No new packet */ + if (p_cfo_track->packet_count == p_cfo_track->packet_count_pre) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): packet counter doesn't change\n")); + return; + } + p_cfo_track->packet_count_pre = p_cfo_track->packet_count; + + /* 4 1.2 Calculate CFO */ + for (i = 0; i < p_dm_odm->num_rf_path; i++) { + + if (p_cfo_track->CFO_cnt[i] == 0) + continue; + + valid_path_cnt++; + CFO_rpt_sum = (u32)((p_cfo_track->CFO_tail[i] < 0) ? (0 - p_cfo_track->CFO_tail[i]) : p_cfo_track->CFO_tail[i]); + cfo_khz_avg[i] = CFO_HW_RPT_2_MHZ(CFO_rpt_sum) / p_cfo_track->CFO_cnt[i]; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("[path %d] CFO_rpt_sum = (( %d )), CFO_cnt = (( %d )) , CFO_avg= (( %s%d )) kHz\n", + i, CFO_rpt_sum, p_cfo_track->CFO_cnt[i], ((p_cfo_track->CFO_tail[i] < 0) ? "-" : " "), cfo_khz_avg[i])); + } + + for (i = 0; i < valid_path_cnt; i++) { + + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("path [%d], p_cfo_track->CFO_tail = %d\n", i, p_cfo_track->CFO_tail[i])); */ + if (p_cfo_track->CFO_tail[i] < 0) { + CFO_ave += (0 - (s32)cfo_khz_avg[i]); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("CFO_ave = %d\n", CFO_ave)); */ + } else + CFO_ave += (s32)cfo_khz_avg[i]; + } + + if (valid_path_cnt >= 2) + CFO_ave = CFO_ave / valid_path_cnt; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("valid_path_cnt = ((%d)), CFO_ave = ((%d kHz))\n", valid_path_cnt, CFO_ave)); + + /*reset counter*/ + for (i = 0; i < p_dm_odm->num_rf_path; i++) { + p_cfo_track->CFO_tail[i] = 0; + p_cfo_track->CFO_cnt[i] = 0; + } + + /* 4 1.3 Avoid abnormal large CFO */ + CFO_ave_diff = (p_cfo_track->CFO_ave_pre >= CFO_ave) ? (p_cfo_track->CFO_ave_pre - CFO_ave) : (CFO_ave - p_cfo_track->CFO_ave_pre); + if (CFO_ave_diff > 20 && p_cfo_track->large_cfo_hit == 0 && !p_cfo_track->is_adjust) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): first large CFO hit\n")); + p_cfo_track->large_cfo_hit = 1; + return; + } else + p_cfo_track->large_cfo_hit = 0; + p_cfo_track->CFO_ave_pre = CFO_ave; + + /* 4 1.4 Dynamic Xtal threshold */ + if (p_cfo_track->is_adjust == false) { + if (CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) + p_cfo_track->is_adjust = true; + } else { + if (CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) + p_cfo_track->is_adjust = false; + } + + /* 4 1.5 BT case: Disable CFO tracking */ + if (p_dm_odm->is_bt_enabled) { + p_cfo_track->is_adjust = false; + odm_set_crystal_cap(p_dm_odm, p_cfo_track->def_x_cap); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable CFO tracking for BT!!\n")); + } + + /* 4 1.7 Adjust Crystal Cap. */ + if (p_cfo_track->is_adjust) { + if (CFO_ave > CFO_TH_XTAL_LOW) + crystal_cap = crystal_cap + adjust_xtal; + else if (CFO_ave < (-CFO_TH_XTAL_LOW)) + crystal_cap = crystal_cap - adjust_xtal; + + if (crystal_cap > 0x3f) + crystal_cap = 0x3f; + else if (crystal_cap < 0) + crystal_cap = 0; + + odm_set_crystal_cap(p_dm_odm, (u8)crystal_cap); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", + p_cfo_track->crystal_cap, p_cfo_track->def_x_cap)); + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + return; + + /* 3 2. Dynamic ATC switch */ + if (CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) { + odm_set_atc_status(p_dm_odm, false); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Disable ATC!!\n")); + } else { + odm_set_atc_status(p_dm_odm, true); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_cfo_tracking(): Enable ATC!!\n")); + } + } +} + +void +odm_parsing_cfo( + void *p_dm_void, + void *p_pktinfo_void, + s8 *pcfotail, + u8 num_ss +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pktinfo_void; + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + u8 i; + + if (!(p_dm_odm->support_ability & ODM_BB_CFO_TRACKING)) + return; + + if (p_pktinfo->is_packet_match_bssid) + { + if (num_ss > p_dm_odm->num_rf_path) /*For fool proof*/ + num_ss = p_dm_odm->num_rf_path; + + /* 3 Update CFO report for path-A & path-B */ + /* Only paht-A and path-B have CFO tail and short CFO */ + for (i = 0; i < num_ss; i++) { + p_cfo_track->CFO_tail[i] += pcfotail[i]; + p_cfo_track->CFO_cnt[i]++; + } + + /* 3 Update packet counter */ + if (p_cfo_track->packet_count == 0xffffffff) + p_cfo_track->packet_count = 0; + else + p_cfo_track->packet_count++; + } +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_cfotracking.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_cfotracking.h new file mode 100644 index 000000000000..273cab2dafaa --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_cfotracking.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMCFOTRACK_H__ +#define __PHYDMCFOTRACK_H__ + +#define CFO_TRACKING_VERSION "1.4" /*2015.10.01 Stanley, Modify for 8822B*/ + +#define CFO_TH_XTAL_HIGH 20 /* kHz */ +#define CFO_TH_XTAL_LOW 10 /* kHz */ +#define CFO_TH_ATC 80 /* kHz */ + +struct _CFO_TRACKING_ { + boolean is_atc_status; + boolean large_cfo_hit; + boolean is_adjust; + u8 crystal_cap; + u8 def_x_cap; + s32 CFO_tail[4]; + u32 CFO_cnt[4]; + s32 CFO_ave_pre; + u32 packet_count; + u32 packet_count_pre; + + boolean is_force_xtal_cap; + boolean is_reset; +}; + +void +odm_cfo_tracking_reset( + void *p_dm_void +); + +void +odm_cfo_tracking_init( + void *p_dm_void +); + +void +odm_cfo_tracking( + void *p_dm_void +); + +void +odm_parsing_cfo( + void *p_dm_void, + void *p_pktinfo_void, + s8 *pcfotail, + u8 num_ss +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_debug.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_debug.c new file mode 100644 index 000000000000..8caf1ac28dc9 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_debug.c @@ -0,0 +1,319 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +phydm_init_debug_setting( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + p_dm_odm->debug_level = ODM_DBG_TRACE; + + p_dm_odm->fw_debug_components = 0; + p_dm_odm->debug_components = + /*BB Functions*/ + /* ODM_COMP_DIG |*/ + /* ODM_COMP_RA_MASK |*/ + /* ODM_COMP_DYNAMIC_TXPWR |*/ + /* ODM_COMP_FA_CNT |*/ + /* ODM_COMP_RSSI_MONITOR |*/ + /* ODM_COMP_SNIFFER |*/ + /* ODM_COMP_ANT_DIV |*/ + /* ODM_COMP_NOISY_DETECT |*/ + /* ODM_COMP_RATE_ADAPTIVE |*/ + /* ODM_COMP_PATH_DIV |*/ + /* ODM_COMP_DYNAMIC_PRICCA |*/ + /* ODM_COMP_MP |*/ + /* ODM_COMP_CFO_TRACKING |*/ + /* ODM_COMP_ACS |*/ + /* PHYDM_COMP_ADAPTIVITY |*/ + /* PHYDM_COMP_RA_DBG |*/ + /* PHYDM_COMP_TXBF |*/ + + /*MAC Functions*/ + /* ODM_COMP_EDCA_TURBO |*/ + /* ODM_COMP_DYNAMIC_RX_PATH |*/ + /* ODM_FW_DEBUG_TRACE |*/ + + /*RF Functions*/ + /* ODM_COMP_TX_PWR_TRACK |*/ + /* ODM_COMP_CALIBRATION |*/ + + /*Common*/ + /* ODM_PHY_CONFIG |*/ + /* ODM_COMP_INIT |*/ + /* ODM_COMP_COMMON |*/ + /* ODM_COMP_API |*/ + + 0; + + p_dm_odm->fw_buff_is_enpty = true; + p_dm_odm->pre_c2h_seq = 0; +} + +void +phydm_bb_dbg_port_header_sel( + void *p_dm_void, + u32 header_idx +) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x8f8, (BIT(25) | BIT(24) | BIT(23) | BIT(22)), header_idx); + + /* + header_idx: + (0:) '{ofdm_dbg[31:0]}' + (1:) '{cca,crc32_fail,dbg_ofdm[29:0]}' + (2:) '{vbon,crc32_fail,dbg_ofdm[29:0]}' + (3:) '{cca,crc32_ok,dbg_ofdm[29:0]}' + (4:) '{vbon,crc32_ok,dbg_ofdm[29:0]}' + (5:) '{dbg_iqk_anta}' + (6:) '{cca,ofdm_crc_ok,dbg_dp_anta[29:0]}' + (7:) '{dbg_iqk_antb}' + (8:) '{DBGOUT_RFC_b[31:0]}' + (9:) '{DBGOUT_RFC_a[31:0]}' + (a:) '{dbg_ofdm}' + (b:) '{dbg_cck}' + */ + } +} + +void +phydm_bb_dbg_port_clock_en( + void *p_dm_void, + u8 enable +) { + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 reg_value = (enable == TRUE) ? 0x7 : 0; + + if (p_dm_odm->support_ic_type & (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B)) { + + odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, reg_value); /*enable/disable debug port clock, for power saving*/ + } +} + +u8 +phydm_set_bb_dbg_port( + void *p_dm_void, + u8 curr_dbg_priority, + u32 debug_port +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 dbg_port_result = FALSE; + + if (curr_dbg_priority > p_dm_odm->pre_dbg_priority) { + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + phydm_bb_dbg_port_clock_en(p_dm_odm, TRUE); + + odm_set_bb_reg(p_dm_odm, 0x8fc, MASKDWORD, debug_port); + /**/ + } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { + odm_set_bb_reg(p_dm_odm, 0x908, MASKDWORD, debug_port); + /**/ + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("DbgPort set success, Reg((0x%x)), Cur_priority=((%d)), Pre_priority=((%d))\n", debug_port, curr_dbg_priority, p_dm_odm->pre_dbg_priority)); + p_dm_odm->pre_dbg_priority = curr_dbg_priority; + dbg_port_result = TRUE; + } + + return dbg_port_result; +} + +void +phydm_release_bb_dbg_port( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + phydm_bb_dbg_port_clock_en(p_dm_odm, FALSE); + phydm_bb_dbg_port_header_sel(p_dm_odm, 0); + + p_dm_odm->pre_dbg_priority = BB_DBGPORT_RELEASE; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("Release BB dbg_port\n")); +} + +u32 +phydm_get_bb_dbg_port_value( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 dbg_port_value = 0; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xfa0, MASKDWORD); + /**/ + } else /*if (p_dm_odm->support_ic_type & ODM_IC_11N_SERIES)*/ { + dbg_port_value = odm_get_bb_reg(p_dm_odm, 0xdf4, MASKDWORD); + /**/ + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("dbg_port_value = 0x%x\n", dbg_port_value)); + return dbg_port_value; +} + +void +phydm_basic_dbg_message +( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct _CFO_TRACKING_ *p_cfo_track = (struct _CFO_TRACKING_ *)phydm_get_structure(p_dm_odm, PHYDM_CFOTRACK); + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u16 macid, phydm_macid, client_cnt = 0; + struct sta_info *p_entry; + s32 tmp_val = 0; + u8 tmp_val_u1 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[PHYDM Common MSG] System up time: ((%d sec))----->\n", p_dm_odm->phydm_sys_up_time)); + + if (p_dm_odm->is_linked) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ID=%d, BW=((%d)), CH=((%d))\n", p_dm_odm->curr_station_id, 20<<(*(p_dm_odm->p_band_width)), *(p_dm_odm->p_channel))); + + /*Print RX rate*/ + if (p_dm_odm->rx_rate <= ODM_RATE11M) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n", + p_dm_odm->cck_lna_idx, p_dm_odm->cck_vga_idx)); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n", + p_dm_odm->ofdm_agc_idx[0], p_dm_odm->ofdm_agc_idx[1], p_dm_odm->ofdm_agc_idx[2], p_dm_odm->ofdm_agc_idx[3])); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI: { %d, %d, %d, %d }, rx_rate:", + (p_dm_odm->RSSI_A == 0xff) ? 0 : p_dm_odm->RSSI_A, + (p_dm_odm->RSSI_B == 0xff) ? 0 : p_dm_odm->RSSI_B, + (p_dm_odm->RSSI_C == 0xff) ? 0 : p_dm_odm->RSSI_C, + (p_dm_odm->RSSI_D == 0xff) ? 0 : p_dm_odm->RSSI_D)); + + phydm_print_rate(p_dm_odm, p_dm_odm->rx_rate, ODM_COMP_COMMON); + + /*Print TX rate*/ + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + + p_entry = p_dm_odm->p_odm_sta_info[macid]; + if (IS_STA_VALID(p_entry)) { + + phydm_macid = (p_dm_odm->platform2phydm_macid_table[macid]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TXRate [%d]:", macid)); + phydm_print_rate(p_dm_odm, p_ra_table->link_tx_rate[macid], ODM_COMP_COMMON); + + client_cnt++; + + if (client_cnt == p_dm_odm->number_linked_client) + break; + } + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("TP { TX, RX, total} = {%d, %d, %d }Mbps, traffic_load = (%d))\n", + p_dm_odm->tx_tp, p_dm_odm->rx_tp, p_dm_odm->total_tp, p_dm_odm->traffic_load)); + + tmp_val_u1 = (p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? (p_cfo_track->crystal_cap - p_cfo_track->def_x_cap) : (p_cfo_track->def_x_cap - p_cfo_track->crystal_cap); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CFO_avg = ((%d kHz)) , CrystalCap_tracking = ((%s%d))\n", + p_cfo_track->CFO_ave_pre, ((p_cfo_track->crystal_cap > p_cfo_track->def_x_cap) ? "+" : "-"), tmp_val_u1)); + + /* Condition number */ + + /*STBC or LDPC pkt*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("LDPC = %s, STBC = %s\n", (p_dm_odm->phy_dbg_info.is_ldpc_pkt) ? "Y" : "N", (p_dm_odm->phy_dbg_info.is_stbc_pkt) ? "Y" : "N")); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("No Link !!!\n")); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("is_linked = %d, Num_client = %d, rssi_min = %d, current_igi = 0x%x, bNoisy=%d\n\n", + p_dm_odm->is_linked, p_dm_odm->number_linked_client, p_dm_odm->rssi_min, p_dm_dig_table->cur_ig_value, p_dm_odm->noisy_decision)); +} + + +s32 +phydm_cmd( + struct PHY_DM_STRUCT *p_dm_odm, + char *input, + u32 in_len, + u8 flag, + char *output, + u32 out_len +) +{ + char *token; + u32 argc = 0; + char argv[MAX_ARGC][MAX_ARGV]; + + do { + token = strsep(&input, ", "); + if (token) { + strcpy(argv[argc], token); + argc++; + } else + break; + } while (argc < MAX_ARGC); + + if (argc == 1) + argv[0][strlen(argv[0]) - 1] = '\0'; + + return 0; +} + +void +phydm_fw_trace_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +) +{ +} + +void +phydm_fw_trace_handler_code( + void *p_dm_void, + u8 *buffer, + u8 cmd_len +) +{ +} + +void +phydm_fw_trace_handler_8051( + void *p_dm_void, + u8 *buffer, + u8 cmd_len +) +{ +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_debug.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_debug.h new file mode 100644 index 000000000000..86cf03fa6f4a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_debug.h @@ -0,0 +1,313 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + +/*#define DEBUG_VERSION "1.1"*/ /*2015.07.29 YuChen*/ +/*#define DEBUG_VERSION "1.2"*/ /*2015.08.28 Dino*/ +#define DEBUG_VERSION "1.3" /*2016.04.28 YuChen*/ +/* ----------------------------------------------------------------------------- + * Define the debug levels + * + * 1. DBG_TRACE and DBG_LOUD are used for normal cases. + * So that, they can help SW engineer to develope or trace states changed + * and also help HW enginner to trace every operation to and from HW, + * e.g IO, Tx, Rx. + * + * 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, + * which help us to debug SW or HW. + * + * ----------------------------------------------------------------------------- + * + * Never used in a call to ODM_RT_TRACE()! + * */ +#define ODM_DBG_OFF 1 + +/* + * Fatal bug. + * For example, Tx/Rx/IO locked up, OS hangs, memory access violation, + * resource allocation failed, unexpected HW behavior, HW BUG and so on. + * */ +#define ODM_DBG_SERIOUS 2 + +/* + * Abnormal, rare, or unexpeted cases. + * For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. + * */ +#define ODM_DBG_WARNING 3 + +/* + * Normal case with useful information about current SW or HW state. + * For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, + * SW protocol state change, dynamic mechanism state change and so on. + * */ +#define ODM_DBG_LOUD 4 + +/* + * Normal case with detail execution flow or information. + * */ +#define ODM_DBG_TRACE 5 + +/*FW DBG MSG*/ +#define RATE_DECISION BIT(0) +#define INIT_RA_TABLE BIT(1) +#define RATE_UP BIT(2) +#define RATE_DOWN BIT(3) +#define TRY_DONE BIT(4) +#define RA_H2C BIT(5) +#define F_RATE_AP_RPT BIT(7) + +/* ----------------------------------------------------------------------------- + * Define the tracing components + * + * ----------------------------------------------------------------------------- + *BB FW Functions*/ +#define PHYDM_FW_COMP_RA BIT(0) +#define PHYDM_FW_COMP_MU BIT(1) +#define PHYDM_FW_COMP_PATH_DIV BIT(2) +#define PHYDM_FW_COMP_PHY_CONFIG BIT(3) + +/*BB Driver Functions*/ +#define ODM_COMP_DIG BIT(0) +#define ODM_COMP_RA_MASK BIT(1) +#define ODM_COMP_DYNAMIC_TXPWR BIT(2) +#define ODM_COMP_FA_CNT BIT(3) +#define ODM_COMP_RSSI_MONITOR BIT(4) +#define ODM_COMP_SNIFFER BIT(5) +#define ODM_COMP_ANT_DIV BIT(6) +#define ODM_COMP_DFS BIT(7) +#define ODM_COMP_NOISY_DETECT BIT(8) +#define ODM_COMP_RATE_ADAPTIVE BIT(9) +#define ODM_COMP_PATH_DIV BIT(10) +#define ODM_COMP_CCX BIT(11) + +#define ODM_COMP_DYNAMIC_PRICCA BIT(12) +/*BIT13 TBD*/ +#define ODM_COMP_MP BIT(14) +#define ODM_COMP_CFO_TRACKING BIT(15) +#define ODM_COMP_ACS BIT(16) +#define PHYDM_COMP_ADAPTIVITY BIT(17) +#define PHYDM_COMP_RA_DBG BIT(18) +#define PHYDM_COMP_TXBF BIT(19) +/* MAC Functions */ +#define ODM_COMP_EDCA_TURBO BIT(20) +#define ODM_COMP_DYNAMIC_RX_PATH BIT(21) +#define ODM_FW_DEBUG_TRACE BIT(22) +/* RF Functions */ +/*BIT23 TBD*/ +#define ODM_COMP_TX_PWR_TRACK BIT(24) +/*BIT25 TBD*/ +#define ODM_COMP_CALIBRATION BIT(26) +/* Common Functions */ +/*BIT27 TBD*/ +#define ODM_PHY_CONFIG BIT(28) +#define ODM_COMP_INIT BIT(29) +#define ODM_COMP_COMMON BIT(30) +#define ODM_COMP_API BIT(31) + +/*------------------------Export Marco Definition---------------------------*/ + +#define config_phydm_read_txagc_check(data) (data != INVALID_TXAGC_DATA) + +#define dbg_print printk +#define RT_PRINTK(fmt, args...) dbg_print("%s(): " fmt, __FUNCTION__, ## args); +#define RT_DISP(dbgtype, dbgflag, printstr) + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) \ + do { \ + if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level || level == ODM_DBG_SERIOUS)) { \ + \ + if (p_dm_odm->support_ic_type == ODM_RTL8188E) \ + dbg_print("[PhyDM-8188E] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8192E) \ + dbg_print("[PhyDM-8192E] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8812) \ + dbg_print("[PhyDM-8812A] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8821) \ + dbg_print("[PhyDM-8821A] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8814A) \ + dbg_print("[PhyDM-8814A] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8703B) \ + dbg_print("[PhyDM-8703B] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8822B) \ + dbg_print("[PhyDM-8822B] "); \ + else if (p_dm_odm->support_ic_type == ODM_RTL8188F) \ + dbg_print("[PhyDM-8188F] "); \ + RT_PRINTK fmt; \ + } \ + } while (0) + +#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt) do {\ + if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ + \ + RT_PRINTK fmt; \ + } \ + } while (0) + +#define ODM_RT_ASSERT(p_dm_odm, expr, fmt) do {\ + if (!(expr)) { \ + dbg_print("Assertion failed! %s at ......\n", #expr); \ + dbg_print(" ......%s,%s, line=%d\n", __FILE__, __FUNCTION__, __LINE__); \ + RT_PRINTK fmt; \ + ASSERT(false); \ + } \ + } while (0) + +#define ODM_dbg_enter() { dbg_print(" == > %s\n", __FUNCTION__); } +#define ODM_dbg_exit() { dbg_print("< == %s\n", __FUNCTION__); } +#define ODM_dbg_trace(str) { dbg_print("%s:%s\n", __FUNCTION__, str); } + +#define ODM_PRINT_ADDR(p_dm_odm, comp, level, title_str, ptr) do {\ + if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level)) { \ + \ + int __i; \ + u8 *__ptr = (u8 *)ptr; \ + dbg_print("[ODM] "); \ + dbg_print(title_str); \ + dbg_print(" "); \ + for (__i = 0; __i < 6; __i++) \ + dbg_print("%02X%s", __ptr[__i], (__i == 5) ? "" : "-"); \ + dbg_print("\n"); \ + } \ + } while (0) + +#define BB_DBGPORT_PRIORITY_3 3 /*Debug function (the highest priority)*/ +#define BB_DBGPORT_PRIORITY_2 2 /*Check hang function & Strong function*/ +#define BB_DBGPORT_PRIORITY_1 1 /*Watch dog function*/ +#define BB_DBGPORT_RELEASE 0 /*Init value (the lowest priority)*/ + +void +phydm_init_debug_setting(struct PHY_DM_STRUCT *p_dm_odm); + +void +phydm_bb_dbg_port_header_sel( + void *p_dm_void, + u32 header_idx +); + +u8 +phydm_set_bb_dbg_port( + void *p_dm_void, + u8 curr_dbg_priority, + u32 debug_port +); + +void +phydm_release_bb_dbg_port( + void *p_dm_void +); + +u32 +phydm_get_bb_dbg_port_value( + void *p_dm_void +); + +void phydm_basic_dbg_message(void *p_dm_void); + +#define PHYDM_DBGPRINT 0 +#define MAX_ARGC 20 +#define MAX_ARGV 16 +#define DCMD_DECIMAL "%d" +#define DCMD_CHAR "%c" +#define DCMD_HEX "%x" + +#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) + +#define PHYDM_VAST_INFO_SNPRINTF(msg)\ + do {\ + snprintf msg;\ + dbg_print(output);\ + } while (0) + +#if (PHYDM_DBGPRINT == 1) +#define PHYDM_SNPRINTF(msg)\ + do {\ + snprintf msg;\ + dbg_print(output);\ + } while (0) +#else +#define PHYDM_SNPRINTF(msg)\ + do {\ + if (out_len > used)\ + used += snprintf msg;\ + } while (0) +#endif + +void phydm_basic_profile( + void *p_dm_void, + u32 *_used, + char *output, + u32 *_out_len +); +s32 +phydm_cmd( + struct PHY_DM_STRUCT *p_dm_odm, + char *input, + u32 in_len, + u8 flag, + char *output, + u32 out_len +); + +boolean +phydm_api_trx_mode( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_path_e tx_path, + enum odm_rf_path_e rx_path, + boolean is_tx2_path +); + +void +phydm_fw_trace_en_h2c( + void *p_dm_void, + boolean enable, + u32 fw_debug_component, + u32 monitor_mode, + u32 macid +); + +void +phydm_fw_trace_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +); + +void +phydm_fw_trace_handler_code( + void *p_dm_void, + u8 *buffer, + u8 cmd_len +); + +void +phydm_fw_trace_handler_8051( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +); + +#endif /* __ODM_DBG_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_dfs.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_dfs.c new file mode 100644 index 000000000000..a695aca01b17 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_dfs.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* +============================================================ + include files +============================================================ +*/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +boolean +phydm_dfs_master_enabled( + void *p_dm_void +) +{ + return false; +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_dfs.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_dfs.h new file mode 100644 index 000000000000..2d63ae423196 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_dfs.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDM_DFS_H__ +#define __PHYDM_DFS_H__ + +#define DFS_VERSION "1.1" + +/* ============================================================ + Definition + ============================================================ +*/ + +/* +============================================================ +1 structure + ============================================================ +*/ + +struct _DFS_STATISTICS { + u8 mask_idx; + u8 igi_cur; + u8 igi_pre; + u8 st_l2h_cur; + u16 fa_count_pre; + u16 fa_inc_hist[5]; + u16 vht_crc_ok_cnt_pre; + u16 ht_crc_ok_cnt_pre; + u16 leg_crc_ok_cnt_pre; + u16 short_pulse_cnt_pre; + u16 long_pulse_cnt_pre; + u8 pwdb_th; + u8 pwdb_th_cur; + u8 pwdb_scalar_factor; + u8 peak_th; + u8 short_pulse_cnt_th; + u8 long_pulse_cnt_th; + u8 peak_window; + u8 nb2wb_th; + u8 fa_mask_th; + u8 det_flag_offset; + u8 st_l2h_max; + u8 st_l2h_min; + u8 mask_hist_checked; + boolean pulse_flag_hist[5]; + boolean radar_det_mask_hist[5]; + boolean idle_mode; + boolean force_TP_mode; + boolean dbg_mode; + boolean det_print; + boolean det_print2; +}; + +/* ============================================================ + enumeration + ============================================================ +*/ + +enum phydm_dfs_region_domain { + PHYDM_DFS_DOMAIN_UNKNOWN = 0, + PHYDM_DFS_DOMAIN_FCC = 1, + PHYDM_DFS_DOMAIN_MKK = 2, + PHYDM_DFS_DOMAIN_ETSI = 3, +}; + +/* +============================================================ + function prototype +============================================================ +*/ + +boolean phydm_dfs_is_meteorology_channel(void *p_dm_void); + +boolean +phydm_dfs_master_enabled( + void *p_dm_void +); + +#endif /*#ifndef __PHYDM_DFS_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_dig.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_dig.c new file mode 100644 index 000000000000..1666373788c3 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_dig.c @@ -0,0 +1,1129 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +odm_change_dynamic_init_gain_thresh( + void *p_dm_void, + u32 dm_type, + u32 dm_value +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + if (dm_type == DIG_TYPE_THRESH_HIGH) + p_dm_dig_table->rssi_high_thresh = dm_value; + else if (dm_type == DIG_TYPE_THRESH_LOW) + p_dm_dig_table->rssi_low_thresh = dm_value; + else if (dm_type == DIG_TYPE_ENABLE) + p_dm_dig_table->dig_enable_flag = true; + else if (dm_type == DIG_TYPE_DISABLE) + p_dm_dig_table->dig_enable_flag = false; + else if (dm_type == DIG_TYPE_BACKOFF) { + if (dm_value > 30) + dm_value = 30; + p_dm_dig_table->backoff_val = (u8)dm_value; + } else if (dm_type == DIG_TYPE_RX_GAIN_MIN) { + if (dm_value == 0) + dm_value = 0x1; + p_dm_dig_table->rx_gain_range_min = (u8)dm_value; + } else if (dm_type == DIG_TYPE_RX_GAIN_MAX) { + if (dm_value > 0x50) + dm_value = 0x50; + p_dm_dig_table->rx_gain_range_max = (u8)dm_value; + } +} /* dm_change_dynamic_init_gain_thresh */ + +int +get_igi_for_diff(int value_IGI) +{ +#define ONERCCA_LOW_TH 0x30 +#define ONERCCA_LOW_DIFF 8 + + if (value_IGI < ONERCCA_LOW_TH) { + if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) + return ONERCCA_LOW_TH; + else + return value_IGI + ONERCCA_LOW_DIFF; + } else + return value_IGI; +} + +void +odm_fa_threshold_check( + void *p_dm_void, + boolean is_dfs_band, + boolean is_performance, + u32 rx_tp, + u32 tx_tp, + u32 *dm_FA_thres +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->is_linked && (is_performance || is_dfs_band)) { + /*For NIC*/ + dm_FA_thres[0] = DM_DIG_FA_TH0; + dm_FA_thres[1] = DM_DIG_FA_TH1; + dm_FA_thres[2] = DM_DIG_FA_TH2; + } else { + if (is_dfs_band) { + /* For DFS band and no link */ + dm_FA_thres[0] = 250; + dm_FA_thres[1] = 1000; + dm_FA_thres[2] = 2000; + } else + { + dm_FA_thres[0] = 2000; + dm_FA_thres[1] = 4000; + dm_FA_thres[2] = 5000; + } + } + return; +} + +u8 +odm_forbidden_igi_check( + void *p_dm_void, + u8 dig_dynamic_min, + u8 current_igi +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + u8 rx_gain_range_min = p_dm_dig_table->rx_gain_range_min; + + if (p_dm_dig_table->large_fa_timeout) { + if (--p_dm_dig_table->large_fa_timeout == 0) + p_dm_dig_table->large_fa_hit = 0; + } + + if (p_false_alm_cnt->cnt_all > 10000) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case.\n")); + + if (p_dm_dig_table->large_fa_hit != 3) + p_dm_dig_table->large_fa_hit++; + + if (p_dm_dig_table->forbidden_igi < current_igi) { /* if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value) */ + p_dm_dig_table->forbidden_igi = current_igi;/* p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value; */ + p_dm_dig_table->large_fa_hit = 1; + p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; + } + + if (p_dm_dig_table->large_fa_hit >= 3) { + if ((p_dm_dig_table->forbidden_igi + 2) > p_dm_dig_table->rx_gain_range_max) + rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; + else + rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); + p_dm_dig_table->recover_cnt = 1800; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); + } + } + + else if (p_false_alm_cnt->cnt_all > 2000) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case.\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("cnt_all=%d, cnt_all_pre=%d, current_igi=0x%x, pre_ig_value=0x%x\n", + p_false_alm_cnt->cnt_all, p_false_alm_cnt->cnt_all_pre, current_igi, p_dm_dig_table->pre_ig_value)); + + /* p_false_alm_cnt->cnt_all = 1.1875*p_false_alm_cnt->cnt_all_pre */ + if ((p_false_alm_cnt->cnt_all > (p_false_alm_cnt->cnt_all_pre + (p_false_alm_cnt->cnt_all_pre >> 3) + (p_false_alm_cnt->cnt_all_pre >> 4))) && (current_igi < p_dm_dig_table->pre_ig_value)) { + if (p_dm_dig_table->large_fa_hit != 3) + p_dm_dig_table->large_fa_hit++; + + if (p_dm_dig_table->forbidden_igi < current_igi) { /*if(p_dm_dig_table->forbidden_igi < p_dm_dig_table->cur_ig_value)*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Updating forbidden_igi by current_igi, forbidden_igi=0x%x, current_igi=0x%x\n", + p_dm_dig_table->forbidden_igi, current_igi)); + + p_dm_dig_table->forbidden_igi = current_igi; /*p_dm_dig_table->forbidden_igi = p_dm_dig_table->cur_ig_value;*/ + p_dm_dig_table->large_fa_hit = 1; + p_dm_dig_table->large_fa_timeout = LARGE_FA_TIMEOUT; + } + + } + + if (p_dm_dig_table->large_fa_hit >= 3) { + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("FaHit is greater than 3, rx_gain_range_max=0x%x, rx_gain_range_min=0x%x, forbidden_igi=0x%x\n", + p_dm_dig_table->rx_gain_range_max, rx_gain_range_min, p_dm_dig_table->forbidden_igi)); + + if ((p_dm_dig_table->forbidden_igi + 1) > p_dm_dig_table->rx_gain_range_max) + rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; + else + rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 1); + + p_dm_dig_table->recover_cnt = 1200; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Abnormally false alarm case: recover_cnt = %d, rx_gain_range_min = 0x%x\n", p_dm_dig_table->recover_cnt, rx_gain_range_min)); + } + } + + else { + if (p_dm_dig_table->recover_cnt != 0) { + + p_dm_dig_table->recover_cnt--; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: recover_cnt = %d\n", p_dm_dig_table->recover_cnt)); + } else { + if (p_dm_dig_table->large_fa_hit < 3) { + if ((p_dm_dig_table->forbidden_igi - 2) < dig_dynamic_min) { /* DM_DIG_MIN) */ + p_dm_dig_table->forbidden_igi = dig_dynamic_min; /* DM_DIG_MIN; */ + rx_gain_range_min = dig_dynamic_min; /* DM_DIG_MIN; */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); + } else { + if (p_dm_dig_table->large_fa_hit == 0) { + p_dm_dig_table->forbidden_igi -= 2; + rx_gain_range_min = (p_dm_dig_table->forbidden_igi + 2); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); + } + } + } else + p_dm_dig_table->large_fa_hit = 0; + } + } + + return rx_gain_range_min; + +} + +void +odm_dig_for_bt_hs_mode( + void *p_dm_void +) +{ +} + +void +phydm_set_big_jump_step( + void *p_dm_void, + u8 current_igi +) +{ +} + +void +odm_write_dig( + void *p_dm_void, + u8 current_igi +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + if (p_dm_dig_table->is_stop_dig) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): Stop Writing IGI\n")); + return; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): ODM_REG(IGI_A,p_dm_odm)=0x%x, ODM_BIT(IGI,p_dm_odm)=0x%x\n", + ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm))); + + /* 1 Check initial gain by upper bound */ + if ((!p_dm_dig_table->is_psd_in_progress) && p_dm_odm->is_linked) { + if (current_igi > p_dm_dig_table->rx_gain_range_max) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x) is larger than upper bound !!\n", current_igi)); + current_igi = p_dm_dig_table->rx_gain_range_max; + } + if (p_dm_odm->support_ability & ODM_BB_ADAPTIVITY && p_dm_odm->adaptivity_flag == true) { + if (current_igi > p_dm_odm->adaptivity_igi_upper) + current_igi = p_dm_odm->adaptivity_igi_upper; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_write_dig(): adaptivity case: Force upper bound to 0x%x !!!!!!\n", current_igi)); + } + } + + if (p_dm_dig_table->cur_ig_value != current_igi) { + + + /* Set IGI value of CCK for new CCK AGC */ + if (p_dm_odm->cck_new_agc) { + if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) + odm_set_bb_reg(p_dm_odm, 0xa0c, 0x00003f00, (current_igi >> 1)); + } + + /*Add by YuChen for USB IO too slow issue*/ + if ((p_dm_odm->support_ability & ODM_BB_ADAPTIVITY) && (current_igi > p_dm_dig_table->cur_ig_value)) { + p_dm_dig_table->cur_ig_value = current_igi; + phydm_adaptivity(p_dm_odm); + } + + /* 1 Set IGI value */ + if (p_dm_odm->support_platform & (ODM_WIN | ODM_CE)) { + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + + if (p_dm_odm->rf_type > ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + + } else if (p_dm_odm->support_platform & (ODM_AP)) { + switch (*(p_dm_odm->p_one_path_cca)) { + case ODM_CCA_2R: + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + + if (p_dm_odm->rf_type > ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + break; + case ODM_CCA_1R_A: + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + if (p_dm_odm->rf_type != ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); + break; + case ODM_CCA_1R_B: + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_B, p_dm_odm), ODM_BIT(IGI, p_dm_odm), get_igi_for_diff(current_igi)); + if (p_dm_odm->rf_type != ODM_1T1R) + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), current_igi); + break; + } + } + + p_dm_dig_table->cur_ig_value = current_igi; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("odm_write_dig(): current_igi(0x%02x).\n", current_igi)); + +} + +void +odm_pause_dig( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 igi_value +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig()=========> level = %d\n", pause_level)); + + if ((p_dm_dig_table->pause_dig_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_DIG) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_dig(): Return: support_ability DIG or FA is disabled !!\n")); + return; + } + + if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_dig(): Return: Wrong pause level !!\n")); + return; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], + p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); + + switch (pause_type) { + /* Pause DIG */ + case PHYDM_PAUSE: + { + /* Disable DIG */ + odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability & (~ODM_BB_DIG)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Pause DIG !!\n")); + + /* Backup IGI value */ + if (p_dm_dig_table->pause_dig_level == 0) { + p_dm_dig_table->igi_backup = p_dm_dig_table->cur_ig_value; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Backup IGI = 0x%x, new IGI = 0x%x\n", p_dm_dig_table->igi_backup, igi_value)); + } + + /* Record IGI value */ + p_dm_dig_table->pause_dig_value[pause_level] = igi_value; + + /* Update pause level */ + p_dm_dig_table->pause_dig_level = (p_dm_dig_table->pause_dig_level | BIT(pause_level)); + + /* Write new IGI value */ + if (BIT(pause_level + 1) > p_dm_dig_table->pause_dig_level) { + odm_write_dig(p_dm_odm, igi_value); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): IGI of higher level = 0x%x\n", igi_value)); + } + break; + } + /* Resume DIG */ + case PHYDM_RESUME: + { + /* check if the level is illegal or not */ + if ((p_dm_dig_table->pause_dig_level & (BIT(pause_level))) != 0) { + p_dm_dig_table->pause_dig_level = p_dm_dig_table->pause_dig_level & (~(BIT(pause_level))); + p_dm_dig_table->pause_dig_value[pause_level] = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Resume DIG !!\n")); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong resume level !!\n")); + break; + } + + /* Resume DIG */ + if (p_dm_dig_table->pause_dig_level == 0) { + /* Write backup IGI value */ + odm_write_dig(p_dm_odm, p_dm_dig_table->igi_backup); + p_dm_dig_table->is_ignore_dig = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write original IGI = 0x%x\n", p_dm_dig_table->igi_backup)); + + /* Enable DIG */ + odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability | ODM_BB_DIG); + break; + } + + if (BIT(pause_level) > p_dm_dig_table->pause_dig_level) { + s8 max_level; + + /* Calculate the maximum level now */ + for (max_level = (pause_level - 1); max_level >= 0; max_level--) { + if ((p_dm_dig_table->pause_dig_level & BIT(max_level)) > 0) + break; + } + + /* write IGI of lower level */ + odm_write_dig(p_dm_odm, p_dm_dig_table->pause_dig_value[max_level]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Write IGI (0x%x) of level (%d)\n", + p_dm_dig_table->pause_dig_value[max_level], max_level)); + break; + } + break; + } + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): Wrong type !!\n")); + break; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_dig_level, igi_value)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_dig(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_dig_value[7], p_dm_dig_table->pause_dig_value[6], p_dm_dig_table->pause_dig_value[5], p_dm_dig_table->pause_dig_value[4], + p_dm_dig_table->pause_dig_value[3], p_dm_dig_table->pause_dig_value[2], p_dm_dig_table->pause_dig_value[1], p_dm_dig_table->pause_dig_value[0])); + +} + +boolean +odm_dig_abort( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + /* support_ability */ + if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_FA_CNT is disabled\n")); + return true; + } + + /* support_ability */ + if (!(p_dm_odm->support_ability & ODM_BB_DIG)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: support_ability ODM_BB_DIG is disabled\n")); + return true; + } + + /* ScanInProcess */ + if (*(p_dm_odm->p_is_scan_in_process)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress\n")); + return true; + } + + if (p_dm_dig_table->is_ignore_dig) { + p_dm_dig_table->is_ignore_dig = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG\n")); + return true; + } + + /* add by Neil Chen to avoid PSD is processing */ + if (p_dm_odm->is_dm_initial_gain_enable == false) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing\n")); + return true; + } + + return false; +} + +void +odm_dig_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u32 ret_value; + u8 i; + + p_dm_dig_table->is_stop_dig = false; + p_dm_dig_table->is_ignore_dig = false; + p_dm_dig_table->is_psd_in_progress = false; + p_dm_dig_table->cur_ig_value = (u8) odm_get_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm)); + p_dm_dig_table->pre_ig_value = 0; + p_dm_dig_table->rssi_low_thresh = DM_DIG_THRESH_LOW; + p_dm_dig_table->rssi_high_thresh = DM_DIG_THRESH_HIGH; + p_dm_dig_table->fa_low_thresh = DM_FALSEALARM_THRESH_LOW; + p_dm_dig_table->fa_high_thresh = DM_FALSEALARM_THRESH_HIGH; + p_dm_dig_table->backoff_val = DM_DIG_BACKOFF_DEFAULT; + p_dm_dig_table->backoff_val_range_max = DM_DIG_BACKOFF_MAX; + p_dm_dig_table->backoff_val_range_min = DM_DIG_BACKOFF_MIN; + p_dm_dig_table->pre_cck_cca_thres = 0xFF; + p_dm_dig_table->cur_cck_cca_thres = 0x83; + p_dm_dig_table->forbidden_igi = DM_DIG_MIN_NIC; + p_dm_dig_table->large_fa_hit = 0; + p_dm_dig_table->large_fa_timeout = 0; + p_dm_dig_table->recover_cnt = 0; + p_dm_dig_table->is_media_connect_0 = false; + p_dm_dig_table->is_media_connect_1 = false; + + /* To Initialize p_dm_odm->is_dm_initial_gain_enable == false to avoid DIG error */ + p_dm_odm->is_dm_initial_gain_enable = true; + + p_dm_dig_table->dig_dynamic_min_0 = DM_DIG_MIN_NIC; + p_dm_dig_table->dig_dynamic_min_1 = DM_DIG_MIN_NIC; + + /* To Initi BT30 IGI */ + p_dm_dig_table->bt30_cur_igi = 0x32; + + odm_memory_set(p_dm_odm, p_dm_dig_table->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + p_dm_dig_table->pause_dig_level = 0; + odm_memory_set(p_dm_odm, p_dm_dig_table->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + p_dm_dig_table->pause_cckpd_level = 0; + + if (p_dm_odm->board_type & (ODM_BOARD_EXT_PA | ODM_BOARD_EXT_LNA)) { + p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; + p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; + } else { + p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_NIC; + p_dm_dig_table->rx_gain_range_min = DM_DIG_MIN_NIC; + } + + +} + +void +odm_DIG( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + /* Common parameters */ + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + boolean first_connect, first_dis_connect; + u8 dig_max_of_min, dig_dynamic_min; + u8 dm_dig_max, dm_dig_min; + u8 current_igi = p_dm_dig_table->cur_ig_value; + u8 offset; + u32 dm_FA_thres[3]; + u32 tx_tp = 0, rx_tp = 0; + boolean is_dfs_band = false; + boolean is_performance = true, is_first_tp_target = false, is_first_coverage = false; + + if (odm_dig_abort(p_dm_odm) == true) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG Start===>\n")); + + + /* 1 Update status */ + { + dig_dynamic_min = p_dm_dig_table->dig_dynamic_min_0; + first_connect = (p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == false); + first_dis_connect = (!p_dm_odm->is_linked) && (p_dm_dig_table->is_media_connect_0 == true); + } + + /* 1 Boundary Decision */ + { + /* 2 For WIN\CE */ + if (p_dm_odm->support_ic_type >= ODM_RTL8188E) + dm_dig_max = 0x5A; + else + dm_dig_max = DM_DIG_MAX_NIC; + + if (p_dm_odm->support_ic_type != ODM_RTL8821) + dm_dig_min = DM_DIG_MIN_NIC; + else + dm_dig_min = 0x1C; + + dig_max_of_min = DM_DIG_MAX_AP; + + /* Modify lower bound for DFS band */ + if ((((*p_dm_odm->p_channel >= 52) && (*p_dm_odm->p_channel <= 64)) || + ((*p_dm_odm->p_channel >= 100) && (*p_dm_odm->p_channel <= 140))) + && phydm_dfs_master_enabled(p_dm_odm) == true + ) { + is_dfs_band = true; + if (*p_dm_odm->p_band_width == ODM_BW20M) + dm_dig_min = DM_DIG_MIN_AP_DFS + 2; + else + dm_dig_min = DM_DIG_MIN_AP_DFS; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: ====== In DFS band ======\n")); + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Absolutly upper bound = 0x%x, lower bound = 0x%x\n", dm_dig_max, dm_dig_min)); + + if (p_dm_odm->pu1_forced_igi_lb && (0 < *p_dm_odm->pu1_forced_igi_lb)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Force IGI lb to: 0x%02x\n", *p_dm_odm->pu1_forced_igi_lb)); + dm_dig_min = *p_dm_odm->pu1_forced_igi_lb; + dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1); + } + + /* 1 Adjust boundary by RSSI */ + if (p_dm_odm->is_linked && is_performance) { + /* 2 Modify DIG upper bound */ + /* 4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT */ + if ((p_dm_odm->support_ic_type & (ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8812 | ODM_RTL8821)) && (p_dm_odm->is_bt_limited_dig == 1)) { + offset = 10; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Coex. case: Force upper bound to RSSI + %d\n", offset)); + } else + offset = 15; + + if ((p_dm_odm->rssi_min + offset) > dm_dig_max) + p_dm_dig_table->rx_gain_range_max = dm_dig_max; + else if ((p_dm_odm->rssi_min + offset) < dm_dig_min) + p_dm_dig_table->rx_gain_range_max = dm_dig_min; + else + p_dm_dig_table->rx_gain_range_max = p_dm_odm->rssi_min + offset; + + /* 2 Modify DIG lower bound */ + /* if(p_dm_odm->is_one_entry_only) */ + { + if (p_dm_odm->rssi_min < dm_dig_min) + dig_dynamic_min = dm_dig_min; + else if (p_dm_odm->rssi_min > dig_max_of_min) + dig_dynamic_min = dig_max_of_min; + else + dig_dynamic_min = p_dm_odm->rssi_min; + + if (is_dfs_band) { + dig_dynamic_min = dm_dig_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force lower bound to 0x%x after link\n", dm_dig_min)); + } + } + } else { + if (is_performance && is_dfs_band) { + p_dm_dig_table->rx_gain_range_max = 0x28; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: Force upper bound to 0x%x before link\n", p_dm_dig_table->rx_gain_range_max)); + } else + { + if (is_performance) + p_dm_dig_table->rx_gain_range_max = DM_DIG_MAX_OF_MIN; + else + p_dm_dig_table->rx_gain_range_max = dm_dig_max; + } + dig_dynamic_min = dm_dig_min; + } + + /* 1 Force Lower Bound for AntDiv */ + if (p_dm_odm->is_linked && !p_dm_odm->is_one_entry_only) { + if ((p_dm_odm->support_ic_type & ODM_ANTDIV_SUPPORT) && (p_dm_odm->support_ability & ODM_BB_ANT_DIV)) { + if (p_dm_odm->ant_div_type == CG_TRX_HW_ANTDIV || p_dm_odm->ant_div_type == CG_TRX_SMART_ANTDIV) { + if (p_dm_dig_table->ant_div_rssi_max > dig_max_of_min) + dig_dynamic_min = dig_max_of_min; + else + dig_dynamic_min = (u8) p_dm_dig_table->ant_div_rssi_max; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: Force lower bound to 0x%x\n", dig_dynamic_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: AntDiv case: RSSI_max = 0x%x\n", p_dm_dig_table->ant_div_rssi_max)); + } + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n", + p_dm_dig_table->rx_gain_range_max, dig_dynamic_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Link status: is_linked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n", + p_dm_odm->is_linked, p_dm_odm->rssi_min, first_connect, first_dis_connect)); + + /* 1 Modify DIG lower bound, deal with abnormal case */ + /* 2 Abnormal false alarm case */ + if (is_dfs_band) + p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; + else + { + if (!p_dm_odm->is_linked) { + p_dm_dig_table->rx_gain_range_min = dig_dynamic_min; + + if (first_dis_connect) + p_dm_dig_table->forbidden_igi = dig_dynamic_min; + } else + p_dm_dig_table->rx_gain_range_min = odm_forbidden_igi_check(p_dm_odm, dig_dynamic_min, current_igi); + } + + /* 2 Abnormal # beacon case */ + if (p_dm_odm->is_linked && !first_connect) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", p_dm_odm->phy_dbg_info.num_qry_beacon_pkt)); + if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_dm_odm->bsta_state)) { + p_dm_dig_table->rx_gain_range_min = 0x1c; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n", + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, p_dm_dig_table->rx_gain_range_min)); + } + } + + /* 2 Abnormal lower bound case */ + if (p_dm_dig_table->rx_gain_range_min > p_dm_dig_table->rx_gain_range_max) { + p_dm_dig_table->rx_gain_range_min = p_dm_dig_table->rx_gain_range_max; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal lower bound case: Force lower bound to 0x%x\n", p_dm_dig_table->rx_gain_range_min)); + } + + /* 1 False alarm threshold decision */ + odm_fa_threshold_check(p_dm_odm, is_dfs_band, is_performance, rx_tp, tx_tp, dm_FA_thres); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: False alarm threshold = %d, %d, %d\n", dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); + + /* 1 Adjust initial gain by false alarm */ + if (p_dm_odm->is_linked && is_performance) { + /* 2 After link */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI after link\n")); + + if (is_first_tp_target || (first_connect && is_performance)) { + p_dm_dig_table->large_fa_hit = 0; + + if (is_dfs_band) { + if (p_dm_odm->rssi_min > 0x28) + current_igi = 0x28; + else + current_igi = p_dm_odm->rssi_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: DFS band: One-shot to 0x28 upmost\n")); + } else + { + if (p_dm_odm->rssi_min < dig_max_of_min) { + if (current_igi < p_dm_odm->rssi_min) + current_igi = p_dm_odm->rssi_min; + } else { + if (current_igi < dig_max_of_min) + current_igi = dig_max_of_min; + } + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First connect case: IGI does on-shot to 0x%x\n", current_igi)); + + } else { + + + if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) + current_igi = current_igi + 4; + else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) + current_igi = current_igi + 2; + else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) + current_igi = current_igi - 2; + + /* 4 Abnormal # beacon case */ + if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH1) && (p_dm_odm->bsta_state)) { + current_igi = p_dm_dig_table->rx_gain_range_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, current_igi)); + } + } + } else { + /* 2 Before link */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Adjust IGI before link\n")); + + if (first_dis_connect || is_first_coverage) { + current_igi = dm_dig_min; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First disconnect case: IGI does on-shot to lower bound\n")); + } else { + + + if (p_false_alm_cnt->cnt_all > dm_FA_thres[2]) + current_igi = current_igi + 4; + else if (p_false_alm_cnt->cnt_all > dm_FA_thres[1]) + current_igi = current_igi + 2; + else if (p_false_alm_cnt->cnt_all < dm_FA_thres[0]) + current_igi = current_igi - 2; + } + } + + /* 1 Check initial gain by upper/lower bound */ + if (current_igi < p_dm_dig_table->rx_gain_range_min) + current_igi = p_dm_dig_table->rx_gain_range_min; + + if (current_igi > p_dm_dig_table->rx_gain_range_max) + current_igi = p_dm_dig_table->rx_gain_range_max; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: cur_ig_value=0x%x, TotalFA = %d\n", current_igi, p_false_alm_cnt->cnt_all)); + + /* 1 Update status */ + { + if (p_dm_odm->is_bt_hs_operation) { + if (p_dm_odm->is_linked) { + if (p_dm_dig_table->bt30_cur_igi > (current_igi)) + odm_write_dig(p_dm_odm, current_igi); + else + odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi); + + p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; + p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; + } else { + if (p_dm_odm->is_link_in_process) + odm_write_dig(p_dm_odm, 0x1c); + else if (p_dm_odm->is_bt_connect_process) + odm_write_dig(p_dm_odm, 0x28); + else + odm_write_dig(p_dm_odm, p_dm_dig_table->bt30_cur_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ + } + } else /* BT is not using */ + { + odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ + p_dm_dig_table->is_media_connect_0 = p_dm_odm->is_linked; + p_dm_dig_table->dig_dynamic_min_0 = dig_dynamic_min; + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG end\n")); +} + +void +odm_dig_by_rssi_lps( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + + u8 rssi_lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */ + u8 current_igi = p_dm_odm->rssi_min; + + if (odm_dig_abort(p_dm_odm) == true) + return; + + current_igi = current_igi + RSSI_OFFSET_DIG; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps()==>\n")); + + /* Using FW PS mode to make IGI */ + /* Adjust by FA in LPS MODE */ + if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH2_LPS) + current_igi = current_igi + 4; + else if (p_false_alm_cnt->cnt_all > DM_DIG_FA_TH1_LPS) + current_igi = current_igi + 2; + else if (p_false_alm_cnt->cnt_all < DM_DIG_FA_TH0_LPS) + current_igi = current_igi - 2; + + /* Lower bound checking */ + + /* RSSI Lower bound check */ + if ((p_dm_odm->rssi_min - 10) > DM_DIG_MIN_NIC) + rssi_lower = (p_dm_odm->rssi_min - 10); + else + rssi_lower = DM_DIG_MIN_NIC; + + /* Upper and Lower Bound checking */ + if (current_igi > DM_DIG_MAX_NIC) + current_igi = DM_DIG_MAX_NIC; + else if (current_igi < rssi_lower) + current_igi = rssi_lower; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_false_alm_cnt->cnt_all = %d\n", p_false_alm_cnt->cnt_all)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): p_dm_odm->rssi_min = %d\n", p_dm_odm->rssi_min)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_dig_by_rssi_lps(): current_igi = 0x%x\n", current_igi)); + + odm_write_dig(p_dm_odm, current_igi);/* odm_write_dig(p_dm_odm, p_dm_dig_table->cur_ig_value); */ +} + +/* 3============================================================ + * 3 FASLE ALARM CHECK + * 3============================================================ */ + +void +odm_false_alarm_counter_statistics( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY); + u32 ret_value; + + if (!(p_dm_odm->support_ability & ODM_BB_FA_CNT)) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Counter()======>\n")); + + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + u32 cck_enable; + + /* read OFDM FA counter */ + false_alm_cnt->cnt_ofdm_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_11AC, MASKLWORD); + + /* Read CCK FA counter */ + false_alm_cnt->cnt_cck_fail = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_FA_11AC, MASKLWORD); + + /* read CCK/OFDM CCA counter */ + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_cck_cca = ret_value & 0xffff; + + /* read CCK CRC32 counter */ + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_cck_crc32_ok = ret_value & 0xffff; + + /* read OFDM CRC32 counter */ + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_ofdm_crc32_ok = ret_value & 0xffff; + + /* read HT CRC32 counter */ + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_ht_crc32_ok = ret_value & 0xffff; + + /* read VHT CRC32 counter */ + ret_value = odm_get_bb_reg(p_dm_odm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD); + false_alm_cnt->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16; + false_alm_cnt->cnt_vht_crc32_ok = ret_value & 0xffff; + + + /* reset OFDM FA coutner */ + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_OFDM_FA_RST_11AC, BIT(17), 0); + + /* reset CCK FA counter */ + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 0); + odm_set_bb_reg(p_dm_odm, ODM_REG_CCK_FA_RST_11AC, BIT(15), 1); + + /* reset CCA counter */ + odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 1); + odm_set_bb_reg(p_dm_odm, ODM_REG_RST_RPT_11AC, BIT(0), 0); + + cck_enable = odm_get_bb_reg(p_dm_odm, ODM_REG_BB_RX_PATH_11AC, BIT(28)); + if (cck_enable) { /* if(*p_dm_odm->p_band_type == ODM_BAND_2_4G) */ + false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail + false_alm_cnt->cnt_cck_fail; + false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_cck_cca + false_alm_cnt->cnt_ofdm_cca; + } else { + false_alm_cnt->cnt_all = false_alm_cnt->cnt_ofdm_fail; + false_alm_cnt->cnt_cca_all = false_alm_cnt->cnt_ofdm_cca; + } + } + + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/ + false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(p_dm_odm); + phydm_release_bb_dbg_port(p_dm_odm); + } + + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) { + false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(30))>>30); + phydm_release_bb_dbg_port(p_dm_odm); + } + + false_alm_cnt->cnt_crc32_error_all = false_alm_cnt->cnt_vht_crc32_error + false_alm_cnt->cnt_ht_crc32_error + false_alm_cnt->cnt_ofdm_crc32_error + false_alm_cnt->cnt_cck_crc32_error; + false_alm_cnt->cnt_crc32_ok_all = false_alm_cnt->cnt_vht_crc32_ok + false_alm_cnt->cnt_ht_crc32_ok + false_alm_cnt->cnt_ofdm_crc32_ok + false_alm_cnt->cnt_cck_crc32_ok; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[CCK] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_cck_crc32_error, false_alm_cnt->cnt_cck_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[OFDM]CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ofdm_crc32_error, false_alm_cnt->cnt_ofdm_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[ HT ] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_ht_crc32_error, false_alm_cnt->cnt_ht_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_vht_crc32_error, false_alm_cnt->cnt_vht_crc32_ok)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("[VHT] CRC32 {error, ok}= {%d, %d}\n", false_alm_cnt->cnt_crc32_error_all, false_alm_cnt->cnt_crc32_ok_all)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n", false_alm_cnt->dbg_port0, false_alm_cnt->edcca_flag)); +} + +/* 3============================================================ + * 3 CCK Packet Detect threshold + * 3============================================================ */ + +void +odm_pause_cck_packet_detection( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 cck_pd_threshold +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection()=========> level = %d\n", pause_level)); + + if ((p_dm_dig_table->pause_cckpd_level == 0) && (!(p_dm_odm->support_ability & ODM_BB_CCK_PD) || !(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Return: support_ability ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); + return; + } + + if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_cck_packet_detection(): Return: Wrong pause level !!\n")); + return; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], + p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); + + switch (pause_type) { + /* Pause CCK Packet Detection threshold */ + case PHYDM_PAUSE: + { + /* Disable CCK PD */ + odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability & (~ODM_BB_CCK_PD)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Pause CCK packet detection threshold !!\n")); + + /* Backup original CCK PD threshold decided by CCK PD mechanism */ + if (p_dm_dig_table->pause_cckpd_level == 0) { + p_dm_dig_table->cck_pd_backup = p_dm_dig_table->cur_cck_cca_thres; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_pause_cck_packet_detection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup, cck_pd_threshold)); + } + + /* Update pause level */ + p_dm_dig_table->pause_cckpd_level = (p_dm_dig_table->pause_cckpd_level | BIT(pause_level)); + + /* Record CCK PD threshold */ + p_dm_dig_table->pause_cckpd_value[pause_level] = cck_pd_threshold; + + /* Write new CCK PD threshold */ + if (BIT(pause_level + 1) > p_dm_dig_table->pause_cckpd_level) { + odm_write_cck_cca_thres(p_dm_odm, cck_pd_threshold); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): CCKPD of higher level = 0x%x\n", cck_pd_threshold)); + } + break; + } + /* Resume CCK Packet Detection threshold */ + case PHYDM_RESUME: + { + /* check if the level is illegal or not */ + if ((p_dm_dig_table->pause_cckpd_level & (BIT(pause_level))) != 0) { + p_dm_dig_table->pause_cckpd_level = p_dm_dig_table->pause_cckpd_level & (~(BIT(pause_level))); + p_dm_dig_table->pause_cckpd_value[pause_level] = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Resume CCK PD !!\n")); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong resume level !!\n")); + break; + } + + /* Resume DIG */ + if (p_dm_dig_table->pause_cckpd_level == 0) { + /* Write backup IGI value */ + odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->cck_pd_backup); + /* p_dm_dig_table->is_ignore_dig = true; */ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write original CCKPD = 0x%x\n", p_dm_dig_table->cck_pd_backup)); + + /* Enable DIG */ + odm_cmn_info_update(p_dm_odm, ODM_CMNINFO_ABILITY, p_dm_odm->support_ability | ODM_BB_CCK_PD); + break; + } + + if (BIT(pause_level) > p_dm_dig_table->pause_cckpd_level) { + s8 max_level; + + /* Calculate the maximum level now */ + for (max_level = (pause_level - 1); max_level >= 0; max_level--) { + if ((p_dm_dig_table->pause_cckpd_level & BIT(max_level)) > 0) + break; + } + + /* write CCKPD of lower level */ + odm_write_cck_cca_thres(p_dm_odm, p_dm_dig_table->pause_cckpd_value[max_level]); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Write CCKPD (0x%x) of level (%d)\n", + p_dm_dig_table->pause_cckpd_value[max_level], max_level)); + break; + } + break; + } + default: + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): Wrong type !!\n")); + break; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause level = 0x%x, Current value = 0x%x\n", p_dm_dig_table->pause_cckpd_level, cck_pd_threshold)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_pause_cck_packet_detection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + p_dm_dig_table->pause_cckpd_value[7], p_dm_dig_table->pause_cckpd_value[6], p_dm_dig_table->pause_cckpd_value[5], p_dm_dig_table->pause_cckpd_value[4], + p_dm_dig_table->pause_cckpd_value[3], p_dm_dig_table->pause_cckpd_value[2], p_dm_dig_table->pause_cckpd_value[1], p_dm_dig_table->pause_cckpd_value[0])); +} + +void +odm_cck_packet_detection_thresh( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); + u8 cur_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres, RSSI_thd = 35; + u8 pd_th = 0, cs_ration = 0; + + if ((!(p_dm_odm->support_ability & ODM_BB_CCK_PD)) || (!(p_dm_odm->support_ability & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: return==========\n")); + #ifdef MCR_WIRELESS_EXTEND + odm_write_cck_cca_thres(p_dm_odm, 0x43); + #endif + return; + } + + if (p_dm_odm->ext_lna) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: ==========>\n")); + + if (p_dm_dig_table->cck_fa_ma == 0xffffffff) + p_dm_dig_table->cck_fa_ma = false_alm_cnt->cnt_cck_fail; + else + p_dm_dig_table->cck_fa_ma = ((p_dm_dig_table->cck_fa_ma << 1) + p_dm_dig_table->cck_fa_ma + false_alm_cnt->cnt_cck_fail) >> 2; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: CCK FA moving average = %d\n", p_dm_dig_table->cck_fa_ma)); + + if (p_dm_odm->is_linked) { + { + if (p_dm_odm->rssi_min > RSSI_thd) + cur_cck_cca_thres = 0xcd; + else if (p_dm_odm->rssi_min > 20) { + if (p_dm_dig_table->cck_fa_ma > ((DM_DIG_FA_TH1 >> 1) + (DM_DIG_FA_TH1 >> 3))) + cur_cck_cca_thres = 0xcd; + else if (p_dm_dig_table->cck_fa_ma < (DM_DIG_FA_TH0 >> 1)) + cur_cck_cca_thres = 0x83; + } else if (p_dm_odm->rssi_min > 7) + cur_cck_cca_thres = 0x83; + else + cur_cck_cca_thres = 0x40; + } + } else { + + if (p_dm_dig_table->cck_fa_ma > 0x400) + cur_cck_cca_thres = 0x83; + else if (p_dm_dig_table->cck_fa_ma < 0x200) + cur_cck_cca_thres = 0x40; + } + + + { + odm_write_cck_cca_thres(p_dm_odm, cur_cck_cca_thres); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CCK_PD: cck_cca_th=((0x%x))\n\n", cur_cck_cca_thres)); +} + +void +odm_write_cck_cca_thres( + void *p_dm_void, + u8 cur_cck_cca_thres +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + + if (p_dm_dig_table->cur_cck_cca_thres != cur_cck_cca_thres) { /* modify by Guo.Mingzhi 2012-01-03 */ + odm_write_1byte(p_dm_odm, ODM_REG(CCK_CCA, p_dm_odm), cur_cck_cca_thres); + p_dm_dig_table->cck_fa_ma = 0xffffffff; + } + p_dm_dig_table->pre_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres; + p_dm_dig_table->cur_cck_cca_thres = cur_cck_cca_thres; +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_dig.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_dig.h new file mode 100644 index 000000000000..81e668b4dde2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_dig.h @@ -0,0 +1,311 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDIG_H__ +#define __PHYDMDIG_H__ + +#define DIG_VERSION "1.32" /* 2016.09.02 YuChen. add CCK PD for 8197F*/ + +/* Pause DIG & CCKPD */ +#define DM_DIG_MAX_PAUSE_TYPE 0x7 + +enum dig_goupcheck_level { + + DIG_GOUPCHECK_LEVEL_0, + DIG_GOUPCHECK_LEVEL_1, + DIG_GOUPCHECK_LEVEL_2 + +}; + +struct _dynamic_initial_gain_threshold_ { + boolean is_stop_dig; /* for debug */ + boolean is_ignore_dig; + boolean is_psd_in_progress; + + u8 dig_enable_flag; + u8 dig_ext_port_stage; + + int rssi_low_thresh; + int rssi_high_thresh; + + u32 fa_low_thresh; + u32 fa_high_thresh; + + u8 cur_sta_connect_state; + u8 pre_sta_connect_state; + u8 cur_multi_sta_connect_state; + + u8 pre_ig_value; + u8 cur_ig_value; + u8 backup_ig_value; /* MP DIG */ + u8 bt30_cur_igi; + u8 igi_backup; + + s8 backoff_val; + s8 backoff_val_range_max; + s8 backoff_val_range_min; + u8 rx_gain_range_max; + u8 rx_gain_range_min; + u8 rssi_val_min; + + u8 pre_cck_cca_thres; + u8 cur_cck_cca_thres; + u8 pre_cck_pd_state; + u8 cur_cck_pd_state; + u8 cck_pd_backup; + u8 pause_cckpd_level; + u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + + u8 large_fa_hit; + u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout" sec, if timeout, large_fa_hit=0*/ + u8 forbidden_igi; + u32 recover_cnt; + + u8 dig_dynamic_min_0; + u8 dig_dynamic_min_1; + boolean is_media_connect_0; + boolean is_media_connect_1; + + u32 ant_div_rssi_max; + u32 RSSI_max; + + u8 *is_p2p_in_process; + + u8 pause_dig_level; + u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + + u32 cck_fa_ma; + enum dig_goupcheck_level dig_go_up_check_level; + u8 aaa_default; + + u8 rf_gain_idx; + u8 agc_table_idx; + u8 big_jump_lmt[16]; + u8 enable_adjust_big_jump:1; + u8 big_jump_step1:3; + u8 big_jump_step2:2; + u8 big_jump_step3:2; + +}; + +struct _FALSE_ALARM_STATISTICS { + u32 cnt_parity_fail; + u32 cnt_rate_illegal; + u32 cnt_crc8_fail; + u32 cnt_mcs_fail; + u32 cnt_ofdm_fail; + u32 cnt_ofdm_fail_pre; /* For RTL8881A */ + u32 cnt_cck_fail; + u32 cnt_all; + u32 cnt_all_pre; + u32 cnt_fast_fsync; + u32 cnt_sb_search_fail; + u32 cnt_ofdm_cca; + u32 cnt_cck_cca; + u32 cnt_cca_all; + u32 cnt_bw_usc; /* Gary */ + u32 cnt_bw_lsc; /* Gary */ + u32 cnt_cck_crc32_error; + u32 cnt_cck_crc32_ok; + u32 cnt_ofdm_crc32_error; + u32 cnt_ofdm_crc32_ok; + u32 cnt_ht_crc32_error; + u32 cnt_ht_crc32_ok; + u32 cnt_vht_crc32_error; + u32 cnt_vht_crc32_ok; + u32 cnt_crc32_error_all; + u32 cnt_crc32_ok_all; + boolean cck_block_enable; + boolean ofdm_block_enable; + u32 dbg_port0; + boolean edcca_flag; +}; + +enum dm_dig_op_e { + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_BACKOFF = 2, + DIG_TYPE_RX_GAIN_MIN = 3, + DIG_TYPE_RX_GAIN_MAX = 4, + DIG_TYPE_ENABLE = 5, + DIG_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}; + +/* +enum dm_cck_pdth_e +{ + CCK_PD_STAGE_LowRssi = 0, + CCK_PD_STAGE_HighRssi = 1, + CCK_PD_STAGE_MAX = 3, +}; + +enum dm_dig_ext_port_alg_e +{ + DIG_EXT_PORT_STAGE_0 = 0, + DIG_EXT_PORT_STAGE_1 = 1, + DIG_EXT_PORT_STAGE_2 = 2, + DIG_EXT_PORT_STAGE_3 = 3, + DIG_EXT_PORT_STAGE_MAX = 4, +}; + +enum dm_dig_connect_e +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + dig_multi_sta_disconnect = 3, + dig_multi_sta_connect = 4, + DIG_CONNECT_MAX +}; + +#define DM_MultiSTA_InitGainChangeNotify(Event) {dm_dig_table.cur_multi_sta_connect_state = Event;} + +#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_connect) + +#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(dig_multi_sta_disconnect) +*/ + +enum phydm_pause_type { + PHYDM_PAUSE = BIT(0), + PHYDM_RESUME = BIT(1) +}; + +enum phydm_pause_level { + /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ + PHYDM_PAUSE_LEVEL_0 = 0, + PHYDM_PAUSE_LEVEL_1 = 1, + PHYDM_PAUSE_LEVEL_2 = 2, + PHYDM_PAUSE_LEVEL_3 = 3, + PHYDM_PAUSE_LEVEL_4 = 4, + PHYDM_PAUSE_LEVEL_5 = 5, + PHYDM_PAUSE_LEVEL_6 = 6, + PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ +}; + +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_FALSEALARM_THRESH_LOW 400 +#define DM_FALSEALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x20 +#define DM_DIG_MAX_OF_MIN_NIC 0x3e + +#define DM_DIG_MAX_AP 0x3e +#define DM_DIG_MIN_AP 0x20 +#define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */ +#define DM_DIG_MIN_AP_DFS 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +#define DM_DIG_FA_TH0 0x200/* 0x20 */ + +#define DM_DIG_FA_TH1 0x300 +#define DM_DIG_FA_TH2 0x400 +/* this is for 92d */ +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +#define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */ +#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */ +#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */ +#define RSSI_OFFSET_DIG 0x05 +#define LARGE_FA_TIMEOUT 60 + +void +odm_change_dynamic_init_gain_thresh( + void *p_dm_void, + u32 dm_type, + u32 dm_value +); + +void +odm_write_dig( + void *p_dm_void, + u8 current_igi +); + +void +odm_pause_dig( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 igi_value +); + +void +odm_dig_init( + void *p_dm_void +); + +void +odm_DIG( + void *p_dm_void +); + +void +odm_dig_by_rssi_lps( + void *p_dm_void +); + +void +odm_false_alarm_counter_statistics( + void *p_dm_void +); + +void +odm_pause_cck_packet_detection( + void *p_dm_void, + enum phydm_pause_type pause_type, + enum phydm_pause_level pause_level, + u8 cck_pd_threshold +); + +void +odm_cck_packet_detection_thresh( + void *p_dm_void +); + +void +odm_write_cck_cca_thres( + void *p_dm_void, + u8 cur_cck_cca_thres +); + +boolean +phydm_dig_go_up_check( + void *p_dm_void +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h new file mode 100644 index 000000000000..3546553d4ab0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamic_rx_path.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYMICRXPATH_H__ +#define __PHYDMDYMICRXPATH_H__ + +#define DYNAMIC_RX_PATH_VERSION "1.0" /*2016.07.15 Dino */ + +#define DRP_RSSI_TH 35 + +#define INIT_DRP_TIMMER 0 +#define CANCEL_DRP_TIMMER 1 +#define RELEASE_DRP_TIMMER 2 + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c new file mode 100644 index 000000000000..97925a594341 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.c @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void odm_dynamic_bb_power_saving_init(void *p_dm_void) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _dynamic_power_saving *p_dm_ps_table = &p_dm_odm->dm_ps_table; + + p_dm_ps_table->pre_cca_state = CCA_MAX; + p_dm_ps_table->cur_cca_state = CCA_MAX; + p_dm_ps_table->pre_rf_state = RF_MAX; + p_dm_ps_table->cur_rf_state = RF_MAX; + p_dm_ps_table->rssi_val_min = 0; + p_dm_ps_table->initialize = 0; +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h new file mode 100644 index 000000000000..9220507dfcde --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_dynamicbbpowersaving.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ +#define __PHYDMDYNAMICBBPOWERSAVING_H__ + +#define DYNAMIC_BBPWRSAV_VERSION "1.1" + + +struct _dynamic_power_saving { + u8 pre_cca_state; + u8 cur_cca_state; + + u8 pre_rf_state; + u8 cur_rf_state; + + int rssi_val_min; + + u8 initialize; + u32 reg874, regc70, reg85c, rega74; + +}; + +#define dm_rf_saving odm_rf_saving + +void +odm_dynamic_bb_power_saving_init( + void *p_dm_void +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h new file mode 100644 index 000000000000..2b47469bd96b --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_edcaturbocheck.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMEDCATURBOCHECK_H__ +#define __PHYDMEDCATURBOCHECK_H__ + + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_hwconfig.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_hwconfig.c new file mode 100644 index 000000000000..35a040632c9e --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_hwconfig.c @@ -0,0 +1,1652 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm_odm)) +#define READ_AND_CONFIG_TC(ic, txt) (odm_read_and_config_tc_##ic##txt(p_dm_odm)) + +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define READ_AND_CONFIG(ic, txt) do {\ + if (p_dm_odm->is_mp_chip)\ + READ_AND_CONFIG_MP(ic, txt);\ + else\ + READ_AND_CONFIG_TC(ic, txt);\ + } while (0) +#else +#define READ_AND_CONFIG READ_AND_CONFIG_MP +#endif + +#define READ_FIRMWARE_MP(ic, txt) (odm_read_firmware_mp_##ic##txt(p_dm_odm, p_firmware, p_size)) +#define READ_FIRMWARE_TC(ic, txt) (odm_read_firmware_tc_##ic##txt(p_dm_odm, p_firmware, p_size)) + +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define READ_FIRMWARE(ic, txt) do {\ + if (p_dm_odm->is_mp_chip)\ + READ_FIRMWARE_MP(ic, txt);\ + else\ + READ_FIRMWARE_TC(ic, txt);\ + } while (0) +#else +#define READ_FIRMWARE READ_FIRMWARE_MP +#endif + +#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt()) +#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt()) + +#if (PHYDM_TESTCHIP_SUPPORT == 1) + #define GET_VERSION(ic, txt) (p_dm_odm->is_mp_chip ? GET_VERSION_MP(ic, txt) : GET_VERSION_TC(ic, txt)) +#else + #define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt) +#endif + +u8 +odm_query_rx_pwr_percentage( + s8 ant_power +) +{ + if ((ant_power <= -100) || (ant_power >= 20)) + return 0; + else if (ant_power >= 0) + return 100; + else + return 100 + ant_power; +} + +/* + * 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. + * IF other SW team do not support the feature, remove this section.?? + * */ +s32 +odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_lenovo( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig +) +{ + s32 ret_sig = 0; + return ret_sig; +} + +s32 +odm_signal_scale_mapping_92c_series_patch_rt_cid_819x_netcore( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig +) +{ + s32 ret_sig = 0; + return ret_sig; +} + +s32 +odm_signal_scale_mapping_92c_series( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig +) +{ + s32 ret_sig = 0; +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if (p_dm_odm->support_interface == ODM_ITRF_PCIE) { + /* step 1. Scale mapping. */ + if (curr_sig >= 61 && curr_sig <= 100) + ret_sig = 90 + ((curr_sig - 60) / 4); + else if (curr_sig >= 41 && curr_sig <= 60) + ret_sig = 78 + ((curr_sig - 40) / 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 5 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 5) * 2) / 3); + else if (curr_sig == 4) + ret_sig = 36; + else if (curr_sig == 3) + ret_sig = 27; + else if (curr_sig == 2) + ret_sig = 18; + else if (curr_sig == 1) + ret_sig = 9; + else + ret_sig = curr_sig; + } +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if ((p_dm_odm->support_interface == ODM_ITRF_USB) || (p_dm_odm->support_interface == ODM_ITRF_SDIO)) { + if (curr_sig >= 51 && curr_sig <= 100) + ret_sig = 100; + else if (curr_sig >= 41 && curr_sig <= 50) + ret_sig = 80 + ((curr_sig - 40) * 2); + else if (curr_sig >= 31 && curr_sig <= 40) + ret_sig = 66 + (curr_sig - 30); + else if (curr_sig >= 21 && curr_sig <= 30) + ret_sig = 54 + (curr_sig - 20); + else if (curr_sig >= 10 && curr_sig <= 20) + ret_sig = 42 + (((curr_sig - 10) * 2) / 3); + else if (curr_sig >= 5 && curr_sig <= 9) + ret_sig = 22 + (((curr_sig - 5) * 3) / 2); + else if (curr_sig >= 1 && curr_sig <= 4) + ret_sig = 6 + (((curr_sig - 1) * 3) / 2); + else + ret_sig = curr_sig; + } + +#endif + return ret_sig; +} +s32 +odm_signal_scale_mapping( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig +) +{ + { + return curr_sig; + } +} + +static u8 +odm_evm_db_to_percentage( + s8 value +) +{ + /* */ + /* -33dB~0dB to 0%~99% */ + /* */ + s8 ret_val; + + ret_val = value; + ret_val /= 2; + + /*dbg_print("value=%d\n", value);*/ + /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C value=%d / %x\n", ret_val, ret_val));*/ + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -33) + ret_val = -33; + + ret_val = 0 - ret_val; + ret_val *= 3; + + if (ret_val == 99) + ret_val = 100; + + return (u8)ret_val; +} + +static u8 +odm_evm_dbm_jaguar_series( + s8 value +) +{ + s8 ret_val = value; + + /* -33dB~0dB to 33dB ~ 0dB */ + if (ret_val == -128) + ret_val = 127; + else if (ret_val < 0) + ret_val = 0 - ret_val; + + ret_val = ret_val >> 1; + return (u8)ret_val; +} + +static s16 +odm_cfo( + s8 value +) +{ + s16 ret_val; + + if (value < 0) { + ret_val = 0 - value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ + ret_val = ret_val | BIT(12); /* set bit12 as 1 for negative cfo */ + } else { + ret_val = value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; /* *2.5~=312.5/2^7 */ + } + return ret_val; +} + +u8 +phydm_rate_to_num_ss( + struct PHY_DM_STRUCT *p_dm_odm, + u8 data_rate +) +{ + u8 num_ss = 1; + + if (data_rate <= ODM_RATE54M) + num_ss = 1; + else if (data_rate <= ODM_RATEMCS31) + num_ss = ((data_rate - ODM_RATEMCS0) >> 3) + 1; + else if (data_rate <= ODM_RATEVHTSS1MCS9) + num_ss = 1; + else if (data_rate <= ODM_RATEVHTSS2MCS9) + num_ss = 2; + else if (data_rate <= ODM_RATEVHTSS3MCS9) + num_ss = 3; + else if (data_rate <= ODM_RATEVHTSS4MCS9) + num_ss = 4; + + return num_ss; +} + + + +void +odm_rx_phy_bw_jaguar_series_parsing( + struct _odm_phy_status_info_ *p_phy_info, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _phy_status_rpt_8812 *p_phy_sta_rpt +) +{ + + if (p_pktinfo->data_rate <= ODM_RATE54M) { + switch (p_phy_sta_rpt->r_RFMOD) { + case 1: + if (p_phy_sta_rpt->sub_chnl == 0) + p_phy_info->band_width = 1; + else + p_phy_info->band_width = 0; + break; + + case 2: + if (p_phy_sta_rpt->sub_chnl == 0) + p_phy_info->band_width = 2; + else if (p_phy_sta_rpt->sub_chnl == 9 || p_phy_sta_rpt->sub_chnl == 10) + p_phy_info->band_width = 1; + else + p_phy_info->band_width = 0; + break; + + default: + case 0: + p_phy_info->band_width = 0; + break; + } + } + +} + +void +odm_rx_phy_status_jaguar_series_parsing( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ + u8 i, max_spatial_stream; + s8 rx_pwr[4], rx_pwr_all = 0; + u8 EVM, evm_dbm, PWDB_ALL = 0, PWDB_ALL_BT; + u8 RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; + u8 is_cck_rate = 0; + u8 rf_rx_num = 0; + u8 cck_highpwr = 0; + u8 LNA_idx, VGA_idx; + struct _phy_status_rpt_8812 *p_phy_sta_rpt = (struct _phy_status_rpt_8812 *)p_phy_status; + struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table; + u8 num_ss; + + odm_rx_phy_bw_jaguar_series_parsing(p_phy_info, p_pktinfo, p_phy_sta_rpt); + + if (p_pktinfo->data_rate <= ODM_RATE11M) + is_cck_rate = true; + else + is_cck_rate = false; + + if (p_pktinfo->is_to_self) + p_dm_odm->curr_station_id = p_pktinfo->station_id; + else + p_dm_odm->curr_station_id = 0xff; + + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_B] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_C] = -1; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_D] = -1; + + if (is_cck_rate) { + u8 cck_agc_rpt; + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; + + /*(1)Hardware does not provide RSSI for CCK*/ + /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + cck_highpwr = p_dm_odm->is_cck_high_power; + + cck_agc_rpt = p_phy_sta_rpt->cfosho[0] ; + LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + if (p_dm_odm->support_ic_type == ODM_RTL8812) { + switch (LNA_idx) { + case 7: + if (VGA_idx <= 27) + rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/ + else + rx_pwr_all = -100; + break; + case 6: + rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/ + break; + case 5: + rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/ + break; + case 4: + rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/ + break; + case 3: + /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/ + rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/ + break; + case 2: + if (cck_highpwr) + rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/ + else + rx_pwr_all = -6 + 2 * (5 - VGA_idx); + break; + case 1: + rx_pwr_all = 8 - 2 * VGA_idx; + break; + case 0: + rx_pwr_all = 14 - 2 * VGA_idx; + break; + default: + /*dbg_print("CCK Exception default\n");*/ + break; + } + rx_pwr_all += 6; + PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); + + if (cck_highpwr == false) { + if (PWDB_ALL >= 80) + PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; + else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) + PWDB_ALL += 3; + if (PWDB_ALL > 100) + PWDB_ALL = 100; + } + } else if (p_dm_odm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) { + s8 pout = -6; + + switch (LNA_idx) { + case 5: + rx_pwr_all = pout - 32 - (2 * VGA_idx); + break; + case 4: + rx_pwr_all = pout - 24 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = pout - 11 - (2 * VGA_idx); + break; + case 1: + rx_pwr_all = pout + 5 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = pout + 21 - (2 * VGA_idx); + break; + } + PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); + } else if (p_dm_odm->support_ic_type == ODM_RTL8814A || p_dm_odm->support_ic_type == ODM_RTL8822B) { + s8 pout = -6; + + switch (LNA_idx) { + /*CCK only use LNA: 2, 3, 5, 7*/ + case 7: + rx_pwr_all = pout - 32 - (2 * VGA_idx); + break; + case 5: + rx_pwr_all = pout - 22 - (2 * VGA_idx); + break; + case 3: + rx_pwr_all = pout - 2 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = pout + 5 - (2 * VGA_idx); + break; + default: + break; + } + PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); + } + + p_dm_odm->cck_lna_idx = LNA_idx; + p_dm_odm->cck_vga_idx = VGA_idx; + p_phy_info->rx_pwdb_all = PWDB_ALL; + p_phy_info->bt_rx_rssi_percentage = PWDB_ALL; + p_phy_info->recv_signal_power = rx_pwr_all; + /*(3) Get Signal Quality (EVM)*/ + { + u8 SQ, SQ_rpt; + + if (p_phy_info->rx_pwdb_all > 40 && !p_dm_odm->is_in_hct_test) + SQ = 100; + else { + SQ_rpt = p_phy_sta_rpt->pwdb_all; + + if (SQ_rpt > 64) + SQ = 0; + else if (SQ_rpt < 20) + SQ = 100; + else + SQ = ((64 - SQ_rpt) * 100) / 44; + } + + /* dbg_print("cck SQ = %d\n", SQ); */ + p_phy_info->signal_quality = SQ; + p_phy_info->rx_mimo_signal_quality[ODM_RF_PATH_A] = SQ; + } + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (i == 0) + p_phy_info->rx_mimo_signal_strength[0] = PWDB_ALL; + else + p_phy_info->rx_mimo_signal_strength[i] = 0; + } + } else { + /*is OFDM rate*/ + p_dm_fat_table->hw_antsw_occur = p_phy_sta_rpt->hw_antsw_occur; + + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; + + /*(1)Get RSSI for OFDM rate*/ + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + /*2008/01/30 MH we will judge RF RX path now.*/ + /* dbg_print("p_dm_odm->rf_path_rx_enable = %x\n", p_dm_odm->rf_path_rx_enable); */ + if (p_dm_odm->rf_path_rx_enable & BIT(i)) + rf_rx_num++; + /* else */ + /* continue; */ + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ + /* if((p_dm_odm->support_ic_type & (ODM_RTL8812|ODM_RTL8821)) && (!p_dm_odm->is_mp_chip)) */ + if (i < ODM_RF_PATH_C) + rx_pwr[i] = (p_phy_sta_rpt->gain_trsw[i] & 0x7F) - 110; + else + rx_pwr[i] = (p_phy_sta_rpt->gain_trsw_cd[i - 2] & 0x7F) - 110; + /* else */ + /*rx_pwr[i] = ((p_phy_sta_rpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ + + p_phy_info->rx_pwr[i] = rx_pwr[i]; + + /* Translate DBM to percentage. */ + RSSI = odm_query_rx_pwr_percentage(rx_pwr[i]); + + /*total_rssi += RSSI;*/ + /*Get the best two RSSI*/ + if (RSSI > best_rssi && RSSI > second_rssi) { + second_rssi = best_rssi; + best_rssi = RSSI; + } else if (RSSI > second_rssi && RSSI <= best_rssi) + second_rssi = RSSI; + + /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/ + + p_phy_info->rx_mimo_signal_strength[i] = (u8) RSSI; + + /*Get Rx snr value in DB*/ + if (i < ODM_RF_PATH_C) + p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->rxsnr[i] / 2; + else if (p_dm_odm->support_ic_type & (ODM_RTL8814A | ODM_RTL8822B)) + p_phy_info->rx_snr[i] = p_dm_odm->phy_dbg_info.rx_snr_db[i] = p_phy_sta_rpt->csi_current[i - 2] / 2; + + /*(2) CFO_short & CFO_tail*/ + if (i < ODM_RF_PATH_C) { + p_phy_info->cfo_short[i] = odm_cfo((p_phy_sta_rpt->cfosho[i])); + p_phy_info->cfo_tail[i] = odm_cfo((p_phy_sta_rpt->cfotail[i])); + } + } + + /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ + if ((p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!p_dm_odm->is_mp_chip)) + rx_pwr_all = (p_phy_sta_rpt->pwdb_all & 0x7f) - 110; + else + rx_pwr_all = (((p_phy_sta_rpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ + + PWDB_ALL_BT = PWDB_ALL = odm_query_rx_pwr_percentage(rx_pwr_all); + + p_phy_info->rx_pwdb_all = PWDB_ALL; + /*ODM_RT_TRACE(p_dm_odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",p_phy_info->rx_pwdb_all));*/ + p_phy_info->bt_rx_rssi_percentage = PWDB_ALL_BT; + p_phy_info->rx_power = rx_pwr_all; + p_phy_info->recv_signal_power = rx_pwr_all; + + if ((p_dm_odm->support_platform == ODM_WIN) && (p_dm_odm->patch_id == 19)) { + /*do nothing*/ + } else { + /*p_mgnt_info->customer_id != RT_CID_819X_LENOVO*/ + + /*(4)EVM of OFDM rate*/ + + if ((p_pktinfo->data_rate >= ODM_RATEMCS8) && + (p_pktinfo->data_rate <= ODM_RATEMCS15)) + max_spatial_stream = 2; + else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS2MCS0) && + (p_pktinfo->data_rate <= ODM_RATEVHTSS2MCS9)) + max_spatial_stream = 2; + else if ((p_pktinfo->data_rate >= ODM_RATEMCS16) && + (p_pktinfo->data_rate <= ODM_RATEMCS23)) + max_spatial_stream = 3; + else if ((p_pktinfo->data_rate >= ODM_RATEVHTSS3MCS0) && + (p_pktinfo->data_rate <= ODM_RATEVHTSS3MCS9)) + max_spatial_stream = 3; + else + max_spatial_stream = 1; + + /*if (p_pktinfo->is_packet_match_bssid) */ + { + /*dbg_print("p_pktinfo->data_rate = %d\n", p_pktinfo->data_rate);*/ + + for (i = 0; i < max_spatial_stream; i++) { + /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ + /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ + /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ + + if (p_pktinfo->data_rate >= ODM_RATE6M && p_pktinfo->data_rate <= ODM_RATE54M) { + if (i == ODM_RF_PATH_A) { + EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->sigevm)); /*dbm*/ + EVM += 20; + if (EVM > 100) + EVM = 100; + } + } else { + if (i < ODM_RF_PATH_C) { + if (p_phy_sta_rpt->rxevm[i] == -128) + p_phy_sta_rpt->rxevm[i] = -25; + EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm[i])); /*dbm*/ + } else { + if (p_phy_sta_rpt->rxevm_cd[i - 2] == -128) + p_phy_sta_rpt->rxevm_cd[i - 2] = -25; + EVM = odm_evm_db_to_percentage((p_phy_sta_rpt->rxevm_cd[i - 2])); /*dbm*/ + } + } + + if (i < ODM_RF_PATH_C) + evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm[i]); + else + evm_dbm = odm_evm_dbm_jaguar_series(p_phy_sta_rpt->rxevm_cd[i - 2]); + /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ + /*p_pktinfo->data_rate, p_phy_sta_rpt->rxevm[i], "%", EVM));*/ + + { + if (i == ODM_RF_PATH_A) { + /*Fill value in RFD, Get the first spatial stream only*/ + p_phy_info->signal_quality = EVM; + } + p_phy_info->rx_mimo_signal_quality[i] = EVM; + p_phy_info->rx_mimo_evm_dbm[i] = evm_dbm; + } + } + } + } + + num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfotail, num_ss); + + } + /* dbg_print("is_cck_rate= %d, p_phy_info->signal_strength=%d % PWDB_AL=%d rf_rx_num=%d\n", is_cck_rate, p_phy_info->signal_strength, PWDB_ALL, rf_rx_num); */ + + /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ + /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ + if (is_cck_rate) { + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, PWDB_ALL));/*PWDB_ALL;*/ + } else { + if (rf_rx_num != 0) { + /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ + if (rf_rx_num == 1) + avg_rssi = best_rssi; + else + avg_rssi = (best_rssi + second_rssi) / 2; + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_dm_odm, avg_rssi)); + } + } + p_dm_odm->rx_pwdb_ave = p_dm_odm->rx_pwdb_ave + p_phy_info->rx_pwdb_all; + + p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_anta; + p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_antb; + p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_antc; + p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_antd; +} + + +void +phydm_reset_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm, + u8 station_id +) +{ + struct sta_info *p_entry; + p_entry = p_dm_odm->p_odm_sta_info[station_id]; + + if (!IS_STA_VALID(p_entry)) { + /**/ + return; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("Reset RSSI for macid = (( %d ))\n", station_id)); + + p_entry->rssi_stat.undecorated_smoothed_cck = -1; + p_entry->rssi_stat.undecorated_smoothed_ofdm = -1; + p_entry->rssi_stat.undecorated_smoothed_pwdb = -1; + p_entry->rssi_stat.ofdm_pkt = 0; + p_entry->rssi_stat.cck_pkt = 0; + p_entry->rssi_stat.cck_sum_power = 0; + p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_INIT; + p_entry->rssi_stat.packet_map = 0; + p_entry->rssi_stat.valid_bit = 0; + + /*in WIN Driver: sta_ID==0->p_entry==NULL -> default port HAL_Data*/ +} + +void +odm_init_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + +} + +void +odm_process_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ + + s32 undecorated_smoothed_pwdb, undecorated_smoothed_cck, undecorated_smoothed_ofdm, rssi_ave, cck_pkt; + u8 i, is_cck_rate = 0; + u8 RSSI_max, RSSI_min; + u32 weighting = 0; + u8 send_rssi_2_fw = 0; + struct sta_info *p_entry; + + if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; + + if (!IS_STA_VALID(p_entry)) { + return; + /**/ + } + + { + if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ + return; + } + + if (p_pktinfo->is_packet_beacon) + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; + + is_cck_rate = (p_pktinfo->data_rate <= ODM_RATE11M) ? true : false; + p_dm_odm->rx_rate = p_pktinfo->data_rate; + + /* --------------Statistic for antenna/path diversity------------------ */ + if (p_dm_odm->support_ability & ODM_BB_ANT_DIV) { + } + /* -----------------Smart Antenna Debug Message------------------ */ + + undecorated_smoothed_cck = p_entry->rssi_stat.undecorated_smoothed_cck; + undecorated_smoothed_ofdm = p_entry->rssi_stat.undecorated_smoothed_ofdm; + undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + + if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { + + if (!is_cck_rate) { /* ofdm rate */ + { + if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B] == 0) { + rssi_ave = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_B = 0; + } else { + /*dbg_print("p_rfd->status.rx_mimo_signal_strength[0] = %d, p_rfd->status.rx_mimo_signal_strength[1] = %d\n",*/ + /*p_rfd->status.rx_mimo_signal_strength[0], p_rfd->status.rx_mimo_signal_strength[1]);*/ + p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; + + if (p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A] > p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]) { + RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; + } else { + RSSI_max = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; + RSSI_min = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + } + if ((RSSI_max - RSSI_min) < 3) + rssi_ave = RSSI_max; + else if ((RSSI_max - RSSI_min) < 6) + rssi_ave = RSSI_max - 1; + else if ((RSSI_max - RSSI_min) < 10) + rssi_ave = RSSI_max - 2; + else + rssi_ave = RSSI_max - 3; + } + } + + /* 1 Process OFDM RSSI */ + if (undecorated_smoothed_ofdm <= 0) { /* initialize */ + undecorated_smoothed_ofdm = p_phy_info->rx_pwdb_all; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_INIT: (( %d ))\n", undecorated_smoothed_ofdm)); + } else { + if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_ofdm) { + undecorated_smoothed_ofdm = + (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + + (rssi_ave)) / (RX_SMOOTH_FACTOR); + undecorated_smoothed_ofdm = undecorated_smoothed_ofdm + 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_1: (( %d ))\n", undecorated_smoothed_ofdm)); + } else { + undecorated_smoothed_ofdm = + (((undecorated_smoothed_ofdm)*(RX_SMOOTH_FACTOR - 1)) + + (rssi_ave)) / (RX_SMOOTH_FACTOR); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("OFDM_2: (( %d ))\n", undecorated_smoothed_ofdm)); + } + } + if (p_entry->rssi_stat.ofdm_pkt != 64) { + i = 63; + p_entry->rssi_stat.ofdm_pkt -= (u8)(((p_entry->rssi_stat.packet_map >> i) & BIT(0)) - 1); + } + p_entry->rssi_stat.packet_map = (p_entry->rssi_stat.packet_map << 1) | BIT(0); + + } else { + rssi_ave = p_phy_info->rx_pwdb_all; + p_dm_odm->RSSI_A = (u8) p_phy_info->rx_pwdb_all; + p_dm_odm->RSSI_B = 0xFF; + p_dm_odm->RSSI_C = 0xFF; + p_dm_odm->RSSI_D = 0xFF; + + if (p_entry->rssi_stat.cck_pkt <= 63) + p_entry->rssi_stat.cck_pkt++; + + /* 1 Process CCK RSSI */ + if (undecorated_smoothed_cck <= 0) { /* initialize */ + undecorated_smoothed_cck = p_phy_info->rx_pwdb_all; + p_entry->rssi_stat.cck_sum_power = (u16)p_phy_info->rx_pwdb_all ; /*reset*/ + p_entry->rssi_stat.cck_pkt = 1; /*reset*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_INIT: (( %d ))\n", undecorated_smoothed_cck)); + } else if (p_entry->rssi_stat.cck_pkt <= CCK_RSSI_INIT_COUNT) { + + p_entry->rssi_stat.cck_sum_power = p_entry->rssi_stat.cck_sum_power + (u16)p_phy_info->rx_pwdb_all; + undecorated_smoothed_cck = p_entry->rssi_stat.cck_sum_power / p_entry->rssi_stat.cck_pkt; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_0: (( %d )), SumPow = (( %d )), cck_pkt = (( %d ))\n", + undecorated_smoothed_cck, p_entry->rssi_stat.cck_sum_power, p_entry->rssi_stat.cck_pkt)); + } else { + if (p_phy_info->rx_pwdb_all > (u32)undecorated_smoothed_cck) { + undecorated_smoothed_cck = + (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + + (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); + undecorated_smoothed_cck = undecorated_smoothed_cck + 1; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_1: (( %d ))\n", undecorated_smoothed_cck)); + } else { + undecorated_smoothed_cck = + (((undecorated_smoothed_cck)*(RX_SMOOTH_FACTOR - 1)) + + (p_phy_info->rx_pwdb_all)) / (RX_SMOOTH_FACTOR); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("CCK_2: (( %d ))\n", undecorated_smoothed_cck)); + } + } + i = 63; + p_entry->rssi_stat.ofdm_pkt -= (u8)((p_entry->rssi_stat.packet_map >> i) & BIT(0)); + p_entry->rssi_stat.packet_map = p_entry->rssi_stat.packet_map << 1; + } + + /* if(p_entry) */ + { + /* 2011.07.28 LukeLee: modified to prevent unstable CCK RSSI */ + if (p_entry->rssi_stat.ofdm_pkt == 64) { /* speed up when all packets are OFDM*/ + undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_0[%d] = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck)); + } else { + if (p_entry->rssi_stat.valid_bit < 64) + p_entry->rssi_stat.valid_bit++; + + if (p_entry->rssi_stat.valid_bit == 64) { + weighting = ((p_entry->rssi_stat.ofdm_pkt) > 4) ? 64 : (p_entry->rssi_stat.ofdm_pkt << 4); + undecorated_smoothed_pwdb = (weighting * undecorated_smoothed_ofdm + (64 - weighting) * undecorated_smoothed_cck) >> 6; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_1[%d] = (( %d )), W = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, weighting)); + } else { + if (p_entry->rssi_stat.valid_bit != 0) + undecorated_smoothed_pwdb = (p_entry->rssi_stat.ofdm_pkt * undecorated_smoothed_ofdm + (p_entry->rssi_stat.valid_bit - p_entry->rssi_stat.ofdm_pkt) * undecorated_smoothed_cck) / p_entry->rssi_stat.valid_bit; + else + undecorated_smoothed_pwdb = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("PWDB_2[%d] = (( %d )), ofdm_pkt = (( %d )), Valid_Bit = (( %d ))\n", p_pktinfo->station_id, undecorated_smoothed_cck, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.valid_bit)); + } + } + + if ((p_entry->rssi_stat.ofdm_pkt >= 1 || p_entry->rssi_stat.cck_pkt >= 5) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_INIT)) { + + send_rssi_2_fw = 1; + p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_SEND; + } + + p_entry->rssi_stat.undecorated_smoothed_cck = undecorated_smoothed_cck; + p_entry->rssi_stat.undecorated_smoothed_ofdm = undecorated_smoothed_ofdm; + p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; + + if (send_rssi_2_fw) { /* Trigger init rate by RSSI */ + + if (p_entry->rssi_stat.ofdm_pkt != 0) + p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_ofdm; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("[Send to FW] PWDB = (( %d )), ofdm_pkt = (( %d )), cck_pkt = (( %d ))\n", + undecorated_smoothed_pwdb, p_entry->rssi_stat.ofdm_pkt, p_entry->rssi_stat.cck_pkt)); + + phydm_ra_rssi_rpt_wk(p_dm_odm); + } + } + } +} + + +/* + * Endianness before calling this API + * */ + +void +odm_phy_status_query_jaguar_series( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ + odm_rx_phy_status_jaguar_series_parsing(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); + odm_process_rssi_for_dm(p_dm_odm, p_phy_info, p_pktinfo); + +} + +void +odm_phy_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ + if (p_dm_odm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE) { + phydm_rx_phy_status_new_type(p_dm_odm, p_phy_status, p_pktinfo, p_phy_info); + return; + } + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) + odm_phy_status_query_jaguar_series(p_dm_odm, p_phy_info, p_phy_status, p_pktinfo); + +} + +/* For future use. */ +void +odm_mac_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_mac_status, + u8 mac_id, + boolean is_packet_match_bssid, + boolean is_packet_to_self, + boolean is_packet_beacon +) +{ + /* 2011/10/19 Driver team will handle in the future. */ + +} + +/* + * If you want to add a new IC, Please follow below template and generate a new one. + * + * */ + +enum hal_status +odm_config_rf_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_config_type config_type, + enum odm_rf_radio_path_e e_rf_path +) +{ + enum hal_status ret = HAL_STATUS_SUCCESS; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>odm_config_rf_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", + p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + + /* 1 All platforms support */ + if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_RF_RADIO) { + if (e_rf_path == ODM_RF_PATH_A) + READ_AND_CONFIG(8821c, _radioa); + } else if (config_type == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG(8821c, _txpwr_lmt); + } + + return ret; +} + +enum hal_status +odm_config_rf_with_tx_pwr_track_header_file( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>odm_config_rf_with_tx_pwr_track_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", + p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + + /* 1 All platforms support */ + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + READ_AND_CONFIG(8821c, _txpowertrack); + + return HAL_STATUS_SUCCESS; +} + +enum hal_status +odm_config_bb_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_bb_config_type config_type +) +{ + enum hal_status ret = HAL_STATUS_SUCCESS; + + /* 1 All platforms support */ + if (p_dm_odm->support_ic_type == ODM_RTL8821C) { + if (config_type == CONFIG_BB_PHY_REG) + READ_AND_CONFIG(8821c, _phy_reg); + else if (config_type == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG(8821c, _agc_tab); + /* According to RFEtype, choosing correct AGC table*/ + if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_BTG) + AGC_DIFF_CONFIG_MP(8821c, btg); + } else if (config_type == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8821c, _phy_reg_pg); + else if (config_type == CONFIG_BB_AGC_TAB_DIFF) { + if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG) + AGC_DIFF_CONFIG_MP(8821c, btg); + else if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLG) + AGC_DIFF_CONFIG_MP(8821c, wlg); + } + } + + return ret; +} + +enum hal_status +odm_config_mac_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + enum hal_status ret = HAL_STATUS_SUCCESS; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>odm_config_mac_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n", + p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type)); + + + /* 1 All platforms support */ + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + READ_AND_CONFIG(8821c, _mac_reg); + + return ret; +} + +enum hal_status +odm_config_fw_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_fw_config_type config_type, + u8 *p_firmware, + u32 *p_size +) +{ + return HAL_STATUS_SUCCESS; +} + +u32 +odm_get_hw_img_version( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 version = 0; + + /*1 All platforms support*/ + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + version = GET_VERSION(8821c, _mac_reg); + + return version; +} + +/* For 8822B only!! need to move to FW finally */ +/*==============================================*/ + +boolean +phydm_query_is_mu_api( + struct PHY_DM_STRUCT *p_phydm, + u8 ppdu_idx, + u8 *p_data_rate, + u8 *p_gid +) +{ + u8 data_rate = 0, gid = 0; + boolean is_mu = FALSE; + + data_rate = p_phydm->phy_dbg_info.num_of_ppdu[ppdu_idx]; + gid = p_phydm->phy_dbg_info.gid_num[ppdu_idx]; + + if (data_rate & BIT(7)) { + is_mu = TRUE; + data_rate = data_rate & ~(BIT(7)); + } else + is_mu = FALSE; + + *p_data_rate = data_rate; + *p_gid = gid; + + return is_mu; + +} + +VOID +phydm_rx_statistic_cal( + struct PHY_DM_STRUCT *p_phydm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ + struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; + u8 date_rate = p_pktinfo->data_rate & ~(BIT(7)); + + if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) { + if (date_rate >= ODM_RATEVHTSS1MCS0) { + p_phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - 0x2C]++; + if (p_pktinfo->ppdu_cnt < 4) { + p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7); + p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; + } + } + + } else { + if (date_rate >= ODM_RATEVHTSS1MCS0) { + p_phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - 0x2C]++; + if (p_pktinfo->ppdu_cnt < 4) { + p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate; + p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid; + } + } + } + +} + +void +phydm_reset_phy_info( + struct PHY_DM_STRUCT *p_phydm, + struct _odm_phy_status_info_ *p_phy_info +) +{ + p_phy_info->rx_pwdb_all = 0; + p_phy_info->signal_quality = 0; + p_phy_info->band_width = 0; + p_phy_info->rx_count = 0; + odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_quality, 0, 4); + odm_memory_set(p_phydm, p_phy_info->rx_mimo_signal_strength, 0, 4); + odm_memory_set(p_phydm, p_phy_info->rx_snr, 0, 4); + + p_phy_info->rx_power = -110; + p_phy_info->recv_signal_power = -110; + p_phy_info->bt_rx_rssi_percentage = 0; + p_phy_info->signal_strength = 0; + p_phy_info->bt_coex_pwr_adjust = 0; + p_phy_info->channel = 0; + p_phy_info->is_mu_packet = 0; + p_phy_info->is_beamformed = 0; + p_phy_info->rxsc = 0; + odm_memory_set(p_phydm, p_phy_info->rx_pwr, -110, 4); + odm_memory_set(p_phydm, p_phy_info->cfo_short, 0, 8); + odm_memory_set(p_phydm, p_phy_info->cfo_tail, 0, 8); + odm_memory_set(p_phydm, p_phy_info->rx_mimo_evm_dbm, 0, 4); +} + +void +phydm_set_per_path_phy_info( + u8 rx_path, + s8 rx_pwr, + s8 rx_evm, + s8 cfo_tail, + s8 rx_snr, + struct _odm_phy_status_info_ *p_phy_info +) +{ + u8 evm_dbm = 0; + u8 evm_percentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + if (rx_evm < 0) { + /* Calculate EVM in dBm */ + evm_dbm = ((u8)(0 - rx_evm) >> 1); + + /* Calculate EVM in percentage */ + if (evm_dbm >= 34) + evm_percentage = 100; + else + evm_percentage = (evm_dbm << 1) + (evm_dbm); + } + + p_phy_info->rx_pwr[rx_path] = rx_pwr; + /*p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm;*/ + + /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/ + p_phy_info->cfo_tail[rx_path] = cfo_tail; + p_phy_info->cfo_tail[rx_path] = ((p_phy_info->cfo_tail[rx_path] << 5) + (p_phy_info->cfo_tail[rx_path] << 2) + + (p_phy_info->cfo_tail[rx_path] << 1) + (p_phy_info->cfo_tail[rx_path])) >> 9; + if (evm_dbm == 64) + evm_dbm = 0; /*if 1SS rate, evm_dbm [2nd stream] =64*/ + + p_phy_info->rx_mimo_evm_dbm[rx_path] = evm_dbm; + + p_phy_info->rx_mimo_signal_strength[rx_path] = odm_query_rx_pwr_percentage(rx_pwr); + p_phy_info->rx_mimo_signal_quality[rx_path] = evm_percentage; + p_phy_info->rx_snr[rx_path] = rx_snr >> 1; +} + +void +phydm_set_common_phy_info( + s8 rx_power, + u8 channel, + boolean is_beamformed, + boolean is_mu_packet, + u8 bandwidth, + u8 signal_quality, + u8 rxsc, + struct _odm_phy_status_info_ *p_phy_info +) +{ + p_phy_info->rx_power = rx_power; /* RSSI in dB */ + p_phy_info->recv_signal_power = rx_power; /* RSSI in dB */ + p_phy_info->channel = channel; /* channel number */ + p_phy_info->is_beamformed = is_beamformed; /* apply BF */ + p_phy_info->is_mu_packet = is_mu_packet; /* MU packet */ + p_phy_info->rxsc = rxsc; + p_phy_info->rx_pwdb_all = odm_query_rx_pwr_percentage(rx_power); /* RSSI in percentage */ + p_phy_info->signal_quality = signal_quality; /* signal quality */ + p_phy_info->band_width = bandwidth; /* bandwidth */ +} + +void +phydm_get_rx_phy_status_type0( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info +) +{ + /* type 0 is used for cck packet */ + + struct _phy_status_rpt_jaguar2_type0 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type0 *)p_phy_status; + u8 i, SQ = 0; + s8 rx_power = p_phy_sta_rpt->pwdb - 110; + + +/* RTL8710B do not need recalculate the offset By James Liao@20170527 */ + + if (p_dm_odm->support_ic_type & ODM_RTL8821C) { + if (p_phy_sta_rpt->pwdb >= -57) + rx_power = p_phy_sta_rpt->pwdb - 100; + else + rx_power = p_phy_sta_rpt->pwdb - 102; + } + /* Calculate Signal Quality*/ + if (p_pktinfo->is_packet_match_bssid) { + if (p_phy_sta_rpt->signal_quality >= 64) + SQ = 0; + else if (p_phy_sta_rpt->signal_quality <= 20) + SQ = 100; + else { + /* mapping to 2~99% */ + SQ = 64 - p_phy_sta_rpt->signal_quality; + SQ = ((SQ << 3) + SQ) >> 2; + } + } + + /* Modify CCK PWDB if old AGC */ + if (p_dm_odm->cck_new_agc == false) { + u8 lna_idx, vga_idx; + + lna_idx = ((p_phy_sta_rpt->lna_h << 3) | p_phy_sta_rpt->lna_l); + vga_idx = p_phy_sta_rpt->vga; + +/* JJ ADD 20161014 */ + + } + + /* Update CCK packet counter */ + p_dm_odm->phy_dbg_info.num_qry_phy_status_cck++; + + /*CCK no STBC and LDPC*/ + p_dm_odm->phy_dbg_info.is_ldpc_pkt = false; + p_dm_odm->phy_dbg_info.is_stbc_pkt = false; + + /* Update Common information */ + phydm_set_common_phy_info(rx_power, p_phy_sta_rpt->channel, false, + false, ODM_BW20M, SQ, p_phy_sta_rpt->rxsc, p_phy_info); + + /* Update CCK pwdb */ + phydm_set_per_path_phy_info(ODM_RF_PATH_A, rx_power, 0, 0, 0, p_phy_info); /* Update per-path information */ + + p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; + p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; + p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; + p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; +} + +void +phydm_get_rx_phy_status_type1( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info +) +{ + /* type 1 is used for ofdm packet */ + + struct _phy_status_rpt_jaguar2_type1 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type1 *)p_phy_status; + s8 rx_pwr_db = -120; + u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; + boolean is_mu; + u8 num_ss; + + /* Update OFDM packet counter */ + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; + + /* Update per-path information */ + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (p_dm_odm->rx_ant_status & BIT(i)) { + s8 rx_path_pwr_db; + + /* RX path counter */ + rx_count++; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ + /* EVM report is reported by stream, not path */ + rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + phydm_set_per_path_phy_info(i, rx_path_pwr_db, p_phy_sta_rpt->rxevm[rx_count - 1], + p_phy_sta_rpt->cfo_tail[i], p_phy_sta_rpt->rxsnr[i], p_phy_info); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + p_phy_info->rx_count = rx_count - 1; + + /* Check if MU packet or not */ + if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63)) { + is_mu = true; + p_dm_odm->phy_dbg_info.num_qry_mu_pkt++; + } else + is_mu = false; + + /* count BF packet */ + p_dm_odm->phy_dbg_info.num_qry_bf_pkt = p_dm_odm->phy_dbg_info.num_qry_bf_pkt + p_phy_sta_rpt->beamformed; + + /*STBC or LDPC pkt*/ + p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; + p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; + + /* Check sub-channel */ + if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) + rxsc = p_phy_sta_rpt->l_rxsc; + else + rxsc = p_phy_sta_rpt->ht_rxsc; + + /* Check RX bandwidth */ + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + if ((rxsc >= 1) && (rxsc <= 8)) + bw = ODM_BW20M; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = ODM_BW40M; + else if (rxsc >= 13) + bw = ODM_BW80M; + else + bw = p_phy_sta_rpt->rf_mode; + } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ + if (p_phy_sta_rpt->rf_mode == 0) + bw = ODM_BW20M; + else if ((rxsc == 1) || (rxsc == 2)) + bw = ODM_BW20M; + else + bw = ODM_BW40M; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, + is_mu, bw, odm_evm_db_to_percentage(p_phy_sta_rpt->rxevm[0]), rxsc, p_phy_info); + + num_ss = phydm_rate_to_num_ss(p_dm_odm, p_pktinfo->data_rate); + + odm_parsing_cfo(p_dm_odm, p_pktinfo, p_phy_sta_rpt->cfo_tail, num_ss); + p_dm_odm->dm_fat_table.antsel_rx_keep_0 = p_phy_sta_rpt->antidx_a; + p_dm_odm->dm_fat_table.antsel_rx_keep_1 = p_phy_sta_rpt->antidx_b; + p_dm_odm->dm_fat_table.antsel_rx_keep_2 = p_phy_sta_rpt->antidx_c; + p_dm_odm->dm_fat_table.antsel_rx_keep_3 = p_phy_sta_rpt->antidx_d; + + if (p_pktinfo->is_packet_match_bssid) { + /* + dbg_print("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", p_phy_sta_rpt->channel, p_phy_sta_rpt->band, p_phy_sta_rpt->l_rxsc, p_phy_sta_rpt->ht_rxsc, p_phy_sta_rpt->rf_mode); + dbg_print("Antidx A = %d, B = %d, C = %d, D = %d\n", p_phy_sta_rpt->antidx_a, p_phy_sta_rpt->antidx_b, p_phy_sta_rpt->antidx_c, p_phy_sta_rpt->antidx_d); + dbg_print("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", p_phy_sta_rpt->pwdb[0], p_phy_sta_rpt->pwdb[1], p_phy_sta_rpt->pwdb[2], p_phy_sta_rpt->pwdb[3]); + dbg_print("EVM A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxevm[0], p_phy_sta_rpt->rxevm[1], p_phy_sta_rpt->rxevm[2], p_phy_sta_rpt->rxevm[3]); + dbg_print("SNR A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->rxsnr[0], p_phy_sta_rpt->rxsnr[1], p_phy_sta_rpt->rxsnr[2], p_phy_sta_rpt->rxsnr[3]); + dbg_print("CFO A: %d, B: %d, C: %d, D: %d\n", p_phy_sta_rpt->cfo_tail[0], p_phy_sta_rpt->cfo_tail[1], p_phy_sta_rpt->cfo_tail[2], p_phy_sta_rpt->cfo_tail[3]); + dbg_print("paid = %d, gid = %d, length = %d\n", (p_phy_sta_rpt->paid + (p_phy_sta_rpt->paid_msb<<8)), p_phy_sta_rpt->gid, p_phy_sta_rpt->lsig_length); + dbg_print("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", p_phy_sta_rpt->ldpc, p_phy_sta_rpt->stbc, p_phy_sta_rpt->beamformed, p_phy_sta_rpt->gnt_bt, p_phy_sta_rpt->hw_antsw_occu); + dbg_print("NBI: %d, pos: %d\n", p_phy_sta_rpt->nb_intf_flag, (p_phy_sta_rpt->intf_pos + (p_phy_sta_rpt->intf_pos_msb<<8))); + dbg_print("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", p_phy_sta_rpt->rsvd_0, p_phy_sta_rpt->rsvd_1, p_phy_sta_rpt->rsvd_2, p_phy_sta_rpt->rsvd_3, p_phy_sta_rpt->rsvd_4, p_phy_sta_rpt->rsvd_5); + */ + phydm_rx_statistic_cal(p_dm_odm, p_phy_status, p_pktinfo); + } + /* + dbg_print("phydm_get_rx_phy_status_type1 p_pktinfo->is_packet_match_bssid = %d\n", p_pktinfo->is_packet_match_bssid); + dbg_print("p_pktinfo->data_rate = 0x%x\n", p_pktinfo->data_rate); + */ +} + +void +phydm_get_rx_phy_status_type2( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info +) +{ + struct _phy_status_rpt_jaguar2_type2 *p_phy_sta_rpt = (struct _phy_status_rpt_jaguar2_type2 *)p_phy_status; + s8 rx_pwr_db = -120; + u8 i, rxsc, bw = ODM_BW20M, rx_count = 0; + + /* Update OFDM packet counter */ + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm++; + + /* Update per-path information */ + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (p_dm_odm->rx_ant_status & BIT(i)) { + s8 rx_path_pwr_db; + + /* RX path counter */ + rx_count++; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ + rx_path_pwr_db = p_phy_sta_rpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + + phydm_set_per_path_phy_info(i, rx_path_pwr_db, 0, 0, 0, p_phy_info); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (rx_count > 0) + p_phy_info->rx_count = rx_count - 1; + + /* Check RX sub-channel */ + if ((p_pktinfo->data_rate > ODM_RATE11M) && (p_pktinfo->data_rate < ODM_RATEMCS0)) + rxsc = p_phy_sta_rpt->l_rxsc; + else + rxsc = p_phy_sta_rpt->ht_rxsc; + + /*STBC or LDPC pkt*/ + p_dm_odm->phy_dbg_info.is_ldpc_pkt = p_phy_sta_rpt->ldpc; + p_dm_odm->phy_dbg_info.is_stbc_pkt = p_phy_sta_rpt->stbc; + + /* Check RX bandwidth */ + /* the BW information of sc=0 is useless, because there is no information of RF mode*/ + + if (p_dm_odm->support_ic_type & ODM_RTL8822B) { + if ((rxsc >= 1) && (rxsc <= 8)) + bw = ODM_BW20M; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = ODM_BW40M; + else if (rxsc >= 13) + bw = ODM_BW80M; + else + bw = ODM_BW20M; + } else if (p_dm_odm->support_ic_type & (ODM_RTL8197F | ODM_RTL8723D | ODM_RTL8710B)) {/* JJ ADD 20161014 */ + if (rxsc == 3) + bw = ODM_BW40M; + else if ((rxsc == 1) || (rxsc == 2)) + bw = ODM_BW20M; + else + bw = ODM_BW20M; + } + + /* Update packet information */ + phydm_set_common_phy_info(rx_pwr_db, p_phy_sta_rpt->channel, (boolean)p_phy_sta_rpt->beamformed, + false, bw, 0, rxsc, p_phy_info); +} + +void +phydm_get_rx_phy_status_type5( + u8 *p_phy_status +) +{ + /* + dbg_print("DW0: 0x%02x%02x%02x%02x\n", *(p_phy_status + 3), *(p_phy_status + 2), *(p_phy_status + 1), *(p_phy_status + 0)); + dbg_print("DW1: 0x%02x%02x%02x%02x\n", *(p_phy_status + 7), *(p_phy_status + 6), *(p_phy_status + 5), *(p_phy_status + 4)); + dbg_print("DW2: 0x%02x%02x%02x%02x\n", *(p_phy_status + 11), *(p_phy_status + 10), *(p_phy_status + 9), *(p_phy_status + 8)); + dbg_print("DW3: 0x%02x%02x%02x%02x\n", *(p_phy_status + 15), *(p_phy_status + 14), *(p_phy_status + 13), *(p_phy_status + 12)); + dbg_print("DW4: 0x%02x%02x%02x%02x\n", *(p_phy_status + 19), *(p_phy_status + 18), *(p_phy_status + 17), *(p_phy_status + 16)); + dbg_print("DW5: 0x%02x%02x%02x%02x\n", *(p_phy_status + 23), *(p_phy_status + 22), *(p_phy_status + 21), *(p_phy_status + 20)); + dbg_print("DW6: 0x%02x%02x%02x%02x\n", *(p_phy_status + 27), *(p_phy_status + 26), *(p_phy_status + 25), *(p_phy_status + 24)); + */ +} + +void +phydm_process_rssi_for_dm_new_type( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + struct _odm_per_pkt_info_ *p_pktinfo +) +{ + s32 undecorated_smoothed_pwdb, accumulate_pwdb; + u32 rssi_ave; + u8 i; + struct sta_info *p_entry; + u8 scaling_factor = 4; + + if (p_pktinfo->station_id >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + p_entry = p_dm_odm->p_odm_sta_info[p_pktinfo->station_id]; + + if (!IS_STA_VALID(p_entry)) + return; + + if ((!p_pktinfo->is_packet_match_bssid))/*data frame only*/ + return; + + if (p_pktinfo->is_packet_beacon) + p_dm_odm->phy_dbg_info.num_qry_beacon_pkt++; + + + + if (p_pktinfo->is_packet_to_self || p_pktinfo->is_packet_beacon) { + u32 RSSI_linear = 0; + + p_dm_odm->rx_rate = p_pktinfo->data_rate; + undecorated_smoothed_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + accumulate_pwdb = p_dm_odm->accumulate_pwdb[p_pktinfo->station_id]; + p_dm_odm->RSSI_A = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_A]; + p_dm_odm->RSSI_B = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_B]; + p_dm_odm->RSSI_C = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_C]; + p_dm_odm->RSSI_D = p_phy_info->rx_mimo_signal_strength[ODM_RF_PATH_D]; + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (p_phy_info->rx_mimo_signal_strength[i] != 0) + RSSI_linear += odm_convert_to_linear(p_phy_info->rx_mimo_signal_strength[i]); + } + + switch (p_phy_info->rx_count + 1) { + case 2: + RSSI_linear = (RSSI_linear >> 1); + break; + case 3: + RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ + break; + case 4: + RSSI_linear = (RSSI_linear >> 2); + break; + } + rssi_ave = odm_convert_to_db(RSSI_linear); + + if (undecorated_smoothed_pwdb <= 0) { + accumulate_pwdb = (p_phy_info->rx_pwdb_all << scaling_factor); + undecorated_smoothed_pwdb = p_phy_info->rx_pwdb_all; + } else { + accumulate_pwdb = accumulate_pwdb - (accumulate_pwdb >> scaling_factor) + rssi_ave; + undecorated_smoothed_pwdb = (accumulate_pwdb + (1 << (scaling_factor - 1))) >> scaling_factor; + } + + if (p_entry->rssi_stat.undecorated_smoothed_pwdb == -1) + phydm_ra_rssi_rpt_wk(p_dm_odm); + p_entry->rssi_stat.undecorated_smoothed_pwdb = undecorated_smoothed_pwdb; + p_dm_odm->accumulate_pwdb[p_pktinfo->station_id] = accumulate_pwdb; + } +} + +void +phydm_rx_phy_status_new_type( + struct PHY_DM_STRUCT *p_phydm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info +) +{ + u8 phy_status_type = (*p_phy_status & 0xf); + + /*dbg_print("phydm_rx_phy_status_new_type================> (page: %d)\n", phy_status_type);*/ + + /* Memory reset */ + phydm_reset_phy_info(p_phydm, p_phy_info); + + /* Phy status parsing */ + switch (phy_status_type) { + case 0: + { + phydm_get_rx_phy_status_type0(p_phydm, p_phy_status, p_pktinfo, p_phy_info); + break; + } + case 1: + { + phydm_get_rx_phy_status_type1(p_phydm, p_phy_status, p_pktinfo, p_phy_info); + break; + } + case 2: + { + phydm_get_rx_phy_status_type2(p_phydm, p_phy_status, p_pktinfo, p_phy_info); + break; + } + default: + return; + } + + /* Update signal strength to UI, and p_phy_info->rx_pwdb_all is the maximum RSSI of all path */ + p_phy_info->signal_strength = (u8)(odm_signal_scale_mapping(p_phydm, p_phy_info->rx_pwdb_all)); + + /* Calculate average RSSI and smoothed RSSI */ + phydm_process_rssi_for_dm_new_type(p_phydm, p_phy_info, p_pktinfo); + +} +/*==============================================*/ + +u32 +query_phydm_trx_capability( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0xFFFFFFFF; + + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_trx_capability_8821c(p_dm_odm); + + return value32; +} + +u32 +query_phydm_stbc_capability( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0xFFFFFFFF; + + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_stbc_capability_8821c(p_dm_odm); + + return value32; +} + +u32 +query_phydm_ldpc_capability( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0xFFFFFFFF; + + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_ldpc_capability_8821c(p_dm_odm); + + return value32; +} + +u32 +query_phydm_txbf_parameters( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0xFFFFFFFF; + + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_parameters_8821c(p_dm_odm); + + return value32; +} + +u32 +query_phydm_txbf_capability( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0xFFFFFFFF; + + if (p_dm_odm->support_ic_type == ODM_RTL8821C) + value32 = query_phydm_txbf_capability_8821c(p_dm_odm); + + return value32; +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_hwconfig.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_hwconfig.h new file mode 100644 index 000000000000..5c7e9399d0e7 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_hwconfig.h @@ -0,0 +1,558 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + +/*--------------------------Define -------------------------------------------*/ +#define CCK_RSSI_INIT_COUNT 5 + +#define RA_RSSI_STATE_INIT 0 +#define RA_RSSI_STATE_SEND 1 +#define RA_RSSI_STATE_HOLD 2 + +#define CFO_HW_RPT_2_MHZ(val) ((val<<1) + (val>>1)) +/* ((X* 3125) / 10)>>7 = (X*10)>>2 = X*2.5 = X<<1 + X>>1 */ + +#define AGC_DIFF_CONFIG_MP(ic, band) (odm_read_and_config_mp_##ic##_agc_tab_diff(p_dm_odm, array_mp_##ic##_agc_tab_diff_##band, \ + sizeof(array_mp_##ic##_agc_tab_diff_##band)/sizeof(u32))) +#define AGC_DIFF_CONFIG_TC(ic, band) (odm_read_and_config_tc_##ic##_agc_tab_diff(p_dm_odm, array_tc_##ic##_agc_tab_diff_##band, \ + sizeof(array_tc_##ic##_agc_tab_diff_##band)/sizeof(u32))) + +#define AGC_DIFF_CONFIG(ic, band) do {\ + if (p_dm_odm->is_mp_chip)\ + AGC_DIFF_CONFIG_MP(ic, band);\ + else\ + AGC_DIFF_CONFIG_TC(ic, band);\ + } while (0) + +/* ************************************************************ + * structure and define + * ************************************************************ */ + +__PACK struct _phy_rx_agc_info { +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain: 7, trsw: 1; +#else + u8 trsw: 1, gain: 7; +#endif +}; + +__PACK struct _phy_status_rpt_8192cd { + struct _phy_rx_agc_info path_agc[2]; + u8 ch_corr[2]; + u8 cck_sig_qual_ofdm_pwdb_all; + u8 cck_agc_rpt_ofdm_cfosho_a; + u8 cck_rpt_b_ofdm_cfosho_b; + u8 rsvd_1;/*ch_corr_msb;*/ + u8 noise_power_db_msb; + s8 path_cfotail[2]; + u8 pcts_mask[2]; + s8 stream_rxevm[2]; + u8 path_rxsnr[2]; + u8 noise_power_db_lsb; + u8 rsvd_2[3]; + u8 stream_csi[2]; + u8 stream_target_csi[2]; + s8 sig_evm; + u8 rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ + u8 sgi_en: 1; + u8 rxsc: 2; + u8 idle_long: 1; + u8 r_ant_train_en: 1; + u8 ant_sel_b: 1; + u8 ant_sel: 1; +#else /*_BIG_ENDIAN_ */ + u8 ant_sel: 1; + u8 ant_sel_b: 1; + u8 r_ant_train_en: 1; + u8 idle_long: 1; + u8 rxsc: 2; + u8 sgi_en: 1; + u8 antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ +#endif +}; + +struct _phy_status_rpt_8812 { + /* DWORD 0*/ + u8 gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u8 chl_num_LSB; /*channel number[7:0]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 chl_num_MSB: 2; /*channel number[9:8]*/ + u8 sub_chnl: 4; /*sub-channel location[3:0]*/ + u8 r_RFMOD: 2; /*RF mode[1:0]*/ +#else /*_BIG_ENDIAN_ */ + u8 r_RFMOD: 2; + u8 sub_chnl: 4; + u8 chl_num_MSB: 2; +#endif + + /* DWORD 1*/ + u8 pwdb_all; /*CCK signal quality / OFDM pwdb all*/ + s8 cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM path-A and path-B short CFO*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + /*this should be checked again because the definition of 8812 and 8814 is different*/ + /* u8 r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ + /* u8 cck_rx_path:4; cck rx path[3:0]*/ + u8 resvd_0: 6; + u8 bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ +#else /*_BIG_ENDIAN_*/ + u8 bt_RF_ch_MSB: 2; + u8 resvd_0: 6; +#endif + + /* DWORD 2*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ + u8 ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ + u8 bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ +#else /*_BIG_ENDIAN_ */ + u8 bt_RF_ch_LSB: 6; + u8 ant_div_sw_b: 1; + u8 ant_div_sw_a: 1; +#endif + s8 cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u8 PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u8 PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + + /* DWORD 3*/ + s8 rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s8 rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + + /* DWORD 4*/ + u8 PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ + u8 pcts_rpt_valid: 1; /*pcts_rpt_valid*/ + u8 resvd_1: 1; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u8 resvd_1: 1; + u8 pcts_rpt_valid: 1; + u8 PCTS_MSK_RPT_3: 6; +#endif + s8 rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ + + /* DWORD 5*/ + u8 csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ + u8 gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ + + /* DWORD 6*/ + s8 sigevm; /*signal field EVM*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u8 antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u8 dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u8 GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ +#else /*_BIG_ENDIAN_*/ + u8 GNT_BT_keep: 1; + u8 dpdt_ctrl_keep: 1; + u8 antidx_antd: 3; + u8 antidx_antc: 3; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_anta: 3; /*antidx_anta[2:0]*/ + u8 antidx_antb: 3; /*antidx_antb[2:0]*/ + u8 hw_antsw_occur: 2; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u8 hw_antsw_occur: 2; + u8 antidx_antb: 3; + u8 antidx_anta: 3; +#endif +}; + +void +phydm_reset_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm, + u8 station_id +); + +void +odm_init_rssi_for_dm( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +odm_phy_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + struct _odm_phy_status_info_ *p_phy_info, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo +); + +void +odm_mac_status_query( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_mac_status, + u8 mac_id, + boolean is_packet_match_bssid, + boolean is_packet_to_self, + boolean is_packet_beacon +); + +enum hal_status +odm_config_rf_with_tx_pwr_track_header_file( + struct PHY_DM_STRUCT *p_dm_odm +); + +enum hal_status +odm_config_rf_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_config_type config_type, + enum odm_rf_radio_path_e e_rf_path +); + +enum hal_status +odm_config_bb_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_bb_config_type config_type +); + +enum hal_status +odm_config_mac_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm +); + +enum hal_status +odm_config_fw_with_header_file( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_fw_config_type config_type, + u8 *p_firmware, + u32 *p_size +); + +u32 +odm_get_hw_img_version( + struct PHY_DM_STRUCT *p_dm_odm +); + +s32 +odm_signal_scale_mapping( + struct PHY_DM_STRUCT *p_dm_odm, + s32 curr_sig +); + +/*For 8822B only!! need to move to FW finally */ +/*==============================================*/ +void +phydm_rx_phy_status_new_type( + struct PHY_DM_STRUCT *p_phydm, + u8 *p_phy_status, + struct _odm_per_pkt_info_ *p_pktinfo, + struct _odm_phy_status_info_ *p_phy_info +); + +boolean +phydm_query_is_mu_api( + struct PHY_DM_STRUCT *p_phydm, + u8 ppdu_idx, + u8 *p_data_rate, + u8 *p_gid +); + +struct _phy_status_rpt_jaguar2_type0 { + /* DW0 */ + u8 page_num; + u8 pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain: 6; + u8 rsvd_0: 1; + u8 trsw: 1; +#else + u8 trsw: 1; + u8 rsvd_0: 1; + u8 gain: 6; +#endif + u8 rsvd_1; + + /* DW1 */ + u8 rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 rxsc: 4; + u8 agc_table: 4; +#else + u8 agc_table: 4; + u8 rxsc: 4; +#endif + u8 channel; + u8 band; + + /* DW2 */ + u16 length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a: 3; + u8 antidx_b: 3; + u8 rsvd_3: 2; + u8 antidx_c: 3; + u8 antidx_d: 3; + u8 rsvd_4:2; +#else + u8 rsvd_3: 2; + u8 antidx_b: 3; + u8 antidx_a: 3; + u8 rsvd_4:2; + u8 antidx_d: 3; + u8 antidx_c: 3; +#endif + + /* DW3 */ + u8 signal_quality; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 vga:5; + u8 lna_l:3; + u8 bb_power:6; + u8 rsvd_9:1; + u8 lna_h:1; +#else + u8 lna_l:3; + u8 vga:5; + u8 lna_h:1; + u8 rsvd_9:1; + u8 bb_power:6; +#endif + u8 rsvd_5; + + /* DW4 */ + u32 rsvd_6; + + /* DW5 */ + u32 rsvd_7; + + /* DW6 */ + u32 rsvd_8; +}; + +struct _phy_status_rpt_jaguar2_type1 { + /* DW0 and DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; +#endif + + /* DW2 */ + u16 lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 antidx_a: 3; + u8 antidx_b: 3; + u8 rsvd_1: 2; + u8 antidx_c: 3; + u8 antidx_d: 3; + u8 rsvd_2: 2; +#else + u8 rsvd_1: 2; + u8 antidx_b: 3; + u8 antidx_a: 3; + u8 rsvd_2: 2; + u8 antidx_d: 3; + u8 antidx_c: 3; +#endif + + /* DW3 */ + u8 paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 paid_msb: 1; + u8 gid: 6; + u8 rsvd_3: 1; +#else + u8 rsvd_3: 1; + u8 gid: 6; + u8 paid_msb: 1; +#endif + u8 intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 intf_pos_msb: 1; + u8 rsvd_4: 2; + u8 nb_intf_flag: 1; + u8 rf_mode: 2; + u8 rsvd_5: 2; +#else + u8 rsvd_5: 2; + u8 rf_mode: 2; + u8 nb_intf_flag: 1; + u8 rsvd_4: 2; + u8 intf_pos_msb: 1; +#endif + + /* DW4 */ + s8 rxevm[4]; /* s(8,1) */ + + /* DW5 */ + s8 cfo_tail[4]; /* s(8,7) */ + + /* DW6 */ + s8 rxsnr[4]; /* s(8,1) */ +}; + +struct _phy_status_rpt_jaguar2_type2 { + /* DW0 ane DW1 */ + u8 page_num; + u8 pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 l_rxsc: 4; + u8 ht_rxsc: 4; +#else + u8 ht_rxsc: 4; + u8 l_rxsc: 4; +#endif + u8 channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 band: 2; + u8 rsvd_0: 1; + u8 hw_antsw_occu: 1; + u8 gnt_bt: 1; + u8 ldpc: 1; + u8 stbc: 1; + u8 beamformed: 1; +#else + u8 beamformed: 1; + u8 stbc: 1; + u8 ldpc: 1; + u8 gnt_bt: 1; + u8 hw_antsw_occu: 1; + u8 rsvd_0: 1; + u8 band: 2; +#endif + + /* DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 shift_l_map: 6; + u8 rsvd_1: 2; +#else + u8 rsvd_1: 2; + u8 shift_l_map: 6; +#endif + u8 cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 agc_table_a: 4; + u8 agc_table_b: 4; + u8 agc_table_c: 4; + u8 agc_table_d: 4; +#else + u8 agc_table_b: 4; + u8 agc_table_a: 4; + u8 agc_table_d: 4; + u8 agc_table_c: 4; +#endif + + /* DW3 ~ DW6*/ + u8 cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 gain_a: 6; + u8 rsvd_2: 1; + u8 trsw_a: 1; + u8 gain_b: 6; + u8 rsvd_3: 1; + u8 trsw_b: 1; + u8 gain_c: 6; + u8 rsvd_4: 1; + u8 trsw_c: 1; + u8 gain_d: 6; + u8 rsvd_5: 1; + u8 trsw_d: 1; + u8 aagc_step_a: 2; + u8 aagc_step_b: 2; + u8 aagc_step_c: 2; + u8 aagc_step_d: 2; +#else + u8 trsw_a: 1; + u8 rsvd_2: 1; + u8 gain_a: 6; + u8 trsw_b: 1; + u8 rsvd_3: 1; + u8 gain_b: 6; + u8 trsw_c: 1; + u8 rsvd_4: 1; + u8 gain_c: 6; + u8 trsw_d: 1; + u8 rsvd_5: 1; + u8 gain_d: 6; + u8 aagc_step_d: 2; + u8 aagc_step_c: 2; + u8 aagc_step_b: 2; + u8 aagc_step_a: 2; +#endif + u8 ht_aagc_gain[4]; + u8 dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u8 counter: 6; + u8 rsvd_6: 2; + u8 syn_count: 5; + u8 rsvd_7:3; +#else + u8 rsvd_6: 2; + u8 counter: 6; + u8 rsvd_7:3; + u8 syn_count: 5; +#endif +}; +/*==============================================*/ + +u32 +query_phydm_trx_capability( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_stbc_capability( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_ldpc_capability( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_txbf_parameters( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_txbf_capability( + struct PHY_DM_STRUCT *p_dm_odm +); + +#endif /*#ifndef __HALHWOUTSRC_H__*/ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_interface.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_interface.c new file mode 100644 index 000000000000..c5bcabe7a1a8 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_interface.c @@ -0,0 +1,509 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* + * ODM IO Relative API. + * */ + +u8 +odm_read_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + return rtw_read8(adapter, reg_addr); +} + +u16 +odm_read_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + return rtw_read16(adapter, reg_addr); +} + +u32 +odm_read_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + return rtw_read32(adapter, reg_addr); +} + +void +odm_write_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u8 data +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_write8(adapter, reg_addr, data); +} + +void +odm_write_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u16 data +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_write16(adapter, reg_addr, data); +} + +void +odm_write_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 data +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_write32(adapter, reg_addr, data); +} + +void +odm_set_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +) +{ + phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); +} + +u32 +odm_get_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +) +{ + return phy_query_mac_reg(p_dm_odm->adapter, reg_addr, bit_mask); +} + +void +odm_set_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +) +{ + phy_set_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask, data); +} + +u32 +odm_get_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +) +{ + return phy_query_bb_reg(p_dm_odm->adapter, reg_addr, bit_mask); +} + +void +odm_set_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +) +{ + phy_set_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask, data); +} + +u32 +odm_get_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask +) +{ + return phy_query_rf_reg(p_dm_odm->adapter, e_rf_path, reg_addr, bit_mask); +} + +/* + * ODM Memory relative API. + * */ +void +odm_allocate_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void **p_ptr, + u32 length +) +{ + *p_ptr = rtw_zvmalloc(length); +} + +/* length could be ignored, used to detect memory leakage. */ +void +odm_free_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_ptr, + u32 length +) +{ + rtw_vmfree(p_ptr, length); +} + +void +odm_move_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_dest, + void *p_src, + u32 length +) +{ + _rtw_memcpy(p_dest, p_src, length); +} + +void odm_memory_set( + struct PHY_DM_STRUCT *p_dm_odm, + void *pbuf, + s8 value, + u32 length +) +{ + _rtw_memset(pbuf, value, length); +} +s32 odm_compare_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_buf1, + void *p_buf2, + u32 length +) +{ + return _rtw_memcmp(p_buf1, p_buf2, length); +} + +/* + * ODM MISC relative API. + * */ +void +odm_acquire_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_odm_acquirespinlock(adapter, type); +} +void +odm_release_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + rtw_odm_releasespinlock(adapter, type); +} + +/* + * ODM Timer relative API. + * */ +void +odm_stall_execution( + u32 us_delay +) +{ + rtw_udelay_os(us_delay); +} + +void +ODM_delay_ms(u32 ms) +{ + rtw_mdelay_os(ms); +} + +void +ODM_delay_us(u32 us) +{ + rtw_udelay_os(us); +} + +void +ODM_sleep_ms(u32 ms) +{ + rtw_msleep_os(ms); +} + +void +ODM_sleep_us(u32 us) +{ + rtw_usleep_os(us); +} + +void +odm_set_timer( + struct PHY_DM_STRUCT *p_dm_odm, + struct phydm_timer_list *p_timer, + u32 ms_delay +) +{ + _set_timer(p_timer, ms_delay); /* ms */ +} + +void +odm_initialize_timer( + struct PHY_DM_STRUCT *p_dm_odm, + struct phydm_timer_list *p_timer, + void *call_back_func, + void *p_context, + const char *sz_id +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + _init_timer(p_timer, adapter->pnetdev, call_back_func, p_dm_odm); +} + +void +odm_cancel_timer( + struct PHY_DM_STRUCT *p_dm_odm, + struct phydm_timer_list *p_timer +) +{ + _cancel_timer_ex(p_timer); +} + +u8 +phydm_trans_h2c_id( + struct PHY_DM_STRUCT *p_dm_odm, + u8 phydm_h2c_id +) +{ + u8 platform_h2c_id = phydm_h2c_id; + + switch (phydm_h2c_id) { + /* 1 [0] */ + case ODM_H2C_RSSI_REPORT: + platform_h2c_id = H2C_RSSI_SETTING; + break; + + /* 1 [3] */ + case ODM_H2C_WIFI_CALIBRATION: + break; + + /* 1 [4] */ + case ODM_H2C_IQ_CALIBRATION: + break; + /* 1 [5] */ + case ODM_H2C_RA_PARA_ADJUST: + break; + + /* 1 [6] */ + case PHYDM_H2C_DYNAMIC_TX_PATH: + break; + + /* [7]*/ + case PHYDM_H2C_FW_TRACE_EN: + platform_h2c_id = 0x49; + break; + + case PHYDM_H2C_TXBF: + break; + + case PHYDM_H2C_MU: + break; + + default: + platform_h2c_id = phydm_h2c_id; + break; + } + + return platform_h2c_id; + +} + +/*ODM FW relative API.*/ + +void +odm_fill_h2c_cmd( + struct PHY_DM_STRUCT *p_dm_odm, + u8 phydm_h2c_id, + u32 cmd_len, + u8 *p_cmd_buffer +) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + u8 platform_h2c_id; + + platform_h2c_id = phydm_trans_h2c_id(p_dm_odm, phydm_h2c_id); + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] platform_h2c_id = ((0x%x))\n", platform_h2c_id)); + + rtw_hal_fill_h2c_cmd(adapter, platform_h2c_id, cmd_len, p_cmd_buffer); +} + +u8 +phydm_c2H_content_parsing( + void *p_dm_void, + u8 c2h_cmd_id, + u8 c2h_cmd_len, + u8 *tmp_buf +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 extend_c2h_sub_id = 0; + u8 find_c2h_cmd = true; + + switch (c2h_cmd_id) { + case PHYDM_C2H_DBG: + phydm_fw_trace_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_RA_RPT: + phydm_c2h_ra_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_RA_PARA_RPT: + odm_c2h_ra_para_report_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: + if (p_dm_odm->support_ic_type & (ODM_RTL8814A)) + phydm_c2h_dtp_handler(p_dm_odm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_IQK_FINISH: + break; + + case PHYDM_C2H_DBG_CODE: + phydm_fw_trace_handler_code(p_dm_odm, tmp_buf, c2h_cmd_len); + break; + + case PHYDM_C2H_EXTEND: + extend_c2h_sub_id = tmp_buf[0]; + if (extend_c2h_sub_id == PHYDM_EXTEND_C2H_DBG_PRINT) + phydm_fw_trace_handler_8051(p_dm_odm, tmp_buf, c2h_cmd_len); + + break; + + default: + find_c2h_cmd = false; + break; + } + + return find_c2h_cmd; + +} + +u64 +odm_get_current_time( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + return (u64)rtw_get_current_time(); +} + +u64 +odm_get_progressing_time( + struct PHY_DM_STRUCT *p_dm_odm, + u64 start_time +) +{ + return rtw_get_passing_time_ms((u32)start_time); +} + +void +phydm_set_hw_reg_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RegName, + u8 *val + ) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + adapter->hal_func.set_hw_reg_handler(adapter, RegName, val); +} + +void +phydm_get_hal_def_var_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + enum _HAL_DEF_VARIABLE e_variable, + void *p_value + ) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + adapter->hal_func.get_hal_def_var_handler(adapter, e_variable, p_value); +} + +void +odm_set_tx_power_index_by_rate_section ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 Channel, + u8 RateSection + ) +{ + phy_set_tx_power_index_by_rate_section(p_dm_odm->adapter, RFPath, Channel, RateSection); +} + +u8 +odm_get_tx_power_index ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 tx_rate, + u8 band_width, + u8 Channel + ) +{ + return phy_get_tx_power_index(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel); +} + +u8 +odm_efuse_one_byte_read( + struct PHY_DM_STRUCT *p_dm_odm, + u16 addr, + u8 *data, + boolean bPseudoTest + ) +{ + return efuse_OneByteRead(p_dm_odm->adapter, addr, data, bPseudoTest); +} + +enum hal_status +odm_iq_calibrate_by_fw( + struct PHY_DM_STRUCT *p_dm_odm, + u8 clear, + u8 segment + ) +{ + enum hal_status iqk_result = HAL_STATUS_FAILURE; + return iqk_result; +} + diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_interface.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_interface.h new file mode 100644 index 000000000000..2aa9c88c89e3 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_interface.h @@ -0,0 +1,376 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + +#define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/ + +/* + * =========== Constant/Structure/Enum/... Define + * */ + +/* + * =========== Macro Define + * */ + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +/* _cat: implemented by Token-Pasting Operator. */ +/*=================================== + +#define ODM_REG_DIG_11N 0xC50 +#define ODM_REG_DIG_11AC 0xDDD + +ODM_REG(DIG,_pdm_odm) +=====================================*/ + +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + + +#define _cat(_name, _ic_type, _func) \ + (\ + ((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ + _func##_11AC(_name) \ + ) +/* + * only sample code + *#define _cat(_name, _ic_type, _func) \ + * ( \ + * ((_ic_type) & ODM_RTL8188E) ? _func##_ic(_name, _8188E) : \ + * _func##_ic(_name, _8195) \ + * ) + */ + +/* _name: name of register or bit. + * Example: "ODM_REG(R_A_AGC_CORE1, p_dm_odm)" + * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on support_ic_type. */ + #define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg) + #define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit) +enum phydm_h2c_cmd { + PHYDM_H2C_TXBF = 0x41, + ODM_H2C_RSSI_REPORT = 0x42, + ODM_H2C_IQ_CALIBRATION = 0x45, + ODM_H2C_RA_PARA_ADJUST = 0x47, + PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, + PHYDM_H2C_FW_TRACE_EN = 0x49, + ODM_H2C_WIFI_CALIBRATION = 0x6d, + PHYDM_H2C_MU = 0x4a, + PHYDM_H2C_FW_GENERAL_INIT = 0x4c, + ODM_MAX_H2CCMD +}; + +enum phydm_c2h_evt { + PHYDM_C2H_DBG = 0, + PHYDM_C2H_LB = 1, + PHYDM_C2H_XBF = 2, + PHYDM_C2H_TX_REPORT = 3, + PHYDM_C2H_INFO = 9, + PHYDM_C2H_BT_MP = 11, + PHYDM_C2H_RA_RPT = 12, + PHYDM_C2H_RA_PARA_RPT = 14, + PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, + PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ + PHYDM_C2H_DBG_CODE = 0xFE, + PHYDM_C2H_EXTEND = 0xFF, +}; + +enum phydm_extend_c2h_evt { + PHYDM_EXTEND_C2H_DBG_PRINT = 0 + +}; + +/* + * =========== Extern Variable ??? It should be forbidden. + * */ + +/* + * =========== EXtern Function Prototype + * */ + +u8 +odm_read_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +); + +u16 +odm_read_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +); + +u32 +odm_read_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr +); + +void +odm_write_1byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u8 data +); + +void +odm_write_2byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u16 data +); + +void +odm_write_4byte( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 data +); + +void +odm_set_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +); + +u32 +odm_get_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +); + +void +odm_set_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask, + u32 data +); + +u32 +odm_get_bb_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u32 reg_addr, + u32 bit_mask +); + +void +odm_set_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +); + +u32 +odm_get_rf_reg( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e e_rf_path, + u32 reg_addr, + u32 bit_mask +); + +/* + * Memory Relative Function. + * */ +void +odm_allocate_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void **p_ptr, + u32 length +); +void +odm_free_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_ptr, + u32 length +); + +void +odm_move_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_dest, + void *p_src, + u32 length +); + +s32 odm_compare_memory( + struct PHY_DM_STRUCT *p_dm_odm, + void *p_buf1, + void *p_buf2, + u32 length +); + +void odm_memory_set +(struct PHY_DM_STRUCT *p_dm_odm, + void *pbuf, + s8 value, + u32 length); + +/* + * ODM MISC-spin lock relative API. + * */ +void +odm_acquire_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +); + +void +odm_release_spin_lock( + struct PHY_DM_STRUCT *p_dm_odm, + enum rt_spinlock_type type +); + +/* + * ODM Timer relative API. + * */ +void +odm_stall_execution( + u32 us_delay +); + +void +ODM_delay_ms(u32 ms); + +void +ODM_delay_us(u32 us); + +void +ODM_sleep_ms(u32 ms); + +void +ODM_sleep_us(u32 us); + +void +odm_set_timer( + struct PHY_DM_STRUCT *p_dm_odm, + struct phydm_timer_list *p_timer, + u32 ms_delay +); + +void +odm_initialize_timer( + struct PHY_DM_STRUCT *p_dm_odm, + struct phydm_timer_list *p_timer, + void *call_back_func, + void *p_context, + const char *sz_id +); + +void +odm_cancel_timer( + struct PHY_DM_STRUCT *p_dm_odm, + struct phydm_timer_list *p_timer +); + +void +odm_release_timer( + struct PHY_DM_STRUCT *p_dm_odm, + struct phydm_timer_list *p_timer +); + +/* + * ODM FW relative API. + * */ +void +odm_fill_h2c_cmd( + struct PHY_DM_STRUCT *p_dm_odm, + u8 element_id, + u32 cmd_len, + u8 *p_cmd_buffer +); + +u8 +phydm_c2H_content_parsing( + void *p_dm_void, + u8 c2h_cmd_id, + u8 c2h_cmd_len, + u8 *tmp_buf +); + +u64 +odm_get_current_time( + struct PHY_DM_STRUCT *p_dm_odm +); +u64 +odm_get_progressing_time( + struct PHY_DM_STRUCT *p_dm_odm, + u64 start_time +); + +void +phydm_set_hw_reg_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 reg_Name, + u8 *val + ); + +void +phydm_get_hal_def_var_handler_interface ( + struct PHY_DM_STRUCT *p_dm_odm, + enum _HAL_DEF_VARIABLE e_variable, + void *p_value + ); + +void +odm_set_tx_power_index_by_rate_section ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 Channel, + u8 RateSection +); + +u8 +odm_get_tx_power_index ( + struct PHY_DM_STRUCT *p_dm_odm, + u8 RFPath, + u8 tx_rate, + u8 band_width, + u8 Channel +); + +u8 +odm_efuse_one_byte_read( + struct PHY_DM_STRUCT *p_dm_odm, + u16 addr, + u8 *data, + boolean bPseudoTest +); + +enum hal_status +odm_iq_calibrate_by_fw( + struct PHY_DM_STRUCT *p_dm_odm, + u8 clear, + u8 segment +); +#endif /* __ODM_INTERFACE_H__ */ + diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_iqk.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_iqk.h new file mode 100644 index 000000000000..baba44715d2f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_iqk.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMIQK_H__ +#define __PHYDMIQK_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOK_delay 1 +#define WBIQK_delay 10 +#define TX_IQK 0 +#define RX_IQK 1 +#define TXIQK 0 +#define RXIQK1 1 +#define RXIQK2 2 +#define kcount_limit_80m 2 +#define kcount_limit_others 4 +#define rxiqk_gs_limit 4 + +#define NUM 4 +/*---------------------------End Define Parameters-------------------------------*/ + +struct _IQK_INFORMATION { + boolean LOK_fail[NUM]; + boolean IQK_fail[2][NUM]; + u32 iqc_matrix[2][NUM]; + u8 iqk_times; + u32 rf_reg18; + u32 lna_idx; + u8 rxiqk_step; + u8 tmp1bcc; + u8 kcount; + + u32 iqk_channel[2]; + boolean IQK_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */ + u32 IQK_CFIR_real[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/ + u32 IQK_CFIR_imag[2][4][2][8]; /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/ + u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */ + u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */ + u8 RXIQK_fail_code[2][4]; /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */ + u32 LOK_IDAC[2][4]; /*channel / path*/ + u16 RXIQK_AGC[2][4]; /*channel / path*/ + u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/ + u32 tmp_GNTWL; + boolean is_BTG; + boolean isbnd; +}; + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_kfree.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_kfree.c new file mode 100644 index 000000000000..62808cf48f44 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_kfree.c @@ -0,0 +1,331 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================*/ +/*include files*/ +/*============================================================*/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/*<YuChen, 150720> Add for KFree Feature Requested by RF David.*/ +/*This is a phydm API*/ + +void +phydm_set_kfree_to_rf_8814a( + void *p_dm_void, + u8 e_rf_path, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + boolean is_odd; + + if ((data % 2) != 0) { /*odd->positive*/ + data = data - 1; + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 1); + is_odd = true; + } else { /*even->negative*/ + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(19), 0); + is_odd = false; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): RF_0x55[19]= %d\n", is_odd)); + switch (data) { + case 0: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 0; + break; + case 2: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 0); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 0; + break; + case 4: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 1; + break; + case 6: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 1); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 1; + break; + case 8: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 2; + break; + case 10: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 2); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 2; + break; + case 12: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 3; + break; + case 14: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 3); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 3; + break; + case 16: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 4; + break; + case 18: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 4); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 4; + break; + case 20: + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(14), 0); + odm_set_rf_reg(p_dm_odm, e_rf_path, REG_RF_TX_GAIN_OFFSET, BIT(17) | BIT(16) | BIT(15), 5); + p_rf_calibrate_info->kfree_offset[e_rf_path] = 5; + break; + + default: + break; + } + + if (is_odd == false) { + /*that means Kfree offset is negative, we need to record it.*/ + p_rf_calibrate_info->kfree_offset[e_rf_path] = (-1) * p_rf_calibrate_info->kfree_offset[e_rf_path]; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path])); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("phy_ConfigKFree8814A(): kfree_offset = %d\n", p_rf_calibrate_info->kfree_offset[e_rf_path])); + +} + +void +phydm_get_thermal_trim_offset_8821c( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 pg_therm = 0xff; + + odm_efuse_one_byte_read(p_dm_odm, PPG_THERMAL_OFFSET_8821C, &pg_therm, false); + + if (pg_therm != 0xff) { + pg_therm = pg_therm & 0x1f; + if ((pg_therm & BIT0) == 0) + p_power_trim_info->thermal = (-1 * (pg_therm >> 1)); + else + p_power_trim_info->thermal = (pg_therm >> 1); + + p_power_trim_info->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power trim flag:0x%02x\n", p_power_trim_info->flag)); + + if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] thermal:%d\n", p_power_trim_info->thermal)); +} + +void +phydm_get_power_trim_offset_8821c( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 pg_power = 0xff, i; + + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_2G_TXA_OFFSET_8821C, &pg_power, false); + + if (pg_power != 0xff) { + p_power_trim_info->bb_gain[0][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[1][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[2][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[3][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[4][0] = pg_power; + odm_efuse_one_byte_read(p_dm_odm, PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C, &pg_power, false); + p_power_trim_info->bb_gain[5][0] = pg_power; + p_power_trim_info->flag |= KFREE_FLAG_ON; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power trim flag:0x%02x\n", p_power_trim_info->flag)); + + if (p_power_trim_info->flag & KFREE_FLAG_ON) { + for (i = 0; i < 6; i++) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] power_trim_data->bb_gain[%d][0]=0x%X\n", i, p_power_trim_info->bb_gain[i][0])); + } +} + +void +phydm_set_kfree_to_rf_8821c( + void *p_dm_void, + u8 e_rf_path, + boolean wlg_btg, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + boolean is_odd; + u8 wlg, btg; + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(5), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(6), 1); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(6), 1); + + if (wlg_btg == true) { + wlg = data & 0xf; + btg = (data & 0xf0) >> 4; + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (wlg & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (wlg >> 1)); + + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, BIT(19), (btg & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), (btg >> 1)); + } else { + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, BIT(19), (data & BIT(0))); + odm_set_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14)), ((data & 0x1f) >> 1)); + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, + ("[kfree] 0x55[19:14]=0x%X 0x65[19:14]=0x%X\n", + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x55, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))), + odm_get_rf_reg(p_dm_odm, e_rf_path, 0x65, (BIT(19) | BIT(18) | BIT(17) | BIT(16) | BIT(15) | BIT(14))) + )); +} + +void +phydm_set_kfree_to_rf( + void *p_dm_void, + u8 e_rf_path, + u8 data +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + phydm_set_kfree_to_rf_8814a(p_dm_odm, e_rf_path, data); + + if ((p_dm_odm->support_ic_type & ODM_RTL8821C) && (*p_dm_odm->p_band_type == ODM_BAND_2_4G)) + phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, true, data); + else if (p_dm_odm->support_ic_type & ODM_RTL8821C) + phydm_set_kfree_to_rf_8821c(p_dm_odm, e_rf_path, false, data); +} + +void +phydm_get_thermal_trim_offset( + void *p_dm_void +) +{ + phydm_get_thermal_trim_offset_8821c(p_dm_void); +} + +void +phydm_get_power_trim_offset( + void *p_dm_void +) +{ + phydm_get_power_trim_offset_8821c(p_dm_void); +} + +s8 +phydm_get_thermal_offset( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + if (p_power_trim_info->flag & KFREE_FLAG_THERMAL_K_ON) + return p_power_trim_info->thermal; + else + return 0; +} + +void +phydm_config_kfree( + void *p_dm_void, + u8 channel_to_sw +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct odm_power_trim_data *p_power_trim_info = &(p_dm_odm->power_trim_data); + + u8 rfpath = 0, max_rf_path = 0; + u8 channel_idx = 0, i; + + if (p_dm_odm->support_ic_type & ODM_RTL8814A) + max_rf_path = 4; /*0~3*/ + else if (p_dm_odm->support_ic_type & (ODM_RTL8812 | ODM_RTL8192E | ODM_RTL8822B)) + max_rf_path = 2; /*0~1*/ + else if (p_dm_odm->support_ic_type & ODM_RTL8821C) + max_rf_path = 1; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("===>[kfree] phy_ConfigKFree()\n")); + + if (p_rf_calibrate_info->reg_rf_kfree_enable == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == 2, Disable\n")); + return; + } else if (p_rf_calibrate_info->reg_rf_kfree_enable == 1 || p_rf_calibrate_info->reg_rf_kfree_enable == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): reg_rf_kfree_enable == true\n")); + /*Make sure the targetval is defined*/ + if (p_power_trim_info->flag & KFREE_FLAG_ON) { + /*if kfree_table[0] == 0xff, means no Kfree*/ + if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) { + if (channel_to_sw >= 1 && channel_to_sw <= 14) + channel_idx = PHYDM_2G; + } else if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + if (channel_to_sw >= 36 && channel_to_sw <= 48) + channel_idx = PHYDM_5GLB1; + if (channel_to_sw >= 52 && channel_to_sw <= 64) + channel_idx = PHYDM_5GLB2; + if (channel_to_sw >= 100 && channel_to_sw <= 120) + channel_idx = PHYDM_5GMB1; + if (channel_to_sw >= 122 && channel_to_sw <= 144) + channel_idx = PHYDM_5GMB2; + if (channel_to_sw >= 149 && channel_to_sw <= 177) + channel_idx = PHYDM_5GHB; + } + + for (i = 0; i < (max_rf_path * BB_GAIN_NUM); i++) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] p_power_trim_info->bb_gain[%d][%d]=0x%X\n", i, max_rf_path - 1, p_power_trim_info->bb_gain[i][max_rf_path - 1])); + + for (rfpath = ODM_RF_PATH_A; rfpath < max_rf_path; rfpath++) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phydm_kfree(): channel_to_sw=%d PATH_%d: 0x%X\n", channel_to_sw, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath])); + + phydm_set_kfree_to_rf(p_dm_odm, rfpath, p_power_trim_info->bb_gain[channel_idx][rfpath]); + } + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("[kfree] phy_ConfigKFree(): targetval not defined, Don't execute KFree Process.\n")); + return; + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_MP, ODM_DBG_LOUD, ("<===[kfree] phy_ConfigKFree()\n")); +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_kfree.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_kfree.h new file mode 100644 index 000000000000..c1ba67e5add0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_kfree.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMKFREE_H__ +#define __PHYDKFREE_H__ + +#define KFREE_VERSION "1.0" + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8821C 0x1EE +#define PPG_BB_GAIN_5GL1_TXA_OFFSET_8821C 0x1EC +#define PPG_BB_GAIN_5GL2_TXA_OFFSET_8821C 0x1E8 +#define PPG_BB_GAIN_5GM1_TXA_OFFSET_8821C 0x1E4 +#define PPG_BB_GAIN_5GM2_TXA_OFFSET_8821C 0x1E0 +#define PPG_BB_GAIN_5GH1_TXA_OFFSET_8821C 0x1DC + +#define PPG_THERMAL_OFFSET_8821C 0x1EF + +struct odm_power_trim_data { + u8 flag; + s8 bb_gain[BB_GAIN_NUM][MAX_RF_PATH]; + s8 thermal; +}; + +enum phydm_kfree_channeltosw { + PHYDM_2G = 0, + PHYDM_5GLB1 = 1, + PHYDM_5GLB2 = 2, + PHYDM_5GMB1 = 3, + PHYDM_5GMB2 = 4, + PHYDM_5GHB = 5, +}; + +void +phydm_get_thermal_trim_offset( + void *p_dm_void +); + +void +phydm_get_power_trim_offset( + void *p_dm_void +); + +s8 +phydm_get_thermal_offset( + void *p_dm_void +); + +void +phydm_config_kfree( + void *p_dm_void, + u8 channel_to_sw +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_noisemonitor.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_noisemonitor.h new file mode 100644 index 000000000000..6286abf62f7a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_noisemonitor.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + *****************************************************************************/ +#ifndef __ODMNOISEMONITOR_H__ +#define __ODMNOISEMONITOR_H__ + +#define ODM_MAX_CHANNEL_NUM 38/* 14+24 */ +struct noise_level { + /* u8 value_a, value_b; */ + u8 value[MAX_RF_PATH]; + /* s8 sval_a, sval_b; */ + s8 sval[MAX_RF_PATH]; + + /* s32 noise_a=0, noise_b=0,sum_a=0, sum_b=0; */ + /* s32 noise[ODM_RF_PATH_MAX]; */ + s32 sum[MAX_RF_PATH]; + /* u8 valid_cnt_a=0, valid_cnt_b=0, */ + u8 valid[MAX_RF_PATH]; + u8 valid_cnt[MAX_RF_PATH]; + +}; + +struct _ODM_NOISE_MONITOR_ { + s8 noise[MAX_RF_PATH]; + s16 noise_all; +}; + +s16 odm_inband_noise_monitor(void *p_dm_void, u8 is_pause_dig, u8 igi_value, u32 max_time); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_pathdiv.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_pathdiv.c new file mode 100644 index 000000000000..9bc598bc839d --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_pathdiv.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +void +phydm_c2h_dtp_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +) +{ +} + +void +odm_path_diversity( + void *p_dm_void +) +{ +} + +void +odm_path_diversity_init( + void *p_dm_void +) +{ +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_pathdiv.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_pathdiv.h new file mode 100644 index 000000000000..ec5950b52bce --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_pathdiv.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPATHDIV_H__ +#define __PHYDMPATHDIV_H__ +#define PATHDIV_VERSION "3.1" /*2015.07.29 by YuChen*/ + + +void +phydm_c2h_dtp_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +); + +void +odm_path_diversity_init( + void *p_dm_void +); + +void +odm_path_diversity( + void *p_dm_void +); + +void +odm_pathdiv_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + +#endif /* #ifndef __ODMPATHDIV_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ap.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ap.h new file mode 100644 index 000000000000..26e83cb0cfa1 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ap.h @@ -0,0 +1,302 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 + +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define iqk_matrix_reg_num 8 +/* #define IQK_MATRIX_SETTINGS_NUM 1+24+21 */ +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ + +#if !defined(_OUTSRC_COEXIST) + #define OFDM_TABLE_SIZE_92D 43 + #define OFDM_TABLE_SIZE 37 + #define CCK_TABLE_SIZE 33 + #define CCK_TABLE_SIZE_88F 21 + + /* #define OFDM_TABLE_SIZE_92E 54 */ + /* #define CCK_TABLE_SIZE_92E 54 */ + extern u32 ofdm_swing_table[OFDM_TABLE_SIZE_92D]; + extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + + extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE_92D]; + extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; + extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; + extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; + extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; + +#endif + +#define ODM_OFDM_TABLE_SIZE 37 +#define ODM_CCK_TABLE_SIZE 33 +/* <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. */ +extern u8 delta_swing_table_idx_2ga_p_default[DELTA_SWINGIDX_SIZE]; +extern u8 delta_swing_table_idx_2ga_n_default[DELTA_SWINGIDX_SIZE]; + +static u8 delta_swing_table_idx_2ga_p_8188e[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u8 delta_swing_table_idx_2ga_n_8188e[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +/* extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E]; + * extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8]; + * extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; */ + +#ifdef CONFIG_WLAN_HAL_8192EE + #define OFDM_TABLE_SIZE_92E 54 + #define CCK_TABLE_SIZE_92E 54 + extern u32 ofdm_swing_table_92e[OFDM_TABLE_SIZE_92E]; + extern u8 cck_swing_table_ch1_ch13_92e[CCK_TABLE_SIZE_92E][8]; + extern u8 cck_swing_table_ch14_92e[CCK_TABLE_SIZE_92E][8]; +#endif + +#define OFDM_TABLE_SIZE_8812 43 +#define AVG_THERMAL_NUM_8812 4 + + extern unsigned int ofdm_swing_table_8812[OFDM_TABLE_SIZE_8812]; + +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; + +#define dm_check_txpowertracking odm_txpowertracking_check + +struct _IQK_MATRIX_REGS_SETTING { + boolean is_iqk_done; + s32 value[1][iqk_matrix_reg_num]; +}; + +struct odm_rf_calibration_structure { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + + /* u8 is_txpowertracking; */ + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_dpk; + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + boolean txpowertracking_in_progress; + boolean is_dpk_enable; + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset; + s8 delta_power_index; + s8 delta_power_index_last; + boolean is_tx_power_changed; + + u8 thermal_value_hp[HP_THERMAL_NUM]; + u8 thermal_value_hp_index; + struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u64 iqk_start_time; + u64 iqk_total_progressing_time; + u64 iqk_progressing_time; + u32 lok_result; + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + u32 tx_lok[2]; +}; + +void +odm_txpowertracking_check_ap( + void *p_dm_void +); + +void +odm_txpowertracking_check( + void *p_dm_void +); + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +); + +void +odm_txpowertracking_init( + void *p_dm_void +); + +void +odm_txpowertracking_check_mp( + void *p_dm_void +); + +void +odm_txpowertracking_check_ce( + void *p_dm_void +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ce.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ce.c new file mode 100644 index 000000000000..a17bdb790ad1 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ce.c @@ -0,0 +1,726 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +/* ************************************************************ + * Global var + * ************************************************************ */ + +u32 ofdm_swing_table[OFDM_TABLE_SIZE] = { + 0x7f8001fe, /* 0, +6.0dB */ + 0x788001e2, /* 1, +5.5dB */ + 0x71c001c7, /* 2, +5.0dB*/ + 0x6b8001ae, /* 3, +4.5dB*/ + 0x65400195, /* 4, +4.0dB*/ + 0x5fc0017f, /* 5, +3.5dB*/ + 0x5a400169, /* 6, +3.0dB*/ + 0x55400155, /* 7, +2.5dB*/ + 0x50800142, /* 8, +2.0dB*/ + 0x4c000130, /* 9, +1.5dB*/ + 0x47c0011f, /* 10, +1.0dB*/ + 0x43c0010f, /* 11, +0.5dB*/ + 0x40000100, /* 12, +0dB*/ + 0x3c8000f2, /* 13, -0.5dB*/ + 0x390000e4, /* 14, -1.0dB*/ + 0x35c000d7, /* 15, -1.5dB*/ + 0x32c000cb, /* 16, -2.0dB*/ + 0x300000c0, /* 17, -2.5dB*/ + 0x2d4000b5, /* 18, -3.0dB*/ + 0x2ac000ab, /* 19, -3.5dB*/ + 0x288000a2, /* 20, -4.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x24000090, /* 22, -5.0dB*/ + 0x22000088, /* 23, -5.5dB*/ + 0x20000080, /* 24, -6.0dB*/ + 0x1e400079, /* 25, -6.5dB*/ + 0x1c800072, /* 26, -7.0dB*/ + 0x1b00006c, /* 27. -7.5dB*/ + 0x19800066, /* 28, -8.0dB*/ + 0x18000060, /* 29, -8.5dB*/ + 0x16c0005b, /* 30, -9.0dB*/ + 0x15800056, /* 31, -9.5dB*/ + 0x14400051, /* 32, -10.0dB*/ + 0x1300004c, /* 33, -10.5dB*/ + 0x12000048, /* 34, -11.0dB*/ + 0x11000044, /* 35, -11.5dB*/ + 0x10000040, /* 36, -12.0dB*/ +}; + +u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB*/ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB*/ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB <== default */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB*/ +}; + +u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB*/ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB*/ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB <== default*/ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB*/ + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB*/ +}; + +u32 ofdm_swing_table_new[OFDM_TABLE_SIZE] = { + 0x0b40002d, /* 0, -15.0dB */ + 0x0c000030, /* 1, -14.5dB*/ + 0x0cc00033, /* 2, -14.0dB*/ + 0x0d800036, /* 3, -13.5dB*/ + 0x0e400039, /* 4, -13.0dB */ + 0x0f00003c, /* 5, -12.5dB*/ + 0x10000040, /* 6, -12.0dB*/ + 0x11000044, /* 7, -11.5dB*/ + 0x12000048, /* 8, -11.0dB*/ + 0x1300004c, /* 9, -10.5dB*/ + 0x14400051, /* 10, -10.0dB*/ + 0x15800056, /* 11, -9.5dB*/ + 0x16c0005b, /* 12, -9.0dB*/ + 0x18000060, /* 13, -8.5dB*/ + 0x19800066, /* 14, -8.0dB*/ + 0x1b00006c, /* 15, -7.5dB*/ + 0x1c800072, /* 16, -7.0dB*/ + 0x1e400079, /* 17, -6.5dB*/ + 0x20000080, /* 18, -6.0dB*/ + 0x22000088, /* 19, -5.5dB*/ + 0x24000090, /* 20, -5.0dB*/ + 0x26000098, /* 21, -4.5dB*/ + 0x288000a2, /* 22, -4.0dB*/ + 0x2ac000ab, /* 23, -3.5dB*/ + 0x2d4000b5, /* 24, -3.0dB*/ + 0x300000c0, /* 25, -2.5dB*/ + 0x32c000cb, /* 26, -2.0dB*/ + 0x35c000d7, /* 27, -1.5dB*/ + 0x390000e4, /* 28, -1.0dB*/ + 0x3c8000f2, /* 29, -0.5dB*/ + 0x40000100, /* 30, +0dB*/ + 0x43c0010f, /* 31, +0.5dB*/ + 0x47c0011f, /* 32, +1.0dB*/ + 0x4c000130, /* 33, +1.5dB*/ + 0x50800142, /* 34, +2.0dB*/ + 0x55400155, /* 35, +2.5dB*/ + 0x5a400169, /* 36, +3.0dB*/ + 0x5fc0017f, /* 37, +3.5dB*/ + 0x65400195, /* 38, +4.0dB*/ + 0x6b8001ae, /* 39, +4.5dB*/ + 0x71c001c7, /* 40, +5.0dB*/ + 0x788001e2, /* 41, +5.5dB*/ + 0x7f8001fe /* 42, +6.0dB*/ +}; + +u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = { + {0x44, 0x42, 0x3C, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ + {0x48, 0x46, 0x3F, 0x2A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ + {0x4D, 0x4A, 0x43, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ + {0x51, 0x4F, 0x47, 0x2F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ + {0x56, 0x53, 0x4B, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ + {0x5B, 0x58, 0x50, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ + {0x60, 0x5D, 0x54, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ + {0x66, 0x63, 0x59, 0x3B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ + {0x6C, 0x69, 0x5F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ + {0x73, 0x6F, 0x64, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ + {0x79, 0x76, 0x6A, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ + {0x81, 0x7C, 0x71, 0x4A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ + {0x88, 0x84, 0x77, 0x4F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ + {0x90, 0x8C, 0x7E, 0x54, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ + {0x99, 0x94, 0x86, 0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ + {0xA2, 0x9D, 0x8E, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ + {0xAC, 0xA6, 0x96, 0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ + {0xB6, 0xB0, 0x9F, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ + {0xC1, 0xBA, 0xA8, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ + {0xCC, 0xC5, 0xB2, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ + {0xD8, 0xD1, 0xBD, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + +u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 19, -6.5dB*/ + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /*20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 25, -3.5dB*/ + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 26, -3.0dB*/ + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 30, -1.0dB*/ + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 31, -0.5dB*/ + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} /* 32, +0dB*/ +}; + +u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, /* 0, -16.0dB*/ + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 1, -15.5dB*/ + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 2, -15.0dB*/ + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 3, -14.5dB*/ + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 4, -14.0dB*/ + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /*5, -13.5dB*/ + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 6, -13.0dB*/ + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 7, -12.5dB*/ + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 8, -12.0dB*/ + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 9, -11.5dB*/ + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 10, -11.0dB*/ + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /*11, -10.5dB*/ + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 12, -10.0dB*/ + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 13, -9.5dB*/ + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /*14, -9.0dB */ + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 15, -8.5dB*/ + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */ + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 17, -7.5dB*/ + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 18, -7.0dB */ + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 19, -6.5dB */ + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 20, -6.0dB */ + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 21, -5.5dB*/ + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 22, -5.0dB */ + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /*23, -4.5dB*/ + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 24, -4.0dB */ + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 25, -3.5dB */ + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 26, -3.0dB */ + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /*27, -2.5dB*/ + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 28, -2.0dB */ + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /*29, -1.5dB*/ + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 30, -1.0dB */ + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 31, -0.5dB */ + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} /* 32, +0dB */ +}; +u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; +/* JJ ADD 20161014 */ +u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B] = { + 0x0CD, /*0 , -20dB*/ + 0x0D9, + 0x0E6, + 0x0F3, + 0x102, + 0x111, + 0x121, + 0x132, + 0x144, + 0x158, + 0x16C, + 0x182, + 0x198, + 0x1B1, + 0x1CA, + 0x1E5, + 0x202, + 0x221, + 0x241, + 0x263, + 0x287, + 0x2AE, + 0x2D6, + 0x301, + 0x32F, + 0x35F, + 0x392, + 0x3C9, + 0x402, + 0x43F, + 0x47F, + 0x4C3, + 0x50C, + 0x558, + 0x5A9, + 0x5FF, + 0x65A, + 0x6BA, + 0x720, + 0x78C, + 0x7FF, +}; + +u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE] = { + 0x081, /* 0, -12.0dB*/ + 0x088, /* 1, -11.5dB*/ + 0x090, /* 2, -11.0dB*/ + 0x099, /* 3, -10.5dB*/ + 0x0A2, /* 4, -10.0dB*/ + 0x0AC, /* 5, -9.5dB*/ + 0x0B6, /* 6, -9.0dB*/ + 0x0C0, /*7, -8.5dB*/ + 0x0CC, /* 8, -8.0dB*/ + 0x0D8, /* 9, -7.5dB*/ + 0x0E5, /* 10, -7.0dB*/ + 0x0F2, /* 11, -6.5dB*/ + 0x101, /* 12, -6.0dB*/ + 0x110, /* 13, -5.5dB*/ + 0x120, /* 14, -5.0dB*/ + 0x131, /* 15, -4.5dB*/ + 0x143, /* 16, -4.0dB*/ + 0x156, /* 17, -3.5dB*/ + 0x16A, /* 18, -3.0dB*/ + 0x180, /* 19, -2.5dB*/ + 0x197, /* 20, -2.0dB*/ + 0x1AF, /* 21, -1.5dB*/ + 0x1C8, /* 22, -1.0dB*/ + 0x1E3, /* 23, -0.5dB*/ + 0x200, /* 24, +0 dB*/ + 0x21E, /* 25, +0.5dB*/ + 0x23E, /* 26, +1.0dB*/ + 0x261, /* 27, +1.5dB*/ + 0x285,/* 28, +2.0dB*/ + 0x2AB, /* 29, +2.5dB*/ + 0x2D3, /*30, +3.0dB*/ + 0x2FE, /* 31, +3.5dB*/ + 0x32B, /* 32, +4.0dB*/ + 0x35C, /* 33, +4.5dB*/ + 0x38E, /* 34, +5.0dB*/ + 0x3C4, /* 35, +5.5dB*/ + 0x3FE /* 36, +6.0dB */ +}; + +#ifdef AP_BUILD_WORKAROUND + +unsigned int tx_pwr_trk_ofdm_swing_tbl[tx_pwr_trk_ofdm_swing_tbl_len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; +#endif + +void +odm_txpowertracking_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + odm_txpowertracking_thermal_meter_init(p_dm_odm); +} + +u8 +get_swing_index( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 i = 0; + u32 bb_swing; + u32 swing_table_size; + u32 *p_swing_table; + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B + || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B + ) { + bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000); + + p_swing_table = ofdm_swing_table_new; + swing_table_size = OFDM_TABLE_SIZE; + } else { + { + bb_swing = 0; + p_swing_table = ofdm_swing_table; + swing_table_size = OFDM_TABLE_SIZE; + } + } + + for (i = 0; i < swing_table_size; ++i) { + u32 table_value = p_swing_table[i]; + + if (table_value >= 0x100000) + table_value >>= 22; + if (bb_swing == table_value) + break; + } + return i; +} + +u8 +get_cck_swing_index( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + u8 i = 0; + u32 bb_cck_swing; + + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || + p_dm_odm->support_ic_type == ODM_RTL8192E) { + bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0]) + break; + } + } else if (p_dm_odm->support_ic_type == ODM_RTL8703B) { + bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22); + + for (i = 0; i < CCK_TABLE_SIZE_88F; i++) { + if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0]) + break; + } + } + + return i; +} + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 default_swing_index = get_swing_index(p_dm_odm); + u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm); + u8 p = 0; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + + p_rf_calibrate_info->is_txpowertracking = _TRUE; + p_rf_calibrate_info->tx_powercount = 0; + p_rf_calibrate_info->is_txpowertracking_init = _FALSE; + + if (p_dm_odm->mp_mode == false) + p_rf_calibrate_info->txpowertrack_control = _TRUE; + else + p_rf_calibrate_info->txpowertrack_control = _FALSE; + + if (p_dm_odm->mp_mode == false) + p_rf_calibrate_info->txpowertrack_control = _TRUE; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("p_dm_odm txpowertrack_control = %d\n", p_rf_calibrate_info->txpowertrack_control)); + + /* p_dm_odm->rf_calibrate_info.txpowertrack_control = true; */ + p_rf_calibrate_info->thermal_value = p_hal_data->eeprom_thermal_meter; + p_rf_calibrate_info->thermal_value_iqk = p_hal_data->eeprom_thermal_meter; + p_rf_calibrate_info->thermal_value_lck = p_hal_data->eeprom_thermal_meter; + + if (p_rf_calibrate_info->default_bb_swing_index_flag != true) { + /*The index of "0 dB" in SwingTable.*/ + if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B || + p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index; + p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index; + } else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/ + } else if (p_dm_odm->support_ic_type == ODM_RTL8723D) { /*add by zhaohe 2015-10-27*/ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + } else if (p_dm_odm->support_ic_type == ODM_RTL8710B) { /* JJ ADD 20161014 */ + p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/ + p_rf_calibrate_info->default_cck_index = 28; /*CCK: -6dB*/ + } else { + p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= TXSCALE_TABLE_SIZE) ? 24 : default_swing_index; + p_rf_calibrate_info->default_cck_index = 24; + } + p_rf_calibrate_info->default_bb_swing_index_flag = true; + } + + p_rf_calibrate_info->bb_swing_idx_cck_base = p_rf_calibrate_info->default_cck_index; + p_rf_calibrate_info->CCK_index = p_rf_calibrate_info->default_cck_index; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) { + p_rf_calibrate_info->bb_swing_idx_ofdm_base[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->OFDM_index[p] = p_rf_calibrate_info->default_ofdm_index; + p_rf_calibrate_info->delta_power_index[p] = 0; + p_rf_calibrate_info->delta_power_index_last[p] = 0; + p_rf_calibrate_info->power_index_offset[p] = 0; + } + p_rf_calibrate_info->modify_tx_agc_value_ofdm = 0; + p_rf_calibrate_info->modify_tx_agc_value_cck = 0; + +} + +void +odm_txpowertracking_check( + void *p_dm_void +) +{ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + at the same time. In the stage2/3, we need to prive universal interface and merge all + HW dynamic mechanism. */ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + switch (p_dm_odm->support_platform) { + case ODM_WIN: + odm_txpowertracking_check_mp(p_dm_odm); + break; + + case ODM_CE: + odm_txpowertracking_check_ce(p_dm_odm); + break; + + case ODM_AP: + odm_txpowertracking_check_ap(p_dm_odm); + break; + + default: + break; + } + +} + +void +odm_txpowertracking_check_ce( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + + if (!(p_dm_odm->support_ability & ODM_RF_TX_PWR_TRACK)) + return; + + if (!p_dm_odm->rf_calibrate_info.tm_trigger) { + + if (IS_HARDWARE_TYPE_8188E(adapter) || IS_HARDWARE_TYPE_8188F(adapter) || IS_HARDWARE_TYPE_8192E(adapter) + || IS_HARDWARE_TYPE_8723B(adapter) || IS_HARDWARE_TYPE_JAGUAR(adapter) || IS_HARDWARE_TYPE_8814A(adapter) + || IS_HARDWARE_TYPE_8703B(adapter) || IS_HARDWARE_TYPE_8723D(adapter) || IS_HARDWARE_TYPE_8822B(adapter) + || IS_HARDWARE_TYPE_8821C(adapter) || (p_dm_odm->support_ic_type == ODM_RTL8710B) + )/* JJ ADD 20161014 */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT(17) | BIT(16)), 0x03); + else + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_T_METER_OLD, RFREGOFFSETMASK, 0x60); + + p_dm_odm->rf_calibrate_info.tm_trigger = 1; + return; + } else { + + odm_txpowertracking_callback_thermal_meter(adapter); + p_dm_odm->rf_calibrate_info.tm_trigger = 0; + } + +} + +void +odm_txpowertracking_check_mp( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +} + +void +odm_txpowertracking_check_ap( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ce.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ce.h new file mode 100644 index 000000000000..2e5cf987ce3f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_powertracking_ce.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 +#define TXSCALE_TABLE_SIZE 37 +#define CCK_TABLE_SIZE_8723D 41 +/* JJ ADD 20161014 */ +#define CCK_TABLE_SIZE_8710B 41 + +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define DELTA_SWINTSSI_SIZE 61 +#define BAND_NUM 4 + +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + +#define iqk_matrix_reg_num 8 +#define IQK_MATRIX_SETTINGS_NUM (14+24+21) /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ + +extern u32 ofdm_swing_table[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14[CCK_TABLE_SIZE][8]; + +extern u32 ofdm_swing_table_new[OFDM_TABLE_SIZE]; +extern u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch14_new[CCK_TABLE_SIZE][8]; +extern u8 cck_swing_table_ch1_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch1_ch13_88f[CCK_TABLE_SIZE_88F][16]; +extern u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16]; +extern u32 cck_swing_table_ch1_ch14_8723d[CCK_TABLE_SIZE_8723D]; +/* JJ ADD 20161014 */ +extern u32 cck_swing_table_ch1_ch14_8710b[CCK_TABLE_SIZE_8710B]; + +extern u32 tx_scaling_table_jaguar[TXSCALE_TABLE_SIZE]; + +#define dm_check_txpowertracking odm_txpowertracking_check + +struct _IQK_MATRIX_REGS_SETTING { + boolean is_iqk_done; + s32 value[3][iqk_matrix_reg_num]; + boolean is_bw_iqk_result_saved[3]; +}; + +struct odm_rf_calibration_structure { + /* for tx power tracking */ + + u32 rega24; /* for TempCCK */ + s32 rege94; + s32 rege9c; + s32 regeb4; + s32 regebc; + + u8 tx_powercount; + boolean is_txpowertracking_init; + boolean is_txpowertracking; + u8 txpowertrack_control; /* for mp mode, turn off txpwrtracking as default */ + u8 tm_trigger; + u8 internal_pa_5g[2]; /* pathA / pathB */ + + u8 thermal_meter[2]; /* thermal_meter, index 0 for RFIC0, and 1 for RFIC1 */ + u8 thermal_value; + u8 thermal_value_lck; + u8 thermal_value_iqk; + s8 thermal_value_delta; /* delta of thermal_value and efuse thermal */ + u8 thermal_value_dpk; + u8 thermal_value_avg[AVG_THERMAL_NUM]; + u8 thermal_value_avg_index; + u8 thermal_value_rx_gain; + u8 thermal_value_crystal; + u8 thermal_value_dpk_store; + u8 thermal_value_dpk_track; + boolean txpowertracking_in_progress; + + boolean is_reloadtxpowerindex; + u8 is_rf_pi_enable; + u32 txpowertracking_callback_cnt; /* cosa add for debug */ + + /* ------------------------- Tx power Tracking ------------------------- */ + u8 is_cck_in_ch14; + u8 CCK_index; + u8 OFDM_index[MAX_RF_PATH]; + s8 power_index_offset[MAX_RF_PATH]; + s8 delta_power_index[MAX_RF_PATH]; + s8 delta_power_index_last[MAX_RF_PATH]; + boolean is_tx_power_changed; + s8 xtal_offset; + s8 xtal_offset_last; + + u8 thermal_value_hp[HP_THERMAL_NUM]; + u8 thermal_value_hp_index; + struct _IQK_MATRIX_REGS_SETTING iqk_matrix_reg_setting[IQK_MATRIX_SETTINGS_NUM]; + u8 delta_lck; + s8 bb_swing_diff_2g, bb_swing_diff_5g; /* Unit: dB */ + u8 delta_swing_table_idx_2g_cck_a_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_a_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_b_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_c_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2g_cck_d_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gb_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gc_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_p[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2gd_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5ga_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gb_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gc_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_p[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_5gd_n[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u8 delta_swing_tssi_table_2g_cck_a[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_b[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_c[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2g_cck_d[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2ga[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gb[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gc[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_2gd[DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5ga[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gb[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gc[BAND_NUM][DELTA_SWINTSSI_SIZE]; + u8 delta_swing_tssi_table_5gd[BAND_NUM][DELTA_SWINTSSI_SIZE]; + s8 delta_swing_table_xtal_p[DELTA_SWINGIDX_SIZE]; + s8 delta_swing_table_xtal_n[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_p_8188e[DELTA_SWINGIDX_SIZE]; + u8 delta_swing_table_idx_2ga_n_8188e[DELTA_SWINGIDX_SIZE]; + + u8 bb_swing_idx_ofdm[MAX_RF_PATH]; + u8 bb_swing_idx_ofdm_current; + u8 bb_swing_idx_ofdm_base[MAX_RF_PATH]; + boolean default_bb_swing_index_flag; + boolean bb_swing_flag_ofdm; + u8 bb_swing_idx_cck; + u8 bb_swing_idx_cck_current; + u8 bb_swing_idx_cck_base; + u8 default_ofdm_index; + u8 default_cck_index; + boolean bb_swing_flag_cck; + + s8 absolute_ofdm_swing_idx[MAX_RF_PATH]; + s8 remnant_ofdm_swing_idx[MAX_RF_PATH]; + s8 absolute_cck_swing_idx[MAX_RF_PATH]; + s8 remnant_cck_swing_idx; + s8 modify_tx_agc_value; /*Remnat compensate value at tx_agc */ + boolean modify_tx_agc_flag_path_a; + boolean modify_tx_agc_flag_path_b; + boolean modify_tx_agc_flag_path_c; + boolean modify_tx_agc_flag_path_d; + boolean modify_tx_agc_flag_path_a_cck; + + s8 kfree_offset[MAX_RF_PATH]; + + /* -------------------------------------------------------------------- */ + + /* for IQK */ + u32 regc04; + u32 reg874; + u32 regc08; + u32 regb68; + u32 regb6c; + u32 reg870; + u32 reg860; + u32 reg864; + + boolean is_iqk_initialized; + boolean is_lck_in_progress; + boolean is_antenna_detected; + boolean is_need_iqk; + boolean is_iqk_in_progress; + boolean is_iqk_pa_off; + u8 delta_iqk; + u32 ADDA_backup[IQK_ADDA_REG_NUM]; + u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; + u32 IQK_BB_backup_recover[9]; + u32 IQK_BB_backup[IQK_BB_REG_NUM]; + u32 tx_iqc_8723b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u32 rx_iqc_8723b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u32 tx_iqc_8703b[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8703b[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + u32 tx_iqc_8723d[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8723d[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + /* JJ ADD 20161014 */ + u32 tx_iqc_8710b[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u32 rx_iqc_8710b[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + u8 iqk_step; + u8 kcount; + u8 retry_count[4][2]; /* [4]: path ABCD, [2] TXK, RXK */ + boolean is_mp_mode; + + /* <James> IQK time measurement */ + u64 iqk_start_time; + u64 iqk_progressing_time; + u64 iqk_total_progressing_time; + + u32 lok_result; + + /* for APK */ + u32 ap_koutput[2][2]; /* path A/B; output1_1a/output1_2a */ + u8 is_ap_kdone; + u8 is_apk_thermal_meter_ignore; + + /* DPK */ + boolean is_dpk_fail; + u8 is_dp_done; + u8 is_dp_path_aok; + u8 is_dp_path_bok; + + u32 tx_lok[2]; + u32 dpk_tx_agc; + s32 dpk_gain; + u32 dpk_thermal[4]; + s8 modify_tx_agc_value_ofdm; + s8 modify_tx_agc_value_cck; + + /*Add by Yuchen for Kfree Phydm*/ + u8 reg_rf_kfree_enable; /*for registry*/ + u8 rf_kfree_enable; /*for efuse enable check*/ + +}; + +void +odm_txpowertracking_check( + void *p_dm_void +); + +void +odm_txpowertracking_init( + void *p_dm_void +); + +void +odm_txpowertracking_check_ap( + void *p_dm_void +); + +void +odm_txpowertracking_thermal_meter_init( + void *p_dm_void +); + +void +odm_txpowertracking_init( + void *p_dm_void +); + +void +odm_txpowertracking_check_mp( + void *p_dm_void +); + +void +odm_txpowertracking_check_ce( + void *p_dm_void +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_pre_define.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_pre_define.h new file mode 100644 index 000000000000..261110ea1471 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_pre_define.h @@ -0,0 +1,587 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPREDEFINE_H__ +#define __PHYDMPREDEFINE_H__ + +/* 1 ============================================================ + * 1 Definition + * 1 ============================================================ */ + +#define PHYDM_CODE_BASE "PHYDM_V014" +#define PHYDM_RELEASE_DATE "00000000" + +/* Max path of IC */ +#define MAX_PATH_NUM_8188E 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8723B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8814A 4 +#define MAX_PATH_NUM_8822B 2 +#define MAX_PATH_NUM_8821B 2 +#define MAX_PATH_NUM_8703B 1 +#define MAX_PATH_NUM_8188F 1 +#define MAX_PATH_NUM_8723D 1 +#define MAX_PATH_NUM_8197F 2 +#define MAX_PATH_NUM_8821C 1 +/* JJ ADD 20161014 */ +#define MAX_PATH_NUM_8710B 1 + +/* Max RF path */ +#define ODM_RF_PATH_MAX 2 +#define ODM_RF_PATH_MAX_JAGUAR 4 + +/*Bit define path*/ +#define PHYDM_A BIT(0) +#define PHYDM_B BIT(1) +#define PHYDM_C BIT(2) +#define PHYDM_D BIT(3) +#define PHYDM_AB (BIT(0) | BIT(1)) +#define PHYDM_AC (BIT(0) | BIT(2)) +#define PHYDM_AD (BIT(0) | BIT(3)) +#define PHYDM_BC (BIT(1) | BIT(2)) +#define PHYDM_BD (BIT(1) | BIT(3)) +#define PHYDM_CD (BIT(2) | BIT(3)) +#define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2)) +#define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3)) +#define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3)) +#define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3)) +#define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +/* number of entry */ +#define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of asoc_entry[].*/ +#define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM + +/* -----MGN rate--------------------------------- */ + +enum ODM_MGN_RATE { + ODM_MGN_1M = 0x02, + ODM_MGN_2M = 0x04, + ODM_MGN_5_5M = 0x0B, + ODM_MGN_6M = 0x0C, + ODM_MGN_9M = 0x12, + ODM_MGN_11M = 0x16, + ODM_MGN_12M = 0x18, + ODM_MGN_18M = 0x24, + ODM_MGN_24M = 0x30, + ODM_MGN_36M = 0x48, + ODM_MGN_48M = 0x60, + ODM_MGN_54M = 0x6C, + ODM_MGN_MCS32 = 0x7F, + ODM_MGN_MCS0, + ODM_MGN_MCS1, + ODM_MGN_MCS2, + ODM_MGN_MCS3, + ODM_MGN_MCS4, + ODM_MGN_MCS5, + ODM_MGN_MCS6, + ODM_MGN_MCS7, + ODM_MGN_MCS8, + ODM_MGN_MCS9, + ODM_MGN_MCS10, + ODM_MGN_MCS11, + ODM_MGN_MCS12, + ODM_MGN_MCS13, + ODM_MGN_MCS14, + ODM_MGN_MCS15, + ODM_MGN_MCS16, + ODM_MGN_MCS17, + ODM_MGN_MCS18, + ODM_MGN_MCS19, + ODM_MGN_MCS20, + ODM_MGN_MCS21, + ODM_MGN_MCS22, + ODM_MGN_MCS23, + ODM_MGN_MCS24, + ODM_MGN_MCS25, + ODM_MGN_MCS26, + ODM_MGN_MCS27, + ODM_MGN_MCS28, + ODM_MGN_MCS29, + ODM_MGN_MCS30, + ODM_MGN_MCS31, + ODM_MGN_VHT1SS_MCS0, + ODM_MGN_VHT1SS_MCS1, + ODM_MGN_VHT1SS_MCS2, + ODM_MGN_VHT1SS_MCS3, + ODM_MGN_VHT1SS_MCS4, + ODM_MGN_VHT1SS_MCS5, + ODM_MGN_VHT1SS_MCS6, + ODM_MGN_VHT1SS_MCS7, + ODM_MGN_VHT1SS_MCS8, + ODM_MGN_VHT1SS_MCS9, + ODM_MGN_VHT2SS_MCS0, + ODM_MGN_VHT2SS_MCS1, + ODM_MGN_VHT2SS_MCS2, + ODM_MGN_VHT2SS_MCS3, + ODM_MGN_VHT2SS_MCS4, + ODM_MGN_VHT2SS_MCS5, + ODM_MGN_VHT2SS_MCS6, + ODM_MGN_VHT2SS_MCS7, + ODM_MGN_VHT2SS_MCS8, + ODM_MGN_VHT2SS_MCS9, + ODM_MGN_VHT3SS_MCS0, + ODM_MGN_VHT3SS_MCS1, + ODM_MGN_VHT3SS_MCS2, + ODM_MGN_VHT3SS_MCS3, + ODM_MGN_VHT3SS_MCS4, + ODM_MGN_VHT3SS_MCS5, + ODM_MGN_VHT3SS_MCS6, + ODM_MGN_VHT3SS_MCS7, + ODM_MGN_VHT3SS_MCS8, + ODM_MGN_VHT3SS_MCS9, + ODM_MGN_VHT4SS_MCS0, + ODM_MGN_VHT4SS_MCS1, + ODM_MGN_VHT4SS_MCS2, + ODM_MGN_VHT4SS_MCS3, + ODM_MGN_VHT4SS_MCS4, + ODM_MGN_VHT4SS_MCS5, + ODM_MGN_VHT4SS_MCS6, + ODM_MGN_VHT4SS_MCS7, + ODM_MGN_VHT4SS_MCS8, + ODM_MGN_VHT4SS_MCS9, + ODM_MGN_UNKNOWN +}; + +#define ODM_MGN_MCS0_SG 0xc0 +#define ODM_MGN_MCS1_SG 0xc1 +#define ODM_MGN_MCS2_SG 0xc2 +#define ODM_MGN_MCS3_SG 0xc3 +#define ODM_MGN_MCS4_SG 0xc4 +#define ODM_MGN_MCS5_SG 0xc5 +#define ODM_MGN_MCS6_SG 0xc6 +#define ODM_MGN_MCS7_SG 0xc7 +#define ODM_MGN_MCS8_SG 0xc8 +#define ODM_MGN_MCS9_SG 0xc9 +#define ODM_MGN_MCS10_SG 0xca +#define ODM_MGN_MCS11_SG 0xcb +#define ODM_MGN_MCS12_SG 0xcc +#define ODM_MGN_MCS13_SG 0xcd +#define ODM_MGN_MCS14_SG 0xce +#define ODM_MGN_MCS15_SG 0xcf + +/* -----DESC rate--------------------------------- */ + +#define ODM_RATEMCS15_SG 0x1c +#define ODM_RATEMCS32 0x20 + +/* CCK Rates, TxHT = 0 */ +#define ODM_RATE1M 0x00 +#define ODM_RATE2M 0x01 +#define ODM_RATE5_5M 0x02 +#define ODM_RATE11M 0x03 +/* OFDM Rates, TxHT = 0 */ +#define ODM_RATE6M 0x04 +#define ODM_RATE9M 0x05 +#define ODM_RATE12M 0x06 +#define ODM_RATE18M 0x07 +#define ODM_RATE24M 0x08 +#define ODM_RATE36M 0x09 +#define ODM_RATE48M 0x0A +#define ODM_RATE54M 0x0B +/* MCS Rates, TxHT = 1 */ +#define ODM_RATEMCS0 0x0C +#define ODM_RATEMCS1 0x0D +#define ODM_RATEMCS2 0x0E +#define ODM_RATEMCS3 0x0F +#define ODM_RATEMCS4 0x10 +#define ODM_RATEMCS5 0x11 +#define ODM_RATEMCS6 0x12 +#define ODM_RATEMCS7 0x13 +#define ODM_RATEMCS8 0x14 +#define ODM_RATEMCS9 0x15 +#define ODM_RATEMCS10 0x16 +#define ODM_RATEMCS11 0x17 +#define ODM_RATEMCS12 0x18 +#define ODM_RATEMCS13 0x19 +#define ODM_RATEMCS14 0x1A +#define ODM_RATEMCS15 0x1B +#define ODM_RATEMCS16 0x1C +#define ODM_RATEMCS17 0x1D +#define ODM_RATEMCS18 0x1E +#define ODM_RATEMCS19 0x1F +#define ODM_RATEMCS20 0x20 +#define ODM_RATEMCS21 0x21 +#define ODM_RATEMCS22 0x22 +#define ODM_RATEMCS23 0x23 +#define ODM_RATEMCS24 0x24 +#define ODM_RATEMCS25 0x25 +#define ODM_RATEMCS26 0x26 +#define ODM_RATEMCS27 0x27 +#define ODM_RATEMCS28 0x28 +#define ODM_RATEMCS29 0x29 +#define ODM_RATEMCS30 0x2A +#define ODM_RATEMCS31 0x2B +#define ODM_RATEVHTSS1MCS0 0x2C +#define ODM_RATEVHTSS1MCS1 0x2D +#define ODM_RATEVHTSS1MCS2 0x2E +#define ODM_RATEVHTSS1MCS3 0x2F +#define ODM_RATEVHTSS1MCS4 0x30 +#define ODM_RATEVHTSS1MCS5 0x31 +#define ODM_RATEVHTSS1MCS6 0x32 +#define ODM_RATEVHTSS1MCS7 0x33 +#define ODM_RATEVHTSS1MCS8 0x34 +#define ODM_RATEVHTSS1MCS9 0x35 +#define ODM_RATEVHTSS2MCS0 0x36 +#define ODM_RATEVHTSS2MCS1 0x37 +#define ODM_RATEVHTSS2MCS2 0x38 +#define ODM_RATEVHTSS2MCS3 0x39 +#define ODM_RATEVHTSS2MCS4 0x3A +#define ODM_RATEVHTSS2MCS5 0x3B +#define ODM_RATEVHTSS2MCS6 0x3C +#define ODM_RATEVHTSS2MCS7 0x3D +#define ODM_RATEVHTSS2MCS8 0x3E +#define ODM_RATEVHTSS2MCS9 0x3F +#define ODM_RATEVHTSS3MCS0 0x40 +#define ODM_RATEVHTSS3MCS1 0x41 +#define ODM_RATEVHTSS3MCS2 0x42 +#define ODM_RATEVHTSS3MCS3 0x43 +#define ODM_RATEVHTSS3MCS4 0x44 +#define ODM_RATEVHTSS3MCS5 0x45 +#define ODM_RATEVHTSS3MCS6 0x46 +#define ODM_RATEVHTSS3MCS7 0x47 +#define ODM_RATEVHTSS3MCS8 0x48 +#define ODM_RATEVHTSS3MCS9 0x49 +#define ODM_RATEVHTSS4MCS0 0x4A +#define ODM_RATEVHTSS4MCS1 0x4B +#define ODM_RATEVHTSS4MCS2 0x4C +#define ODM_RATEVHTSS4MCS3 0x4D +#define ODM_RATEVHTSS4MCS4 0x4E +#define ODM_RATEVHTSS4MCS5 0x4F +#define ODM_RATEVHTSS4MCS6 0x50 +#define ODM_RATEVHTSS4MCS7 0x51 +#define ODM_RATEVHTSS4MCS8 0x52 +#define ODM_RATEVHTSS4MCS9 0x53 + +#define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) + +/* 1 ============================================================ + * 1 enumeration + * 1 ============================================================ */ + +/* ODM_CMNINFO_INTERFACE */ +enum odm_interface_e { + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}; + +/* ODM_CMNINFO_IC_TYPE */ +enum odm_ic_type_e { + ODM_RTL8188E = BIT(0), + ODM_RTL8812 = BIT(1), + ODM_RTL8821 = BIT(2), + ODM_RTL8192E = BIT(3), + ODM_RTL8723B = BIT(4), + ODM_RTL8814A = BIT(5), + ODM_RTL8881A = BIT(6), + ODM_RTL8822B = BIT(7), + ODM_RTL8703B = BIT(8), + ODM_RTL8195A = BIT(9), + ODM_RTL8188F = BIT(10), + ODM_RTL8723D = BIT(11), + ODM_RTL8197F = BIT(12), + ODM_RTL8821C = BIT(13), + ODM_RTL8814B = BIT(14), + ODM_RTL8198F = BIT(15), + /* JJ ADD 20161014 */ + ODM_RTL8710B = BIT(16), +}; + +/* JJ ADD 20161014 */ +#define ODM_IC_1SS (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | ODM_RTL8195A | ODM_RTL8710B) +#define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B) +#define ODM_IC_3SS (ODM_RTL8814A) +#define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F) + +/* JJ ADD 20161014 */ +#define ODM_IC_11N_SERIES (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) +#define ODM_IC_11AC_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8821C) +#define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A) +#define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) +#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B) +#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C) +#define ODM_IC_PHY_STATUE_NEW_TYPE (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | ODM_RTL8710B) + +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) + +#define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C) + +/* JJ ADD 20161014 */ + +/* JJ ADD 20161014 */ + +/* ODM_CMNINFO_CUT_VER */ +enum odm_cut_version_e { + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + + ODM_CUT_I = 8, + ODM_CUT_J = 9, + ODM_CUT_K = 10, + ODM_CUT_TEST = 15, +}; + +/* ODM_CMNINFO_FAB_VER */ +enum odm_fab_e { + ODM_TSMC = 0, + ODM_UMC = 1, +}; + +/* ODM_CMNINFO_RF_TYPE + * + * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5)) + * */ +enum odm_rf_path_e { + ODM_RF_A = BIT(0), + ODM_RF_B = BIT(1), + ODM_RF_C = BIT(2), + ODM_RF_D = BIT(3), +}; + +enum odm_rf_tx_num_e { + ODM_1T = 1, + ODM_2T = 2, + ODM_3T = 3, + ODM_4T = 4, +}; + +enum odm_rf_type_e { + ODM_1T1R, + ODM_1T2R, + ODM_2T2R, + ODM_2T2R_GREEN, + ODM_2T3R, + ODM_2T4R, + ODM_3T3R, + ODM_3T4R, + ODM_4T4R, + ODM_XTXR +}; + +enum odm_mac_phy_mode_e { + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}; + +enum odm_bt_coexist_e { + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}; + +/* ODM_CMNINFO_OP_MODE */ +enum odm_operation_mode_e { + ODM_NO_LINK = BIT(0), + ODM_LINK = BIT(1), + ODM_SCAN = BIT(2), + ODM_POWERSAVE = BIT(3), + ODM_AP_MODE = BIT(4), + ODM_CLIENT_MODE = BIT(5), + ODM_AD_HOC = BIT(6), + ODM_WIFI_DIRECT = BIT(7), + ODM_WIFI_DISPLAY = BIT(8), +}; + +/* ODM_CMNINFO_WM_MODE */ +enum odm_wireless_mode_e { + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT(0), + ODM_WM_G = BIT(1), + ODM_WM_A = BIT(2), + ODM_WM_N24G = BIT(3), + ODM_WM_N5G = BIT(4), + ODM_WM_AUTO = BIT(5), + ODM_WM_AC = BIT(6), +}; + +/* ODM_CMNINFO_BAND */ +enum odm_band_type_e { + ODM_BAND_2_4G = 0, + ODM_BAND_5G, + ODM_BAND_ON_BOTH, + ODM_BANDMAX +}; + +/* ODM_CMNINFO_SEC_CHNL_OFFSET */ +enum phydm_sec_chnl_offset_e { + + PHYDM_DONT_CARE = 0, + PHYDM_BELOW = 1, + PHYDM_ABOVE = 2 +}; + +/* ODM_CMNINFO_SEC_MODE */ +enum odm_security_e { + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ + ODM_SEC_SMS4 = 7, +}; + +/* ODM_CMNINFO_BW */ +enum odm_bw_e { + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW5M = 4, + ODM_BW10M = 5, + ODM_BW_MAX = 6 +}; + +/* ODM_CMNINFO_CHNL */ + +/* ODM_CMNINFO_BOARD_TYPE */ +enum odm_board_type_e { + ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ + ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */ + ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ + ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ + ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ + ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ + ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ + ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ + ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ +}; + +enum odm_package_type_e { + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), +}; + +enum odm_type_gpa_e { + TYPE_GPA0 = 0x0000, + TYPE_GPA1 = 0x0055, + TYPE_GPA2 = 0x00AA, + TYPE_GPA3 = 0x00FF, + TYPE_GPA4 = 0x5500, + TYPE_GPA5 = 0x5555, + TYPE_GPA6 = 0x55AA, + TYPE_GPA7 = 0x55FF, + TYPE_GPA8 = 0xAA00, + TYPE_GPA9 = 0xAA55, + TYPE_GPA10 = 0xAAAA, + TYPE_GPA11 = 0xAAFF, + TYPE_GPA12 = 0xFF00, + TYPE_GPA13 = 0xFF55, + TYPE_GPA14 = 0xFFAA, + TYPE_GPA15 = 0xFFFF, +}; + +enum odm_type_apa_e { + TYPE_APA0 = 0x0000, + TYPE_APA1 = 0x0055, + TYPE_APA2 = 0x00AA, + TYPE_APA3 = 0x00FF, + TYPE_APA4 = 0x5500, + TYPE_APA5 = 0x5555, + TYPE_APA6 = 0x55AA, + TYPE_APA7 = 0x55FF, + TYPE_APA8 = 0xAA00, + TYPE_APA9 = 0xAA55, + TYPE_APA10 = 0xAAAA, + TYPE_APA11 = 0xAAFF, + TYPE_APA12 = 0xFF00, + TYPE_APA13 = 0xFF55, + TYPE_APA14 = 0xFFAA, + TYPE_APA15 = 0xFFFF, +}; + +enum odm_type_glna_e { + TYPE_GLNA0 = 0x0000, + TYPE_GLNA1 = 0x0055, + TYPE_GLNA2 = 0x00AA, + TYPE_GLNA3 = 0x00FF, + TYPE_GLNA4 = 0x5500, + TYPE_GLNA5 = 0x5555, + TYPE_GLNA6 = 0x55AA, + TYPE_GLNA7 = 0x55FF, + TYPE_GLNA8 = 0xAA00, + TYPE_GLNA9 = 0xAA55, + TYPE_GLNA10 = 0xAAAA, + TYPE_GLNA11 = 0xAAFF, + TYPE_GLNA12 = 0xFF00, + TYPE_GLNA13 = 0xFF55, + TYPE_GLNA14 = 0xFFAA, + TYPE_GLNA15 = 0xFFFF, +}; + +enum odm_type_alna_e { + TYPE_ALNA0 = 0x0000, + TYPE_ALNA1 = 0x0055, + TYPE_ALNA2 = 0x00AA, + TYPE_ALNA3 = 0x00FF, + TYPE_ALNA4 = 0x5500, + TYPE_ALNA5 = 0x5555, + TYPE_ALNA6 = 0x55AA, + TYPE_ALNA7 = 0x55FF, + TYPE_ALNA8 = 0xAA00, + TYPE_ALNA9 = 0xAA55, + TYPE_ALNA10 = 0xAAAA, + TYPE_ALNA11 = 0xAAFF, + TYPE_ALNA12 = 0xFF00, + TYPE_ALNA13 = 0xFF55, + TYPE_ALNA14 = 0xFFAA, + TYPE_ALNA15 = 0xFFFF, +}; + +enum odm_rf_radio_path_e { + ODM_RF_PATH_A = 0, /* Radio path A */ + ODM_RF_PATH_B = 1, /* Radio path B */ + ODM_RF_PATH_C = 2, /* Radio path C */ + ODM_RF_PATH_D = 3, /* Radio path D */ + ODM_RF_PATH_AB, + ODM_RF_PATH_AC, + ODM_RF_PATH_AD, + ODM_RF_PATH_BC, + ODM_RF_PATH_BD, + ODM_RF_PATH_CD, + ODM_RF_PATH_ABC, + ODM_RF_PATH_ACD, + ODM_RF_PATH_BCD, + ODM_RF_PATH_ABCD, + /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */ +}; + +enum odm_parameter_init_e { + ODM_PRE_SETTING = 0, + ODM_POST_SETTING = 1, + ODM_INIT_FW_SETTING +}; + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_precomp.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_precomp.h new file mode 100644 index 000000000000..bb4a42620e29 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_precomp.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "phydm_types.h" + +#define TEST_FALG___ 1 + +/* 2 Config Flags and Structs - defined by each ODM type */ + +#define __PACK +#define __WLAN_ATTRIB_PACK__ + +/* 2 OutSrc Header Files */ + +#include "phydm.h" +#include "phydm_hwconfig.h" +#include "phydm_debug.h" +#include "phydm_regdefine11ac.h" +#include "phydm_regdefine11n.h" +#include "phydm_interface.h" +#include "phydm_reg.h" + +#include "phydm_adc_sampling.h" + +void +phy_set_tx_power_limit( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit +); + +#include "rtl8821c/phydm_hal_api8821c.h" +#include "rtl8821c/halhwimg8821c_mac.h" +#include "rtl8821c/halhwimg8821c_rf.h" +#include "rtl8821c/halhwimg8821c_bb.h" +#include "rtl8821c/halhwimg8821c_fw.h" +#include "rtl8821c/phydm_regconfig8821c.h" +#include "rtl8821c/halphyrf_8821c.h" +#include "rtl8821c/version_rtl8821c.h" +#include "rtl8821c_hal.h" + +#endif /* __ODM_PRECOMP_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_psd.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_psd.c new file mode 100644 index 000000000000..da3d3c9a91be --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_psd.c @@ -0,0 +1,447 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +u32 +phydm_get_psd_data( + void *p_dm_void, + u32 psd_tone_idx, + u32 igi + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u32 psd_report = 0; + + odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, 0x3ff, psd_tone_idx); + + odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 1); /*PSD trigger start*/ + ODM_delay_us(10); + odm_set_bb_reg(p_dm_odm, p_dm_psd_table->psd_reg, BIT(22), 0); /*PSD trigger stop*/ + + psd_report = odm_get_bb_reg(p_dm_odm, p_dm_psd_table->psd_report_reg, 0xffff); + psd_report = odm_convert_to_db(psd_report) + igi; + + return psd_report; +} + +u8 +phydm_psd_stop_trx( + void *p_dm_void + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u32 i; + u8 trx_idle_success = FALSE; + u32 dbg_port_value = 0; + + /*[Stop TRX]---------------------------------------------------------------------*/ + if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_3, 0x0) == FALSE) /*set debug port to 0x0*/ + return STOP_TRX_FAIL; + + for (i = 0; i<10000; i++) { + dbg_port_value = phydm_get_bb_dbg_port_value(p_dm_odm); + if ((dbg_port_value & (BIT(17) | BIT(3))) == 0) /* PHYTXON && CCA_all */ { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD wait for ((%d)) times\n", i)); + + trx_idle_success = TRUE; + break; + } + } + + if (trx_idle_success) { + + odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0xff); /*pause all TX queue*/ + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0); /*disable CCK block*/ + odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 1); /*disable OFDM RX CCA*/ + } else { + /*TBD*/ + odm_set_bb_reg(p_dm_odm, 0x800, BIT(24), 0); /* disable whole CCK block */ + odm_set_bb_reg(p_dm_odm, 0xC14, MASKDWORD, 0x0); /* [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] */ + } + + } else { + return STOP_TRX_FAIL; + } + + phydm_release_bb_dbg_port(p_dm_odm); + + return STOP_TRX_SUCCESS; + +} + +u8 psd_result_cali_tone_8821[7]= {21, 28, 33, 93, 98, 105, 127}; +u8 psd_result_cali_val_8821[7] = {67,69,71,72,71,69,67}; + +void +phydm_psd( + void *p_dm_void, + u32 igi, + u16 start_point, + u16 stop_point + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u32 i = 0, mod_tone_idx; + u32 t = 0; + u16 fft_max_half_bw; + u32 psd_igi_a_reg; + u32 psd_igi_b_reg; + u16 psd_fc_channel = p_dm_psd_table->psd_fc_channel; + u8 ag_rf_mode_reg = 0; + u8 rf_reg18_9_8 = 0; + u32 psd_result_tmp = 0; + u8 psd_result = 0; + u8 psd_result_cali_tone[7] = {0}; + u8 psd_result_cali_val[7] = {0}; + u8 noise_table_idx = 0; + u8 psd_result_cali_tmp = 0; + + if (p_dm_odm->support_ic_type == ODM_RTL8821) { + odm_move_memory(p_dm_odm, psd_result_cali_tone, psd_result_cali_tone_8821, 7); + odm_move_memory(p_dm_odm, psd_result_cali_val, psd_result_cali_val_8821, 7); + } + + p_dm_psd_table->psd_in_progress = 1; + + /*[Stop DIG]*/ + p_dm_odm->support_ability &= ~(ODM_BB_DIG); + p_dm_odm->support_ability &= ~(ODM_BB_FA_CNT); + + + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD Start =>\n")); + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xe50; + } else { + psd_igi_a_reg = 0xc50; + psd_igi_b_reg = 0xc58; + } + + /*[back up IGI]*/ + p_dm_psd_table->initial_gain_backup = odm_get_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff); + odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ + odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, 0x6e); /*IGI target at 0dBm & make it can't CCA*/ + ODM_delay_us(10); + + if (phydm_psd_stop_trx(p_dm_odm) == STOP_TRX_FAIL) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("STOP_TRX_FAIL\n")); + return; + } + + /*[Set IGI]*/ + odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, igi); + odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, igi); + + /*[Backup RF Reg]*/ + p_dm_psd_table->rf_0x18_bkp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + + if (psd_fc_channel > 14) { + + rf_reg18_9_8 = 1; + + if (36 <= psd_fc_channel && psd_fc_channel <= 64) + ag_rf_mode_reg = 0x1; + else if (100 <= psd_fc_channel && psd_fc_channel <= 140) + ag_rf_mode_reg = 0x3; + else if (140 < psd_fc_channel) + ag_rf_mode_reg = 0x5; + } + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel); /* Set RF fc*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xc00, p_dm_psd_table->psd_bw_rf_reg); /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg); /* Set RF ag fc mode*/ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("0xc50=((0x%x))\n", odm_get_bb_reg(p_dm_odm, 0xc50, MASKDWORD))); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x0=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK)));*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("RF0x18=((0x%x))\n", odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK))); + + /*[Stop 3-wires]*/ + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */ + odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x4);/* hardware 3-wire off */ + } else { + odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0xf); /* 3 wire Disable 88c[23:20]=0xf */ + } + ODM_delay_us(10); + + if (stop_point > (p_dm_psd_table->fft_smp_point-1)) + stop_point = (p_dm_psd_table->fft_smp_point-1); + + if (start_point > (p_dm_psd_table->fft_smp_point-1)) + start_point = (p_dm_psd_table->fft_smp_point-1); + + if (start_point > stop_point) + stop_point = start_point; + + + for (i = start_point; i <= stop_point; i++ ) { + + fft_max_half_bw = (p_dm_psd_table->fft_smp_point)>>1; + + if (i < fft_max_half_bw) { + mod_tone_idx = i + fft_max_half_bw; + } else { + mod_tone_idx = i - fft_max_half_bw; + } + + psd_result_tmp = 0; + for (t = 0; t < p_dm_psd_table->sw_avg_time; t++) { + psd_result_tmp += phydm_get_psd_data(p_dm_odm, mod_tone_idx, igi); + /**/ + } + psd_result = (u8)((psd_result_tmp/p_dm_psd_table->sw_avg_time)) - p_dm_psd_table->psd_pwr_common_offset; + + if( p_dm_psd_table->fft_smp_point == 128) { + + if (p_dm_psd_table->noise_k_en) { + if (i > psd_result_cali_tone[noise_table_idx]) { + noise_table_idx ++; + } + + if (noise_table_idx > 6) + noise_table_idx = 6; + + if (psd_result >= psd_result_cali_val[noise_table_idx]) + psd_result = psd_result - psd_result_cali_val[noise_table_idx]; + else + psd_result = 0; + } + + p_dm_psd_table->psd_result[i] = psd_result; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("[%d] N_cali = %d, PSD = %d\n", mod_tone_idx, psd_result_cali_val[noise_table_idx], psd_result)); + + } + + /*[Start 3-wires]*/ + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + odm_set_bb_reg(p_dm_odm, 0xc00, 0xf, 0x7);/* hardware 3-wire on */ + odm_set_bb_reg(p_dm_odm, 0xe00, 0xf, 0x7);/* hardware 3-wire on */ + } else { + odm_set_bb_reg(p_dm_odm, 0x88c, 0xf00000, 0x0); /* 3 wire enable 88c[23:20]=0x0 */ + } + ODM_delay_us(10); + + /*[Revert Reg]*/ + odm_set_bb_reg(p_dm_odm, 0x520, 0xff0000, 0x0); /*start all TX queue*/ + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 1); /*enable CCK block*/ + odm_set_bb_reg(p_dm_odm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/ + + odm_set_bb_reg(p_dm_odm, psd_igi_a_reg, 0xff, p_dm_psd_table->initial_gain_backup); + odm_set_bb_reg(p_dm_odm, psd_igi_b_reg, 0xff, p_dm_psd_table->initial_gain_backup); + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, p_dm_psd_table->rf_0x18_bkp); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD finished\n\n")); + + p_dm_odm->support_ability |= ODM_BB_DIG; + p_dm_odm->support_ability |= ODM_BB_FA_CNT; + p_dm_psd_table->psd_in_progress = 0; + + +} + +void +phydm_psd_para_setting( + void *p_dm_void, + u8 sw_avg_time, + u8 hw_avg_time, + u8 i_q_setting, + u16 fft_smp_point, + u8 ant_sel, + u8 psd_input, + u8 channel, + u8 noise_k_en + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u32 avg_temp; + u8 fft_smp_point_idx = 0; + + p_dm_psd_table->fft_smp_point = fft_smp_point; + + if (sw_avg_time == 0) + sw_avg_time = 1; + + p_dm_psd_table->sw_avg_time = sw_avg_time; + p_dm_psd_table->psd_fc_channel = channel; + p_dm_psd_table->noise_k_en = noise_k_en; + + if (fft_smp_point == 128) + fft_smp_point_idx = 0; + else if (fft_smp_point == 256) + fft_smp_point_idx = 1; + else if (fft_smp_point == 512) + fft_smp_point_idx = 2; + else if (fft_smp_point == 1024) + fft_smp_point_idx = 3; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + odm_set_bb_reg(p_dm_odm, 0x910, BIT(11) | BIT(10), i_q_setting); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(13) | BIT(12), hw_avg_time); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(17) | BIT(16), ant_sel); + odm_set_bb_reg(p_dm_odm, 0x910, BIT(23), psd_input); + + } else { + + } + + /*bw = (*p_dm_odm->p_band_width); //ODM_BW20M */ + /*channel = *(p_dm_odm->p_channel);*/ + + + + +} + +void +phydm_psd_init( + void *p_dm_void + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_API, ODM_DBG_LOUD, ("PSD para init\n")); + + p_dm_psd_table->psd_in_progress = FALSE; + + if (p_dm_odm->support_ic_type & ODM_IC_11AC_SERIES) { + + p_dm_psd_table->psd_reg = 0x910; + p_dm_psd_table->psd_report_reg = 0xF44; + + if (ODM_IC_11AC_2_SERIES) + p_dm_psd_table->psd_bw_rf_reg = 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + else + p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + + } else { + + p_dm_psd_table->psd_reg = 0x808; + p_dm_psd_table->psd_report_reg = 0x8B4; + p_dm_psd_table->psd_bw_rf_reg = 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */ + } + + if (p_dm_odm->support_ic_type == ODM_RTL8812) + p_dm_psd_table->psd_pwr_common_offset = 0; + else if (p_dm_odm->support_ic_type == ODM_RTL8821) + p_dm_psd_table->psd_pwr_common_offset = 0; + else + p_dm_psd_table->psd_pwr_common_offset = 0; + + phydm_psd_para_setting(p_dm_odm, 1, 2, 3, 128, 0, 0, 7, 0); + /*phydm_psd(p_dm_odm, 0x3c, 0, 127);*/ /* target at -50dBm */ + + +} + +void +phydm_psd_debug( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + char help[] = "-h"; + u32 var1[10] = {0}; + u32 used = *_used; + u32 out_len = *_out_len; + u8 i; + + if ((strcmp(input[1], help) == 0)) { + PHYDM_SNPRINTF((output + used, out_len - used, "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n")); + PHYDM_SNPRINTF((output + used, out_len - used, "{1} {IGI(hex)} {start_point} {stop_point}\n")); + + } else { + + + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + + if (var1[0] == 0) { + + for (i = 1; i < 10; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + } + + PHYDM_SNPRINTF((output + used, out_len - used, "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n", + var1[1], var1[2], var1[3], var1[4], var1[5], var1[6], (u8)var1[7], (u8)var1[8])); + phydm_psd_para_setting(p_dm_odm, (u8)var1[1], (u8)var1[2], (u8)var1[3], (u16)var1[4], (u8)var1[5], (u8)var1[6], (u8)var1[7], (u8)var1[8]); + + } else if (var1[0] == 1) { + + PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]); + PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]); + PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]); + PHYDM_SNPRINTF((output + used, out_len - used, "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n", var1[1], var1[2], var1[3])); + p_dm_odm->debug_components |= ODM_COMP_API; + phydm_psd(p_dm_odm, var1[1], (u16)var1[2], (u16)var1[3]); + p_dm_odm->debug_components &= (~ODM_COMP_API); + } + + } + + + +} + +u8 +phydm_get_psd_result_table( + void *p_dm_void, + int index + ) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _PHYDM_PSD_ *p_dm_psd_table = &(p_dm_odm->dm_psd_table); + u8 temp_result = 0; + + if(index<128) + temp_result = p_dm_psd_table->psd_result[index]; + + return temp_result; + +} + + diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_psd.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_psd.h new file mode 100644 index 000000000000..37bc240f715a --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_psd.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPSD_H__ +#define __PHYDMPSD_H__ + +/*#define PSD_VERSION "1.0"*/ /*2016.09.22 Dino*/ +#define PSD_VERSION "1.1" /*2016.10.07 Dino, Add Option for PSD Tone index Selection */ + + + +#define STOP_TRX_SUCCESS 1 +#define STOP_TRX_FAIL 0 + + +struct _PHYDM_PSD_ { + + u8 psd_in_progress; + u32 psd_reg; + u32 psd_report_reg; + u8 psd_pwr_common_offset; + u16 sw_avg_time; + u16 fft_smp_point; + u32 initial_gain_backup; + u32 rf_0x18_bkp; + u16 psd_fc_channel; + u32 psd_bw_rf_reg; + u8 psd_result[128]; + u8 noise_k_en; +}; + +u32 +phydm_get_psd_data( + void *p_dm_void, + u32 psd_tone_idx, + u32 igi +); + +void +phydm_psd_debug( + void *p_dm_void, + char input[][16], + u32 *_used, + char *output, + u32 *_out_len, + u32 input_num +); + +void +phydm_psd( + void *p_dm_void, + u32 igi, + u16 start_point, + u16 stop_point +); + +void +phydm_psd_para_setting( + void *p_dm_void, + u8 sw_avg_time, + u8 hw_avg_time, + u8 i_q_setting, + u16 fft_smp_point, + u8 ant_sel, + u8 psd_input, + u8 channel, + u8 noise_k_en +); + +void +phydm_psd_init( + void *p_dm_void +); + +u8 +phydm_get_psd_result_table( + void *p_dm_void, + int index +); + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_rainfo.c b/drivers/staging/rtl8821ce/hal/phydm/phydm_rainfo.c new file mode 100644 index 000000000000..101bd8d2f671 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_rainfo.c @@ -0,0 +1,1641 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/* ************************************************************ + * include files + * ************************************************************ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +void +phydm_h2C_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 h2c_parameter[H2C_MAX_LENGTH] = {0}; + u8 phydm_h2c_id = (u8)dm_value[0]; + u8 i; + u32 used = *_used; + u32 out_len = *_out_len; + + PHYDM_SNPRINTF((output + used, out_len - used, "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id)); + for (i = 0; i < H2C_MAX_LENGTH; i++) { + + h2c_parameter[i] = (u8)dm_value[i + 1]; + PHYDM_SNPRINTF((output + used, out_len - used, "H2C: Byte[%d] = ((0x%x))\n", i, h2c_parameter[i])); + } + + odm_fill_h2c_cmd(p_dm_odm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter); + +} + + +void +phydm_RA_debug_PCR( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u32 used = *_used; + u32 out_len = *_out_len; + + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "[Get] PCR RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); + /**/ + } else if (dm_value[0] == 0) { + p_ra_table->RA_offset_direction = 0; + p_ra_table->RA_threshold_offset = (u8)dm_value[1]; + PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( -%d ))\n", p_ra_table->RA_threshold_offset)); + } else if (dm_value[0] == 1) { + p_ra_table->RA_offset_direction = 1; + p_ra_table->RA_threshold_offset = (u8)dm_value[1]; + PHYDM_SNPRINTF((output + used, out_len - used, "[Set] PCR RA_threshold_offset = (( +%d ))\n", p_ra_table->RA_threshold_offset)); + } else { + PHYDM_SNPRINTF((output + used, out_len - used, "[Set] Error\n")); + /**/ + } + +} + + +void +odm_c2h_ra_para_report_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + + u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/ + u8 rate_type_start = cmd_buf[1]; + u8 rate_type_length = cmd_len - 2; + u8 i; + + ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] cmd_buf[0]= (( %d ))\n", cmd_buf[0])); + + if (para_idx == RADBG_DEBUG_MONITOR1) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { + + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "rate =", cmd_buf[2] & 0x7f)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI =", (cmd_buf[2] & 0x80) >> 7)); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW =", cmd_buf[3])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "BW_max =", cmd_buf[4])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate0 =", cmd_buf[5])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "multi_rate1 =", cmd_buf[6])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[7])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[8])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "SGI_support =", cmd_buf[9])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "try_ness =", cmd_buf[10])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "pre_rate =", cmd_buf[11])); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "RSSI =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x\n", "BW =", cmd_buf[2])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "DISRA =", cmd_buf[3])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "VHT_EN =", cmd_buf[4])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Hightest rate =", cmd_buf[5])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Lowest rate =", cmd_buf[6])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "SGI_support =", cmd_buf[7])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Rate_ID =", cmd_buf[8]));; + } + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR2) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (p_dm_odm->support_ic_type & PHYDM_IC_3081_SERIES) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate_id =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest_rate =", cmd_buf[2])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "lowest_rate =", cmd_buf[3])); + + for (i = 4; i <= 11; i++) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x\n", cmd_buf[i])); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x\n", "RA Mask:", + cmd_buf[8], cmd_buf[7], cmd_buf[6], cmd_buf[5], cmd_buf[4], cmd_buf[3], cmd_buf[2], cmd_buf[1])); + } + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR3) { + + for (i = 0; i < (cmd_len - 1); i++) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d\n", i, cmd_buf[1 + i])); + } else if (para_idx == RADBG_DEBUG_MONITOR4) + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d}\n", "RA version =", cmd_buf[1], cmd_buf[2])); + else if (para_idx == RADBG_DEBUG_MONITOR5) { + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "Current rate =", cmd_buf[1])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "Retry ratio =", cmd_buf[2])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d\n", "rate down ratio =", cmd_buf[3])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x\n", "highest rate =", cmd_buf[4])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {0x%x 0x%x}\n", "Muti-try =", cmd_buf[5], cmd_buf[6])); + ODM_RT_TRACE(p_dm_odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x%x%x%x%x\n", "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9], cmd_buf[8], cmd_buf[7])); + } +} + +void +phydm_ra_dynamic_retry_count( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct sta_info *p_entry; + u8 i, retry_offset; + u32 ma_rx_tp; + + if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_ARFR)) + return; + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("p_dm_odm->pre_b_noisy = %d\n", p_dm_odm->pre_b_noisy ));*/ + if (p_dm_odm->pre_b_noisy != p_dm_odm->noisy_decision) { + + if (p_dm_odm->noisy_decision) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); + odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x0); + odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x04030201); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); + odm_set_mac_reg(p_dm_odm, 0x430, MASKDWORD, 0x01000000); + odm_set_mac_reg(p_dm_odm, 0x434, MASKDWORD, 0x06050402); + } + p_dm_odm->pre_b_noisy = p_dm_odm->noisy_decision; + } +} + + +void +phydm_ra_dynamic_retry_limit( + void *p_dm_void +) +{ +} + + +void +phydm_print_rate( + void *p_dm_void, + u8 rate, + u32 dbg_component +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0; + u8 b_sgi = (rate & 0x80) >> 7; + + ODM_RT_TRACE_F(p_dm_odm, dbg_component, ODM_DBG_LOUD, ("( %s%s%s%s%d%s%s)\n", + ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", + ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", + ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) : ((rate_idx >= ODM_RATEMCS0) ? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M) ? legacy_table[rate_idx] : 0)), + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M")); +} + +void +phydm_c2h_ra_report_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u8 macid = cmd_buf[1]; + u8 rate = cmd_buf[0]; + u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u8 pre_rate = p_ra_table->link_tx_rate[macid]; + u8 rate_order; + + if (cmd_len >= 4) { + if (cmd_buf[3] == 0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("TX Init-rate Update[%d]:", macid)); + /**/ + } else if (cmd_buf[3] == 0xff) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("FW Level: Fix rate[%d]:", macid)); + /**/ + } else if (cmd_buf[3] == 1) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Success[%d]:", macid)); + /**/ + } else if (cmd_buf[3] == 2) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try Fail & Try Again[%d]:", macid)); + /**/ + } else if (cmd_buf[3] == 3) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("rate Back[%d]:", macid)); + /**/ + } else if (cmd_buf[3] == 4) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("start rate by RSSI[%d]:", macid)); + /**/ + } else if (cmd_buf[3] == 5) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Try rate[%d]:", macid)); + /**/ + } + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx rate Update[%d]:", macid)); + /**/ + } + + /*phydm_print_rate(p_dm_odm, pre_rate_idx, ODM_COMP_RATE_ADAPTIVE);*/ + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, (">\n",macid );*/ + phydm_print_rate(p_dm_odm, rate, ODM_COMP_RATE_ADAPTIVE); + + p_ra_table->link_tx_rate[macid] = rate; + + /*trigger power training*/ + rate_order = phydm_rate_order_compute(p_dm_odm, rate_idx); + + if ((p_dm_odm->is_one_entry_only) || + ((rate_order > p_ra_table->highest_client_tx_order) && (p_ra_table->power_tracking_flag == 1)) + ) { + phydm_update_pwr_track(p_dm_odm, rate_idx); + p_ra_table->power_tracking_flag = 0; + } + + /*trigger dynamic rate ID*/ + +} + +void +odm_rssi_monitor_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + + p_ra_table->firstconnect = false; +} + +void +odm_ra_post_action_on_assoc( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + /* + p_dm_odm->h2c_rarpt_connect = 1; + odm_rssi_monitor_check(p_dm_odm); + p_dm_odm->h2c_rarpt_connect = 0; + */ +} + +void +phydm_init_ra_info( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +} + +void +phydm_modify_RA_PCR_threshold( + void *p_dm_void, + u8 RA_offset_direction, + u8 RA_threshold_offset + +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + + p_ra_table->RA_offset_direction = RA_offset_direction; + p_ra_table->RA_threshold_offset = RA_threshold_offset; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Set RA_threshold_offset = (( %s%d ))\n", ((RA_threshold_offset == 0) ? " " : ((RA_offset_direction) ? "+" : "-")), RA_threshold_offset)); +} + +/*H2C_RSSI_REPORT*/ +s8 phydm_rssi_report(struct PHY_DM_STRUCT *p_dm_odm, u8 mac_id) +{ + struct _ADAPTER *adapter = p_dm_odm->adapter; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(adapter); + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 h2c_parameter[H2C_0X42_LENGTH] = {0}; + u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0; + u8 cmdlen = H2C_0X42_LENGTH, first_connect = _FALSE; + u64 cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0; + struct sta_info *p_entry = p_dm_odm->p_odm_sta_info[mac_id]; + + if (!IS_STA_VALID(p_entry)) + return _FAIL; + + if (mac_id != p_entry->mac_id) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u:%u invalid\n", __func__, mac_id, p_entry->mac_id)); + rtw_warn_on(1); + return _FAIL; + } + + if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ + return _FAIL; + + if (p_dm_odm->is_in_lps_pg) + return _FAIL; + + if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, p_entry->mac_id, MAC_ARG(p_entry->hwaddr))); + return _FAIL; + } + + cur_tx_ok_cnt = pdvobjpriv->traffic_stat.cur_tx_bytes; + cur_rx_ok_cnt = pdvobjpriv->traffic_stat.cur_rx_bytes; + if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6)) + UL_DL_STATE = 1; + else + UL_DL_STATE = 0; + + + if (tx_bf_en) + STBC_TX = 0; + else { + if (is_supported_vht(p_entry->wireless_mode)) + STBC_TX = TEST_FLAG(p_entry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); + else + STBC_TX = TEST_FLAG(p_entry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); + } + + h2c_parameter[0] = (u8)(p_entry->mac_id & 0xFF); + h2c_parameter[2] = p_entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F; + + if (UL_DL_STATE) + h2c_parameter[3] |= RAINFO_BE_RX_STATE; + + if (tx_bf_en) + h2c_parameter[3] |= RAINFO_BF_STATE; + if (STBC_TX) + h2c_parameter[3] |= RAINFO_STBC_STATE; + if (p_dm_odm->noisy_decision) + h2c_parameter[3] |= RAINFO_NOISY_STATE; + + if ((p_entry->ra_rpt_linked == _FALSE) && (p_entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND)) { + h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + p_entry->ra_rpt_linked = _TRUE; + p_entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD; + first_connect = _TRUE; + } + + h2c_parameter[4] = (p_ra_table->RA_threshold_offset & 0x7f) | (p_ra_table->RA_offset_direction << 7); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA_threshold_offset = (( %s%d ))\n", ((p_ra_table->RA_threshold_offset == 0) ? " " : ((p_ra_table->RA_offset_direction) ? "+" : "-")), p_ra_table->RA_threshold_offset)); + + if (first_connect) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, + p_entry->mac_id, MAC_ARG(p_entry->hwaddr), p_entry->rssi_stat.undecorated_smoothed_pwdb)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, + (UL_DL_STATE) ? "DL" : "UL", (tx_bf_en) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", + (p_dm_odm->noisy_decision) ? "True" : "False", (first_connect) ? "True" : "False")); + } + + if (p_hal_data->fw_ractrl == _TRUE) { + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_RSSI_REPORT, cmdlen, h2c_parameter); + } else { + } + return _SUCCESS; +} + +void phydm_ra_rssi_rpt_wk_hdl(void *p_context) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; + int i; + u8 mac_id = 0xFF; + struct sta_info *p_entry = NULL; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ + continue; + if (p_entry->ra_rpt_linked == _FALSE) { + mac_id = i; + break; + } + } + } + if (mac_id != 0xFF) + phydm_rssi_report(p_dm_odm, mac_id); +} +void phydm_ra_rssi_rpt_wk(void *p_context) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_context; + + rtw_run_in_thread_cmd(p_dm_odm->adapter, phydm_ra_rssi_rpt_wk_hdl, p_dm_odm); +} + +static void +find_minimum_rssi( + struct _ADAPTER *p_adapter +) +{ + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->odmpriv); + + /*Determine the minimum RSSI*/ + + if ((p_dm_odm->is_linked != _TRUE) && + (p_hal_data->entry_min_undecorated_smoothed_pwdb == 0)) { + p_hal_data->min_undecorated_pwdb_for_dm = 0; + /*ODM_RT_TRACE(p_dm_odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ + } else + p_hal_data->min_undecorated_pwdb_for_dm = p_hal_data->entry_min_undecorated_smoothed_pwdb; + + /*DBG_8192C("%s=>min_undecorated_pwdb_for_dm(%d)\n",__FUNCTION__,pdmpriv->min_undecorated_pwdb_for_dm);*/ + /*ODM_RT_TRACE(p_dm_odm,COMP_DIG, DBG_LOUD, ("min_undecorated_pwdb_for_dm =%d\n",p_hal_data->min_undecorated_pwdb_for_dm));*/ +} + +void +odm_rssi_monitor_check_ce( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct sta_info *p_entry; + int i; + int tmp_entry_max_pwdb = 0, tmp_entry_min_pwdb = 0xff; + u8 sta_cnt = 0; + + if (p_dm_odm->is_linked != _TRUE) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + p_entry = p_dm_odm->p_odm_sta_info[i]; + if (IS_STA_VALID(p_entry)) { + if (IS_MCAST(p_entry->hwaddr)) /*if(psta->mac_id ==1)*/ + continue; + + if (p_entry->rssi_stat.undecorated_smoothed_pwdb == (-1)) + continue; + + if (p_entry->rssi_stat.undecorated_smoothed_pwdb < tmp_entry_min_pwdb) + tmp_entry_min_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + + if (p_entry->rssi_stat.undecorated_smoothed_pwdb > tmp_entry_max_pwdb) + tmp_entry_max_pwdb = p_entry->rssi_stat.undecorated_smoothed_pwdb; + + if (phydm_rssi_report(p_dm_odm, i)) + sta_cnt++; + } + } + + if (tmp_entry_max_pwdb != 0) /* If associated entry is found */ + p_hal_data->entry_max_undecorated_smoothed_pwdb = tmp_entry_max_pwdb; + else + p_hal_data->entry_max_undecorated_smoothed_pwdb = 0; + + if (tmp_entry_min_pwdb != 0xff) /* If associated entry is found */ + p_hal_data->entry_min_undecorated_smoothed_pwdb = tmp_entry_min_pwdb; + else + p_hal_data->entry_min_undecorated_smoothed_pwdb = 0; + + find_minimum_rssi(adapter);/* get pdmpriv->min_undecorated_pwdb_for_dm */ + + p_dm_odm->rssi_min = p_hal_data->min_undecorated_pwdb_for_dm; +} + +void +odm_rssi_monitor_check( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + if (!(p_dm_odm->support_ability & ODM_BB_RSSI_MONITOR)) + return; + + switch (p_dm_odm->support_platform) { + case ODM_CE: + odm_rssi_monitor_check_ce(p_dm_odm); + break; + default: + break; + } + +} + +void +odm_rate_adaptive_mask_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_RATE_ADAPTIVE *p_odm_ra = &p_dm_odm->rate_adaptive; + + p_odm_ra->type = dm_type_by_driver; + if (p_odm_ra->type == dm_type_by_driver) + p_dm_odm->is_use_ra_mask = _TRUE; + else + p_dm_odm->is_use_ra_mask = _FALSE; + + p_odm_ra->ratr_state = DM_RATR_STA_INIT; + p_odm_ra->ldpc_thres = 35; + p_odm_ra->is_use_ldpc = false; + p_odm_ra->high_rssi_thresh = 50; + p_odm_ra->low_rssi_thresh = 20; +} +/*----------------------------------------------------------------------------- + * Function: odm_refresh_rate_adaptive_mask() + * + * Overview: Update rate table mask according to rssi + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/27/2009 hpfan Create version 0. + * + *---------------------------------------------------------------------------*/ +void +odm_refresh_rate_adaptive_mask( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + + if (!p_dm_odm->is_linked) + return; + + if (!(p_dm_odm->support_ability & ODM_BB_RA_MASK)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_refresh_rate_adaptive_mask(): Return cos not supported\n")); + return; + } + + p_ra_table->force_update_ra_mask_count++; + /* */ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */ + /* at the same time. In the stage2/3, we need to prive universal interface and merge all */ + /* HW dynamic mechanism. */ + /* */ + switch (p_dm_odm->support_platform) { + case ODM_CE: + odm_refresh_rate_adaptive_mask_ce(p_dm_odm); + break; + } +} + +u8 +phydm_trans_platform_bw( + void *p_dm_void, + u8 BW +) +{ + if (BW == CHANNEL_WIDTH_20) + BW = PHYDM_BW_20; + + else if (BW == CHANNEL_WIDTH_40) + BW = PHYDM_BW_40; + + else if (BW == CHANNEL_WIDTH_80) + BW = PHYDM_BW_80; + + else if (BW == CHANNEL_WIDTH_160) + BW = PHYDM_BW_160; + + else if (BW == CHANNEL_WIDTH_80_80) + BW = PHYDM_BW_80_80; + + return BW; +} + +u8 +phydm_trans_platform_rf_type( + void *p_dm_void, + u8 rf_type +) +{ + if (rf_type == RF_1T2R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == RF_2T4R) + rf_type = PHYDM_RF_2T4R; + + else if (rf_type == RF_2T2R) + rf_type = PHYDM_RF_2T2R; + + else if (rf_type == RF_1T1R) + rf_type = PHYDM_RF_1T1R; + + else if (rf_type == RF_2T2R_GREEN) + rf_type = PHYDM_RF_2T2R_GREEN; + + else if (rf_type == RF_3T3R) + rf_type = PHYDM_RF_3T3R; + + else if (rf_type == RF_4T4R) + rf_type = PHYDM_RF_4T4R; + + else if (rf_type == RF_2T3R) + rf_type = PHYDM_RF_1T2R; + + else if (rf_type == RF_3T4R) + rf_type = PHYDM_RF_3T4R; + + return rf_type; + +} + +u32 +phydm_trans_platform_wireless_mode( + void *p_dm_void, + u32 wireless_mode +) +{ + if (wireless_mode == WIRELESS_11A) + wireless_mode = PHYDM_WIRELESS_MODE_A; + + else if (wireless_mode == WIRELESS_11B) + wireless_mode = PHYDM_WIRELESS_MODE_B; + + else if ((wireless_mode == WIRELESS_11G) || (wireless_mode == WIRELESS_11BG)) + wireless_mode = PHYDM_WIRELESS_MODE_G; + + else if (wireless_mode == WIRELESS_AUTO) + wireless_mode = PHYDM_WIRELESS_MODE_AUTO; + + else if ((wireless_mode == WIRELESS_11_24N) || (wireless_mode == WIRELESS_11G_24N) || (wireless_mode == WIRELESS_11B_24N) || + (wireless_mode == WIRELESS_11BG_24N) || (wireless_mode == WIRELESS_MODE_24G) || (wireless_mode == WIRELESS_11ABGN) || (wireless_mode == WIRELESS_11AGN)) + wireless_mode = PHYDM_WIRELESS_MODE_N_24G; + + else if ((wireless_mode == WIRELESS_11_5N) || (wireless_mode == WIRELESS_11A_5N)) + wireless_mode = PHYDM_WIRELESS_MODE_N_5G; + + else if ((wireless_mode == WIRELESS_11AC) || (wireless_mode == WIRELESS_11_5AC) || (wireless_mode == WIRELESS_MODE_5G)) + wireless_mode = PHYDM_WIRELESS_MODE_AC_5G; + + else if (wireless_mode == WIRELESS_11_24AC) + wireless_mode = PHYDM_WIRELESS_MODE_AC_24G; + + else if (wireless_mode == WIRELESS_11AC) + wireless_mode = PHYDM_WIRELESS_MODE_AC_ONLY; + + else if (wireless_mode == WIRELESS_MODE_MAX) + wireless_mode = PHYDM_WIRELESS_MODE_MAX; + else + wireless_mode = PHYDM_WIRELESS_MODE_UNKNOWN; + + return wireless_mode; + +} + +u8 +phydm_vht_en_mapping( + void *p_dm_void, + u32 wireless_mode +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 vht_en_out = 0; + + if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) || + (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) || + (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY) + ) { + vht_en_out = 1; + /**/ + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n", wireless_mode, vht_en_out)); + return vht_en_out; +} + +u8 +phydm_rate_id_mapping( + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 bw +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 rate_id_idx = 0; + u8 phydm_BW; + u8 phydm_rf_type; + + phydm_BW = phydm_trans_platform_bw(p_dm_odm, bw); + phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); + wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n", + wireless_mode, phydm_rf_type, phydm_BW)); + + switch (wireless_mode) { + + case PHYDM_WIRELESS_MODE_N_24G: + { + + if (phydm_BW == PHYDM_BW_40) { + + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_BGN_40M_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_BGN_40M_2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + + } else { + + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_BGN_20M_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_BGN_20M_2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + } + } + break; + + case PHYDM_WIRELESS_MODE_N_5G: + { + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_GN_N1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_GN_N2SS; + else + rate_id_idx = PHYDM_ARFR5_N_3SS; + } + + break; + + case PHYDM_WIRELESS_MODE_G: + rate_id_idx = PHYDM_BG; + break; + + case PHYDM_WIRELESS_MODE_A: + rate_id_idx = PHYDM_G; + break; + + case PHYDM_WIRELESS_MODE_B: + rate_id_idx = PHYDM_B_20M; + break; + + case PHYDM_WIRELESS_MODE_AC_5G: + case PHYDM_WIRELESS_MODE_AC_ONLY: + { + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } + break; + + case PHYDM_WIRELESS_MODE_AC_24G: + { + /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS in 2.4G/5G*/ + if (phydm_BW >= PHYDM_BW_80) { + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR1_AC_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_ARFR0_AC_2SS; + else + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } else { + + if (phydm_rf_type == PHYDM_RF_1T1R) + rate_id_idx = PHYDM_ARFR2_AC_2G_1SS; + else if (phydm_rf_type == PHYDM_RF_2T2R) + rate_id_idx = PHYDM_ARFR3_AC_2G_2SS; + else + rate_id_idx = PHYDM_ARFR4_AC_3SS; + } + } + break; + + default: + rate_id_idx = 0; + break; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RA rate ID = (( 0x%x ))\n", rate_id_idx)); + + return rate_id_idx; +} + +void +phydm_update_hal_ra_mask( + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 BW, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_lsb_in, + u8 tx_rate_level +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 mask_rate_threshold; + u8 phydm_rf_type; + u8 phydm_BW; + u32 ratr_bitmap = *ratr_bitmap_lsb_in, ratr_bitmap_msb = *ratr_bitmap_msb_in; + /*struct _ODM_RATE_ADAPTIVE* p_ra = &(p_dm_odm->rate_adaptive);*/ + + wireless_mode = phydm_trans_platform_wireless_mode(p_dm_odm, wireless_mode); + + phydm_rf_type = phydm_trans_platform_rf_type(p_dm_odm, rf_type); + phydm_BW = phydm_trans_platform_bw(p_dm_odm, BW); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("phydm_rf_type = (( %x )), rf_type = (( %x ))\n", phydm_rf_type, rf_type));*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Platfoem original RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap)); + + switch (wireless_mode) { + + case PHYDM_WIRELESS_MODE_B: + { + ratr_bitmap &= 0x0000000f; + } + break; + + case PHYDM_WIRELESS_MODE_G: + { + ratr_bitmap &= 0x00000ff5; + } + break; + + case PHYDM_WIRELESS_MODE_A: + { + ratr_bitmap &= 0x00000ff0; + } + break; + + case PHYDM_WIRELESS_MODE_N_24G: + case PHYDM_WIRELESS_MODE_N_5G: + { + if (mimo_ps_enable) + phydm_rf_type = PHYDM_RF_1T1R; + + if (phydm_rf_type == PHYDM_RF_1T1R) { + + if (phydm_BW == PHYDM_BW_40) + ratr_bitmap &= 0x000ff015; + else + ratr_bitmap &= 0x000ff005; + } else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) { + + if (phydm_BW == PHYDM_BW_40) + ratr_bitmap &= 0x0ffff015; + else + ratr_bitmap &= 0x0ffff005; + } else { /*3T*/ + + ratr_bitmap &= 0xfffff015; + ratr_bitmap_msb &= 0xf; + } + } + break; + + case PHYDM_WIRELESS_MODE_AC_24G: + { + if (phydm_rf_type == PHYDM_RF_1T1R) + ratr_bitmap &= 0x003ff015; + else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) + ratr_bitmap &= 0xfffff015; + else {/*3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } + + if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } + break; + + case PHYDM_WIRELESS_MODE_AC_5G: + { + if (phydm_rf_type == PHYDM_RF_1T1R) + ratr_bitmap &= 0x003ff010; + else if (phydm_rf_type == PHYDM_RF_2T2R || phydm_rf_type == PHYDM_RF_2T4R || phydm_rf_type == PHYDM_RF_2T3R) + ratr_bitmap &= 0xfffff010; + else {/*3T*/ + + ratr_bitmap &= 0xfffff010; + ratr_bitmap_msb &= 0x3ff; + } + + if (phydm_BW == PHYDM_BW_20) {/* AC 20MHz doesn't support MCS9 */ + ratr_bitmap &= 0x7fdfffff; + ratr_bitmap_msb &= 0x1ff; + } + } + break; + + default: + break; + } + + if (wireless_mode != PHYDM_WIRELESS_MODE_B) { + + if (tx_rate_level == 0) + ratr_bitmap &= 0xffffffff; + else if (tx_rate_level == 1) + ratr_bitmap &= 0xfffffff0; + else if (tx_rate_level == 2) + ratr_bitmap &= 0xffffefe0; + else if (tx_rate_level == 3) + ratr_bitmap &= 0xffffcfc0; + else if (tx_rate_level == 4) + ratr_bitmap &= 0xffff8f80; + else if (tx_rate_level >= 5) + ratr_bitmap &= 0xffff0f00; + + } + + if (disable_cck_rate) + ratr_bitmap &= 0xfffffff0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n", + wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable, tx_rate_level)); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("111 Phydm modified RA Mask = (( 0x %x | %x ))\n", ratr_bitmap_msb, ratr_bitmap));*/ + + *ratr_bitmap_lsb_in = ratr_bitmap; + *ratr_bitmap_msb_in = ratr_bitmap_msb; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Phydm modified RA Mask = (( 0x %x | %x ))\n", *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in)); + +} + +u8 +phydm_RA_level_decision( + void *p_dm_void, + u32 rssi, + u8 ratr_state +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 ra_lowest_rate; + u8 ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {20, 34, 38, 42, 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/ + u8 new_ratr_state = 0; + u8 i; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n", ratr_state, + ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + + if (i >= (ratr_state)) + ra_rate_floor_table[i] += RA_FLOOR_UP_GAP; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n", + rssi, ra_rate_floor_table[0], ra_rate_floor_table[1], ra_rate_floor_table[2], ra_rate_floor_table[3], ra_rate_floor_table[4], ra_rate_floor_table[5])); + + for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { + + if (rssi < ra_rate_floor_table[i]) { + new_ratr_state = i; + break; + } + } + + return new_ratr_state; + +} + +void +odm_refresh_rate_adaptive_mask_ce( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; + u32 i; + struct sta_info *p_entry; + u8 ratr_state_new; + + if (RTW_CANNOT_RUN(p_adapter)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_refresh_rate_adaptive_mask(): driver is going to unload\n")); + return; + } + + if (!p_dm_odm->is_use_ra_mask) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_refresh_rate_adaptive_mask(): driver does not control rate adaptive mask\n")); + return; + } + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + + p_entry = p_dm_odm->p_odm_sta_info[i]; + + if (IS_STA_VALID(p_entry)) { + + if (IS_MCAST(p_entry->hwaddr)) + continue; + + + ratr_state_new = phydm_RA_level_decision(p_dm_odm, p_entry->rssi_stat.undecorated_smoothed_pwdb, p_entry->rssi_level); + + if ((p_entry->rssi_level != ratr_state_new) || (p_ra_table->force_update_ra_mask_count >= FORCED_UPDATE_RAMASK_PERIOD)) { + + p_ra_table->force_update_ra_mask_count = 0; + /*ODM_PRINT_ADDR(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr :"), pstat->hwaddr);*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Update Tx RA Level: ((%x)) -> ((%x)), RSSI = ((%d))\n", + p_entry->rssi_level, ratr_state_new, p_entry->rssi_stat.undecorated_smoothed_pwdb)); + + p_entry->rssi_level = ratr_state_new; + rtw_hal_update_ra_mask(p_entry, p_entry->rssi_level, _FALSE); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Stay in RA level = (( %d ))\n\n", ratr_state_new)); + /**/ + } + + } + } +} + +u8 +phydm_rate_order_compute( + void *p_dm_void, + u8 rate_idx +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 rate_order = 0; + + if (rate_idx >= ODM_RATEVHTSS4MCS0) { + + rate_idx -= ODM_RATEVHTSS4MCS0; + /**/ + } else if (rate_idx >= ODM_RATEVHTSS3MCS0) { + + rate_idx -= ODM_RATEVHTSS3MCS0; + /**/ + } else if (rate_idx >= ODM_RATEVHTSS2MCS0) { + + rate_idx -= ODM_RATEVHTSS2MCS0; + /**/ + } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { + + rate_idx -= ODM_RATEVHTSS1MCS0; + /**/ + } else if (rate_idx >= ODM_RATEMCS24) { + + rate_idx -= ODM_RATEMCS24; + /**/ + } else if (rate_idx >= ODM_RATEMCS16) { + + rate_idx -= ODM_RATEMCS16; + /**/ + } else if (rate_idx >= ODM_RATEMCS8) { + + rate_idx -= ODM_RATEMCS8; + /**/ + } + rate_order = rate_idx; + + return rate_order; + +} + +void +phydm_ra_common_info_update( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + u16 macid; + u8 rate_order_tmp; + u8 cnt = 0; + + p_ra_table->highest_client_tx_order = 0; + p_ra_table->power_tracking_flag = 1; + + if (p_dm_odm->number_linked_client != 0) { + for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) { + + rate_order_tmp = phydm_rate_order_compute(p_dm_odm, ((p_ra_table->link_tx_rate[macid]) & 0x7f)); + + if (rate_order_tmp >= (p_ra_table->highest_client_tx_order)) { + p_ra_table->highest_client_tx_order = rate_order_tmp; + p_ra_table->highest_client_tx_rate_order = macid; + } + + cnt++; + + if (cnt == p_dm_odm->number_linked_client) + break; + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("MACID[%d], Highest Tx order Update for power traking: %d\n", (p_ra_table->highest_client_tx_rate_order), (p_ra_table->highest_client_tx_order))); + } +} + +void +phydm_ra_info_watchdog( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + phydm_ra_common_info_update(p_dm_odm); + phydm_ra_dynamic_retry_limit(p_dm_odm); + phydm_ra_dynamic_retry_count(p_dm_odm); + odm_refresh_rate_adaptive_mask(p_dm_odm); +} + +void +phydm_ra_info_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _rate_adaptive_table_ *p_ra_table = &p_dm_odm->dm_ra_table; + + p_ra_table->highest_client_tx_rate_order = 0; + p_ra_table->highest_client_tx_order = 0; + p_ra_table->RA_threshold_offset = 0; + p_ra_table->RA_offset_direction = 0; + + + +} + +u8 +odm_find_rts_rate( + void *p_dm_void, + u8 tx_rate, + boolean is_erp_protect +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 rts_ini_rate = ODM_RATE6M; + + if (is_erp_protect) /* use CCK rate as RTS*/ + rts_ini_rate = ODM_RATE1M; + else { + switch (tx_rate) { + case ODM_RATEVHTSS3MCS9: + case ODM_RATEVHTSS3MCS8: + case ODM_RATEVHTSS3MCS7: + case ODM_RATEVHTSS3MCS6: + case ODM_RATEVHTSS3MCS5: + case ODM_RATEVHTSS3MCS4: + case ODM_RATEVHTSS3MCS3: + case ODM_RATEVHTSS2MCS9: + case ODM_RATEVHTSS2MCS8: + case ODM_RATEVHTSS2MCS7: + case ODM_RATEVHTSS2MCS6: + case ODM_RATEVHTSS2MCS5: + case ODM_RATEVHTSS2MCS4: + case ODM_RATEVHTSS2MCS3: + case ODM_RATEVHTSS1MCS9: + case ODM_RATEVHTSS1MCS8: + case ODM_RATEVHTSS1MCS7: + case ODM_RATEVHTSS1MCS6: + case ODM_RATEVHTSS1MCS5: + case ODM_RATEVHTSS1MCS4: + case ODM_RATEVHTSS1MCS3: + case ODM_RATEMCS15: + case ODM_RATEMCS14: + case ODM_RATEMCS13: + case ODM_RATEMCS12: + case ODM_RATEMCS11: + case ODM_RATEMCS7: + case ODM_RATEMCS6: + case ODM_RATEMCS5: + case ODM_RATEMCS4: + case ODM_RATEMCS3: + case ODM_RATE54M: + case ODM_RATE48M: + case ODM_RATE36M: + case ODM_RATE24M: + rts_ini_rate = ODM_RATE24M; + break; + case ODM_RATEVHTSS3MCS2: + case ODM_RATEVHTSS3MCS1: + case ODM_RATEVHTSS2MCS2: + case ODM_RATEVHTSS2MCS1: + case ODM_RATEVHTSS1MCS2: + case ODM_RATEVHTSS1MCS1: + case ODM_RATEMCS10: + case ODM_RATEMCS9: + case ODM_RATEMCS2: + case ODM_RATEMCS1: + case ODM_RATE18M: + case ODM_RATE12M: + rts_ini_rate = ODM_RATE12M; + break; + case ODM_RATEVHTSS3MCS0: + case ODM_RATEVHTSS2MCS0: + case ODM_RATEVHTSS1MCS0: + case ODM_RATEMCS8: + case ODM_RATEMCS0: + case ODM_RATE9M: + case ODM_RATE6M: + rts_ini_rate = ODM_RATE6M; + break; + case ODM_RATE11M: + case ODM_RATE5_5M: + case ODM_RATE2M: + case ODM_RATE1M: + rts_ini_rate = ODM_RATE1M; + break; + default: + rts_ini_rate = ODM_RATE6M; + break; + } + } + + if (*p_dm_odm->p_band_type == 1) { + if (rts_ini_rate < ODM_RATE6M) + rts_ini_rate = ODM_RATE6M; + } + return rts_ini_rate; + +} + +void +odm_set_ra_dm_arfb_by_noisy( + struct PHY_DM_STRUCT *p_dm_odm +) +{ +} + +void +odm_update_noisy_state( + void *p_dm_void, + boolean is_noisy_state_from_c2h +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + +/* JJ ADD 20161014 */ + /*dbg_print("Get C2H Command! NoisyState=0x%x\n ", is_noisy_state_from_c2h);*/ + if (p_dm_odm->support_ic_type == ODM_RTL8821 || p_dm_odm->support_ic_type == ODM_RTL8812 || + p_dm_odm->support_ic_type == ODM_RTL8723B || p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) + p_dm_odm->is_noisy_state = is_noisy_state_from_c2h; + odm_set_ra_dm_arfb_by_noisy(p_dm_odm); +}; + +void +phydm_update_pwr_track( + void *p_dm_void, + u8 rate +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u8 path_idx = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Pwr Track Get rate=0x%x\n", rate)); + + p_dm_odm->tx_rate = rate; +} + +u64 +phydm_get_rate_bitmap_ex( + void *p_dm_void, + u32 macid, + u64 ra_mask, + u8 rssi_level, + u64 *dm_ra_mask, + u8 *dm_rte_id +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct sta_info *p_entry; + u64 rate_bitmap = 0; + u8 wireless_mode; + + p_entry = p_dm_odm->p_odm_sta_info[macid]; + if (!IS_STA_VALID(p_entry)) + return ra_mask; + wireless_mode = p_entry->wireless_mode; + switch (wireless_mode) { + case ODM_WM_B: + if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */ + rate_bitmap = 0x000000000000000d; + else + rate_bitmap = 0x000000000000000f; + break; + + case (ODM_WM_G): + case (ODM_WM_A): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000000000f00; + else + rate_bitmap = 0x0000000000000ff0; + break; + + case (ODM_WM_B|ODM_WM_G): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000000000f00; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0000000000000ff0; + else + rate_bitmap = 0x0000000000000ff5; + break; + + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_B|ODM_WM_N24G): + case (ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_A|ODM_WM_N5G): + { + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000000000f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000000000ff000; + else { + if (*(p_dm_odm->p_band_width) == ODM_BW40M) + rate_bitmap = 0x00000000000ff015; + else + rate_bitmap = 0x00000000000ff005; + } + } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x000000000f8f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x000000000f8ff000; + else { + if (*(p_dm_odm->p_band_width) == ODM_BW40M) + rate_bitmap = 0x000000000f8ff015; + else + rate_bitmap = 0x000000000f8ff005; + } + } else { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000f0f0f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0000000fcfcfe000; + else { + if (*(p_dm_odm->p_band_width) == ODM_BW40M) + rate_bitmap = 0x0000000ffffff015; + else + rate_bitmap = 0x0000000ffffff005; + } + } + } + break; + + case (ODM_WM_AC|ODM_WM_G): + if (rssi_level == 1) + rate_bitmap = 0x00000000fc3f0000; + else if (rssi_level == 2) + rate_bitmap = 0x00000000fffff000; + else + rate_bitmap = 0x00000000ffffffff; + break; + + case (ODM_WM_AC|ODM_WM_A): + + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x00000000003f8000; + else if (rssi_level == 2) + rate_bitmap = 0x00000000003fe000; + else + rate_bitmap = 0x00000000003ff010; + } else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x00000000fe3f8000; /* VHT 2SS MCS3~9 */ + else if (rssi_level == 2) + rate_bitmap = 0x00000000fffff000; /* VHT 2SS MCS0~9 */ + else + rate_bitmap = 0x00000000fffff010; /* All */ + } else { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x000003f8fe3f8000ULL; /* VHT 3SS MCS3~9 */ + else if (rssi_level == 2) + rate_bitmap = 0x000003fffffff000ULL; /* VHT3SS MCS0~9 */ + else + rate_bitmap = 0x000003fffffff010ULL; /* All */ + } + break; + + default: + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) + rate_bitmap = 0x00000000000fffff; + else if (p_dm_odm->rf_type == ODM_2T2R || p_dm_odm->rf_type == ODM_2T3R || p_dm_odm->rf_type == ODM_2T4R) + rate_bitmap = 0x000000000fffffff; + else + rate_bitmap = 0x0000003fffffffffULL; + break; + + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, wireless_mode, rate_bitmap)); + + return ra_mask & rate_bitmap; +} + +u32 +odm_get_rate_bitmap( + void *p_dm_void, + u32 macid, + u32 ra_mask, + u8 rssi_level +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct sta_info *p_entry; + u32 rate_bitmap = 0; + u8 wireless_mode; + /* u8 wireless_mode =*(p_dm_odm->p_wireless_mode); */ + + p_entry = p_dm_odm->p_odm_sta_info[macid]; + if (!IS_STA_VALID(p_entry)) + return ra_mask; + + wireless_mode = p_entry->wireless_mode; + + switch (wireless_mode) { + case ODM_WM_B: + if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */ + rate_bitmap = 0x0000000d; + else + rate_bitmap = 0x0000000f; + break; + + case (ODM_WM_G): + case (ODM_WM_A): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else + rate_bitmap = 0x00000ff0; + break; + + case (ODM_WM_B|ODM_WM_G): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000ff0; + else + rate_bitmap = 0x00000ff5; + break; + + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_B|ODM_WM_N24G): + case (ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_A|ODM_WM_N5G): + { + if (p_dm_odm->rf_type == ODM_1T2R || p_dm_odm->rf_type == ODM_1T1R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x000f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x000ff000; + else { + if (*(p_dm_odm->p_band_width) == ODM_BW40M) + rate_bitmap = 0x000ff015; + else + rate_bitmap = 0x000ff005; + } + } else { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0f8f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0f8ff000; + else { + if (*(p_dm_odm->p_band_width) == ODM_BW40M) + rate_bitmap = 0x0f8ff015; + else + rate_bitmap = 0x0f8ff005; + } + } + } + break; + + case (ODM_WM_AC|ODM_WM_G): + if (rssi_level == 1) + rate_bitmap = 0xfc3f0000; + else if (rssi_level == 2) + rate_bitmap = 0xfffff000; + else + rate_bitmap = 0xffffffff; + break; + + case (ODM_WM_AC|ODM_WM_A): + + if (p_dm_odm->rf_type == RF_1T1R) { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x003f8000; + else if (rssi_level == 2) + rate_bitmap = 0x003ff000; + else + rate_bitmap = 0x003ff010; + } else { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0xfe3f8000; /* VHT 2SS MCS3~9 */ + else if (rssi_level == 2) + rate_bitmap = 0xfffff000; /* VHT 2SS MCS0~9 */ + else + rate_bitmap = 0xfffff010; /* All */ + } + break; + + default: + if (p_dm_odm->rf_type == RF_1T2R) + rate_bitmap = 0x000fffff; + else + rate_bitmap = 0x0fffffff; + break; + + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("%s ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, wireless_mode, rate_bitmap)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, wireless_mode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, wireless_mode, rate_bitmap)); + + return ra_mask & rate_bitmap; + +} + + +boolean +odm_ra_state_check( + void *p_dm_void, + s32 RSSI, + boolean is_force_update, + u8 *p_ra_tr_state +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ODM_RATE_ADAPTIVE *p_ra = &p_dm_odm->rate_adaptive; + const u8 go_up_gap = 5; + u8 high_rssi_thresh_for_ra = p_ra->high_rssi_thresh; + u8 low_rssi_thresh_for_ra = p_ra->low_rssi_thresh; + u8 ratr_state; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *p_ra_tr_state)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); + /* threshold Adjustment:*/ + /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough.*/ + /* Here go_up_gap is added to solve the boundary's level alternation issue.*/ + + switch (*p_ra_tr_state) { + case DM_RATR_STA_INIT: + case DM_RATR_STA_HIGH: + break; + + case DM_RATR_STA_MIDDLE: + high_rssi_thresh_for_ra += go_up_gap; + break; + + case DM_RATR_STA_LOW: + high_rssi_thresh_for_ra += go_up_gap; + low_rssi_thresh_for_ra += go_up_gap; + break; + + default: + ODM_RT_ASSERT(p_dm_odm, false, ("wrong rssi level setting %d !", *p_ra_tr_state)); + break; + } + + /* Decide ratr_state by RSSI.*/ + if (RSSI > high_rssi_thresh_for_ra) + ratr_state = DM_RATR_STA_HIGH; + else if (RSSI > low_rssi_thresh_for_ra) + ratr_state = DM_RATR_STA_MIDDLE; + else + ratr_state = DM_RATR_STA_LOW; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", high_rssi_thresh_for_ra, low_rssi_thresh_for_ra)); + /*printk("==>%s,ratr_state:0x%02x,RSSI:%d\n",__FUNCTION__,ratr_state,RSSI);*/ + + if (*p_ra_tr_state != ratr_state || is_force_update) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d->%d\n", *p_ra_tr_state, ratr_state)); + *p_ra_tr_state = ratr_state; + return true; + } + + return false; +} + diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_rainfo.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_rainfo.h new file mode 100644 index 000000000000..8d7262d39c5e --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_rainfo.h @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMRAINFO_H__ +#define __PHYDMRAINFO_H__ + +#define RAINFO_VERSION "4.3" /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */ + +#define FORCED_UPDATE_RAMASK_PERIOD 5 + +#define H2C_0X42_LENGTH 5 +#define H2C_MAX_LENGTH 7 + +#define RA_FLOOR_UP_GAP 3 +#define RA_FLOOR_TABLE_SIZE 7 + +#define ACTIVE_TP_THRESHOLD 150 +#define RA_RETRY_DESCEND_NUM 2 +#define RA_RETRY_LIMIT_LOW 4 +#define RA_RETRY_LIMIT_HIGH 32 + +#define RAINFO_BE_RX_STATE BIT(0) /* 1:RX */ /* ULDL */ +#define RAINFO_STBC_STATE BIT(1) +#define RAINFO_NOISY_STATE BIT(2) /* set by Noisy_Detection */ +#define RAINFO_SHURTCUT_STATE BIT(3) +#define RAINFO_SHURTCUT_FLAG BIT(4) +#define RAINFO_INIT_RSSI_RATE_STATE BIT(5) +#define RAINFO_BF_STATE BIT(6) +#define RAINFO_BE_TX_STATE BIT(7) /* 1:TX */ + +#define RA_MASK_CCK 0xf +#define RA_MASK_OFDM 0xff0 +#define RA_MASK_HT1SS 0xff000 +#define RA_MASK_HT2SS 0xff00000 +#define RA_MASK_HT4SS 0xff0 +#define RA_MASK_VHT1SS 0x3ff000 +#define RA_MASK_VHT2SS 0xffc00000 + +#define RA_FIRST_MACID 0 + +#define ap_init_rate_adaptive_state odm_rate_adaptive_state_ap_init + + #define DM_RATR_STA_INIT 0 + #define DM_RATR_STA_HIGH 1 + #define DM_RATR_STA_MIDDLE 2 + #define DM_RATR_STA_LOW 3 + #define DM_RATR_STA_ULTRA_LOW 4 + +enum phydm_ra_arfr_num_e { + ARFR_0_RATE_ID = 0x9, + ARFR_1_RATE_ID = 0xa, + ARFR_2_RATE_ID = 0xb, + ARFR_3_RATE_ID = 0xc, + ARFR_4_RATE_ID = 0xd, + ARFR_5_RATE_ID = 0xe +}; + +enum phydm_ra_dbg_para_e { + RADBG_PCR_TH_OFFSET = 0, + RADBG_RTY_PENALTY = 1, + RADBG_N_HIGH = 2, + RADBG_N_LOW = 3, + RADBG_TRATE_UP_TABLE = 4, + RADBG_TRATE_DOWN_TABLE = 5, + RADBG_TRYING_NECESSARY = 6, + RADBG_TDROPING_NECESSARY = 7, + RADBG_RATE_UP_RTY_RATIO = 8, + RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */ + + RADBG_DEBUG_MONITOR1 = 0xc, + RADBG_DEBUG_MONITOR2 = 0xd, + RADBG_DEBUG_MONITOR3 = 0xe, + RADBG_DEBUG_MONITOR4 = 0xf, + RADBG_DEBUG_MONITOR5 = 0x10, + NUM_RA_PARA +}; + +enum phydm_wireless_mode_e { + + PHYDM_WIRELESS_MODE_UNKNOWN = 0x00, + PHYDM_WIRELESS_MODE_A = 0x01, + PHYDM_WIRELESS_MODE_B = 0x02, + PHYDM_WIRELESS_MODE_G = 0x04, + PHYDM_WIRELESS_MODE_AUTO = 0x08, + PHYDM_WIRELESS_MODE_N_24G = 0x10, + PHYDM_WIRELESS_MODE_N_5G = 0x20, + PHYDM_WIRELESS_MODE_AC_5G = 0x40, + PHYDM_WIRELESS_MODE_AC_24G = 0x80, + PHYDM_WIRELESS_MODE_AC_ONLY = 0x100, + PHYDM_WIRELESS_MODE_MAX = 0x800, + PHYDM_WIRELESS_MODE_ALL = 0xFFFF +}; + +enum phydm_rateid_idx_e { + + PHYDM_BGN_40M_2SS = 0, + PHYDM_BGN_40M_1SS = 1, + PHYDM_BGN_20M_2SS = 2, + PHYDM_BGN_20M_1SS = 3, + PHYDM_GN_N2SS = 4, + PHYDM_GN_N1SS = 5, + PHYDM_BG = 6, + PHYDM_G = 7, + PHYDM_B_20M = 8, + PHYDM_ARFR0_AC_2SS = 9, + PHYDM_ARFR1_AC_1SS = 10, + PHYDM_ARFR2_AC_2G_1SS = 11, + PHYDM_ARFR3_AC_2G_2SS = 12, + PHYDM_ARFR4_AC_3SS = 13, + PHYDM_ARFR5_N_3SS = 14 +}; + +enum phydm_rf_type_def_e { + PHYDM_RF_1T1R = 0, + PHYDM_RF_1T2R, + PHYDM_RF_2T2R, + PHYDM_RF_2T2R_GREEN, + PHYDM_RF_2T3R, + PHYDM_RF_2T4R, + PHYDM_RF_3T3R, + PHYDM_RF_3T4R, + PHYDM_RF_4T4R, + PHYDM_RF_MAX_TYPE +}; + +enum phydm_bw_e { + PHYDM_BW_20 = 0, + PHYDM_BW_40, + PHYDM_BW_80, + PHYDM_BW_80_80, + PHYDM_BW_160, + PHYDM_BW_10, + PHYDM_BW_5 +}; + + +struct _rate_adaptive_table_ { + u8 firstconnect; + u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; + u8 highest_client_tx_order; + u16 highest_client_tx_rate_order; + u8 power_tracking_flag; + u8 RA_threshold_offset; + u8 RA_offset_direction; + u8 force_update_ra_mask_count; + + +}; + +struct _ODM_RATE_ADAPTIVE { + u8 type; /* dm_type_by_fw/dm_type_by_driver */ + u8 high_rssi_thresh; /* if RSSI > high_rssi_thresh => ratr_state is DM_RATR_STA_HIGH */ + u8 low_rssi_thresh; /* if RSSI <= low_rssi_thresh => ratr_state is DM_RATR_STA_LOW */ + u8 ratr_state; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ + + u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */ + boolean is_lower_rts_rate; + + boolean is_use_ldpc; +}; + +void +phydm_h2C_debug( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + + +void +phydm_RA_debug_PCR( + void *p_dm_void, + u32 *const dm_value, + u32 *_used, + char *output, + u32 *_out_len +); + + +void +odm_c2h_ra_para_report_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +); + +void +odm_ra_para_adjust( + void *p_dm_void +); + +void +phydm_ra_dynamic_retry_count( + void *p_dm_void +); + +void +phydm_ra_dynamic_retry_limit( + void *p_dm_void +); + +void +phydm_ra_dynamic_rate_id_on_assoc( + void *p_dm_void, + u8 wireless_mode, + u8 init_rate_id +); + +void +phydm_print_rate( + void *p_dm_void, + u8 rate, + u32 dbg_component +); + +void +phydm_c2h_ra_report_handler( + void *p_dm_void, + u8 *cmd_buf, + u8 cmd_len +); + +u8 +phydm_rate_order_compute( + void *p_dm_void, + u8 rate_idx +); + +void +phydm_ra_info_watchdog( + void *p_dm_void +); + +void +phydm_ra_info_init( + void *p_dm_void +); + +void +odm_rssi_monitor_init( + void *p_dm_void +); + +void +phydm_modify_RA_PCR_threshold( + void *p_dm_void, + u8 RA_offset_direction, + u8 RA_threshold_offset +); + +void +odm_rssi_monitor_check( + void *p_dm_void +); + +void +phydm_init_ra_info( + void *p_dm_void +); + +u8 +phydm_vht_en_mapping( + void *p_dm_void, + u32 wireless_mode +); + +u8 +phydm_rate_id_mapping( + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 bw +); + +void +phydm_update_hal_ra_mask( + void *p_dm_void, + u32 wireless_mode, + u8 rf_type, + u8 BW, + u8 mimo_ps_enable, + u8 disable_cck_rate, + u32 *ratr_bitmap_msb_in, + u32 *ratr_bitmap_in, + u8 tx_rate_level +); + +void +odm_rate_adaptive_mask_init( + void *p_dm_void +); + +void +odm_refresh_rate_adaptive_mask( + void *p_dm_void +); + +void +odm_refresh_rate_adaptive_mask_mp( + void *p_dm_void +); + +void +odm_refresh_rate_adaptive_mask_ce( + void *p_dm_void +); + +void +odm_refresh_rate_adaptive_mask_apadsl( + void *p_dm_void +); + +u8 +phydm_RA_level_decision( + void *p_dm_void, + u32 rssi, + u8 ratr_state +); + +boolean +odm_ra_state_check( + void *p_dm_void, + s32 RSSI, + boolean is_force_update, + u8 *p_ra_tr_state +); + +void +odm_refresh_basic_rate_mask( + void *p_dm_void +); +void +odm_ra_post_action_on_assoc( + void *p_dm_odm +); + +u8 +odm_find_rts_rate( + void *p_dm_void, + u8 tx_rate, + boolean is_erp_protect +); + +void +odm_update_noisy_state( + void *p_dm_void, + boolean is_noisy_state_from_c2h +); + +void +phydm_update_pwr_track( + void *p_dm_void, + u8 rate +); + +u64 +phydm_get_rate_bitmap_ex( + void *p_dm_void, + u32 macid, + u64 ra_mask, + u8 rssi_level, + u64 *dm_ra_mask, + u8 *dm_rte_id +); +u32 +odm_get_rate_bitmap( + void *p_dm_void, + u32 macid, + u32 ra_mask, + u8 rssi_level +); + +void phydm_ra_rssi_rpt_wk(void *p_context); + +#endif /*#ifndef __ODMRAINFO_H__*/ diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_reg.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_reg.h new file mode 100644 index 000000000000..bd80a8365aa8 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_reg.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/* ************************************************************ + * File Name: odm_reg.h + * + * Description: + * + * This file is for general register definition. + * + * + * ************************************************************ */ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +/* + * Register Definition + * */ + +/* MAC REG */ +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define RF_T_METER_OLD 0x24 +#define RF_T_METER_NEW 0x42 + +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +/* LTE_COEX */ +#define REG_LTECOEX_CTRL 0x07C0 +#define REG_LTECOEX_WRITE_DATA 0x07C4 +#define REG_LTECOEX_READ_DATA 0x07C8 +#define REG_LTECOEX_PATH_CONTROL 0x70 + +/* BB REG */ +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +/* RF REG */ +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 +#define ODM_RF_T_METER 0x24 +#define ODM_RF_T_METER_92D 0x42 +#define ODM_RF_T_METER_88E 0x42 +#define ODM_RF_T_METER_92E 0x42 +#define ODM_RF_T_METER_8812 0x42 +#define REG_RF_TX_GAIN_OFFSET 0x55 + +/* ant Detect Reg */ +#define ODM_DPDT 0x300 + +/* PSD Init */ +#define ODM_PSDREG 0x808 + +/* 92D path Div */ +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + +/* + * Bitmap Definition + * */ + +#define BIT_FA_RESET BIT(0) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_regdefine11ac.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_regdefine11ac.h new file mode 100644 index 000000000000..8bf7f12f0055 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_regdefine11ac.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +/* 2 RF REG LIST */ + +/* 2 BB REG LIST + * PAGE 8 */ +#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 +#define ODM_REG_BB_RX_PATH_11AC 0x808 +#define ODM_REG_BB_TX_PATH_11AC 0x80c +#define ODM_REG_BB_ATC_11AC 0x860 +#define ODM_REG_EDCCA_POWER_CAL 0x8dc +#define ODM_REG_DBG_RPT_11AC 0x8fc +/* PAGE 9 */ +#define ODM_REG_EDCCA_DOWN_OPT 0x900 +#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 +#define odm_adc_trigger_jaguar2 0x95C /*ADC sample mode*/ +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +#define ODM_REG_CCX_PERIOD_11AC 0x990 +#define ODM_REG_NHM_TH9_TH10_11AC 0x994 +#define ODM_REG_CLM_11AC 0x994 +#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 +#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c +#define ODM_REG_NHM_TH8_11AC 0x9a0 +#define ODM_REG_NHM_9E8_11AC 0x9e8 +#define ODM_REG_CSI_CONTENT_VALUE 0x9b4 +/* PAGE A */ +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +/* PAGE B */ +#define ODM_REG_RST_RPT_11AC 0xB58 +/* PAGE C */ +#define ODM_REG_TRMUX_11AC 0xC08 +#define ODM_REG_IGI_A_11AC 0xC50 +/* PAGE E */ +#define ODM_REG_IGI_B_11AC 0xE50 +#define ODM_REG_TRMUX_11AC_B 0xE08 +/* PAGE F */ +#define ODM_REG_CCK_CRC32_CNT_11AC 0xF04 +#define ODM_REG_CCK_CCA_CNT_11AC 0xF08 +#define ODM_REG_VHT_CRC32_CNT_11AC 0xF0c +#define ODM_REG_HT_CRC32_CNT_11AC 0xF10 +#define ODM_REG_OFDM_CRC32_CNT_11AC 0xF14 +#define ODM_REG_OFDM_FA_11AC 0xF48 +#define ODM_REG_RPT_11AC 0xfa0 +#define ODM_REG_CLM_RESULT_11AC 0xfa4 +#define ODM_REG_NHM_CNT_11AC 0xfa8 +#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 + +#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac +#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 +#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +/* PAGE 18 */ +#define ODM_REG_IGI_C_11AC 0x1850 +/* PAGE 1A */ +#define ODM_REG_IGI_D_11AC 0x1A50 + +/* 2 MAC REG LIST */ +#define ODM_REG_RESP_TX_11AC 0x6D8 + +/* DIG Related */ +#define ODM_BIT_IGI_11AC 0xFFFFFFFF +#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT(16) +#define ODM_BIT_BB_RX_PATH_11AC 0xF +#define ODM_BIT_BB_TX_PATH_11AC 0xF +#define ODM_BIT_BB_ATC_11AC BIT(14) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_regdefine11n.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_regdefine11n.h new file mode 100644 index 000000000000..58040b9689a7 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_regdefine11n.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + +/* 2 RF REG LIST */ +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 + +/* 2 BB REG LIST + * PAGE 8 */ +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C +#define ODM_REG_RX_DEFUALT_A_11N 0x858 +#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_CCX_PERIOD_11N 0x894 +#define ODM_REG_NHM_TH9_TH10_11N 0x890 +#define ODM_REG_CLM_11N 0x890 +#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 +#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c +#define ODM_REG_NHM_TH8_11N 0xe28 +#define ODM_REG_CLM_READY_11N 0x8b4 +#define ODM_REG_CLM_RESULT_11N 0x8d0 +#define ODM_REG_NHM_CNT_11N 0x8d8 + +/* For struct _ACS_, Jeffery, 2014-12-26 */ +#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc +#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 +#define ODM_REG_NHM_CNT10_TO_CNT11_11N 0x8d4 + +/* PAGE 9 */ +#define ODM_REG_BB_CTRL_PAGE9_11N 0x900 +#define ODM_REG_DBG_RPT_11N 0x908 +#define ODM_REG_BB_TX_PATH_11N 0x90c +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 +#define ODM_REG_RX_DFIR_MOD_97F 0x948 + +/* PAGE A */ +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_ANT_SEL_11N 0xA04 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +/* PAGE B */ +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +#define ODM_REG_RXCK_RFMOD 0xBB0 +#define ODM_REG_EDCCA_DCNF_97F 0xBC0 + +/* PAGE C */ +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_BB_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_DOWNSAM_FACTOR_11N 0xC10 +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_L1SBD_PD_CH_11N 0XC6C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_BB_AGC_SET_2_11N 0xc74 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_SMALL_BANDWIDTH_11N 0xCE4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +/* PAGE D */ +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_BB_RX_ANT_11N 0xD04 +#define ODM_REG_BB_ATC_11N 0xD2C +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +#define ODM_REG_RPT_11N 0xDF4 +/* PAGE E */ +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_EDCCA_DCNF_11N 0xE24 +#define ODM_REG_TAP_UPD_97F 0xE24 +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_PAGE_B1_97F 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC +/* PAGE F */ +#define ODM_REG_PAGE_F_RST_11N 0xF14 +#define ODM_REG_IGI_C_11N 0xF84 +#define ODM_REG_IGI_D_11N 0xF88 +#define ODM_REG_CCK_CRC32_ERROR_CNT_11N 0xF84 +#define ODM_REG_CCK_CRC32_OK_CNT_11N 0xF88 +#define ODM_REG_HT_CRC32_CNT_11N 0xF90 +#define ODM_REG_OFDM_CRC32_CNT_11N 0xF94 + +/* 2 MAC REG LIST */ +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + +/* DIG Related */ +#define ODM_BIT_IGI_11N 0x0000007F +#define ODM_BIT_CCK_RPT_FORMAT_11N BIT(9) +#define ODM_BIT_BB_RX_PATH_11N 0xF +#define ODM_BIT_BB_TX_PATH_11N 0xF +#define ODM_BIT_BB_ATC_11N BIT(11) + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/phydm_types.h b/drivers/staging/rtl8821ce/hal/phydm/phydm_types.h new file mode 100644 index 000000000000..4aa26415a6f0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/phydm_types.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + +/*Define Different SW team support*/ +#define ODM_AP 0x01 /*BIT0*/ +#define ODM_CE 0x04 /*BIT2*/ +#define ODM_WIN 0x08 /*BIT3*/ +#define ODM_ADSL 0x10 /*BIT4*/ +#define ODM_IOT 0x20 /*BIT5*/ + +/*Deifne HW endian support*/ +#define ODM_ENDIAN_BIG 0 +#define ODM_ENDIAN_LITTLE 1 + +#define GET_PDM_ODM(__padapter) ((struct PHY_DM_STRUCT*)(&((GET_HAL_DATA(__padapter))->odmpriv))) + +#define RT_PCI_INTERFACE 1 +#define RT_USB_INTERFACE 2 +#define RT_SDIO_INTERFACE 3 + +enum hal_status { + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, + /*RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED,*/ +}; + +/* + * Declare for ODM spin lock defintion temporarily fro compile pass. + * */ +enum rt_spinlock_type { + RT_TX_SPINLOCK = 1, + RT_RX_SPINLOCK = 2, + RT_RM_SPINLOCK = 3, + RT_CAM_SPINLOCK = 4, + RT_SCAN_SPINLOCK = 5, + RT_LOG_SPINLOCK = 7, + RT_BW_SPINLOCK = 8, + RT_CHNLOP_SPINLOCK = 9, + RT_RF_OPERATE_SPINLOCK = 10, + RT_INITIAL_SPINLOCK = 11, + RT_RF_STATE_SPINLOCK = 12, /* For RF state. Added by Bruce, 2007-10-30. */ + /* Shall we define Ndis 6.2 SpinLock Here ? */ + RT_PORT_SPINLOCK = 16, + RT_VNIC_SPINLOCK = 17, + RT_HVL_SPINLOCK = 18, + RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */ + + rt_bt_data_spinlock = 25, + + RT_WAPI_OPTION_SPINLOCK = 26, + RT_WAPI_RX_SPINLOCK = 27, + + /* add for 92D CCK control issue */ + RT_CCK_PAGEA_SPINLOCK = 28, + RT_BUFFER_SPINLOCK = 29, + RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, + RT_GEN_TEMP_BUF_SPINLOCK = 31, + RT_AWB_SPINLOCK = 32, + RT_FW_PS_SPINLOCK = 33, + RT_HW_TIMER_SPIN_LOCK = 34, + RT_MPT_WI_SPINLOCK = 35, + RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */ + RT_DBG_SPIN_LOCK = 37, + RT_IQK_SPINLOCK = 38, + RT_PENDED_OID_SPINLOCK = 39, + RT_CHNLLIST_SPINLOCK = 40, + RT_INDIC_SPINLOCK = 41, /* protect indication */ + RT_RFD_SPINLOCK = 42, + RT_SYNC_IO_CNT_SPINLOCK = 43, + RT_LAST_SPINLOCK, +}; + +#include <drv_types.h> +#define DEV_BUS_TYPE RT_PCI_INTERFACE + +#ifdef __LITTLE_ENDIAN +#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE +#else +#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG +#endif + +#define boolean bool + +#define true _TRUE +#define false _FALSE + +#define SET_TX_DESC_ANTSEL_A_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 24, 1, __value) +#define SET_TX_DESC_ANTSEL_B_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+8, 25, 1, __value) +#define SET_TX_DESC_ANTSEL_C_88E(__ptx_desc, __value) SET_BITS_TO_LE_4BYTE(__ptx_desc+28, 29, 1, __value) + +/* define useless flag to avoid compile warning */ +#define FOR_BRAZIL_PRETEST 0 +#define FPGA_TWO_MAC_VERIFICATION 0 + +#if (defined(TESTCHIP_SUPPORT)) +#define PHYDM_TESTCHIP_SUPPORT 1 +#else +#define PHYDM_TESTCHIP_SUPPORT 0 +#endif + +#define phydm_timer_list rtw_timer_list + +#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= array_len) break; i += 2; v1 = array[i]; v2 = array[i+1]; } while (0) +#define COND_ELSE 2 +#define COND_ENDIF 3 + +#define MASKBYTE0 0xff +#define MASKBYTE1 0xff00 +#define MASKBYTE2 0xff0000 +#define MASKBYTE3 0xff000000 +#define MASKHWORD 0xffff0000 +#define MASKLWORD 0x0000ffff +#define MASKDWORD 0xffffffff +#define MASK7BITS 0x7f +#define MASK12BITS 0xfff +#define MASKH4BITS 0xf0000000 +#define MASK20BITS 0xfffff +#define MASKOFDM_D 0xffc00000 +#define MASKCCK 0x3f3f3f3f +#define RFREGOFFSETMASK 0xfffff +#define MASKH3BYTES 0xffffff00 +#define MASKL3BYTES 0x00ffffff +#define MASKBYTE2HIGHNIBBLE 0x00f00000 +#define MASKBYTE3LOWNIBBLE 0x0f000000 +#define MASKL3BYTES 0x00ffffff +#define RFREGOFFSETMASK 0xfffff + +#endif /* __ODM_TYPES_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtchnlplan.h b/drivers/staging/rtl8821ce/hal/phydm/rtchnlplan.h new file mode 100644 index 000000000000..6117a9494be5 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtchnlplan.h @@ -0,0 +1,613 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __RT_CHANNELPLAN_H__ +#define __RT_CHANNELPLAN_H__ + +enum rt_channel_domain_new { + + /* ===== Add new channel plan above this line =============== */ + + /* For new architecture we define different 2G/5G CH area for all country. */ + /* 2.4 G only */ + RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20, + RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21, + RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22, + RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23, + RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24, + /* 2.4 G + 5G type 1 */ + RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25, + RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26, + /* RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27, */ + /* ..... */ + + RT_CHANNEL_DOMAIN_MAX_NEW, + +}; + + +/* + * + * + * + +Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz + 2G 5G Ch# of 40MHz +"Albania����� AL Local Test + +"Algeria��Q�� DZ CE TCF + +"Antigua & Barbuda�w���ʮq&�ڥ��F" AG 2G_WORLD FCC TCF + +"Argentina�� AR 2G_WORLD Local Test + +"Armenia�Ȭ� AM 2G_WORLD ETSI + +"Aruba��q" AW 2G_WORLD FCC TCF + +"Australia�D�w" AU 2G_WORLD 5G_ETSI2 + +"Austria��" AT 2G_WORLD 5G_ETSI1 CE + +"Azerbaijan��� AZ 2G_WORLD CE TCF + +"Bahamas�ګ���" BS 2G_WORLD + +"Barbados�ڤڦh��" BB 2G_WORLD FCC TCF + +"Belgium��� BE 2G_WORLD 5G_ETSI1 CE + +"Bermuda�ʼ}�F" BM 2G_WORLD FCC TCF + +"Brazil�ڦ� BR 2G_WORLD Local Test + +"Bulgaria�O�[�Q�� BG 2G_WORLD 5G_ETSI1 CE + +"Canada�[���j" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC + +"Cayman Islands�}�Ҹs�q" KY 2G_WORLD 5G_ETSI1 CE + +"Chile���Q" CL 2G_WORLD FCC TCF + +"China���� CN 2G_WORLD 5G_FCC5 �H��?�i2002�j353? + +"Columbia��� CO 2G_WORLD Voluntary + +"Costa Rica��F���[" CR 2G_WORLD FCC TCF + +"Cyprus���� CY 2G_WORLD 5G_ETSI1 CE + +"Czech ���J" CZ 2G_WORLD 5G_ETSI1 CE + +"Denmark���� DK 2G_WORLD 5G_ETSI1 CE + +"Dominican Republic�h���@�M��DO 2G_WORLD FCC TCF + +"Egypt�J�� EG 2G_WORLD CE T CF + +"El Salvador����˦h" SV 2G_WORLD Voluntary + +"Estonia�R�F���� EE 2G_WORLD 5G_ETSI1 CE + +"Finland��" FI 2G_WORLD 5G_ETSI1 CE + +"France�k�� FR 5G_E TSI1 CE + +"Germany�w�� DE 2G_WORLD 5G_ETSI1 CE + +"Greece ���" GR 2G_WORLD 5G_ETSI1 CE + +"Guam��q" GU 2G_WORLD + +"Guatemala�ʦa���� GT 2G_WORLD + +"Haiti�� HT 2G_WORLD FCC TCF + +"Honduras�����Դ�" HN 2G_WORLD FCC TCF + +"Hungary�I�� HU 2G_WORLD 5G_ETSI1 CE + +"Iceland�B�q" IS 2G_WORLD 5G_ETSI1 CE + +"India�L�� 2G_WORLD 5G_FCC3 FCC/CE TCF + +"Ireland�R���" IE 2G_WORLD 5G_ETSI1 CE + +"Israel�H��" IL 5G_F CC6 CE TCF + +"Italy�q�j�Q" IT 2G_WORLD 5G_ETSI1 CE + +"Japan�饻" JP 2G_MKK1 5G_MKK1 MKK MKK + +"Korea��� KR 2G_WORLD 5G_KCC1 KCC KCC + +"Latvia�Բ��� LV 2G_WORLD 5G_ETSI1 CE + +"Lithuania�߳��{" LT 2G_WORLD 5G_ETSI1 CE + +"Luxembourg�c�˳� LU 2G_WORLD 5G_ETSI1 CE + +"Malaysia���Ӧ�" MY 2G_WORLD Local Test + +"Malta�����L" MT 2G_WORLD 5G_ETSI1 CE + +"Mexico����" MX 2G_WORLD 5G_FCC3 Local Test + +"Morocco������ MA CE TCF + +"Netherlands�� NL 2G_WORLD 5G_ETSI1 CE + +"New Zealand�æ�" NZ 2G_WORLD 5G_ETSI2 + +"Norway���� NO 2G_WORLD 5G_ETSI1 CE + +"Panama�ڮ��� " PA 2G_FCC1 Voluntary + +"Philippines����" PH 2G_WORLD FCC TCF + +"Poland�i�" PL 2G_WORLD 5G_ETSI1 CE + +"Portugal����" PT 2G_WORLD 5G_ETSI1 CE + +"Romaniaù������ RO 2G_WORLD 5G_ETSI1 CE + +"Russia�Xù��" RU 2G_WORLD 5G_ETSI3 CE TCF + +"Saudi Arabia�F�a�� SA 2G_WORLD CE TCF + +"Singapore�s�[�Y" SG 2G_WORLD + +"Slovakia������" SK 2G_WORLD 5G_ETSI1 CE + +"Slovenia������" SI 2G_WORLD 5G_ETSI1 CE + +"South Africa�n�D" ZA 2G_WORLD CE TCF + +"Spain���� ES 5G_ETSI1 CE + +"Sweden��" SE 2G_WORLD 5G_ETSI1 CE + +"Switzerland��" CH 2G_WORLD 5G_ETSI1 CE + +"Taiwan�O�" TW 2G_FCC1 5G_NCC1 NCC + +"Thailand�� TH 2G_WORLD FCC/CE TCF + +"Turkey�g�ը� TR 2G_WORLD + +"Ukraine�Q�J�" UA 2G_WORLD Local Test + +"United Kingdom�^�� GB 2G_WORLD 5G_ETSI1 CE ETSI + +"United States�� US 2G_FCC1 5G_FCC7 FCC FCC + +"Venezuela�e����" VE 2G_WORLD 5G_FCC4 FCC TCF + +"Vietnam�V�n" VN 2G_WORLD FCC/CE TCF + +*/ + +/* counter abbervation. */ +enum rt_country_name { + RT_CTRY_AL, /* "Albania����� */ + RT_CTRY_DZ, /* "Algeria��Q�� */ + RT_CTRY_AG, /* "Antigua & Barbuda�w���ʮq&�ڥ��F" */ + RT_CTRY_AR, /* "Argentina�� */ + RT_CTRY_AM, /* "Armenia�Ȭ� */ + RT_CTRY_AW, /* "Aruba��q" */ + RT_CTRY_AU, /* "Australia�D�w" */ + RT_CTRY_AT, /* "Austria��" */ + RT_CTRY_AZ, /* "Azerbaijan��� */ + RT_CTRY_BS, /* "Bahamas�ګ���" */ + RT_CTRY_BB, /* "Barbados�ڤڦh��" */ + RT_CTRY_BE, /* "Belgium��� */ + RT_CTRY_BM, /* "Bermuda�ʼ}�F" */ + RT_CTRY_BR, /* "Brazil�ڦ�*/ + RT_CTRY_BG, /* "Bulgaria�O�[�Q�� */ + RT_CTRY_CA, /* "Canada�[���j" */ + RT_CTRY_KY, /* "Cayman Islands�}�Ҹs�q" */ + RT_CTRY_CL, /* "Chile���Q" */ + RT_CTRY_CN, /* "China����*/ + RT_CTRY_CO, /* "Columbia��� */ + RT_CTRY_CR, /* "Costa Rica��F���[" */ + RT_CTRY_CY, /* "Cyprus���� */ + RT_CTRY_CZ, /* "Czech ���J" */ + RT_CTRY_DK, /* "Denmark���� */ + RT_CTRY_DO, /* "Dominican Republic�h���@�M��*/ + RT_CTRY_CE, /* "Egypt�J�� EG 2G_WORLD */ + RT_CTRY_SV, /* "El Salvador����˦h" */ + RT_CTRY_EE, /* "Estonia�R�F���� */ + RT_CTRY_FI, /* "Finland��" */ + RT_CTRY_FR, /* "France�k��*/ + RT_CTRY_DE, /* "Germany�w��*/ + RT_CTRY_GR, /* "Greece ���" */ + RT_CTRY_GU, /* "Guam��q" */ + RT_CTRY_GT, /* "Guatemala�ʦa���� */ + RT_CTRY_HT, /* "Haiti��/ + RT_CTRY_HN, /* "Honduras�����Դ�" */ + RT_CTRY_HU, /* "Hungary�I��*/ + RT_CTRY_IS, /* "Iceland�B�q" */ + RT_CTRY_IN, /* "India�L�� */ + RT_CTRY_IE, /* "Ireland�R���" */ + RT_CTRY_IL, /* "Israel�H��" */ + RT_CTRY_IT, /* "Italy�q�j�Q" */ + RT_CTRY_JP, /* "Japan�饻" */ + RT_CTRY_KR, /* "Korea���*/ + RT_CTRY_LV, /* "Latvia�Բ��� */ + RT_CTRY_LT, /* "Lithuania�߳��{" */ + RT_CTRY_LU, /* "Luxembourg�c�˳� + RT_CTRY_MY, /* "Malaysia���Ӧ�" */ + RT_CTRY_MT, /* "Malta�����L" */ + RT_CTRY_MX, /* "Mexico����" */ + RT_CTRY_MA, /* "Morocco������/ + RT_CTRY_NL, /* "Netherlands��/ + RT_CTRY_NZ, /* "New Zealand�æ�" */ + RT_CTRY_NO, /* "Norway���� */ + RT_CTRY_PA, /* "Panama�ڮ��� " */ + RT_CTRY_PH, /* "Philippines����" */ + RT_CTRY_PL, /* "Poland�i�" */ + RT_CTRY_PT, /* "Portugal����" */ + RT_CTRY_RO, /* "Romaniaù������ */ + RT_CTRY_RU, /* "Russia�Xù��" */ + RT_CTRY_SA, /* "Saudi Arabia�F�a�� */ + RT_CTRY_SG, /* "Singapore�s�[�Y" */ + RT_CTRY_SK, /* "Slovakia������" */ + RT_CTRY_SI, /* "Slovenia������" */ + RT_CTRY_ZA, /* "South Africa�n�D" */ + RT_CTRY_ES, /* "Spain���� + RT_CTRY_SE, /* "Sweden��" */ + RT_CTRY_CH, /* "Switzerland��" */ + RT_CTRY_TW, /* "Taiwan�O�" */ + RT_CTRY_TH, /* "Thailand�� */ + RT_CTRY_TR, /* "Turkey�g�ը�*/ + RT_CTRY_UA, /* "Ukraine�Q�J�" */ + RT_CTRY_GB, /* "United Kingdom�^��*/ + RT_CTRY_US, /* "United States��/ + RT_CTRY_VE, /* "Venezuela�e����" */ + RT_CTRY_VN, /* "Vietnam�V�n" */ + RT_CTRY_MAX, + +}; + +/* Scan type including active and passive scan. */ +enum rt_scan_type_new { + SCAN_NULL, + SCAN_ACT, + SCAN_PAS, + SCAN_BOTH, +}; + +/* Power table sample. */ + +struct _RT_CHNL_PLAN_LIMIT { + u16 chnl_start; + u16 chnl_end; + + u16 freq_start; + u16 freq_end; +}; + +/* + * 2.4G Regulatory Domains + * */ +enum rt_regulation_2g { + RT_2G_NULL, + RT_2G_WORLD, + RT_2G_ETSI1, + RT_2G_FCC1, + RT_2G_MKK1, + RT_2G_ETSI2 + +}; + +/* typedef struct _RT_CHANNEL_BEHAVIOR + * { + * u8 chnl; + * enum rt_scan_type_new + * + * }RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; */ + +/* typedef struct _RT_CHANNEL_PLAN_TYPE + * { + * RT_CHANNEL_BEHAVIOR + * u8 Chnl_num; + * }RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; */ + +/* + * 2.4G channel number + * channel definition & number + * */ +#define CHNL_RT_2G_NULL \ + {0}, 0 +#define CHNL_RT_2G_WORLD \ + {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13 +#define CHNL_RT_2G_WORLD_TEST \ + {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13 + +#define CHNL_RT_2G_EFSI1 \ + {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13 +#define CHNL_RT_2G_FCC1 \ + {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11 +#define CHNL_RT_2G_MKK1 \ + {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14 +#define CHNL_RT_2G_ETSI2 \ + {10, 11, 12, 13}, 4 + +/* + * 2.4G channel active or passive scan. + * */ +#define CHNL_RT_2G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_2G_WORLD_SCAN_TYPE \ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0} +#define CHNL_RT_2G_EFSI1_SCAN_TYPE \ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} +#define CHNL_RT_2G_FCC1_SCAN_TYPE \ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} +#define CHNL_RT_2G_MKK1_SCAN_TYPE \ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} +#define CHNL_RT_2G_ETSI2_SCAN_TYPE \ + {1, 1, 1, 1} + +/* + * 2.4G band & Frequency Section + * Freqency start & end / band number + * */ +#define FREQ_RT_2G_NULL \ + {0}, 0 +/* Passive scan CH 12, 13 */ +#define FREQ_RT_2G_WORLD \ + {2412, 2472}, 1 +#define FREQ_RT_2G_EFSI1 \ + {2412, 2472}, 1 +#define FREQ_RT_2G_FCC1 \ + {2412, 2462}, 1 +#define FREQ_RT_2G_MKK1 \ + {2412, 2484}, 1 +#define FREQ_RT_2G_ETSI2 \ + {2457, 2472}, 1 + +/* + * 5G Regulatory Domains + * */ +enum rt_regulation_5g { + RT_5G_NULL, + RT_5G_WORLD, + RT_5G_ETSI1, + RT_5G_ETSI2, + RT_5G_ETSI3, + RT_5G_FCC1, + RT_5G_FCC2, + RT_5G_FCC3, + RT_5G_FCC4, + RT_5G_FCC5, + RT_5G_FCC6, + RT_5G_FCC7, + RT_5G_IC1, + RT_5G_KCC1, + RT_5G_MKK1, + RT_5G_MKK2, + RT_5G_MKK3, + RT_5G_NCC1, + +}; + +/* + * 5G channel number + * */ +#define CHNL_RT_5G_NULL \ + {0}, 0 +#define CHNL_RT_5G_WORLD \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19 +#define CHNL_RT_5G_ETSI1 \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24 +#define CHNL_RT_5G_ETSI2 \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22 +#define CHNL_RT_5G_ETSI3 \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24 +#define CHNL_RT_5G_FCC1 \ + {36, 40, 44, 48, 149, 153, 157, 161, 165}, 9 +#define CHNL_RT_5G_FCC2 \ + {36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13 +#define CHNL_RT_5G_FCC3 \ + {36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12 +#define CHNL_RT_5G_FCC4 \ + {149, 153, 157, 161, 165}, 5 +#define CHNL_RT_5G_FCC5 \ + {36, 40, 44, 48, 52, 56, 60, 64}, 8 +#define CHNL_RT_5G_FCC6 \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20 +#define CHNL_RT_5G_FCC7 \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20 +#define CHNL_RT_5G_IC1 \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20 +#define CHNL_RT_5G_KCC1 \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19 +#define CHNL_RT_5G_MKK1 \ + {36, 40, 44, 48, 52, 56, 60, 64}, 8 +#define CHNL_RT_5G_MKK2 \ + {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11 +#define CHNL_RT_5G_MKK3 \ + {56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24 +#define CHNL_RT_5G_NCC1 \ + {56, 60, 64, 149, 153, 157, 161, 165}, 8 + +/* + * 5G channel active or passive scan. + * */ +#define CHNL_RT_5G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_5G_WORLD_SCAN_TYPE \ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} +#define CHNL_RT_5G_ETSI1_SCAN_TYPE \ + {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} +#define CHNL_RT_5G_ETSI2_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22 +#define CHNL_RT_5G_ETSI3_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24 +#define CHNL_RT_5G_FCC1_SCAN_TYPE \ + {36, 40, 44, 48, 149, 153, 157, 161, 165}, 9 +#define CHNL_RT_5G_FCC2_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13 +#define CHNL_RT_5G_FCC3_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12 +#define CHNL_RT_5G_FCC4_SCAN_TYPE \ + {149, 153, 157, 161, 165}, 5 +#define CHNL_RT_5G_FCC5_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64}, 8 +#define CHNL_RT_5G_FCC6_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20 +#define CHNL_RT_5G_FCC7_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20 +#define CHNL_RT_5G_IC1_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20 +#define CHNL_RT_5G_KCC1_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19 +#define CHNL_RT_5G_MKK1_SCAN_TYPE \ + {36, 40, 44, 48, 52, 56, 60, 64}, 8 +#define CHNL_RT_5G_MKK2_SCAN_TYPE \ + {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11 +#define CHNL_RT_5G_MKK3_SCAN_TYPE \ + {56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 24 +#define CHNL_RT_5G_NCC1_SCAN_TYPE \ + {56, 60, 64, 149, 153, 157, 161, 165}, 8 + +/* + * Global regulation + * */ +enum rt_regulation_cmn { + RT_WORLD, + RT_FCC, + RT_MKK, + RT_ETSI, + RT_IC, + RT_CE, + RT_NCC, + +}; + +/* + * Special requirement for different regulation domain. + * For internal test or customerize special request. + * */ +enum rt_chnlplan_sreq { + RT_SREQ_NA = 0x0, + RT_SREQ_2G_ADHOC_11N = 0x00000001, + RT_SREQ_2G_ADHOC_11B = 0x00000002, + RT_SREQ_2G_ALL_PASS = 0x00000004, + RT_SREQ_2G_ALL_ACT = 0x00000008, + RT_SREQ_5G_ADHOC_11N = 0x00000010, + RT_SREQ_5G_ADHOC_11AC = 0x00000020, + RT_SREQ_5G_ALL_PASS = 0x00000040, + RT_SREQ_5G_ALL_ACT = 0x00000080, + RT_SREQ_C1_PLAN = 0x00000100, + RT_SREQ_C2_PLAN = 0x00000200, + RT_SREQ_C3_PLAN = 0x00000400, + RT_SREQ_C4_PLAN = 0x00000800, + RT_SREQ_NFC_ON = 0x00001000, + RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */ + +}; + +/* + * enum rt_country_name & enum rt_regulation_2g & enum rt_regulation_5g transfer table + * + * */ +struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE { + /* */ + /* Define countery domain and corresponding */ + /* */ + enum rt_country_name country_enum; + char country_name[3]; + + /* char Domain_Name[12]; */ + enum rt_regulation_2g domain_2g; + + enum rt_regulation_5g domain_5g; + + RT_CHANNEL_DOMAIN rt_ch_domain; + /* u8 Country_Area; */ + +}; + +#define RT_MAX_CHNL_NUM_2G 13 +#define RT_MAX_CHNL_NUM_5G 44 + +/* Power table sample. */ + +struct _RT_CHNL_PLAN_PWR_LIMIT { + u16 chnl_start; + u16 chnl_end; + u8 db_max; + u16 m_w_max; +}; + +#define RT_MAX_BAND_NUM 5 + +struct _RT_CHANNEL_PLAN_MAXPWR { + /* STRING_T */ + struct _RT_CHNL_PLAN_PWR_LIMIT chnl[RT_MAX_BAND_NUM]; + u8 band_useful_num; + +}; + +/* + * Power By rate Table. + * */ + +struct _RT_CHANNEL_PLAN_NEW { + /* */ + /* Define countery domain and corresponding */ + /* */ + /* char country_name[36]; */ + /* u8 country_enum; */ + + /* char Domain_Name[12]; */ + + struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE *p_ctry_transfer; + + RT_CHANNEL_DOMAIN rt_ch_domain; + + enum rt_regulation_2g domain_2g; + + enum rt_regulation_5g domain_5g; + + enum rt_regulation_cmn regulator; + + enum rt_chnlplan_sreq chnl_sreq; + + /* struct _RT_CHNL_PLAN_LIMIT RtChnl; */ + + u8 chnl_2g[MAX_CHANNEL_NUM]; /* CHNL_RT_2G_WORLD */ + u8 len_2g; + u8 chnl_2g_scan_tp[MAX_CHANNEL_NUM]; /* CHNL_RT_2G_WORLD_SCAN_TYPE */ + /* u8 Freq2G[2]; */ /* FREQ_RT_2G_WORLD */ + + u8 chnl_5g[MAX_CHANNEL_NUM]; + u8 len_5g; + u8 chnl_5g_scan_tp[MAX_CHANNEL_NUM]; + /* u8 Freq2G[2]; */ /* FREQ_RT_2G_WORLD */ + + struct _RT_CHANNEL_PLAN_MAXPWR chnl_max_pwr; + +}; + +#endif /* __RT_CHANNELPLAN_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c new file mode 100644 index 000000000000..4ebde76c27e9 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.c @@ -0,0 +1,3421 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 3.4*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +static boolean +check_positive( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 +) +{ + u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ + ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ + ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ + ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ + ((p_dm_odm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ + ((p_dm_odm->board_type & BIT(1)) >> 1) << 5; /* _NGFF*/ + + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; + + u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; + u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + + u32 driver1 = cut_version_for_para << 24 | + (p_dm_odm->support_interface & 0xF0) << 16 | + p_dm_odm->support_platform << 16 | + pkg_type_for_para << 12 | + (p_dm_odm->support_interface & 0x0F) << 8 | + _board_type; + + u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | + (p_dm_odm->type_gpa & 0xFF) << 8 | + (p_dm_odm->type_alna & 0xFF) << 16 | + (p_dm_odm->type_apa & 0xFF) << 24; + + u32 driver3 = 0; + + u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | + (p_dm_odm->type_gpa & 0xFF00) | + (p_dm_odm->type_alna & 0xFF00) << 8 | + (p_dm_odm->type_apa & 0xFF00) << 16; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type)); + + /*============== value Defined Check ===============*/ + /*QFN type [15:12] and cut version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u32 bit_mask = 0; + + if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ + return true; + + if ((cond1 & BIT(0)) != 0) /*GLNA*/ + bit_mask |= 0x000000FF; + if ((cond1 & BIT(1)) != 0) /*GPA*/ + bit_mask |= 0x0000FF00; + if ((cond1 & BIT(2)) != 0) /*ALNA*/ + bit_mask |= 0x00FF0000; + if ((cond1 & BIT(3)) != 0) /*APA*/ + bit_mask |= 0xFF000000; + + if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ + return true; + else + return false; + } else + return false; +} + +/****************************************************************************** +* agc_tab.TXT +******************************************************************************/ + +u32 array_mp_8821c_agc_tab[] = { + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000003, + 0x81C, 0xFA020003, + 0x81C, 0xF9040003, + 0x81C, 0xF8060003, + 0x81C, 0xF7080003, + 0x81C, 0xF60A0003, + 0x81C, 0xF50C0003, + 0x81C, 0xF40E0003, + 0x81C, 0xF3100003, + 0x81C, 0xF2120003, + 0x81C, 0xF1140003, + 0x81C, 0xF0160003, + 0x81C, 0xEF180003, + 0x81C, 0xEE1A0003, + 0x81C, 0xED1C0003, + 0x81C, 0xEC1E0003, + 0x81C, 0xEB200003, + 0x81C, 0xEA220003, + 0x81C, 0xE9240003, + 0x81C, 0xE8260003, + 0x81C, 0xE7280003, + 0x81C, 0xE62A0003, + 0x81C, 0xE52C0003, + 0x81C, 0xE42E0003, + 0x81C, 0xE3300003, + 0x81C, 0xE2320003, + 0x81C, 0xE1340003, + 0x81C, 0xC4360003, + 0x81C, 0xC3380003, + 0x81C, 0xC23A0003, + 0x81C, 0xC13C0003, + 0x81C, 0x883E0003, + 0x81C, 0x87400003, + 0x81C, 0x86420003, + 0x81C, 0x85440003, + 0x81C, 0x84460003, + 0x81C, 0x83480003, + 0x81C, 0x824A0003, + 0x81C, 0x814C0003, + 0x81C, 0x804E0003, + 0x81C, 0x64500003, + 0x81C, 0x63520003, + 0x81C, 0x62540003, + 0x81C, 0x61560003, + 0x81C, 0x60580003, + 0x81C, 0x475A0003, + 0x81C, 0x465C0003, + 0x81C, 0x455E0003, + 0x81C, 0x44600003, + 0x81C, 0x43620003, + 0x81C, 0x42640003, + 0x81C, 0x41660003, + 0x81C, 0x40680003, + 0x81C, 0x236A0003, + 0x81C, 0x226C0003, + 0x81C, 0x056E0003, + 0x81C, 0x04700003, + 0x81C, 0x03720003, + 0x81C, 0x02740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0xA0000000, 0x00000000, + 0x81C, 0xFB000003, + 0x81C, 0xFA020003, + 0x81C, 0xF9040003, + 0x81C, 0xF8060003, + 0x81C, 0xF7080003, + 0x81C, 0xF60A0003, + 0x81C, 0xF50C0003, + 0x81C, 0xF40E0003, + 0x81C, 0xF3100003, + 0x81C, 0xF2120003, + 0x81C, 0xF1140003, + 0x81C, 0xF0160003, + 0x81C, 0xEF180003, + 0x81C, 0xEE1A0003, + 0x81C, 0xED1C0003, + 0x81C, 0xEC1E0003, + 0x81C, 0xEB200003, + 0x81C, 0xEA220003, + 0x81C, 0xE9240003, + 0x81C, 0xE8260003, + 0x81C, 0xE7280003, + 0x81C, 0xE62A0003, + 0x81C, 0xCA2C0003, + 0x81C, 0xC92E0003, + 0x81C, 0xC8300003, + 0x81C, 0xC7320003, + 0x81C, 0xC6340003, + 0x81C, 0xC5360003, + 0x81C, 0xC4380003, + 0x81C, 0xC33A0003, + 0x81C, 0xC23C0003, + 0x81C, 0xC13E0003, + 0x81C, 0x88400003, + 0x81C, 0x87420003, + 0x81C, 0x86440003, + 0x81C, 0x85460003, + 0x81C, 0x84480003, + 0x81C, 0x834A0003, + 0x81C, 0x674C0003, + 0x81C, 0x664E0003, + 0x81C, 0x65500003, + 0x81C, 0x64520003, + 0x81C, 0x63540003, + 0x81C, 0x62560003, + 0x81C, 0x61580003, + 0x81C, 0x455A0003, + 0x81C, 0x445C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x25640003, + 0x81C, 0x24660003, + 0x81C, 0x23680003, + 0x81C, 0x226A0003, + 0x81C, 0x216C0003, + 0x81C, 0x016E0003, + 0x81C, 0x01700003, + 0x81C, 0x01720003, + 0x81C, 0x01740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0xB0000000, 0x00000000, + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEF1C0103, + 0x81C, 0xEE1E0103, + 0x81C, 0xED200103, + 0x81C, 0xEC220103, + 0x81C, 0xEB240103, + 0x81C, 0xEA260103, + 0x81C, 0xE9280103, + 0x81C, 0xE82A0103, + 0x81C, 0xE72C0103, + 0x81C, 0xE62E0103, + 0x81C, 0xE5300103, + 0x81C, 0xE4320103, + 0x81C, 0xE3340103, + 0x81C, 0xE2360103, + 0x81C, 0xE1380103, + 0x81C, 0xE03A0103, + 0x81C, 0xC33C0103, + 0x81C, 0xC23E0103, + 0x81C, 0xC1400103, + 0x81C, 0xC0420103, + 0x81C, 0xA3440103, + 0x81C, 0xA2460103, + 0x81C, 0xA1480103, + 0x81C, 0xA04A0103, + 0x81C, 0x824C0103, + 0x81C, 0x814E0103, + 0x81C, 0x80500103, + 0x81C, 0x62520103, + 0x81C, 0x61540103, + 0x81C, 0x60560103, + 0x81C, 0x24580103, + 0x81C, 0x235A0103, + 0x81C, 0x225C0103, + 0x81C, 0x215E0103, + 0x81C, 0x20600103, + 0x81C, 0x03620103, + 0x81C, 0x02640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0xA0000000, 0x00000000, + 0x81C, 0xFD000103, + 0x81C, 0xFC020103, + 0x81C, 0xFB040103, + 0x81C, 0xFA060103, + 0x81C, 0xF9080103, + 0x81C, 0xF80A0103, + 0x81C, 0xF70C0103, + 0x81C, 0xF60E0103, + 0x81C, 0xF5100103, + 0x81C, 0xF4120103, + 0x81C, 0xF3140103, + 0x81C, 0xF2160103, + 0x81C, 0xF1180103, + 0x81C, 0xF01A0103, + 0x81C, 0xEF1C0103, + 0x81C, 0xEE1E0103, + 0x81C, 0xED200103, + 0x81C, 0xEC220103, + 0x81C, 0xEB240103, + 0x81C, 0xEA260103, + 0x81C, 0xE9280103, + 0x81C, 0xE82A0103, + 0x81C, 0xE72C0103, + 0x81C, 0xE62E0103, + 0x81C, 0xE5300103, + 0x81C, 0xE4320103, + 0x81C, 0xE3340103, + 0x81C, 0xE2360103, + 0x81C, 0xE1380103, + 0x81C, 0xE03A0103, + 0x81C, 0xA83C0103, + 0x81C, 0xA73E0103, + 0x81C, 0xA6400103, + 0x81C, 0xA5420103, + 0x81C, 0xA4440103, + 0x81C, 0xA3460103, + 0x81C, 0xA2480103, + 0x81C, 0xA14A0103, + 0x81C, 0x834C0103, + 0x81C, 0x824E0103, + 0x81C, 0x81500103, + 0x81C, 0x63520103, + 0x81C, 0x62540103, + 0x81C, 0x61560103, + 0x81C, 0x25580103, + 0x81C, 0x245A0103, + 0x81C, 0x235C0103, + 0x81C, 0x225E0103, + 0x81C, 0x04600103, + 0x81C, 0x03620103, + 0x81C, 0x02640103, + 0x81C, 0x01660103, + 0x81C, 0x01680103, + 0x81C, 0x016A0103, + 0x81C, 0x016C0103, + 0x81C, 0x016E0103, + 0x81C, 0x01700103, + 0x81C, 0x01720103, + 0x81C, 0x01740103, + 0x81C, 0x01760103, + 0x81C, 0x01780103, + 0x81C, 0x017A0103, + 0x81C, 0x017C0103, + 0x81C, 0x017E0103, + 0xB0000000, 0x00000000, + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000203, + 0x81C, 0xFA020203, + 0x81C, 0xF9040203, + 0x81C, 0xF8060203, + 0x81C, 0xF7080203, + 0x81C, 0xF60A0203, + 0x81C, 0xF50C0203, + 0x81C, 0xF40E0203, + 0x81C, 0xF3100203, + 0x81C, 0xF2120203, + 0x81C, 0xF1140203, + 0x81C, 0xF0160203, + 0x81C, 0xEF180203, + 0x81C, 0xEE1A0203, + 0x81C, 0xED1C0203, + 0x81C, 0xEC1E0203, + 0x81C, 0xEB200203, + 0x81C, 0xEA220203, + 0x81C, 0xE9240203, + 0x81C, 0xE8260203, + 0x81C, 0xE7280203, + 0x81C, 0xE62A0203, + 0x81C, 0xE52C0203, + 0x81C, 0xE42E0203, + 0x81C, 0xE3300203, + 0x81C, 0xE2320203, + 0x81C, 0xE1340203, + 0x81C, 0xC5360203, + 0x81C, 0xC4380203, + 0x81C, 0xC33A0203, + 0x81C, 0xC23C0203, + 0x81C, 0xC13E0203, + 0x81C, 0xA4400203, + 0x81C, 0xA3420203, + 0x81C, 0xA2440203, + 0x81C, 0xA1460203, + 0x81C, 0xA0480203, + 0x81C, 0x834A0203, + 0x81C, 0x824C0203, + 0x81C, 0x814E0203, + 0x81C, 0x63500203, + 0x81C, 0x62520203, + 0x81C, 0x61540203, + 0x81C, 0x60560203, + 0x81C, 0x23580203, + 0x81C, 0x225A0203, + 0x81C, 0x215C0203, + 0x81C, 0x205E0203, + 0x81C, 0x04600203, + 0x81C, 0x03620203, + 0x81C, 0x02640203, + 0x81C, 0x01660203, + 0x81C, 0x01680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0xA0000000, 0x00000000, + 0x81C, 0xFC000203, + 0x81C, 0xFB020203, + 0x81C, 0xFA040203, + 0x81C, 0xF9060203, + 0x81C, 0xF8080203, + 0x81C, 0xF70A0203, + 0x81C, 0xF60C0203, + 0x81C, 0xF50E0203, + 0x81C, 0xF4100203, + 0x81C, 0xF3120203, + 0x81C, 0xF2140203, + 0x81C, 0xF1160203, + 0x81C, 0xF0180203, + 0x81C, 0xEF1A0203, + 0x81C, 0xEE1C0203, + 0x81C, 0xED1E0203, + 0x81C, 0xEC200203, + 0x81C, 0xEB220203, + 0x81C, 0xEA240203, + 0x81C, 0xE9260203, + 0x81C, 0xE8280203, + 0x81C, 0xE72A0203, + 0x81C, 0xE62C0203, + 0x81C, 0xE52E0203, + 0x81C, 0xE4300203, + 0x81C, 0xE3320203, + 0x81C, 0xE2340203, + 0x81C, 0xE1360203, + 0x81C, 0xC5380203, + 0x81C, 0xC43A0203, + 0x81C, 0xC33C0203, + 0x81C, 0xC23E0203, + 0x81C, 0xA6400203, + 0x81C, 0xA5420203, + 0x81C, 0xA4440203, + 0x81C, 0xA3460203, + 0x81C, 0xA2480203, + 0x81C, 0x844A0203, + 0x81C, 0x834C0203, + 0x81C, 0x824E0203, + 0x81C, 0x64500203, + 0x81C, 0x63520203, + 0x81C, 0x62540203, + 0x81C, 0x61560203, + 0x81C, 0x60580203, + 0x81C, 0x235A0203, + 0x81C, 0x225C0203, + 0x81C, 0x215E0203, + 0x81C, 0x04600203, + 0x81C, 0x03620203, + 0x81C, 0x02640203, + 0x81C, 0x01660203, + 0x81C, 0x01680203, + 0x81C, 0x016A0203, + 0x81C, 0x016C0203, + 0x81C, 0x016E0203, + 0x81C, 0x01700203, + 0x81C, 0x01720203, + 0x81C, 0x01740203, + 0x81C, 0x01760203, + 0x81C, 0x01780203, + 0x81C, 0x017A0203, + 0x81C, 0x017C0203, + 0x81C, 0x017E0203, + 0xB0000000, 0x00000000, + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000303, + 0x81C, 0xFA020303, + 0x81C, 0xF9040303, + 0x81C, 0xF8060303, + 0x81C, 0xF7080303, + 0x81C, 0xF60A0303, + 0x81C, 0xF50C0303, + 0x81C, 0xF40E0303, + 0x81C, 0xF3100303, + 0x81C, 0xF2120303, + 0x81C, 0xF1140303, + 0x81C, 0xF0160303, + 0x81C, 0xEF180303, + 0x81C, 0xEE1A0303, + 0x81C, 0xED1C0303, + 0x81C, 0xEC1E0303, + 0x81C, 0xEB200303, + 0x81C, 0xEA220303, + 0x81C, 0xE9240303, + 0x81C, 0xE8260303, + 0x81C, 0xE7280303, + 0x81C, 0xE62A0303, + 0x81C, 0xE52C0303, + 0x81C, 0xE42E0303, + 0x81C, 0xE3300303, + 0x81C, 0xE2320303, + 0x81C, 0xE1340303, + 0x81C, 0xC4360303, + 0x81C, 0xC3380303, + 0x81C, 0xC23A0303, + 0x81C, 0xC13C0303, + 0x81C, 0xA53E0303, + 0x81C, 0xA4400303, + 0x81C, 0xA3420303, + 0x81C, 0xA2440303, + 0x81C, 0xA1460303, + 0x81C, 0x83480303, + 0x81C, 0x824A0303, + 0x81C, 0x814C0303, + 0x81C, 0x644E0303, + 0x81C, 0x63500303, + 0x81C, 0x62520303, + 0x81C, 0x61540303, + 0x81C, 0x60560303, + 0x81C, 0x23580303, + 0x81C, 0x225A0303, + 0x81C, 0x215C0303, + 0x81C, 0x045E0303, + 0x81C, 0x03600303, + 0x81C, 0x02620303, + 0x81C, 0x01640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0xA0000000, 0x00000000, + 0x81C, 0xFC000303, + 0x81C, 0xFB020303, + 0x81C, 0xFA040303, + 0x81C, 0xF9060303, + 0x81C, 0xF8080303, + 0x81C, 0xF70A0303, + 0x81C, 0xF60C0303, + 0x81C, 0xF50E0303, + 0x81C, 0xF4100303, + 0x81C, 0xF3120303, + 0x81C, 0xF2140303, + 0x81C, 0xF1160303, + 0x81C, 0xF0180303, + 0x81C, 0xEF1A0303, + 0x81C, 0xEE1C0303, + 0x81C, 0xED1E0303, + 0x81C, 0xEC200303, + 0x81C, 0xEB220303, + 0x81C, 0xEA240303, + 0x81C, 0xE9260303, + 0x81C, 0xE8280303, + 0x81C, 0xE72A0303, + 0x81C, 0xE62C0303, + 0x81C, 0xE52E0303, + 0x81C, 0xE4300303, + 0x81C, 0xE3320303, + 0x81C, 0xE2340303, + 0x81C, 0xE1360303, + 0x81C, 0xC4380303, + 0x81C, 0xC33A0303, + 0x81C, 0xC23C0303, + 0x81C, 0xC13E0303, + 0x81C, 0xA5400303, + 0x81C, 0xA4420303, + 0x81C, 0xA3440303, + 0x81C, 0xA2460303, + 0x81C, 0xA1480303, + 0x81C, 0x834A0303, + 0x81C, 0x824C0303, + 0x81C, 0x814E0303, + 0x81C, 0x64500303, + 0x81C, 0x63520303, + 0x81C, 0x62540303, + 0x81C, 0x61560303, + 0x81C, 0x24580303, + 0x81C, 0x235A0303, + 0x81C, 0x225C0303, + 0x81C, 0x215E0303, + 0x81C, 0x04600303, + 0x81C, 0x03620303, + 0x81C, 0x02640303, + 0x81C, 0x01660303, + 0x81C, 0x01680303, + 0x81C, 0x016A0303, + 0x81C, 0x016C0303, + 0x81C, 0x016E0303, + 0x81C, 0x01700303, + 0x81C, 0x01720303, + 0x81C, 0x01740303, + 0x81C, 0x01760303, + 0x81C, 0x01780303, + 0x81C, 0x017A0303, + 0x81C, 0x017C0303, + 0x81C, 0x017E0303, + 0xB0000000, 0x00000000, + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFC000803, + 0x81C, 0xFB020803, + 0x81C, 0xFA040803, + 0x81C, 0xF9060803, + 0x81C, 0xF8080803, + 0x81C, 0xF70A0803, + 0x81C, 0xF60C0803, + 0x81C, 0xF50E0803, + 0x81C, 0xF4100803, + 0x81C, 0xF3120803, + 0x81C, 0xF2140803, + 0x81C, 0xF1160803, + 0x81C, 0xF0180803, + 0x81C, 0xEF1A0803, + 0x81C, 0xEE1C0803, + 0x81C, 0xED1E0803, + 0x81C, 0xB5200803, + 0x81C, 0xB4220803, + 0x81C, 0xB3240803, + 0x81C, 0xB2260803, + 0x81C, 0xB1280803, + 0x81C, 0xB02A0803, + 0x81C, 0xAF2C0803, + 0x81C, 0xAE2E0803, + 0x81C, 0xAD300803, + 0x81C, 0xAC320803, + 0x81C, 0xAB340803, + 0x81C, 0xAA360803, + 0x81C, 0xA9380803, + 0x81C, 0xA83A0803, + 0x81C, 0xA73C0803, + 0x81C, 0xA63E0803, + 0x81C, 0x88400803, + 0x81C, 0x87420803, + 0x81C, 0x86440803, + 0x81C, 0x85460803, + 0x81C, 0x84480803, + 0x81C, 0x834A0803, + 0x81C, 0x674C0803, + 0x81C, 0x664E0803, + 0x81C, 0x65500803, + 0x81C, 0x64520803, + 0x81C, 0x63540803, + 0x81C, 0x62560803, + 0x81C, 0x61580803, + 0x81C, 0x455A0803, + 0x81C, 0x445C0803, + 0x81C, 0x435E0803, + 0x81C, 0x42600803, + 0x81C, 0x41620803, + 0x81C, 0x25640803, + 0x81C, 0x24660803, + 0x81C, 0x23680803, + 0x81C, 0x226A0803, + 0x81C, 0x216C0803, + 0x81C, 0x016E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0xA0000000, 0x00000000, + 0x81C, 0xFC000803, + 0x81C, 0xFB020803, + 0x81C, 0xFA040803, + 0x81C, 0xF9060803, + 0x81C, 0xF8080803, + 0x81C, 0xF70A0803, + 0x81C, 0xF60C0803, + 0x81C, 0xF50E0803, + 0x81C, 0xF4100803, + 0x81C, 0xF3120803, + 0x81C, 0xF2140803, + 0x81C, 0xF1160803, + 0x81C, 0xF0180803, + 0x81C, 0xEF1A0803, + 0x81C, 0xEE1C0803, + 0x81C, 0xED1E0803, + 0x81C, 0xB5200803, + 0x81C, 0xB4220803, + 0x81C, 0xB3240803, + 0x81C, 0xB2260803, + 0x81C, 0xB1280803, + 0x81C, 0xB02A0803, + 0x81C, 0xAF2C0803, + 0x81C, 0xAE2E0803, + 0x81C, 0xAD300803, + 0x81C, 0xAC320803, + 0x81C, 0xAB340803, + 0x81C, 0xAA360803, + 0x81C, 0xA9380803, + 0x81C, 0xA83A0803, + 0x81C, 0xA73C0803, + 0x81C, 0xA63E0803, + 0x81C, 0x88400803, + 0x81C, 0x87420803, + 0x81C, 0x86440803, + 0x81C, 0x85460803, + 0x81C, 0x84480803, + 0x81C, 0x834A0803, + 0x81C, 0x674C0803, + 0x81C, 0x664E0803, + 0x81C, 0x65500803, + 0x81C, 0x64520803, + 0x81C, 0x63540803, + 0x81C, 0x62560803, + 0x81C, 0x61580803, + 0x81C, 0x455A0803, + 0x81C, 0x445C0803, + 0x81C, 0x435E0803, + 0x81C, 0x42600803, + 0x81C, 0x41620803, + 0x81C, 0x25640803, + 0x81C, 0x24660803, + 0x81C, 0x23680803, + 0x81C, 0x226A0803, + 0x81C, 0x216C0803, + 0x81C, 0x016E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0xB0000000, 0x00000000, + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000913, + 0x81C, 0xFE020913, + 0x81C, 0xFD040913, + 0x81C, 0xFC060913, + 0x81C, 0xFB080913, + 0x81C, 0xFA0A0913, + 0x81C, 0xF90C0913, + 0x81C, 0xF80E0913, + 0x81C, 0xF7100913, + 0x81C, 0xF6120913, + 0x81C, 0xF5140913, + 0x81C, 0xF4160913, + 0x81C, 0xF3180913, + 0x81C, 0xF21A0913, + 0x81C, 0xF11C0913, + 0x81C, 0x941E0913, + 0x81C, 0x93200913, + 0x81C, 0x92220913, + 0x81C, 0x91240913, + 0x81C, 0x90260913, + 0x81C, 0x8F280913, + 0x81C, 0x8E2A0913, + 0x81C, 0x8D2C0913, + 0x81C, 0x8C2E0913, + 0x81C, 0x8B300913, + 0x81C, 0x8A320913, + 0x81C, 0x89340913, + 0x81C, 0x88360913, + 0x81C, 0x87380913, + 0x81C, 0x863A0913, + 0x81C, 0x853C0913, + 0x81C, 0x843E0913, + 0x81C, 0x83400913, + 0x81C, 0x82420913, + 0x81C, 0x81440913, + 0x81C, 0x07460913, + 0x81C, 0x06480913, + 0x81C, 0x054A0913, + 0x81C, 0x044C0913, + 0x81C, 0x034E0913, + 0x81C, 0x02500913, + 0x81C, 0x01520913, + 0x81C, 0x88540903, + 0x81C, 0x87560903, + 0x81C, 0x86580903, + 0x81C, 0x855A0903, + 0x81C, 0x845C0903, + 0x81C, 0x835E0903, + 0x81C, 0x82600903, + 0x81C, 0x81620903, + 0x81C, 0x07640903, + 0x81C, 0x06660903, + 0x81C, 0x05680903, + 0x81C, 0x046A0903, + 0x81C, 0x036C0903, + 0x81C, 0x026E0903, + 0x81C, 0x01700903, + 0x81C, 0x01720903, + 0x81C, 0x01740903, + 0x81C, 0x01760903, + 0x81C, 0x01780903, + 0x81C, 0x017A0903, + 0x81C, 0x017C0903, + 0x81C, 0x017E0903, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000913, + 0x81C, 0xFE020913, + 0x81C, 0xFD040913, + 0x81C, 0xFC060913, + 0x81C, 0xFB080913, + 0x81C, 0xFA0A0913, + 0x81C, 0xF90C0913, + 0x81C, 0xF80E0913, + 0x81C, 0xF7100913, + 0x81C, 0xF6120913, + 0x81C, 0xF5140913, + 0x81C, 0xF4160913, + 0x81C, 0xF3180913, + 0x81C, 0xF21A0913, + 0x81C, 0xF11C0913, + 0x81C, 0x941E0913, + 0x81C, 0x93200913, + 0x81C, 0x92220913, + 0x81C, 0x91240913, + 0x81C, 0x90260913, + 0x81C, 0x8F280913, + 0x81C, 0x8E2A0913, + 0x81C, 0x8D2C0913, + 0x81C, 0x8C2E0913, + 0x81C, 0x8B300913, + 0x81C, 0x8A320913, + 0x81C, 0x89340913, + 0x81C, 0x88360913, + 0x81C, 0x87380913, + 0x81C, 0x863A0913, + 0x81C, 0x853C0913, + 0x81C, 0x843E0913, + 0x81C, 0x83400913, + 0x81C, 0x82420913, + 0x81C, 0x81440913, + 0x81C, 0x07460913, + 0x81C, 0x06480913, + 0x81C, 0x054A0913, + 0x81C, 0x044C0913, + 0x81C, 0x034E0913, + 0x81C, 0x02500913, + 0x81C, 0x01520913, + 0x81C, 0x88540903, + 0x81C, 0x87560903, + 0x81C, 0x86580903, + 0x81C, 0x855A0903, + 0x81C, 0x845C0903, + 0x81C, 0x835E0903, + 0x81C, 0x82600903, + 0x81C, 0x81620903, + 0x81C, 0x07640903, + 0x81C, 0x06660903, + 0x81C, 0x05680903, + 0x81C, 0x046A0903, + 0x81C, 0x036C0903, + 0x81C, 0x026E0903, + 0x81C, 0x01700903, + 0x81C, 0x01720903, + 0x81C, 0x01740903, + 0x81C, 0x01760903, + 0x81C, 0x01780903, + 0x81C, 0x017A0903, + 0x81C, 0x017C0903, + 0x81C, 0x017E0903, + 0xB0000000, 0x00000000, + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xA0000000, 0x00000000, + 0xC50, 0x00000022, + 0xC50, 0x00000020, + 0xB0000000, 0x00000000, + +}; + +void +odm_read_and_config_mp_8821c_agc_tab( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8821c_agc_tab)/sizeof(u32); + u32 *array = array_mp_8821c_agc_tab; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_agc_tab\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_bb_agc_8821c(p_dm_odm, v1, MASKDWORD, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8821c_agc_tab(void) +{ + return 36; +} + +/****************************************************************************** +* agc_tab_diff.TXT +******************************************************************************/ + +u32 array_mp_8821c_agc_tab_diff_wlg[] = { + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFB000003, + 0x81C, 0xFA020003, + 0x81C, 0xF9040003, + 0x81C, 0xF8060003, + 0x81C, 0xF7080003, + 0x81C, 0xF60A0003, + 0x81C, 0xF50C0003, + 0x81C, 0xF40E0003, + 0x81C, 0xF3100003, + 0x81C, 0xF2120003, + 0x81C, 0xF1140003, + 0x81C, 0xF0160003, + 0x81C, 0xEF180003, + 0x81C, 0xEE1A0003, + 0x81C, 0xED1C0003, + 0x81C, 0xEC1E0003, + 0x81C, 0xEB200003, + 0x81C, 0xEA220003, + 0x81C, 0xE9240003, + 0x81C, 0xE8260003, + 0x81C, 0xE7280003, + 0x81C, 0xE62A0003, + 0x81C, 0xE52C0003, + 0x81C, 0xE42E0003, + 0x81C, 0xE3300003, + 0x81C, 0xE2320003, + 0x81C, 0xE1340003, + 0x81C, 0xC4360003, + 0x81C, 0xC3380003, + 0x81C, 0xC23A0003, + 0x81C, 0xC13C0003, + 0x81C, 0x883E0003, + 0x81C, 0x87400003, + 0x81C, 0x86420003, + 0x81C, 0x85440003, + 0x81C, 0x84460003, + 0x81C, 0x83480003, + 0x81C, 0x824A0003, + 0x81C, 0x814C0003, + 0x81C, 0x804E0003, + 0x81C, 0x64500003, + 0x81C, 0x63520003, + 0x81C, 0x62540003, + 0x81C, 0x61560003, + 0x81C, 0x60580003, + 0x81C, 0x475A0003, + 0x81C, 0x465C0003, + 0x81C, 0x455E0003, + 0x81C, 0x44600003, + 0x81C, 0x43620003, + 0x81C, 0x42640003, + 0x81C, 0x41660003, + 0x81C, 0x40680003, + 0x81C, 0x236A0003, + 0x81C, 0x226C0003, + 0x81C, 0x056E0003, + 0x81C, 0x04700003, + 0x81C, 0x03720003, + 0x81C, 0x02740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x81C, 0xFF000803, + 0x81C, 0xFE020803, + 0x81C, 0xFD040803, + 0x81C, 0xFC060803, + 0x81C, 0xFB080803, + 0x81C, 0xFA0A0803, + 0x81C, 0xF90C0803, + 0x81C, 0xF80E0803, + 0x81C, 0xF7100803, + 0x81C, 0xF6120803, + 0x81C, 0xF5140803, + 0x81C, 0xF4160803, + 0x81C, 0xF3180803, + 0x81C, 0xF21A0803, + 0x81C, 0xF11C0803, + 0x81C, 0xF01E0803, + 0x81C, 0xB7200803, + 0x81C, 0xB6220803, + 0x81C, 0xB5240803, + 0x81C, 0xB4260803, + 0x81C, 0xB3280803, + 0x81C, 0xB22A0803, + 0x81C, 0xB12C0803, + 0x81C, 0xAF2E0803, + 0x81C, 0xAE300803, + 0x81C, 0xAD320803, + 0x81C, 0xAC340803, + 0x81C, 0xAB360803, + 0x81C, 0xAA380803, + 0x81C, 0xA93A0803, + 0x81C, 0xA83C0803, + 0x81C, 0xA73E0803, + 0x81C, 0x88400803, + 0x81C, 0x87420803, + 0x81C, 0x86440803, + 0x81C, 0x85460803, + 0x81C, 0x84480803, + 0x81C, 0x834A0803, + 0x81C, 0x674C0803, + 0x81C, 0x664E0803, + 0x81C, 0x65500803, + 0x81C, 0x64520803, + 0x81C, 0x63540803, + 0x81C, 0x62560803, + 0x81C, 0x61580803, + 0x81C, 0x455A0803, + 0x81C, 0x445C0803, + 0x81C, 0x435E0803, + 0x81C, 0x42600803, + 0x81C, 0x41620803, + 0x81C, 0x25640803, + 0x81C, 0x24660803, + 0x81C, 0x23680803, + 0x81C, 0x226A0803, + 0x81C, 0x216C0803, + 0x81C, 0x016E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0xA0000000, 0x00000000, + 0x81C, 0xFB000003, + 0x81C, 0xFA020003, + 0x81C, 0xF9040003, + 0x81C, 0xF8060003, + 0x81C, 0xF7080003, + 0x81C, 0xF60A0003, + 0x81C, 0xF50C0003, + 0x81C, 0xF40E0003, + 0x81C, 0xF3100003, + 0x81C, 0xF2120003, + 0x81C, 0xF1140003, + 0x81C, 0xF0160003, + 0x81C, 0xEF180003, + 0x81C, 0xEE1A0003, + 0x81C, 0xED1C0003, + 0x81C, 0xEC1E0003, + 0x81C, 0xEB200003, + 0x81C, 0xEA220003, + 0x81C, 0xE9240003, + 0x81C, 0xE8260003, + 0x81C, 0xE7280003, + 0x81C, 0xE62A0003, + 0x81C, 0xCA2C0003, + 0x81C, 0xC92E0003, + 0x81C, 0xC8300003, + 0x81C, 0xC7320003, + 0x81C, 0xC6340003, + 0x81C, 0xC5360003, + 0x81C, 0xC4380003, + 0x81C, 0xC33A0003, + 0x81C, 0xC23C0003, + 0x81C, 0xC13E0003, + 0x81C, 0x88400003, + 0x81C, 0x87420003, + 0x81C, 0x86440003, + 0x81C, 0x85460003, + 0x81C, 0x84480003, + 0x81C, 0x834A0003, + 0x81C, 0x674C0003, + 0x81C, 0x664E0003, + 0x81C, 0x65500003, + 0x81C, 0x64520003, + 0x81C, 0x63540003, + 0x81C, 0x62560003, + 0x81C, 0x61580003, + 0x81C, 0x455A0003, + 0x81C, 0x445C0003, + 0x81C, 0x435E0003, + 0x81C, 0x42600003, + 0x81C, 0x41620003, + 0x81C, 0x25640003, + 0x81C, 0x24660003, + 0x81C, 0x23680003, + 0x81C, 0x226A0003, + 0x81C, 0x216C0003, + 0x81C, 0x016E0003, + 0x81C, 0x01700003, + 0x81C, 0x01720003, + 0x81C, 0x01740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x81C, 0xFF000803, + 0x81C, 0xFE020803, + 0x81C, 0xFD040803, + 0x81C, 0xFC060803, + 0x81C, 0xFB080803, + 0x81C, 0xFA0A0803, + 0x81C, 0xF90C0803, + 0x81C, 0xF80E0803, + 0x81C, 0xF7100803, + 0x81C, 0xF6120803, + 0x81C, 0xF5140803, + 0x81C, 0xF4160803, + 0x81C, 0xF3180803, + 0x81C, 0xF21A0803, + 0x81C, 0xF11C0803, + 0x81C, 0xF01E0803, + 0x81C, 0xB7200803, + 0x81C, 0xB6220803, + 0x81C, 0xB5240803, + 0x81C, 0xB4260803, + 0x81C, 0xB3280803, + 0x81C, 0xB22A0803, + 0x81C, 0xB12C0803, + 0x81C, 0xAF2E0803, + 0x81C, 0xAE300803, + 0x81C, 0xAD320803, + 0x81C, 0xAC340803, + 0x81C, 0xAB360803, + 0x81C, 0xAA380803, + 0x81C, 0xA93A0803, + 0x81C, 0xA83C0803, + 0x81C, 0xA73E0803, + 0x81C, 0x88400803, + 0x81C, 0x87420803, + 0x81C, 0x86440803, + 0x81C, 0x85460803, + 0x81C, 0x84480803, + 0x81C, 0x834A0803, + 0x81C, 0x674C0803, + 0x81C, 0x664E0803, + 0x81C, 0x65500803, + 0x81C, 0x64520803, + 0x81C, 0x63540803, + 0x81C, 0x62560803, + 0x81C, 0x61580803, + 0x81C, 0x455A0803, + 0x81C, 0x445C0803, + 0x81C, 0x435E0803, + 0x81C, 0x42600803, + 0x81C, 0x41620803, + 0x81C, 0x25640803, + 0x81C, 0x24660803, + 0x81C, 0x23680803, + 0x81C, 0x226A0803, + 0x81C, 0x216C0803, + 0x81C, 0x016E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0xB0000000, 0x00000000, +}; + +u32 array_mp_8821c_agc_tab_diff_btg[] = { + 0x80001000, 0x00000000, 0x40000000, 0x00000000, + 0x81C, 0xFF000013, + 0x81C, 0xFE020013, + 0x81C, 0xFD040013, + 0x81C, 0xFC060013, + 0x81C, 0xFB080013, + 0x81C, 0xFA0A0013, + 0x81C, 0xF90C0013, + 0x81C, 0xF80E0013, + 0x81C, 0xF7100013, + 0x81C, 0xF6120013, + 0x81C, 0xF5140013, + 0x81C, 0xF4160013, + 0x81C, 0xF3180013, + 0x81C, 0xF21A0013, + 0x81C, 0xF11C0013, + 0x81C, 0xF01E0013, + 0x81C, 0xEF200013, + 0x81C, 0xEE220013, + 0x81C, 0xED240013, + 0x81C, 0xEC260013, + 0x81C, 0xEB280013, + 0x81C, 0xEA2A0013, + 0x81C, 0xE92C0013, + 0x81C, 0xE82E0013, + 0x81C, 0xE7300013, + 0x81C, 0x8B320013, + 0x81C, 0x8A340013, + 0x81C, 0x89360013, + 0x81C, 0x88380013, + 0x81C, 0x873A0013, + 0x81C, 0x863C0013, + 0x81C, 0x853E0013, + 0x81C, 0x84400013, + 0x81C, 0x83420013, + 0x81C, 0x82440013, + 0x81C, 0x81460013, + 0x81C, 0x08480013, + 0x81C, 0x074A0013, + 0x81C, 0x064C0013, + 0x81C, 0x054E0013, + 0x81C, 0x04500013, + 0x81C, 0x03520013, + 0x81C, 0x88540003, + 0x81C, 0x87560003, + 0x81C, 0x86580003, + 0x81C, 0x855A0003, + 0x81C, 0x845C0003, + 0x81C, 0x835E0003, + 0x81C, 0x82600003, + 0x81C, 0x81620003, + 0x81C, 0x07640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x01720003, + 0x81C, 0x01740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x81C, 0xFF000813, + 0x81C, 0xFE020813, + 0x81C, 0xFD040813, + 0x81C, 0xFC060813, + 0x81C, 0xFB080813, + 0x81C, 0xFA0A0813, + 0x81C, 0xF90C0813, + 0x81C, 0xF80E0813, + 0x81C, 0xF7100813, + 0x81C, 0xF6120813, + 0x81C, 0xF5140813, + 0x81C, 0xF4160813, + 0x81C, 0xF3180813, + 0x81C, 0xF21A0813, + 0x81C, 0xF11C0813, + 0x81C, 0x941E0813, + 0x81C, 0x93200813, + 0x81C, 0x92220813, + 0x81C, 0x91240813, + 0x81C, 0x90260813, + 0x81C, 0x8F280813, + 0x81C, 0x8E2A0813, + 0x81C, 0x8D2C0813, + 0x81C, 0x8C2E0813, + 0x81C, 0x8B300813, + 0x81C, 0x8A320813, + 0x81C, 0x89340813, + 0x81C, 0x88360813, + 0x81C, 0x87380813, + 0x81C, 0x863A0813, + 0x81C, 0x853C0813, + 0x81C, 0x843E0813, + 0x81C, 0x83400813, + 0x81C, 0x82420813, + 0x81C, 0x81440813, + 0x81C, 0x07460813, + 0x81C, 0x06480813, + 0x81C, 0x054A0813, + 0x81C, 0x044C0813, + 0x81C, 0x034E0813, + 0x81C, 0x02500813, + 0x81C, 0x01520813, + 0x81C, 0x88540803, + 0x81C, 0x87560803, + 0x81C, 0x86580803, + 0x81C, 0x855A0803, + 0x81C, 0x845C0803, + 0x81C, 0x835E0803, + 0x81C, 0x82600803, + 0x81C, 0x81620803, + 0x81C, 0x07640803, + 0x81C, 0x06660803, + 0x81C, 0x05680803, + 0x81C, 0x046A0803, + 0x81C, 0x036C0803, + 0x81C, 0x026E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0xA0000000, 0x00000000, + 0x81C, 0xFF000013, + 0x81C, 0xFE020013, + 0x81C, 0xFD040013, + 0x81C, 0xFC060013, + 0x81C, 0xFB080013, + 0x81C, 0xFA0A0013, + 0x81C, 0xF90C0013, + 0x81C, 0xF80E0013, + 0x81C, 0xF7100013, + 0x81C, 0xF6120013, + 0x81C, 0xF5140013, + 0x81C, 0xF4160013, + 0x81C, 0xF3180013, + 0x81C, 0xF21A0013, + 0x81C, 0xF11C0013, + 0x81C, 0xF01E0013, + 0x81C, 0xEF200013, + 0x81C, 0xEE220013, + 0x81C, 0xED240013, + 0x81C, 0xEC260013, + 0x81C, 0xEB280013, + 0x81C, 0xEA2A0013, + 0x81C, 0xE92C0013, + 0x81C, 0xE82E0013, + 0x81C, 0xE7300013, + 0x81C, 0x8A320013, + 0x81C, 0x89340013, + 0x81C, 0x88360013, + 0x81C, 0x87380013, + 0x81C, 0x863A0013, + 0x81C, 0x853C0013, + 0x81C, 0x843E0013, + 0x81C, 0x83400013, + 0x81C, 0x82420013, + 0x81C, 0x81440013, + 0x81C, 0x07460013, + 0x81C, 0x06480013, + 0x81C, 0x054A0013, + 0x81C, 0x044C0013, + 0x81C, 0x034E0013, + 0x81C, 0x02500013, + 0x81C, 0x01520013, + 0x81C, 0x88540003, + 0x81C, 0x87560003, + 0x81C, 0x86580003, + 0x81C, 0x855A0003, + 0x81C, 0x845C0003, + 0x81C, 0x835E0003, + 0x81C, 0x82600003, + 0x81C, 0x81620003, + 0x81C, 0x07640003, + 0x81C, 0x06660003, + 0x81C, 0x05680003, + 0x81C, 0x046A0003, + 0x81C, 0x036C0003, + 0x81C, 0x026E0003, + 0x81C, 0x01700003, + 0x81C, 0x01720003, + 0x81C, 0x01740003, + 0x81C, 0x01760003, + 0x81C, 0x01780003, + 0x81C, 0x017A0003, + 0x81C, 0x017C0003, + 0x81C, 0x017E0003, + 0x81C, 0xFF000813, + 0x81C, 0xFE020813, + 0x81C, 0xFD040813, + 0x81C, 0xFC060813, + 0x81C, 0xFB080813, + 0x81C, 0xFA0A0813, + 0x81C, 0xF90C0813, + 0x81C, 0xF80E0813, + 0x81C, 0xF7100813, + 0x81C, 0xF6120813, + 0x81C, 0xF5140813, + 0x81C, 0xF4160813, + 0x81C, 0xF3180813, + 0x81C, 0xF21A0813, + 0x81C, 0xF11C0813, + 0x81C, 0x961E0813, + 0x81C, 0x95200813, + 0x81C, 0x94220813, + 0x81C, 0x93240813, + 0x81C, 0x92260813, + 0x81C, 0x91280813, + 0x81C, 0x8F2A0813, + 0x81C, 0x8E2C0813, + 0x81C, 0x8D2E0813, + 0x81C, 0x8C300813, + 0x81C, 0x8B320813, + 0x81C, 0x8A340813, + 0x81C, 0x89360813, + 0x81C, 0x88380813, + 0x81C, 0x873A0813, + 0x81C, 0x863C0813, + 0x81C, 0x853E0813, + 0x81C, 0x84400813, + 0x81C, 0x83420813, + 0x81C, 0x82440813, + 0x81C, 0x08460813, + 0x81C, 0x07480813, + 0x81C, 0x064A0813, + 0x81C, 0x054C0813, + 0x81C, 0x044E0813, + 0x81C, 0x03500813, + 0x81C, 0x02520813, + 0x81C, 0x89540803, + 0x81C, 0x88560803, + 0x81C, 0x87580803, + 0x81C, 0x865A0803, + 0x81C, 0x855C0803, + 0x81C, 0x845E0803, + 0x81C, 0x83600803, + 0x81C, 0x82620803, + 0x81C, 0x07640803, + 0x81C, 0x06660803, + 0x81C, 0x05680803, + 0x81C, 0x046A0803, + 0x81C, 0x036C0803, + 0x81C, 0x026E0803, + 0x81C, 0x01700803, + 0x81C, 0x01720803, + 0x81C, 0x01740803, + 0x81C, 0x01760803, + 0x81C, 0x01780803, + 0x81C, 0x017A0803, + 0x81C, 0x017C0803, + 0x81C, 0x017E0803, + 0xB0000000, 0x00000000, +}; + +void +odm_read_and_config_mp_8821c_agc_tab_diff( + struct PHY_DM_STRUCT *p_dm_odm, + u32 array[], + u32 array_len +) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_agc_tab_diff\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_bb_agc_8821c(p_dm_odm, v1, MASKDWORD, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8821c_agc_tab_diff(void) +{ + return 36; +} + +/****************************************************************************** +* phy_reg.TXT +******************************************************************************/ + +u32 array_mp_8821c_phy_reg[] = { + 0x800, 0x9020D010, + 0x804, 0x80018180, + 0x808, 0x04028211, + 0x80C, 0x13D10011, + 0x810, 0x21104255, + 0x814, 0x020C3D10, + 0x818, 0x84A10385, + 0x81C, 0x1E1E081F, + 0x820, 0x0001AAAA, + 0x824, 0x00030FE0, + 0x828, 0x0000CCCC, + 0x82C, 0x75CB7010, + 0x830, 0x79A0EA2A, + 0x834, 0x072E698A, + 0x838, 0x87766461, + 0x83C, 0x9194B2B6, + 0x840, 0x171740E0, + 0x844, 0x4D3D7CDB, + 0x848, 0x4AD0408B, + 0x84C, 0x6AFBF7A5, + 0x850, 0x28A74706, + 0x854, 0x0001520C, + 0x858, 0x4060C000, + 0x85C, 0x74010160, + 0x860, 0x68A7C321, + 0x864, 0x79F27432, + 0x868, 0x8CA7A314, + 0x86C, 0x558C2878, + 0x870, 0x55555555, + 0x874, 0x27612C2E, + 0x878, 0xC0003152, + 0x87C, 0x5C8FC000, + 0x880, 0x00000000, + 0x884, 0x00000000, + 0x888, 0x00000000, + 0x88C, 0x00000000, + 0x890, 0x00000000, + 0x894, 0x00000000, + 0x898, 0x00000000, + 0x89C, 0x00000000, + 0x8A0, 0x00000013, + 0x8A4, 0x7F7F7F7F, + 0x8A8, 0x2202033E, + 0x8AC, 0xF00F000A, + 0x8B0, 0x00000600, + 0x8B4, 0x000FC080, + 0x8B8, 0xEC0057FF, + 0x8BC, 0xACB520A3, + 0x8C0, 0xFFE04020, + 0x8C4, 0x47C00000, + 0x8C8, 0x00025165, + 0x8CC, 0x08108492, + 0x8D0, 0x0000B800, + 0x8D4, 0x860308A0, + 0x8D8, 0x290B5612, + 0x8DC, 0x00000000, + 0x8E0, 0x32D16777, + 0x8E4, 0x49092925, + 0x8E8, 0xFFFFC42C, + 0x8EC, 0x99999999, + 0x8F0, 0x00009999, + 0x8F4, 0x00D80FA1, + 0x8F8, 0x400000C0, + 0x8FC, 0x00000130, + 0x900, 0x00C00000, + 0x904, 0x0FFF0FFF, + 0x908, 0x00000000, + 0x90C, 0x13000000, + 0x910, 0x0000FC00, + 0x914, 0xC6380000, + 0x918, 0x1C1028C0, + 0x91C, 0x64B11A1C, + 0x920, 0xE0767233, + 0x924, 0x855A2500, + 0x928, 0x4AB0E4E4, + 0x92C, 0xFFFEB200, + 0x930, 0xFFFFFFFE, + 0x934, 0x001FFFFF, + 0x938, 0x00008480, + 0x93C, 0xE41C0642, + 0x940, 0x0E470430, + 0x944, 0x00000000, + 0x948, 0xAC000000, + 0x94C, 0x10000083, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0xB2010080, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x950, 0xB2010080, + 0xA0000000, 0x00000000, + 0x950, 0xF2010080, + 0xB0000000, 0x00000000, + 0x954, 0x86510080, + 0x958, 0x00000181, + 0x95C, 0x04248000, + 0x960, 0x00000000, + 0x964, 0x00000000, + 0x968, 0x00000000, + 0x96C, 0x00000000, + 0x970, 0x00001FFF, + 0x974, 0x04000FFF, + 0x978, 0x00000000, + 0x97C, 0x00000000, + 0x980, 0x00000000, + 0x984, 0x00000000, + 0x988, 0x00000000, + 0x98C, 0x23440000, + 0x990, 0x27100000, + 0x994, 0xFFFF0100, + 0x998, 0xFFFFFF5C, + 0x99C, 0xFFFFFFFF, + 0x9A0, 0x000000FF, + 0x9A4, 0x80000088, + 0x9A8, 0x0C2F0000, + 0x9AC, 0x01560000, + 0x9B0, 0x70000000, + 0x9B4, 0x00000000, + 0x9B8, 0x00000000, + 0x9BC, 0x00000000, + 0x9C0, 0x00000000, + 0x9C4, 0x00000000, + 0x9C8, 0x00000000, + 0x9CC, 0x00000000, + 0x9D0, 0x00000000, + 0x9D4, 0x00000000, + 0x9D8, 0x00000000, + 0x9DC, 0x00000000, + 0x9E0, 0x00000000, + 0x9E4, 0x02000402, + 0x9E8, 0x000022D4, + 0x9EC, 0x00000000, + 0x9F0, 0x00000000, + 0x9F4, 0x00000000, + 0x9F8, 0x00000000, + 0x9FC, 0xEFFFF7FF, + 0xA00, 0x00D040C8, + 0xA04, 0x80FF800C, + 0xA08, 0x9C838300, + 0xA0C, 0x2E20200F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0xE82C0000, + 0xA24, 0x64B80C1C, + 0xA28, 0x00008810, + 0xA2C, 0x00D20000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000107, + 0xA78, 0x00008900, + 0xA7C, 0x225B0606, + 0xA80, 0x21807532, + 0xA84, 0x80200000, + 0xA88, 0x048C0000, + 0xA8C, 0x12345678, + 0xA90, 0xABCDEF00, + 0xA94, 0x001B1B89, + 0xA98, 0x00000000, + 0xA9C, 0x00060000, + 0xAA0, 0x00000000, + 0xAA4, 0x00080000, + 0xAA8, 0xEACF0004, + 0xAAC, 0x01235667, + 0xAB0, 0x00000000, + 0xB00, 0xE1000440, + 0xB04, 0x00800000, + 0xB08, 0xFF02030B, + 0xB0C, 0x01EAA406, + 0xB10, 0x00030690, + 0xB14, 0x006000FA, + 0xB18, 0x00000002, + 0xB1C, 0x00000002, + 0xB20, 0x4B00001F, + 0xB24, 0x4E8E3E40, + 0xB28, 0x03020100, + 0xB2C, 0x07060504, + 0xB30, 0x0B0A0908, + 0xB34, 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0x5C321CA5, + 0x1B80, 0x5C321CA7, + 0x1B80, 0x00011CB5, + 0x1B80, 0x00011CB7, + 0x1B80, 0x5C321CC5, + 0x1B80, 0x5C321CC7, + 0x1B80, 0x07141CD5, + 0x1B80, 0x07141CD7, + 0x1B80, 0x54001CE5, + 0x1B80, 0x54001CE7, + 0x1B80, 0x5C311CF5, + 0x1B80, 0x5C311CF7, + 0x1B80, 0x00011D05, + 0x1B80, 0x00011D07, + 0x1B80, 0x4C981D15, + 0x1B80, 0x4C981D17, + 0x1B80, 0x4C181D25, + 0x1B80, 0x4C181D27, + 0x1B80, 0x00011D35, + 0x1B80, 0x00011D37, + 0x1B80, 0x5C321D45, + 0x1B80, 0x5C321D47, + 0x1B80, 0x62841D55, + 0x1B80, 0x62841D57, + 0x1B80, 0x66861D65, + 0x1B80, 0x66861D67, + 0x1B80, 0x6C031D75, + 0x1B80, 0x6C031D77, + 0x1B80, 0x7B201D85, + 0x1B80, 0x7B201D87, + 0x1B80, 0x7A001D95, + 0x1B80, 0x7A001D97, + 0x1B80, 0x79001DA5, + 0x1B80, 0x79001DA7, + 0x1B80, 0x7F201DB5, + 0x1B80, 0x7F201DB7, + 0x1B80, 0x7E001DC5, + 0x1B80, 0x7E001DC7, + 0x1B80, 0x7D001DD5, + 0x1B80, 0x7D001DD7, + 0x1B80, 0x09011DE5, + 0x1B80, 0x09011DE7, + 0x1B80, 0x0C011DF5, + 0x1B80, 0x0C011DF7, + 0x1B80, 0x0BA61E05, + 0x1B80, 0x0BA61E07, + 0x1B80, 0x00011E15, + 0x1B80, 0x00011E17, + 0x1B80, 0x00000006, + 0x1B80, 0x00000002, + +}; + +void +odm_read_and_config_mp_8821c_phy_reg( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8821c_phy_reg)/sizeof(u32); + u32 *array = array_mp_8821c_phy_reg; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_phy_reg\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_bb_phy_8821c(p_dm_odm, v1, MASKDWORD, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8821c_phy_reg(void) +{ + return 36; +} + +/****************************************************************************** +* phy_reg_mp.TXT +******************************************************************************/ + +u32 array_mp_8821c_phy_reg_mp[] = { + 0x810, 0x21104285, + +}; + +void +odm_read_and_config_mp_8821c_phy_reg_mp( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8821c_phy_reg_mp)/sizeof(u32); + u32 *array = array_mp_8821c_phy_reg_mp; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_phy_reg_mp\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_bb_phy_8821c(p_dm_odm, v1, MASKDWORD, v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8821c_phy_reg_mp(void) +{ + return 36; +} + +/****************************************************************************** +* phy_reg_pg.TXT +******************************************************************************/ + +u32 array_mp_8821c_phy_reg_pg[] = { + 0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638, + 0, 0, 0, 0x00000c24, 0xffffffff, 0x36363636, + 0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363636, + 0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c3c, 0xffffffff, 0x34363636, + 0, 0, 0, 0x00000c40, 0xffffffff, 0x26283032, + 0, 0, 0, 0x00000c44, 0xffffffff, 0x22222224, + 1, 0, 0, 0x00000c24, 0xffffffff, 0x34343434, + 1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032, + 1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343434, + 1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343434, + 1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830, + 1, 0, 0, 0x00000c44, 0xffffffff, 0x20202022 +}; + +void +odm_read_and_config_mp_8821c_phy_reg_pg( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8821c_phy_reg_pg)/sizeof(u32); + u32 *array = array_mp_8821c_phy_reg_pg; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_phy_reg_pg\n")); + + p_dm_odm->phy_reg_pg_version = 1; + p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < array_len; i += 6) { + u32 v1 = array[i]; + u32 v2 = array[i+1]; + u32 v3 = array[i+2]; + u32 v4 = array[i+3]; + u32 v5 = array[i+4]; + u32 v6 = array[i+5]; + + odm_config_bb_phy_reg_pg_8821c(p_dm_odm, v1, v2, v3, v4, v5, v6); + } +} + + diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h new file mode 100644 index 000000000000..45834bc46c93 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_bb.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 3.4*/ +#ifndef __INC_MP_BB_HW_IMG_8821C_H +#define __INC_MP_BB_HW_IMG_8821C_H + +/****************************************************************************** +* agc_tab.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_agc_tab(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_agc_tab(void); + +/****************************************************************************** +* agc_tab_diff.TXT +******************************************************************************/ + +extern u32 array_mp_8821c_agc_tab_diff_wlg[520]; +extern u32 array_mp_8821c_agc_tab_diff_btg[520]; +void +odm_read_and_config_mp_8821c_agc_tab_diff( + struct PHY_DM_STRUCT *p_dm_odm, + u32 array[], + u32 array_len +); +u32 odm_get_version_mp_8821c_agc_tab_diff(void); + +/****************************************************************************** +* phy_reg.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_phy_reg(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_phy_reg(void); + +/****************************************************************************** +* phy_reg_mp.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_phy_reg_mp(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_phy_reg_mp(void); + +/****************************************************************************** +* phy_reg_pg.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_phy_reg_pg(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_phy_reg_pg(void); + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h new file mode 100644 index 000000000000..20d7c2f186e8 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_fw.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#ifndef __INC_MP_FW_HW_IMG_8821C_H +#define __INC_MP_FW_HW_IMG_8821C_H + +/****************************************************************************** +* FW_AP.TXT +******************************************************************************/ + +void +odm_read_firmware_mp_8821c_fw_ap( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size +); + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +odm_read_firmware_mp_8821c_fw_nic( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size +); + +/****************************************************************************** +* FW_WoWLAN.TXT +******************************************************************************/ + +void +odm_read_firmware_mp_8821c_fw_wowlan( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *p_firmware, + u32 *p_firmware_size +); + +#endif diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c new file mode 100644 index 000000000000..6d5cb638f94e --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.c @@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +static boolean +check_positive( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 +) +{ + u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ + ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ + ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ + ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ + ((p_dm_odm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ + ((p_dm_odm->board_type & BIT(1)) >> 1) << 5; /* _NGFF*/ + + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; + + u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; + u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + + u32 driver1 = cut_version_for_para << 24 | + (p_dm_odm->support_interface & 0xF0) << 16 | + p_dm_odm->support_platform << 16 | + pkg_type_for_para << 12 | + (p_dm_odm->support_interface & 0x0F) << 8 | + _board_type; + + u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | + (p_dm_odm->type_gpa & 0xFF) << 8 | + (p_dm_odm->type_alna & 0xFF) << 16 | + (p_dm_odm->type_apa & 0xFF) << 24; + + u32 driver3 = 0; + + u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | + (p_dm_odm->type_gpa & 0xFF00) | + (p_dm_odm->type_alna & 0xFF00) << 8 | + (p_dm_odm->type_apa & 0xFF00) << 16; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type)); + + /*============== value Defined Check ===============*/ + /*QFN type [15:12] and cut version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u32 bit_mask = 0; + + if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ + return true; + + if ((cond1 & BIT(0)) != 0) /*GLNA*/ + bit_mask |= 0x000000FF; + if ((cond1 & BIT(1)) != 0) /*GPA*/ + bit_mask |= 0x0000FF00; + if ((cond1 & BIT(2)) != 0) /*ALNA*/ + bit_mask |= 0x00FF0000; + if ((cond1 & BIT(3)) != 0) /*APA*/ + bit_mask |= 0xFF000000; + + if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ + return true; + else + return false; + } else + return false; +} + +/****************************************************************************** +* mac_reg.TXT +******************************************************************************/ + +u32 array_mp_8821c_mac_reg[] = { + 0x010, 0x00000043, + 0x025, 0x0000001D, + 0x026, 0x000000CE, + 0x04F, 0x00000001, + 0x029, 0x000000F9, + 0x420, 0x00000080, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x000000F0, + 0x446, 0x00000001, + 0x447, 0x000000FE, + 0x448, 0x00000000, + 0x449, 0x00000000, + 0x44A, 0x00000000, + 0x44B, 0x00000040, + 0x44C, 0x00000010, + 0x44D, 0x000000F0, + 0x44E, 0x0000003F, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x00000000, + 0x452, 0x00000000, + 0x453, 0x00000040, + 0x455, 0x00000070, + 0x45E, 0x00000004, + 0x49C, 0x00000010, + 0x49D, 0x000000F0, + 0x49E, 0x00000000, + 0x49F, 0x00000006, + 0x4A0, 0x000000E0, + 0x4A1, 0x00000003, + 0x4A2, 0x00000000, + 0x4A3, 0x00000040, + 0x4A4, 0x00000015, + 0x4A5, 0x000000F0, + 0x4A6, 0x00000000, + 0x4A7, 0x00000006, + 0x4A8, 0x000000E0, + 0x4A9, 0x00000000, + 0x4AA, 0x00000000, + 0x4AB, 0x00000000, + 0x7DA, 0x00000008, + 0x1448, 0x00000006, + 0x144A, 0x00000006, + 0x144C, 0x00000006, + 0x144E, 0x00000006, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CA, 0x0000002B, + 0x4CB, 0x0000002B, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x4CF, 0x00000008, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x521, 0x0000002F, + 0x525, 0x0000004F, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000050, + 0x55D, 0x000000FF, + 0x577, 0x0000000B, + 0x578, 0x00000014, + 0x579, 0x00000014, + 0x57A, 0x00000014, + 0x5BE, 0x00000064, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x00000022, + 0x60C, 0x00000018, + 0x6A0, 0x000000FF, + 0x6A1, 0x000000FF, + 0x6A2, 0x000000FF, + 0x6A3, 0x000000FF, + 0x6A4, 0x000000FF, + 0x6A5, 0x000000FF, + 0x6DE, 0x00000084, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000050, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + 0x718, 0x00000040, + 0x7D4, 0x00000098, + +}; + +void +odm_read_and_config_mp_8821c_mac_reg( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8821c_mac_reg)/sizeof(u32); + u32 *array = array_mp_8821c_mac_reg; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_mac_reg\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_mac_8821c(p_dm_odm, v1, (u8)v2); + } + i = i + 2; + } +} + +u32 +odm_get_version_mp_8821c_mac_reg(void) +{ + return 36; +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h new file mode 100644 index 000000000000..761eb6f97789 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_mac.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 3.4*/ +#ifndef __INC_MP_MAC_HW_IMG_8821C_H +#define __INC_MP_MAC_HW_IMG_8821C_H + +/****************************************************************************** +* mac_reg.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_mac_reg(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_mac_reg(void); + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c new file mode 100644 index 000000000000..2fc7ba50eb8c --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.c @@ -0,0 +1,1793 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 3.4*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +static boolean +check_positive( + struct PHY_DM_STRUCT *p_dm_odm, + const u32 condition1, + const u32 condition2, + const u32 condition3, + const u32 condition4 +) +{ + u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/ + ((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/ + ((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/ + ((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */ + ((p_dm_odm->board_type & BIT(2)) >> 2) << 4 | /* _BT*/ + ((p_dm_odm->board_type & BIT(1)) >> 1) << 5; /* _NGFF*/ + + u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4; + + u8 cut_version_for_para = (p_dm_odm->cut_version == ODM_CUT_A) ? 15 : p_dm_odm->cut_version; + u8 pkg_type_for_para = (p_dm_odm->package_type == 0) ? 15 : p_dm_odm->package_type; + + u32 driver1 = cut_version_for_para << 24 | + (p_dm_odm->support_interface & 0xF0) << 16 | + p_dm_odm->support_platform << 16 | + pkg_type_for_para << 12 | + (p_dm_odm->support_interface & 0x0F) << 8 | + _board_type; + + u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 | + (p_dm_odm->type_gpa & 0xFF) << 8 | + (p_dm_odm->type_alna & 0xFF) << 16 | + (p_dm_odm->type_apa & 0xFF) << 24; + + u32 driver3 = 0; + + u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 | + (p_dm_odm->type_gpa & 0xFF00) | + (p_dm_odm->type_alna & 0xFF00) << 8 | + (p_dm_odm->type_apa & 0xFF00) << 16; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type)); + + /*============== value Defined Check ===============*/ + /*QFN type [15:12] and cut version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return false; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return false; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u32 bit_mask = 0; + + if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/ + return true; + + if ((cond1 & BIT(0)) != 0) /*GLNA*/ + bit_mask |= 0x000000FF; + if ((cond1 & BIT(1)) != 0) /*GPA*/ + bit_mask |= 0x0000FF00; + if ((cond1 & BIT(2)) != 0) /*ALNA*/ + bit_mask |= 0x00FF0000; + if ((cond1 & BIT(3)) != 0) /*APA*/ + bit_mask |= 0xFF000000; + + if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/ + return true; + else + return false; + } else + return false; +} + +/****************************************************************************** +* radioa.TXT +******************************************************************************/ + +u32 array_mp_8821c_radioa[] = { + 0x000, 0x00010000, + 0x018, 0x00010D24, + 0x0EF, 0x00080000, + 0x033, 0x00000002, + 0x03E, 0x0000003F, + 0x03F, 0x000C0F4E, + 0x033, 0x00000001, + 0x03E, 0x00000034, + 0x03F, 0x0004080E, + 0x0EF, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EF, 0x00000000, + 0x0EE, 0x00000400, + 0x033, 0x00000000, + 0x03F, 0x000005DF, + 0x0EE, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x0B1, 0x0007DBE4, + 0x0B2, 0x000225D1, + 0x0B3, 0x000FC760, + 0x0B4, 0x00099DD0, + 0x0B5, 0x000400FC, + 0x0B6, 0x000187F0, + 0x0B7, 0x00030018, + 0x0B8, 0x00080800, + 0x0B9, 0x00000000, + 0x0BA, 0x00008000, + 0x0BB, 0x00000004, + 0x0BC, 0x00040000, + 0x0BD, 0x00000000, + 0x0BE, 0x00000000, + 0x0BF, 0x00000000, + 0x0C0, 0x00000000, + 0x0C1, 0x00000000, + 0x0C2, 0x00000000, + 0x0C3, 0x00000000, + 0x0C4, 0x00002402, + 0x0C5, 0x00000009, + 0x0C6, 0x00040299, + 0x0C7, 0x00055555, + 0x0C8, 0x0000C16C, + 0x0C9, 0x0001C140, + 0x0CA, 0x00000000, + 0x0CB, 0x00000000, + 0x0CC, 0x00000000, + 0x0CD, 0x00000000, + 0x0CE, 0x00090C00, + 0x0CF, 0x0006D200, + 0x0DF, 0x00000009, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00010000, + 0x033, 0x00000058, + 0x03F, 0x0000001C, + 0x0EE, 0x00000000, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x0EE, 0x00010000, + 0x033, 0x00000058, + 0x03F, 0x0000001C, + 0x0EE, 0x00000000, + 0xA0000000, 0x00000000, + 0x0EE, 0x00010000, + 0x033, 0x00000058, + 0x03F, 0x0000002C, + 0x0EE, 0x00000000, + 0xB0000000, 0x00000000, + 0x018, 0x00010524, + 0x081, 0x0000FCC1, + 0x089, 0x00000004, + 0x08A, 0x0008A186, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x08B, 0x0006FFFC, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x08B, 0x0006FFFC, + 0xA0000000, 0x00000000, + 0x08B, 0x0007060C, + 0xB0000000, 0x00000000, + 0x08C, 0x000312C7, + 0x08D, 0x00020888, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x08E, 0x00064140, + 0xA0000000, 0x00000000, + 0x08E, 0x00064540, + 0xB0000000, 0x00000000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x08F, 0x000A8010, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x08F, 0x000A8010, + 0xA0000000, 0x00000000, + 0x08F, 0x000A8018, + 0xB0000000, 0x00000000, + 0x0DD, 0x00000020, + 0x0EF, 0x00020000, + 0x033, 0x00000007, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038000, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038000, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C000, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000006, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038080, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038080, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C080, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000005, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000380C8, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000380C8, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C0C8, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000004, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038190, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038190, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C190, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000003, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038998, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038998, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C998, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000002, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039840, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039840, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D840, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000001, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000398C4, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000398C4, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D8C4, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039930, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039930, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D930, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x0000000F, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038000, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038000, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C000, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x0000000E, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038080, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038080, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C080, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x0000000D, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000380C8, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000380C8, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C0C8, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x0000000C, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038190, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038190, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C190, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x0000000B, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038998, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038998, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C998, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x0000000A, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039840, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039840, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D840, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000009, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000398C4, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000398C4, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D8C4, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000008, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039930, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039930, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D930, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000017, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038000, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038000, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C000, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000016, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038080, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038080, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C080, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000015, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000380C8, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000380C8, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C0C8, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000014, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038190, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038190, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C190, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000013, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038998, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00038998, + 0xA0000000, 0x00000000, + 0x03E, 0x0003C998, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000012, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039840, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039840, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D840, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000011, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000398C4, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x000398C4, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D8C4, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x033, 0x00000010, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039930, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03E, 0x00039930, + 0xA0000000, 0x00000000, + 0x03E, 0x0003D930, + 0xB0000000, 0x00000000, + 0x03F, 0x000C3186, + 0x0EF, 0x00000000, + 0x0EF, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x0000000F, + 0x033, 0x00000001, + 0x03F, 0x0000000A, + 0x033, 0x00000002, + 0x03F, 0x00000005, + 0x0EF, 0x00000000, + 0x018, 0x00000401, + 0x084, 0x00001209, + 0x086, 0x000001A0, + 0x087, 0x000E8180, + 0x088, 0x00047020, + 0x0DF, 0x00008009, + 0x0EF, 0x00008000, + 0x033, 0x0000000F, + 0x03F, 0x0000003C, + 0x033, 0x0000000E, + 0x03F, 0x00000038, + 0x033, 0x0000000D, + 0x03F, 0x00000030, + 0x033, 0x0000000C, + 0x03F, 0x00000028, + 0x033, 0x0000000B, + 0x03F, 0x00000020, + 0x033, 0x0000000A, + 0x03F, 0x00000018, + 0x033, 0x00000009, + 0x03F, 0x00000010, + 0x033, 0x00000008, + 0x03F, 0x00000008, + 0x033, 0x00000007, + 0x03F, 0x0000003C, + 0x033, 0x00000006, + 0x03F, 0x00000038, + 0x033, 0x00000005, + 0x03F, 0x00000030, + 0x033, 0x00000004, + 0x03F, 0x00000028, + 0x033, 0x00000003, + 0x03F, 0x00000020, + 0x033, 0x00000002, + 0x03F, 0x00000018, + 0x033, 0x00000001, + 0x03F, 0x00000010, + 0x033, 0x00000000, + 0x03F, 0x00000008, + 0x0EF, 0x00000000, + 0x0EE, 0x00000002, + 0x033, 0x0000001E, + 0x03F, 0x00000000, + 0x033, 0x0000001C, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000006, + 0xB0000000, 0x00000000, + 0x033, 0x0000000E, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000006, + 0xB0000000, 0x00000000, + 0x033, 0x0000000C, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000006, + 0xB0000000, 0x00000000, + 0x033, 0x0000000A, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000006, + 0xB0000000, 0x00000000, + 0x033, 0x00000008, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000000, + 0xA0000000, 0x00000000, + 0x03F, 0x00000006, + 0xB0000000, 0x00000000, + 0x033, 0x00000036, + 0x03F, 0x00000000, + 0x033, 0x00000037, + 0x03F, 0x00000000, + 0x033, 0x00000034, + 0x03F, 0x00000000, + 0x033, 0x00000026, + 0x03F, 0x00000006, + 0x033, 0x00000027, + 0x03F, 0x00000006, + 0x033, 0x00000024, + 0x03F, 0x00000006, + 0x033, 0x00000022, + 0x03F, 0x00000006, + 0x033, 0x00000020, + 0x03F, 0x00000006, + 0x033, 0x00000006, + 0x03F, 0x00000000, + 0x033, 0x00000007, + 0x03F, 0x00000006, + 0x033, 0x00000004, + 0x03F, 0x00000006, + 0x033, 0x00000002, + 0x03F, 0x00000006, + 0x033, 0x00000000, + 0x03F, 0x00000006, + 0x0EE, 0x00000000, + 0x0A0, 0x000F0005, + 0x0A1, 0x0006C000, + 0x0A2, 0x0000161B, + 0x0A3, 0x000B9D3D, + 0x0AF, 0x00070000, + 0x0DE, 0x00000200, + 0x0EE, 0x00000100, + 0x033, 0x00000007, + 0x03F, 0x00000043, + 0x033, 0x00000006, + 0x03F, 0x0000007A, + 0x033, 0x00000005, + 0x03F, 0x00000041, + 0x033, 0x00000004, + 0x03F, 0x00000079, + 0x033, 0x00000003, + 0x03F, 0x00000043, + 0x033, 0x00000002, + 0x03F, 0x0000007A, + 0x033, 0x00000001, + 0x03F, 0x00000041, + 0x033, 0x00000000, + 0x03F, 0x00000079, + 0x0EE, 0x00000000, + 0x0B8, 0x00080A00, + 0x0B0, 0x000FF0FA, + 0xFFE, 0x00000000, + 0x0CA, 0x00080000, + 0x0C9, 0x0001C141, + 0xFFE, 0x00000000, + 0x0B0, 0x000FF0F8, + 0x018, 0x00018D24, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x018, 0x00010D24, + 0x01B, 0x00003A40, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0004D3A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x061, 0x0004D3A3, + 0xA0000000, 0x00000000, + 0x061, 0x0004D3A1, + 0xB0000000, 0x00000000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x062, 0x0000D303, + 0xA0000000, 0x00000000, + 0x062, 0x0000D3A3, + 0xB0000000, 0x00000000, + 0x063, 0x00000002, + 0x0EF, 0x00000200, + 0x030, 0x00000000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00001000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00002000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000331A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00003000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00004000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00005000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00006000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00007000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00008000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x00009000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x0000A000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x030, 0x0000B000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000080, + 0x033, 0x00000000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000001, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000002, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000003, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000004, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000005, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000006, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000007, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00033303, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A0, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000008, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000009, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x0000000A, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x0000000B, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x0000000C, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000313A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x0000000D, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x0000000E, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x0000000F, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000010, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000011, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x033, 0x00000012, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A3, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000333A1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x000335A3, + 0xA0000000, 0x00000000, + 0x03F, 0x000335A1, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000040, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000644, + 0x030, 0x00001412, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x030, 0x00000743, + 0x030, 0x00001412, + 0xA0000000, 0x00000000, + 0x030, 0x00000640, + 0x030, 0x00001512, + 0xB0000000, 0x00000000, + 0x030, 0x00002202, + 0x030, 0x00004000, + 0x030, 0x00005000, + 0x030, 0x00006000, + 0x0EF, 0x00000000, + 0x0EF, 0x00000800, + 0x033, 0x00000020, + 0x03F, 0x00000E42, + 0x033, 0x00000021, + 0x03F, 0x00000E45, + 0x033, 0x00000022, + 0x03F, 0x00000E48, + 0x033, 0x00000023, + 0x03F, 0x00000E68, + 0x033, 0x00000024, + 0x03F, 0x00000E6B, + 0x033, 0x00000025, + 0x03F, 0x00000EAA, + 0x033, 0x00000026, + 0x03F, 0x00000EEA, + 0x033, 0x00000027, + 0x03F, 0x00000EED, + 0x033, 0x00000028, + 0x03F, 0x00000EF0, + 0x033, 0x00000029, + 0x03F, 0x00000EF3, + 0x033, 0x0000002A, + 0x03F, 0x00000EF6, + 0x033, 0x00000060, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000E0A, + 0xA0000000, 0x00000000, + 0x03F, 0x00000E09, + 0xB0000000, 0x00000000, + 0x033, 0x00000061, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000E44, + 0xA0000000, 0x00000000, + 0x03F, 0x00000E43, + 0xB0000000, 0x00000000, + 0x033, 0x00000062, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000E47, + 0xA0000000, 0x00000000, + 0x03F, 0x00000E46, + 0xB0000000, 0x00000000, + 0x033, 0x00000063, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000E4A, + 0xA0000000, 0x00000000, + 0x03F, 0x00000E49, + 0xB0000000, 0x00000000, + 0x033, 0x00000064, + 0x03F, 0x00000E6A, + 0x033, 0x00000065, + 0x03F, 0x00000EAA, + 0x033, 0x00000066, + 0x03F, 0x00000EEB, + 0x033, 0x00000067, + 0x03F, 0x00000EEE, + 0x033, 0x00000068, + 0x03F, 0x00000EF1, + 0x033, 0x00000069, + 0x03F, 0x00000EF4, + 0x033, 0x0000006A, + 0x03F, 0x00000EF7, + 0x033, 0x000000A0, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00000E08, + 0xA0000000, 0x00000000, + 0x03F, 0x00000E09, + 0xB0000000, 0x00000000, + 0x033, 0x000000A1, + 0x03F, 0x00000E42, + 0x033, 0x000000A2, + 0x03F, 0x00000E45, + 0x033, 0x000000A3, + 0x03F, 0x00000E48, + 0x033, 0x000000A4, + 0x03F, 0x00000E69, + 0x033, 0x000000A5, + 0x03F, 0x00000EA9, + 0x033, 0x000000A6, + 0x03F, 0x00000EEA, + 0x033, 0x000000A7, + 0x03F, 0x00000EED, + 0x033, 0x000000A8, + 0x03F, 0x00000EF0, + 0x033, 0x000000A9, + 0x03F, 0x00000EF3, + 0x033, 0x000000AA, + 0x03F, 0x00000EF6, + 0x0EF, 0x00000000, + 0x0EF, 0x00000400, + 0x033, 0x00000000, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x0006AC00, + 0xA0000000, 0x00000000, + 0x03F, 0x00086A00, + 0xB0000000, 0x00000000, + 0x033, 0x00000001, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00060C00, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00060C00, + 0xA0000000, 0x00000000, + 0x03F, 0x00086A00, + 0xB0000000, 0x00000000, + 0x033, 0x00000002, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x0006AC00, + 0xA0000000, 0x00000000, + 0x03F, 0x00086A00, + 0xB0000000, 0x00000000, + 0x033, 0x00000003, + 0x03F, 0x00086A00, + 0x0EF, 0x00000000, + 0x0EF, 0x00000100, + 0x033, 0x00000000, + 0x03F, 0x00000040, + 0x033, 0x00000001, + 0x03F, 0x00000040, + 0x033, 0x00000002, + 0x03F, 0x00000040, + 0x033, 0x00000003, + 0x03F, 0x00000040, + 0x0EF, 0x00000000, + 0x0EF, 0x00040000, + 0x033, 0x00000000, + 0x03F, 0x00086A40, + 0x033, 0x00000001, + 0x03F, 0x00086A40, + 0x033, 0x00000002, + 0x03F, 0x00086A40, + 0x033, 0x00000003, + 0x03F, 0x00086A40, + 0x033, 0x00000004, + 0x03F, 0x00086A40, + 0x033, 0x00000005, + 0x03F, 0x00086A40, + 0x033, 0x00000006, + 0x03F, 0x00084A40, + 0x033, 0x00000007, + 0x03F, 0x00084A40, + 0x0EF, 0x00000000, + 0x051, 0x000801A8, + 0x052, 0x000972E3, + 0x053, 0x00008069, + 0x054, 0x00030032, + 0x055, 0x00082003, + 0x056, 0x00051CCB, + 0x057, 0x0000CFC2, + 0x058, 0x00000010, + 0x059, 0x00030000, + 0x0EF, 0x00000800, + 0x033, 0x00000000, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051429, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051429, + 0xA0000000, 0x00000000, + 0x03F, 0x00051427, + 0xB0000000, 0x00000000, + 0x033, 0x00000001, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051449, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051449, + 0xA0000000, 0x00000000, + 0x03F, 0x00051446, + 0xB0000000, 0x00000000, + 0x033, 0x00000002, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x0005144C, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x0005144C, + 0xA0000000, 0x00000000, + 0x03F, 0x00051449, + 0xB0000000, 0x00000000, + 0x033, 0x00000003, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051C66, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051C66, + 0xA0000000, 0x00000000, + 0x03F, 0x0005144C, + 0xB0000000, 0x00000000, + 0x033, 0x00000004, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051C69, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051C67, + 0xA0000000, 0x00000000, + 0x03F, 0x00051C69, + 0xB0000000, 0x00000000, + 0x033, 0x00000005, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051C6C, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051C6A, + 0xA0000000, 0x00000000, + 0x03F, 0x00051C6C, + 0xB0000000, 0x00000000, + 0x033, 0x00000006, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CE8, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051C8B, + 0xA0000000, 0x00000000, + 0x03F, 0x00051C8D, + 0xB0000000, 0x00000000, + 0x033, 0x00000007, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CEB, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CE9, + 0xA0000000, 0x00000000, + 0x03F, 0x00051CEB, + 0xB0000000, 0x00000000, + 0x033, 0x00000008, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CEE, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CEC, + 0xA0000000, 0x00000000, + 0x03F, 0x00051CEE, + 0xB0000000, 0x00000000, + 0x033, 0x00000009, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CF1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CEF, + 0xA0000000, 0x00000000, + 0x03F, 0x00051CF1, + 0xB0000000, 0x00000000, + 0x033, 0x0000000A, + 0x81001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CF4, + 0x90001000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CF1, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x03F, 0x00051CF2, + 0xA0000000, 0x00000000, + 0x03F, 0x00051CF4, + 0xB0000000, 0x00000000, + 0x0EF, 0x00000000, + 0x0EE, 0x00004000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00086E00, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x0EE, 0x00000000, + 0x0EE, 0x00002000, + 0x033, 0x00000000, + 0x03F, 0x00000000, + 0x033, 0x00000001, + 0x03F, 0x00000000, + 0x033, 0x00000002, + 0x03F, 0x00000000, + 0x033, 0x00000003, + 0x03F, 0x00000000, + 0x0EE, 0x00000000, + 0x0EE, 0x00080000, + 0x033, 0x00000000, + 0x03F, 0x00048400, + 0x033, 0x00000001, + 0x03F, 0x00048400, + 0x033, 0x00000002, + 0x03F, 0x00048400, + 0x033, 0x00000003, + 0x03F, 0x00048400, + 0x033, 0x00000004, + 0x03F, 0x00048400, + 0x033, 0x00000005, + 0x03F, 0x00048400, + 0x033, 0x00000006, + 0x03F, 0x00048400, + 0x033, 0x00000007, + 0x03F, 0x00048400, + 0x0EE, 0x00000000, + 0x070, 0x00008000, + 0x075, 0x000027DA, + 0x076, 0x00006997, + 0x077, 0x00070418, + 0x078, 0x000BB000, + 0x07D, 0x00007600, + 0x07F, 0x00000000, + 0x06A, 0x000F4C00, + 0x065, 0x00082030, + 0x0EE, 0x00008000, + 0x033, 0x00000000, + 0x03F, 0x00051427, + 0x033, 0x00000001, + 0x03F, 0x00051446, + 0x033, 0x00000002, + 0x03F, 0x00051449, + 0x033, 0x00000003, + 0x03F, 0x0005144C, + 0x033, 0x00000004, + 0x03F, 0x00051C69, + 0x033, 0x00000005, + 0x03F, 0x00051C6C, + 0x033, 0x00000006, + 0x03F, 0x00051C8D, + 0x033, 0x00000007, + 0x03F, 0x00051CEB, + 0x033, 0x00000008, + 0x03F, 0x00051CEE, + 0x033, 0x00000009, + 0x03F, 0x00051CF1, + 0x033, 0x0000000A, + 0x03F, 0x00051CF4, + 0x0EE, 0x00000000, + 0x0EF, 0x00000010, + 0x033, 0x00000000, + 0x008, 0x0009C060, + 0x033, 0x00000001, + 0x008, 0x0009C060, + 0x0EF, 0x00000000, + 0x033, 0x000000A2, + 0x0EF, 0x00080000, + 0x03E, 0x0000593F, + 0x03F, 0x000C0F4F, + 0x0EF, 0x00000000, + 0x033, 0x000000A3, + 0x0EF, 0x00080000, + 0x03E, 0x00005934, + 0x03F, 0x0005AFCF, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000024, + 0x03E, 0x0000003F, + 0x03F, 0x00060FDE, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000025, + 0x03E, 0x00000037, + 0x03F, 0x0007EFCE, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x033, 0x00000026, + 0x03E, 0x00000037, + 0x03F, 0x0005EFCE, + 0x0EF, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000004, + 0x03F, 0x00001EC1, + 0x0EE, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000005, + 0x03F, 0x00001ECF, + 0x0EE, 0x00000000, + 0x0EE, 0x00001000, + 0x033, 0x00000006, + 0x03F, 0x00001F9D, + 0x0EE, 0x00000000, + +}; + +void +odm_read_and_config_mp_8821c_radioa( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; + u8 c_cond; + boolean is_matched = true, is_skipped = false; + u32 array_len = sizeof(array_mp_8821c_radioa)/sizeof(u32); + u32 *array = array_mp_8821c_radioa; + + u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_radioa\n")); + + while ((i + 1) < array_len) { + v1 = array[i]; + v2 = array[i + 1]; + + if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/ + if (v1 & BIT(31)) {/* positive condition*/ + c_cond = (u8)((v1 & (BIT(29)|BIT(28))) >> 28); + if (c_cond == COND_ENDIF) {/*end*/ + is_matched = true; + is_skipped = false; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (c_cond == COND_ELSE) { /*else*/ + is_matched = is_skipped?false:true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT(30)) { /*negative condition*/ + if (is_skipped == false) { + if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) { + is_matched = true; + is_skipped = true; + } else { + is_matched = false; + is_skipped = false; + } + } else + is_matched = false; + } + } else { + if (is_matched) + odm_config_rf_radio_a_8821c(p_dm_odm, v1, v2); + } + i = i + 2; + } +} + +/****************************************************************************** +* txpowertrack.TXT +******************************************************************************/ + +u8 g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, +}; +u8 g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12}, +}; +u8 g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8821c[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12, 12}, + {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11, 12, 12, 12, 12, 12, 12, 12}, +}; +u8 g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8821c[] = {0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 8, 8, 9}; +u8 g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8821c[] = {0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 5, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9}; +u8 g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8821c[] = {0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 9, 9, 9}; + +void +odm_read_and_config_mp_8821c_txpowertrack( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_mp_8821c\n")); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_p, g_delta_swing_table_idx_mp_2ga_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2ga_n, g_delta_swing_table_idx_mp_2ga_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_p, g_delta_swing_table_idx_mp_2gb_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2gb_n, g_delta_swing_table_idx_mp_2gb_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p, g_delta_swing_table_idx_mp_2g_cck_a_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n, g_delta_swing_table_idx_mp_2g_cck_a_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p, g_delta_swing_table_idx_mp_2g_cck_b_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n, g_delta_swing_table_idx_mp_2g_cck_b_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE); + + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_p, g_delta_swing_table_idx_mp_5ga_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5ga_n, g_delta_swing_table_idx_mp_5ga_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_p, g_delta_swing_table_idx_mp_5gb_p_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); + odm_move_memory(p_dm_odm, p_rf_calibrate_info->delta_swing_table_idx_5gb_n, g_delta_swing_table_idx_mp_5gb_n_txpowertrack_8821c, DELTA_SWINGIDX_SIZE*3); +} + +/****************************************************************************** +* txpwr_lmt.TXT +******************************************************************************/ + +const char *array_mp_8821c_txpwr_lmt[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "24", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "16", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "30", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "34", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "34", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "32", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "16", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "34", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "34", + "FCC", "2.4G", "20M", "HT", "1T", "02", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "34", + "FCC", "2.4G", "20M", "HT", "1T", "03", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "34", + "FCC", "2.4G", "20M", "HT", "1T", "04", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "34", + "FCC", "2.4G", "20M", "HT", "1T", "05", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "34", + "FCC", "2.4G", "20M", "HT", "1T", "06", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "34", + "FCC", "2.4G", "20M", "HT", "1T", "07", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "34", + "FCC", "2.4G", "20M", "HT", "1T", "08", "34", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "34", + "FCC", "2.4G", "20M", "HT", "1T", "09", "32", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "34", + "FCC", "2.4G", "20M", "HT", "1T", "10", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "34", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "34", + "FCC", "2.4G", "20M", "HT", "1T", "12", "26", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "34", + "FCC", "2.4G", "20M", "HT", "1T", "13", "12", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "34", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "30", + "MKK", "2.4G", "40M", "HT", "1T", "03", "30", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "30", + "MKK", "2.4G", "40M", "HT", "1T", "04", "30", + "FCC", "2.4G", "40M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "30", + "MKK", "2.4G", "40M", "HT", "1T", "05", "30", + "FCC", "2.4G", "40M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "30", + "MKK", "2.4G", "40M", "HT", "1T", "06", "30", + "FCC", "2.4G", "40M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "30", + "MKK", "2.4G", "40M", "HT", "1T", "07", "30", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "30", + "MKK", "2.4G", "40M", "HT", "1T", "08", "30", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "30", + "MKK", "2.4G", "40M", "HT", "1T", "09", "30", + "FCC", "2.4G", "40M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "30", + "MKK", "2.4G", "40M", "HT", "1T", "10", "30", + "FCC", "2.4G", "40M", "HT", "1T", "11", "20", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "30", + "MKK", "2.4G", "40M", "HT", "1T", "11", "30", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "63", + "MKK", "2.4G", "40M", "HT", "1T", "12", "63", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "63", + "MKK", "2.4G", "40M", "HT", "1T", "13", "63", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "31", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "33", + "FCC", "5G", "20M", "OFDM", "1T", "40", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "33", + "FCC", "5G", "20M", "OFDM", "1T", "44", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "33", + "FCC", "5G", "20M", "OFDM", "1T", "48", "31", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "33", + "FCC", "5G", "20M", "OFDM", "1T", "52", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "33", + "FCC", "5G", "20M", "OFDM", "1T", "56", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "33", + "FCC", "5G", "20M", "OFDM", "1T", "60", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "33", + "FCC", "5G", "20M", "OFDM", "1T", "64", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "33", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "33", + "FCC", "5G", "20M", "OFDM", "1T", "104", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "104", "32", + "MKK", "5G", "20M", "OFDM", "1T", "104", "33", + "FCC", "5G", "20M", "OFDM", "1T", "108", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "33", + "FCC", "5G", "20M", "OFDM", "1T", "112", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "33", + "FCC", "5G", "20M", "OFDM", "1T", "116", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "33", + "FCC", "5G", "20M", "OFDM", "1T", "120", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "33", + "FCC", "5G", "20M", "OFDM", "1T", "124", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "33", + "FCC", "5G", "20M", "OFDM", "1T", "128", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "33", + "FCC", "5G", "20M", "OFDM", "1T", "132", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "33", + "FCC", "5G", "20M", "OFDM", "1T", "136", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "33", + "FCC", "5G", "20M", "OFDM", "1T", "140", "31", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "33", + "FCC", "5G", "20M", "OFDM", "1T", "144", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "144", "32", + "MKK", "5G", "20M", "OFDM", "1T", "144", "63", + "FCC", "5G", "20M", "OFDM", "1T", "149", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "63", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "63", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "63", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "63", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "33", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "63", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "33", + "FCC", "5G", "20M", "HT", "1T", "40", "33", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "33", + "FCC", "5G", "20M", "HT", "1T", "44", "33", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "33", + "FCC", "5G", "20M", "HT", "1T", "48", "33", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "33", + "FCC", "5G", "20M", "HT", "1T", "52", "33", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "33", + "FCC", "5G", "20M", "HT", "1T", "56", "33", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "33", + "FCC", "5G", "20M", "HT", "1T", "60", "33", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "33", + "FCC", "5G", "20M", "HT", "1T", "64", "30", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "33", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "33", + "FCC", "5G", "20M", "HT", "1T", "104", "33", + "ETSI", "5G", "20M", "HT", "1T", "104", "32", + "MKK", "5G", "20M", "HT", "1T", "104", "33", + "FCC", "5G", "20M", "HT", "1T", "108", "33", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "33", + "FCC", "5G", "20M", "HT", "1T", "112", "33", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "33", + "FCC", "5G", "20M", "HT", "1T", "116", "33", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "33", + "FCC", "5G", "20M", "HT", "1T", "120", "33", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "33", + "FCC", "5G", "20M", "HT", "1T", "124", "33", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "33", + "FCC", "5G", "20M", "HT", "1T", "128", "33", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "33", + "FCC", "5G", "20M", "HT", "1T", "132", "33", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "33", + "FCC", "5G", "20M", "HT", "1T", "136", "33", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "33", + "FCC", "5G", "20M", "HT", "1T", "140", "29", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "33", + "FCC", "5G", "20M", "HT", "1T", "144", "27", + "ETSI", "5G", "20M", "HT", "1T", "144", "63", + "MKK", "5G", "20M", "HT", "1T", "144", "63", + "FCC", "5G", "20M", "HT", "1T", "149", "33", + "ETSI", "5G", "20M", "HT", "1T", "149", "63", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "33", + "ETSI", "5G", "20M", "HT", "1T", "153", "63", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "33", + "ETSI", "5G", "20M", "HT", "1T", "157", "63", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "33", + "ETSI", "5G", "20M", "HT", "1T", "161", "63", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "33", + "ETSI", "5G", "20M", "HT", "1T", "165", "63", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "22", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "32", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "23", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "21", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "32", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "32", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "142", "29", + "ETSI", "5G", "40M", "HT", "1T", "142", "63", + "MKK", "5G", "40M", "HT", "1T", "142", "63", + "FCC", "5G", "40M", "HT", "1T", "151", "32", + "ETSI", "5G", "40M", "HT", "1T", "151", "63", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "32", + "ETSI", "5G", "40M", "HT", "1T", "159", "63", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "19", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "28", + "FCC", "5G", "80M", "VHT", "1T", "58", "22", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "28", + "FCC", "5G", "80M", "VHT", "1T", "106", "18", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "32", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "138", "28", + "ETSI", "5G", "80M", "VHT", "1T", "138", "63", + "MKK", "5G", "80M", "VHT", "1T", "138", "63", + "FCC", "5G", "80M", "VHT", "1T", "155", "32", + "ETSI", "5G", "80M", "VHT", "1T", "155", "63", + "MKK", "5G", "80M", "VHT", "1T", "155", "63" +}; + +void +odm_read_and_config_mp_8821c_txpwr_lmt( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 i = 0; + u32 array_len = sizeof(array_mp_8821c_txpwr_lmt)/sizeof(u8 *); + u8 **array = (u8 **)array_mp_8821c_txpwr_lmt; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8821c_txpwr_lmt\n")); + + for (i = 0; i < array_len; i += 7) { + u8 *regulation = array[i]; + u8 *band = array[i+1]; + u8 *bandwidth = array[i+2]; + u8 *rate = array[i+3]; + u8 *rf_path = array[i+4]; + u8 *chnl = array[i+5]; + u8 *val = array[i+6]; + + odm_config_bb_txpwr_lmt_8821c(p_dm_odm, regulation, band, bandwidth, rate, rf_path, chnl, val); + } + +} + + diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h new file mode 100644 index 000000000000..3b3c0a968dc8 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halhwimg8821c_rf.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 3.4*/ +#ifndef __INC_MP_RF_HW_IMG_8821C_H +#define __INC_MP_RF_HW_IMG_8821C_H + +/****************************************************************************** +* radioa.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_radioa(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_radioa(void); + +/****************************************************************************** +* txpowertrack.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_txpowertrack(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_txpowertrack(void); + +/****************************************************************************** +* txpwr_lmt.TXT +******************************************************************************/ + +void +odm_read_and_config_mp_8821c_txpwr_lmt(/* tc: Test Chip, mp: mp Chip*/ + struct PHY_DM_STRUCT *p_dm_odm +); +u32 odm_get_version_mp_8821c_txpwr_lmt(void); + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c new file mode 100644 index 000000000000..8d6978df6ebb --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.c @@ -0,0 +1,372 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + +boolean +get_mix_mode_tx_agc_bbs_wing_offset_8821c( + void *p_dm_void, + enum pwrtrack_method method, + u8 rf_path, + u8 tx_power_index_offest_upper_bound, + s8 tx_power_index_offest_lower_bound +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + + u8 bb_swing_upper_bound = p_rf_calibrate_info->default_ofdm_index + 10; + u8 bb_swing_lower_bound = 0; + + s8 tx_agc_index = 0; + u8 tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d, tx_power_index_offest_upper_bound=%d, tx_power_index_offest_lower_bound=%d\n", + rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound)); + + if (tx_power_index_offest_upper_bound > 0XF) + tx_power_index_offest_upper_bound = 0XF; + + if (tx_power_index_offest_lower_bound < -15) + tx_power_index_offest_lower_bound = -15; + + if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= 0 && p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] <= tx_power_index_offest_upper_bound) { + tx_agc_index = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; + tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index; + } else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= 0 && (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] > tx_power_index_offest_upper_bound)) { + tx_agc_index = tx_power_index_offest_upper_bound; + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_upper_bound; + tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]; + + if (tx_bb_swing_index > bb_swing_upper_bound) + tx_bb_swing_index = bb_swing_upper_bound; + } else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] < 0 && (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] >= tx_power_index_offest_lower_bound)) { + tx_agc_index = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]; + tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index; + } else if (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] < 0 && (p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] < tx_power_index_offest_lower_bound)) { + tx_agc_index = tx_power_index_offest_lower_bound; + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] - tx_power_index_offest_lower_bound; + + if (p_rf_calibrate_info->default_ofdm_index > (p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] * (-1))) + tx_bb_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]; + else + tx_bb_swing_index = bb_swing_lower_bound; + } + + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path] = tx_agc_index; + p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path] = tx_bb_swing_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("MixMode Offset Path_%d pRF->absolute_ofdm_swing_idx[rf_path]=%d pRF->bb_swing_idx_ofdm[rf_path]=%d TxPwrIdxOffestUpper=%d TxPwrIdxOffestLower=%d\n", + rf_path, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound)); + + return true; +} + +void +odm_tx_pwr_track_set_pwr8821c( + void *p_dm_void, + enum pwrtrack_method method, + u8 rf_path, + u8 channel_mapped_index +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + u8 channel = *p_dm_odm->p_channel; + u8 band_width = *p_dm_odm->p_band_width; + u8 tx_power_index_offest_upper_bound = 0; + s8 tx_power_index_offest_lower_bound = 0; + u8 tx_power_index = 0; + u8 tx_rate = 0xFF; + + if (p_dm_odm->mp_mode == true) { + PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx); + + tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index); + } else { + u16 rate = *(p_dm_odm->p_forced_data_rate); + + if (!rate) { /*auto rate*/ + if (p_dm_odm->number_linked_client != 0) + tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate); + } else /*force rate*/ + tx_rate = (u8) rate; + } + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Call:%s tx_rate=0x%X\n", __func__, tx_rate)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->default_ofdm_index=%d pRF->default_cck_index=%d\n", p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->default_cck_index)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRF->absolute_ofdm_swing_idx=%d pRF->remnant_ofdm_swing_idx=%d pRF->absolute_cck_swing_idx=%d pRF->remnant_cck_swing_idx=%d rf_path=%d\n", + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path], p_rf_calibrate_info->absolute_cck_swing_idx[rf_path], p_rf_calibrate_info->remnant_cck_swing_idx, rf_path)); + + if (p_dm_odm->mp_mode == true) + tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, band_width, channel); + else { + if (p_dm_odm->number_linked_client != 0) + tx_power_index = odm_get_tx_power_index(p_dm_odm, (enum odm_rf_radio_path_e) rf_path, tx_rate, band_width, channel); + } + + if (tx_power_index >= 63) + tx_power_index = 63; + + tx_power_index_offest_upper_bound = 63 - tx_power_index; + + tx_power_index_offest_lower_bound = 0 - tx_power_index; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("tx_power_index=%d tx_power_index_offest_upper_bound=%d tx_power_index_offest_lower_bound=%d rf_path=%d\n", tx_power_index, tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound, rf_path)); + + if (method == BBSWING) { /*use for mp driver clean power tracking status*/ + switch (rf_path) { + case ODM_RF_PATH_A: + odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f)); + odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + break; + + default: + break; + } + + } else if (method == MIX_MODE) { + switch (rf_path) { + case ODM_RF_PATH_A: + get_mix_mode_tx_agc_bbs_wing_offset_8821c(p_dm_odm, method, rf_path, tx_power_index_offest_upper_bound, tx_power_index_offest_lower_bound); + odm_set_bb_reg(p_dm_odm, 0xC94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1)), ((p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]) & 0x3f)); + odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path]]); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TXAGC(0xC94)=0x%x BBSwing(0xc1c)=0x%x BBSwingIndex=%d rf_path=%d\n", + odm_get_bb_reg(p_dm_odm, 0xC94, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1))), + odm_get_bb_reg(p_dm_odm, 0xc1c, 0xFFE00000), + p_rf_calibrate_info->bb_swing_idx_ofdm[rf_path], rf_path)); + break; + + default: + break; + } + } + +} + +void +get_delta_swing_table_8821c( + void *p_dm_void, + u8 **temperature_up_a, + u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info); + struct _ADAPTER *adapter = p_dm_odm->adapter; + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter); + u8 channel = *p_dm_odm->p_channel; + + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_p; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_2ga_n; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_p; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_2gb_n; + + if (36 <= channel && channel <= 64) { + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[0]; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[0]; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[0]; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[0]; + } else if (100 <= channel && channel <= 144) { + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[1]; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[1]; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[1]; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[1]; + } else if (149 <= channel && channel <= 177) { + *temperature_up_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[2]; + *temperature_down_a = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[2]; + *temperature_up_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[2]; + *temperature_down_b = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[2]; + } +} + +void +_phy_aac_calibrate_8821c( + struct PHY_DM_STRUCT *p_dm_odm + ) +{ + u32 cnt = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[AACK]AACK start!!!!!!!\n")); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb8, bRFRegOffsetMask, 0x80a00); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xff0fa); + ODM_delay_ms(10); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xca, bRFRegOffsetMask, 0x80000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xc9, bRFRegOffsetMask, 0x1c141); + for (cnt = 0; cnt < 100; cnt++) { + ODM_delay_ms(1); + if (odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xca, 0x1000) != 0x1) + break; + } + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xff0f8); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[AACK]AACK end!!!!!!!\n")); +} + +void +_phy_lc_calibrate_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 lc_cal = 0, cnt = 0, tmp0xc00; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK start!!!!!!!\n")); + + /*RF to standby mode*/ + tmp0xc00 = odm_read_4byte(p_dm_odm, 0xc00); + odm_write_4byte(p_dm_odm, 0xc00, 0x4); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x10000); + + _phy_aac_calibrate_8821c(p_dm_odm); + + /*backup RF0x18*/ + lc_cal = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK); + /*Start LCK*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal | 0x08000); + ODM_delay_ms(50); + + for (cnt = 0; cnt < 100; cnt++) { + if (odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + + /*Recover channel number*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, RF_CHNLBW, RFREGOFFSETMASK, lc_cal); + /**restore*/ + odm_write_4byte(p_dm_odm, 0xc00, tmp0xc00); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, bRFRegOffsetMask, 0x3ffff); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK end!!!!!!!\n")); +} + +void +phy_lc_calibrate_8821c( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + boolean is_start_cont_tx = false, is_single_tone = false, is_carrier_suppression = false; + u64 start_time; + u64 progressing_time; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx); + is_start_cont_tx = p_mpt_ctx->is_start_cont_tx; + is_single_tone = p_mpt_ctx->is_single_tone; + is_carrier_suppression = p_mpt_ctx->is_carrier_suppression; + + if (is_start_cont_tx || is_single_tone || is_carrier_suppression) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]continues TX ing !!! LCK return\n")); + return; + } + + if (*(p_dm_odm->p_is_scan_in_process)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]scan is in process, bypass LCK\n")); + return; + } + + start_time = odm_get_current_time(p_dm_odm); + p_dm_odm->rf_calibrate_info.is_lck_in_progress = true; + _phy_lc_calibrate_8821c(p_dm_odm); + p_dm_odm->rf_calibrate_info.is_lck_in_progress = false; + progressing_time = odm_get_progressing_time(p_dm_odm, start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[LCK]LCK progressing_time = %lld\n", progressing_time)); +} + +void configure_txpower_track_8821c( + struct _TXPWRTRACK_CFG *p_config +) +{ + p_config->swing_table_size_cck = TXSCALE_TABLE_SIZE; + p_config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE; + p_config->threshold_iqk = IQK_THRESHOLD; + p_config->threshold_dpk = DPK_THRESHOLD; + p_config->average_thermal_num = AVG_THERMAL_NUM_8821C; + p_config->rf_path_count = MAX_PATH_NUM_8821C; + p_config->thermal_reg_addr = RF_T_METER_8821C; + + p_config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8821c; + p_config->do_iqk = do_iqk_8821c; + p_config->phy_lc_calibrate = phy_lc_calibrate_8821c; + + p_config->get_delta_swing_table = get_delta_swing_table_8821c; +} + +void phy_set_rf_path_switch_8821c( + struct _ADAPTER *p_adapter, + boolean is_main +) +{ + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; + u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/ + + if (is_main) + ant_num = SWITCH_TO_ANT1; /*Main = ANT_1*/ + else + ant_num = SWITCH_TO_ANT2; /*Aux = ANT_2*/ + + config_phydm_set_ant_path(p_dm_odm, p_dm_odm->current_rf_set_8821c, ant_num); + +} + +boolean +_phy_query_rf_path_switch_8821c( + struct _ADAPTER *p_adapter +) +{ + HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter); + struct PHY_DM_STRUCT *p_dm_odm = &p_hal_data->odmpriv; + u8 ant_num = 0; /*0: ANT_1, 1: ANT_2*/ + + ODM_delay_ms(300); + + ant_num = query_phydm_current_ant_num_8821c(p_dm_odm); + + if (ant_num == SWITCH_TO_ANT1) + return true; /*Main = ANT_1*/ + else + return false; /*Aux = ANT_2*/ + +} + +boolean phy_query_rf_path_switch_8821c( + struct _ADAPTER *p_adapter +) +{ + return _phy_query_rf_path_switch_8821c(p_adapter); +} + diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h new file mode 100644 index 000000000000..e2da1e491734 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/halphyrf_8821c.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8821C_H__ +#define __HAL_PHY_RF_8821C_H__ + +#define AVG_THERMAL_NUM_8821C 4 +#define RF_T_METER_8821C 0x42 + +void configure_txpower_track_8821c( + struct _TXPWRTRACK_CFG *p_config +); + +void +odm_tx_pwr_track_set_pwr8821c( + void *p_dm_void, + enum pwrtrack_method method, + u8 rf_path, + u8 channel_mapped_index +); + +void +get_delta_swing_table_8821c( + void *p_dm_void, + u8 **temperature_up_a, + u8 **temperature_down_a, + u8 **temperature_up_b, + u8 **temperature_down_b +); + +void +phy_lc_calibrate_8821c( + void *p_dm_void +); + +void phy_set_rf_path_switch_8821c( + struct _ADAPTER *p_adapter, + boolean is_main +); + +boolean phy_query_rf_path_switch_8821c( + struct _ADAPTER *p_adapter +); + +#endif /* #ifndef __HAL_PHY_RF_8821C_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c new file mode 100644 index 000000000000..62ebc73c2afe --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.c @@ -0,0 +1,888 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + +/* ======================================================================== */ +/* These following functions can be used for PHY DM only*/ + +u32 reg82c_8821c; +u32 reg838_8821c; +u32 reg830_8821c; +u32 rega24_8821c; +u32 rega28_8821c; +u32 regaac_8821c; + +enum odm_bw_e bw_8821c; +u8 central_ch_8821c; + +void +phydm_rxdfirpar_by_bw_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_bw_e bandwidth +) +{ + if (bandwidth == ODM_BW40M) { + /* RX DFIR for BW40 */ + odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8f0, BIT(31), 0x0); + } else if (bandwidth == ODM_BW80M) { + /* RX DFIR for BW80 */ + odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x1); + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8f0, BIT(31), 0x1); + } else { + /* RX DFIR for BW20, BW10 and BW5*/ + odm_set_bb_reg(p_dm_odm, 0x948, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0x94c, BIT(29) | BIT(28), 0x2); + odm_set_bb_reg(p_dm_odm, 0xc20, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0x8f0, BIT(31), 0x0); + } +} + +void +phydm_init_hw_info_by_rfe_type_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + p_dm_odm->is_init_hw_info_by_rfe = false; + /*2.4G default rf set with wlg or btg*/ + if (p_dm_odm->rfe_type == 2 || p_dm_odm->rfe_type == 4 || p_dm_odm->rfe_type == 7) + p_dm_odm->default_rf_set_8821c = SWITCH_TO_BTG; + else if (p_dm_odm->rfe_type == 0 || p_dm_odm->rfe_type == 1 || p_dm_odm->rfe_type == 3 || p_dm_odm->rfe_type == 5 || p_dm_odm->rfe_type == 6) + p_dm_odm->default_rf_set_8821c = SWITCH_TO_WLG; + else if (p_dm_odm->rfe_type == 0x22 || p_dm_odm->rfe_type == 0x24 || p_dm_odm->rfe_type == 0x27) { + p_dm_odm->default_rf_set_8821c = SWITCH_TO_BTG; + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + } else if (p_dm_odm->rfe_type == 0x20 || p_dm_odm->rfe_type == 0x21 || p_dm_odm->rfe_type == 0x23 || p_dm_odm->rfe_type == 0x25 || p_dm_odm->rfe_type == 0x26) { + p_dm_odm->default_rf_set_8821c = SWITCH_TO_WLG; + odm_cmn_info_init(p_dm_odm, ODM_CMNINFO_PACKAGE_TYPE, 1); + } + + if (p_dm_odm->rfe_type == 3 || p_dm_odm->rfe_type == 4 || p_dm_odm->rfe_type == 0x23 || p_dm_odm->rfe_type == 0x24) + p_dm_odm->default_ant_num_8821c = SWITCH_TO_ANT2; + else + p_dm_odm->default_ant_num_8821c = SWITCH_TO_ANT1; + + p_dm_odm->is_init_hw_info_by_rfe = true; + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("%s: RFE type (%d), rf set (%s)\n", __FUNCTION__, p_dm_odm->rfe_type, (p_dm_odm->default_rf_set_8821c == 0 ? "BTG" : "WLG"))); +} + +void +phydm_set_gnt_state_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean gnt_wl_state, + boolean gnt_bt_state +) +{ + u32 gnt_val = 0; + + odm_set_mac_reg(p_dm_odm, 0x70, BIT(26), 0x1); + + if (gnt_wl_state) + gnt_val = 0x3300; + else + gnt_val = 0x1100; + + if (gnt_bt_state) + gnt_val = gnt_val | 0xcc00; + else + gnt_val = gnt_val | 0x4400; + + odm_set_mac_reg(p_dm_odm, 0x1704, MASKLWORD, gnt_val); + ODM_delay_us(50); /*waiting before access 0x1700 */ + odm_set_mac_reg(p_dm_odm, 0x1700, MASKDWORD, 0xc00f0038); +} +/* ======================================================================== */ + +/* ======================================================================== */ +/* These following functions can be used by driver*/ + +u32 +config_phydm_read_rf_reg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask +) +{ + u32 readback_value, direct_addr; + u32 offset_read_rf[2] = {0x2800, 0x2c00}; + u32 power_RF[2] = {0x1c, 0xec}; + + /* Error handling.*/ + if (rf_path > ODM_RF_PATH_A) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, rf_path)); + return INVALID_RF_DATA; + } + + /* Error handling. Check if RF power is enable or not */ + /* 0xffffffff means RF power is disable */ + if (odm_get_mac_reg(p_dm_odm, power_RF[rf_path], MASKBYTE3) != 0x7) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Read fail, RF is disabled\n", __func__)); + return INVALID_RF_DATA; + } + + /* Calculate offset */ + reg_addr &= 0xff; + direct_addr = offset_read_rf[rf_path] + (reg_addr << 2); + + /* RF register only has 20bits */ + bit_mask &= RFREGOFFSETMASK; + + /* Read RF register directly */ + readback_value = odm_get_bb_reg(p_dm_odm, direct_addr, bit_mask); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x, bit mask = 0x%x\n", + __func__, rf_path, reg_addr, readback_value, bit_mask)); + return readback_value; +} + +boolean +config_phydm_write_rf_reg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +) +{ + u32 data_and_addr = 0, data_original = 0; + u32 offset_write_rf[2] = {0xc90, 0xe90}; + u32 power_RF[2] = {0x1c, 0xec}; + u8 bit_shift; + + /* Error handling.*/ + if (rf_path > ODM_RF_PATH_A) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, rf_path)); + return false; + } + + /* Read RF register content first */ + reg_addr &= 0xff; + bit_mask = bit_mask & RFREGOFFSETMASK; + + if (bit_mask != RFREGOFFSETMASK) { + data_original = config_phydm_read_rf_reg_8821c(p_dm_odm, rf_path, reg_addr, RFREGOFFSETMASK); + + /* Error handling. RF is disabled */ + if (config_phydm_read_rf_check_8821c(data_original) == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disable\n", __func__)); + return false; + } + + /* check bit mask */ + if (bit_mask != 0xfffff) { + for (bit_shift = 0; bit_shift <= 19; bit_shift++) { + if (((bit_mask >> bit_shift) & 0x1) == 1) + break; + } + data = ((data_original)&(~bit_mask)) | (data << bit_shift); + } + } else if (odm_get_mac_reg(p_dm_odm, power_RF[rf_path], MASKBYTE3) != 0x7) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Write fail, RF is disabled\n", __func__)); + return false; + } + + /* Put write addr in [27:20] and write data in [19:00] */ + data_and_addr = ((reg_addr << 20) | (data & 0x000fffff)) & 0x0fffffff; + + /* Write operation */ + odm_set_bb_reg(p_dm_odm, offset_write_rf[rf_path], MASKDWORD, data_and_addr); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: RF-%d 0x%x = 0x%x (original: 0x%x), bit mask = 0x%x\n", + __func__, rf_path, reg_addr, data, data_original, bit_mask)); + return true; +} + +boolean +config_phydm_write_txagc_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate +) +{ + u32 offset_txagc[2] = {0x1d00, 0x1d80}; + u8 rate_idx = (hw_rate & 0xfc), i; + u32 txagc_content = 0x0; + + /* Input need to be HW rate index, not driver rate index!!!! */ + + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return true; + } + + /* Error handling */ + if ((path > ODM_RF_PATH_A) || (hw_rate > 0x53)) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, path)); + return false; + } + + /* driver need to construct a 4-byte power index */ + odm_set_bb_reg(p_dm_odm, (offset_txagc[path] + rate_idx), MASKDWORD, power_index); + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: path-%d rate index 0x%x (0x%x) = 0x%x\n", + __func__, path, hw_rate, (offset_txagc[path] + hw_rate), power_index)); + return true; +} + +u8 +config_phydm_read_txagc_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e path, + u8 hw_rate +) +{ + u8 read_back_data; + + /* Input need to be HW rate index, not driver rate index!!!! */ + + /* Error handling */ + if ((path > ODM_RF_PATH_A) || (hw_rate > 0x53)) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: unsupported path (%d)\n", __func__, path)); + return INVALID_TXAGC_DATA; + } + + /* Disable TX AGC report */ + odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); /* need to check */ + + /* Set data rate index (bit0~6) and path index (bit7) */ + odm_set_bb_reg(p_dm_odm, 0x1998, MASKBYTE0, (hw_rate | (path << 7))); + + /* Enable TXAGC report */ + odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x1); + + /* Read TX AGC report */ + read_back_data = (u8)odm_get_bb_reg(p_dm_odm, 0xd30, 0x7f0000); + + /* Driver have to disable TXAGC report after reading TXAGC (ref. user guide v11) */ + odm_set_bb_reg(p_dm_odm, 0x1998, BIT(16), 0x0); + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: path-%d rate index 0x%x = 0x%x\n", __func__, path, hw_rate, read_back_data)); + return read_back_data; +} + +boolean +config_phydm_switch_band_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +) +{ + u32 rf_reg18; + boolean rf_reg_status = true; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]======================>\n", __func__)); + + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return true; + } + + rf_reg18 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); + + if (central_ch <= 14) { + /* 2.4G */ + + /* Enable CCK block */ + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x1); + + /* Disable MAC CCK check */ + odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x0); + + /* Disable BB CCK check */ + odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x0); + + /*CCA Mask*/ + odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ + + /* RF band */ + rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); + + /* Switch WLG/BTG*/ + if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_BTG) + config_phydm_switch_rf_set_8821c(p_dm_odm, SWITCH_TO_BTG); + else if (p_dm_odm->default_rf_set_8821c == SWITCH_TO_WLG) + config_phydm_switch_rf_set_8821c(p_dm_odm, SWITCH_TO_WLG); + + /*RF TXA_TANK LUT mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(6), 0x1); + + /*RF TXA_PA_TANK*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x64, 0x0000f, 0xf); + + } else if (central_ch > 35) { + /* 5G */ + + /* Enable BB CCK check */ + odm_set_bb_reg(p_dm_odm, 0xa80, BIT(18), 0x1); + + /* Enable CCK check */ + odm_set_bb_reg(p_dm_odm, 0x454, BIT(7), 0x1); + + /* Disable CCK block */ + odm_set_bb_reg(p_dm_odm, 0x808, BIT(28), 0x0); + + /*CCA Mask*/ + odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 15); /*default value*/ + /*odm_set_bb_reg(p_dm_odm, 0x814, 0x0000FC00, 34); CCA mask = 13.6us*/ + + /* RF band */ + rf_reg18 = (rf_reg18 & (~(BIT(16) | BIT(9) | BIT(8)))); + rf_reg18 = (rf_reg18 | BIT(8) | BIT(16)); + + /* Switch WLA */ + config_phydm_switch_rf_set_8821c(p_dm_odm, SWITCH_TO_WLA); + + /*RF TXA_TANK LUT mode*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, BIT(6), 0x0); + + } else { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); + return false; + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + + if (rf_reg_status == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d), because writing RF register is fail\n", __func__, central_ch)); + return false; + } + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch band (ch: %d)\n", __func__, central_ch)); + return true; +} + +boolean +config_phydm_switch_channel_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +) +{ + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u32 rf_reg18, rf_reg_b8 = 0; + boolean rf_reg_status = true; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]====================>\n", __func__)); + + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return true; + } + + central_ch_8821c = central_ch; + rf_reg18 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); + + if (p_dm_odm->cut_version == ODM_CUT_A) { + rf_reg_b8 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg_b8); + } + + /* Switch band and channel */ + if (central_ch <= 14) { + /* 2.4G */ + + /* 1. RF band and channel*/ + rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0))); + rf_reg18 = (rf_reg18 | central_ch); + + /* 2. AGC table selection */ + odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x0); + p_dm_dig_table->agc_table_idx = 0x0; + + /* 3. Set central frequency for clock offset tracking */ + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x96a); + + /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ + if (p_dm_odm->cut_version == ODM_CUT_A) + rf_reg_b8 = rf_reg_b8 | BIT(19); + + /* CCK TX filter parameters */ + if (central_ch == 14) { + odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, 0x0000b81c); + odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, 0x0000); + odm_set_bb_reg(p_dm_odm, 0xaac, MASKDWORD, 0x00003667); + } else { + odm_set_bb_reg(p_dm_odm, 0xa24, MASKDWORD, rega24_8821c); + odm_set_bb_reg(p_dm_odm, 0xa28, MASKLWORD, (rega28_8821c & MASKLWORD)); + odm_set_bb_reg(p_dm_odm, 0xaac, MASKDWORD, regaac_8821c); + } + + } else if (central_ch > 35) { + /* 5G */ + + /* 1. RF band and channel*/ + rf_reg18 = (rf_reg18 & (~(BIT(18) | BIT(17) | MASKBYTE0))); + rf_reg18 = (rf_reg18 | central_ch); + + if (central_ch >= 36 && central_ch <= 64) + ; + else if ((central_ch >= 100) && (central_ch <= 140)) + rf_reg18 = (rf_reg18 | BIT(17)); + else if (central_ch > 140) + rf_reg18 = (rf_reg18 | BIT(18)); + else { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (RF18) (ch: %d)\n", __func__, central_ch)); + return false; + } + + /* 2. AGC table selection */ + if ((central_ch >= 36) && (central_ch <= 64)) { + odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x1); + p_dm_dig_table->agc_table_idx = 0x1; + } else if ((central_ch >= 100) && (central_ch <= 144)) { + odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x2); + p_dm_dig_table->agc_table_idx = 0x2; + } else if (central_ch >= 149) { + odm_set_bb_reg(p_dm_odm, 0xc1c, 0x00000F00, 0x3); + p_dm_dig_table->agc_table_idx = 0x3; + } else { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (AGC) (ch: %d)\n", __func__, central_ch)); + return false; + } + + /* 3. Set central frequency for clock offset tracking */ + if ((central_ch >= 36) && (central_ch <= 48)) + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x494); + else if ((central_ch >= 52) && (central_ch <= 64)) + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x453); + else if ((central_ch >= 100) && (central_ch <= 116)) + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x452); + else if ((central_ch >= 118) && (central_ch <= 177)) + odm_set_bb_reg(p_dm_odm, 0x860, 0x1ffe0000, 0x412); + else { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (fc_area) (ch: %d)\n", __func__, central_ch)); + return false; + } + + /* Fix A-cut LCK fail issue @ 5285MHz~5375MHz, 0xb8[19]=0x0 */ + if (p_dm_odm->cut_version == ODM_CUT_A) { + if ((central_ch >= 57) && (central_ch <= 75)) + rf_reg_b8 = rf_reg_b8 & (~BIT(19)); + else + rf_reg_b8 = rf_reg_b8 | BIT(19); + } + + } else { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch band (ch: %d)\n", __func__, central_ch)); + return false; + } + + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + + if (p_dm_odm->cut_version == ODM_CUT_A) + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0xb8, RFREGOFFSETMASK, rf_reg_b8); + + if (rf_reg_status == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch channel (ch: %d), because writing RF register is fail\n", __func__, central_ch)); + return false; + } + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch channel (ch: %d)\n", __func__, central_ch)); + return true; +} + +boolean +config_phydm_switch_bandwidth_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +) +{ + u32 rf_reg18; + boolean rf_reg_status = true; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]===================>\n", __func__)); + + if (p_dm_odm->is_disable_phy_api) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: disable PHY API for debug!!\n", __func__)); + return true; + } + + /* Error handling */ + if ((bandwidth >= ODM_BW_MAX) || ((bandwidth == ODM_BW40M) && (primary_ch_idx > 2)) || ((bandwidth == ODM_BW80M) && (primary_ch_idx > 4))) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + return false; + } + + bw_8821c = bandwidth; + rf_reg18 = config_phydm_read_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + rf_reg_status = rf_reg_status & config_phydm_read_rf_check_8821c(rf_reg18); + + /* Switch bandwidth */ + switch (bandwidth) { + case ODM_BW20M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, ODM_BW20M); + + /* ADC clock = 160M clock for BW20 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x1); + + /* DAC clock = 160M clock for BW20 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x1); + + /* ADC buffer clock */ + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); + + break; + } + case ODM_BW40M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 40M */ + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW40M)); + + /* CCK primary channel */ + if (primary_ch_idx == 1) + odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), primary_ch_idx); + else + odm_set_bb_reg(p_dm_odm, 0xa00, BIT(4), 0); + + /* ADC clock = 160M clock for BW40 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(11) | BIT(10)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(17), 0x1); + + /* DAC clock = 160M clock for BW20 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(23) | BIT(22)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(29), 0x1); + + /* ADC buffer clock */ + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); + rf_reg18 = (rf_reg18 | BIT(11)); + + break; + } + case ODM_BW80M: + { + /* Small BW([7:6]) = 0, primary channel ([5:2]) = sub-channel, rf mode([1:0]) = 80M */ + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (((primary_ch_idx & 0xf) << 2) | ODM_BW80M)); + + /* ADC clock = 160M clock for BW80 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(13) | BIT(12)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(18), 0x1); + + /* DAC clock = 160M clock for BW20 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(25) | BIT(24)), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(30), 0x1); + + /* ADC buffer clock */ + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 & (~(BIT(11) | BIT(10)))); + rf_reg18 = (rf_reg18 | BIT(10)); + + break; + } + case ODM_BW5M: + { + /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(6) | ODM_BW20M)); + + /* ADC clock = 40M clock */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x2); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); + + /* DAC clock = 160M clock for BW20 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x2); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); + + /* ADC buffer clock */ + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); + + break; + } + case ODM_BW10M: + { + /* Small BW([7:6]) = 1, primary channel ([5:2]) = 0, rf mode([1:0]) = 20M */ + odm_set_bb_reg(p_dm_odm, 0x8ac, MASKBYTE0, (BIT(7) | ODM_BW20M)); + + /* ADC clock = 80M clock */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(9) | BIT(8)), 0x3); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(16), 0x0); + + /* DAC clock = 160M clock for BW20 */ + odm_set_bb_reg(p_dm_odm, 0x8ac, (BIT(21) | BIT(20)), 0x3); + odm_set_bb_reg(p_dm_odm, 0x8ac, BIT(28), 0x0); + + /* ADC buffer clock */ + odm_set_bb_reg(p_dm_odm, 0x8c4, BIT(30), 0x0); + odm_set_bb_reg(p_dm_odm, 0x8c8, BIT(31), 0x1); + + /* RF bandwidth */ + rf_reg18 = (rf_reg18 | BIT(11) | BIT(10)); + + break; + } + default: + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + } + + /* Write RF register */ + rf_reg_status = rf_reg_status & config_phydm_write_rf_reg_8821c(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK, rf_reg18); + + if (rf_reg_status == false) { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Fail to switch bandwidth (bw: %d, primary ch: %d), because writing RF register is fail\n", __func__, bandwidth, primary_ch_idx)); + return false; + } + + /* Modify RX DFIR parameters */ + phydm_rxdfirpar_by_bw_8821c(p_dm_odm, bandwidth); + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Success to switch bandwidth (bw: %d, primary ch: %d)\n", __func__, bandwidth, primary_ch_idx)); + return true; +} + +boolean +config_phydm_parameter_init_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_parameter_init_e type +) +{ + if (type == ODM_PRE_SETTING) { + odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x0); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Pre setting: disable OFDM and CCK block\n", __func__)); + } else if (type == ODM_POST_SETTING) { + odm_set_bb_reg(p_dm_odm, 0x808, (BIT(28) | BIT(29)), 0x3); + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Post setting: enable OFDM and CCK block\n", __func__)); + reg82c_8821c = odm_get_bb_reg(p_dm_odm, 0x82c, MASKDWORD); + reg838_8821c = odm_get_bb_reg(p_dm_odm, 0x838, MASKDWORD); + reg830_8821c = odm_get_bb_reg(p_dm_odm, 0x830, MASKDWORD); + rega24_8821c = odm_get_bb_reg(p_dm_odm, 0xa24, MASKDWORD); + rega28_8821c = odm_get_bb_reg(p_dm_odm, 0xa28, MASKDWORD); + regaac_8821c = odm_get_bb_reg(p_dm_odm, 0xaac, MASKDWORD); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: Wrong type!!\n", __func__)); + return false; + } + + return true; +} + +void +config_phydm_switch_rf_set_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 rf_set +) +{ + u32 bb_reg32; + + odm_set_mac_reg(p_dm_odm, 0x1080, BIT(16), 0x1); + odm_set_mac_reg(p_dm_odm, 0x00, BIT(26), 0x1); + /*odm_set_mac_reg(p_dm_odm, 0x70, BIT(26), 0x1);*/ + /*odm_set_mac_reg(p_dm_odm, 0x1704, MASKLWORD, 0x4000);*/ + /*odm_set_mac_reg(p_dm_odm, 0x1700, (BIT(31) | BIT(30)), 0x3); */ + + bb_reg32 = odm_get_bb_reg(p_dm_odm, 0xcb8, MASKDWORD); + switch (rf_set) { + + case SWITCH_TO_BTG: + + p_dm_odm->current_rf_set_8821c = SWITCH_TO_BTG; + + bb_reg32 = (bb_reg32 | BIT(16)); + bb_reg32 &= (~(BIT(18) | BIT(20) | BIT(21) | BIT(22) | BIT(23))); + if (p_dm_odm->mp_mode == true) + { + odm_config_bb_with_header_file(p_dm_odm, CONFIG_BB_AGC_TAB_DIFF); + /*Toggle initial gain twice for valid gain table*/ + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x22); + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x20); + } + break; + case SWITCH_TO_WLG: + + p_dm_odm->current_rf_set_8821c = SWITCH_TO_WLG; + + bb_reg32 = (bb_reg32 | BIT(20) | BIT(21) | BIT(22)); + bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(23))); + if (p_dm_odm->mp_mode == true) + { + odm_config_bb_with_header_file(p_dm_odm, CONFIG_BB_AGC_TAB_DIFF); + /*Toggle initial gain twice for valid gain table*/ + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x22); + odm_set_bb_reg(p_dm_odm, ODM_REG(IGI_A, p_dm_odm), ODM_BIT(IGI, p_dm_odm), 0x20); + } + break; + case SWITCH_TO_WLA: + + p_dm_odm->current_rf_set_8821c = SWITCH_TO_WLA; + + bb_reg32 = (bb_reg32 | BIT(20) | BIT(22) | BIT(23)); + bb_reg32 &= (~(BIT(16) | BIT(18) | BIT(21))); + + break; + case SWITCH_TO_BT: + + p_dm_odm->current_rf_set_8821c = SWITCH_TO_BT; + + break; + default: + break; + + } + + odm_set_bb_reg(p_dm_odm, 0xcb8, MASKDWORD, bb_reg32); + +} + +void +config_phydm_set_ant_path( + struct PHY_DM_STRUCT *p_dm_odm, + u8 rf_set, + u8 ant_num +) +{ + boolean switch_polarity_inverse = false; + u8 regval_0xcb7 = 0; + + p_dm_odm->current_ant_num_8821c = ant_num; + config_phydm_switch_rf_set_8821c(p_dm_odm, rf_set); + + if (rf_set == SWITCH_TO_BT) + phydm_set_gnt_state_8821c(p_dm_odm, false, true); /* GNT_WL=0, GNT_BT=1 for BT test */ + else + phydm_set_gnt_state_8821c(p_dm_odm, true, false); /* GNT_WL=1, GNT_BT=0 for WL test */ + + if (p_dm_odm->rfe_type == 0x5 || p_dm_odm->rfe_type == 0x6 || p_dm_odm->rfe_type == 0x25 || p_dm_odm->rfe_type == 0x26) /*switch does not exist*/ + return; + + if (p_dm_odm->current_ant_num_8821c) /*Ant1 = 0, Ant2 = 1*/ + switch_polarity_inverse = !switch_polarity_inverse; + + if (rf_set == SWITCH_TO_WLG) + switch_polarity_inverse = !switch_polarity_inverse; + + /*set antenna control by WL 0xcb4[29:28]*/ + odm_set_mac_reg(p_dm_odm, 0x4c, BIT(24)|BIT(23), 0x2); + + /*set RFE_ctrl8 and RFE_ctrl9 as antenna control pins by software*/ + odm_set_bb_reg(p_dm_odm, 0xcb4, 0x000000ff, 0x77); + + /*0xcb4[29:28] = 2b'01 for no switch_polatiry_inverse, DPDT_SEL_N =1, DPDT_SEL_P =0*/ + regval_0xcb7 = (switch_polarity_inverse == false ? 0x1 : 0x2); + + odm_set_bb_reg(p_dm_odm, 0xcb4, 0x30000000, regval_0xcb7); + +} + +u32 +query_phydm_trx_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0x00000000; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: trx_capability = 0x%x\n", __func__, value32)); + return value32; +} + +u32 +query_phydm_stbc_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0x00010001; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: stbc_capability = 0x%x\n", __func__, value32)); + return value32; +} + +u32 +query_phydm_ldpc_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0x01000100; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: ldpc_capability = 0x%x\n", __func__, value32)); + return value32; +} + +u32 +query_phydm_txbf_parameters_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0x00030003; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_parameters = 0x%x\n", __func__, value32)); + return value32; +} + +u32 +query_phydm_txbf_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 value32 = 0x01010001; + + ODM_RT_TRACE(p_dm_odm, ODM_PHY_CONFIG, ODM_DBG_TRACE, ("[%s]: txbf_capability = 0x%x\n", __func__, value32)); + return value32; +} + +u8 +query_phydm_default_rf_set_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + return p_dm_odm->default_rf_set_8821c; +} + +u8 +query_phydm_current_ant_num_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 regval_0xcb4 = odm_get_bb_reg(p_dm_odm, 0xcb4, BIT(29)|BIT(28)); + + if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG || p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLA || p_dm_odm->current_rf_set_8821c == SWITCH_TO_BT) { + if (regval_0xcb4 == 1) + p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT1; + else if (regval_0xcb4 == 2) + p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT2; + else + if (regval_0xcb4 == 1) + p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT2; + else if (regval_0xcb4 == 2) + p_dm_odm->current_ant_num_8821c = SWITCH_TO_ANT1; + } + + return p_dm_odm->current_ant_num_8821c; +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h new file mode 100644 index 000000000000..b777f32385af --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_hal_api8821c.h @@ -0,0 +1,213 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_PHYDM_API_H_8821C__ +#define __INC_PHYDM_API_H_8821C__ + + +#define PHY_CONFIG_VERSION_8821C "3.1.20" /*2016.11.21 (HW user guide version: R03, SW user guide version: R01, Modification: R20)*/ + +#define INVALID_RF_DATA 0xffffffff +#define INVALID_TXAGC_DATA 0xff + +#define config_phydm_read_rf_check_8821c(data) (data != INVALID_RF_DATA) +#define config_phydm_read_txagc_check_8821c(data) (data != INVALID_TXAGC_DATA) + +enum rf_set_8821c { + SWITCH_TO_BTG = 0x0, + SWITCH_TO_WLG = 0x1, + SWITCH_TO_WLA = 0x2, + SWITCH_TO_BT = 0x3 +}; + +enum ant_num_8821c { + SWITCH_TO_ANT1 = 0x0, + SWITCH_TO_ANT2 = 0x1 +}; + +enum ant_num_map_8821c { + BOTH_AVAILABLE = 0x1, + ONLY_ANT1 = 0x2, + ONLY_ANT2 = 0x3, + DONT_CARE = 0x4 +}; + +u32 +config_phydm_read_rf_reg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask +); + +boolean +config_phydm_write_rf_reg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e rf_path, + u32 reg_addr, + u32 bit_mask, + u32 data +); + +boolean +config_phydm_write_txagc_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate +); + +u8 +config_phydm_read_txagc_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_radio_path_e path, + u8 hw_rate +); + +boolean +config_phydm_switch_band_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +); + +boolean +config_phydm_switch_channel_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch +); + +boolean +config_phydm_switch_bandwidth_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +); + +boolean +config_phydm_switch_channel_bw_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 central_ch, + u8 primary_ch_idx, + enum odm_bw_e bandwidth +); + +boolean +config_phydm_trx_mode_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_rf_path_e tx_path, + enum odm_rf_path_e rx_path, + boolean is_tx2_path +); + +boolean +config_phydm_parameter_init_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + enum odm_parameter_init_e type +); + +void +config_phydm_switch_rf_set_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 rf_set +); + +void +config_phydm_set_ant_path( + struct PHY_DM_STRUCT *p_dm_odm, + u8 rf_set, + u8 ant_num +); + +/* ======================================================================== */ +/* These following functions can be used for PHY DM only*/ + +boolean +phydm_write_txagc_1byte_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 power_index, + enum odm_rf_radio_path_e path, + u8 hw_rate +); + +void +phydm_init_hw_info_by_rfe_type_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +void +phydm_set_gnt_state_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean gnt_wl_state, + boolean gnt_bt_state +); + +/* ======================================================================== */ + +u32 +query_phydm_trx_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_stbc_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_ldpc_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_txbf_parameters_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u32 +query_phydm_txbf_capability_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u8 +query_phydm_default_rf_set_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u8 +query_phydm_current_rf_set_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u8 +query_phydm_rfetype_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u8 +query_phydm_current_ant_num_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +u8 +query_phydm_ant_num_map_8821c( + struct PHY_DM_STRUCT *p_dm_odm +); + +#endif /* __INC_PHYDM_API_H_8821C__ */ diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c new file mode 100644 index 000000000000..6395b56662c0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.c @@ -0,0 +1,1991 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + +/*---------------------------Define Local Constant---------------------------*/ + +static u32 dpk_result[DPK_BACKUP_REG_NUM_8821C] ; +#define enable_8821c_dpk 1 +#define dpk_forcein_sram4 0 + +/*---------------------------Define Local Constant---------------------------*/ + +void do_iqk_8821c( + void *p_dm_void, + u8 delta_thermal_index, + u8 thermal_value, + u8 threshold +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + + p_dm_odm->rf_calibrate_info.thermal_value_iqk = thermal_value; + phy_iq_calibrate_8821c(p_dm_odm, true); +} + +void +_iqk_check_coex_status( + struct PHY_DM_STRUCT *p_dm_odm, + boolean beforeK +) +{ + u8 u1b_tmp; + u16 count = 0; + u8 h2c_parameter; + + h2c_parameter = 1; + + if (beforeK) { + u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x before h2c 0x6d\n", u1b_tmp)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x before h2c 0x6d\n", u1b_tmp)); + + /*check if BT IQK */ + u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c); + while ((u1b_tmp & BIT(1)) && (count < 100)) { + ODM_delay_ms(10); + u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c); + count++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count)); + } + odm_fill_h2c_cmd(p_dm_odm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter); + + u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x after h2c 0x6d\n", u1b_tmp)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[0] = 0x%x after h2c 0x6d\n", u1b_tmp)); + + u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c); + /*check if WL IQK available form WL FW */ + while ((!(u1b_tmp & BIT(0))) && (count < 100)) { + ODM_delay_ms(10); + u1b_tmp = odm_read_1byte(p_dm_odm, 0x49c); + count++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c[1]=0x%x, count = %d\n", u1b_tmp, count)); + } + + if (count >= 100) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Polling 0x49c to 1 for WiFi calibration H2C cmd FAIL! count(%d)\n", count)); + + } else + odm_set_bb_reg(p_dm_odm, 0x49c, BIT(0), 0x0); +} + +u32 +_iqk_indirect_read_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u16 reg_addr +) +{ + u32 j = 0; + + /*wait for ready bit before access 0x1700*/ + odm_write_4byte(p_dm_odm, 0x1700, 0x800f0000 | reg_addr); + + do { + j++; + } while (((odm_read_1byte(p_dm_odm, 0x1703) & BIT(5)) == 0) && (j < 30000)); + + return odm_read_4byte(p_dm_odm, 0x1708); /*get read data*/ + +} + +void +_iqk_indirect_write_reg( + struct PHY_DM_STRUCT *p_dm_odm, + u16 reg_addr, + u32 bit_mask, + u32 reg_value +) +{ + u32 val, i = 0, j = 0, bitpos = 0; + + if (bit_mask == 0x0) + return; + if (bit_mask == 0xffffffff) { + odm_write_4byte(p_dm_odm, 0x1704, reg_value); /*put write data*/ + + /*wait for ready bit before access 0x1700*/ + do { + j++; + } while (((odm_read_1byte(p_dm_odm, 0x1703) & BIT(5)) == 0) && (j < 30000)); + + odm_write_4byte(p_dm_odm, 0x1700, 0xc00f0000 | reg_addr); + } else { + for (i = 0; i <= 31; i++) { + if (((bit_mask >> i) & 0x1) == 0x1) { + bitpos = i; + break; + } + } + + /*read back register value before write*/ + val = _iqk_indirect_read_reg(p_dm_odm, reg_addr); + val = (val & (~bit_mask)) | (reg_value << bitpos); + + odm_write_4byte(p_dm_odm, 0x1704, val); /*put write data*/ + + /*wait for ready bit before access 0x1700*/ + do { + j++; + } while (((odm_read_1byte(p_dm_odm, 0x1703) & BIT(5)) == 0) && (j < 30000)); + + odm_write_4byte(p_dm_odm, 0x1700, 0xc00f0000 | reg_addr); + } +} + +void +_iqk_set_gnt_wl_high( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 val = 0; + u8 state = 0x1, sw_control = 0x1; + + /*GNT_WL = 1*/ + val = (sw_control) ? ((state << 1) | 0x1) : 0; + _iqk_indirect_write_reg(p_dm_odm, 0x38, 0x3000, val); /*0x38[13:12]*/ + _iqk_indirect_write_reg(p_dm_odm, 0x38, 0x0300, val); /*0x38[9:8]*/ +} + +void _iqk_set_gnt_bt_low( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + u32 val = 0; + u8 state = 0x0, sw_control = 0x1; + + /*GNT_BT = 0*/ + val = (sw_control) ? ((state << 1) | 0x1) : 0; + _iqk_indirect_write_reg(p_dm_odm, 0x38, 0xc000, val); /*0x38[15:14]*/ + _iqk_indirect_write_reg(p_dm_odm, 0x38, 0x0c00, val); /*0x38[11:10]*/ +} + +void _iqk_set_gnt_wl_gnt_bt( + struct PHY_DM_STRUCT *p_dm_odm, + boolean beforeK +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + if (beforeK) { + _iqk_set_gnt_wl_high(p_dm_odm); + _iqk_set_gnt_bt_low(p_dm_odm); + } else + _iqk_indirect_write_reg(p_dm_odm, 0x38, MASKDWORD, p_iqk_info->tmp_GNTWL); +} + +void +_iqk_fill_iqk_report_8821c( + void *p_dm_void, + u8 channel +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0; + u8 i; + + for (i = 0; i < SS_8821C; i++) { + tmp1 = tmp1 + ((p_iqk_info->IQK_fail_report[channel][i][TX_IQK] & 0x1) << i); + tmp2 = tmp2 + ((p_iqk_info->IQK_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4)); + tmp3 = tmp3 + ((p_iqk_info->RXIQK_fail_code[channel][i] & 0x3) << (i * 2 + 8)); + } + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_set_bb_reg(p_dm_odm, 0x1bf0, 0x00ffffff, tmp1 | tmp2 | tmp3); + + for (i = 0; i < SS_8821C; i++) + odm_write_4byte(p_dm_odm, 0x1be8 + (i * 4), (p_iqk_info->RXIQK_AGC[channel][(i * 2) + 1] << 16) | p_iqk_info->RXIQK_AGC[channel][i * 2]); +} + +void +_iqk_backup_mac_bb_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 *MAC_backup, + u32 *BB_backup, + u32 *backup_mac_reg, + u32 *backup_bb_reg, + u8 num_backup_bb_reg +) +{ + u32 i; + + for (i = 0; i < MAC_REG_NUM_8821C; i++) + MAC_backup[i] = odm_read_4byte(p_dm_odm, backup_mac_reg[i]); + + for (i = 0; i < num_backup_bb_reg; i++) + BB_backup[i] = odm_read_4byte(p_dm_odm, backup_bb_reg[i]); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupMacBB Success!!!!\n")); */ +} + +void +_iqk_backup_rf_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 RF_backup[][SS_8821C], + u32 *backup_rf_reg +) +{ + u32 i, j; + + for (i = 0; i < RF_REG_NUM_8821C; i++) + for (j = 0; j < SS_8821C; j++) + RF_backup[i][j] = odm_get_rf_reg(p_dm_odm, j, backup_rf_reg[i], RFREGOFFSETMASK); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BackupRF Success!!!!\n")); */ + +} + +void +_iqk_agc_bnd_int_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + /*initialize RX AGC bnd, it must do after bbreset*/ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf80a7008); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8015008); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]init. rx agc bnd\n"));*/ +} + +void +_iqk_bb_reset_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + boolean cca_ing = false; + u32 count = 0; + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x0, RFREGOFFSETMASK, 0x10000); + + while (1) { + odm_write_4byte(p_dm_odm, 0x8fc, 0x0); + odm_set_bb_reg(p_dm_odm, 0x198c, 0x7, 0x7); + cca_ing = (boolean) odm_get_bb_reg(p_dm_odm, 0xfa0, BIT(3)); + + if (count > 30) + cca_ing = false; + + if (cca_ing) { + ODM_delay_ms(1); + count++; + } else { + odm_write_1byte(p_dm_odm, 0x808, 0x0); /*RX ant off*/ + odm_set_bb_reg(p_dm_odm, 0xa04, BIT(27) | BIT26 | BIT25 | BIT24, 0x0); /*CCK RX path off*/ + + /*BBreset*/ + odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x0); + odm_set_bb_reg(p_dm_odm, 0x0, BIT(16), 0x1); + + if (odm_get_bb_reg(p_dm_odm, 0x660, BIT(16))) + odm_write_4byte(p_dm_odm, 0x6b4, 0x89000006); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]BBreset!!!!\n")); + break; + } + } +} + +void +_iqk_afe_setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean do_iqk +) +{ + if (do_iqk) { + /*IQK AFE setting RX_WAIT_CCA mode */ + odm_write_4byte(p_dm_odm, 0xc60, 0x50000000); + odm_write_4byte(p_dm_odm, 0xc60, 0x700F0040); + + /*AFE setting*/ + odm_write_4byte(p_dm_odm, 0xc58, 0xd8000402); + odm_write_4byte(p_dm_odm, 0xc5c, 0xd1000120); + odm_write_4byte(p_dm_odm, 0xc6c, 0x00000a15); + _iqk_bb_reset_8821c(p_dm_odm); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for IQK mode!!!!\n")); */ + } else { + /*IQK AFE setting RX_WAIT_CCA mode */ + odm_write_4byte(p_dm_odm, 0xc60, 0x50000000); + odm_write_4byte(p_dm_odm, 0xc60, 0x700B8040); + + /*AFE setting*/ + odm_write_4byte(p_dm_odm, 0xc58, 0xd8020402); + odm_write_4byte(p_dm_odm, 0xc5c, 0xde000120); + odm_write_4byte(p_dm_odm, 0xc6c, 0x0000122a); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]AFE setting for Normal mode!!!!\n")); */ + } +} + +void +_iqk_restore_mac_bb_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 *MAC_backup, + u32 *BB_backup, + u32 *backup_mac_reg, + u32 *backup_bb_reg, + u8 num_backup_bb_reg +) +{ + u32 i; + + for (i = 0; i < MAC_REG_NUM_8821C; i++) + odm_write_4byte(p_dm_odm, backup_mac_reg[i], MAC_backup[i]); + for (i = 0; i < num_backup_bb_reg; i++) + odm_write_4byte(p_dm_odm, backup_bb_reg[i], BB_backup[i]); + + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreMacBB Success!!!!\n")); */ +} + +void +_iqk_restore_rf_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 *backup_rf_reg, + u32 RF_backup[][SS_8821C] +) +{ + u32 i; + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xee, RFREGOFFSETMASK, 0x0); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xdf, RFREGOFFSETMASK, RF_backup[0][ODM_RF_PATH_A] & (~BIT(4))); + /*odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK, RF_backup[1][ODM_RF_PATH_A]|BIT4);*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK, RF_backup[1][ODM_RF_PATH_A] & (~BIT(4))); + + for (i = 2; i < (RF_REG_NUM_8821C-1); i++) + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][ODM_RF_PATH_A]); + + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, (RF_backup[5][ODM_RF_PATH_A] & (~BIT(0)))); + + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]RestoreRF Success!!!!\n")); */ + +} + +void +_iqk_backup_iqk_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 step +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i, j, k, path, idx; + u32 tmp; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + if (step == 0x0) { + p_iqk_info->iqk_channel[1] = p_iqk_info->iqk_channel[0]; + for (i = 0; i < SS_8821C; i++) { + p_iqk_info->LOK_IDAC[1][i] = p_iqk_info->LOK_IDAC[0][i]; + p_iqk_info->RXIQK_AGC[1][i] = p_iqk_info->RXIQK_AGC[0][i]; + p_iqk_info->bypass_iqk[1][i] = p_iqk_info->bypass_iqk[0][i]; + p_iqk_info->RXIQK_fail_code[1][i] = p_iqk_info->RXIQK_fail_code[0][i]; + for (j = 0; j < 2; j++) { + p_iqk_info->IQK_fail_report[1][i][j] = p_iqk_info->IQK_fail_report[0][i][j]; + for (k = 0; k < 8; k++) { + p_iqk_info->IQK_CFIR_real[1][i][j][k] = p_iqk_info->IQK_CFIR_real[0][i][j][k]; + p_iqk_info->IQK_CFIR_imag[1][i][j][k] = p_iqk_info->IQK_CFIR_imag[0][i][j][k]; + } + } + } + + for (i = 0; i < 4; i++) { + p_iqk_info->RXIQK_fail_code[0][i] = 0x0; + p_iqk_info->RXIQK_AGC[0][i] = 0x0; + for (j = 0; j < 2; j++) { + p_iqk_info->IQK_fail_report[0][i][j] = true; + p_iqk_info->gs_retry_count[0][i][j] = 0x0; + } + for (j = 0; j < 3; j++) + p_iqk_info->retry_count[0][i][j] = 0x0; + } + } else { + p_iqk_info->iqk_channel[0] = p_iqk_info->rf_reg18; + for (path = 0; path < SS_8821C; path++) { + p_iqk_info->LOK_IDAC[0][path] = odm_get_rf_reg(p_dm_odm, path, 0x58, RFREGOFFSETMASK); + p_iqk_info->bypass_iqk[0][path] = odm_get_bb_reg(p_dm_odm, iqk_apply[path], MASKDWORD); + + for (idx = 0; idx < 2; idx++) { + odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + + if (idx == 0) + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1); + + odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + + for (i = 0; i < 8; i++) { + odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0xe0000001 + (i * 4)); + tmp = odm_get_bb_reg(p_dm_odm, 0x1bfc, MASKDWORD); + p_iqk_info->IQK_CFIR_real[0][path][idx][i] = (tmp & 0x0fff0000) >> 16; + p_iqk_info->IQK_CFIR_imag[0][path][idx][i] = tmp & 0xfff; + } + } + odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0); + } + } +} + +void +_iqk_reload_iqk_setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 channel, + u8 reload_idx /*1: reload TX, 2: reload LO, TX, RX*/ +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i, path, idx; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + for (path = 0; path < SS_8821C; path++) { + for (idx = 0; idx < reload_idx; idx++) { + odm_set_bb_reg(p_dm_odm, 0x1b00, MASKDWORD, 0xf8000008 | path << 1); + odm_set_bb_reg(p_dm_odm, 0x1b2c, MASKDWORD, 0x7); + odm_set_bb_reg(p_dm_odm, 0x1b38, MASKDWORD, 0x20000000); + odm_set_bb_reg(p_dm_odm, 0x1b3c, MASKDWORD, 0x20000000); + odm_set_bb_reg(p_dm_odm, 0x1bcc, MASKDWORD, 0x00000000); + + if (idx == 0) + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x3); + else + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x1); + + odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10); + + for (i = 0; i < 8; i++) { + odm_write_4byte(p_dm_odm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (p_iqk_info->IQK_CFIR_real[channel][path][idx][i] << 9)); + odm_write_4byte(p_dm_odm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (p_iqk_info->IQK_CFIR_imag[channel][path][idx][i] << 9)); + } + } + odm_set_bb_reg(p_dm_odm, iqk_apply[path], MASKDWORD, p_iqk_info->bypass_iqk[channel][path]); + + odm_set_bb_reg(p_dm_odm, 0x1bd8, MASKDWORD, 0x0); + odm_set_bb_reg(p_dm_odm, 0x1b0c, BIT(13) | BIT(12), 0x0); + } +} + +boolean +_iqk_reload_iqk_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean reset +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i; + boolean reload = false; + + if (reset) { + for (i = 0; i < 2; i++) + p_iqk_info->iqk_channel[i] = 0x0; + } else { + p_iqk_info->rf_reg18 = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + + for (i = 0; i < 2; i++) { + if (p_iqk_info->rf_reg18 == p_iqk_info->iqk_channel[i]) { + _iqk_reload_iqk_setting_8821c(p_dm_odm, i, 2); + _iqk_fill_iqk_report_8821c(p_dm_odm, i); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]reload IQK result before!!!!\n")); + reload = true; + } + } + } + return reload; +} + +void +_iqk_rfe_setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean ext_pa_on +) +{ + if (ext_pa_on) { + /*RFE setting*/ + odm_write_4byte(p_dm_odm, 0xcb0, 0x77777777); + odm_write_4byte(p_dm_odm, 0xcb4, 0x00007777); + odm_write_4byte(p_dm_odm, 0xcbc, 0x0000083B); + /*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA on!!!!\n")); + } else { + /*RFE setting*/ + odm_write_4byte(p_dm_odm, 0xcb0, 0x77171117); + odm_write_4byte(p_dm_odm, 0xcb4, 0x00001177); + odm_write_4byte(p_dm_odm, 0xcbc, 0x00000404); + /*odm_write_4byte(p_dm_odm, 0x1990, 0x00000c30);*/ + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]external PA off!!!!\n"));*/ + } +} + +void +_iqk_rfsetting_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + u8 path; + u32 tmp; + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_write_4byte(p_dm_odm, 0x1bb8, 0x00000000); + + for (path = 0; path < SS_8821C; path++) { + /*0xdf:B11 = 1,B4 = 0, B1 = 1*/ + tmp = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK); + tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xdf, RFREGOFFSETMASK, tmp); + + if (p_iqk_info->is_BTG) { + tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK); + tmp = (tmp & (~BIT(4))) | BIT(15); + /*tmp = tmp|BIT4|BIT15; //manual LOK value for A-cut*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xde, RFREGOFFSETMASK, tmp); + } + + if (!p_iqk_info->is_BTG) { + /*WLAN_AG*/ + /*TX IQK mode init*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00024); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x0003f); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x60fde); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, RFREGOFFSETMASK, 0x00000); + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0xdefce); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0); + } else { + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00026); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3e, RFREGOFFSETMASK, 0x00037); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x5efce); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xef, BIT(19), 0x0); + } + } else { + /*WLAN_BTG*/ + /*TX IQK mode init*/ + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xee, RFREGOFFSETMASK, 0x01000); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x33, RFREGOFFSETMASK, 0x00004); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x3f, RFREGOFFSETMASK, 0x01ec1); + odm_set_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0xee, RFREGOFFSETMASK, 0x00000); + } + } +} + +void +_iqk_configure_macbb_8821c( + struct PHY_DM_STRUCT *p_dm_odm +) +{ + /*MACBB register setting*/ + odm_write_1byte(p_dm_odm, 0x522, 0x7f); + odm_set_bb_reg(p_dm_odm, 0x1518, BIT(16), 0x1); + odm_set_bb_reg(p_dm_odm, 0x550, BIT(11) | BIT(3), 0x0); + odm_set_bb_reg(p_dm_odm, 0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/ + odm_set_bb_reg(p_dm_odm, 0x9a4, BIT(31), 0x0); /*0x9a4[31]=0: Select da clock*/ + /*0xc94[0]=1, 0xe94[0]=1: �tx�qiqk���X��/ + odm_set_bb_reg(p_dm_odm, 0xc94, BIT(0), 0x1); + /* 3-wire off*/ + odm_write_4byte(p_dm_odm, 0xc00, 0x00000004); + /*disable PMAC*/ + odm_set_bb_reg(p_dm_odm, 0xb00, BIT(8), 0x0); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set MACBB setting for IQK!!!!\n"));*/ + +} + +void +_iqk_lok_setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 uPADindex +) +{ + u32 LOK0x56_2G = 0x50ef3; + u32 LOK0x56_5G = 0x50ee8; + u32 LOK0x33 = 0; + u32 LOK0x78 = 0xbcbba; + u32 tmp = 0; + + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + LOK0x33 = uPADindex; +/*add delay of MAC send packet*/ + if (p_dm_odm->mp_mode) + odm_set_bb_reg(p_dm_odm, 0x810, BIT(7)|BIT(6)|BIT(5)|BIT(4), 0x8); + + if (p_iqk_info->is_BTG) { + tmp = (LOK0x78 & 0x1c000) >> 14; + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x1b); + odm_write_1byte(p_dm_odm, 0x1b23, 0x00); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + /*0x78[11:0] = IDAC value*/ + LOK0x78 = LOK0x78 & (0xe3fff | ((u32)uPADindex << 14)); + odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, LOK0x78); + odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x05320); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xac018); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xee, BIT(4), 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, BIT(3), 0x0); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK] In the BTG\n")); + } else { + /*tmp = (LOK0x56 & 0xe0) >> 5;*/ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x9); + odm_write_1byte(p_dm_odm, 0x1b23, 0x00); + + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + LOK0x56_2G = LOK0x56_2G & (0xfff1f | ((u32)uPADindex << 5)); + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, LOK0x56_2G); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xadc18); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, BIT(4), 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, BIT(3), 0x0); + break; + case ODM_BAND_5G: + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + LOK0x56_5G = LOK0x56_5G & (0xfff1f | ((u32)uPADindex << 5)); + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, LOK0x56_5G); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xadc18); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xef, BIT(4), 0x1); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, BIT(3), 0x1); + break; + } + } + /*for IDAC LUT by PAD idx*/ + odm_set_rf_reg(p_dm_odm, path, 0x33, BIT(2) | BIT(1) | BIT(0), LOK0x33); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK] LOK0x33 = 0x%x, LOK0x56_2G = 0x%x, LOK0x56_5G = 0x%x,LOK0x78 =0x%x\n", + LOK0x33, LOK0x56_2G, LOK0x56_5G, LOK0x78)); + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set LOK setting!!!!\n"));*/ +} + +void +_iqk_txk_setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + if (p_iqk_info->is_BTG) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x1b); + odm_write_4byte(p_dm_odm, 0x1b20, 0x00840008); + + /*0x78[11:0] = IDAC value*/ + odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, 0xbcbba); + odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x04320); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xac018); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + } else { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x9); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01440008); + + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x50EF3); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xadc18); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + break; + case ODM_BAND_5G: + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x50EF0); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c18); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + break; + } + + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set TXK setting!!!!\n"));*/ +} + +void +_iqk_rxk1setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + if (p_iqk_info->is_BTG) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x09); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); + odm_write_4byte(p_dm_odm, 0x1b24, 0x01460c88); + + /*0x78[11:0] = IDAC value*/ + odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, 0x8cbba); + odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x00320); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa8018); + } else { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + odm_write_1byte(p_dm_odm, 0x1bcc, 0x12); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); + odm_write_4byte(p_dm_odm, 0x1b24, 0x01461068); + + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x510f3); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + case ODM_BAND_5G: + odm_write_1byte(p_dm_odm, 0x1bcc, 0x9); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_write_4byte(p_dm_odm, 0x1b20, 0x00450008); + odm_write_4byte(p_dm_odm, 0x1b24, 0x00461468); + + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x510f3); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + } + } + /*ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/ +} + +static u8 btg_lna[5] = {0x0, 0x4, 0x8, 0xc, 0xf}; +static u8 wlg_lna[5] = {0x0, 0x1, 0x2, 0x3, 0x5}; +static u8 wla_lna[5] = {0x0, 0x1, 0x3, 0x4, 0x5}; + +void +_iqk_rxk2setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + boolean is_gs +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + if (p_iqk_info->is_BTG) { + if (is_gs) { + p_iqk_info->tmp1bcc = 0x1b; + p_iqk_info->lna_idx = 2; + } + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x80); + odm_write_4byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); + odm_write_4byte(p_dm_odm, 0x1b24, (0x01460048 | (btg_lna[p_iqk_info->lna_idx] << 10))); + /*0x78[11:0] = IDAC value*/ + odm_set_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK, 0x8cbba); + odm_set_rf_reg(p_dm_odm, path, 0x5c, RFREGOFFSETMASK, 0x00320); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa8018); + } else { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + switch (*p_dm_odm->p_band_type) { + case ODM_BAND_2_4G: + if (is_gs) { + p_iqk_info->tmp1bcc = 0x12; + p_iqk_info->lna_idx = 2; + } + odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_write_4byte(p_dm_odm, 0x1b20, 0x01450008); + odm_write_4byte(p_dm_odm, 0x1b24, (0x01460048 | (wlg_lna[p_iqk_info->lna_idx] << 10))); + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x510f3); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + case ODM_BAND_5G: + if (is_gs) { + p_iqk_info->tmp1bcc = 0x12; + p_iqk_info->lna_idx = 2; + } + odm_write_1byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); + odm_write_1byte(p_dm_odm, 0x1b2b, 0x00); + odm_write_4byte(p_dm_odm, 0x1b20, 0x00450008); + odm_write_4byte(p_dm_odm, 0x1b24, (0x01460048 | (wla_lna[p_iqk_info->lna_idx] << 10))); + odm_set_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK, 0x51000); + odm_set_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK, 0xa9c00); + break; + } + } + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Set RXK setting!!!!\n"));*/ + +} + +boolean +_iqk_check_cal_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 IQK_CMD +) +{ + boolean notready = true, fail = true; + u32 delay_count = 0x0; + + while (notready) { + if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f)) { + fail = (boolean) odm_get_bb_reg(p_dm_odm, 0x1b08, BIT(26)); + notready = false; + } else { + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + fail = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]IQK timeout!!!\n")); + break; + } + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]delay count = 0x%x!!!\n", delay_count)); + return fail; +} + +boolean +_iqk_rx_iqk_gain_search_fail_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 step +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + boolean fail = true; + u32 IQK_CMD = 0x0, rf_reg0, tmp, rxbb; + u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24}, *plna; + u8 idx; + + if (p_iqk_info->is_BTG) + plna = btg_lna; + else if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) + plna = wlg_lna; + else + plna = wla_lna; + + for (idx = 0; idx < 4; idx++) + if (p_iqk_info->tmp1bcc == IQMUX[idx]) + break; + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1bcc, p_iqk_info->tmp1bcc); + + if (step == RXIQK1) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d RXIQK GainSearch ============\n", p_iqk_info->is_BTG)); + + if (step == RXIQK1) + IQK_CMD = 0xf8000208 | (1 << (path + 4)); + else + IQK_CMD = 0xf8000308 | (1 << (path + 4)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S%d GS%d_Trigger = 0x%x\n", path, step, IQK_CMD)); + + _iqk_set_gnt_wl_gnt_bt(p_dm_odm, true); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1); + ODM_delay_ms(GS_delay_8821C); + fail = _iqk_check_cal_8821c(p_dm_odm, IQK_CMD); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c))); + _iqk_set_gnt_wl_gnt_bt(p_dm_odm, false); + + if (step == RXIQK2) { + rf_reg0 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n", path, rf_reg0, p_iqk_info->tmp1bcc, idx, odm_read_4byte(p_dm_odm, 0x1b3c))); + tmp = (rf_reg0 & 0x1fe0) >> 5; + rxbb = tmp & 0x1f; + + if (rxbb == 0x1) { + if (idx != 3) + idx++; + else if (p_iqk_info->lna_idx != 0x0) + p_iqk_info->lna_idx--; + else + p_iqk_info->isbnd = true; + fail = true; + } else if (rxbb == 0xa) { + if (idx != 0) + idx--; + else if (p_iqk_info->lna_idx != 0x4) + p_iqk_info->lna_idx++; + else + p_iqk_info->isbnd = true; + fail = true; + } else + fail = false; + + if (p_iqk_info->isbnd == true) + fail = false; + + p_iqk_info->tmp1bcc = IQMUX[idx]; + + if (fail) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + odm_write_4byte(p_dm_odm, 0x1b24, (odm_read_4byte(p_dm_odm, 0x1b24) & 0xffffc3ff) | (*(plna + p_iqk_info->lna_idx) << 10)); + } + } + return fail; +} + +boolean +_lok_one_shot_8821c( + struct PHY_DM_STRUCT *p_dm_void, + u8 path, + u8 uPADindex + +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 delay_count = 0; + boolean LOK_notready = false; + u32 LOK_temp2 = 0, LOK_temp3 = 0; + u32 IQK_CMD = 0x0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==========S%d LOK ==========\n", p_iqk_info->is_BTG)); + + IQK_CMD = 0xf8000008 | (1 << (4 + path)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]LOK_Trigger = 0x%x\n", IQK_CMD)); + + _iqk_set_gnt_wl_gnt_bt(p_dm_odm, true); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 1); + /*LOK: CMD ID = 0 {0xf8000018, 0xf8000028}*/ + /*LOK: CMD ID = 0 {0xf8000019, 0xf8000029}*/ + ODM_delay_ms(LOK_delay_8821C); + + delay_count = 0; + LOK_notready = true; + + while (LOK_notready) { + if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f)) + LOK_notready = false; + else + LOK_notready = true; + + if (LOK_notready) { + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]S%d LOK timeout!!!\n", path)); + break; + } + } + + _iqk_set_gnt_wl_gnt_bt(p_dm_odm, false); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count)); + + if (!LOK_notready) { + LOK_temp2 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x8, RFREGOFFSETMASK); + LOK_temp3 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x58, RFREGOFFSETMASK); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]0x8 = 0x%x, 0x58 = 0x%x\n", LOK_temp2, LOK_temp3)); + } else { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==>S%d LOK Fail!!!\n", path)); + } + p_iqk_info->LOK_fail[path] = LOK_notready; + + /*fill IDAC LUT table*/ + /* + for (i = 0; i < 8; i++) { + odm_set_rf_reg(p_dm_odm, path, 0x33, BIT(2)|BIT(1)|BIT(0), i); + odm_set_rf_reg(p_dm_odm, path, 0x8, RFREGOFFSETMASK, LOK_temp2); + } + */ + return LOK_notready; +} + +boolean +_iqk_one_shot_8821c( + void *p_dm_void, + u8 path, + u8 idx +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 delay_count = 0; + boolean notready = true, fail = true; + u32 IQK_CMD = 0x0; + u16 iqk_apply[2] = {0xc94, 0xe94}; + + if (idx == TX_IQK) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBTXIQK ============\n", p_iqk_info->is_BTG)); + else if (idx == RXIQK1) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP1============\n", p_iqk_info->is_BTG)); + else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]============ S%d WBRXIQK STEP2============\n", p_iqk_info->is_BTG)); + + if (idx == TXIQK) { + IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 4) << 8) | (1 << (path + 4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]TXK_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/ + /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/ + /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/ + } else if (idx == RXIQK1) { + if (*p_dm_odm->p_band_width == 2) + IQK_CMD = 0xf8000808 | (1 << (path + 4)); + else + IQK_CMD = 0xf8000708 | (1 << (path + 4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/ + /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/ + /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/ + } else if (idx == RXIQK2) { + IQK_CMD = 0xf8000008 | ((*p_dm_odm->p_band_width + 9) << 8) | (1 << (path + 4)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD)); + /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/ + /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/ + /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/ + } + + _iqk_set_gnt_wl_gnt_bt(p_dm_odm, true); + + odm_write_4byte(p_dm_odm, 0x1bc8, 0x80000000); + odm_write_4byte(p_dm_odm, 0x8f8, 0x41400080); + + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD); + odm_write_4byte(p_dm_odm, 0x1b00, IQK_CMD + 0x1); + ODM_delay_ms(WBIQK_delay_8821C); + + while (notready) { + if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/ + notready = false; + else + notready = true; + + if (notready) { + ODM_delay_ms(1); + delay_count++; + } else { + fail = (boolean) odm_get_bb_reg(p_dm_odm, 0x1b08, BIT(26)); + break; + } + + if (delay_count >= 50) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]S%d IQK timeout!!!\n", path)); + break; + } + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c))); + _iqk_set_gnt_wl_gnt_bt(p_dm_odm, false); + + if (p_dm_odm->debug_components && ODM_COMP_CALIBRATION) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path, odm_read_4byte(p_dm_odm, 0x1b00), odm_read_4byte(p_dm_odm, 0x1b08))); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> delay_count = 0x%x\n", path, delay_count)); + if (idx != TXIQK) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]S%d ==> RF0x0 = 0x%x, RF0x%x = 0x%x\n", path, + odm_get_rf_reg(p_dm_odm, path, 0x0, RFREGOFFSETMASK), (p_iqk_info->is_BTG) ? 0x78 : 0x56, + (p_iqk_info->is_BTG) ? odm_get_rf_reg(p_dm_odm, path, 0x78, RFREGOFFSETMASK) : odm_get_rf_reg(p_dm_odm, path, 0x56, RFREGOFFSETMASK))); + } + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | path << 1); + if (idx == TXIQK) + if (fail) + odm_set_bb_reg(p_dm_odm, iqk_apply[path], BIT(0), 0x0); + + if (idx == RXIQK2) { + p_iqk_info->RXIQK_AGC[0][path] = + (u16)(((odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x0, RFREGOFFSETMASK) >> 5) & 0xff) | + (p_iqk_info->tmp1bcc << 8)); + + odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000); + + if (!fail) + odm_set_bb_reg(p_dm_odm, iqk_apply[path], (BIT(11) | BIT(10)), 0x1); + else + odm_set_bb_reg(p_dm_odm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0); + } + + if (idx == TXIQK) + p_iqk_info->IQK_fail_report[0][path][TXIQK] = fail; + else + p_iqk_info->IQK_fail_report[0][path][RXIQK] = fail; + + return fail; +} + +boolean +_iqk_rxiqkbystep_8821c( + void *p_dm_void, + u8 path +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + boolean KFAIL = true, gonext; + + switch (p_iqk_info->rxiqk_step) { + case 1: /*gain search_RXK1*/ + _iqk_rxk1setting_8821c(p_dm_odm, path); + gonext = false; + while (1) { + KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(p_dm_odm, path, RXIQK1); + if (KFAIL && (p_iqk_info->gs_retry_count[0][path][0] < 2)) + p_iqk_info->gs_retry_count[0][path][0]++; + else if (KFAIL) { + p_iqk_info->RXIQK_fail_code[0][path] = 0; + p_iqk_info->rxiqk_step = 5; + gonext = true; + } else { + p_iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + break; + case 2: /*gain search_RXK2*/ + _iqk_rxk2setting_8821c(p_dm_odm, path, true); + p_iqk_info->isbnd = false; + while (1) { + KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(p_dm_odm, path, RXIQK2); + if (KFAIL && (p_iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit)) + p_iqk_info->gs_retry_count[0][path][1]++; + else { + p_iqk_info->rxiqk_step++; + break; + } + } + break; + case 3: /*RXK1*/ + _iqk_rxk1setting_8821c(p_dm_odm, path); + gonext = false; + while (1) { + KFAIL = _iqk_one_shot_8821c(p_dm_odm, path, RXIQK1); + if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK1] < 2)) + p_iqk_info->retry_count[0][path][RXIQK1]++; + else if (KFAIL) { + p_iqk_info->RXIQK_fail_code[0][path] = 1; + p_iqk_info->rxiqk_step = 5; + gonext = true; + } else { + p_iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + break; + case 4: /*RXK2*/ + _iqk_rxk2setting_8821c(p_dm_odm, path, false); + gonext = false; + while (1) { + KFAIL = _iqk_one_shot_8821c(p_dm_odm, path, RXIQK2); + if (KFAIL && (p_iqk_info->retry_count[0][path][RXIQK2] < 2)) + p_iqk_info->retry_count[0][path][RXIQK2]++; + else if (KFAIL) { + p_iqk_info->RXIQK_fail_code[0][path] = 2; + p_iqk_info->rxiqk_step = 5; + gonext = true; + } else { + p_iqk_info->rxiqk_step++; + gonext = true; + } + if (gonext) + break; + } + break; + } + return KFAIL; +} + +void +_iqk_iqk_by_path_8821c( + void *p_dm_void, + boolean segment_iqk +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + boolean KFAIL = true; + u8 i, kcount_limit; + u32 cnt_iqk_fail = 0; + /* ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]iqk_step = 0x%x\n", p_dm_odm->rf_calibrate_info.iqk_step)); */ + + if (*p_dm_odm->p_band_width == 2) + kcount_limit = kcount_limit_80m; + else + kcount_limit = kcount_limit_others; + + while (1) { + switch (p_dm_odm->rf_calibrate_info.iqk_step) { + case 1: /*S0 LOK*/ + for (i = 0; i < 8 ; i++) {/* the LOK Cal in the each PAD stage*/ + _iqk_lok_setting_8821c(p_dm_odm, ODM_RF_PATH_A, i); + _lok_one_shot_8821c(p_dm_odm, ODM_RF_PATH_A, i); + } + p_dm_odm->rf_calibrate_info.iqk_step++; + break; + case 2: /*S0 TXIQK*/ + _iqk_txk_setting_8821c(p_dm_odm, ODM_RF_PATH_A); + KFAIL = _iqk_one_shot_8821c(p_dm_odm, ODM_RF_PATH_A, TXIQK); + p_iqk_info->kcount++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]KFail = 0x%x\n", KFAIL)); + if (KFAIL) + cnt_iqk_fail++; + if (KFAIL && (p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK] < 3)) + p_iqk_info->retry_count[0][ODM_RF_PATH_A][TXIQK]++; + else + p_dm_odm->rf_calibrate_info.iqk_step++; + break; + case 3: /*S0 RXIQK*/ + while (1) { + KFAIL = _iqk_rxiqkbystep_8821c(p_dm_odm, ODM_RF_PATH_A); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]S0RXK KFail = 0x%x\n", KFAIL)); + if (p_iqk_info->rxiqk_step == 5) { + p_dm_odm->rf_calibrate_info.iqk_step++; + p_iqk_info->rxiqk_step = 1; + if (KFAIL) { + cnt_iqk_fail++; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]S0RXK fail code: %d!!!\n", p_iqk_info->RXIQK_fail_code[0][ODM_RF_PATH_A])); + } + break; + } + } + p_iqk_info->kcount++; + break; + } + + if (p_dm_odm->rf_calibrate_info.iqk_step == 4) { + for (i = 0; i < SS_8821C; i++) { + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008 | i << 1); + odm_write_4byte(p_dm_odm, 0x1b2c, 0x7); + odm_write_4byte(p_dm_odm, 0x1bcc, 0x0); + odm_write_4byte(p_dm_odm, 0x1b38, 0x20000000); + } + break; + } + + p_dm_odm->n_iqk_cnt++; + + if (cnt_iqk_fail == 0) + p_dm_odm->n_iqk_ok_cnt++; + else + p_dm_odm->n_iqk_fail_cnt = p_dm_odm->n_iqk_fail_cnt + cnt_iqk_fail; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("All/Ok/Fail = %d %d %d\n", p_dm_odm->n_iqk_cnt, p_dm_odm->n_iqk_ok_cnt, p_dm_odm->n_iqk_fail_cnt)); + + if ((segment_iqk == true) && (p_iqk_info->kcount == kcount_limit)) + break; + + } +} + +void +_iqk_start_iqk_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean segment_iqk +) +{ + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + u32 tmp; + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_write_4byte(p_dm_odm, 0x1bb8, 0x00000000); + + /*GNT_WL = 1*/ + if (p_iqk_info->is_BTG) { + tmp = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK); + tmp = (tmp & (~BIT(3))) | BIT(0) | BIT(2); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x1, RFREGOFFSETMASK, tmp); + } + + _iqk_iqk_by_path_8821c(p_dm_odm, segment_iqk); +} + +void +_iq_calibrate_8821c_init( + void *p_dm_void +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + u8 i, j, k, m; + + if (p_iqk_info->iqk_times == 0x0) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]=====>PHY_IQCalibrate_8821C_Init\n")); + + for (i = 0; i < SS_8821C; i++) { + for (j = 0; j < 2; j++) { + p_iqk_info->LOK_fail[i] = true; + p_iqk_info->IQK_fail[j][i] = true; + p_iqk_info->iqc_matrix[j][i] = 0x20000000; + } + } + + for (i = 0; i < 2; i++) { + p_iqk_info->iqk_channel[i] = 0x0; + + for (j = 0; j < SS_8821C; j++) { + p_iqk_info->LOK_IDAC[i][j] = 0x0; + p_iqk_info->RXIQK_AGC[i][j] = 0x0; + p_iqk_info->bypass_iqk[i][j] = 0x0; + + for (k = 0; k < 2; k++) { + p_iqk_info->IQK_fail_report[i][j][k] = true; + for (m = 0; m < 8; m++) { + p_iqk_info->IQK_CFIR_real[i][j][k][m] = 0x0; + p_iqk_info->IQK_CFIR_imag[i][j][k][m] = 0x0; + } + } + + for (k = 0; k < 3; k++) + p_iqk_info->retry_count[i][j][k] = 0x0; + } + } + } +} +/* +void +_DPK_BackupReg_8821C( + struct PHY_DM_STRUCT* p_dm_odm, + static u32* DPK_backup, + u32* backup_dpk_reg + ) +{ + + u32 i; + + for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++) + DPK_backup[i] = odm_read_4byte(p_dm_odm, backup_dpk_reg[i]); + +} +void +_DPK_Restore_8821C( + struct PHY_DM_STRUCT* p_dm_odm, + static u32* DPK_backup, + u32* backup_dpk_reg + ) +{ + u32 i; + for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++) + odm_write_4byte(p_dm_odm, backup_dpk_reg[i], DPK_backup[i]); +} + +*/ +void +_dpk_dpk_setting_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]==========Start the DPD setting Initilaize/n")); + /*AFE setting*/ + odm_write_4byte(p_dm_odm, 0xc60, 0x50000000); + odm_write_4byte(p_dm_odm, 0xc60, 0x700F0040); + odm_write_4byte(p_dm_odm, 0xc5c, 0xd1000120); + odm_write_4byte(p_dm_odm, 0xc58, 0xd8000402); + odm_write_4byte(p_dm_odm, 0xc6c, 0x00000a15); + odm_write_4byte(p_dm_odm, 0xc00, 0x00000000); + /*_iqk_bb_reset_8821c(p_dm_odm);*/ + odm_write_4byte(p_dm_odm, 0xe5c, 0xD1000120); + odm_write_4byte(p_dm_odm, 0xc6c, 0x00000A15); + odm_write_4byte(p_dm_odm, 0xe6c, 0x00000A15); + odm_write_4byte(p_dm_odm, 0x808, 0x2D028200); + odm_write_4byte(p_dm_odm, 0x810, 0x20101063); + odm_write_4byte(p_dm_odm, 0x90c, 0x0B00C000); + odm_write_4byte(p_dm_odm, 0x9a4, 0x00000080); + odm_write_4byte(p_dm_odm, 0xc94, 0x01000101); + odm_write_4byte(p_dm_odm, 0xe94, 0x01000101); + odm_write_4byte(p_dm_odm, 0xe5c, 0xD1000120); + odm_write_4byte(p_dm_odm, 0xc6c, 0x00000A15); + odm_write_4byte(p_dm_odm, 0xe6c, 0x00000A15); + + odm_write_4byte(p_dm_odm, 0x808, 0x2D028200); + odm_write_4byte(p_dm_odm, 0x810, 0x20101063); + odm_write_4byte(p_dm_odm, 0x90c, 0x0B00C000); + odm_write_4byte(p_dm_odm, 0x9a4, 0x00000080); + odm_write_4byte(p_dm_odm, 0xc94, 0x01000101); + odm_write_4byte(p_dm_odm, 0xe94, 0x01000101); + odm_write_4byte(p_dm_odm, 0x1904, 0x00020000); + /*path A*/ + odm_set_bb_reg(p_dm_odm, 0x1d00, MASKDWORD, 0x30303030); /* cck */ + odm_set_bb_reg(p_dm_odm, 0x1d04, MASKDWORD, 0x30303030); /* ofdm 6M/9M/12M/18M */ + odm_set_bb_reg(p_dm_odm, 0x1d08, MASKDWORD, 0x30303030); /* ofdm 24M/36M/48M/54M */ + odm_set_bb_reg(p_dm_odm, 0x1d0c, MASKDWORD, 0x30303030); /* mcs0~3 */ + odm_set_bb_reg(p_dm_odm, 0x1d10, MASKDWORD, 0x30303030); /* mcs4~7 */ + odm_set_bb_reg(p_dm_odm, 0x1d2c, MASKDWORD, 0x30303030); /* vht_1ss_mcs0~3 */ + odm_set_bb_reg(p_dm_odm, 0x1d30, MASKDWORD, 0x30303030); /* vht_1ss_mcs4~7 */ + odm_set_bb_reg(p_dm_odm, 0x1d34, 0x0000FFFF, 0x3030); /* vht_1ss_mcs8/9 */ + + /*RF*/ + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xEF, RFREGOFFSETMASK, 0x80000); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x33, RFREGOFFSETMASK, 0x00024); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x3E, RFREGOFFSETMASK, 0x0003F); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x3F, RFREGOFFSETMASK, 0xCBFCE); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0xEF, RFREGOFFSETMASK, 0x00000); + /*AGC boundary selection*/ + odm_write_4byte(p_dm_odm, 0x1bbc, 0x0001abf6); + odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018); + odm_write_4byte(p_dm_odm, 0x1bb8, 0x000fffff); + odm_write_4byte(p_dm_odm, 0x1bc8, 0x000c55aa); + /*odm_write_4byte(p_dm_odm, 0x1bcc, 0x11978200);*/ + odm_write_4byte(p_dm_odm, 0x1bcc, 0x11978800); + odm_write_4byte(p_dm_odm, 0xcb0, 0x77775747); + odm_write_4byte(p_dm_odm, 0xcb4, 0x100000f7); + odm_write_4byte(p_dm_odm, 0xcbc, 0x0); +} + +void +_dpk_dpk_boundary_selection_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + u8 tmp_pad, compared_pad; + u32 rf_backup_reg00; + u32 boundaryselect = 0; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]Start the DPD boundary selection\n")); + rf_backup_reg00 = odm_get_rf_reg(p_dm_odm, (enum odm_rf_radio_path_e)path, 0x00, RFREGOFFSETMASK); + tmp_pad = 0; + compared_pad = 0; + boundaryselect = 0; + boundaryselect = 0x0; + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_backup_reg00); + odm_write_4byte(p_dm_odm, 0x1bbc, boundaryselect); + +} + +u8 +_dpk_get_dpk_tx_agc_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path +) +{ + + u8 tx_agc_init_value = 0x1f; /* DPK TXAGC value*/ + u32 rf_reg00 = 0x0; + u8 gainloss = 0x1; + u8 best_tx_agc ; + u8 tmp; + u8 i = 0; + boolean notready = true; + u8 delay_count = 0x0; + /* rf_reg00 = 0x40000 + tx_agc_init_value; set TXAGC value */ + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + tx_agc_init_value = 0x1d; + rf_reg00 = 0x40000 + tx_agc_init_value; /* set TXAGC value*/ + odm_write_4byte(p_dm_odm, 0x1bc8, 0x000c55aa); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8F, RFREGOFFSETMASK, 0xA9C00); + } else { + tx_agc_init_value = 0x17; + rf_reg00 = 0x44000 + tx_agc_init_value; /* set TXAGC value*/ + odm_write_4byte(p_dm_odm, 0x1bc8, 0x000c44aa); + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x8F, RFREGOFFSETMASK, 0xAEC00); + } + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_reg00); + odm_set_bb_reg(p_dm_odm, 0x1b8c, BIT(15) | BIT(14) | BIT(13), gainloss); + odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000d18); + /*ODM_delay_ms(1);*/ + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000d19); + ODM_delay_ms(2); + + while (notready) { + if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/ + notready = false; + else + notready = true; + + if (notready) { + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[DPK]S%d DPK_GetDPKTXAGC_8821C timeout!!!\n", path)); + break; + } + } + + odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("rf_reg00 =0x%x, 0x8F =0x%x\n", odm_get_rf_reg(p_dm_odm, path, 0x00, RFREGOFFSETMASK), odm_get_rf_reg(p_dm_odm, path, 0x8f, RFREGOFFSETMASK))); + + odm_write_4byte(p_dm_odm, 0x1bd4, 0x60001); + tmp = (u8)odm_read_4byte(p_dm_odm, 0x1bfc); + best_tx_agc = tx_agc_init_value - (0xa - tmp); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK](2), 0x1b8c =0x%x, delay_count=%d, rf_reg00 = 0x%x, 0x1b00 = 0x%x, 0x1bfc = 0x%x, 0x1bd4 = 0x%x,best_tx_agc =0x%x, tmp =0x%x, delay =%d ms\n", + odm_read_4byte(p_dm_odm, 0x1b8c), delay_count, rf_reg00, odm_read_4byte(p_dm_odm, 0x1b00), odm_read_4byte(p_dm_odm, 0x1bfc), odm_read_4byte(p_dm_odm, 0x1bd4), best_tx_agc, tmp, i * 2)); + /* dbg message*/ + return best_tx_agc; +} + +boolean +_dpk_enable_dpk_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 best_tx_agc +) +{ + u32 rf_reg00 = 0x0; + u32 tmp; + boolean fail = true; + boolean notready = true; + u8 delay_count = 0x0; + + if (*p_dm_odm->p_band_type == ODM_BAND_5G) { + rf_reg00 = 0x40000 + best_tx_agc; /* set TXAGC value*/ + } else { + rf_reg00 = 0x44000 + best_tx_agc; /* set TXAGC value*/ + } + odm_set_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x00, RFREGOFFSETMASK, rf_reg00); + ODM_delay_ms(1); + odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1); + odm_write_4byte(p_dm_odm, 0x8f8, 0x41400080); + ODM_delay_ms(1); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000e18); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000e19); + + ODM_delay_ms(5); + while (notready) { + if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/ + notready = false; + else + notready = true; + + if (notready) { + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[DPK]S%d DPK_GetDPKTXAGC_8821C timeout!!!\n", path)); + break; + } + } + + odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018); + odm_write_4byte(p_dm_odm, 0x1bd4, 0xA0001); + tmp = odm_read_4byte(p_dm_odm, 0x1bfc); + + if ((odm_read_4byte(p_dm_odm, 0x1b08) & 0x0f000000) == 0x0) + fail = false; + else + fail = true; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK] (3), delay_count= %d, 0x1b0b = 0x%x, 0x1bc8 = 0x%x, rf_reg00 = 0x%x, ,0x1bfc = 0x%x, 0x1b90=0x%x, 0x1b94=0x%x\n", + delay_count, odm_read_1byte(p_dm_odm, 0x1b0b), odm_read_4byte(p_dm_odm, 0x1bc8), rf_reg00, tmp, odm_read_4byte(p_dm_odm, 0x1b90), odm_read_4byte(p_dm_odm, 0x1b94))); + /* dbg message*/ + return fail; +} + +boolean +_dpk_enable_dpd_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 path, + u8 best_tx_agc +) +{ + + boolean fail = true; + u8 tmp; + u8 offset = 0x0; + boolean notready = true; + u8 delay_count = 0x0; + + odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1); + odm_write_4byte(p_dm_odm, 0x8f8, 0x41400080); + ODM_delay_ms(1); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000f18); + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000f19); + ODM_delay_ms(30); + while (notready) { + if (odm_read_4byte(p_dm_odm, 0xfa0) & BIT(27))/*if (odm_read_4byte(p_dm_odm, 0x1b00) == (IQK_CMD & 0xffffff0f))*/ + notready = false; + else + notready = true; + + if (notready) { + ODM_delay_ms(1); + delay_count++; + } + + if (delay_count >= 50) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[DPK]S%d DPK_GetDPKTXAGC_8821C timeout!!!\n", path)); + break; + } + } + odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018); + odm_write_4byte(p_dm_odm, 0x1b90, 0x0001e018); + odm_write_4byte(p_dm_odm, 0x1bd4, 0xA0001); + tmp = odm_read_1byte(p_dm_odm, 0x1bfc); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK](4) init 0x1b08 =%x, 0x1bc8 = 0x%x,0x1bfc = 0x%x, ,0x1bd0 = 0x%x, offset =%x, 1bcc =%x\n", + odm_read_4byte(p_dm_odm, 0x1b08), odm_read_4byte(p_dm_odm, 0x1bc8), tmp, odm_read_4byte(p_dm_odm, 0x1bd0), offset, odm_read_4byte(p_dm_odm, 0x1bcc))); + + /*if( (odm_read_4byte(p_dm_odm, 0x1b08) & 0x0f000000) == 0x0)*/ + if (true) { + odm_write_4byte(p_dm_odm, 0x1b98, 0x48004800); + odm_write_4byte(p_dm_odm, 0x1bdc, 0x0); + + if (best_tx_agc >= 0x19) + offset = best_tx_agc - 0x19; + else + offset = 0x20 - (0x19 - best_tx_agc); + odm_set_bb_reg(p_dm_odm, 0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), offset); + + fail = false; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK](4) OK 0x1b08 =%x, 0x1bc8 = 0x%x,0x1bfc = 0x%x, ,0x1bd0 = 0x%x, offset =%x, 1bcc =%x\n", + odm_read_4byte(p_dm_odm, 0x1b08), odm_read_4byte(p_dm_odm, 0x1bc8), tmp, odm_read_4byte(p_dm_odm, 0x1bd0), offset, odm_read_4byte(p_dm_odm, 0x1bcc))); + } else + fail = true; + + return fail; + +} +void +phy_dpd_calibrate_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean reset +) +{ + + u32 backup_dpdbb[3]; + u8 best_tx_agc = 0x1c; + u32 MAC_backup[MAC_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1]; + u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518}; + u32 BB_backup[DPK_BB_REG_NUM_8821C]; + u32 backup_bb_reg[DPK_BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04 + , 0xc58, 0xc5c, 0xe58, 0xe5c, 0xc6c, 0xe6c, 0x810, 0x90c, 0xc94, 0xe94, 0x1904, 0xcb0, 0xcb4, 0xcbc, 0xc00 + }; + u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x65, 0x0, 0x1}; + u8 i; + u32 backup_dpk_reg[3] = {0x1bd0, 0x1b98, 0x1bbc}; + + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + p_iqk_info->is_BTG = (boolean) odm_get_bb_reg(p_dm_odm, 0xcb8, BIT(16)); + if (!p_dm_odm->mp_mode) + if (_iqk_reload_iqk_8821c(p_dm_odm, reset)) + return; + /*2G is not stable*/ + /* if (!(*p_dm_odm->p_band_type == ODM_BAND_5G)) return; */ + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]==========DPK strat!!!!!==========\n")); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[DPK]p_band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*p_dm_odm->p_band_type == ODM_BAND_5G) ? "5G" : "2G", *p_dm_odm->p_band_width, p_dm_odm->ext_pa, p_dm_odm->ext_pa_5g)); + _iqk_backup_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C); + _iqk_afe_setting_8821c(p_dm_odm, true); + _iqk_backup_rf_8821c(p_dm_odm, RF_backup, backup_rf_reg); + + + if (p_iqk_info->is_BTG) { + } else { + if (*p_dm_odm->p_band_type == ODM_BAND_2_4G) + odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(8), 0x1); + else + odm_set_bb_reg(p_dm_odm, 0xcb8, BIT(8), 0x0); + } + + /*backup 0x1b2c, 1b38,0x1b3c*/ + { + backup_dpdbb[0] = odm_read_4byte(p_dm_odm, 0x1b2c); + } + { + backup_dpdbb[1] = odm_read_4byte(p_dm_odm, 0x1b38); + } + { + backup_dpdbb[2] = odm_read_4byte(p_dm_odm, 0x1b3c); + } + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]In DPD Proces(1), Backup\n")); + + /*PDK Init Register setting*/ + _dpk_dpk_setting_8821c(p_dm_odm, ODM_RF_PATH_A); + _dpk_dpk_boundary_selection_8821c(p_dm_odm, ODM_RF_PATH_A); + odm_set_bb_reg(p_dm_odm, 0x1bc8, BIT(31), 0x1); + odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5); + /* Get the best TXAGC*/ + + best_tx_agc = _dpk_get_dpk_tx_agc_8821c(p_dm_odm, ODM_RF_PATH_A); + ODM_delay_ms(2); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]In DPD Process(2), Best TXAGC = 0x%x\n", best_tx_agc)); + + if (_dpk_enable_dpk_8821c(p_dm_odm, ODM_RF_PATH_A, best_tx_agc)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]In DPD Process(3), DPK process is Fail\n")); + } + ODM_delay_ms(2); + if (_dpk_enable_dpd_8821c(p_dm_odm, ODM_RF_PATH_A, best_tx_agc)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]In DPD Process(4), DPD process is Fail\n")); + } + /* restore IQK */ + p_iqk_info->rf_reg18 = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK]reload IQK result before, p_iqk_info->rf_reg18=0x%x, p_iqk_info->iqk_channel[0]=0x%x, p_iqk_info->iqk_channel[1]=0x%x!!!!\n", p_iqk_info->rf_reg18, p_iqk_info->iqk_channel[0], p_iqk_info->iqk_channel[1])); + _iqk_reload_iqk_setting_8821c(p_dm_odm, 0, 2); + _iqk_fill_iqk_report_8821c(p_dm_odm, 0); + /* Restore setup */ + odm_set_bb_reg(p_dm_odm, 0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5); + odm_set_bb_reg(p_dm_odm, 0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0); + odm_set_bb_reg(p_dm_odm, 0x1b00, BIT(2) | BIT(1), 0x0); + odm_set_bb_reg(p_dm_odm, 0x1b08, BIT(6) | BIT(5), 0x2); + + odm_write_4byte(p_dm_odm, 0x1b2c, backup_dpdbb[0]); + odm_write_4byte(p_dm_odm, 0x1b38, backup_dpdbb[1]); + odm_write_4byte(p_dm_odm, 0x1b3c, backup_dpdbb[2]); + /*enable DPK*/ + odm_set_bb_reg(p_dm_odm, 0x1b2c, BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x5); + /*enable boundary condition*/ + odm_write_4byte(p_dm_odm, 0x1bcc, 0x11868800); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]In DPD Process(5), Restore\n")); + _iqk_restore_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C); + _iqk_afe_setting_8821c(p_dm_odm, false); + _iqk_restore_rf_8821c(p_dm_odm, backup_rf_reg, RF_backup); + /* backup the DPK current result*/ + for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++) + dpk_result[i] = odm_read_4byte(p_dm_odm, backup_dpk_reg[i]); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[DPK]the DPD calibration Process Finish (6), dpk_result = 0x%x\n", dpk_result[0])); + return; +} + +void +_phy_iq_calibrate_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + boolean reset +) +{ + + u32 MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1]; + u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518}; + u32 backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04, 0xb00}; + u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x65, 0x0, 0x1}; + boolean segment_iqk = false, is_mp = false; + + struct _IQK_INFORMATION *p_iqk_info = &p_dm_odm->IQK_info; + + if (p_dm_odm->mp_mode) + is_mp = true; + else if (p_dm_odm->is_linked) + segment_iqk = false; + + p_iqk_info->is_BTG = (boolean)odm_get_bb_reg(p_dm_odm, 0xcb8, BIT(16)); + + if (!is_mp) + if (_iqk_reload_iqk_8821c(p_dm_odm, reset)) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==========IQK strat!!!!!==========\n")); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]p_band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n", (*p_dm_odm->p_band_type == ODM_BAND_5G) ? "5G" : "2G", *p_dm_odm->p_band_width, p_dm_odm->ext_pa, p_dm_odm->ext_pa_5g)); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]Interface = %d, cut_version = %x\n", p_dm_odm->support_interface, p_dm_odm->cut_version)); + + p_iqk_info->tmp_GNTWL = _iqk_indirect_read_reg(p_dm_odm, 0x38); + + p_iqk_info->iqk_times++; + p_iqk_info->kcount = 0; + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time = 0; + p_dm_odm->rf_calibrate_info.iqk_step = 1; + p_iqk_info->rxiqk_step = 1; + + _iqk_backup_iqk_8821c(p_dm_odm, 0); + _iqk_backup_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg,BB_REG_NUM_8821C); + _iqk_backup_rf_8821c(p_dm_odm, RF_backup, backup_rf_reg); + + while (1) { + if (!is_mp) + p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); + + _iqk_configure_macbb_8821c(p_dm_odm); + _iqk_afe_setting_8821c(p_dm_odm, true); + _iqk_rfe_setting_8821c(p_dm_odm, false); + _iqk_agc_bnd_int_8821c(p_dm_odm); + _iqk_rfsetting_8821c(p_dm_odm); + + _iqk_start_iqk_8821c(p_dm_odm, segment_iqk); + + _iqk_afe_setting_8821c(p_dm_odm, false); + _iqk_restore_mac_bb_8821c(p_dm_odm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg,BB_REG_NUM_8821C); + _iqk_restore_rf_8821c(p_dm_odm, backup_rf_reg, RF_backup); + + if (!is_mp) { + p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time += odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, + ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time)); + } + + if (p_dm_odm->rf_calibrate_info.iqk_step == 4) + break; + + p_iqk_info->kcount = 0; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]delay 50ms!!!\n")); + ODM_delay_ms(50); + }; + + _iqk_backup_iqk_8821c(p_dm_odm, 1); + _iqk_fill_iqk_report_8821c(p_dm_odm, 0); + + if (!is_mp) + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]Total IQK progressing_time = %lld ms\n", + p_dm_odm->rf_calibrate_info.iqk_total_progressing_time)); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]==========IQK end!!!!!==========\n")); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]check 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c))); +} + +/*IQK version:0xe, NCTL:0x7*/ +/*1. disable segment IQK*/ +void +phy_iq_calibrate_8821c( + void *p_dm_void, + boolean clear +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + u32 counter = 0x0; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + + PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx); + + if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression) + return; + + if (!p_dm_odm->mp_mode) + _iqk_check_coex_status(p_dm_odm, true); + + if (*(p_dm_odm->p_is_scan_in_process)) { + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]scan is in process, bypass IQK\n")); + return; + } + + p_dm_odm->iqk_fw_offload = 0; + + /*FW IQK*/ + if (p_dm_odm->iqk_fw_offload) { + if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + + p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); + + odm_write_4byte(p_dm_odm, 0x1b00, 0xf8000008); + odm_set_bb_reg(p_dm_odm, 0x1bf0, 0xff000000, 0xff); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, + ("[IQK]0x1bf0 = 0x%x\n", odm_read_4byte(p_dm_odm, 0x1bf0))); + + while (1) { + if (((odm_read_4byte(p_dm_odm, 0x1bf0) >> 24) == 0x7f) || (counter > 300)) + break; + + counter++; + ODM_delay_ms(1); + }; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE, ("[IQK]counter = %d\n", counter)); + + p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time)); + + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n")); + } else { + + _iq_calibrate_8821c_init(p_dm_void); + + if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + if (p_dm_odm->mp_mode) + p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); + + _phy_iq_calibrate_8821c(p_dm_odm, clear); + if (p_dm_odm->mp_mode) { + p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]IQK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time)); + } + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[IQK]== Return the IQK CMD, because the IQK in Progress ==\n")); + } + + if (!p_dm_odm->mp_mode) + _iqk_check_coex_status(p_dm_odm, false); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[IQK]final 0x49c = %x\n", odm_read_1byte(p_dm_odm, 0x49c))); +} + +void +phy_dp_calibrate_8821c( + void *p_dm_void, + boolean clear +) +{ + struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void; + struct _ADAPTER *p_adapter = p_dm_odm->adapter; + + PMPT_CONTEXT p_mpt_ctx = &(p_adapter->mppriv.mpt_ctx); + + if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression) + return; + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK] In PHY, p_dm_odm->dpk_en == %x\n", p_dm_odm->dpk_en)); + + /*if dpk is not enable*/ + if (p_dm_odm->dpk_en == 0x0) + return; + + /*start*/ + if (!p_dm_odm->rf_calibrate_info.is_iqk_in_progress) { + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = true; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + if (p_dm_odm->mp_mode) + p_dm_odm->rf_calibrate_info.iqk_start_time = odm_get_current_time(p_dm_odm); + + /*do DPK*/ + phy_dpd_calibrate_8821c(p_dm_odm, clear); + + if (p_dm_odm->mp_mode) { + p_dm_odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(p_dm_odm, p_dm_odm->rf_calibrate_info.iqk_start_time); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK]DPK progressing_time = %lld ms\n", p_dm_odm->rf_calibrate_info.iqk_progressing_time)); + } + odm_acquire_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + p_dm_odm->rf_calibrate_info.is_iqk_in_progress = false; + odm_release_spin_lock(p_dm_odm, RT_IQK_SPINLOCK); + } else + ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("[DPK]== Return the DPK CMD, because the DPK in Progress ==\n")); + +} diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h new file mode 100644 index 000000000000..0e4a0c94c08f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_iqk_8821c.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __PHYDM_IQK_8821C_H__ +#define __PHYDM_IQK_8821C_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +#define MAC_REG_NUM_8821C 3 +#define BB_REG_NUM_8821C 10 +#define RF_REG_NUM_8821C 6 +#define DPK_BB_REG_NUM_8821C 24 +#define DPK_BACKUP_REG_NUM_8821C 3 + +#define LOK_delay_8821C 2 +#define GS_delay_8821C 2 +#define WBIQK_delay_8821C 2 + +#define TXIQK 0 +#define RXIQK 1 +#define SS_8821C 1 + +/*---------------------------End Define Parameters-------------------------------*/ + +void +do_iqk_8821c( + void *p_dm_void, + u8 delta_thermal_index, + u8 thermal_value, + u8 threshold +); + +void +phy_iq_calibrate_8821c( + void *p_dm_void, + boolean clear +); +VOID +phy_dp_calibrate_8821c( + void *p_dm_void, + boolean clear + + ); + + +#endif /* #ifndef __PHYDM_IQK_8821C_H__*/ diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c new file mode 100644 index 000000000000..57bc15e48d51 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.c @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + + +void +odm_config_rf_reg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data, + enum odm_rf_radio_path_e RF_PATH, + u32 reg_addr +) +{ + if (addr == 0xffe) { + ODM_sleep_ms(50); + } else { + odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + } +} + +void +odm_config_rf_radio_a_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +) +{ + u32 content = 0x1000; /* RF_Content: radioa_txt */ + u32 maskfor_phy_set = (u32)(content & 0xE000); + + odm_config_rf_reg_8821c(p_dm_odm, addr, data, ODM_RF_PATH_A, addr | maskfor_phy_set); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data)); +} + +void +odm_config_mac_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u8 data +) +{ + odm_write_1byte(p_dm_odm, addr, data); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data)); +} + +void +odm_update_agc_big_jump_lmt_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +) +{ + struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table; + u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24); + u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16); + u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8); + static boolean is_limit; + + if (addr != 0x81c) + return; + + /*dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/ + /*dbg_print("rf_gain_idx = 0x%x, p_dm_dig_table->rf_gain_idx = 0x%x\n", rf_gain_idx, p_dm_dig_table->rf_gain_idx);*/ + + if (bb_gain_idx > 0x3c) { + if ((rf_gain_idx == p_dm_dig_table->rf_gain_idx) && (is_limit == false)) { + is_limit = true; + p_dm_dig_table->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2; + ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n", agc_table_idx, p_dm_dig_table->big_jump_lmt[agc_table_idx])); + } + } else + is_limit = false; + + p_dm_dig_table->rf_gain_idx = rf_gain_idx; + +} + +void +odm_config_bb_agc_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +) +{ + odm_update_agc_big_jump_lmt_8821c(p_dm_odm, addr, data); + + odm_set_bb_reg(p_dm_odm, addr, bitmask, data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data)); +} + +void +odm_config_bb_phy_reg_pg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 band, + u32 rf_path, + u32 tx_num, + u32 addr, + u32 bitmask, + u32 data +) +{ + phy_store_tx_power_by_rate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data)); +} + +void +odm_config_bb_phy_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +) +{ + if (addr == 0xffe) + ODM_sleep_ms(50); + else + odm_set_bb_reg(p_dm_odm, addr, bitmask, data); + + /* Add 1us delay between BB/RF register setting. */ + ODM_delay_us(1); + ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data)); +} + +void +odm_config_bb_txpwr_lmt_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit +) +{ + phy_set_tx_power_limit(p_dm_odm, regulation, band, + bandwidth, rate_section, rf_path, channel, power_limit); +} + diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h new file mode 100644 index 000000000000..8a34d89c35d5 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/phydm_regconfig8821c.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8821C +#define __INC_ODM_REGCONFIG_H_8821C + + +void +odm_config_rf_reg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data, + enum odm_rf_radio_path_e RF_PATH, + u32 reg_addr +); + +void +odm_config_rf_radio_a_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +); + +void +odm_config_rf_radio_b_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +); + +void +odm_config_mac_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u8 data +); + +void +odm_update_agc_big_jump_lmt_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 data +); + +void +odm_config_bb_agc_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +); + +void +odm_config_bb_phy_reg_pg_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 band, + u32 rf_path, + u32 tx_num, + u32 addr, + u32 bitmask, + u32 data +); + +void +odm_config_bb_phy_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u32 addr, + u32 bitmask, + u32 data +); + +void +odm_config_bb_txpwr_lmt_8821c( + struct PHY_DM_STRUCT *p_dm_odm, + u8 *regulation, + u8 *band, + u8 *bandwidth, + u8 *rate_section, + u8 *rf_path, + u8 *channel, + u8 *power_limit +); + +#endif /* RTL8822B_SUPPORT == 1*/ diff --git a/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h new file mode 100644 index 000000000000..d2b4a24958a7 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/rtl8821c/version_rtl8821c.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*RTL8821C PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8821C 20170206 +#define COMMIT_BY_8821C "Coiln" +#define RELEASE_VERSION_8821C 36 diff --git a/drivers/staging/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h b/drivers/staging/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h new file mode 100644 index 000000000000..75017630e7e4 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/phydm/txbf/haltxbfjaguar.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_TXBF_JAGUAR_H__ +#define __HAL_TXBF_JAGUAR_H__ + +#define hal_txbf_8812a_set_ndpa_rate(p_dm_void, BW, rate) +#define hal_txbf_jaguar_enter(p_dm_void, idx) +#define hal_txbf_jaguar_leave(p_dm_void, idx) +#define hal_txbf_jaguar_status(p_dm_void, idx) +#define hal_txbf_jaguar_fw_txbf(p_dm_void, idx) +#define hal_txbf_jaguar_patch(p_dm_void, operation) +#define hal_txbf_jaguar_clk_8812a(p_dm_void) + +#endif /* #ifndef __HAL_TXBF_JAGUAR_H__ */ diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/hal8821c_fw.c b/drivers/staging/rtl8821ce/hal/rtl8821c/hal8821c_fw.c new file mode 100644 index 000000000000..3889c386e37b --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/hal8821c_fw.c @@ -0,0 +1,14412 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#include "drv_types.h" + +u8 array_mp_8821c_fw_nic[] = { +0x21, 0x88, 0x00, 0x00, 0x09, 0x00, 0x07, 0x00, +0x42, 0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x03, 0x0C, 0x12, 0x03, 0xE1, 0x07, 0x00, 0x00, +0x18, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, +0x00, 0x00, 0x20, 0x80, 0xC0, 0x7C, 0x00, 0x00, +0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, +0xD8, 0xED, 0x00, 0x00, 0x98, 0x56, 0x00, 0x00, +0x00, 0x00, 0x10, 0x80, 0x00, 0x00, 0x03, 0x80, +0x00, 0x00, 0x04, 0x04, 0x08, 0x08, 0x08, 0x08, +0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, +0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, +0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 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0x14, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x54, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xA5, 0xF7, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x58, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0x06, 0xF1, 0x18, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xAE, 0xF6, 0x5C, 0xDB, 0x10, 0xF0, 0x21, 0x6A, +0xC6, 0xF1, 0x0C, 0x4A, 0x30, 0xF0, 0x20, 0x6B, +0xCE, 0xF6, 0x40, 0xDB, 0x20, 0xE8, 0x00, 0x65, +0x19, 0xEE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +u32 array_length_mp_8821c_fw_nic = 115080; diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/hal8821c_fw.h b/drivers/staging/rtl8821ce/hal/rtl8821c/hal8821c_fw.h new file mode 100644 index 000000000000..34b3098cf4cc --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/hal8821c_fw.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +#ifndef _FW_HEADER_8821C_H +#define _FW_HEADER_8821C_H + +extern u8 array_mp_8821c_fw_nic[115080]; +extern u32 array_length_mp_8821c_fw_nic; +extern u8 array_mp_8821c_fw_wowlan[92840]; +extern u32 array_length_mp_8821c_fw_wowlan; + +#endif + diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h new file mode 100644 index 000000000000..9ead34e99a31 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL8821CE_H_ +#define _RTL8821CE_H_ + +#include <drv_types.h> /* PADAPTER */ +#include "../../hal_halmac.h" /* HALMAC_RX_FIFO_SIZE_8821C */ + +#define TX_BD_NUM_8821CE 128 +#define RX_BD_NUM_8821CE 128 +#define TX_BD_NUM_8821CE_BCN 2 +#define TX_BD_NUM_8821CE_CMD 128 + +#define RTL8821CE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */ + +#ifndef MAX_RECVBUF_SZ + #ifndef CONFIG_MINIMAL_MEMORY_USAGE + #define MAX_RECVBUF_SZ (32768) + #else + #define MAX_RECVBUF_SZ (4000) + #endif +#endif /* !MAX_RECVBUF_SZ */ + +#define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ + +#define MAX_RECVBUF_SZ_8821C HALMAC_RX_FIFO_SIZE_8821C + +/* TX BD */ +#define SET_TXBUFFER_DESC_LEN_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 0, 16, __Valeu) +#define SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8), 31, 1, __Valeu) +#define SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(__pTxDesc, __Offset, __Valeu) \ + SET_BITS_TO_LE_4BYTE(__pTxDesc+(__Offset*8)+4, 0, 32, __Valeu) + +/* RX BD */ +#define SET_RX_BD_PHYSICAL_ADDR_LOW(__pRxBd, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxBd + 0x04, 0, 32, __Value) +#define SET_RX_BD_RXBUFFSIZE(__pRxBd, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 0, 14, __Value) +#define SET_RX_BD_LS(__pRxBd, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 14, 1, __Value) +#define SET_RX_BD_FS(__pRxBd, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 15, 1, __Value) +#define SET_RX_BD_TOTALRXPKTSIZE(__pRxBd, __Value) \ + SET_BITS_TO_LE_4BYTE(__pRxBd + 0x00, 16, 13, __Value) + +/* rtl8821ce_halinit.c */ +u32 rtl8821ce_hal_init(PADAPTER); +u32 rtl8821ce_hal_deinit(PADAPTER); +void rtl8821ce_init_default_value(PADAPTER); + +/* rtl8821ce_halmac.c */ +int rtl8821ce_halmac_init_adapter(PADAPTER); + +/* rtl8821ce_io.c */ + +/* rtl8821ce_led.c */ +void rtl8821ce_initswleds(PADAPTER); +void rtl8821ce_deinitswleds(PADAPTER); + +/* rtl8821ce_xmit.c */ +#define OFFSET_SZ 0 + +s32 rtl8821ce_init_xmit_priv(PADAPTER); +void rtl8821ce_free_xmit_priv(PADAPTER); +struct xmit_buf *rtl8821ce_dequeue_xmitbuf(struct rtw_tx_ring *); +void rtl8821ce_fill_fake_txdesc(PADAPTER, u8 *pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); +int rtl8821ce_init_txbd_ring(PADAPTER, unsigned int q_idx, + unsigned int entries); +void rtl8821ce_free_txbd_ring(PADAPTER, unsigned int prio); + +void rtl8821ce_tx_isr(PADAPTER, int prio); + +s32 rtl8821ce_mgnt_xmit(PADAPTER, struct xmit_frame *); +s32 rtl8821ce_hal_xmit(PADAPTER, struct xmit_frame *); +s32 rtl8821ce_hal_xmitframe_enqueue(PADAPTER, struct xmit_frame *); + + +void rtl8821ce_xmitframe_resume(PADAPTER); + +/* rtl8821ce_recv.c */ +s32 rtl8821ce_init_recv_priv(PADAPTER); +void rtl8821ce_free_recv_priv(PADAPTER); +int rtl8821ce_init_rxbd_ring(PADAPTER); +void rtl8821ce_free_rxbd_ring(PADAPTER); + +/* rtl8821cs_ops.c */ + +#endif /* _RTL8821CE_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c new file mode 100644 index 000000000000..b46ba3e7b036 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halinit.c @@ -0,0 +1,319 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _RTL8821CE_HALINIT_C_ +#include <drv_types.h> /* PADAPTER, basic_types.h and etc. */ +#include <hal_data.h> /* HAL_DATA_TYPE */ +#include "../rtl8821c.h" +#include "rtl8821ce.h" + +u32 InitMAC_TRXBD_8821CE(PADAPTER Adapter) +{ + u8 tmpU1b; + u16 tmpU2b; + u32 tmpU4b; + int q_idx; + struct recv_priv *precvpriv = &Adapter->recvpriv; + struct xmit_priv *pxmitpriv = &Adapter->xmitpriv; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + RTW_INFO("=======>InitMAC_TXBD_8821CE()\n"); + + /* + * Set CMD TX BD (buffer descriptor) physical address(from OS API). + */ + rtw_write32(Adapter, REG_H2CQ_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[TXCMD_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + rtw_write32(Adapter, REG_H2CQ_TXBD_NUM_8821C, + TX_BD_NUM_8821CE_CMD | ((RTL8821CE_SEG_NUM << 12) & + 0x3000)); + + /* + * Set TX/RX BD (buffer descriptor) physical address(from OS API). + */ + rtw_write32(Adapter, REG_BCNQ_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[BCN_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + rtw_write32(Adapter, REG_MGQ_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[MGT_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + rtw_write32(Adapter, REG_VOQ_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[VO_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + rtw_write32(Adapter, REG_VIQ_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[VI_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + rtw_write32(Adapter, REG_BEQ_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[BE_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + + /* vincent sync windows */ + tmpU4b = rtw_read32(Adapter, REG_BEQ_TXBD_DESA_8821C); + + rtw_write32(Adapter, REG_BKQ_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[BK_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + rtw_write32(Adapter, REG_HI0Q_TXBD_DESA_8821C, + (u64)pxmitpriv->tx_ring[HIGH_QUEUE_INX].dma & + DMA_BIT_MASK(32)); + rtw_write32(Adapter, REG_RXQ_RXBD_DESA_8821C, + (u64)precvpriv->rx_ring[RX_MPDU_QUEUE].dma & + DMA_BIT_MASK(32)); + + + /* pci buffer descriptor mode: Reset the Read/Write point to 0 */ + PlatformEFIOWrite4Byte(Adapter, REG_TSFTIMER_HCI_8821C, 0x3fffffff); + + /* Reset the H2CQ R/W point index to 0 */ + tmpU4b = rtw_read32(Adapter, REG_H2CQ_CSR_8821C); + rtw_write32(Adapter, REG_H2CQ_CSR_8821C, (tmpU4b | BIT8 | BIT16)); + + tmpU1b = rtw_read8(Adapter, REG_PCIE_CTRL + 3); + rtw_write8(Adapter, REG_PCIE_CTRL + 3, (tmpU1b | 0xF7)); + + /* 20100318 Joseph: Reset interrupt migration setting + * when initialization. Suggested by SD1 + */ + + rtw_write32(Adapter, REG_INT_MIG, 0); + pHalData->bInterruptMigration = _FALSE; + + /* 2009.10.19. Reset H2C protection register. by tynli. */ + rtw_write32(Adapter, REG_MCUTST_I_8821C, 0x0); + + if (Adapter->registrypriv.mp_mode == 1) { + rtw_write32(Adapter, REG_MACID, 0x87654321); + rtw_write32(Adapter, 0x0700, 0x87654321); + } + + /* pic buffer descriptor mode: */ + /* ---- tx */ + rtw_write16(Adapter, REG_MGQ_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_VOQ_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_VIQ_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_BEQ_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_BKQ_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI0Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI1Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI2Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI3Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI4Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI5Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI6Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + rtw_write16(Adapter, REG_HI7Q_TXBD_NUM_8821C, + TX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 12) & 0x3000)); + + /* rx. support 32 bits in linux */ + + /* using 64bit + * rtw_write16(Adapter, REG_RX_RXBD_NUM_8821C, + * RX_BD_NUM_8821CE |((RTL8821CE_SEG_NUM<<13 ) & 0x6000) |0x8000); + */ + + /* using 32bit */ + rtw_write16(Adapter, REG_RX_RXBD_NUM_8821C, + RX_BD_NUM_8821CE | ((RTL8821CE_SEG_NUM << 13) & 0x6000)); + + /* reset read/write point */ + rtw_write32(Adapter, REG_TSFTIMER_HCI_8821C, 0XFFFFFFFF); + + /* Start debug mode */ + { + u8 reg0x3f3 = 0; + + reg0x3f3 = rtw_read8(Adapter, 0x3f3); + rtw_write8(Adapter, 0x3f3, reg0x3f3 | BIT2); + } + + { + /* Need to disable BT coex to let MP tool Tx, this would be done in FW + * in the future, suggest by ChunChu, 2015.05.19 + */ + + u8 tmp1Byte; + u16 tmp2Byte; + u32 tmp4Byte; + + tmp2Byte = rtw_read16(Adapter, REG_SYS_FUNC_EN_8821C); + rtw_write16(Adapter, REG_SYS_FUNC_EN_8821C, tmp2Byte | BIT10); + tmp1Byte = rtw_read8(Adapter, REG_DIS_TXREQ_CLR_8821C); + rtw_write8(Adapter, REG_DIS_TXREQ_CLR_8821C, tmp1Byte | BIT7); + tmp4Byte = rtw_read32(Adapter, 0x1080); + rtw_write32(Adapter, 0x1080, tmp4Byte | BIT16); + } + + RTW_INFO("InitMAC_TXBD_8821CE() <====\n"); + + return _SUCCESS; +} + +u32 rtl8821ce_hal_init(PADAPTER padapter) +{ + u8 ok = _TRUE; + u8 val8; + PHAL_DATA_TYPE hal; + struct registry_priv *registry_par; + + hal = GET_HAL_DATA(padapter); + registry_par = &padapter->registrypriv; + + InitMAC_TRXBD_8821CE(padapter); + + ok = rtl8821c_hal_init(padapter); + if (ok == _FALSE) + return _FAIL; + + /* have to init after halmac init */ + val8 = rtw_read8(padapter, REG_PCIE_CTRL_8821C + 2); + rtw_write8(padapter, REG_PCIE_CTRL_8821C + 2, (val8 | BIT4)); + rtw_write16(padapter, REG_PCIE_CTRL_8821C, 0x8000); + + rtw_write8(padapter, REG_RX_DRVINFO_SZ_8821C, 0x4); + + hal->pci_backdoor_ctrl = registry_par->pci_aspm_config; + + rtw_pci_aspm_config(padapter); + + return _SUCCESS; +} + +void rtl8821ce_init_default_value(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + + rtl8821c_init_default_value(padapter); + + /* interface related variable */ + pHalData->CurrentWirelessMode = WIRELESS_MODE_AUTO; + pHalData->bDefaultAntenna = 1; + pHalData->TransmitConfig = BIT_CFEND_FORMAT | BIT_WMAC_TCR_ERRSTEN_3; + + /* Set RCR-Receive Control Register . + * The value is set in InitializeAdapter8190Pci(). + */ + pHalData->ReceiveConfig = ( + BIT_APP_FCS | + BIT_APP_MIC | + BIT_APP_ICV | + BIT_APP_PHYSTS | + BIT_VHT_DACK | + BIT_HTC_LOC_CTRL | + /* BIT_AMF | */ + BIT_CBSSID_DATA | + BIT_CBSSID_BCN | + /* BIT_ACF | */ + /* BIT_ADF | PS-Poll filter */ + BIT_AB | + BIT_AB | + BIT_APM | + 0); + + /* + * Set default value of Interrupt Mask Register0 + */ + pHalData->IntrMaskDefault[0] = (u32)( + BIT(29) | /* BIT_PSTIMEOUT */ + BIT(27) | /* BIT_GTINT3 */ + BIT_TXBCN0ERR_MSK | + BIT_TXBCN0OK_MSK | + BIT_BCNDMAINT0_MSK | + BIT_HSISR_IND_ON_INT_MSK | + BIT_C2HCMD_MSK | + BIT_HIGHDOK_MSK | + BIT_MGTDOK_MSK | + BIT_BKDOK_MSK | + BIT_BEDOK_MSK | + BIT_VIDOK_MSK | + BIT_VODOK_MSK | + BIT_RDU_MSK | + BIT_RXOK_MSK | + 0); + + /* + * Set default value of Interrupt Mask Register1 + */ + pHalData->IntrMaskDefault[1] = (u32)( + BIT(9) | /* TXFOVW */ + BIT_FOVW_MSK | + 0); + + /* + * Set default value of Interrupt Mask Register3 + */ + pHalData->IntrMaskDefault[3] = (u32)( + BIT_SETH2CDOK_MASK | /* H2C_TX_OK */ + 0); + + /* 2012/03/27 hpfan Add for win8 DTM DPC ISR test */ + pHalData->IntrMaskReg[0] = (u32)( + BIT_RDU_MSK | + BIT(29) | /* BIT_PSTIMEOUT */ + 0); + + pHalData->IntrMaskReg[1] = (u32)( + BIT_C2HCMD_MSK | + 0); + + pHalData->IntrMask[0] = pHalData->IntrMaskDefault[0]; + pHalData->IntrMask[1] = pHalData->IntrMaskDefault[1]; + pHalData->IntrMask[3] = pHalData->IntrMaskDefault[3]; + +} + +static void hal_deinit_misc(PADAPTER padapter) +{ + +} + +u32 rtl8821ce_hal_deinit(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pobj_priv = adapter_to_dvobj(padapter); + u8 status = _TRUE; + + RTW_INFO("==> %s\n", __func__); + + hal_deinit_misc(padapter); + status = rtl8821c_hal_deinit(padapter); + if (status == _FALSE) { + RTW_INFO("%s: rtl8821c_hal_deinit fail\n", __func__); + return _FAIL; + } + + RTW_INFO("%s <==\n", __func__); + return _SUCCESS; +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c new file mode 100644 index 000000000000..5334cae4e01f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_halmac.c @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821CE_HALMAC_C_ +#include <drv_types.h> /* struct dvobj_priv and etc. */ +#include "../../hal_halmac.h" +#include "rtl8821ce.h" + +static u8 pci_write_port_not_xmitframe(void *d, u32 size, u8 *pBuf) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + struct pci_dev *pdev = pobj->ppcidev; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + u8 *txbd; + u64 txbd_dma; + u8 ret = _SUCCESS; + dma_addr_t mapping; + + u16 seg_num = 2 << TX_BUFFER_SEG_NUM; + + u16 page_size_length = 0; + + /* map TX DESC buf_addr (including TX DESC + tx data) */ + mapping = pci_map_single(pdev, pBuf, + size+TX_WIFI_INFO_SIZE, PCI_DMA_TODEVICE); + + /* Calculate page size. + * Total buffer length including TX_WIFI_INFO and PacketLen + */ + page_size_length = + (size + TX_WIFI_INFO_SIZE) / HALMAC_TX_PAGE_SIZE_8821C; + + if (((size + TX_WIFI_INFO_SIZE) % HALMAC_TX_PAGE_SIZE_8821C) > 0) + page_size_length++; + + txbd = pci_alloc_consistent(pdev, + sizeof(struct tx_buf_desc), &txbd_dma); + + if (!txbd) { + pci_unmap_single(pdev, mapping, + size + TX_WIFI_INFO_SIZE, PCI_DMA_FROMDEVICE); + + return _FALSE; + } + + /* + * Reset all tx buffer desciprtor content + * -- Reset first element + */ + _rtw_memset(txbd, 0, sizeof(struct tx_buf_desc)); + + /* + * Fill buffer length of the first buffer, + * For 8821ce, it is required that TX_WIFI_INFO is put in first segment, + * and the size of the first segment cannot be larger than + * TX_WIFI_INFO_SIZE. + */ + SET_TX_BD_TX_BUFF_SIZE0(txbd, TX_WIFI_INFO_SIZE); + SET_TX_BD_PSB(txbd, page_size_length); + /* starting addr of TXDESC */ + SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping); + + /* + * It is assumed that in linux implementation, packet is coalesced + * in only one buffer. Extension mode is not supported here + */ + SET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, 1, size); + + SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1, + mapping + TX_WIFI_INFO_SIZE); /* pkt */ + + /* Set BCN BD Reg */ + rtw_write32(padapter, REG_BCNQ_TXBD_DESA_8821C, + txbd_dma & DMA_BIT_MASK(32)); + + /* Need Comment */ + wmb(); + + /* fill_txbd_own*/ + SET_TX_BD_OWN(txbd, 1); + + /* kick start */ + rtw_write8(padapter, REG_RX_RXBD_NUM + 1, + rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4)); + + udelay(100); + + pci_free_consistent(pdev, sizeof(*txbd), txbd, txbd_dma); + + pci_unmap_single(pdev, mapping, + size + TX_WIFI_INFO_SIZE, PCI_DMA_FROMDEVICE); + + return ret; + +} + +static u8 pci_write_data_not_xmitframe(void *d, u8 *pBuf, u32 size, u8 qsel) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); + PHALMAC_API api = HALMAC_GET_API(halmac); + u8 desclen = 0; + u8 *buf = NULL; + u8 ret = _FALSE; + + if ((size + TXDESC_OFFSET) > MAX_CMDBUF_SZ) { + RTW_INFO("%s: total buffer size(%d) > MAX_CMDBUF_SZ(%d)\n" + , __func__, size + TXDESC_OFFSET, MAX_CMDBUF_SZ); + return _FALSE; + } + + desclen = HALMAC_TX_DESC_SIZE_8821C; + + buf = rtw_zmalloc(desclen + size); + + if (!buf) { + RTW_INFO("%s: rtw_zmalloc for rsvd Fail\n", __func__); + return _FALSE; + } + + _rtw_memcpy(buf + desclen, pBuf, size); + + SET_TX_DESC_TXPKTSIZE_8821C(buf, size); + SET_TX_DESC_OFFSET_8821C(buf, desclen); + SET_TX_DESC_QSEL_8821C(buf, qsel); + + api->halmac_fill_txdesc_checksum(halmac, buf); + + ret = pci_write_port_not_xmitframe(d, size, buf); + + if (ret == _SUCCESS) + ret = _TRUE; + else + ret = _FALSE; + + rtw_mfree(buf, desclen + size); + + return _TRUE; +} + +static u8 pci_write_data_rsvd_page_xmitframe(void *d, u8 *pBuf, u32 size) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pcmdframe = NULL; + struct pkt_attrib *pattrib = NULL; + PHALMAC_API api = HALMAC_GET_API(halmac); + u8 desclen = 0; + u8 *txdesc = NULL; + + if (size + TXDESC_OFFSET > MAX_CMDBUF_SZ) { + RTW_INFO("%s: total buffer size(%d) > MAX_CMDBUF_SZ(%d)\n" + , __func__, size + TXDESC_OFFSET, MAX_CMDBUF_SZ); + return _FALSE; + } + + pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + + if (pcmdframe == NULL) { + RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __func__); + return _FALSE; + } + + desclen = HALMAC_TX_DESC_SIZE_8821C; + txdesc = pcmdframe->buf_addr; + + _rtw_memcpy((txdesc + desclen), pBuf, size); /* shift desclen */ + + /* update attribute */ + pattrib = &pcmdframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->qsel = QSLT_BEACON; + pattrib->pktlen = size; + pattrib->last_txcmdsz = size; + + dump_mgntframe(padapter, pcmdframe); + + return _TRUE; +} + +static u8 pci_write_data_h2c_normal(void *d, u8 *pBuf, u32 size) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + PHALMAC_ADAPTER halmac = dvobj_to_halmac((struct dvobj_priv *)d); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pcmdframe = NULL; + struct pkt_attrib *pattrib = NULL; + PHALMAC_API api; + u32 desclen; + u8 *buf; + + if (size + TXDESC_OFFSET > MAX_XMIT_EXTBUF_SZ) { + RTW_INFO("%s: total buffer size(%d) > MAX_XMIT_EXTBUF_SZ(%d)\n" + , __func__, size + TXDESC_OFFSET, MAX_XMIT_EXTBUF_SZ); + return _FALSE; + } + + pcmdframe = alloc_mgtxmitframe(pxmitpriv); + + if (pcmdframe == NULL) { + RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __func__); + return _FALSE; + } + + api = HALMAC_GET_API(halmac); + + desclen = HALMAC_TX_DESC_SIZE_8821C; + buf = pcmdframe->buf_addr; + _rtw_memcpy(buf + desclen, pBuf, size); /* shift desclen */ + + SET_TX_DESC_TXPKTSIZE_8821C(buf, size); + SET_TX_DESC_OFFSET_8821C(buf, 0); + SET_TX_DESC_QSEL_8821C(buf, HALMAC_QUEUE_SELECT_CMD); + SET_TX_DESC_TXDESC_CHECKSUM_8821C(buf, 0); + api->halmac_fill_txdesc_checksum(halmac, buf); + + /* update attribute */ + pattrib = &pcmdframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->qsel = QSLT_CMD; + pattrib->pktlen = size; + pattrib->last_txcmdsz = size; + + /* fill tx desc in dump_mgntframe */ + dump_mgntframe(padapter, pcmdframe); + + return _TRUE; +} + +static u8 pci_write_data_rsvd_page(void *d, u8 *pBuf, u32 size) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->not_xmitframe_fw_dl) + return pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_BEACON); + else + return pci_write_data_rsvd_page_xmitframe(d, pBuf, size); +} + +static u8 pci_write_data_h2c(void *d, u8 *pBuf, u32 size) +{ + struct dvobj_priv *pobj = (struct dvobj_priv *)d; + PADAPTER padapter = dvobj_get_primary_adapter(pobj); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->not_xmitframe_fw_dl) + return pci_write_data_not_xmitframe(d, pBuf, size, HALMAC_TXDESC_QSEL_H2C_CMD); + else + return pci_write_data_h2c_normal(d, pBuf, size); +} + +int rtl8821ce_halmac_init_adapter(PADAPTER padapter) +{ + struct dvobj_priv *d; + PHALMAC_PLATFORM_API api; + int err; + + d = adapter_to_dvobj(padapter); + api = &rtw_halmac_platform_api; + api->SEND_RSVD_PAGE = pci_write_data_rsvd_page; + api->SEND_H2C_PKT = pci_write_data_h2c; + + err = rtw_halmac_init_adapter(d, api); + + return err; +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c new file mode 100644 index 000000000000..fe2242a3c185 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_io.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821CE_IO_C_ + +#include <drv_types.h> /* PADAPTER and etc. */ + + +static u8 pci_read8(struct intf_hdl *phdl, u32 addr) +{ + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev; + + return 0xff & readb((u8 *)pdvobjpriv->pci_mem_start + addr); +} + +static u16 pci_read16(struct intf_hdl *phdl, u32 addr) +{ + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev; + + return readw((u8 *)pdvobjpriv->pci_mem_start + addr); +} + +static u32 pci_read32(struct intf_hdl *phdl, u32 addr) +{ + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev; + + return readl((u8 *)pdvobjpriv->pci_mem_start + addr); +} + +/* + * 2009.12.23. by tynli. Suggested by SD1 victorh. + * For ASPM hang on AMD and Nvidia. + * 20100212 Tynli: Do read IO operation after write for + * all PCI bridge suggested by SD1. Origianally this is only for INTEL. + */ +static int pci_write8(struct intf_hdl *phdl, u32 addr, u8 val) +{ + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev; + + writeb(val, (u8 *)pdvobjpriv->pci_mem_start + addr); + return 1; +} + +static int pci_write16(struct intf_hdl *phdl, u32 addr, u16 val) +{ + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev; + + writew(val, (u8 *)pdvobjpriv->pci_mem_start + addr); + return 2; +} + +static int pci_write32(struct intf_hdl *phdl, u32 addr, u32 val) +{ + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)phdl->pintf_dev; + + writel(val, (u8 *)pdvobjpriv->pci_mem_start + addr); + return 4; +} + +static void pci_read_mem(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *rmem) +{ + RTW_INFO("%s(%d)fake function\n", __func__, __LINE__); +} + +static void pci_write_mem(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *wmem) +{ + RTW_INFO("%s(%d)fake function\n", __func__, __LINE__); +} + +static u32 pci_read_port(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *rmem) +{ + return 0; +} + +static u32 pci_write_port(struct intf_hdl *phdl, u32 addr, u32 cnt, u8 *wmem) +{ + _adapter *padapter = (_adapter *)phdl->padapter; + + netif_trans_update(padapter->pnetdev); + + return 0; +} + +void rtl8821ce_set_intf_ops(struct _io_ops *pops) +{ + + _rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops)); + + pops->_read8 = &pci_read8; + pops->_read16 = &pci_read16; + pops->_read32 = &pci_read32; + + pops->_read_mem = &pci_read_mem; + pops->_read_port = &pci_read_port; + + pops->_write8 = &pci_write8; + pops->_write16 = &pci_write16; + pops->_write32 = &pci_write32; + + pops->_write_mem = &pci_write_mem; + pops->_write_port = &pci_write_port; + +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c new file mode 100644 index 000000000000..39c1476b3719 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_ops.c @@ -0,0 +1,694 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _HCI_OPS_OS_C_ + +#include <drv_types.h> /* PADAPTER, basic_types.h and etc. */ +#include <hal_data.h> /* HAL_DATA_TYPE, GET_HAL_DATA() and etc. */ +#include <hal_intf.h> /* struct hal_ops */ +#include "../rtl8821c.h" +#include "rtl8821ce.h" + +static void init_bd_ring_var(_adapter *padapter) +{ + struct recv_priv *r_priv = &padapter->recvpriv; + struct xmit_priv *t_priv = &padapter->xmitpriv; + u8 i = 0; + + for (i = 0; i < HW_QUEUE_ENTRY; i++) + t_priv->txringcount[i] = TX_BD_NUM_8821CE; + + /* + * we just alloc 2 desc for beacon queue, + * because we just need first desc in hw beacon. + */ + t_priv->txringcount[BCN_QUEUE_INX] = TX_BD_NUM_8821CE_BCN; + t_priv->txringcount[TXCMD_QUEUE_INX] = TX_BD_NUM_8821CE_CMD; + + /* + * BE queue need more descriptor for performance consideration + * or, No more tx desc will happen, and may cause mac80211 mem leakage. + */ + r_priv->rxbuffersize = MAX_RECVBUF_SZ; + r_priv->rxringcount = PCI_MAX_RX_COUNT; +} + +static void rtl8821ce_reset_bd(_adapter *padapter) +{ + _irqL irqL; + struct xmit_priv *t_priv = &padapter->xmitpriv; + struct recv_priv *r_priv = &padapter->recvpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct xmit_buf *pxmitbuf = NULL; + u8 *tx_bd, *rx_bd; + int i, rx_queue_idx; + + for (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) { + if (r_priv->rx_ring[rx_queue_idx].buf_desc) { + rx_bd = NULL; + for (i = 0; i < r_priv->rxringcount; i++) { + rx_bd = (u8 *) + &r_priv->rx_ring[rx_queue_idx].buf_desc[i]; + } + r_priv->rx_ring[rx_queue_idx].idx = 0; + } + } + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) { + if (t_priv->tx_ring[i].buf_desc) { + struct rtw_tx_ring *ring = &t_priv->tx_ring[i]; + + while (ring->qlen) { + tx_bd = (u8 *)(&ring->buf_desc[ring->idx]); + SET_TX_BD_OWN(tx_bd, 0); + + if (i != BCN_QUEUE_INX) + ring->idx = + (ring->idx + 1) % ring->entries; + + pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring); + if (pxmitbuf) { + pci_unmap_single(pdvobjpriv->ppcidev, + GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_bd), + pxmitbuf->len, PCI_DMA_TODEVICE); + rtw_free_xmitbuf(t_priv, pxmitbuf); + } else { + RTW_INFO("%s(): qlen(%d) is not zero, but have xmitbuf in pending queue\n", + __func__, ring->qlen); + break; + } + } + ring->idx = 0; + } + } + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); +} + +static void intf_chip_configure(PADAPTER padapter) +{ + +} + +/* + * Description: + * Collect all hardware information, fill "HAL_DATA_TYPE". + * Sometimes this would be used to read MAC address. + * This function will do + * 1. Read Efuse/EEPROM to initialize + * 2. Read registers to initialize + * 3. Other vaiables initialization + */ +static u8 read_adapter_info(PADAPTER padapter) +{ + /* + * 1. Read Efuse/EEPROM to initialize + */ + rtl8821c_read_efuse(padapter); + + /* + * 2. Read registers to initialize + */ + + /* + * 3. Other Initialization + */ + + return _SUCCESS; +} + +static BOOLEAN rtl8821ce_InterruptRecognized(PADAPTER Adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + BOOLEAN bRecognized = _FALSE; + + /* 2013.11.18 Glayrainx suggests that turn off IMR and + * restore after cleaning ISR. + */ + rtw_write32(Adapter, REG_HIMR0, 0); + rtw_write32(Adapter, REG_HIMR1, 0); + rtw_write32(Adapter, REG_HIMR3, 0); + + pHalData->IntArray[0] = rtw_read32(Adapter, REG_HISR0); + pHalData->IntArray[0] &= pHalData->IntrMask[0]; + rtw_write32(Adapter, REG_HISR0, pHalData->IntArray[0]); + + /* For HISR extension. Added by tynli. 2009.10.07. */ + pHalData->IntArray[1] = rtw_read32(Adapter, REG_HISR1); + pHalData->IntArray[1] &= pHalData->IntrMask[1]; + rtw_write32(Adapter, REG_HISR1, pHalData->IntArray[1]); + + /* for H2C cmd queue */ + pHalData->IntArray[3] = rtw_read32(Adapter, REG_HISR3); + pHalData->IntArray[3] &= pHalData->IntrMask[3]; + rtw_write32(Adapter, REG_HISR3, pHalData->IntArray[3]); + + if (((pHalData->IntArray[0]) & pHalData->IntrMask[0]) != 0 || + ((pHalData->IntArray[1]) & pHalData->IntrMask[1]) != 0) + bRecognized = _TRUE; + + /* restore IMR */ + rtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0] & 0xFFFFFFFF); + rtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1] & 0xFFFFFFFF); + rtw_write32(Adapter, REG_HIMR3, pHalData->IntrMask[3] & 0xFFFFFFFF); + + return bRecognized; +} + +static VOID DisableInterrupt8821ce(PADAPTER Adapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + + rtw_write32(Adapter, REG_HIMR0, 0x0); + rtw_write32(Adapter, REG_HIMR1, 0x0); + rtw_write32(Adapter, REG_HIMR3, 0x0); + pdvobjpriv->irq_enabled = 0; +} + +static VOID rtl8821ce_enable_interrupt(PADAPTER Adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + + pdvobjpriv->irq_enabled = 1; + + rtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0] & 0xFFFFFFFF); + rtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1] & 0xFFFFFFFF); + rtw_write32(Adapter, REG_HIMR3, pHalData->IntrMask[3] & 0xFFFFFFFF); + +} + +static VOID rtl8821ce_clear_interrupt(PADAPTER Adapter) +{ + u32 u32b; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + u32b = rtw_read32(Adapter, REG_HISR0_8821C); + rtw_write32(Adapter, REG_HISR0_8821C, u32b); + pHalData->IntArray[0] = 0; + + u32b = rtw_read32(Adapter, REG_HISR1_8821C); + rtw_write32(Adapter, REG_HISR1_8821C, u32b); + pHalData->IntArray[1] = 0; +} + +static VOID rtl8821ce_disable_interrupt(PADAPTER Adapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + + rtw_write32(Adapter, REG_HIMR0, 0x0); + rtw_write32(Adapter, REG_HIMR1, 0x0); /* by tynli */ + pdvobjpriv->irq_enabled = 0; +} + +VOID UpdateInterruptMask8821CE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, + u32 RemoveMSR, u32 RemoveMSR1) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + DisableInterrupt8821ce(Adapter); + + if (AddMSR) + pHalData->IntrMask[0] |= AddMSR; + + if (AddMSR1) + pHalData->IntrMask[1] |= AddMSR1; + + if (RemoveMSR) + pHalData->IntrMask[0] &= (~RemoveMSR); + + if (RemoveMSR1) + pHalData->IntrMask[1] &= (~RemoveMSR1); + + rtl8821ce_enable_interrupt(Adapter); +} + +static void rtl8821ce_bcn_handler(PADAPTER Adapter, u32 handled[]) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + if (pHalData->IntArray[0] & BIT_TXBCN0OK_MSK) { + /* do nothing */ + handled[0] |= BIT_TXBCN0OK_MSK; + } + + if (pHalData->IntArray[0] & BIT_TXBCN0ERR_MSK) { + RTW_INFO("IMR_TXBCN0ERR isr!\n"); + handled[0] |= BIT_TXBCN0ERR_MSK; + } + + if (pHalData->IntArray[0] & BIT_BCNDERR0_MSK) { + RTW_INFO("BIT_BCNDERR0_MSK isr!\n"); + handled[0] |= BIT_BCNDERR0_MSK; + } + + if (pHalData->IntArray[0] & BIT_BCNDMAINT0_MSK) { + struct tasklet_struct *bcn_tasklet; + /* Modify for MI temporary, + * this processor cannot apply to multi-ap + */ + PADAPTER bcn_adapter = rtw_mi_get_ap_adapter(Adapter); + + bcn_tasklet = &bcn_adapter->recvpriv.irq_prepare_beacon_tasklet; + tasklet_hi_schedule(bcn_tasklet); + handled[0] |= BIT_BCNDMAINT0_MSK; + } +} + +static void rtl8821ce_rx_handler(PADAPTER Adapter, u32 handled[]) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + if ((pHalData->IntArray[0] & (BIT_RXOK | BIT_RDU)) || + (pHalData->IntArray[1] & (BIT_FOVW | BIT_RXERR_INT))) { + pHalData->IntrMask[0] &= (~(BIT_RXOK_MSK | BIT_RDU_MSK)); + pHalData->IntrMask[1] &= (~(BIT_FOVW_MSK | BIT_RXERR_MSK)); + rtw_write32(Adapter, REG_HIMR0, pHalData->IntrMask[0]); + rtw_write32(Adapter, REG_HIMR1, pHalData->IntrMask[1]); + tasklet_hi_schedule(&Adapter->recvpriv.recv_tasklet); + handled[0] |= pHalData->IntArray[0] & (BIT_RXOK | BIT_RDU); + handled[1] |= pHalData->IntArray[1] & (BIT_FOVW | BIT_RXERR_INT); + } +} + +static void rtl8821ce_tx_handler(PADAPTER Adapter, u32 events[], u32 handled[]) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + if (events[0] & BIT_MGTDOK_MSK) { + rtl8821ce_tx_isr(Adapter, MGT_QUEUE_INX); + handled[0] |= BIT_MGTDOK_MSK; + } + + if (events[0] & BIT_HIGHDOK_MSK) { + rtl8821ce_tx_isr(Adapter, HIGH_QUEUE_INX); + handled[0] |= BIT_HIGHDOK_MSK; + } + + if (events[0] & BIT_BKDOK_MSK) { + rtl8821ce_tx_isr(Adapter, BK_QUEUE_INX); + handled[0] |= BIT_BKDOK_MSK; + } + + if (events[0] & BIT_BEDOK_MSK) { + rtl8821ce_tx_isr(Adapter, BE_QUEUE_INX); + handled[0] |= BIT_BEDOK_MSK; + } + + if (events[0] & BIT_VIDOK_MSK) { + rtl8821ce_tx_isr(Adapter, VI_QUEUE_INX); + handled[0] |= BIT_VIDOK_MSK; + } + + if (events[0] & BIT_VODOK_MSK) { + rtl8821ce_tx_isr(Adapter, VO_QUEUE_INX); + handled[0] |= BIT_VODOK_MSK; + } +} + +static void rtl8821ce_cmd_handler(PADAPTER Adapter, u32 handled[]) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + if (pHalData->IntArray[3] & BIT_SETH2CDOK_MASK) { + rtl8821ce_tx_isr(Adapter, TXCMD_QUEUE_INX); + handled[3] |= BIT_SETH2CDOK_MASK; + } +} + +static s32 rtl8821ce_interrupt(PADAPTER Adapter) +{ + _irqL irqL; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + struct xmit_priv *t_priv = &Adapter->xmitpriv; + int ret = _SUCCESS; + u32 handled[4] = {0}; + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + + /* read ISR: 4/8bytes */ + if (rtl8821ce_InterruptRecognized(Adapter) == _FALSE) { + ret = _FAIL; + goto done; + } + + /* <1> beacon related */ + rtl8821ce_bcn_handler(Adapter, handled); + + /* <2> Rx related */ + rtl8821ce_rx_handler(Adapter, handled); + + /* <3> Tx related */ + rtl8821ce_tx_handler(Adapter, pHalData->IntArray, handled); + + if (pHalData->IntArray[1] & BIT_TXFOVW) { + /*if (printk_ratelimit())*/ + RTW_WARN("[TXFOVW]\n"); + handled[1] |= BIT_TXFOVW; + } + + /* <4> Cmd related */ + rtl8821ce_cmd_handler(Adapter, handled); + + if ((pHalData->IntArray[0] & (~handled[0])) || (pHalData->IntArray[1] & (~handled[1])) || (pHalData->IntArray[3] & (~handled[3]))) { + /*if (printk_ratelimit()) */ + { + RTW_WARN("Unhandled ISR = %x, %x, %x\n", + (pHalData->IntArray[0] & (~handled[0])), + (pHalData->IntArray[1] & (~handled[1])), + (pHalData->IntArray[3] & (~handled[3])) + ); + } + } +done: + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + return ret; +} + +u32 rtl8821ce_init_bd(_adapter *padapter) +{ + struct xmit_priv *t_priv = &padapter->xmitpriv; + int i, ret = _SUCCESS; + + init_bd_ring_var(padapter); + ret = rtl8821ce_init_rxbd_ring(padapter); + + if (ret == _FAIL) + return ret; + + /* general process for other queue */ + for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) { + ret = rtl8821ce_init_txbd_ring(padapter, i, + t_priv->txringcount[i]); + if (ret == _FAIL) + goto err_free_rings; + } + + return ret; + +err_free_rings: + + rtl8821ce_free_rxbd_ring(padapter); + + for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) + if (t_priv->tx_ring[i].buf_desc) + rtl8821ce_free_txbd_ring(padapter, i); + + return ret; +} + +u32 rtl8821ce_free_bd(_adapter *padapter) +{ + struct xmit_priv *t_priv = &padapter->xmitpriv; + u32 i; + + /* free rxbd rings */ + rtl8821ce_free_rxbd_ring(padapter); + + /* free txbd rings */ + for (i = 0; i < HW_QUEUE_ENTRY; i++) + rtl8821ce_free_txbd_ring(padapter, i); + + return _SUCCESS; +} + +static u16 +hal_mdio_read_8821ce(PADAPTER Adapter, u8 Addr) +{ + u2Byte ret = 0; + u1Byte tmpU1b = 0, count = 0; + + rtw_write8(Adapter, REG_PCIE_MIX_CFG_8821C, Addr | BIT6); + tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT6; + count = 0; + while (tmpU1b && count < 20) { + rtw_udelay_os(10); + tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT6; + count++; + } + if (tmpU1b == 0) + ret = rtw_read16(Adapter, REG_MDIO_V1_8821C); + + return ret; +} + +static VOID +hal_mdio_write_8821ce(PADAPTER Adapter, u8 Addr, u16 Data) +{ + u1Byte tmpU1b = 0, count = 0; + + rtw_write16(Adapter, REG_MDIO_V1_8821C, Data); + rtw_write8(Adapter, REG_PCIE_MIX_CFG_8821C, Addr | BIT5); + tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT5; + count = 0; + while (tmpU1b && count < 20) { + rtw_udelay_os(10); + tmpU1b = rtw_read8(Adapter, REG_PCIE_MIX_CFG_8821C) & BIT5; + count++; + } +} + +static void hal_dbi_write_8821ce(PADAPTER Adapter, u16 Addr, u8 Data) +{ + u1Byte tmpU1b = 0, count = 0; + u2Byte WriteAddr = 0, Remainder = Addr % 4; + + /* Write DBI 1Byte Data */ + WriteAddr = REG_DBI_WDATA_V1_8821C + Remainder; + rtw_write8(Adapter, WriteAddr, Data); + + /* Write DBI 2Byte Address & Write Enable */ + WriteAddr = (Addr & 0xfffc) | (BIT0 << (Remainder + 12)); + rtw_write16(Adapter, REG_DBI_FLAG_V1_8821C, WriteAddr); + + /* Write DBI Write Flag */ + rtw_write8(Adapter, REG_DBI_FLAG_V1_8821C + 2, 0x1); + + tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2); + count = 0; + while (tmpU1b && count < 20) { + rtw_udelay_os(10); + tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2); + count++; + } +} + +static u8 hal_dbi_read_8821ce(PADAPTER Adapter, u16 Addr) +{ + u16 ReadAddr = Addr & 0xfffc; + u8 ret = 0, tmpU1b = 0, count = 0; + + rtw_write16(Adapter, REG_DBI_FLAG_V1_8821C, ReadAddr); + rtw_write8(Adapter, REG_DBI_FLAG_V1_8821C + 2, 0x2); + tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2); + count = 0; + while (tmpU1b && count < 20) { + rtw_udelay_os(10); + tmpU1b = rtw_read8(Adapter, REG_DBI_FLAG_V1_8821C + 2); + count++; + } + if (tmpU1b == 0) { + ReadAddr = REG_DBI_RDATA_V1_8821C + Addr % 4; + ret = rtw_read8(Adapter, ReadAddr); + } + + return ret; +} + +/* +* Description: +* Query setting of specified variable. +*/ +static u8 gethaldefvar(PADAPTER padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 bResult = _SUCCESS; + + switch (eVariable) { + + case HAL_DEF_MAX_RECVBUF_SZ: + *((u32 *)pValue) = MAX_RECVBUF_SZ; + break; + + case HW_VAR_MAX_RX_AMPDU_FACTOR: + *(HT_CAP_AMPDU_FACTOR *)pValue = MAX_AMPDU_FACTOR_64K; + break; + default: + bResult = rtl8821c_gethaldefvar(padapter, eVariable, pValue); + break; + } + + return bResult; +} + +/* + * Description: + * Change default setting of specified variable. + */ +static u8 sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE eVariable, void *pval) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u8 bResult = _SUCCESS; + + switch (eVariable) { + default: + bResult = rtl8821c_sethaldefvar(adapter, eVariable, pval); + break; + } + + return bResult; +} + +/* + * If variable not handled here, + * some variables will be processed in rtl8821c_sethwreg() + */ +static void sethwreg(PADAPTER adapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE hal; + u8 val8; + + hal = GET_HAL_DATA(adapter); + + switch (variable) { + + case HW_VAR_DBI: + { + u16 *pCmd; + + pCmd = (u16 *)val; + hal_dbi_write_8821ce(adapter, pCmd[0], (u8)pCmd[1]); + break; + } + case HW_VAR_MDIO: + { + u16 *pCmd; + + pCmd = (u16 *)val; + hal_mdio_write_8821ce(adapter, (u8)pCmd[0], pCmd[1]); + break; + } + default: + rtl8821c_sethwreg(adapter, variable, val); + break; + } + +} + +/* + * If variable not handled here, + * some variables will be processed in GetHwReg8723B() + */ +static void gethwreg(PADAPTER adapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE hal; + + hal = GET_HAL_DATA(adapter); + switch (variable) { + case HW_VAR_DBI: + *val = hal_dbi_read_8821ce(adapter, *((u16 *)(val))); + break; + case HW_VAR_MDIO: + *((u16 *)(val)) = hal_mdio_read_8821ce(adapter, *val); + break; + case HW_VAR_L1OFF_NIC_SUPPORT: + { + u8 l1off; + + l1off = hal_dbi_read_8821ce(adapter, 0x168); + if (l1off & (BIT2|BIT3)) + *val = _TRUE; + else + *val = _FALSE; + } + break; + case HW_VAR_L1OFF_CAPABILITY: + { + u8 l1off; + + l1off = hal_dbi_read_8821ce(adapter, 0x164); + if (l1off & (BIT2|BIT3)) + *val = _TRUE; + else + *val = _FALSE; + } + break; + default: + rtl8821c_gethwreg(adapter, variable, val); + break; + } +} + +void rtl8821ce_set_hal_ops(PADAPTER padapter) +{ + struct hal_ops *ops; + int err; + + err = rtl8821ce_halmac_init_adapter(padapter); + if (err) { + RTW_INFO("%s: [ERROR]HALMAC initialize FAIL!\n", __func__); + return; + } + + rtl8821c_set_hal_ops(padapter); + + ops = &padapter->hal_func; + + ops->hal_init = rtl8821ce_hal_init; + ops->hal_deinit = rtl8821ce_hal_deinit; + ops->inirp_init = rtl8821ce_init_bd; + ops->inirp_deinit = rtl8821ce_free_bd; + ops->irp_reset = rtl8821ce_reset_bd; + ops->init_xmit_priv = rtl8821ce_init_xmit_priv; + ops->free_xmit_priv = rtl8821ce_free_xmit_priv; + ops->init_recv_priv = rtl8821ce_init_recv_priv; + ops->free_recv_priv = rtl8821ce_free_recv_priv; + + ops->InitSwLeds = NULL; + ops->DeInitSwLeds = NULL; + + ops->init_default_value = rtl8821ce_init_default_value; + ops->intf_chip_configure = intf_chip_configure; + ops->read_adapter_info = read_adapter_info; + + ops->enable_interrupt = rtl8821ce_enable_interrupt; + ops->disable_interrupt = rtl8821ce_disable_interrupt; + ops->interrupt_handler = rtl8821ce_interrupt; + /* + * ops->check_ips_status = check_ips_status; + */ + ops->clear_interrupt = rtl8821ce_clear_interrupt; + /* + * ops->clear_interrupt = clear_interrupt_all; + */ + + ops->set_hw_reg_handler = sethwreg; + ops->GetHwRegHandler = gethwreg; + ops->get_hal_def_var_handler = gethaldefvar; + ops->SetHalDefVarHandler = sethaldefvar; + + ops->hal_xmit = rtl8821ce_hal_xmit; + ops->mgnt_xmit = rtl8821ce_mgnt_xmit; + ops->hal_xmitframe_enqueue = rtl8821ce_hal_xmitframe_enqueue; + + ops->hal_set_l1ssbackdoor_handler = rtw_pci_aspm_config_l1off_general; +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c new file mode 100644 index 000000000000..66162d078c8f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_recv.c @@ -0,0 +1,435 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821CE_RECV_C_ + +#include <drv_types.h> /* PADAPTER and etc. */ +#include <hal_data.h> /* HAL_DATA_TYPE */ +#include "../rtl8821c.h" +#include "rtl8821ce.h" + +/* Debug Buffer Descriptor Ring */ + +#define buf_desc_debug(...) do {} while (0) + +/* + * Wait until rx data is ready + * return value: _SUCCESS if Rx packet is ready, _FAIL if not ready + */ + +static u32 rtl8821ce_wait_rxrdy(_adapter *padapter, + u8 *rx_bd, u16 rx_q_idx) +{ + struct recv_priv *r_priv = &padapter->recvpriv; + u8 first_seg = 0, last_seg = 0; + u16 total_len = 0, read_cnt = 0; + + static BOOLEAN start_rx = _FALSE; + u16 status = _SUCCESS; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (rx_bd == NULL) + return _FAIL; + + total_len = (u2Byte)GET_RX_BD_TOTALRXPKTSIZE(rx_bd); + first_seg = (u1Byte)GET_RX_BD_FS(rx_bd); + last_seg = (u1Byte)GET_RX_BD_LS(rx_bd); + + buf_desc_debug("RX:%s enter: rx_bd addr = %p, total_len=%d, first_seg=%d, last_seg=%d, read_cnt %d, index %d, address %p\n", + __func__, + (u8 *)&r_priv->rx_ring[rx_q_idx].desc[r_priv->rx_ring[rx_q_idx].idx], + total_len, first_seg, last_seg, read_cnt, + r_priv->rx_ring[rx_q_idx].idx, rx_bd); + + /* Rx Tag not ported */ + if (!start_rx) { + start_rx = _TRUE; + pHalData->RxTag = 1; + } else { + while (total_len != (pHalData->RxTag + 1)) { + + read_cnt++; + + total_len = (u2Byte)GET_RX_BD_TOTALRXPKTSIZE(rx_bd); + first_seg = (u1Byte)GET_RX_BD_FS(rx_bd); + last_seg = (u1Byte)GET_RX_BD_LS(rx_bd); + + if (read_cnt > 10000) { + pHalData->RxTag = total_len; + break; + } + + if (total_len == 0 && pHalData->RxTag == 0x1fff) + break; + } + pHalData->RxTag = total_len; + } + + buf_desc_debug("RX:%s exit total_len=%d, rx_tag = %d, first_seg=%d, last_seg=%d, read_cnt %d\n", + __func__, total_len, pHalData->RxTag, + first_seg, last_seg, read_cnt); + + return status; +} + +/* + * Check the number of rxdec to be handled between + * "index of RX queue descriptor maintained by host (write pointer)" and + * "index of RX queue descriptor maintained by hardware (read pointer)" + */ +static u16 rtl8821ce_check_rxdesc_remain(_adapter *padapter, int rx_queue_idx) +{ + struct recv_priv *r_priv = &padapter->recvpriv; + u16 desc_idx_hw = 0, desc_idx_host = 0, num_rxdesc_to_handle = 0; + u32 tmp_4bytes = 0; + static BOOLEAN start_rx = FALSE; + + tmp_4bytes = rtw_read32(padapter, REG_RXQ_RXBD_IDX_8821C); + desc_idx_hw = (u16)((tmp_4bytes >> 16) & 0x7ff); + desc_idx_host = (u16)(tmp_4bytes & 0x7ff); + + /* + * make sure driver does not handle packet if hardware pointer + * keeps in zero in initial state + */ + buf_desc_debug("RX:%s(%d) reg_value %x\n", __func__, __LINE__, + tmp_4bytes); + + if (desc_idx_hw > 0) + start_rx = TRUE; + + if (!start_rx) + return 0; + + if (desc_idx_hw < desc_idx_host) + /* hw idx is turn around */ + num_rxdesc_to_handle = RX_BD_NUM_8821CE - desc_idx_host + desc_idx_hw; + else + num_rxdesc_to_handle = desc_idx_hw - desc_idx_host; + + if (num_rxdesc_to_handle == 0) + return 0; + + r_priv->rx_ring[rx_queue_idx].idx = desc_idx_host; + + buf_desc_debug("RX:%s reg_val %x, hw_idx %x, host_idx %x, desc to handle = %d\n", + __func__, tmp_4bytes, desc_idx_hw, desc_idx_host, num_rxdesc_to_handle); + + return num_rxdesc_to_handle; +} + +static void rtl8821ce_rx_mpdu(_adapter *padapter) +{ + struct recv_priv *r_priv = &padapter->recvpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + _queue *pfree_recv_queue = &r_priv->free_recv_queue; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + union recv_frame *precvframe = NULL; + u8 *pphy_info = NULL; + struct rx_pkt_attrib *pattrib = NULL; + int rx_q_idx = RX_MPDU_QUEUE; + u32 count = r_priv->rxringcount; + u16 remaing_rxdesc = 0; + u8 *rx_bd; + struct sk_buff *skb; + + /* RX NORMAL PKT */ + + remaing_rxdesc = rtl8821ce_check_rxdesc_remain(padapter, rx_q_idx); + while (remaing_rxdesc) { + + /* rx descriptor */ + rx_bd = (u8 *)&r_priv->rx_ring[rx_q_idx].buf_desc[r_priv->rx_ring[rx_q_idx].idx]; + + /* rx packet */ + skb = r_priv->rx_ring[rx_q_idx].rx_buf[r_priv->rx_ring[rx_q_idx].idx]; + + buf_desc_debug("RX:%s(%d), rx_bd addr = %x, total_len = %d, ring idx = %d\n", + __func__, __LINE__, (u32)rx_bd, + GET_RX_BD_TOTALRXPKTSIZE(rx_bd), + r_priv->rx_ring[rx_q_idx].idx); + + buf_desc_debug("RX:%s(%d), skb(rx_buf)=%x, buf addr(virtual = %x, phisycal = %x)\n", + __func__, __LINE__, (u32)skb, + (u32)(skb_tail_pointer(skb)), + GET_RX_BD_PHYSICAL_ADDR_LOW(rx_bd)); + + /* wait until packet is ready. this operation is similar to + * check own bit and should be called before pci_unmap_single + * which release memory mapping + */ + + if (rtl8821ce_wait_rxrdy(padapter, rx_bd, rx_q_idx) != + _SUCCESS) + buf_desc_debug("RX:%s(%d) packet not ready\n", + __func__, __LINE__); + + { + precvframe = rtw_alloc_recvframe(pfree_recv_queue); + + if (precvframe == NULL) + goto done; + + _rtw_init_listhead(&precvframe->u.hdr.list); + precvframe->u.hdr.len = 0; + + pci_unmap_single(pdvobjpriv->ppcidev, + *((dma_addr_t *)skb->cb), + r_priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + + rtl8821c_query_rx_desc(precvframe, skb->data); + pattrib = &precvframe->u.hdr.attrib; + + { + struct mlme_priv *mlmepriv = + &padapter->mlmepriv; + + if (check_fwstate(mlmepriv, + WIFI_MONITOR_STATE) == _FALSE) + if (pattrib->pkt_rpt_type == NORMAL_RX) + pattrib->pkt_len -= + IEEE80211_FCS_LEN; + } + + buf_desc_debug("RX:%s(%d), pkt_len = %d, pattrib->drvinfo_sz = %d, pattrib->qos = %d, pattrib->shift_sz = %d\n", + __func__, __LINE__, pattrib->pkt_len, + pattrib->drvinfo_sz, pattrib->qos, + pattrib->shift_sz); + + if (rtw_os_alloc_recvframe(padapter, precvframe, + (skb->data + HALMAC_RX_DESC_SIZE_8821C + + pattrib->drvinfo_sz + pattrib->shift_sz), + skb) == _FAIL) { + + rtw_free_recvframe(precvframe, + &r_priv->free_recv_queue); + + RTW_INFO("rtl8821ce_rx_mpdu:can't allocate memory for skb copy\n"); + *((dma_addr_t *) skb->cb) = + pci_map_single(pdvobjpriv->ppcidev, + skb_tail_pointer(skb), + r_priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + goto done; + } + + recvframe_put(precvframe, pattrib->pkt_len); + + if (pattrib->pkt_rpt_type == NORMAL_RX) { + /* Normal rx packet */ + if (pattrib->physt) + pphy_info = (u8 *)(skb->data) + + HALMAC_RX_DESC_SIZE_8821C; + + + if (pattrib->physt && pphy_info) + rx_query_phy_status(precvframe, + pphy_info); + + rtw_recv_entry(precvframe); + } else { + if (pattrib->pkt_rpt_type == C2H_PACKET) + /*To be checked for 8821CE*/ + c2h_pre_handler_rtl8821c(padapter, skb->data, HALMAC_RX_DESC_SIZE_8821C + pattrib->pkt_len); + rtw_free_recvframe(precvframe, pfree_recv_queue); + } + *((dma_addr_t *) skb->cb) = + pci_map_single(pdvobjpriv->ppcidev, + skb_tail_pointer(skb), + r_priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + } +done: + + SET_RX_BD_PHYSICAL_ADDR_LOW(rx_bd, *((dma_addr_t *)skb->cb)); + SET_RX_BD_RXBUFFSIZE(rx_bd, r_priv->rxbuffersize); + + r_priv->rx_ring[rx_q_idx].idx = + (r_priv->rx_ring[rx_q_idx].idx + 1) % + r_priv->rxringcount; + + rtw_write16(padapter, REG_RXQ_RXBD_IDX, + r_priv->rx_ring[rx_q_idx].idx); + + buf_desc_debug("RX:%s(%d) reg_value %x\n", __func__, __LINE__, + rtw_read32(padapter, REG_RXQ_RXBD_IDX)); + + remaing_rxdesc--; + } +} + +static void rtl8821ce_recv_tasklet(void *priv) +{ + _irqL irqL; + _adapter *padapter = (_adapter *)priv; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + rtl8821ce_rx_mpdu(padapter); + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + pHalData->IntrMask[0] |= (BIT_RXOK_MSK_8821C | BIT_RDU_MSK_8821C); + pHalData->IntrMask[1] |= BIT_FOVW_MSK_8821C; + rtw_write32(padapter, REG_HIMR0_8821C, pHalData->IntrMask[0]); + rtw_write32(padapter, REG_HIMR1_8821C, pHalData->IntrMask[1]); + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); +} + +static void rtl8821ce_xmit_beacon(PADAPTER Adapter) +{ + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + /* send_beacon(Adapter); */ + if (pmlmepriv->update_bcn == _TRUE) + tx_beacon_hdl(Adapter, NULL); + } +} + +static void rtl8821ce_prepare_bcn_tasklet(void *priv) +{ + _adapter *padapter = (_adapter *)priv; + + rtl8821ce_xmit_beacon(padapter); +} + +s32 rtl8821ce_init_recv_priv(_adapter *padapter) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + s32 ret = _SUCCESS; + + tasklet_init(&precvpriv->recv_tasklet, + (void(*)(unsigned long))rtl8821ce_recv_tasklet, + (unsigned long)padapter); + + tasklet_init(&precvpriv->irq_prepare_beacon_tasklet, + (void(*)(unsigned long))rtl8821ce_prepare_bcn_tasklet, + (unsigned long)padapter); + + return ret; +} + +void rtl8821ce_free_recv_priv(_adapter *padapter) +{ + +} + +int rtl8821ce_init_rxbd_ring(_adapter *padapter) +{ + struct recv_priv *r_priv = &padapter->recvpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct net_device *dev = padapter->pnetdev; + dma_addr_t *mapping = NULL; + struct sk_buff *skb = NULL; + u8 *rx_desc = NULL; + int i, rx_queue_idx; + + /* rx_queue_idx 0:RX_MPDU_QUEUE */ + /* rx_queue_idx 1:RX_CMD_QUEUE */ + for (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) { + r_priv->rx_ring[rx_queue_idx].buf_desc = + pci_alloc_consistent(pdev, + sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) * + r_priv->rxringcount, + &r_priv->rx_ring[rx_queue_idx].dma); + + if (!r_priv->rx_ring[rx_queue_idx].buf_desc || + (unsigned long)r_priv->rx_ring[rx_queue_idx].buf_desc & + 0xFF) { + RTW_INFO("Cannot allocate RX ring\n"); + return _FAIL; + } + + _rtw_memset(r_priv->rx_ring[rx_queue_idx].buf_desc, 0, + sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) * + r_priv->rxringcount); + r_priv->rx_ring[rx_queue_idx].idx = 0; + + for (i = 0; i < r_priv->rxringcount; i++) { + skb = dev_alloc_skb(r_priv->rxbuffersize); + if (!skb) { + RTW_INFO("Cannot allocate skb for RX ring\n"); + return _FAIL; + } + + rx_desc = + (u8 *)(&r_priv->rx_ring[rx_queue_idx].buf_desc[i]); + r_priv->rx_ring[rx_queue_idx].rx_buf[i] = skb; + mapping = (dma_addr_t *)skb->cb; + + /* just set skb->cb to mapping addr + * for pci_unmap_single use + */ + *mapping = pci_map_single(pdev, skb_tail_pointer(skb), + r_priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + + /* Reset FS, LS, Total len */ + SET_RX_BD_LS(rx_desc, 0); + SET_RX_BD_FS(rx_desc, 0); + SET_RX_BD_TOTALRXPKTSIZE(rx_desc, 0); + SET_RX_BD_RXBUFFSIZE(rx_desc, r_priv->rxbuffersize); + SET_RX_BD_PHYSICAL_ADDR_LOW(rx_desc, *mapping); + + buf_desc_debug("RX:rx buffer desc addr[%d] = %x, skb(rx_buf) = %x, buffer addr (virtual = %x, physical = %x)\n", + i, (u32)&r_priv->rx_ring[rx_queue_idx].buf_desc[i], + (u32)r_priv->rx_ring[rx_queue_idx].rx_buf[i], + (u32)(skb_tail_pointer(skb)), (u32)(*mapping)); + } + } + + return _SUCCESS; +} + +void rtl8821ce_free_rxbd_ring(_adapter *padapter) +{ + struct recv_priv *r_priv = &padapter->recvpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + int i, rx_queue_idx; + + /* rx_queue_idx 0:RX_MPDU_QUEUE */ + /* rx_queue_idx 1:RX_CMD_QUEUE */ + for (rx_queue_idx = 0; rx_queue_idx < 1; rx_queue_idx++) { + for (i = 0; i < r_priv->rxringcount; i++) { + struct sk_buff *skb; + + skb = r_priv->rx_ring[rx_queue_idx].rx_buf[i]; + + if (!skb) + continue; + + pci_unmap_single(pdev, + *((dma_addr_t *) skb->cb), + r_priv->rxbuffersize, + PCI_DMA_FROMDEVICE); + kfree_skb(skb); + } + + pci_free_consistent(pdev, + sizeof(*r_priv->rx_ring[rx_queue_idx].buf_desc) * + r_priv->rxringcount, + r_priv->rx_ring[rx_queue_idx].buf_desc, + r_priv->rx_ring[rx_queue_idx].dma); + r_priv->rx_ring[rx_queue_idx].buf_desc = NULL; + } + +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c new file mode 100644 index 000000000000..e3745e20b7e9 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/pci/rtl8821ce_xmit.c @@ -0,0 +1,984 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821CE_XMIT_C_ + +#include <drv_types.h> /* PADAPTER, rtw_xmit.h and etc. */ +#include <hal_data.h> /* HAL_DATA_TYPE */ +#include "../halmac/halmac_api.h" +#include "../rtl8821c.h" +#include "rtl8821ce.h" + +/* Debug Buffer Descriptor Ring */ +#define buf_desc_debug(...) do {} while (0) + +static void rtl8821ce_xmit_tasklet(void *priv) +{ + _irqL irqL; + _adapter *padapter = (_adapter *)priv; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + /* try to deal with the pending packets */ + rtl8821ce_xmitframe_resume(padapter); + +} + +s32 rtl8821ce_init_xmit_priv(_adapter *padapter) +{ + s32 ret = _SUCCESS; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + _rtw_spinlock_init(&pdvobjpriv->irq_th_lock); + + tasklet_init(&pxmitpriv->xmit_tasklet, + (void(*)(unsigned long))rtl8821ce_xmit_tasklet, + (unsigned long)padapter); + + return ret; +} + +void rtl8821ce_free_xmit_priv(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + _rtw_spinlock_free(&pdvobjpriv->irq_th_lock); +} + +static s32 rtl8821ce_enqueue_xmitbuf(struct rtw_tx_ring *ring, + struct xmit_buf *pxmitbuf) +{ + _irqL irqL; + _queue *ppending_queue = &ring->queue; + + if (pxmitbuf == NULL) + return _FAIL; + + rtw_list_delete(&pxmitbuf->list); + rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(ppending_queue)); + ring->qlen++; + + return _SUCCESS; +} + +struct xmit_buf *rtl8821ce_dequeue_xmitbuf(struct rtw_tx_ring *ring) +{ + _irqL irqL; + _list *plist, *phead; + struct xmit_buf *pxmitbuf = NULL; + _queue *ppending_queue = &ring->queue; + + if (_rtw_queue_empty(ppending_queue) == _TRUE) + pxmitbuf = NULL; + else { + + phead = get_list_head(ppending_queue); + plist = get_next(phead); + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + rtw_list_delete(&(pxmitbuf->list)); + ring->qlen--; + } + + return pxmitbuf; +} + +static u8 *get_txbd(_adapter *padapter, u8 q_idx) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_ring *ring; + u8 *ptxbd = NULL; + int idx = 0; + + ring = &pxmitpriv->tx_ring[q_idx]; + + /* DO NOT use last entry. */ + /* (len -1) to avoid wrap around overlap problem in cycler queue. */ + if (ring->qlen == (ring->entries - 1)) { + RTW_INFO("No more TX desc@%d, ring->idx = %d,idx = %d\n", + q_idx, ring->idx, idx); + return NULL; + } + + if (q_idx == BCN_QUEUE_INX) + idx = 0; + else + idx = (ring->idx + ring->qlen) % ring->entries; + + ptxbd = (u8 *)&ring->buf_desc[idx]; + + return ptxbd; +} + +/* + * Get txbd reg addr according to q_sel + */ +static u16 get_txbd_rw_reg(u16 q_idx) +{ + u16 txbd_reg_addr = REG_BEQ_TXBD_IDX; + + switch (q_idx) { + + case BK_QUEUE_INX: + txbd_reg_addr = REG_BKQ_TXBD_IDX; + break; + + case BE_QUEUE_INX: + txbd_reg_addr = REG_BEQ_TXBD_IDX; + break; + + case VI_QUEUE_INX: + txbd_reg_addr = REG_VIQ_TXBD_IDX; + break; + + case VO_QUEUE_INX: + txbd_reg_addr = REG_VOQ_TXBD_IDX; + break; + + case BCN_QUEUE_INX: + txbd_reg_addr = REG_BEQ_TXBD_IDX; /* need check */ + break; + + case TXCMD_QUEUE_INX: + txbd_reg_addr = REG_H2CQ_TXBD_IDX; + break; + + case MGT_QUEUE_INX: + txbd_reg_addr = REG_MGQ_TXBD_IDX; + break; + + case HIGH_QUEUE_INX: + txbd_reg_addr = REG_HI0Q_TXBD_IDX; /* need check */ + break; + + default: + break; + } + + return txbd_reg_addr; +} + +struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type) +{ + _adapter *padapter; + u16 queue_idx = BCN_QUEUE_INX; + u8 *ptxdesc = NULL; + + padapter = GET_PRIMARY_ADAPTER(pxmitpriv->adapter); + + ptxdesc = get_txbd(padapter, BCN_QUEUE_INX); + + /* set OWN bit in Beacon tx descriptor */ + if (ptxdesc != NULL) + SET_TX_BD_OWN(ptxdesc, 0); + else + return NULL; + + return __rtw_alloc_cmdxmitframe(pxmitpriv, CMDBUF_BEACON); +} + +/* + * Update Read/Write pointer + * Read pointer is h/w descriptor index + * Write pointer is host desciptor index: + * For tx side, if own bit is set in packet index n, + * host pointer (write pointer) point to index n + 1.) + */ +void fill_txbd_own(_adapter *padapter, u8 *txbd, u16 queue_idx, + struct rtw_tx_ring *ptxring) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_ring *ring; + u16 host_wp = 0; + + if (queue_idx == BCN_QUEUE_INX) { + + SET_TX_BD_OWN(txbd, 1); + + /* kick start */ + rtw_write8(padapter, REG_RX_RXBD_NUM + 1, + rtw_read8(padapter, REG_RX_RXBD_NUM + 1) | BIT(4)); + + return; + } + + /* + * update h/w index + * for tx side, if own bit is set in packet index n, + * host pointer (write pointer) point to index n + 1. + */ + + /* for current tx packet, enqueue has been ring->qlen++ before. + * so, host_wp = ring->idx + ring->qlen. + */ + host_wp = (ptxring->idx + ptxring->qlen) % ptxring->entries; + rtw_write16(padapter, get_txbd_rw_reg(queue_idx), host_wp); +} + +/* + * Fill tx buffer desciptor. Map each buffer address in tx buffer descriptor + * segment. Designed for tx buffer descriptor architecture + * Input *pmem: pointer to the Tx Buffer Descriptor + */ +static void rtl8821ce_update_txbd(struct xmit_frame *pxmitframe, + u8 *txbd, s32 sz) +{ + _adapter *padapter = pxmitframe->padapter; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + dma_addr_t mapping; + u32 i = 0; + u16 seg_num = + ((TX_BUFFER_SEG_NUM == 0) ? 2 : ((TX_BUFFER_SEG_NUM == 1) ? 4 : 8)); + u16 tx_page_size_reg = 1; + u16 page_size_length = 0; + + /* map TX DESC buf_addr (including TX DESC + tx data) */ + mapping = pci_map_single(pdvobjpriv->ppcidev, pxmitframe->buf_addr, + sz + TX_WIFI_INFO_SIZE, PCI_DMA_TODEVICE); + + /* Calculate page size. + * Total buffer length including TX_WIFI_INFO and PacketLen + */ + if (tx_page_size_reg > 0) { + page_size_length = (sz + TX_WIFI_INFO_SIZE) / + (tx_page_size_reg * 128); + if (((sz + TX_WIFI_INFO_SIZE) % (tx_page_size_reg * 128)) > 0) + page_size_length++; + } + + /* + * Reset all tx buffer desciprtor content + * -- Reset first element + */ + SET_TX_BD_TX_BUFF_SIZE0(txbd, 0); + SET_TX_BD_PSB(txbd, 0); + SET_TX_BD_OWN(txbd, 0); + + /* -- Reset second and other element */ + for (i = 1 ; i < seg_num ; i++) { + SET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, i, 0); + SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, i, 0); + SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, i, 0); + } + + /* + * Fill buffer length of the first buffer, + * For 8821ce, it is required that TX_WIFI_INFO is put in first segment, + * and the size of the first segment cannot be larger than + * TX_WIFI_INFO_SIZE. + */ + SET_TX_BD_TX_BUFF_SIZE0(txbd, TX_WIFI_INFO_SIZE); + SET_TX_BD_PSB(txbd, page_size_length); + /* starting addr of TXDESC */ + SET_TX_BD_PHYSICAL_ADDR0_LOW(txbd, mapping); + + /* + * It is assumed that in linux implementation, packet is coalesced + * in only one buffer. Extension mode is not supported here + */ + SET_TXBUFFER_DESC_LEN_WITH_OFFSET(txbd, 1, sz); + /* don't using extendsion mode. */ + SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(txbd, 1, 0); + SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(txbd, 1, + mapping + TX_WIFI_INFO_SIZE); /* pkt */ + + /*buf_desc_debug("TX:%s, txbd = 0x%p\n", __FUNCTION__, txbd);*/ + buf_desc_debug("%s, txbd = 0x%08x\n", __func__, txbd); + buf_desc_debug("TXBD:, 00h(0x%08x)\n", *((u32 *)(txbd))); + buf_desc_debug("TXBD:, 04h(0x%08x)\n", *((u32 *)(txbd + 4))); + buf_desc_debug("TXBD:, 08h(0x%08x)\n", *((u32 *)(txbd + 8))); + buf_desc_debug("TXBD:, 12h(0x%08x)\n", *((u32 *)(txbd + 12))); + +} + +static s32 update_txdesc(struct xmit_frame *pxmitframe, s32 sz) +{ + uint qsel; + u8 data_rate, pwr_status; + _adapter *padapter = pxmitframe->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pkt_attrib *pattrib = &pxmitframe->attrib; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *ptxdesc; + sint bmcst = IS_MCAST(pattrib->ra); + u16 SWDefineContent = 0x0; + u8 DriverFixedRate = 0x0; + + ptxdesc = pxmitframe->buf_addr; + _rtw_memset(ptxdesc, 0, TXDESC_SIZE); + + /* offset 0 */ + /*SET_TX_DESC_FIRST_SEG_8812(ptxdesc, 1);*/ + SET_TX_DESC_LS_8821C(ptxdesc, 1); + /*SET_TX_DESC_OWN_8812(ptxdesc, 1);*/ + + SET_TX_DESC_TXPKTSIZE_8821C(ptxdesc, sz); + SET_TX_DESC_OFFSET_8821C(ptxdesc, TXDESC_SIZE); + + + if (bmcst) + SET_TX_DESC_BMC_8821C(ptxdesc, 1); + + SET_TX_DESC_MACID_8821C(ptxdesc, pattrib->mac_id); + SET_TX_DESC_RATE_ID_8821C(ptxdesc, pattrib->raid); + + SET_TX_DESC_QSEL_8821C(ptxdesc, pattrib->qsel); + + if (!pattrib->qos_en) { + /* Hw set sequence number */ + SET_TX_DESC_EN_HWSEQ_8821C(ptxdesc, 1); + SET_TX_DESC_EN_HWEXSEQ_8821C(ptxdesc, 0); + SET_TX_DESC_DISQSELSEQ_8821C(ptxdesc, 1); + SET_TX_DESC_HW_SSN_SEL_8821C(ptxdesc, 0); + } else + SET_TX_DESC_SW_SEQ_8821C(ptxdesc, pattrib->seqnum); + + if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) { + rtl8821c_fill_txdesc_sectype(pattrib, ptxdesc); + rtl8821c_fill_txdesc_vcs(padapter, pattrib, ptxdesc); + + + if ((pattrib->ether_type != 0x888e) && + (pattrib->ether_type != 0x0806) && + (pattrib->ether_type != 0x88b4) && + (pattrib->dhcp_pkt != 1) + ) { + /* Non EAP & ARP & DHCP type data packet */ + + if (pattrib->ampdu_en == _TRUE) { + /* 8821c does NOT support AGG broadcast pkt */ + if (!bmcst) + SET_TX_DESC_AGG_EN_8821C(ptxdesc, 1); + + SET_TX_DESC_MAX_AGG_NUM_8821C(ptxdesc, 0x1f); + /* Set A-MPDU aggregation. */ + SET_TX_DESC_AMPDU_DENSITY_8821C(ptxdesc, + pattrib->ampdu_spacing); + } else + SET_TX_DESC_BK_8821C(ptxdesc, 1); + + rtl8821c_fill_txdesc_phy(padapter, pattrib, ptxdesc); + + /* DATA Rate FB LMT */ + /* compatibility for MCC consideration, + * use pmlmeext->cur_channel + */ + if (pmlmeext->cur_channel > 14) + /* for 5G. OFMD 6M */ + SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C( + ptxdesc, 4); + else + /* for 2.4G. CCK 1M */ + SET_TX_DESC_DATA_RTY_LOWEST_RATE_8821C( + ptxdesc, 0); + + if (pHalData->fw_ractrl == _FALSE) { + SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1); + DriverFixedRate = 0x01; + + if (pHalData->INIDATA_RATE[pattrib->mac_id] & + BIT(7)) + SET_TX_DESC_DATA_SHORT_8821C( + ptxdesc, 1); + + SET_TX_DESC_DATARATE_8821C(ptxdesc, + pHalData->INIDATA_RATE[pattrib->mac_id] + & 0x7F); + } + + if (padapter->fix_rate != 0xFF) { + /* modify data rate by iwpriv */ + SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1); + + DriverFixedRate = 0x01; + if (padapter->fix_rate & BIT(7)) + SET_TX_DESC_DATA_SHORT_8821C( + ptxdesc, 1); + + SET_TX_DESC_DATARATE_8821C(ptxdesc, + (padapter->fix_rate & 0x7F)); + if (!padapter->data_fb) + SET_TX_DESC_DISDATAFB_8821C(ptxdesc, 1); + } + + if (pattrib->ldpc) + SET_TX_DESC_DATA_LDPC_8821C(ptxdesc, 1); + if (pattrib->stbc) + SET_TX_DESC_DATA_STBC_8821C(ptxdesc, 1); + } else { + /* + * EAP data packet and ARP packet and DHCP. + * Use the 1M data rate to send the EAP/ARP packet. + * This will maybe make the handshake smooth. + */ + + SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1); + DriverFixedRate = 0x01; + SET_TX_DESC_BK_8821C(ptxdesc, 1); + + /* HW will ignore this setting if the transmission rate + * is legacy OFDM. + */ + if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) + SET_TX_DESC_DATA_SHORT_8821C(ptxdesc, 1); + + SET_TX_DESC_DATARATE_8821C(ptxdesc, + MRateToHwRate(pmlmeext->tx_rate)); + } + + } else if ((pxmitframe->frame_tag & 0x0f) == MGNT_FRAMETAG) { + SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1); + DriverFixedRate = 0x01; + + SET_TX_DESC_DATARATE_8821C(ptxdesc, MRateToHwRate(pattrib->rate)); + + SET_TX_DESC_RTY_LMT_EN_8821C(ptxdesc, 1); + if (pattrib->retry_ctrl == _TRUE) + SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(ptxdesc, 6); + else + SET_TX_DESC_RTS_DATA_RTY_LMT_8821C(ptxdesc, 12); + + /*rtl8821c_fill_txdesc_mgnt_bf(pxmitframe, ptxdesc); Todo for 8821C*/ + + /* CCX-TXRPT ack for xmit mgmt frames. */ + if (pxmitframe->ack_report) { + SET_TX_DESC_SPE_RPT_8821C(ptxdesc, 1); + } + } else if ((pxmitframe->frame_tag & 0x0f) == TXAGG_FRAMETAG) + RTW_INFO("pxmitframe->frame_tag == TXAGG_FRAMETAG\n"); + else if (((pxmitframe->frame_tag & 0x0f) == MP_FRAMETAG) && + (padapter->registrypriv.mp_mode == 1)) + fill_txdesc_for_mp(padapter, ptxdesc); + else { + RTW_INFO("pxmitframe->frame_tag = %d\n", + pxmitframe->frame_tag); + + SET_TX_DESC_USE_RATE_8821C(ptxdesc, 1); + DriverFixedRate = 0x01; + SET_TX_DESC_DATARATE_8821C(ptxdesc, + MRateToHwRate(pmlmeext->tx_rate)); + } + + + /*rtl8821c_fill_txdesc_bf(pxmitframe, ptxdesc);Todo for 8821C*/ + + /*SET_TX_DESC_TX_BUFFER_SIZE_8812(ptxdesc, sz);*/ + + if (DriverFixedRate) + SWDefineContent |= 0x01; + + SET_TX_DESC_SW_DEFINE_8821C(ptxdesc, SWDefineContent); + + SET_TX_DESC_PORT_ID_8821C(ptxdesc, get_hw_port(padapter)); + SET_TX_DESC_MULTIPLE_PORT_8821C(ptxdesc, get_hw_port(padapter)); + + rtl8821c_cal_txdesc_chksum(padapter, ptxdesc); + rtl8821c_dbg_dump_tx_desc(padapter, pxmitframe->frame_tag, ptxdesc); + return 0; +} + +s32 rtl8821ce_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + s32 ret = _SUCCESS; + s32 inner_ret = _SUCCESS; + _irqL irqL; + int t, sz, w_sz, pull = 0; + u32 ff_hwaddr; + struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct security_priv *psecuritypriv = &padapter->securitypriv; + u8 *txbd; + struct rtw_tx_ring *ptx_ring; + + if ((pxmitframe->frame_tag == DATA_FRAMETAG) && + (pxmitframe->attrib.ether_type != 0x0806) && + (pxmitframe->attrib.ether_type != 0x888e) && + (pxmitframe->attrib.dhcp_pkt != 1)) + rtw_issue_addbareq_cmd(padapter, pxmitframe); + + for (t = 0; t < pattrib->nr_frags; t++) { + + if (inner_ret != _SUCCESS && ret == _SUCCESS) + ret = _FAIL; + + if (t != (pattrib->nr_frags - 1)) { + + sz = pxmitpriv->frag_len - 4; + + if (!psecuritypriv->sw_encrypt) + sz -= pattrib->icv_len; + } else { + /* no frag */ + sz = pattrib->last_txcmdsz; + } + + ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + txbd = get_txbd(GET_PRIMARY_ADAPTER(padapter), ff_hwaddr); + + ptx_ring = &(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.tx_ring[ff_hwaddr]); + + + if (txbd == NULL) { + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + rtw_sctx_done_err(&pxmitbuf->sctx, + RTW_SCTX_DONE_TX_DESC_NA); + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + RTW_INFO("##### Tx desc unavailable !#####\n"); + break; + } + + if (pattrib->qsel != HALMAC_TXDESC_QSEL_H2C_CMD) + update_txdesc(pxmitframe, sz); + + /* rtl8821ce_update_txbd() must be called after update_txdesc() + * It rely on rtl8821ce_update_txbd() to map it into non cache memory + */ + + rtl8821ce_update_txbd(pxmitframe, txbd, sz); + + if (pxmitbuf->buf_tag != XMITBUF_CMD) + rtl8821ce_enqueue_xmitbuf(ptx_ring, pxmitbuf); + + pxmitbuf->len = sz + TX_WIFI_INFO_SIZE; + w_sz = sz; + + /* Please comment here */ + wmb(); + fill_txbd_own(padapter, txbd, ff_hwaddr, ptx_ring); + + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + + inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, + (unsigned char *)pxmitbuf); + + rtw_count_tx_stats(padapter, pxmitframe, sz); + } + + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + if (ret != _SUCCESS) + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN); + + return ret; +} + +/* + * Packet should not be dequeued if there is no available descriptor + * return: _SUCCESS if there is available descriptor + */ +static u8 check_tx_desc_resource(_adapter *padapter, int prio) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_ring *ring; + + ring = &pxmitpriv->tx_ring[prio]; + + /* + * for now we reserve two free descriptor as a safety boundary + * between the tail and the head + */ + + if ((ring->entries - ring->qlen) >= 2) + return _TRUE; + else + return _FALSE; +} + +static u8 check_nic_enough_desc_all(_adapter *padapter) +{ + u8 status = (check_tx_desc_resource(padapter, VI_QUEUE_INX) && + check_tx_desc_resource(padapter, VO_QUEUE_INX) && + check_tx_desc_resource(padapter, BE_QUEUE_INX) && + check_tx_desc_resource(padapter, BK_QUEUE_INX) && + check_tx_desc_resource(padapter, MGT_QUEUE_INX) && + check_tx_desc_resource(padapter, TXCMD_QUEUE_INX) && + check_tx_desc_resource(padapter, HIGH_QUEUE_INX)); + return status; +} + +static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + s32 res = _SUCCESS; + + res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); + if (res == _SUCCESS) + rtl8821ce_dump_xframe(padapter, pxmitframe); + + return res; +} + + +void rtl8821ce_xmitframe_resume(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pxmitframe = NULL; + struct xmit_buf *pxmitbuf = NULL; + int res = _SUCCESS, xcnt = 0; + + + while (1) { + if (RTW_CANNOT_RUN(padapter)) { + RTW_INFO("%s => bDriverStopped or bSurpriseRemoved\n", + __func__); + break; + } + + if (!check_nic_enough_desc_all(padapter)) + break; + + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (!pxmitbuf) + break; + + + pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, + pxmitpriv->hwxmit_entry); + + if (pxmitframe) { + pxmitframe->pxmitbuf = pxmitbuf; + pxmitframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pxmitframe; + + if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) { + if (pxmitframe->attrib.priority <= 15) { + /* TID0~15 */ + res = rtw_xmitframe_coalesce(padapter, + pxmitframe->pkt, pxmitframe); + } + + /* always return ndis_packet after + * rtw_xmitframe_coalesce + */ + rtw_os_xmit_complete(padapter, pxmitframe); + } + + if (res == _SUCCESS) + rtl8821ce_dump_xframe(padapter, pxmitframe); + else { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } + + xcnt++; + } else { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + break; + } + } +} + +static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u32 prio; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct rtw_tx_ring *ring; + + switch (pattrib->qsel) { + case 0: + case 3: + prio = BE_QUEUE_INX; + break; + case 1: + case 2: + prio = BK_QUEUE_INX; + break; + case 4: + case 5: + prio = VI_QUEUE_INX; + break; + case 6: + case 7: + prio = VO_QUEUE_INX; + break; + default: + prio = BE_QUEUE_INX; + break; + } + + ring = &pxmitpriv->tx_ring[prio]; + + /* + * for now we reserve two free descriptor as a safety boundary + * between the tail and the head + */ + if ((ring->entries - ring->qlen) >= 2) + return _TRUE; + else + return _FALSE; +} + +/* + * Return + * _TRUE dump packet directly + * _FALSE enqueue packet + */ +static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + _irqL irqL; + s32 res; + struct xmit_buf *pxmitbuf = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + if ((rtw_txframes_sta_ac_pending(padapter, pattrib) > 0) || + (check_nic_enough_desc(padapter, pattrib) == _FALSE)) + goto enqueue; + + if (rtw_xmit_ac_blocked(padapter) == _TRUE) + goto enqueue; + + if (DEV_STA_LG_NUM(padapter->dvobj)) + goto enqueue; + + + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (pxmitbuf == NULL) + goto enqueue; + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + pxmitframe->pxmitbuf = pxmitbuf; + pxmitframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pxmitframe; + + if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } + + return _TRUE; + +enqueue: + res = rtw_xmitframe_enqueue(padapter, pxmitframe); + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + if (res != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + pxmitpriv->tx_drop++; + return _TRUE; + } + + return _FALSE; +} + +s32 rtl8821ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + return rtl8821ce_dump_xframe(padapter, pmgntframe); +} + +/* + * Return + * _TRUE dump packet directly ok + * _FALSE temporary can't transmit packets to hardware + */ +s32 rtl8821ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + return pre_xmitframe(padapter, pxmitframe); +} + +s32 rtl8821ce_hal_xmitframe_enqueue(_adapter *padapter, + struct xmit_frame *pxmitframe) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + s32 err; + + err = rtw_xmitframe_enqueue(padapter, pxmitframe); + if (err != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + pxmitpriv->tx_drop++; + } else { + if (check_nic_enough_desc(padapter, + &pxmitframe->attrib) == _TRUE) + tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + } + + return err; +} + +int rtl8821ce_init_txbd_ring(_adapter *padapter, unsigned int q_idx, + unsigned int entries) +{ + struct xmit_priv *t_priv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct tx_buf_desc *txbd; + u8 *tx_desc; + dma_addr_t dma; + int i; + + RTW_INFO("%s entries num:%d\n", __func__, entries); + + txbd = pci_alloc_consistent(pdev, sizeof(*txbd) * entries, &dma); + + if (!txbd || (unsigned long)txbd & 0xFF) { + RTW_INFO("Cannot allocate TXBD (q_idx = %d)\n", q_idx); + return _FAIL; + } + + _rtw_memset(txbd, 0, sizeof(*txbd) * entries); + t_priv->tx_ring[q_idx].buf_desc = txbd; + t_priv->tx_ring[q_idx].dma = dma; + t_priv->tx_ring[q_idx].idx = 0; + t_priv->tx_ring[q_idx].entries = entries; + _rtw_init_queue(&t_priv->tx_ring[q_idx].queue); + t_priv->tx_ring[q_idx].qlen = 0; + + RTW_INFO("%s queue:%d, ring_addr:%p\n", __func__, q_idx, txbd); + + return _SUCCESS; +} + +void rtl8821ce_free_txbd_ring(_adapter *padapter, unsigned int prio) +{ + struct xmit_priv *t_priv = &padapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct rtw_tx_ring *ring = &t_priv->tx_ring[prio]; + u8 *txbd; + struct xmit_buf *pxmitbuf; + + while (ring->qlen) { + txbd = (u8 *)(&ring->buf_desc[ring->idx]); + SET_TX_BD_OWN(txbd, 0); + + if (prio != BCN_QUEUE_INX) + ring->idx = (ring->idx + 1) % ring->entries; + + pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring); + + if (pxmitbuf) { + pci_unmap_single(pdev, + GET_TX_BD_PHYSICAL_ADDR0_LOW(txbd), + pxmitbuf->len, PCI_DMA_TODEVICE); + + rtw_free_xmitbuf(t_priv, pxmitbuf); + + } else { + RTW_INFO("%s qlen=%d!=0,but have xmitbuf in pendingQ\n", + __func__, ring->qlen); + break; + } + } + + pci_free_consistent(pdev, sizeof(*ring->buf_desc) * ring->entries, + ring->buf_desc, ring->dma); + ring->buf_desc = NULL; + +} + +/* + * Draw a line to show queue status. For debug + * i: queue index / W:HW index / h:host index / .: enpty entry / *:ready to DMA + * Example: R- 3- 4- 8 ..iW***h..... (i=3,W=4,h=8, + * *** means 3 tx_desc is reaady to dma) + */ + +/* + * Read pointer is h/w descriptor index + * Write pointer is host desciptor index: For tx side, if own bit is set in + * packet index n, host pointer (write pointer) point to index n + 1. + */ +static u32 rtl8821ce_check_txdesc_closed(PADAPTER Adapter, u32 queue_idx, + struct rtw_tx_ring *ring) +{ + /* + * hw_rp_cache is used to reduce REG access. + */ + u32 tmp32; + + /* bcn queue should not enter this function */ + if (queue_idx == BCN_QUEUE_INX) + return _TRUE; + + /* qlen == 0 --> don't need to process */ + if (ring->qlen == 0) + return _FALSE; + + /* sw_rp == hw_rp_cache --> sync hw_rp */ + if (ring->idx == ring->hw_rp_cache) { + + tmp32 = rtw_read32(Adapter, get_txbd_rw_reg(queue_idx)); + + ring->hw_rp_cache = (tmp32 >> 16) & 0x0FFF; + } + + /* check if need to handle TXOK */ + if (ring->idx == ring->hw_rp_cache) + return _FALSE; + + return _TRUE; +} + +void rtl8821ce_tx_isr(PADAPTER Adapter, int prio) +{ + struct xmit_priv *t_priv = &Adapter->xmitpriv; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + struct rtw_tx_ring *ring = &t_priv->tx_ring[prio]; + struct xmit_buf *pxmitbuf; + u8 *tx_desc; + u16 tmp_4bytes; + u16 desc_idx_hw = 0, desc_idx_host = 0; + + while (ring->qlen) { + tx_desc = (u8 *)&ring->buf_desc[ring->idx]; + + /* beacon use cmd buf Never run into here */ + if (!rtl8821ce_check_txdesc_closed(Adapter, prio, ring)) + return; + + buf_desc_debug("TX: %s, q_idx = %d, tx_bd = %04x, close [%04x] r_idx [%04x]\n", + __func__, prio, (u32)tx_desc, ring->idx, + (ring->idx + 1) % ring->entries); + + ring->idx = (ring->idx + 1) % ring->entries; + pxmitbuf = rtl8821ce_dequeue_xmitbuf(ring); + + if (pxmitbuf) { + pci_unmap_single(pdvobjpriv->ppcidev, + GET_TX_BD_PHYSICAL_ADDR0_LOW(tx_desc), + pxmitbuf->len, PCI_DMA_TODEVICE); + rtw_sctx_done(&pxmitbuf->sctx); + rtw_free_xmitbuf(&(pxmitbuf->padapter->xmitpriv), + pxmitbuf); + } else { + RTW_INFO("%s qlen=%d!=0,but have xmitbuf in pendingQ\n", + __func__, ring->qlen); + } + } + + if (check_tx_desc_resource(Adapter, prio) + && rtw_xmit_ac_blocked(Adapter) != _TRUE) + rtw_mi_xmit_tasklet_schedule(Adapter); +} + + diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c.h b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c.h new file mode 100644 index 000000000000..9cb3db9a5c64 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** +* +* Copyright(c) 2016 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ +#ifndef _RTL8821C_H_ +#define _RTL8821C_H_ + +#include <drv_types.h> /* PADAPTER */ +#include <rtw_rf.h> /* CHANNEL_WIDTH */ +#include <rtw_xmit.h> /* struct pkt_attrib, struct xmit_frame */ +#include <rtw_recv.h> /* struct recv_frame */ +#include <hal_intf.h> /* HAL_DEF_VARIABLE */ + +#define DRIVER_EARLY_INT_TIME_8821C 0x05 +#define BCN_DMA_ATIME_INT_TIME_8821C 0x02 + +/* rtl8821c_halinit.c */ +u32 rtl8821c_power_on(PADAPTER); +void rtl8821c_power_off(PADAPTER); +u8 rtl8821c_mac_init(PADAPTER); +u8 rtl8821c_mac_verify(PADAPTER); +void rtl8821c_hal_init_channel_setting(PADAPTER adapter); +void rtl8821c_hal_init_misc(PADAPTER padapter); +u32 rtl8821c_hal_init(PADAPTER); +u32 rtl8821c_hal_deinit(PADAPTER); +void rtl8821c_init_default_value(PADAPTER); +u8 rtl8821c_phy_init(PADAPTER adapter); +u8 rtl8821c_init_phy_parameter_mac(PADAPTER adapter); + +#define BIT_PRETXERR_HANDLE_IMR BIT(31) +#define BIT_PRETXERR_HANDLE_ISR BIT(31) +#define BIT_PRETXERR BIT(7) +void rtl8821c_pretx_cd_config(_adapter *adapter); + +/* rtl8821c_mac.c */ +u8 rtl8821c_rcr_config(PADAPTER, u32 rcr); +u8 rtl8821c_rcr_get(PADAPTER, u32 *rcr); +u8 rtl8821c_rcr_check(PADAPTER, u32 check_bit); +u8 rtl8821c_rcr_add(PADAPTER, u32 add); +u8 rtl8821c_rcr_clear(PADAPTER, u32 clear); +u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter); +u8 rtl8821c_rx_ba_ssn_appended(PADAPTER); +u8 rtl8821c_rx_fcs_append_switch(PADAPTER, u8 enable); +u8 rtl8821c_rx_fcs_appended(PADAPTER); +u8 rtl8821c_rx_tsf_addr_filter_config(_adapter *adapter, u8 config); +s32 rtl8821c_fw_dl(PADAPTER); +s32 rtl8821c_fw_mem_dl(PADAPTER adapter, enum fw_mem mem); + +/* rtl8821c_ops.c */ +u8 rtl8821c_read_efuse(PADAPTER); +void rtl8821c_run_thread(PADAPTER); +void rtl8821c_cancel_thread(PADAPTER); +void rtl8821c_sethwreg(PADAPTER, u8 variable, u8 *pval); +void rtl8821c_gethwreg(PADAPTER, u8 variable, u8 *pval); +u8 rtl8821c_sethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); +u8 rtl8821c_gethaldefvar(PADAPTER, HAL_DEF_VARIABLE, void *pval); +void rtl8821c_set_hal_ops(PADAPTER); +void rtl8821c_resume_tx_beacon(PADAPTER); +void rtl8821c_stop_tx_beacon(PADAPTER); + +/* tx */ +void rtl8821c_init_xmit_priv(_adapter *adapter); +void rtl8821c_fill_txdesc_sectype(struct pkt_attrib *, u8 *ptxdesc); +void rtl8821c_fill_txdesc_vcs(PADAPTER, struct pkt_attrib *, u8 *ptxdesc); +void rtl8821c_fill_txdesc_phy(PADAPTER, struct pkt_attrib *, u8 *ptxdesc); +u8 rtl8821c_bw_mapping(PADAPTER, struct pkt_attrib *); +u8 rtl8821c_sc_mapping(PADAPTER, struct pkt_attrib *); +void rtl8821c_cal_txdesc_chksum(PADAPTER, u8 *ptxdesc); +void rtl8821c_update_txdesc(struct xmit_frame *, u8 *pbuf); +void rtl8821c_dbg_dump_tx_desc(PADAPTER, int frame_tag, u8 *ptxdesc); + +/* rx */ +void rtl8821c_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc); +void rtl8821c_query_rx_desc(union recv_frame *, u8 *pdesc); + +/* rtl8821c_cmd.c */ +s32 rtl8821c_fillh2ccmd(PADAPTER, u8 id, u32 buf_len, u8 *pbuf); +void rtl8821c_set_FwMacIdConfig_cmd(PADAPTER , u64 bitmap, u8 *arg, u8 bw); +void rtl8821c_set_FwRssiSetting_cmd(PADAPTER, u8 *param); +void rtl8821c_set_FwPwrMode_cmd(PADAPTER, u8 psmode); +void rtl8821c_set_FwPwrModeInIPS_cmd(PADAPTER adapter, u8 cmd_param); +void rtl8821c_fw_update_beacon_cmd(PADAPTER); +void c2h_handler_rtl8821c(_adapter *adapter, u8 *pbuf, u16 length); +void c2h_pre_handler_rtl8821c(_adapter *adapter, u8 *pbuf, s32 length); +void rtl8821c_download_BTCoex_AP_mode_rsvd_page(PADAPTER); + +/* rtl8821c_phy.c */ +u32 rtl8821c_read_bb_reg(PADAPTER, u32 addr, u32 mask); +void rtl8821c_write_bb_reg(PADAPTER, u32 addr, u32 mask, u32 val); +u32 rtl8821c_read_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask); +void rtl8821c_write_rf_reg(PADAPTER, u8 path, u32 addr, u32 mask, u32 val); +void rtl8821c_set_channel_bw(PADAPTER, u8 center_ch, CHANNEL_WIDTH, u8 offset40, u8 offset80); +void rtl8821c_set_tx_power_level(PADAPTER, u8 channel); +void rtl8821c_get_tx_power_level(PADAPTER, s32 *power); +void rtl8821c_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); +u8 rtl8821c_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); +void rtl8821c_notch_filter_switch(PADAPTER, bool enable); + +#endif /* _RTL8821C_H_ */ diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c new file mode 100644 index 000000000000..8061e34bbf37 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_cmd.c @@ -0,0 +1,816 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821C_CMD_C_ + +#include <hal_data.h> /* HAL_DATA_TYPE */ +#include "../hal_halmac.h" /* HRTW_HALMAC_H2C_MAX_SIZE, CMD_ID_RSVD_PAGE and etc. */ +#include "rtl8821c.h" + +/* + * Below functions are for C2H + */ +/***************************************** + * H2C Msg format : + *| 31 - 8 |7-5 | 4 - 0 | + *| h2c_msg |Class |CMD_ID | + *| 31-0 | + *| Ext msg | + * + ******************************************/ +s32 rtl8821c_fillh2ccmd(PADAPTER adapter, u8 id, u32 buf_len, u8 *pbuf) +{ + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + int err; + s32 ret = _FAIL; + + if (!pbuf) + goto exit; + + if (buf_len > (RTW_HALMAC_H2C_MAX_SIZE - 1)) + goto exit; + + if (rtw_is_surprise_removed(adapter)) + goto exit; + + + h2c[0] = id; + _rtw_memcpy(h2c + 1, pbuf, buf_len); + + err = rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); + if (_SUCCESS == err) + ret = _SUCCESS; + +exit: + + return ret; +} + +static void rtl8821c_set_FwRsvdPage_cmd(PADAPTER adapter, PRSVDPAGE_LOC rsvdpageloc) +{ + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + + RTW_INFO(FUNC_ADPT_FMT ": ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n", + FUNC_ADPT_ARG(adapter), + rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll, + rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull, + rsvdpageloc->LocBTQosNull); + + RSVD_PAGE_SET_CMD_ID(h2c, CMD_ID_RSVD_PAGE); + RSVD_PAGE_SET_CLASS(h2c, CLASS_RSVD_PAGE); + RSVD_PAGE_SET_LOC_PROBE_RSP(h2c, rsvdpageloc->LocProbeRsp); + RSVD_PAGE_SET_LOC_PS_POLL(h2c, rsvdpageloc->LocPsPoll); + RSVD_PAGE_SET_LOC_NULL_DATA(h2c, rsvdpageloc->LocNullData); + RSVD_PAGE_SET_LOC_QOS_NULL(h2c, rsvdpageloc->LocQosNull); + RSVD_PAGE_SET_LOC_BT_QOS_NULL(h2c, rsvdpageloc->LocBTQosNull); + + RTW_DBG_DUMP("H2C-RsvdPage Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); + rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); +} + +static void rtl8821c_set_FwAoacRsvdPage_cmd(PADAPTER adapter, PRSVDPAGE_LOC rsvdpageloc) +{ +} + +static u8 get_ra_vht_en(u32 wirelessMode, u32 bitmap) +{ + u8 ret = 0; + + if (wirelessMode == WIRELESS_11_24AC) { + if (bitmap & 0xfff00000) /* 2SS */ + ret = 3; + else /* 1SS */ + ret = 2; + } else if (wirelessMode == WIRELESS_11_5AC) + ret = 1; + + return ret; +} + +static u8 get_ra_ldpc(struct sta_info *psta) +{ + u8 en_ldpc = 0; + + if (psta != NULL) { + if (psta->mac_id == 1) + en_ldpc = 0; + else { + if (is_supported_vht(psta->wireless_mode)) { + if (TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_CAP_TX)) + en_ldpc = 1; + else + en_ldpc = 0; + } else if (is_supported_ht(psta->wireless_mode)) { + if (TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_CAP_TX)) + en_ldpc = 1; + else + en_ldpc = 0; + } else + en_ldpc = 0; + } + } + + return en_ldpc; +} + +/* + * arg[0] = macid + * arg[1] = raid + * arg[2] = shortGIrate + * arg[3] = init_rate + */ +void rtl8821c_set_FwMacIdConfig_cmd(PADAPTER adapter, u64 mask, u8 *arg, u8 bw) +{ + HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter); + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + struct sta_info *psta = NULL; + u8 mac_id, init_rate, raid, sgi = _FALSE; + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + u8 ignore_bw = _FALSE; + + if (hal->fw_ractrl == _FALSE) { + RTW_INFO(FUNC_ADPT_FMT" fw ractrl = _FALSE\n", + FUNC_ADPT_ARG(adapter)); + return; + } + + mac_id = arg[0]; + raid = arg[1]; + sgi = arg[2] & 0x0F; + ignore_bw = arg[2] >> 4; + init_rate = arg[3]; + + if (mac_id < macid_ctl->num) + psta = macid_ctl->sta[mac_id]; + + if (!psta) { + RTW_INFO(FUNC_ADPT_FMT" macid:%u, sta is NULL\n", + FUNC_ADPT_ARG(adapter), mac_id); + return; + } + + RTW_INFO(FUNC_ADPT_FMT ": mac_id=%d raid=0x%x bw=%d mask=0x%016llx\n", + FUNC_ADPT_ARG(adapter), mac_id, raid, bw, mask); + + MACID_CFG_SET_CMD_ID(h2c, CMD_ID_MACID_CFG); + MACID_CFG_SET_CLASS(h2c, CLASS_MACID_CFG); + + /* common for h2c cmd 0x40 */ + MACID_CFG_SET_MAC_ID(h2c, mac_id); + MACID_CFG_SET_RATE_ID(h2c, raid); + + MACID_CFG_SET_SGI(h2c, (sgi) ? 1 : 0); + MACID_CFG_SET_NO_UPDATE(h2c, (ignore_bw) ? 1 : 0); + MACID_CFG_SET_BW(h2c, bw); + MACID_CFG_SET_LDPC_CAP(h2c, get_ra_ldpc(psta)); + MACID_CFG_SET_WHT_EN(h2c, get_ra_vht_en(psta->wireless_mode, mask)); + + /* DisableTXPowerTraining */ + if (hal->bDisableTXPowerTraining) { + MACID_CFG_SET_DISPT(h2c, 1); + RTW_INFO("%s: Disable PWT by driver\n", __FUNCTION__); + } else { + struct PHY_DM_STRUCT *pDM_OutSrc = &hal->odmpriv; + + if (pDM_OutSrc->is_disable_power_training) { + MACID_CFG_SET_DISPT(h2c, 1); + RTW_INFO("%s: Disable PWT by DM\n", __FUNCTION__); + } + } + + MACID_CFG_SET_RATE_MASK7_0(h2c, (u8)(mask & 0x000000ff)); + MACID_CFG_SET_RATE_MASK15_8(h2c, (u8)((mask & 0x0000ff00) >> 8)); + MACID_CFG_SET_RATE_MASK23_16(h2c, (u8)((mask & 0x00ff0000) >> 16)); + MACID_CFG_SET_RATE_MASK31_24(h2c, (u8)((mask & 0xff000000) >> 24)); + + RTW_INFO("%s, mask=0x%016llx, mac_id=0x%x, raid=0x%x, shortGIrate=%x, power training=%02x\n" + , __FUNCTION__, mask, mac_id, raid, sgi, h2c[2] & BIT(6)); + RTW_DBG_DUMP("H2C-MACIDConfig Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); + rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); + + /* update initial rate */ + if (sgi) + init_rate |= BIT(7); + + hal->INIDATA_RATE[mac_id] = init_rate; +} + +void rtl8821c_set_FwPwrMode_cmd(PADAPTER adapter, u8 psmode) +{ + int i; + u8 mode = 0, smart_ps = 0; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 h2c[RTW_HALMAC_H2C_MAX_SIZE] = {0}; + u8 PowerState = 0, awake_intvl = 1, rlbm = 0; + u8 pwrmode_data5 = 0; + struct wifidirect_info *wdinfo = &adapter->wdinfo; + + if (pwrpriv->dtim > 0) + RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, dtim=%d, HW port id=%d\n", + FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, pwrpriv->dtim, + psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); + else + RTW_INFO(FUNC_ADPT_FMT ": FW LPS mode = %d, SmartPS=%d, HW port id=%d\n", + FUNC_ADPT_ARG(adapter), psmode, pwrpriv->smart_ps, + psmode == PS_MODE_ACTIVE ? pwrpriv->current_lps_hw_port_id:get_hw_port(adapter)); + + smart_ps = pwrpriv->smart_ps; + switch (psmode) { + case PS_MODE_MIN: + mode = 1; + rlbm = 0; + awake_intvl = 2; + break; + case PS_MODE_MAX: + mode = 1; + rlbm = 1; + awake_intvl = 2; + break; + case PS_MODE_DTIM: + { + mode = 1; + rlbm = 2; + + /* For WOWLAN LPS, DTIM = (awake_intvl - 1) */ + if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16) /* DTIM = (awake_intvl - 1) */ + awake_intvl = pwrpriv->dtim + 1; + else /* DTIM = 3 */ + awake_intvl = 4; + } + break; + case PS_MODE_UAPSD_WMM: + mode = 2; + rlbm = 0; /*1*/ + /*(WMM)smart_ps: 0:PS_Poll, 1:NullData*/ + smart_ps = (pwrpriv->smart_ps) ? 1 : 0; + break; + case PS_MODE_ACTIVE: + default: + mode = 0; + break; + } + + if (!rtw_p2p_chk_state(wdinfo, P2P_STATE_NONE)) { + awake_intvl = 2; + rlbm = 1; + } + + if (adapter->registrypriv.wifi_spec == 1) { + awake_intvl = 2; + rlbm = 1; + } + + if (psmode > 0) { + if (rtw_btcoex_IsBtControlLps(adapter) == _TRUE) { + PowerState = rtw_btcoex_RpwmVal(adapter); + pwrmode_data5 = rtw_btcoex_LpsVal(adapter); + + if ((rlbm == 2) && (pwrmode_data5 & BIT(4))) { + /* + * Keep awake interval to 1 to prevent from + * decreasing coex performance + */ + awake_intvl = 2; + rlbm = 2; + } + } else + { + PowerState = 0x00; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + pwrmode_data5 = 0x40; + } + } else { + PowerState = 0x0C; /* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + pwrmode_data5 = 0x40; + } + + SET_PWR_MODE_SET_CMD_ID(h2c, CMD_ID_SET_PWR_MODE); + SET_PWR_MODE_SET_CLASS(h2c, CLASS_SET_PWR_MODE); + SET_PWR_MODE_SET_MODE(h2c, mode); + SET_PWR_MODE_SET_SMART_PS(h2c, smart_ps); + SET_PWR_MODE_SET_RLBM(h2c, rlbm); + SET_PWR_MODE_SET_AWAKE_INTERVAL(h2c, awake_intvl); + SET_PWR_MODE_SET_B_ALL_QUEUE_UAPSD(h2c, adapter->registrypriv.uapsd_enable); + SET_PWR_MODE_SET_PWR_STATE(h2c, PowerState); + if (psmode == PS_MODE_ACTIVE) { + /* Leave LPS, set the same HW port ID */ + SET_PWR_MODE_SET_PORT_ID(h2c, pwrpriv->current_lps_hw_port_id); + } else { + /* Enter LPS, record HW port ID */ + SET_PWR_MODE_SET_PORT_ID(h2c, get_hw_port(adapter)); + pwrpriv->current_lps_hw_port_id = get_hw_port(adapter); + } + + if (pwrmode_data5) + h2c[6] = pwrmode_data5; + else { + /* pwrmode_data5 section*/ + SET_PWR_MODE_SET_LOW_POWER_RX_BCN(h2c, 0);/*bit-16*/ + SET_PWR_MODE_SET_ANT_AUTO_SWITCH(h2c, 0);/*bit-17*/ + SET_PWR_MODE_SET_PS_ALLOW_BT_HIGH_PRIORITY(h2c, 0);/*bit-18*/ + SET_PWR_MODE_SET_PROTECT_BCN(h2c, 0);/*bit-19*/ + SET_PWR_MODE_SET_SILENCE_PERIOD(h2c, 0);/*bit-20*/ + SET_PWR_MODE_SET_FAST_BT_CONNECT(h2c, 0);/*bit-21*/ + SET_PWR_MODE_SET_TWO_ANTENNA_EN(h2c, 0);/*bit-22*/ + } + /* pwrmode_data6 section*/ + SET_PWR_MODE_SET_ADOPT_USER_SETTING(h2c, 0);/*bit-24*/ + SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT(h2c, 0);/*bit-25:3*/ + SET_PWR_MODE_SET_DRV_BCN_EARLY_SHIFT2(h2c, 0);/*bit-28:4*/ + + RTW_INFO("%s=> psmode:%02x, smart_ps:%02x, PowerState:%02x\n", __func__, psmode, smart_ps, PowerState); + + rtw_btcoex_RecordPwrMode(adapter, h2c + 1, RTW_HALMAC_H2C_MAX_SIZE - 1); + + RTW_DBG_DUMP("H2C-PwrMode Parm:", h2c, RTW_HALMAC_H2C_MAX_SIZE); + rtw_halmac_send_h2c(adapter_to_dvobj(adapter), h2c); +} + +static void ConstructBeacon(PADAPTER adapter, u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 rate_len, pktlen; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + WLAN_BSSID_EX *cur_network = &pmlmeinfo->network; + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + set_frame_sub_type(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* timestamp will be inserted by hardware */ + pframe += 8; + pktlen += 8; + + /* beacon interval: 2 bytes */ + _rtw_memcpy(pframe, (u8 *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + /* capability info: 2 bytes */ + _rtw_memcpy(pframe, (u8 *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); + _rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen); + + goto _ConstructBeacon; + } + + /* below for ad-hoc mode */ + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); + + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + u32 ATIMWindow; + /* IBSS Parameter Set... */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); + } + + /* todo: ERP IE */ + + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); + + /* todo:HT for adhoc */ + +_ConstructBeacon: + + if ((pktlen + TXDESC_SIZE) > 512) { + RTW_INFO("beacon frame too large\n"); + return; + } + + *pLength = pktlen; +} + +static void ConstructBtNullFunctionData( + PADAPTER adapter, + u8 *pframe, + u32 *pLength, + u8 *StaAddr, + u8 bQoS, + u8 AC, + u8 bEosp, + u8 bForcePowerSave) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u8 bssid[ETH_ALEN]; + + RTW_INFO("+" FUNC_ADPT_FMT ": qos=%d eosp=%d ps=%d\n", + FUNC_ADPT_ARG(adapter), bQoS, bEosp, bForcePowerSave); + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + if (NULL == StaAddr) { + _rtw_memcpy(bssid, adapter_mac_addr(adapter), ETH_ALEN); + StaAddr = bssid; + } + + fctrl = &pwlanhdr->frame_ctl; + *fctrl = 0; + if (bForcePowerSave) + SetPwrMgt(fctrl); + + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(adapter), ETH_ALEN); + + set_duration(pwlanhdr, 0); + SetSeqNum(pwlanhdr, 0); + + if (bQoS == _TRUE) { + struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; + + set_frame_sub_type(pframe, WIFI_QOS_DATA_NULL); + + pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; + SetPriority(&pwlanqoshdr->qc, AC); + SetEOSP(&pwlanqoshdr->qc, bEosp); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + } else { + set_frame_sub_type(pframe, WIFI_DATA_NULL); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + } + + *pLength = pktlen; +} + +static void SetFwRsvdPagePkt_BTCoex(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + struct xmit_frame *pcmdframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u32 BeaconLength = 0; + u32 BTQosNullLength = 0; + u8 *ReservedPagePacket; + u8 TxDescLen, TxDescOffset; + u8 TotalPageNum = 0, CurtPktPageNum = 0, RsvdPageNum = 0; + u16 BufIndex, PageSize; + u32 TotalPacketLen, MaxRsvdPageBufSize = 0; + RSVDPAGE_LOC RsvdPageLoc; + + hal = GET_HAL_DATA(adapter); + pxmitpriv = &adapter->xmitpriv; + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + TxDescLen = TXDESC_SIZE; + TxDescOffset = TXDESC_OFFSET; + PageSize = HALMAC_TX_PAGE_SIZE_8821C; + + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); + MaxRsvdPageBufSize = RsvdPageNum * PageSize; + + pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + if (pcmdframe == NULL) { + RTW_INFO("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); + return; + } + + ReservedPagePacket = pcmdframe->buf_addr; + _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); + + /* beacon */ + BufIndex = TxDescOffset; + ConstructBeacon(adapter, &ReservedPagePacket[BufIndex], &BeaconLength); + + /* + * When we count the first page size, we need to reserve description size for the RSVD + * packet, it will be filled in front of the packet in TXPKTBUF. + */ + CurtPktPageNum = (u8)PageNum_128(TxDescLen + BeaconLength); + /* + * If we don't add 1 more page, the WOWLAN function has a problem. + * Maybe it's a bug of firmware? + */ + if (CurtPktPageNum == 1) + CurtPktPageNum += 1; + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum * PageSize); + + /* Jump to lastest page */ + if (BufIndex < (MaxRsvdPageBufSize - PageSize)) { + BufIndex = TxDescOffset + (MaxRsvdPageBufSize - PageSize); + TotalPageNum = RsvdPageNum - 1; + } + + /* BT Qos null data */ + RsvdPageLoc.LocBTQosNull = TotalPageNum; + ConstructBtNullFunctionData( + adapter, + &ReservedPagePacket[BufIndex], + &BTQosNullLength, + NULL, + _TRUE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, &ReservedPagePacket[BufIndex - TxDescLen], BTQosNullLength, _FALSE, _TRUE, _FALSE); + + CurtPktPageNum = (u8)PageNum_128(TxDescLen + BTQosNullLength); + + TotalPageNum += CurtPktPageNum; + + TotalPacketLen = BufIndex + BTQosNullLength; + if (TotalPacketLen > MaxRsvdPageBufSize) { + RTW_INFO(FUNC_ADPT_FMT ": ERROR: The rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", + FUNC_ADPT_ARG(adapter), TotalPacketLen, MaxRsvdPageBufSize); + goto error; + } + + /* update attribute */ + pattrib = &pcmdframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + pattrib->qsel = QSLT_BEACON; + pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset; + dump_mgntframe(adapter, pcmdframe); + + rtl8821c_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc); + rtl8821c_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc); + + return; + +error: + rtw_free_xmitframe(pxmitpriv, pcmdframe); +} + +void rtl8821c_download_BTCoex_AP_mode_rsvd_page(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u8 bRecover = _FALSE; + u8 bcn_valid = _FALSE; + u8 DLBcnCount = 0; + u32 poll = 0; + u8 val8; + + RTW_INFO("+" FUNC_ADPT_FMT ": hw_port=%d fw_state=0x%08X\n", + FUNC_ADPT_ARG(adapter), get_hw_port(adapter), get_fwstate(&adapter->mlmepriv)); + + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _FALSE) { + RTW_INFO(FUNC_ADPT_FMT ": [WARNING] not in AP mode!!\n", + FUNC_ADPT_ARG(adapter)); + } + + hal = GET_HAL_DATA(adapter); + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ + rtw_write16(adapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid)); + + /* set REG_CR bit 8 */ + val8 = rtw_read8(adapter, REG_CR + 1); + val8 |= BIT(0); /* ENSWBCN */ + rtw_write8(adapter, REG_CR + 1, val8); + + /* + * Disable Hw protection for a time which revserd for Hw sending beacon. + * Fix download reserved page packet fail that access collision with the protection time. + */ + val8 = rtw_read8(adapter, REG_BCN_CTRL); + val8 &= ~EN_BCN_FUNCTION; + val8 |= DIS_TSF_UDT; + rtw_write8(adapter, REG_BCN_CTRL, val8); + + /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ + if (hal->RegFwHwTxQCtrl & BIT(6)) + bRecover = _TRUE; + + /* To tell Hw the packet is not a real beacon frame. */ + hal->RegFwHwTxQCtrl &= ~BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL + 2, hal->RegFwHwTxQCtrl); + + /* Clear beacon valid check bit. */ + rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL); + + DLBcnCount = 0; + poll = 0; + do { + SetFwRsvdPagePkt_BTCoex(adapter); + DLBcnCount++; + do { + rtw_yield_os(); + + /* check rsvd page download OK. */ + rtw_hal_get_hwreg(adapter, HW_VAR_BCN_VALID, &bcn_valid); + poll++; + } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(adapter)); + } while (!bcn_valid && (DLBcnCount <= 100) && !RTW_CANNOT_RUN(adapter)); + + if (_TRUE == bcn_valid) { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + + pwrctl->fw_psmode_iface_id = adapter->iface_id; + RTW_INFO(ADPT_FMT": DL RSVD page success! DLBcnCount:%d, poll:%d\n", + ADPT_ARG(adapter), DLBcnCount, poll); + } else { + RTW_INFO(ADPT_FMT": DL RSVD page fail! DLBcnCount:%d, poll:%d\n", + ADPT_ARG(adapter), DLBcnCount, poll); + RTW_INFO(ADPT_FMT": DL RSVD page fail! bSurpriseRemoved=%s\n", + ADPT_ARG(adapter), rtw_is_surprise_removed(adapter) ? "True" : "False"); + RTW_INFO(ADPT_FMT": DL RSVD page fail! bDriverStopped=%s\n", + ADPT_ARG(adapter), rtw_is_drv_stopped(adapter) ? "True" : "False"); + } + + val8 = rtw_read8(adapter, REG_BCN_CTRL); + val8 |= EN_BCN_FUNCTION; + val8 &= ~DIS_TSF_UDT; + rtw_write8(adapter, REG_BCN_CTRL, val8); + + /* + * To make sure that if there exists an adapter which would like to send beacon. + * If exists, the origianl value of 0x422[6] will be 1, we should check this to + * prevent from setting 0x422[6] to 0 after download reserved page, or it will cause + * the beacon cannot be sent by HW. + */ + if (bRecover) { + hal->RegFwHwTxQCtrl |= BIT(6); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL + 2, hal->RegFwHwTxQCtrl); + } + + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ +} + + +void rtl8821c_fw_update_beacon_cmd(PADAPTER adapter) +{ +} + +/* +* Below functions are for C2H +*/ +static void c2h_ccx_rpt(PADAPTER adapter, u8 *pdata) +{ +#define C2H_CCX_RPT_GET_TX_STATE(__pC2H) LE_BITS_TO_4BYTE(__pC2H + 0X04, 30, 2) + u8 tx_state = _FALSE; + + tx_state = C2H_CCX_RPT_GET_TX_STATE(pdata); + + /* 0 means success, 1 means retry drop */ + if (tx_state == 0) + rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS); + else + rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); +} + +/** +* pbuf = RXDESC + c2h packet +* length = RXDESC_SIZE + c2h packet size +* c2h format => ID(1B) | SN(1B) | Payload +*/ +void c2h_handler_rtl8821c(PADAPTER adapter, u8 *pbuf, u16 length) +{ + u8 c2h_id, c2h_sn; + int c2h_len; + u8 *pc2h_hdr; + u8 *pc2h_data; + u8 c2h_sub_cmd_id = 0; + if (pbuf == NULL) + return; + + if (length < HALMAC_RX_DESC_SIZE_8821C) { + RTW_INFO("%s: [ERROR] c2h length(%d) is smaller than RXDESC_SIZE(%d)!!\n", + __func__, length, HALMAC_RX_DESC_SIZE_8821C); + return; + } + + pc2h_hdr = pbuf + HALMAC_RX_DESC_SIZE_8821C; + pc2h_data = pbuf + HALMAC_RX_DESC_SIZE_8821C + 2; /* cmd ID not 0xFF original C2H have 2 bytes C2H header */ + c2h_id = C2H_GET_CMD_ID(pc2h_hdr); + c2h_sn = C2H_GET_SEQ(pc2h_hdr); + c2h_len = length - HALMAC_RX_DESC_SIZE_8821C - 2; + + if ((c2h_len < 0) || (c2h_len > C2H_DBG_CONTENT_MAX_LENGTH)) { + RTW_ERR("%s: [ERROR] C2H_ID(%02x) C2H_SN(%d) warn c2h_len :%d (length:%d)\n", __func__, c2h_id, c2h_sn, c2h_len, length); + rtw_warn_on(1); + } +#ifdef DBG_C2H_CONTENT + RTW_INFO("%s "ADPT_FMT" C2H, ID=%d seq=%d len=%d\n", __func__, ADPT_ARG(adapter), c2h_id, c2h_sn, length); +#endif + switch (c2h_id) { + case CMD_ID_C2H_SND_TXBF: + /*C2HTxBeamformingHandler_8821C(adapter, pc2h_data, c2h_len);*/ + break; + + /* FW offload C2H is 0xFF cmd according to halmac function - halmac_parse_c2h_packet */ + case 0xFF: + /* Get C2H sub cmd ID */ + c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pc2h_hdr); + if (c2h_sub_cmd_id == C2H_SUB_CMD_ID_CCX_RPT) + c2h_ccx_rpt(adapter, pbuf + HALMAC_RX_DESC_SIZE_8821C + 4); /* cmd ID 0xFF new C2H have 4 bytes C2H header */ + else + /* indicate rx desc + c2h pkt to halmac */ + if (rtw_halmac_c2h_handle(adapter_to_dvobj(adapter), pbuf, length == (-1))) + RTW_ERR("%s "ADPT_FMT" C2H, ID=%d, SubID=%d seq=%d len=%d ,HALMAC not to handle\n", + __func__, ADPT_ARG(adapter), c2h_id, c2h_sub_cmd_id, c2h_sn, length); + break; + /* others for c2h common code */ + default: + /* shift 2 byte to remove cmd id & seq */ + c2h_handler(adapter, c2h_id, c2h_sn, c2h_len, pc2h_data); + break; + } +} + +static inline u8 is_c2h_id_handle_directly(u8 c2h_id, u8 c2h_sub_cmd_id) +{ + switch (c2h_id) { + case CMD_ID_C2H_CCX_RPT: + case C2H_IQK_FINISH: + + case C2H_BT_MP_INFO: + + return _TRUE; + case 0xFF: + switch (c2h_sub_cmd_id) { + case C2H_SUB_CMD_ID_CCX_RPT: + return _TRUE; + default: + return _FALSE; + } + default: + return _FALSE; + } + +} + +/* +* pbuf = RXDESC + c2h packet +* length = RXDESC_SIZE + c2h packet size +*/ +void c2h_pre_handler_rtl8821c(_adapter *adapter, u8 *pbuf, s32 length) +{ + u8 c2h_id; + u8 c2h_sub_cmd_id = 0; + + if ((length <= 0) || (!pbuf)) + return; + + c2h_id = C2H_GET_CMD_ID(pbuf + HALMAC_RX_DESC_SIZE_8821C); + + /* Get C2H sub cmd ID */ + if (c2h_id == 0xFF) + c2h_sub_cmd_id = (u8)C2H_HDR_GET_C2H_SUB_CMD_ID(pbuf + HALMAC_RX_DESC_SIZE_8821C); + + if (is_c2h_id_handle_directly(c2h_id, c2h_sub_cmd_id)) + c2h_handler_rtl8821c(adapter, pbuf, length); + else + rtw_c2h_packet_wk_cmd(adapter, pbuf, length); +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c new file mode 100644 index 000000000000..3fa362f9c11d --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_dm.c @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <rtl8821c_hal.h> + +static void dm_CheckStatistics(PADAPTER adapter) +{ +} + +/* + * ============================================================ + * functions + * ============================================================ + */ +static void init_phydm_cominfo(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + struct PHY_DM_STRUCT *pDM_Odm; + u32 SupportAbility = 0; + u8 cut_ver = ODM_CUT_A, fab_ver = ODM_TSMC; + + + hal = GET_HAL_DATA(adapter); + pDM_Odm = &hal->odmpriv; + + Init_ODM_ComInfo(adapter); + + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, hal->PackageType); + + if (IS_CHIP_VENDOR_TSMC(hal->version_id)) + fab_ver = ODM_TSMC; + else if (IS_CHIP_VENDOR_UMC(hal->version_id)) + fab_ver = ODM_UMC; + else if (IS_CHIP_VENDOR_SMIC(hal->version_id)) + fab_ver = ODM_UMC + 1; + else + RTW_INFO("%s: unknown fab_ver=%d !!\n", + __FUNCTION__, GET_CVID_MANUFACTUER(hal->version_id)); + + if (IS_A_CUT(hal->version_id)) + cut_ver = ODM_CUT_A; + else if (IS_B_CUT(hal->version_id)) + cut_ver = ODM_CUT_B; + else if (IS_C_CUT(hal->version_id)) + cut_ver = ODM_CUT_C; + else if (IS_D_CUT(hal->version_id)) + cut_ver = ODM_CUT_D; + else if (IS_E_CUT(hal->version_id)) + cut_ver = ODM_CUT_E; + else if (IS_F_CUT(hal->version_id)) + cut_ver = ODM_CUT_F; + else if (IS_I_CUT(hal->version_id)) + cut_ver = ODM_CUT_I; + else if (IS_J_CUT(hal->version_id)) + cut_ver = ODM_CUT_J; + else if (IS_K_CUT(hal->version_id)) + cut_ver = ODM_CUT_K; + else + RTW_INFO("%s: unknown cut_ver=%d !!\n", + __FUNCTION__, GET_CVID_CUT_VERSION(hal->version_id)); + + RTW_INFO("%s: fab_ver=%d cut_ver=%d\n", __FUNCTION__, fab_ver, cut_ver); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver); + odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver); + + SupportAbility = ODM_RF_CALIBRATION | ODM_RF_TX_PWR_TRACK; + + odm_cmn_info_update(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility); +} + +void rtl8821c_phy_init_dm_priv(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *podmpriv = &hal->odmpriv; + + init_phydm_cominfo(adapter); + + /*PHYDM API - thermal trim*/ + phydm_get_thermal_trim_offset(podmpriv); + /*PHYDM API - power trim*/ + phydm_get_power_trim_offset(podmpriv); +} + +void rtl8821c_phy_init_haldm(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &hal->odmpriv; + + hal->DM_Type = dm_type_by_driver; + odm_dm_init(pDM_Odm); +} + +void rtl8821c_phy_haldm_watchdog(PADAPTER Adapter) +{ + BOOLEAN bFwCurrentInPSMode = _FALSE; + BOOLEAN bFwPSAwake = _TRUE; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + struct PHY_DM_STRUCT *pDM_Odm = &(pHalData->odmpriv); + + if (!rtw_is_hw_init_completed(Adapter)) + goto skip_dm; + + bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode; + rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake)); + + /* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. + modifed by thomas. 2011.06.11.*/ + if (Adapter->wdinfo.p2p_ps_mode) + bFwPSAwake = _FALSE; + + if ((rtw_is_hw_init_completed(Adapter)) + && ((!bFwCurrentInPSMode) && bFwPSAwake)) { + /* Calculate Tx/Rx statistics. */ + dm_CheckStatistics(Adapter); + + /* Dynamically switch RTS/CTS protection.*/ + /*dm_CheckProtection(Adapter);*/ + } + + + if (rtw_is_hw_init_completed(Adapter)) { + u8 bLinked = _FALSE; + u8 bsta_state = _FALSE; + u8 bBtDisabled = _TRUE; + + if (rtw_mi_check_status(Adapter, MI_STA_LINKED) || rtw_mi_check_status(Adapter, MI_AP_ASSOC)) { + bLinked = _TRUE; + if (rtw_mi_check_status(Adapter, MI_STA_LINKED)) + bsta_state = _TRUE; + } + + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_LINK, bLinked); + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_STATION_STATE, bsta_state); + + bBtDisabled = rtw_btcoex_IsBtDisabled(Adapter); + odm_cmn_info_update(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE) ? _FALSE : _TRUE)); + + odm_dm_watchdog(&pHalData->odmpriv); + + } + +skip_dm: + + return; +} + +void rtl8821c_phy_haldm_in_lps(PADAPTER adapter) +{ +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c new file mode 100644 index 000000000000..fb4a6b62f7d0 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_halinit.c @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821C_HALINIT_C_ + +#include <drv_types.h> /* PADAPTER, basic_types.h and etc. */ +#include <hal_data.h> /* GET_HAL_SPEC(), HAL_DATA_TYPE */ +#include "../hal_halmac.h" /* HALMAC API */ +#include "rtl8821c.h" + +void init_hal_spec_rtl8821c(PADAPTER adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + + rtw_halmac_fill_hal_spec(adapter_to_dvobj(adapter), hal_spec); + + hal_spec->ic_name = "rtl8821c"; + hal_spec->macid_num = 128; + /* hal_spec->sec_cam_ent_num follow halmac setting */ + hal_spec->sec_cap = SEC_CAP_CHK_BMC; + + hal_spec->rfpath_num_2g = 2; + hal_spec->rfpath_num_5g = 1; + hal_spec->max_tx_cnt = 1; + hal_spec->tx_nss_num = 1; + hal_spec->rx_nss_num = 1; + hal_spec->band_cap = BAND_CAP_2G | BAND_CAP_5G; + hal_spec->bw_cap = BW_CAP_20M | BW_CAP_40M | BW_CAP_80M; + hal_spec->port_num = 5; + hal_spec->hci_type = 0; + hal_spec->proto_cap = PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC; + + hal_spec->wl_func = 0 + | WL_FUNC_P2P + | WL_FUNC_MIRACAST + ; +} + +u32 rtl8821c_power_on(PADAPTER adapter) +{ + struct dvobj_priv *d; + PHAL_DATA_TYPE hal; + u8 bMacPwrCtrlOn; + int err = 0; + u8 ret = _SUCCESS; + + d = adapter_to_dvobj(adapter); + + bMacPwrCtrlOn = _FALSE; + rtw_hal_get_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if (bMacPwrCtrlOn == _TRUE) + goto out; + + err = rtw_halmac_poweron(d); + + #ifdef CONFIG_POWER_STATE_UNEXPECTED_HDL + if ((-2) == err) { + RTW_ERR("%s:Power ON Fail, Try to power on again !!\n", __FUNCTION__); + rtw_halmac_poweroff(d); + rtw_msleep_os(2); + err = rtw_halmac_poweron(d); + } + #endif + + if (err) { + RTW_ERR("%s: Power ON Fail!!\n", __FUNCTION__); + rtw_warn_on(1); + ret = _FAIL; + goto out; + } + + bMacPwrCtrlOn = _TRUE; + rtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + +out: + return ret; +} + +void rtl8821c_power_off(PADAPTER adapter) +{ + struct dvobj_priv *d; + u8 bMacPwrCtrlOn; + int err = 0; + + d = adapter_to_dvobj(adapter); + + bMacPwrCtrlOn = _FALSE; + rtw_hal_get_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if (bMacPwrCtrlOn == _FALSE) + goto out; + + err = rtw_halmac_poweroff(d); + if (err) { + RTW_ERR("%s: Power OFF Fail!!\n", __FUNCTION__); + rtw_warn_on(1); + goto out; + } + + bMacPwrCtrlOn = _FALSE; + rtw_hal_set_hwreg(adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + + adapter->bFWReady = _FALSE; + +out: + return; +} + +u8 rtl8821c_hal_init_main(PADAPTER adapter) +{ + struct dvobj_priv *d = adapter_to_dvobj(adapter); + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + int err; + s32 ret; + + adapter->bFWReady = _FALSE; + hal->fw_ractrl = _FALSE; + + err = rtw_halmac_init_hal_fw(d, array_mp_8821c_fw_nic, array_length_mp_8821c_fw_nic); + + if (!err) { + adapter->bFWReady = _TRUE; + hal->fw_ractrl = _TRUE; + } + RTW_INFO("FW Version:%d SubVersion:%d\n", hal->firmware_version, hal->firmware_sub_version); + if (err) { + RTW_INFO("%s: fail\n", __FUNCTION__); + return _FALSE; + } + + RTW_INFO("%s: successful\n", __FUNCTION__); + + return _TRUE; +} + +void rtl8821c_hal_init_channel_setting(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + + /* initial channel setting */ + hal_data->current_channel = 0; + hal_data->current_channel_bw = CHANNEL_WIDTH_MAX; + hal_data->current_band_type = BAND_MAX; +} + +void rtl8821c_hal_init_misc(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + u8 drv_info_sz = 0; + + /* + * Sync driver status and hardware setting + */ + + /* initial security setting */ + invalidate_cam_all(adapter); + + /* enable to rx ps-poll ,disable Control frame filter*/ + rtw_write16(adapter, REG_RXFLTMAP1_8821C, 0x0400); + /* Accept all data frames */ + rtw_write16(adapter, REG_RXFLTMAP_8821C, 0xFFFF); + + /* Accept all management frames */ + rtw_write16(adapter, REG_RXFLTMAP0_8821C, 0xFFFF); + + /*RCR setting - Sync driver status with hardware setting */ + rtl8821c_rcr_get(adapter, NULL); + + rtl8821c_rcr_clear(adapter, BIT_AICV_8821C | BIT_ACRC32_8821C | BIT_APP_FCS_8821C | BIT_APWRMGT_8821C); + + rtw_halmac_get_drv_info_sz(adapter_to_dvobj(adapter), &drv_info_sz); + if (drv_info_sz) + rtl8821c_rcr_add(adapter, BIT_APP_PHYSTS_8821C); + + rtl8821c_rcr_add(adapter, BIT_APP_FCS_8821C); + +#ifdef CONFIG_RX_PACKET_APPEND_ICV_ERROR + rtl8821c_rcr_add(adapter, BIT_AICV_8821C); +#endif + + rtl8821c_set_mgnt_xmit_ack(adapter); + + /*Disable BAR, suggested by Scott */ + rtw_write32(adapter, REG_BAR_MODE_CTRL_8821C, 0x0201ffff); + /*Disable secondary CCA 20M,40M?*/ + rtw_write8(adapter, REG_MISC_CTRL_8821C, 0x03); + + /*Enable MAC security engine*/ + rtw_write16(adapter, REG_CR, (rtw_read16(adapter, REG_CR) | BIT_MAC_SEC_EN)); + + rtl8821c_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8821C | BIT_CHK_TSF_CBSSID_8821C); + + /*for 1212 module - 5G RX issue*/ + if (hal_data->rfe_type == 2) + rtw_write8(adapter, REG_PAD_CTRL1 + 3, 0x36); + + + rtw_write16(adapter, REG_PKT_LIFE_TIME_8821C, 0x0400); /* unit: 256us. 256ms */ + rtw_write16(adapter, REG_PKT_LIFE_TIME_8821C+2, 0x0400); /* unit: 256us. 256ms */ + + rtl8821c_pretx_cd_config(adapter); + +} + +u32 rtl8821c_hal_init(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + + hal = GET_HAL_DATA(adapter); + + if (_FALSE == rtl8821c_hal_init_main(adapter)) + return _FAIL; + + rtl8821c_hal_init_misc(adapter); + + rtl8821c_phy_init_haldm(adapter); + + /* Init BT hw config. */ + if (_TRUE == hal->EEPROMBluetoothCoexist) + rtw_btcoex_HAL_Initialize(adapter, _FALSE); + else + rtw_btcoex_wifionly_hw_config(adapter); + + rtl8821c_hal_init_channel_setting(adapter); + + return _SUCCESS; +} + +u32 rtl8821c_hal_deinit(PADAPTER adapter) +{ + struct dvobj_priv *d; + PHAL_DATA_TYPE hal; + int err; + + d = adapter_to_dvobj(adapter); + hal = GET_HAL_DATA(adapter); + + adapter->bFWReady = _FALSE; + hal->fw_ractrl = _FALSE; + + err = rtw_halmac_deinit_hal(d); + if (err) + return _FAIL; + + return _SUCCESS; +} + +void rtl8821c_init_default_value(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + u8 i; + + hal = GET_HAL_DATA(adapter); + + adapter->registrypriv.wireless_mode = WIRELESS_MODE_24G | WIRELESS_MODE_5G; + + /* init default value */ + hal->fw_ractrl = _FALSE; + + if (!adapter_to_pwrctl(adapter)->bkeepfwalive) + hal->LastHMEBoxNum = 0; + + /* init phydm default value */ + hal->bIQKInitialized = _FALSE; + hal->odmpriv.rf_calibrate_info.tm_trigger = 0; /* for IQK */ + hal->odmpriv.rf_calibrate_info.thermal_value_hp_index = 0; + for (i = 0; i < HP_THERMAL_NUM; i++) + hal->odmpriv.rf_calibrate_info.thermal_value_hp[i] = 0; + + /* init Efuse variables */ + hal->EfuseUsedBytes = 0; + hal->EfuseUsedPercentage = 0; +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c new file mode 100644 index 000000000000..a15a40bc3fb2 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_mac.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821C_MAC_C_ + +#include <drv_types.h> /* PADAPTER, basic_types.h and etc. */ +#include <hal_data.h> /* HAL_DATA_TYPE */ +#include "../hal_halmac.h" /* Register Definition and etc. */ + +inline u8 rtl8821c_rcr_config(PADAPTER p, u32 rcr) +{ + int err; + + err = rtw_write32(p, REG_RCR_8821C, rcr); + if (_FAIL == err) + return _FALSE; + + GET_HAL_DATA(p)->ReceiveConfig = rcr; + return _TRUE; +} + +inline u8 rtl8821c_rcr_get(PADAPTER p, u32 *rcr) +{ + u32 v32; + + v32 = rtw_read32(p, REG_RCR_8821C); + if (rcr) + *rcr = v32; + GET_HAL_DATA(p)->ReceiveConfig = v32; + return _TRUE; +} + +inline u8 rtl8821c_rcr_check(PADAPTER p, u32 check_bit) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + + hal = GET_HAL_DATA(p); + rcr = hal->ReceiveConfig; + if ((rcr & check_bit) == check_bit) + return _TRUE; + + return _FALSE; +} + +inline u8 rtl8821c_rcr_add(PADAPTER p, u32 add) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + u8 ret = _TRUE; + + hal = GET_HAL_DATA(p); + + rcr = hal->ReceiveConfig; + rcr |= add; + if (rcr != hal->ReceiveConfig) + ret = rtl8821c_rcr_config(p, rcr); + + return ret; +} + +inline u8 rtl8821c_rcr_clear(PADAPTER p, u32 clear) +{ + PHAL_DATA_TYPE hal; + u32 rcr; + u8 ret = _TRUE; + + hal = GET_HAL_DATA(p); + + rcr = hal->ReceiveConfig; + rcr &= ~clear; + if (rcr != hal->ReceiveConfig) + ret = rtl8821c_rcr_config(p, rcr); + + return ret; +} + +inline u8 rtl8821c_set_mgnt_xmit_ack(_adapter *adapter) +{ + int err; + + /*ack for xmit mgmt frames.*/ + err = rtw_write32(adapter, REG_FWHW_TXQ_CTRL_8821C, rtw_read32(adapter, REG_FWHW_TXQ_CTRL_8821C) | BIT(12)); + if (err == _FAIL) + return _FAIL; + + return _SUCCESS; +} + +u8 rtl8821c_rx_tsf_addr_filter_config(_adapter *adapter, u8 config) +{ + u8 v8; + int err; + + v8 = GET_HAL_DATA(adapter)->rx_tsf_addr_filter_config; + + if (v8 != config) { + + err = rtw_write8(adapter, REG_NAN_RX_TSF_FILTER_8821C, config); + if (_FAIL == err) + return _FALSE; + } + + GET_HAL_DATA(adapter)->rx_tsf_addr_filter_config = config; + return _TRUE; +} + +/* + * Return: + * _SUCCESS Download Firmware OK. + * _FAIL Download Firmware FAIL! + */ +s32 rtl8821c_fw_dl(PADAPTER adapter) +{ + struct dvobj_priv *d = adapter_to_dvobj(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int err; + + err = rtw_halmac_dlfw(d, array_mp_8821c_fw_nic, array_length_mp_8821c_fw_nic); + + if (!err) { + adapter->bFWReady = _TRUE; + hal_data->fw_ractrl = _TRUE; + RTW_INFO("%s Download Firmware from %s success\n", __func__, "array"); + RTW_INFO("%s FW Version:%d SubVersion:%d\n", "NIC", hal_data->firmware_version, hal_data->firmware_sub_version); + + return _SUCCESS; + } else { + RTW_ERR("%s Download Firmware from %s failed\n", __func__, "array"); + return _FAIL; + } +} +/* + * Return: + * _SUCCESS Download Firmware MEM OK. + * _FAIL Download Firmware MEM FAIL! + */ + +#include "rtl8821c.h" +#define AMPDU_NUMBER 0x3F3F /*MAX AMPDU Number = 63*/ +#define REG_PRECNT_CTRL_8821C 0x04E5 +#define BIT_EN_PRECNT_8821C BIT(11) +#define PRECNT_TH 0x1E4 /*6.05us*/ + +/* pre-tx count-down mechanism */ +void rtl8821c_pretx_cd_config(_adapter *adapter) +{ + u8 burst_mode; + u16 pre_cnt = PRECNT_TH | BIT_EN_PRECNT_8821C; + + /*Enable AMPDU PRE-TX, Reg0x4BC[6] = 1*/ + burst_mode = rtw_read8(adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8821C); + if (!(burst_mode & BIT_PRE_TX_CMD_8821C)) { + burst_mode |= BIT_PRE_TX_CMD_8821C; + rtw_write8(adapter, REG_SW_AMPDU_BURST_MODE_CTRL_8821C, burst_mode); + } + /*MAX AMPDU Number = 63, Reg0x4C8[21:16] = 0x3F*/ + rtw_write16(adapter, REG_PROT_MODE_CTRL_8821C + 2, AMPDU_NUMBER); + + /*Reg0x4E5[11] = 1, Reg0x4E5[10:0] = 0x1E4 */ + rtw_write8(adapter, REG_PRECNT_CTRL_8821C, (u8)(pre_cnt & 0xFF)); + rtw_write8(adapter, (REG_PRECNT_CTRL_8821C + 1), (u8)(pre_cnt >> 8)); + +} + + diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c new file mode 100644 index 000000000000..fbf2afa5559f --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_ops.c @@ -0,0 +1,2777 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821C_OPS_C_ + +#include <drv_types.h> /* basic_types.h, rtw_io.h and etc. */ +#include <rtw_xmit.h> /* struct xmit_priv */ + #include <rtw_sreset.h> +#include <hal_data.h> /* PHAL_DATA_TYPE, GET_HAL_DATA() */ +#include <hal_com.h> /* rtw_hal_config_rftype(), dump_chip_info() and etc. */ +#include "../hal_halmac.h" /* GET_RX_DESC_XXX_8821C() */ +#include "rtl8821c.h" + #include "rtl8821ce_hal.h" +#include "rtl8821c_dm.h" + +static void read_chip_version(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + u32 value32; + + hal = GET_HAL_DATA(adapter); + + value32 = rtw_read32(adapter, REG_SYS_CFG1_8821C); + hal->version_id.ICType = CHIP_8821C; + hal->version_id.ChipType = ((value32 & BIT_RTL_ID_8821C) ? TEST_CHIP : NORMAL_CHIP); + hal->version_id.CUTVersion = BIT_GET_CHIP_VER_8821C(value32); + hal->version_id.VendorType = BIT_GET_VENDOR_ID_8821C(value32); + hal->version_id.VendorType >>= 2; + switch (hal->version_id.VendorType) { + case 0: + hal->version_id.VendorType = CHIP_VENDOR_TSMC; + break; + case 1: + hal->version_id.VendorType = CHIP_VENDOR_SMIC; + break; + case 2: + hal->version_id.VendorType = CHIP_VENDOR_UMC; + break; + } + hal->version_id.RFType = ((value32 & BIT_RF_TYPE_ID_8821C) ? RF_TYPE_2T2R : RF_TYPE_1T1R); + hal->RegulatorMode = ((value32 & BIT_SPSLDO_SEL_8821C) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); + + value32 = rtw_read32(adapter, REG_SYS_STATUS1_8821C); + hal->version_id.ROMVer = BIT_GET_RF_RL_ID_8821C(value32); + + /* For multi-function consideration. */ + hal->MultiFunc = RT_MULTI_FUNC_NONE; + value32 = rtw_read32(adapter, REG_WL_BT_PWR_CTRL_8821C); + hal->MultiFunc |= ((value32 & BIT_WL_FUNC_EN_8821C) ? RT_MULTI_FUNC_WIFI : 0); + hal->MultiFunc |= ((value32 & BIT_BT_FUNC_EN_8821C) ? RT_MULTI_FUNC_BT : 0); + hal->PolarityCtl = ((value32 & BIT_WL_HWPDN_SL_8821C) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT); + + rtw_hal_config_rftype(adapter); + + dump_chip_info(hal->version_id); +} + +/* + * Return: + * _TRUE valid ID + * _FALSE invalid ID + */ +static u8 Hal_EfuseParseIDCode(PADAPTER adapter, u8 *map) +{ + u16 EEPROMId; + + /* Check 0x8129 again for making sure autoload status!! */ + EEPROMId = le16_to_cpu(*(u16 *)map); + RTW_INFO("EEPROM ID = 0x%04x\n", EEPROMId); + if (EEPROMId == RTL_EEPROM_ID) + return _TRUE; + + RTW_INFO("<WARN> EEPROM ID is invalid!!\n"); + return _FALSE; +} + +static void Hal_EfuseParseEEPROMVer(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (_TRUE == mapvalid) + hal->EEPROMVersion = map[EEPROM_VERSION_8821C]; + else + hal->EEPROMVersion = 1; + + RTW_INFO("EEPROM Version = %d\n", hal->EEPROMVersion); +} + +static void Hal_EfuseParseTxPowerInfo(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + TxPowerInfo24G tbl2G4; + TxPowerInfo5G tbl5g; + + hal_load_txpwr_info(adapter, &tbl2G4, &tbl5g, map); + + if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF)) + hal->EEPROMRegulatory = map[EEPROM_RF_BOARD_OPTION_8821C] & 0x7; /* bit0~2 */ + else + hal->EEPROMRegulatory = EEPROM_DEFAULT_BOARD_OPTION & 0x7; /* bit0~2 */ + RTW_INFO("EEPROM Regulatory=0x%02x\n", hal->EEPROMRegulatory); +} + +static void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF)) + hal->InterfaceSel = (map[EEPROM_RF_BOARD_OPTION_8821C] & 0xE0) >> 5; + else + hal->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5; + + RTW_INFO("EEPROM Board Type=0x%02x\n", hal->InterfaceSel); +} + +static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + u8 setting; + u32 tmpu4; + + if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) { + hal->EEPROMBluetoothCoexist = _FALSE; + goto exit; + } + + if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8821C] != 0xFF)) { + /* 0xc1[7:5] = 0x01 */ + if (((map[EEPROM_RF_BOARD_OPTION_8821C] & 0xe0) >> 5) == 0x01) + hal->EEPROMBluetoothCoexist = _TRUE; + else + hal->EEPROMBluetoothCoexist = _FALSE; + } else + hal->EEPROMBluetoothCoexist = _FALSE; + + hal->EEPROMBluetoothType = BT_RTL8821C; + + setting = map[EEPROM_RF_BT_SETTING_8821C]; + if ((_TRUE == mapvalid) && (setting != 0xFF)) { + /*Bit[0]: Total antenna number + 0: 2-Antenna / 1: 1-Antenna */ + hal->EEPROMBluetoothAntNum = setting & BIT(0); + /* + * Bit[6]: One-Ant structure use Ant2(aux.) path or Ant1(main) path + * 0: Ant2(aux.) + * 1: Ant1(main), default + */ + hal->ant_path = (setting & BIT(6)) ? ODM_RF_PATH_B : ODM_RF_PATH_A; + } else { + hal->EEPROMBluetoothAntNum = Ant_x1; + hal->ant_path = ODM_RF_PATH_A; + } + +exit: + RTW_INFO("EEPROM %s BT-coex, ant_num=%d\n", + hal->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable", + hal->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1); +} + +static void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail) +{ + adapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan( + adapter, + map ? &map[EEPROM_COUNTRY_CODE_8821C] : NULL, + map ? map[EEPROM_CHANNEL_PLAN_8821C] : 0xFF, + adapter->registrypriv.alpha2, + adapter->registrypriv.channel_plan, + RTW_CHPLAN_REALTEK_DEFINE, + autoloadfail + ); + + RTW_INFO("EEPROM ChannelPlan=0x%02x\n", adapter->mlmepriv.ChannelPlan); +} + +static void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if ((_TRUE == mapvalid) && map[EEPROM_XTAL_8821C] != 0xFF) + hal->crystal_cap = map[EEPROM_XTAL_8821C]; + else + hal->crystal_cap = EEPROM_Default_CrystalCap; + + RTW_INFO("EEPROM crystal_cap=0x%02x\n", hal->crystal_cap); +} + +static void Hal_EfuseParseThermalMeter(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + /* ThermalMeter from EEPROM */ + if ((_TRUE == mapvalid) && (map[EEPROM_THERMAL_METER_8821C] != 0xFF)) + hal->eeprom_thermal_meter = map[EEPROM_THERMAL_METER_8821C]; + else { + hal->eeprom_thermal_meter = EEPROM_Default_ThermalMeter; + hal->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE; + } + + RTW_INFO("EEPROM ThermalMeter=0x%02x\n", hal->eeprom_thermal_meter); +} + +static void Hal_EfuseParseAntennaDiversity(PADAPTER adapter, u8 *map, u8 mapvalid) +{ +} + +static void Hal_EfuseTxBBSwing(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + + if (_TRUE == mapvalid) { + hal_data->tx_bbswing_24G = map[EEPROM_TX_BBSWING_2G_8821C]; + if (0xFF == hal_data->tx_bbswing_24G) + hal_data->tx_bbswing_24G = 0; + hal_data->tx_bbswing_5G = map[EEPROM_TX_BBSWING_5G_8821C]; + if (0xFF == hal_data->tx_bbswing_5G) + hal_data->tx_bbswing_5G = 0; + } else { + hal_data->tx_bbswing_24G = 0; + hal_data->tx_bbswing_5G = 0; + } + RTW_INFO("EEPROM tx_bbswing_24G =0x%02x\n", hal_data->tx_bbswing_24G); + RTW_INFO("EEPROM tx_bbswing_5G =0x%02x\n", hal_data->tx_bbswing_5G); +} + +static void Hal_EfuseParseCustomerID(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (_TRUE == mapvalid) + hal->EEPROMCustomerID = map[EEPROM_CUSTOMER_ID_8821C]; + else + hal->EEPROMCustomerID = 0; + RTW_INFO("EEPROM Customer ID=0x%02x\n", hal->EEPROMCustomerID); +} + +static void Hal_DetectWoWMode(PADAPTER adapter) +{ + adapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _FALSE; + + RTW_INFO("EEPROM SupportRemoteWakeup=%d\n", adapter_to_pwrctl(adapter)->bSupportRemoteWakeup); +} + +static void hal_ReadPAType(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + + if (mapvalid) { + /* AUTO - Get INFO from eFuse*/ + if (GetRegAmplifierType2G(adapter) == 0) { + switch (hal_data->rfe_type) { + default: + hal_data->PAType_2G = 0; + hal_data->LNAType_2G = 0; + hal_data->ExternalPA_2G = 0; + hal_data->ExternalLNA_2G = 0; + break; + } + } else { + hal_data->ExternalPA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA) ? 1 : 0; + hal_data->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0; + } + + /* AUTO */ + if (GetRegAmplifierType5G(adapter) == 0) { + switch (hal_data->rfe_type) { + default: + hal_data->PAType_5G = 0; + hal_data->LNAType_5G = 0; + hal_data->external_pa_5g = 0; + hal_data->external_lna_5g = 0; + break; + } + } else { + hal_data->external_pa_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0; + hal_data->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0; + } + } else { + /*Get INFO from registry*/ + hal_data->ExternalPA_2G = EEPROM_Default_PAType; + hal_data->external_pa_5g = 0xFF; + hal_data->ExternalLNA_2G = EEPROM_Default_LNAType; + hal_data->external_lna_5g = 0xFF; + + if (GetRegAmplifierType2G(adapter) == 0) { + hal_data->ExternalPA_2G = 0; + hal_data->ExternalLNA_2G = 0; + } else { + hal_data->ExternalPA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA) ? 1 : 0; + hal_data->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0; + } + + if (GetRegAmplifierType5G(adapter) == 0) { + hal_data->external_pa_5g = 0; + hal_data->external_lna_5g = 0; + } else { + hal_data->external_pa_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0; + hal_data->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0; + } + } + + RTW_INFO("EEPROM PAType_2G is 0x%x, ExternalPA_2G = %d\n", hal_data->PAType_2G, hal_data->ExternalPA_2G); + RTW_INFO("EEPROM PAType_5G is 0x%x, external_pa_5g = %d\n", hal_data->PAType_5G, hal_data->external_pa_5g); + RTW_INFO("EEPROM LNAType_2G is 0x%x, ExternalLNA_2G = %d\n", hal_data->LNAType_2G, hal_data->ExternalLNA_2G); + RTW_INFO("EEPROM LNAType_5G is 0x%x, external_lna_5g = %d\n", hal_data->LNAType_5G, hal_data->external_lna_5g); +} + +static void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + + if (hal_data->rfe_type < 8) { /*According to RF-EFUSE DOC : R15]*/ + RTW_INFO("WIFI Module is iPA/iLNA\n"); + return; + } + + hal_ReadPAType(adapter, map, mapvalid); + + /* [2.4G] extPA */ + hal_data->TypeGPA = hal_data->PAType_2G; + + /* [5G] extPA */ + hal_data->TypeAPA = hal_data->PAType_5G; + + /* [2.4G] extLNA */ + hal_data->TypeGLNA = hal_data->LNAType_2G; + + /* [5G] extLNA */ + hal_data->TypeALNA = hal_data->LNAType_5G; + + RTW_INFO("EEPROM TypeGPA = 0x%X\n", hal_data->TypeGPA); + RTW_INFO("EEPROM TypeAPA = 0x%X\n", hal_data->TypeAPA); + RTW_INFO("EEPROM TypeGLNA = 0x%X\n", hal_data->TypeGLNA); + RTW_INFO("EEPROM TypeALNA = 0x%X\n", hal_data->TypeALNA); +} + +static void Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid) +{ + /* [20160-06-22 -R15] + Type 0 - (2-Ant, DPDT), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + Type 1 - (1-Ant, SPDT@Ant1), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + Type 2 -(1-Ant, SPDT@Ant1) , (2G_BTG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + Type 3 - (1-Ant, DPDT@Ant2), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + Type 4 - (1-Ant, DPDT@Ant2), (2G_BTG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + Type 5 - (2-Ant), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + Type 6 - (2-Ant), (2G_WLG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + Type 7 - (1-Ant), (2G_BTG, iPA, iLNA, iSW), (5G, iPA, iLNA, iSW) + */ + + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + /* check registry valye */ + if (GetRegRFEType(adapter) != CONFIG_RTW_RFE_TYPE) { + hal->rfe_type = GetRegRFEType(adapter); + goto exit; + } + + if (mapvalid) { + /* check efuse map */ + hal->rfe_type = map[EEPROM_RFE_OPTION_8821C]; + if (0xFF != hal->rfe_type) + goto exit; + } + + /* error handle */ + hal->rfe_type = 0; + RTW_ERR("please pg efuse or change RFE_Type of registrypriv!!\n"); + +exit: + RTW_INFO("EEPROM rfe_type=0x%x\n", hal->rfe_type); +} + +static void Hal_EfuseParsePackageType(PADAPTER adapter, u8 *map, u8 mapvalid) +{ +} + +/* + * Description: + * Collect all information from efuse or files. + * This function will do + * 1. Read registers to check hardware efuse available or not + * 2. Read Efuse/EEPROM + * 3. Read file if necessary + * 4. Parsing Efuse data + */ +u8 rtl8821c_read_efuse(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + u8 val8; + u8 *efuse_map = NULL; + u8 valid; + + hal = GET_HAL_DATA(adapter); + efuse_map = hal->efuse_eeprom_data; + + hal_read_mac_hidden_rpt(adapter); + + /* 1. Read registers to check hardware eFuse available or not */ + val8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8821C); + hal->bautoload_fail_flag = (val8 & BIT_AUTOLOAD_SUS_8821C) ? _FALSE : _TRUE; + /* + * In 8821C, bautoload_fail_flag is used to present eFuse map is valid + * or not, no matter the map comes from hardware or files. + */ + + /* 2. Read eFuse */ + EFUSE_ShadowMapUpdate(adapter, EFUSE_WIFI, 0); + + /* 3. Read Efuse file if necessary */ + + /* 4. Parse Efuse data */ + valid = Hal_EfuseParseIDCode(adapter, efuse_map); + if (_TRUE == valid) + hal->bautoload_fail_flag = _FALSE; + else + hal->bautoload_fail_flag = _TRUE; + + Hal_EfuseParseEEPROMVer(adapter, efuse_map, valid); + hal_config_macaddr(adapter, hal->bautoload_fail_flag); + Hal_EfuseParseTxPowerInfo(adapter, efuse_map, valid); + Hal_EfuseParseBoardType(adapter, efuse_map, valid); + Hal_EfuseParseBTCoexistInfo(adapter, efuse_map, valid); + Hal_EfuseParseChnlPlan(adapter, efuse_map, hal->bautoload_fail_flag); + Hal_EfuseParseXtal(adapter, efuse_map, valid); + Hal_EfuseParseThermalMeter(adapter, efuse_map, valid); + Hal_EfuseParseAntennaDiversity(adapter, efuse_map, valid); + Hal_EfuseParseCustomerID(adapter, efuse_map, valid); + Hal_DetectWoWMode(adapter); + Hal_ReadRFEType(adapter, efuse_map, valid); + Hal_ReadAmplifierType(adapter, efuse_map, valid); + Hal_EfuseTxBBSwing(adapter, efuse_map, valid); + + /* Data out of Efuse Map */ + Hal_EfuseParsePackageType(adapter, efuse_map, valid); + + return _SUCCESS; +} + +/* + * Description: + * Using 0x100 to check the power status of FW. + */ +static u8 check_ips_status(PADAPTER adapter) +{ + u8 val8; + + RTW_INFO(FUNC_ADPT_FMT ": Read 0x100=0x%02x 0x86=0x%02x\n", + FUNC_ADPT_ARG(adapter), + rtw_read8(adapter, 0x100), rtw_read8(adapter, 0x86)); + + val8 = rtw_read8(adapter, 0x100); + if (val8 == 0xEA) + return _TRUE; + + return _FALSE; +} + +static void update_ra_mask_8821c(_adapter *adapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg) +{ + u8 arg[4] = {0}; + + arg[0] = h2c_macid_cfg->mac_id; + arg[1] = h2c_macid_cfg->rate_id; + arg[2] = (h2c_macid_cfg->ignore_bw << 4) | h2c_macid_cfg->short_gi; + arg[3] = psta->init_rate; + + rtl8821c_set_FwMacIdConfig_cmd(adapter, h2c_macid_cfg->ra_mask, arg, h2c_macid_cfg->bandwidth); +} + +static void xmit_status_check(PADAPTER p) +{ +} + +static void linked_status_check(PADAPTER p) +{ +} + +static const struct hw_port_reg port_cfg[] = { + /*port 0*/ + { + .net_type = (REG_CR_8821C + 2), + .net_type_shift = 0, + .macaddr = REG_MACID, + .bssid = REG_BSSID, + .bcn_ctl = REG_BCN_CTRL, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_RST, + .bcn_space = REG_MBSSID_BCN_SPACE, + .bcn_space_shift = 0, + .bcn_space_mask = 0xffff, + .ps_aid = REG_BCN_PSR_RPT_8821C, + }, + /*port 1*/ + { + .net_type = (REG_CR_8821C + 2), + .net_type_shift = 2, + .macaddr = REG_MACID1, + .bssid = REG_BSSID1, + .bcn_ctl = REG_BCN_CTRL_CLINT0, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI0_RST, + .bcn_space = REG_MBSSID_BCN_SPACE, + .bcn_space_shift = 16, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT1_8821C, + }, + /*port 2*/ + { + .net_type = REG_CR_EXT_8821C, + .net_type_shift = 0, + .macaddr = REG_MACID2, + .bssid = REG_BSSID2, + .bcn_ctl = REG_BCN_CTRL_CLINT1, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI1_RST, + .bcn_space = REG_MBSSID_BCN_SPACE2, + .bcn_space_shift = 0, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT2_8821C, + }, + /*port 3*/ + { + .net_type = REG_CR_EXT_8821C, + .net_type_shift = 2, + .macaddr = REG_MACID3, + .bssid = REG_BSSID3, + .bcn_ctl = REG_BCN_CTRL_CLINT2, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI2_RST, + .bcn_space = REG_MBSSID_BCN_SPACE2, + .bcn_space_shift = 16, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT3_8821C, + }, + /*port 4*/ + { + .net_type = REG_CR_EXT_8821C, + .net_type_shift = 4, + .macaddr = REG_MACID4, + .bssid = REG_BSSID4, + .bcn_ctl = REG_BCN_CTRL_CLINT3, + .tsf_rst = REG_DUAL_TSF_RST, + .tsf_rst_bit = BIT_TSFTR_CLI3_RST, + .bcn_space = REG_MBSSID_BCN_SPACE3, + .bcn_space_shift = 0, + .bcn_space_mask = 0xfff, + .ps_aid = REG_BCN_PSR_RPT4_8821C, + }, +}; + +static void hw_bcn_ctrl_set(_adapter *adapter, u8 bcn_ctl_val) +{ + u8 hw_port = get_hw_port(adapter); + u32 bcn_ctl_addr = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + bcn_ctl_addr = port_cfg[hw_port].bcn_ctl; + rtw_write8(adapter, bcn_ctl_addr, bcn_ctl_val); +} + +static void hw_bcn_ctrl_add(_adapter *adapter, u8 bcn_ctl_val) +{ + u8 hw_port = get_hw_port(adapter); + u32 bcn_ctl_addr = 0; + u8 val8 = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + bcn_ctl_addr = port_cfg[hw_port].bcn_ctl; + val8 = rtw_read8(adapter, bcn_ctl_addr) | bcn_ctl_val; + rtw_write8(adapter, bcn_ctl_addr, val8); +} + +static void hw_bcn_ctrl_clr(_adapter *adapter, u8 bcn_ctl_val) +{ + u8 hw_port = get_hw_port(adapter); + u32 bcn_ctl_addr = 0; + u8 val8 = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + bcn_ctl_addr = port_cfg[hw_port].bcn_ctl; + val8 = rtw_read8(adapter, bcn_ctl_addr); + val8 &= ~bcn_ctl_val; + rtw_write8(adapter, bcn_ctl_addr, val8); +} + +static void hw_bcn_func(_adapter *adapter, u8 enable) +{ + if (enable) + hw_bcn_ctrl_add(adapter, BIT_EN_BCN_FUNCTION); + else + hw_bcn_ctrl_clr(adapter, BIT_EN_BCN_FUNCTION); +} +static void hw_bcn_ctrl_tsf(_adapter *adapter, u8 tsf_udt) +{ + if (tsf_udt) + hw_bcn_ctrl_clr(adapter, BIT_DIS_TSF_UDT); + else + hw_bcn_ctrl_add(adapter, BIT_DIS_TSF_UDT); +} + +void hw_port0_tsf_sync_sel(_adapter *adapter, u8 hw_port, u8 benable, u16 tr_offset) +{ + u8 val8; + u8 client_id = 0; + + if (adapter->tsf.sync_port != MAX_HW_PORT) + return; + + if (benable && hw_port == HW_PORT0) { + RTW_ERR(FUNC_ADPT_FMT ": hw_port is port0 under enable\n", FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + return; + } + + /*Disable Port0's beacon function*/ + hw_bcn_func(adapter, _FALSE); + + /*Reg 0x518[15:0]: TSFTR_SYN_OFFSET*/ + if (tr_offset) + rtw_write16(adapter, REG_TSFTR_SYN_OFFSET, tr_offset); + + /*reg 0x577[6]=1*/ /*auto sync by tbtt*/ + rtw_write8(adapter, REG_MISC_CTRL, rtw_read8(adapter, REG_MISC_CTRL) | BIT(6)); + + if (HW_PORT1 == hw_port) + client_id = 0; + else if (HW_PORT2 == hw_port) + client_id = 1; + else if (HW_PORT3 == hw_port) + client_id = 2; + else if (HW_PORT4 == hw_port) + client_id = 3; + + /*0x5B4 [6:4] :SYNC_CLI_SEL - The selector for the CLINT port of sync tsft source for port 0*/ + /* Bit[5:4] : 0 for clint0, 1 for clint1, 2 for clint2, 3 for clint3. + Bit6 : 1= enable sync to port 0. 0=disable sync to port 0.*/ + val8 = rtw_read8(adapter, REG_TIMER0_SRC_SEL); + if (benable) { + val8 &= 0x8F; + val8 |= (BIT(6) | (client_id << 4)); + } else { + val8 &= ~BIT(6); + } + rtw_write8(adapter, REG_TIMER0_SRC_SEL, val8); + + /*Enable Port0's beacon function*/ + hw_bcn_func(adapter, _TRUE); + + adapter->tsf.sync_port = hw_port; + adapter->tsf.offset = tr_offset; +} + +void get_tsf_by_port(_adapter *adapter, u8 *tsftr, u8 hw_port) +{ + u8 i; + u8 val8 = 0; + if (hw_port >= MAX_HW_PORT) { + RTW_ERR("%s hw port(%d) invalid\n", __func__, hw_port); + return; + } + /*0x554[30:28] -BIT_BCN_TIMER_SEL_FWRD*/ + val8 = rtw_read8(adapter, REG_MBSSID_BCN_SPACE + 3); + val8 &= 0x8F; + val8 |= hw_port << 4; + rtw_write8(adapter, REG_MBSSID_BCN_SPACE + 3, val8); + + for (i = 0; i < 8; i++) + tsftr[i] = rtw_read8(adapter, REG_TSFTR+i); +} + +void hw_tsf_reset(_adapter *adapter) +{ + u8 hw_port = get_hw_port(adapter); + u32 tsf_rst_addr = 0; + u8 tsf_rst_bit = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + tsf_rst_addr = port_cfg[hw_port].tsf_rst; + tsf_rst_bit = port_cfg[hw_port].tsf_rst_bit; + rtw_write8(adapter, tsf_rst_addr, tsf_rst_bit); +} + +static void hw_var_set_macaddr(PADAPTER adapter, u8 *val) +{ + if (!val) { + RTW_INFO(ADPT_FMT "set mac address(NULL) failed\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), adapter->hw_port, val); +} + +static void hw_var_set_bssid(PADAPTER adapter, u8 *val) +{ + if (!val) { + RTW_INFO(ADPT_FMT "set bssid (NULL) failed\n", ADPT_ARG(adapter)); + rtw_warn_on(1); + } + + rtw_halmac_set_bssid(adapter_to_dvobj(adapter), adapter->hw_port, val); +} + +static void hw_var_set_monitor(PADAPTER Adapter, u8 *val) +{ + u32 rcr_bits; + u8 mode; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + mode = *((u8 *)val); + + if (mode != _HW_STATE_MONITOR_) { + RTW_ERR(FUNC_ADPT_FMT" mode(0x%02x) invalid\n", FUNC_ADPT_ARG(Adapter), mode); + return; + } + + /* Receive all type */ + rcr_bits = BIT_AAP_8821C | BIT_APM_8821C | BIT_AM_8821C + | BIT_AB_8821C | BIT_APWRMGT_8821C + | BIT_APP_PHYSTS_8821C; + + /* Append FCS */ + rcr_bits |= BIT_APP_FCS_8821C; + + #ifdef CONFIG_RX_PACKET_APPEND_CRC + /*CRC and ICV packet will drop in rx func*/ + rcr_bits |= (BIT_ACRC32_8821C | BIT_AICV_8821C); + #endif + + rtl8821c_rcr_config(Adapter, rcr_bits); + /* Receive all data frames */ + rtw_write16(Adapter, REG_RXFLTMAP_8821C, 0xFFFF); +} + +static void hw_var_set_opmode(PADAPTER Adapter, u8 *val) +{ + u8 mode = *((u8 *)val); + static u8 isMonitor = _FALSE; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if (isMonitor == _TRUE) { + /* reset RCR */ + rtl8821c_rcr_config(Adapter, pHalData->ReceiveConfig); + isMonitor = _FALSE; + } + + if (mode == _HW_STATE_MONITOR_) { + isMonitor = _TRUE; + /* set net_type */ + Set_MSR(Adapter, _HW_STATE_NOLINK_); + + hw_var_set_monitor(Adapter, val); + return; + } + + Adapter->tsf.sync_port = MAX_HW_PORT; + Adapter->tsf.offset = 0; + + rtw_hal_set_hwreg(Adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(Adapter)); /* set mac addr to mac register */ + RTW_INFO(ADPT_FMT ": hw_port(%d) set mode=%d\n", ADPT_ARG(Adapter), get_hw_port(Adapter), mode); + + + /* set net_type */ + Set_MSR(Adapter, mode); + + if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { + + StopTxBeacon(Adapter); + hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); + + } else if ((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) { + ResumeTxBeacon(Adapter); + hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); + + } else if (mode == _HW_STATE_AP_) { + + if (Adapter->hw_port == HW_PORT0) { + ResumeTxBeacon(Adapter); + rtl8821c_rcr_clear(Adapter, RCR_CBSSID_DATA);/* Clear CBSSID_DATA */ + + /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ + if (Adapter->registrypriv.wifi_spec) + rtl8821c_rcr_clear(Adapter, RCR_CBSSID_BCN); + + /* enable to rx data frame */ + rtw_write16(Adapter, REG_RXFLTMAP_8821C, 0xFFFF); + + /* Beacon Control related register for first time */ + rtw_write8(Adapter, REG_BCNDMATIM_8821C, 0x02); /* 2ms */ + + rtw_write8(Adapter, REG_ATIMWND_8821C, 0x0a); /* 10ms */ + rtw_write16(Adapter, REG_BCNTCFG_8821C, 0x00); + rtw_write16(Adapter, REG_TBTT_PROHIBIT_8821C, 0xff04); + /*rtw_write16(Adapter, REG_TSFTR_SYN_OFFSET_8821C, 0x7fff);*//* +32767 (~32ms) */ + hw_tsf_reset(Adapter); + /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */ +#if defined(CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR) + hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C | BIT_P0_EN_TXBCN_RPT_8821C); +#else + hw_bcn_ctrl_set(Adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_DIS_TSF_UDT_8821C); +#endif + /*TODO hw_port0_tsf_sync_sel must modify for multi-interface && multi-port*/ + if (rtw_mi_buddy_check_fwstate(Adapter, (WIFI_STATION_STATE | WIFI_ASOC_STATE))) + hw_port0_tsf_sync_sel(Adapter, HW_PORT1, _TRUE, 0x32);/* About offset = 50ms*/ + + } else { + RTW_ERR(ADPT_FMT ": set AP mode on HW_PORT%d\n", ADPT_ARG(Adapter), Adapter->hw_port); + rtw_warn_on(1); + } + } +} + + +static void hw_var_set_basic_rate(PADAPTER adapter, u8 *ratetbl) +{ +#define RATE_1M BIT(0) +#define RATE_2M BIT(1) +#define RATE_5_5M BIT(2) +#define RATE_11M BIT(3) +#define RATE_6M BIT(4) +#define RATE_9M BIT(5) +#define RATE_12M BIT(6) +#define RATE_18M BIT(7) +#define RATE_24M BIT(8) +#define RATE_36M BIT(9) +#define RATE_48M BIT(10) +#define RATE_54M BIT(11) +#define RATE_MCS0 BIT(12) +#define RATE_MCS1 BIT(13) +#define RATE_MCS2 BIT(14) +#define RATE_MCS3 BIT(15) +#define RATE_MCS4 BIT(16) +#define RATE_MCS5 BIT(17) +#define RATE_MCS6 BIT(18) +#define RATE_MCS7 BIT(19) + +#define RATES_CCK (RATE_11M | RATE_5_5M | RATE_2M | RATE_1M) +#define RATES_OFDM (RATE_54M | RATE_48M | RATE_36M | RATE_24M | RATE_18M | RATE_12M | RATE_9M | RATE_6M) + + struct mlme_ext_info *mlmext_info = &adapter->mlmeextpriv.mlmext_info; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0; + u16 rrsr_2g_force_mask = RATES_CCK; + u16 rrsr_2g_allow_mask = RATE_24M | RATE_12M | RATE_6M | RATES_CCK; + u16 rrsr_5g_force_mask = RATE_6M; + u16 rrsr_5g_allow_mask = RATES_OFDM; + u32 val32; + + HalSetBrateCfg(adapter, ratetbl, &BrateCfg); + input_b = BrateCfg; + + /* apply force and allow mask */ + if (hal->current_band_type == BAND_ON_2_4G) { + BrateCfg |= rrsr_2g_force_mask; + BrateCfg &= rrsr_2g_allow_mask; + } else { + BrateCfg |= rrsr_5g_force_mask; + BrateCfg &= rrsr_5g_allow_mask; + } + + masked = BrateCfg; + + /* IOT consideration */ + if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) { + /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */ + if ((BrateCfg & (RATE_24M | RATE_12M | RATE_6M)) == 0) + BrateCfg |= RATE_6M; + } + + ioted = BrateCfg; + + hal->BasicRateSet = BrateCfg; + + RTW_INFO("[HW_VAR_BASIC_RATE] %#x->%#x->%#x\n", input_b, masked, ioted); + + /* Set RRSR rate table. */ + val32 = rtw_read32(adapter, REG_RRSR_8821C); + val32 &= ~(BIT_MASK_RRSC_BITMAP << BIT_SHIFT_RRSC_BITMAP); + val32 |= BIT_RRSC_BITMAP(BrateCfg); + val32 = rtw_write32(adapter, REG_RRSR_8821C, val32); +} + +static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable) +{ + u8 val8; + + if (enable) { + /* enable TX BCN report + * Reg REG_FWHW_TXQ_CTRL_8821C[2] = 1 + * Reg REG_BCN_CTRL_8821C[3][5] = 1 + */ + val8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8821C); + val8 |= BIT_EN_BCN_TRXRPT_V1_8821C; + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C, val8); + + if (adapter->hw_port == HW_PORT0) + hw_bcn_ctrl_add(adapter, BIT_EN_BCN_FUNCTION_8821C | BIT_P0_EN_TXBCN_RPT_8821C); + else + hw_bcn_ctrl_add(adapter, BIT_EN_BCN_FUNCTION_8821C); + } else { + if (adapter->hw_port == HW_PORT0) { + val8 = BIT_EN_BCN_FUNCTION_8821C | BIT_P0_EN_TXBCN_RPT_8821C; + + /* Always enable port0 beacon function for PSTDMA */ + if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist) + val8 = BIT_P0_EN_TXBCN_RPT_8821C; + hw_bcn_ctrl_clr(adapter, val8); + } else + hw_bcn_ctrl_clr(adapter, BIT_EN_BCN_FUNCTION_8821C); + } +} + +static void hw_var_set_correct_tsf(PADAPTER Adapter) +{ + /*hw_tsf_reset(Adapter);*/ + + /* disable func of port0 TSF sync from another port*/ + hw_port0_tsf_sync_sel(Adapter, Adapter->hw_port, _FALSE, 0); +} + +static void hw_var_set_check_bssid(PADAPTER adapter, u8 enable) +{ + u32 rcr; + + rcr = BIT_CBSSID_DATA_8821C | BIT_CBSSID_BCN_8821C; + if (enable) + rtl8821c_rcr_add(adapter, rcr); + else + rtl8821c_rcr_clear(adapter, rcr); + + RTW_INFO("%s: [HW_VAR_CHECK_BSSID] 0x%x=0x%x\n", __FUNCTION__, + REG_RCR_8821C, rtw_read32(adapter, REG_RCR_8821C)); +} + +static void hw_var_set_mlme_disconnect(PADAPTER adapter) +{ + u8 val8; + + /* reject all data frames under not link state */ + rtw_write16(adapter, REG_RXFLTMAP_8821C, 0); + + /* reset TSF*/ + hw_tsf_reset(adapter); + + /* disable update TSF*/ + hw_bcn_ctrl_tsf(adapter, _FALSE); + + /* disable Port's beacon function */ + hw_bcn_func(adapter, _FALSE); +} + +static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u32 rcr_bit; + u16 value_rxfltmap2; + u8 val8; + PHAL_DATA_TYPE hal; + struct mlme_priv *pmlmepriv; + int i; + _adapter *iface; + + + hal = GET_HAL_DATA(adapter); + pmlmepriv = &adapter->mlmepriv; + + rcr_bit = BIT_CBSSID_BCN_8821C | BIT_CBSSID_DATA_8821C; + + /* Receive all data frames */ + value_rxfltmap2 = 0xFFFF; + + if (rtw_mi_check_fwstate(adapter, WIFI_AP_STATE)) + rcr_bit = BIT_CBSSID_BCN_8821C; + + if (enable) { + /* + * 1. configure REG_RXFLTMAP2 + * 2. disable TSF update & buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN + * 3. config RCR to receive different BSSID BCN or probe rsp + */ + + rtw_write16(adapter, REG_RXFLTMAP_8821C, value_rxfltmap2); + + + /* disable update TSF */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + if (rtw_linked_check(iface) && + check_fwstate(&(iface->mlmepriv), WIFI_AP_STATE) != _TRUE) { + hw_bcn_ctrl_tsf(iface, _FALSE); + iface->mlmeextpriv.en_hw_update_tsf = _FALSE; + } + + } + + rtl8821c_rcr_clear(adapter, rcr_bit); + + /* Save orignal RRSR setting. */ + hal->RegRRSR = rtw_read16(adapter, REG_RRSR_8821C); + + if (rtw_mi_check_status(adapter, MI_AP_MODE)) + rtl8821c_stop_tx_beacon(adapter); + } else { + /* sitesurvey done + * 1. enable rx data frame + * 2. config RCR not to receive different BSSID BCN or probe rsp + * 3. can enable TSF update & buddy TSF right now due to HW support(IC before 8821C not support ex:8812A/8814A/8192E...) + */ + if (rtw_mi_check_fwstate(adapter, _FW_LINKED | WIFI_AP_STATE))/* enable to rx data frame */ + rtw_write16(adapter, REG_RXFLTMAP_8821C, 0xFFFF); + + /* for 11n Logo 4.2.31/4.2.32, disable BSSID BCN check for AP mode */ + if (adapter->registrypriv.wifi_spec && MLME_IS_AP(adapter)) + rcr_bit &= ~(BIT_CBSSID_BCN_8821C); + + rtl8821c_rcr_add(adapter, rcr_bit); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + if (rtw_linked_check(iface) && + check_fwstate(&(iface->mlmepriv), WIFI_AP_STATE) != _TRUE) { + /* enable HW TSF update when receive beacon*/ + hw_bcn_ctrl_tsf(iface, _TRUE); + iface->mlmeextpriv.en_hw_update_tsf = _FALSE; + } + } + + /* Restore orignal RRSR setting. */ + rtw_write16(adapter, REG_RRSR_8821C, hal->RegRRSR); + + if (rtw_mi_check_status(adapter, MI_AP_MODE)) { + rtl8821c_resume_tx_beacon(adapter); + rtw_mi_tx_beacon_hdl(adapter); + } + } +} +static void hw_var_set_mlme_join(PADAPTER adapter, u8 type) +{ + u8 val8; + u16 val16; + u32 val32; + u8 RetryLimit; + PHAL_DATA_TYPE hal; + struct mlme_priv *pmlmepriv; + + RetryLimit = 0x30; + hal = GET_HAL_DATA(adapter); + pmlmepriv = &adapter->mlmepriv; + + if (type == 0) { + /* prepare to join */ + + /* enable to rx data frame.Accept all data frame */ + rtw_write16(adapter, REG_RXFLTMAP_8821C, 0xFFFF); + + hw_var_set_check_bssid(adapter, !adapter->in_cta_test); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + RetryLimit = (hal->CustomerID == RT_CID_CCX) ? 7 : 48; + else /* Ad-hoc Mode */ + RetryLimit = 0x7; + hw_bcn_func(adapter, _TRUE); + } else if (type == 1) { + /* joinbss_event call back when join res < 0 */ + rtw_write16(adapter, REG_RXFLTMAP_8821C, 0x00); + } else if (type == 2) { + /* sta add event callback */ + + /* enable update TSF */ + hw_bcn_ctrl_tsf(adapter, _TRUE); + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) + RetryLimit = 0x7; + } + + val16 = BIT_LRL_8821C(RetryLimit) | BIT_SRL_8821C(RetryLimit); + rtw_write16(adapter, REG_RETRY_LIMIT_8821C, val16); +} + +static void hw_var_set_acm_ctrl(PADAPTER adapter, u8 ctrl) +{ + u8 hwctrl = 0; + + if (ctrl) { + hwctrl |= BIT_ACMHWEN_8821C; + + if (ctrl & BIT(1)) /* BE */ + hwctrl |= BIT_BEQ_ACM_EN_8821C; + else + hwctrl &= (~BIT_BEQ_ACM_EN_8821C); + + if (ctrl & BIT(2)) /* VI */ + hwctrl |= BIT_VIQ_ACM_EN_8821C; + else + hwctrl &= (~BIT_VIQ_ACM_EN_8821C); + + if (ctrl & BIT(3)) /* VO */ + hwctrl |= BIT_VOQ_ACM_EN_8821C; + else + hwctrl &= (~BIT_VOQ_ACM_EN_8821C); + } + + RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl); + rtw_write8(adapter, REG_ACMHWCTRL_8821C, hwctrl); +} + +static void hw_var_set_rcr_am(PADAPTER adapter, u8 enable) +{ + u32 rcr; + + rcr = BIT_AM_8821C; + if (enable) + rtl8821c_rcr_add(adapter, rcr); + else + rtl8821c_rcr_clear(adapter, rcr); + + RTW_INFO("%s: [HW_VAR_ON_RCR_AM] RCR(0x%x)=0x%x\n", + __FUNCTION__, REG_RCR_8821C, rtw_read32(adapter, REG_RCR_8821C)); +} + +static void hw_var_set_bcn_interval(PADAPTER adapter, u16 bcn_interval) +{ + + u8 hw_port = get_hw_port(adapter); + u32 bcn_interval_addr = 0; + u8 bcn_interval_shift = 0; + u16 bcn_interval_mask = 0; + u32 val32 = 0; + + if (hw_port >= MAX_HW_PORT) { + RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port); + rtw_warn_on(1); + return; + } + + bcn_interval_addr = port_cfg[hw_port].bcn_space; + bcn_interval_shift = port_cfg[hw_port].bcn_space_shift; + bcn_interval_mask = port_cfg[hw_port].bcn_space_mask; + + val32 = rtw_read32(adapter, bcn_interval_addr); + val32 &= (~(bcn_interval_mask << bcn_interval_shift)); + val32 |= (bcn_interval & bcn_interval_mask) << bcn_interval_shift; + + rtw_write32(adapter, bcn_interval_addr, val32); + + RTW_INFO(ADPT_FMT" BEACON_INTERVAL : 0x%x = 0x%x\n", ADPT_ARG(adapter), + bcn_interval_addr, (rtw_read32(adapter, bcn_interval_addr) >> bcn_interval_shift) & bcn_interval_mask); +} + +static void hw_var_set_sec_cfg(PADAPTER adapter, u8 cfg) +{ + u16 reg_scr_ori; + u16 reg_scr; + + reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG_8821C); + reg_scr |= (BIT_CHK_KEYID_8821C | BIT_RXDEC_8821C | BIT_TXENC_8821C); + + if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC)) + reg_scr |= BIT_CHK_BMC_8821C; + + if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH)) + reg_scr |= BIT_NOSKMC_8821C; + + if (reg_scr != reg_scr_ori) + rtw_write16(adapter, REG_SECCFG_8821C, reg_scr); + + RTW_INFO("%s: [HW_VAR_SEC_CFG] 0x%x=0x%x\n", __FUNCTION__, + REG_SECCFG_8821C, rtw_read32(adapter, REG_SECCFG_8821C)); +} + +static void hw_var_set_sec_dk_cfg(PADAPTER adapter, u8 enable) +{ + struct security_priv *sec = &adapter->securitypriv; + u8 reg_scr = rtw_read8(adapter, REG_SECCFG_8821C); + + if (enable) { + /* Enable default key related setting */ + reg_scr |= BIT_TXBCUSEDK_8821C; + if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X) + reg_scr |= BIT_RXUHUSEDK_8821C | BIT_TXUHUSEDK_8821C; + } else { + /* Disable default key related setting */ + reg_scr &= ~(BIT_RXBCUSEDK_8821C | BIT_TXBCUSEDK_8821C | BIT_RXUHUSEDK_8821C | BIT_TXUHUSEDK_8821C); + } + + rtw_write8(adapter, REG_SECCFG_8821C, reg_scr); + + RTW_INFO("%s: [HW_VAR_SEC_DK_CFG] 0x%x=0x%08x\n", __FUNCTION__, + REG_SECCFG_8821C, rtw_read32(adapter, REG_SECCFG_8821C)); +} + +static void hw_var_set_bcn_valid(PADAPTER adapter) +{ + u8 val8 = 0; + + /* only port 0 can TX BCN */ + val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8821C + 1); + val8 = val8 | BIT(7); + rtw_write8(adapter, REG_FIFOPAGE_CTRL_2_8821C + 1, val8); +} + +static void hw_var_set_cam_empty_entry(PADAPTER adapter, u8 ucIndex) +{ + u8 i; + u32 ulCommand = 0; + u32 ulContent = 0; + u32 ulEncAlgo = CAM_AES; + + for (i = 0; i < CAM_CONTENT_COUNT; i++) { + /* filled id in CAM config 2 byte */ + if (i == 0) + ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2); + else + ulContent = 0; + + /* polling bit, and No Write enable, and address */ + ulCommand = CAM_CONTENT_COUNT * ucIndex + i; + ulCommand |= BIT_SECCAM_POLLING_8821C | BIT_SECCAM_WE_8821C; + /* write content 0 is equall to mark invalid */ + rtw_write32(adapter, REG_CAMWRITE_8821C, ulContent); + rtw_write32(adapter, REG_CAMCMD_8821C, ulCommand); + } +} + +static void hw_var_set_ack_preamble(PADAPTER adapter, u8 bShortPreamble) +{ + u8 val8 = 0; + + val8 = rtw_read8(adapter, REG_WMAC_TRXPTCL_CTL_8821C + 2); + val8 |= BIT(4) | BIT(5); + + if (bShortPreamble) + val8 |= BIT1; + else + val8 &= (~BIT1); + + rtw_write8(adapter, REG_WMAC_TRXPTCL_CTL_8821C + 2, val8); +} + +void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + BOOLEAN bcn_valid = _FALSE; + u8 DLBcnCount = 0; + u32 poll = 0; + u8 val8; + + RTW_INFO(FUNC_ADPT_FMT ":+ hw_port=%d mstatus(%x)\n", + FUNC_ADPT_ARG(adapter), get_hw_port(adapter), mstatus); + + if (mstatus == RT_MEDIA_CONNECT) { + BOOLEAN bRecover = _FALSE; + u8 v8; + + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 8821C -bit 10:0 */ + rtw_write16(adapter, port_cfg[get_hw_port(adapter)].ps_aid, (0xF800 | pmlmeinfo->aid)); + + /* Enable SW TX beacon - Set REG_CR bit 8. DMA beacon by SW */ + v8 = rtw_read8(adapter, REG_CR_8821C + 1); + v8 |= (BIT_ENSWBCN_8821C >> 8); + rtw_write8(adapter, REG_CR_8821C + 1, v8); + + /* + * Disable Hw protection for a time which revserd for Hw sending beacon. + * Fix download reserved page packet fail that access collision with the protection time. + */ + val8 = rtw_read8(adapter, REG_BCN_CTRL_8821C); + val8 &= ~BIT_EN_BCN_FUNCTION_8821C; + val8 |= BIT_DIS_TSF_UDT_8821C; + rtw_write8(adapter, REG_BCN_CTRL_8821C, val8); + + /* Clear beacon valid check bit. */ + rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL); + + DLBcnCount = 0; + poll = 0; + do { + /* download rsvd page. */ + rtw_hal_set_fw_rsvd_page(adapter, 0); + DLBcnCount++; + do { + rtw_yield_os(); + + /* check rsvd page download OK. */ + rtw_hal_get_hwreg(adapter, HW_VAR_BCN_VALID, (u8 *)(&bcn_valid)); + poll++; + } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(adapter)); + + } while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(adapter)); + + if (RTW_CANNOT_RUN(adapter)) + ; + else if (!bcn_valid) + RTW_INFO(FUNC_ADPT_FMT ": DL RSVD page failed! DLBcnCount:%u, poll:%u\n", + FUNC_ADPT_ARG(adapter), DLBcnCount, poll); + else { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + pwrctl->fw_psmode_iface_id = adapter->iface_id; + RTW_INFO(ADPT_FMT ": DL RSVD page success! DLBcnCount:%u, poll:%u\n", + ADPT_ARG(adapter), DLBcnCount, poll); + } + + val8 = rtw_read8(adapter, REG_BCN_CTRL_8821C); + val8 |= BIT_EN_BCN_FUNCTION_8821C; + val8 &= ~BIT_DIS_TSF_UDT_8821C; + rtw_write8(adapter, REG_BCN_CTRL_8821C, val8); + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ + v8 = rtw_read8(adapter, REG_CR_8821C + 1); + v8 &= ~BIT(0); /* ~ENSWBCN */ + rtw_write8(adapter, REG_CR_8821C + 1, v8); + } + +} + +static void hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus) +{ + if (mstatus == RT_MEDIA_CONNECT) + hw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT); +} + +/* + * Description: Get the reserved page number in Tx packet buffer. + * Retrun value: the page number. + */ +u8 get_txbuffer_rsvdpagenum(PADAPTER adapter, bool wowlan) +{ + u8 RsvdPageNum = HALMAC_RSVD_DRV_PGNUM_8821C; + + return RsvdPageNum; +} + +/* + * Parameters: + * adapter + * enable _TRUE: enable; _FALSE: disable + */ +static u8 rx_agg_switch(PADAPTER adapter, u8 enable) +{ + /* if (rtl8821c_config_rx_agg(adapter, enable)) */ + return _SUCCESS; + + return _FAIL; +} + +void rtl8821c_sethwreg(PADAPTER adapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u8 val8; + u16 val16; + u32 val32; + + switch (variable) { + case HW_VAR_SET_OPMODE: + hw_var_set_opmode(adapter, val); + break; + + case HW_VAR_MAC_ADDR: + hw_var_set_macaddr(adapter, val); + break; + + case HW_VAR_BSSID: + hw_var_set_bssid(adapter, val); + break; + /* + case HW_VAR_INIT_RTS_RATE: + break; + */ + case HW_VAR_BASIC_RATE: + hw_var_set_basic_rate(adapter, val); + break; + + case HW_VAR_TXPAUSE: + rtw_write8(adapter, REG_TXPAUSE_8821C, *val); + break; + + case HW_VAR_BCN_FUNC: + hw_var_set_bcn_func(adapter, *val); + break; + + case HW_VAR_CORRECT_TSF: + hw_var_set_correct_tsf(adapter); + break; + + case HW_VAR_CHECK_BSSID: + hw_var_set_check_bssid(adapter, *val); + break; + + case HW_VAR_MLME_DISCONNECT: + hw_var_set_mlme_disconnect(adapter); + break; + + case HW_VAR_MLME_SITESURVEY: + hw_var_set_mlme_sitesurvey(adapter, *val); + if (hal->EEPROMBluetoothCoexist) + rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE); + else + rtw_btcoex_wifionly_scan_notify(adapter); + + break; + + case HW_VAR_MLME_JOIN: + hw_var_set_mlme_join(adapter, *val); + + if (hal->EEPROMBluetoothCoexist) { + switch (*val) { + case 0: + /* Notify coex. mechanism before join */ + rtw_btcoex_ConnectNotify(adapter, _TRUE); + break; + case 1: + case 2: + /* Notify coex. mechanism after join, whether successful or failed */ + rtw_btcoex_ConnectNotify(adapter, _FALSE); + break; + } + } + break; + + case HW_VAR_ON_RCR_AM: + hw_var_set_rcr_am(adapter, 1); + break; + + case HW_VAR_OFF_RCR_AM: + hw_var_set_rcr_am(adapter, 0); + break; + + case HW_VAR_BEACON_INTERVAL: + hw_var_set_bcn_interval(adapter, *(u16 *)val); +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u16 bcn_interval = *((u16 *)val); + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + RTW_INFO("%s==> bcn_interval:%d, eraly_int:%d\n", __FUNCTION__, bcn_interval, bcn_interval >> 1); + rtw_write8(adapter, REG_DRVERLYINT, bcn_interval >> 1); /* 50ms for sdio */ + } + } +#endif/* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + break; + + case HW_VAR_SLOT_TIME: + rtw_write8(adapter, REG_SLOT_8821C, *val); + break; + + case HW_VAR_RESP_SIFS: + /* RESP_SIFS for CCK */ + rtw_write8(adapter, REG_RESP_SIFS_CCK_8821C, val[0]); + rtw_write8(adapter, REG_RESP_SIFS_CCK_8821C + 1, val[1]); + /* RESP_SIFS for OFDM */ + rtw_write8(adapter, REG_RESP_SIFS_OFDM_8821C, val[2]); + rtw_write8(adapter, REG_RESP_SIFS_OFDM_8821C + 1, val[3]); + break; + + case HW_VAR_ACK_PREAMBLE: + hw_var_set_ack_preamble(adapter, *val); + break; + + case HW_VAR_SEC_CFG: + hw_var_set_sec_cfg(adapter, *val); + break; + + case HW_VAR_SEC_DK_CFG: + if (val) + hw_var_set_sec_dk_cfg(adapter, _TRUE); + else + hw_var_set_sec_dk_cfg(adapter, _FALSE); + break; + + case HW_VAR_BCN_VALID: + hw_var_set_bcn_valid(adapter); + break; + /* + case HW_VAR_RF_TYPE: + break; + */ + case HW_VAR_CAM_EMPTY_ENTRY: + hw_var_set_cam_empty_entry(adapter, *val); + break; + + case HW_VAR_CAM_INVALID_ALL: + val32 = BIT_SECCAM_POLLING_8821C | BIT_SECCAM_CLR_8821C; + rtw_write32(adapter, REG_CAMCMD_8821C, val32); + break; + + case HW_VAR_AC_PARAM_VO: + rtw_write32(adapter, REG_EDCA_VO_PARAM_8821C, *(u32 *)val); + break; + + case HW_VAR_AC_PARAM_VI: + rtw_write32(adapter, REG_EDCA_VI_PARAM_8821C, *(u32 *)val); + break; + + case HW_VAR_AC_PARAM_BE: + hal->ac_param_be = *(u32 *)val; + rtw_write32(adapter, REG_EDCA_BE_PARAM_8821C, *(u32 *)val); + break; + + case HW_VAR_AC_PARAM_BK: + rtw_write32(adapter, REG_EDCA_BK_PARAM_8821C, *(u32 *)val); + break; + + case HW_VAR_ACM_CTRL: + hw_var_set_acm_ctrl(adapter, *val); + break; + /* + case HW_VAR_AMPDU_MIN_SPACE: + break; + */ + case HW_VAR_AMPDU_FACTOR: { + u32 AMPDULen = *val; /* enum AGGRE_SIZE */ + + AMPDULen = (0x2000 << AMPDULen) - 1; + rtw_write32(adapter, REG_AMPDU_MAX_LENGTH_8821C, AMPDULen); + } + break; + + case HW_VAR_RXDMA_AGG_PG_TH: + /* + * TH=1 => invalidate RX DMA aggregation + * TH=0 => validate RX DMA aggregation, use init value. + */ + if (*val == 0) + /* enable RXDMA aggregation */ + rx_agg_switch(adapter, _TRUE); + else + /* disable RXDMA aggregation */ + rx_agg_switch(adapter, _FALSE); + break; + + case HW_VAR_H2C_FW_PWRMODE: + rtl8821c_set_FwPwrMode_cmd(adapter, *val); + break; + /* + case HW_VAR_H2C_PS_TUNE_PARAM: + break; + */ + case HW_VAR_H2C_FW_JOINBSSRPT: + hw_var_set_h2c_fw_joinbssrpt(adapter, *val); + break; + /* + case HW_VAR_FWLPS_RF_ON: + break; + */ + case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: + rtw_set_p2p_ps_offload_cmd(adapter, *val); + break; + + /* + case HW_VAR_TRIGGER_GPIO_0: + case HW_VAR_BT_SET_COEXIST: + case HW_VAR_BT_ISSUE_DELBA: + case HW_VAR_CURRENT_ANTENNA: + break; + */ +#ifdef CONFIG_SW_ANTENNA_DIVERSITY + case HW_VAR_ANTENNA_DIVERSITY_SELECT: + ODM_SetAntConfig(&hal->odmpriv, *val); + break; +#endif + /* + case HW_VAR_SWITCH_EPHY_WoWLAN: + case HW_VAR_EFUSE_USAGE: + case HW_VAR_EFUSE_BYTES: + case HW_VAR_EFUSE_BT_USAGE: + case HW_VAR_EFUSE_BT_BYTES: + break; + */ + case HW_VAR_FIFO_CLEARN_UP: { + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + u8 trycnt = 100; + u32 reg_hw_ssn; + + /* pause tx */ + rtw_write8(adapter, REG_TXPAUSE_8821C, 0xff); + + /* keep hw sn */ + if (adapter->xmitpriv.hw_ssn_seq_no == 1) + reg_hw_ssn = REG_HW_SEQ1_8821C; + else if (adapter->xmitpriv.hw_ssn_seq_no == 2) + reg_hw_ssn = REG_HW_SEQ2_8821C; + else if (adapter->xmitpriv.hw_ssn_seq_no == 3) + reg_hw_ssn = REG_HW_SEQ3_8821C; + else + reg_hw_ssn = REG_HW_SEQ0_8821C; + + adapter->xmitpriv.nqos_ssn = rtw_read16(adapter, reg_hw_ssn); + + if (pwrpriv->bkeepfwalive != _TRUE) { + /* RX DMA stop */ + val32 = rtw_read32(adapter, REG_RXPKT_NUM_8821C); + val32 |= BIT_RW_RELEASE_EN; + rtw_write32(adapter, REG_RXPKT_NUM_8821C, val32); + do { + val32 = rtw_read32(adapter, REG_RXPKT_NUM_8821C); + val32 &= BIT_RXDMA_IDLE_8821C; + if (val32) + break; + + RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", val32, trycnt); + } while (--trycnt); + if (trycnt == 0) + RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed!\n"); + } + } + break; + + case HW_VAR_RESTORE_HW_SEQ: { + /* restore Sequence No. */ + u32 reg_hw_ssn; + + if (adapter->xmitpriv.hw_ssn_seq_no == 1) + reg_hw_ssn = REG_HW_SEQ1_8821C; + else if (adapter->xmitpriv.hw_ssn_seq_no == 2) + reg_hw_ssn = REG_HW_SEQ2_8821C; + else if (adapter->xmitpriv.hw_ssn_seq_no == 3) + reg_hw_ssn = REG_HW_SEQ3_8821C; + else + reg_hw_ssn = REG_HW_SEQ0_8821C; + + rtw_write8(adapter, reg_hw_ssn, adapter->xmitpriv.nqos_ssn); + } + break; + + case HW_VAR_CHECK_TXBUF: { + u16 rtylmtorg; + u8 RetryLimit = 0x01; + u32 start, passtime; + u32 timelmt = 2000; /* ms */ + u32 waittime = 10; /* ms */ + u32 high, low, normal, extra, publc; + u16 rsvd, available; + u8 empty; + + rtylmtorg = rtw_read16(adapter, REG_RETRY_LIMIT_8821C); + + val16 = BIT_LRL_8821C(RetryLimit) | BIT_SRL_8821C(RetryLimit); + rtw_write16(adapter, REG_RETRY_LIMIT_8821C, val16); + + /* Check TX FIFO empty or not */ + empty = _FALSE; + high = 0; + low = 0; + normal = 0; + extra = 0; + publc = 0; + start = rtw_get_current_time(); + while ((rtw_get_passing_time_ms(start) < timelmt) + && !RTW_CANNOT_RUN(adapter)) { + high = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8821C); + low = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8821C); + normal = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8821C); + extra = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8821C); + publc = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8821C); + + rsvd = BIT_GET_HPQ_V1_8821C(high); + available = BIT_GET_HPQ_AVAL_PG_V1_8821C(high); + if (rsvd != available) { + rtw_msleep_os(waittime); + continue; + } + + rsvd = BIT_GET_LPQ_V1_8821C(low); + available = BIT_GET_LPQ_AVAL_PG_V1_8821C(low); + if (rsvd != available) { + rtw_msleep_os(waittime); + continue; + } + + rsvd = BIT_GET_NPQ_V1_8821C(normal); + available = BIT_GET_NPQ_AVAL_PG_V1_8821C(normal); + if (rsvd != available) { + rtw_msleep_os(waittime); + continue; + } + + rsvd = BIT_GET_EXQ_V1_8821C(extra); + available = BIT_GET_EXQ_AVAL_PG_V1_8821C(extra); + if (rsvd != available) { + rtw_msleep_os(waittime); + continue; + } + + rsvd = BIT_GET_PUBQ_V1_8821C(publc); + available = BIT_GET_PUBQ_AVAL_PG_V1_8821C(publc); + if (rsvd != available) { + rtw_msleep_os(waittime); + continue; + } + + empty = _TRUE; + break; + } + + passtime = rtw_get_passing_time_ms(start); + if (_TRUE == empty) + RTW_INFO("[HW_VAR_CHECK_TXBUF] Empty in %d ms\n", passtime); + else if (RTW_CANNOT_RUN(adapter)) + RTW_INFO("[HW_VAR_CHECK_TXBUF] bDriverStopped or bSurpriseRemoved\n"); + else { + RTW_INFO("[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\n", passtime); + RTW_INFO("[HW_VAR_CHECK_TXBUF] 0x230=0x%08x 0x234=0x%08x 0x238=0x%08x 0x23c=0x%08x 0x240=0x%08x\n", + high, low, normal, extra, publc); + } + + rtw_write16(adapter, REG_RETRY_LIMIT_8821C, rtylmtorg); + } + break; + /* + case HW_VAR_PCIE_STOP_TX_DMA: + break; + */ + + /* + case HW_VAR_SYS_CLKR: + break; + */ + case HW_VAR_NAV_UPPER: { +#define HAL_NAV_UPPER_UNIT 128 /* micro-second */ + u32 usNavUpper = *(u32 *)val; + + if (usNavUpper > HAL_NAV_UPPER_UNIT * 0xFF) { + RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_NAV_UPPER] value(0x%08X us) is larger than (%d * 0xFF)!!!\n", + FUNC_ADPT_ARG(adapter), usNavUpper, HAL_NAV_UPPER_UNIT); + break; + } + + usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT - 1) / HAL_NAV_UPPER_UNIT; + rtw_write8(adapter, REG_NAV_CTRL_8821C + 2, (u8)usNavUpper); + } + break; + + /* + case HW_VAR_RPT_TIMER_SETTING: + case HW_VAR_TX_RPT_MAX_MACID: + case HW_VAR_CHK_HI_QUEUE_EMPTY: + break; + */ + + /* + case HW_VAR_AMPDU_MAX_TIME: + case HW_VAR_WIRELESS_MODE: + case HW_VAR_USB_MODE: + break; + */ + case HW_VAR_DO_IQK: + if (*val) + hal->bNeedIQK = _TRUE; + else + hal->bNeedIQK = _FALSE; + break; + + case HW_VAR_DM_IN_LPS: + rtl8821c_phy_haldm_in_lps(adapter); + break; + /* + case HW_VAR_SET_REQ_FW_PS: + case HW_VAR_FW_PS_STATE: + case HW_VAR_SOUNDING_ENTER: + case HW_VAR_SOUNDING_LEAVE: + case HW_VAR_SOUNDING_RATE: + case HW_VAR_SOUNDING_STATUS: + case HW_VAR_SOUNDING_FW_NDPA: + case HW_VAR_SOUNDING_CLK: + break; + */ + case HW_VAR_DL_RSVD_PAGE: + if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtl8821c_download_BTCoex_AP_mode_rsvd_page(adapter); + else + { + hw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT); + } + break; + + case HW_VAR_MACID_SLEEP: { + u32 reg_macid_sleep; + u8 bit_shift; + u8 id = *(u8 *)val; + + if (id < 32) { + reg_macid_sleep = REG_MACID_SLEEP_8821C; + bit_shift = id; + } else if (id < 64) { + reg_macid_sleep = REG_MACID_SLEEP1_8821C; + bit_shift = id - 32; + } else if (id < 96) { + reg_macid_sleep = REG_MACID_SLEEP2_8821C; + bit_shift = id - 64; + } else if (id < 128) { + reg_macid_sleep = REG_MACID_SLEEP3_8821C; + bit_shift = id - 96; + } else { + rtw_warn_on(1); + break; + } + + val32 = rtw_read32(adapter, reg_macid_sleep); + RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid=%d, org reg_0x%03x=0x%08X\n", + FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32); + + if (val32 & BIT(bit_shift)) + break; + + val32 |= BIT(bit_shift); + rtw_write32(adapter, reg_macid_sleep, val32); + } + break; + + case HW_VAR_MACID_WAKEUP: { + u32 reg_macid_sleep; + u8 bit_shift; + u8 id = *(u8 *)val; + + if (id < 32) { + reg_macid_sleep = REG_MACID_SLEEP_8821C; + bit_shift = id; + } else if (id < 64) { + reg_macid_sleep = REG_MACID_SLEEP1_8821C; + bit_shift = id - 32; + } else if (id < 96) { + reg_macid_sleep = REG_MACID_SLEEP2_8821C; + bit_shift = id - 64; + } else if (id < 128) { + reg_macid_sleep = REG_MACID_SLEEP3_8821C; + bit_shift = id - 96; + } else { + rtw_warn_on(1); + break; + } + + val32 = rtw_read32(adapter, reg_macid_sleep); + RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid=%d, org reg_0x%03x=0x%08X\n", + FUNC_ADPT_ARG(adapter), id, reg_macid_sleep, val32); + + if (!(val32 & BIT(bit_shift))) + break; + + val32 &= ~BIT(bit_shift); + rtw_write32(adapter, reg_macid_sleep, val32); + } + break; + + default: + SetHwReg(adapter, variable, val); + break; + } + +} + +struct qinfo { + u32 head:8; + u32 pkt_num:7; + u32 tail:8; + u32 ac:2; + u32 macid:7; +}; + +struct bcn_qinfo { + u16 head:8; + u16 pkt_num:8; +}; + +static void dump_qinfo(void *sel, struct qinfo *info, const char *tag) +{ + RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n", + tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac); +} + +static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, const char *tag) +{ + RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n", + tag ? tag : "", info->head, info->pkt_num); +} + +static void dump_mac_qinfo(void *sel, _adapter *adapter) +{ + u32 q0_info; + u32 q1_info; + u32 q2_info; + u32 q3_info; + u32 q4_info; + u32 q5_info; + u32 q6_info; + u32 q7_info; + u32 mg_q_info; + u32 hi_q_info; + u16 bcn_q_info; + + q0_info = rtw_read32(adapter, REG_Q0_INFO_8821C); + q1_info = rtw_read32(adapter, REG_Q1_INFO_8821C); + q2_info = rtw_read32(adapter, REG_Q2_INFO_8821C); + q3_info = rtw_read32(adapter, REG_Q3_INFO_8821C); + q4_info = rtw_read32(adapter, REG_Q4_INFO_8821C); + q5_info = rtw_read32(adapter, REG_Q5_INFO_8821C); + q6_info = rtw_read32(adapter, REG_Q6_INFO_8821C); + q7_info = rtw_read32(adapter, REG_Q7_INFO_8821C); + mg_q_info = rtw_read32(adapter, REG_MGQ_INFO_8821C); + hi_q_info = rtw_read32(adapter, REG_HIQ_INFO_8821C); + bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO_8821C); + + dump_qinfo(sel, (struct qinfo *)&q0_info, "Q0 "); + dump_qinfo(sel, (struct qinfo *)&q1_info, "Q1 "); + dump_qinfo(sel, (struct qinfo *)&q2_info, "Q2 "); + dump_qinfo(sel, (struct qinfo *)&q3_info, "Q3 "); + dump_qinfo(sel, (struct qinfo *)&q4_info, "Q4 "); + dump_qinfo(sel, (struct qinfo *)&q5_info, "Q5 "); + dump_qinfo(sel, (struct qinfo *)&q6_info, "Q6 "); + dump_qinfo(sel, (struct qinfo *)&q7_info, "Q7 "); + dump_qinfo(sel, (struct qinfo *)&mg_q_info, "MG "); + dump_qinfo(sel, (struct qinfo *)&hi_q_info, "HI "); + dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, "BCN "); +} + +static u8 hw_var_get_bcn_valid(PADAPTER adapter) +{ + u8 val8 = 0; + u8 ret = _FALSE; + + /* only port 0 can TX BCN */ + val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8821C + 1); + ret = (BIT(7) & val8) ? _TRUE : _FALSE; + + return ret; +} + +void rtl8821c_gethwreg(PADAPTER adapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE hal; + u8 val8; + u16 val16; + u32 val32; + + hal = GET_HAL_DATA(adapter); + + switch (variable) { + /* + case HW_VAR_SET_OPMODE: + case HW_VAR_MAC_ADDR: + case HW_VAR_BSSID: + case HW_VAR_INIT_RTS_RATE: + case HW_VAR_BASIC_RATE: + break; + */ + case HW_VAR_TXPAUSE: + *val = rtw_read8(adapter, REG_TXPAUSE_8821C); + break; + /* + case HW_VAR_BCN_FUNC: + case HW_VAR_CORRECT_TSF: + case HW_VAR_CHECK_BSSID: + case HW_VAR_MLME_DISCONNECT: + case HW_VAR_MLME_SITESURVEY: + case HW_VAR_MLME_JOIN: + case HW_VAR_ON_RCR_AM: + case HW_VAR_OFF_RCR_AM: + case HW_VAR_BEACON_INTERVAL: + case HW_VAR_SLOT_TIME: + case HW_VAR_RESP_SIFS: + case HW_VAR_ACK_PREAMBLE: + case HW_VAR_SEC_CFG: + case HW_VAR_SEC_DK_CFG: + break; + */ + case HW_VAR_BCN_VALID: + *val = hw_var_get_bcn_valid(adapter); + break; + /* + case HW_VAR_RF_TYPE: + case HW_VAR_CAM_EMPTY_ENTRY: + case HW_VAR_CAM_INVALID_ALL: + case HW_VAR_AC_PARAM_VO: + case HW_VAR_AC_PARAM_VI: + case HW_VAR_AC_PARAM_BE: + case HW_VAR_AC_PARAM_BK: + case HW_VAR_ACM_CTRL: + case HW_VAR_AMPDU_MIN_SPACE: + case HW_VAR_AMPDU_FACTOR: + case HW_VAR_RXDMA_AGG_PG_TH: + case HW_VAR_H2C_FW_PWRMODE: + case HW_VAR_H2C_PS_TUNE_PARAM: + case HW_VAR_H2C_FW_JOINBSSRPT: + break; + */ + case HW_VAR_FWLPS_RF_ON: + /* When we halt NIC, we should check if FW LPS is leave. */ + if (rtw_is_surprise_removed(adapter) || + (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)) { + /* + * If it is in HW/SW Radio OFF or IPS state, + * we do not check Fw LPS Leave, + * because Fw is unload. + */ + *val = _TRUE; + } else { + rtl8821c_rcr_get(adapter, &val32); + val32 &= (BIT_UC_MD_EN_8821C | BIT_BC_MD_EN_8821C | BIT_TIM_PARSER_EN_8821C); + if (val32) + *val = _FALSE; + else + *val = _TRUE; + } + break; + /* + case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: + case HW_VAR_TDLS_WRCR: + case HW_VAR_TDLS_RS_RCR: + case HW_VAR_TRIGGER_GPIO_0: + case HW_VAR_BT_SET_COEXIST: + case HW_VAR_BT_ISSUE_DELBA: + break; + */ + /* + case HW_VAR_ANTENNA_DIVERSITY_SELECT: + case HW_VAR_SWITCH_EPHY_WoWLAN: + case HW_VAR_EFUSE_USAGE: + case HW_VAR_EFUSE_BYTES: + case HW_VAR_EFUSE_BT_USAGE: + case HW_VAR_EFUSE_BT_BYTES: + case HW_VAR_FIFO_CLEARN_UP: + case HW_VAR_RESTORE_HW_SEQ: + case HW_VAR_CHECK_TXBUF: + case HW_VAR_PCIE_STOP_TX_DMA: + break; + */ + + /* + case HW_VAR_HCI_SUS_STATE: + break; + */ + + /* + case HW_VAR_NAV_UPPER: + case HW_VAR_RPT_TIMER_SETTING: + case HW_VAR_TX_RPT_MAX_MACID: + break; + */ + case HW_VAR_CHK_HI_QUEUE_EMPTY: + val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8821C); + *val = (val16 & BIT_HQQ_EMPTY_8821C) ? _TRUE : _FALSE; + break; + /* + case HW_VAR_AMPDU_MAX_TIME: + case HW_VAR_WIRELESS_MODE: + case HW_VAR_USB_MODE: + case HW_VAR_DO_IQK: + case HW_VAR_DM_IN_LPS: + case HW_VAR_SET_REQ_FW_PS: + case HW_VAR_FW_PS_STATE: + case HW_VAR_SOUNDING_ENTER: + case HW_VAR_SOUNDING_LEAVE: + case HW_VAR_SOUNDING_RATE: + case HW_VAR_SOUNDING_STATUS: + case HW_VAR_SOUNDING_FW_NDPA: + case HW_VAR_SOUNDING_CLK: + case HW_VAR_DL_RSVD_PAGE: + case HW_VAR_MACID_SLEEP: + case HW_VAR_MACID_WAKEUP: + break; + */ + case HW_VAR_DUMP_MAC_QUEUE_INFO: + dump_mac_qinfo(val, adapter); + break; + /* + case HW_VAR_ASIX_IOT: + case HW_VAR_H2C_BT_MP_OPER: + break; + */ + default: + GetHwReg(adapter, variable, val); + break; + } +} + +/* + * Description: + * Change default setting of specified variable. + */ +u8 rtl8821c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval) +{ + PHAL_DATA_TYPE hal; + u8 bResult; + + hal = GET_HAL_DATA(adapter); + bResult = _SUCCESS; + + switch (variable) { + /* + case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: + case HAL_DEF_IS_SUPPORT_ANT_DIV: + case HAL_DEF_DRVINFO_SZ: + case HAL_DEF_MAX_RECVBUF_SZ: + case HAL_DEF_RX_PACKET_OFFSET: + case HAL_DEF_RX_DMA_SZ_WOW: + case HAL_DEF_RX_DMA_SZ: + case HAL_DEF_RX_PAGE_SIZE: + case HAL_DEF_DBG_DUMP_RXPKT: + case HAL_DEF_RA_DECISION_RATE: + case HAL_DEF_RA_SGI: + case HAL_DEF_PT_PWR_STATUS: + case HW_VAR_MAX_RX_AMPDU_FACTOR: + case HW_DEF_RA_INFO_DUMP: + case HAL_DEF_DBG_DUMP_TXPKT: + case HAL_DEF_TX_PAGE_BOUNDARY: + case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN: + case HAL_DEF_ANT_DETECT: + case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR: + case HAL_DEF_PCI_AMD_L1_SUPPORT: + case HAL_DEF_PCI_ASPM_OSC: + case HAL_DEF_MACID_SLEEP: + case HAL_DEF_DBG_DIS_PWT: + case HAL_DEF_EFUSE_USAGE: + case HAL_DEF_EFUSE_BYTES: + case HW_VAR_BEST_AMPDU_DENSITY: + break; + */ + default: + bResult = SetHalDefVar(adapter, variable, pval); + break; + } + + return bResult; +} + +/* + * Description: + * Query setting of specified variable. + */ +u8 rtl8821c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval) +{ + PHAL_DATA_TYPE hal; + u8 bResult; + u8 val8 = 0; + + hal = GET_HAL_DATA(adapter); + bResult = _SUCCESS; + + switch (variable) { + /* + case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: + break; + */ + case HAL_DEF_IS_SUPPORT_ANT_DIV: + *(u8 *)pval = _FALSE; + break; + case HAL_DEF_MAX_RECVBUF_SZ: + *((u32 *)pval) = MAX_RECVBUF_SZ; + break; + case HAL_DEF_RX_PACKET_OFFSET: + rtw_halmac_get_drv_info_sz(adapter_to_dvobj(adapter), &val8); + *((u32 *)pval) = HALMAC_RX_DESC_SIZE_8821C + val8; + break; + /* + case HAL_DEF_DRVINFO_SZ: + rtw_halmac_get_drv_info_sz(adapter_to_dvobj(adapter), &val8); + *((u32 *)pval) = val8; + break; + case HAL_DEF_RX_DMA_SZ_WOW: + case HAL_DEF_RX_DMA_SZ: + case HAL_DEF_RX_PAGE_SIZE: + case HAL_DEF_DBG_DUMP_RXPKT: + case HAL_DEF_RA_DECISION_RATE: + case HAL_DEF_RA_SGI: + break; + */ + /* only for 8188E */ + case HAL_DEF_PT_PWR_STATUS: + break; + + case HAL_DEF_TX_LDPC: + *(u8 *)pval = ((hal->phy_spec.ldpc_cap >> 8) & 0xFF) ? _TRUE : _FALSE; + break; + + case HAL_DEF_RX_LDPC: + *(u8 *)pval = (hal->phy_spec.ldpc_cap & 0xFF) ? _TRUE : _FALSE; + break; + + case HAL_DEF_TX_STBC: + *(u8 *)pval = ((hal->phy_spec.stbc_cap >> 8) & 0xFF) ? _TRUE : _FALSE; + break; + + /* support 1RX for STBC */ + case HAL_DEF_RX_STBC: + *(u8 *)pval = hal->phy_spec.stbc_cap & 0xFF; + break; + + /* support Explicit TxBF for HT/VHT */ + case HAL_DEF_EXPLICIT_BEAMFORMER: + *(u8 *)pval = _FALSE; + break; + + case HAL_DEF_EXPLICIT_BEAMFORMEE: + *(u8 *)pval = _FALSE; + break; + /* + case HAL_DEF_BEAMFORMER_CAP: + case HAL_DEF_BEAMFORMEE_CAP: + break; + */ + + case HW_DEF_RA_INFO_DUMP: + break; + /* + case HAL_DEF_DBG_DUMP_TXPKT: + break; + */ + case HAL_DEF_TX_PAGE_SIZE: + *(u32 *)pval = HALMAC_TX_PAGE_SIZE_8821C; + break; + case HAL_DEF_TX_PAGE_BOUNDARY: + rtw_halmac_get_rsvd_drv_pg_bndy(adapter_to_dvobj(adapter), (u16 *)pval); + break; + /* case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN: + case HAL_DEF_ANT_DETECT: + case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR: + case HAL_DEF_PCI_AMD_L1_SUPPORT: + case HAL_DEF_PCI_ASPM_OSC: + break; + */ + case HAL_DEF_MACID_SLEEP: + *(u8 *)pval = _TRUE; /* support macid sleep */ + break; + /* + case HAL_DEF_DBG_DIS_PWT: + case HAL_DEF_EFUSE_USAGE: + case HAL_DEF_EFUSE_BYTES: + break; + */ + case HW_VAR_BEST_AMPDU_DENSITY: + *((u32 *)pval) = AMPDU_DENSITY_VALUE_4; + break; + + default: + bResult = GetHalDefVar(adapter, variable, pval); + break; + } + + return bResult; +} + +void rtl8821c_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc) +{ + if ((pattrib->encrypt > 0) && !pattrib->bswenc) { + /* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */ + switch (pattrib->encrypt) { + case _WEP40_: + case _WEP104_: + case _TKIP_: + case _TKIP_WTMIC_: + SET_TX_DESC_SEC_TYPE_8821C(ptxdesc, 0x1); + break; + case _AES_: + SET_TX_DESC_SEC_TYPE_8821C(ptxdesc, 0x3); + break; + case _NO_PRIVACY_: + default: + SET_TX_DESC_SEC_TYPE_8821C(ptxdesc, 0x0); + break; + } + } +} + +void rtl8821c_fill_txdesc_vcs(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pattrib->vcs_mode) { + switch (pattrib->vcs_mode) { + case RTS_CTS: + SET_TX_DESC_RTSEN_8821C(ptxdesc, 1); + break; + case CTS_TO_SELF: + SET_TX_DESC_CTS2SELF_8821C(ptxdesc, 1); + break; + case NONE_VCS: + default: + break; + } + + if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) + SET_TX_DESC_RTS_SHORT_8821C(ptxdesc, 1); + + SET_TX_DESC_RTSRATE_8821C(ptxdesc, 0x8);/* RTS Rate=24M */ + SET_TX_DESC_RTS_RTY_LOWEST_RATE_8821C(ptxdesc, 0xf); + } +} + +u8 rtl8821c_bw_mapping(PADAPTER adapter, struct pkt_attrib *pattrib) +{ + u8 BWSettingOfDesc = 0; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (hal->current_channel_bw == CHANNEL_WIDTH_80) { + if (pattrib->bwmode == CHANNEL_WIDTH_80) + BWSettingOfDesc = 2; + else if (pattrib->bwmode == CHANNEL_WIDTH_40) + BWSettingOfDesc = 1; + else + BWSettingOfDesc = 0; + } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) { + if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80)) + BWSettingOfDesc = 1; + else + BWSettingOfDesc = 0; + } else + BWSettingOfDesc = 0; + + return BWSettingOfDesc; +} + +u8 rtl8821c_sc_mapping(PADAPTER adapter, struct pkt_attrib *pattrib) +{ + u8 SCSettingOfDesc = 0; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (hal->current_channel_bw == CHANNEL_WIDTH_80) { + if (pattrib->bwmode == CHANNEL_WIDTH_80) + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + else if (pattrib->bwmode == CHANNEL_WIDTH_40) { + if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ; + else if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } else { + if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ; + else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; + else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } + } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) { + if (pattrib->bwmode == CHANNEL_WIDTH_40) + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + else if (pattrib->bwmode == CHANNEL_WIDTH_20) { + if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; + else if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + } + } else + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + + return SCSettingOfDesc; +} + +void rtl8821c_fill_txdesc_phy(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc) +{ + if (pattrib->ht_en) { + /* Set Bandwidth and sub-channel settings. */ + SET_TX_DESC_DATA_BW_8821C(ptxdesc, rtl8821c_bw_mapping(adapter, pattrib)); + SET_TX_DESC_DATA_SC_8821C(ptxdesc, rtl8821c_sc_mapping(adapter, pattrib)); + } +} + +void rtl8821c_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc) +{ + PHALMAC_ADAPTER halmac; + PHALMAC_API api; + + halmac = adapter_to_halmac(adapter); + api = HALMAC_GET_API(halmac); + + api->halmac_fill_txdesc_checksum(halmac, ptxdesc); +} + +void rtl8821c_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv) +{ + u8 *desc; + struct pkt_attrib *attrib; + u32 pkt_size; + s32 bmcast; + u8 data_rate, pwr_status, offset; + + desc = pmp_priv->tx.desc; + attrib = &pmp_priv->tx.attrib; + pkt_size = attrib->last_txcmdsz; + bmcast = IS_MCAST(attrib->ra); + + SET_TX_DESC_LS_8821C(desc, 1); + SET_TX_DESC_TXPKTSIZE_8821C(desc, pkt_size); + + offset = HALMAC_TX_DESC_SIZE_8821C; + SET_TX_DESC_OFFSET_8821C(desc, offset); + + SET_TX_DESC_PKT_OFFSET_8821C(desc, 0); /* Don't need to set PACKET Offset bit,it's no use 512bytes of length */ + + if (bmcast) + SET_TX_DESC_BMC_8821C(desc, 1); + + SET_TX_DESC_MACID_8821C(desc, attrib->mac_id); + SET_TX_DESC_RATE_ID_8821C(desc, attrib->raid); + SET_TX_DESC_QSEL_8821C(desc, attrib->qsel); + + if (pmp_priv->preamble) + SET_TX_DESC_DATA_SHORT_8821C(desc, 1); + + if (!attrib->qos_en) + SET_TX_DESC_EN_HWSEQ_8821C(desc, 1); + else + SET_TX_DESC_SW_SEQ_8821C(desc, attrib->seqnum); + + if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) + SET_TX_DESC_DATA_BW_8821C(desc, pmp_priv->bandwidth); + else { + RTW_INFO("%s: <ERROR> unknown bandwidth %d, use 20M\n", + __FUNCTION__, pmp_priv->bandwidth); + SET_TX_DESC_DATA_BW_8821C(desc, CHANNEL_WIDTH_20); + } + + SET_TX_DESC_DISDATAFB_8821C(desc, 1); + SET_TX_DESC_USE_RATE_8821C(desc, 1); + SET_TX_DESC_DATARATE_8821C(desc, pmp_priv->rateidx); +} + +#define OFFSET_SZ 0 +void rtl8821c_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc) +{ + u8 bDumpTxPkt; + u8 bDumpTxDesc = _FALSE; + + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_TXPKT, &bDumpTxPkt); + + /* 1 for data frame, 2 for mgnt frame */ + if (bDumpTxPkt == 1) { + RTW_INFO("dump tx_desc for data frame\n"); + if ((frame_tag & 0x0f) == DATA_FRAMETAG) + bDumpTxDesc = _TRUE; + } else if (bDumpTxPkt == 2) { + RTW_INFO("dump tx_desc for mgnt frame\n"); + if ((frame_tag & 0x0f) == MGNT_FRAMETAG) + bDumpTxDesc = _TRUE; + } + + /* 8821C TX SIZE = 48(HALMAC_TX_DESC_SIZE_8821C) */ + if (_TRUE == bDumpTxDesc) { + RTW_INFO("=====================================\n"); + RTW_INFO("Offset00(0x%08x)\n", *((u32 *)(ptxdesc))); + RTW_INFO("Offset04(0x%08x)\n", *((u32 *)(ptxdesc + 4))); + RTW_INFO("Offset08(0x%08x)\n", *((u32 *)(ptxdesc + 8))); + RTW_INFO("Offset12(0x%08x)\n", *((u32 *)(ptxdesc + 12))); + RTW_INFO("Offset16(0x%08x)\n", *((u32 *)(ptxdesc + 16))); + RTW_INFO("Offset20(0x%08x)\n", *((u32 *)(ptxdesc + 20))); + RTW_INFO("Offset24(0x%08x)\n", *((u32 *)(ptxdesc + 24))); + RTW_INFO("Offset28(0x%08x)\n", *((u32 *)(ptxdesc + 28))); + RTW_INFO("Offset32(0x%08x)\n", *((u32 *)(ptxdesc + 32))); + RTW_INFO("Offset36(0x%08x)\n", *((u32 *)(ptxdesc + 36))); + RTW_INFO("Offset40(0x%08x)\n", *((u32 *)(ptxdesc + 40))); + RTW_INFO("Offset44(0x%08x)\n", *((u32 *)(ptxdesc + 44))); + RTW_INFO("=====================================\n"); + } +} + +/* + * Description: + * In normal chip, we should send some packet to HW which will be used by FW + * in FW LPS mode. + * The function is to fill the Tx descriptor of this packets, + * then FW can tell HW to send these packet directly. + */ +static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + /* Clear all status */ + _rtw_memset(pDesc, 0, HALMAC_TX_DESC_SIZE_8821C); + + SET_TX_DESC_LS_8821C(pDesc, 1); + + SET_TX_DESC_OFFSET_8821C(pDesc, HALMAC_TX_DESC_SIZE_8821C); + + SET_TX_DESC_TXPKTSIZE_8821C(pDesc, BufferLen); + SET_TX_DESC_QSEL_8821C(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ + + if (pmlmeext->cur_wireless_mode & WIRELESS_11B) + SET_TX_DESC_RATE_ID_8821C(pDesc, RATEID_IDX_B); + else + SET_TX_DESC_RATE_ID_8821C(pDesc, RATEID_IDX_G); + + /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by HW */ + if (_TRUE == IsPsPoll) + SET_TX_DESC_NAVUSEHDR_8821C(pDesc, 1); + else { + SET_TX_DESC_DISQSELSEQ_8821C(pDesc, 1); + SET_TX_DESC_EN_HWSEQ_8821C(pDesc, 1); + SET_TX_DESC_HW_SSN_SEL_8821C(pDesc, 0);/*pattrib->hw_ssn_sel*/ + SET_TX_DESC_EN_HWEXSEQ_8821C(pDesc, 0); + } + + if (_TRUE == IsBTQosNull) + SET_TX_DESC_BT_NULL_8821C(pDesc, 1); + + SET_TX_DESC_USE_RATE_8821C(pDesc, 1); + SET_TX_DESC_DATARATE_8821C(pDesc, MRateToHwRate(pmlmeext->tx_rate)); + + /* + * Encrypt the data frame if under security mode excepct null data. + */ + if (_TRUE == bDataFrame) { + u32 EncAlg; + + EncAlg = adapter->securitypriv.dot11PrivacyAlgrthm; + switch (EncAlg) { + case _NO_PRIVACY_: + SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x0); + break; + case _WEP40_: + case _WEP104_: + case _TKIP_: + SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x1); + break; + case _SMS4_: + SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x2); + break; + case _AES_: + SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x3); + break; + default: + SET_TX_DESC_SEC_TYPE_8821C(pDesc, 0x0); + break; + } + } + SET_TX_DESC_PORT_ID_8821C(pDesc, get_hw_port(adapter)); + SET_TX_DESC_MULTIPLE_PORT_8821C(pDesc, get_hw_port(adapter)); + +} + +void rtl8821c_rxdesc2attribute(struct rx_pkt_attrib *pattrib, u8 *desc) +{ + _rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib)); + + pattrib->pkt_len = (u16)GET_RX_DESC_PKT_LEN_8821C(desc); + pattrib->crc_err = (u8)GET_RX_DESC_CRC32_8821C(desc); + pattrib->icv_err = (u8)GET_RX_DESC_ICV_ERR_8821C(desc); + + pattrib->drvinfo_sz = (u8)GET_RX_DESC_DRV_INFO_SIZE_8821C(desc) << 3; + pattrib->encrypt = (u8)GET_RX_DESC_SECURITY_8821C(desc); + pattrib->qos = (u8)GET_RX_DESC_QOS_8821C(desc); + pattrib->shift_sz = (u8)GET_RX_DESC_SHIFT_8821C(desc); + pattrib->physt = (u8)GET_RX_DESC_PHYST_8821C(desc); + pattrib->bdecrypted = (u8)GET_RX_DESC_SWDEC_8821C(desc) ? 0 : 1; + + pattrib->priority = (u8)GET_RX_DESC_TID_8821C(desc); + pattrib->amsdu = (u8)GET_RX_DESC_AMSDU_8821C(desc); + pattrib->mdata = (u8)GET_RX_DESC_MD_8821C(desc); + pattrib->mfrag = (u8)GET_RX_DESC_MF_8821C(desc); + + pattrib->seq_num = (u16)GET_RX_DESC_SEQ_8821C(desc); + pattrib->frag_num = (u8)GET_RX_DESC_FRAG_8821C(desc); + pattrib->ppdu_cnt = (u8)GET_RX_DESC_PPDU_CNT_8821C(desc); + + if (GET_RX_DESC_C2H_8821C(desc)) + pattrib->pkt_rpt_type = C2H_PACKET; + else + pattrib->pkt_rpt_type = NORMAL_RX; + + pattrib->data_rate = (u8)GET_RX_DESC_RX_RATE_8821C(desc); + +} + +void rtl8821c_query_rx_desc(union recv_frame *precvframe, u8 *pdesc) +{ + rtl8821c_rxdesc2attribute(&precvframe->u.hdr.attrib, pdesc); +} + +static void InitBeaconParameters(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + rtw_write16(adapter, REG_TBTT_PROHIBIT_8821C, 0x6404); /* ms */ + + rtw_write8(adapter, REG_DRVERLYINT_8821C, DRIVER_EARLY_INT_TIME_8821C); /* 5ms */ + rtw_write8(adapter, REG_BCNDMATIM_8821C, BCN_DMA_ATIME_INT_TIME_8821C); /* 2ms */ + + /* + * Suggested by designer timchen. Change beacon AIFS to the largest number + * beacause test chip does not contension before sending beacon. + */ + rtw_write16(adapter, REG_BCNTCFG_8821C, 0x660F); + + hal->RegBcnCtrlVal = rtw_read8(adapter, REG_BCN_CTRL_8821C); + hal->RegTxPause = rtw_read8(adapter, REG_TXPAUSE_8821C); + hal->RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2); + hal->RegReg542 = rtw_read8(adapter, REG_TBTT_PROHIBIT_8821C + 2); + hal->RegCR_1 = rtw_read8(adapter, REG_CR_8821C + 1); +} + +void rtl8821c_resume_tx_beacon(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + hal->RegFwHwTxQCtrl |= (BIT_EN_BCNQ_DL_8821C >> 16); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, hal->RegFwHwTxQCtrl); + + rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 1, 0xff); + hal->RegReg542 |= BIT(0); + rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 2, hal->RegReg542); +} + +void rtl8821c_stop_tx_beacon(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + hal->RegFwHwTxQCtrl &= ~(BIT_EN_BCNQ_DL_8821C >> 16); + rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8821C + 2, hal->RegFwHwTxQCtrl); + + rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 1, 0x64); + hal->RegReg542 &= ~BIT(0); + rtw_write8(adapter, REG_TBTT_PROHIBIT_8821C + 2, hal->RegReg542); +} + +static void beacon_function_enable(PADAPTER adapter, u8 Enable, u8 Linked) +{ + hw_bcn_ctrl_add(adapter, BIT_DIS_TSF_UDT_8821C | BIT_EN_BCN_FUNCTION_8821C); +} + +static void set_beacon_related_registers(PADAPTER adapter) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + + /* reset TSF, enable update TSF, correcting TSF On Beacon */ + + /* ATIM window */ + rtw_write16(adapter, REG_ATIMWND_8821C, 2); + + /* Beacon interval (in unit of TU). */ + hw_var_set_bcn_interval(adapter, pmlmeinfo->bcn_interval); + + InitBeaconParameters(adapter); + + rtw_write8(adapter, REG_SLOT_8821C, 0x09); + + /* Reset TSF Timer to zero */ + hw_tsf_reset(adapter); + + rtw_write8(adapter, REG_RXTSF_OFFSET_CCK_8821C, 0x50); + rtw_write8(adapter, REG_RXTSF_OFFSET_OFDM_8821C, 0x50); + + beacon_function_enable(adapter, _TRUE, _TRUE); + + rtl8821c_resume_tx_beacon(adapter); +} + +void rtl8821c_set_hal_ops(PADAPTER adapter) +{ + struct hal_ops *ops_func = &adapter->hal_func; + + /*** initialize section ***/ + ops_func->read_chip_version = read_chip_version; + ops_func->read_adapter_info = rtl8821c_read_efuse; + ops_func->hal_power_on = rtl8821c_power_on; + ops_func->hal_power_off = rtl8821c_power_off; + + ops_func->dm_init = rtl8821c_phy_init_dm_priv; + ops_func->dm_deinit = rtl8821c_phy_deinit_dm_priv; + + ops_func->check_ips_status = check_ips_status; + + /*** DM section ***/ + ops_func->set_chnl_bw_handler = rtl8821c_set_channel_bw; + + ops_func->set_tx_power_level_handler = rtl8821c_set_tx_power_level; + ops_func->get_tx_power_level_handler = rtl8821c_get_tx_power_level; + + ops_func->set_tx_power_index_handler = rtl8821c_set_tx_power_index; + ops_func->get_tx_power_index_handler = rtl8821c_get_tx_power_index; + + ops_func->hal_dm_watchdog = rtl8821c_phy_haldm_watchdog; + + ops_func->GetHalODMVarHandler = GetHalODMVar; + ops_func->SetHalODMVarHandler = SetHalODMVar; + + ops_func->update_ra_mask_handler = update_ra_mask_8821c; + ops_func->SetBeaconRelatedRegistersHandler = set_beacon_related_registers; + + /* + ops->interface_ps_func = NULL; + */ + + ops_func->read_bbreg = rtl8821c_read_bb_reg; + ops_func->write_bbreg = rtl8821c_write_bb_reg; + ops_func->read_rfreg = rtl8821c_read_rf_reg; + ops_func->write_rfreg = rtl8821c_write_rf_reg; + + /* + ops->EfusePowerSwitch = NULL; + ops->BTEfusePowerSwitch = NULL; + ops->ReadEFuse = NULL; + ops->EFUSEGetEfuseDefinition = NULL; + ops->EfuseGetCurrentSize = NULL; + ops->Efuse_PgPacketRead = NULL; + ops->Efuse_PgPacketWrite = NULL; + ops->Efuse_WordEnableDataWrite = NULL; + ops->Efuse_PgPacketWrite_BT = NULL; + */ + ops_func->sreset_init_value = sreset_init_value; + ops_func->sreset_reset_value = sreset_reset_value; + ops_func->silentreset = sreset_reset; + ops_func->sreset_xmit_status_check = xmit_status_check; + ops_func->sreset_linked_status_check = linked_status_check; + ops_func->sreset_get_wifi_status = sreset_get_wifi_status; + ops_func->sreset_inprogress = sreset_inprogress; + + + ops_func->hal_notch_filter = rtl8821c_notch_filter_switch; + ops_func->hal_mac_c2h_handler = c2h_handler_rtl8821c; + ops_func->fill_h2c_cmd = rtl8821c_fillh2ccmd; + ops_func->fill_fake_txdesc = fill_fake_txdesc; + ops_func->fw_dl = rtl8821c_fw_dl; + + + ops_func->hal_get_tx_buff_rsvd_page_num = get_txbuffer_rsvdpagenum; + + + ops_func->fw_correct_bcn = rtl8821c_fw_update_beacon_cmd; + + /* HALMAC related functions */ + ops_func->init_mac_register = rtl8821c_init_phy_parameter_mac; + ops_func->init_phy = rtl8821c_phy_init; + +} diff --git a/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c new file mode 100644 index 000000000000..e5a1bbd1d682 --- /dev/null +++ b/drivers/staging/rtl8821ce/hal/rtl8821c/rtl8821c_phy.c @@ -0,0 +1,968 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8821C_PHY_C_ + +#include <hal_data.h> /* HAL_DATA_TYPE */ +#include "../hal_halmac.h" /* REG_CCK_CHECK_8821C */ +#include "rtl8821c.h" + +/* + * Description: + * Initialize Register definition offset for Radio Path A/B/C/D + * The initialization value is constant and it should never be changes + */ +static void bb_rf_register_definition(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + /* RF Interface Sowrtware Control */ + hal->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; + hal->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; + + /* RF Interface Output (and Enable) */ + hal->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; + hal->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; + + /* RF Interface (Output and) Enable */ + hal->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; + hal->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; + + hal->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rA_LSSIWrite_Jaguar; + hal->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rB_LSSIWrite_Jaguar; + + hal->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rHSSIRead_Jaguar; + hal->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rHSSIRead_Jaguar; + + /* Tranceiver Readback LSSI/HSPI mode */ + hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rA_SIRead_Jaguar; + hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rB_SIRead_Jaguar; + hal->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = rA_PIRead_Jaguar; + hal->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = rB_PIRead_Jaguar; +} + +static void init_bb_rf(PADAPTER adapter) +{ + u8 val8; + u16 val16; + + /* Enable BB and RF */ + val8 = rtw_read8(adapter, REG_SYS_FUNC_EN_8821C); + if (IS_HARDWARE_TYPE_8821CU(adapter)) + val8 |= BIT_FEN_USBA_8821C; + else if (IS_HARDWARE_TYPE_8821CE(adapter)) + val8 |= BIT_FEN_PCIEA_8821C; + rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8); + + /* + * 8821C MP Chip => Reset BB/RF ?? + * Need to set BBRSTB and GLB_RSTB = 1->0->1 to generate a postive edge and negtive edge for BB + */ + val8 |= BIT_FEN_BB_GLB_RSTN_8821C | BIT_FEN_BBRSTB_8821C; + rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8); + val8 &= ~(BIT_FEN_BB_GLB_RSTN_8821C | BIT_FEN_BBRSTB_8821C); + rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8); + val8 |= BIT_FEN_BB_GLB_RSTN_8821C | BIT_FEN_BBRSTB_8821C; + rtw_write8(adapter, REG_SYS_FUNC_EN_8821C, val8); + + val8 = BIT_RF_EN_8821C | BIT_RF_RSTB_8821C | BIT_RF_SDMRSTB_8821C; + /* 0x1F[7:0] = 0x07 PathA RF Power On */ + rtw_write8(adapter, REG_RF_CTRL_8821C, val8); + rtw_usleep_os(10); + + /*0xEC [31:24],BIT_WLRF1_CTRL, For WLRF1 control*/ + /* 0xEF[7:0] = 0x07 for RFE Type=2,BTG RF Power On*/ + rtw_write8(adapter, REG_WLRF1_8821C + 3, val8); + rtw_usleep_os(10); + +} + +u8 rtl8821c_init_phy_parameter_mac(PADAPTER adapter) +{ + u8 ret = _FAIL; + PHAL_DATA_TYPE hal; + + hal = GET_HAL_DATA(adapter); + + ret = phy_ConfigMACWithParaFile(adapter, PHY_FILE_MAC_REG); + if (ret == _FAIL) + { + odm_config_mac_with_header_file(&hal->odmpriv); + ret = _SUCCESS; + } + + return ret; +} + +static u8 _init_phy_parameter_bb(PADAPTER Adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter); + u8 ret = _TRUE; + int res; + enum hal_status status; + + /* + * 1. Read PHY_REG.TXT BB INIT!! + */ + res = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG); + if (res == _FAIL) + { + ret = _FALSE; + status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_PHY_REG); + if (HAL_STATUS_SUCCESS == status) + ret = _TRUE; + } + + if (ret != _TRUE) { + RTW_INFO("%s: Write BB Reg Fail!!", __FUNCTION__); + goto exit; + } + + /* + * 2. Read BB AGC table Initialization + */ + res = phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB); + if (res == _FAIL) + { + ret = _FALSE; + status = odm_config_bb_with_header_file(&hal->odmpriv, CONFIG_BB_AGC_TAB); + if (HAL_STATUS_SUCCESS == status) + ret = _TRUE; + } + + if (ret != _TRUE) { + RTW_INFO("%s: AGC Table Fail\n", __FUNCTION__); + goto exit; + } + +exit: + return ret; +} + +static u8 init_bb_reg(PADAPTER adapter) +{ + u8 ret = _TRUE; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + /* + * Config BB and AGC + */ + ret = _init_phy_parameter_bb(adapter); + + hal_set_crystal_cap(adapter, hal->crystal_cap); + + phy_set_bb_reg(adapter, rCCK0_FalseAlarmReport + 2, BIT2 | BIT6, 0); + return ret; +} + +static u8 _init_phy_parameter_rf(PADAPTER adapter) +{ + u32 val32 = 0; + u8 eRFPath; + PBB_REGISTER_DEFINITION_T pPhyReg; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + enum hal_status status; + int res; + u8 ret = _TRUE; + + /* + * Initialize RF + */ + for (eRFPath = 0; eRFPath < hal->NumTotalRFPath; eRFPath++) { + pPhyReg = &hal->PHYRegDef[eRFPath]; + + /* Initialize RF from configuration file */ + switch (eRFPath) { + case RF_PATH_A: + res = PHY_ConfigRFWithParaFile(adapter, PHY_FILE_RADIO_A, eRFPath); + if (res == _FAIL) + { + ret = _FALSE; + status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, (enum odm_rf_radio_path_e)eRFPath); + if (HAL_STATUS_SUCCESS == status) + ret = _TRUE; + } + break; + case RF_PATH_B: + res = PHY_ConfigRFWithParaFile(adapter, PHY_FILE_RADIO_B, eRFPath); + if (res == _FAIL) + { + ret = _FALSE; + status = odm_config_rf_with_header_file(&hal->odmpriv, CONFIG_RF_RADIO, (enum odm_rf_radio_path_e)eRFPath); + if (HAL_STATUS_SUCCESS == status) + ret = _TRUE; + } + break; + case RF_PATH_C: + break; + case RF_PATH_D: + break; + } + + if (ret != _TRUE) + goto exit; + } + + /* + * Configuration of Tx Power Tracking + */ + res = PHY_ConfigRFWithTxPwrTrackParaFile(adapter, PHY_FILE_TXPWR_TRACK); + if (res == _FAIL) + { + ret = _FALSE; + status = odm_config_rf_with_tx_pwr_track_header_file(&hal->odmpriv); + if (HAL_STATUS_SUCCESS == status) + ret = _TRUE; + } + if (ret != _TRUE) + goto exit; + +exit: + return ret; +} + +static u8 init_rf_reg(PADAPTER adapter) +{ + u8 ret = _TRUE; + + ret = _init_phy_parameter_rf(adapter); + + return ret; +} +u8 rtl8821c_phy_init(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + struct PHY_DM_STRUCT *phydm; + + hal = GET_HAL_DATA(adapter); + phydm = &hal->odmpriv; + + bb_rf_register_definition(adapter); + + init_bb_rf(adapter); + + if (_FALSE == config_phydm_parameter_init_8821c(phydm, ODM_PRE_SETTING)) + return _FALSE; + + if (_FALSE == init_bb_reg(adapter)) + return _FALSE; + + if (_FALSE == init_rf_reg(adapter)) + return _FALSE; + + if (_FALSE == config_phydm_parameter_init_8821c(phydm, ODM_POST_SETTING)) + return _FALSE; + + hal->phy_spec.trx_cap = query_phydm_trx_capability(phydm); + hal->phy_spec.stbc_cap = query_phydm_stbc_capability(phydm); + hal->phy_spec.ldpc_cap = query_phydm_ldpc_capability(phydm); + hal->phy_spec.txbf_param = query_phydm_txbf_parameters(phydm); + hal->phy_spec.txbf_cap = query_phydm_txbf_capability(phydm); + /*rtw_dump_phy_cap(RTW_DBGDUMP, adapter);*/ + return _TRUE; +} + +static u32 phy_calculatebitshift(u32 mask) +{ + u32 i; + + for (i = 0; i <= 31; i++) + if (mask & BIT(i)) + break; + + return i; +} + +u32 rtl8821c_read_bb_reg(PADAPTER adapter, u32 addr, u32 mask) +{ + u32 val = 0, val_org, shift; + + + val_org = rtw_read32(adapter, addr); + shift = phy_calculatebitshift(mask); + val = (val_org & mask) >> shift; + + return val; +} + +void rtl8821c_write_bb_reg(PADAPTER adapter, u32 addr, u32 mask, u32 val) +{ + u32 val_org, shift; + + + if (mask != 0xFFFFFFFF) { + /* not "double word" write */ + val_org = rtw_read32(adapter, addr); + shift = phy_calculatebitshift(mask); + val = ((val_org & (~mask)) | ((val << shift) & mask)); + } + + rtw_write32(adapter, addr, val); +} + +u32 rtl8821c_read_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask) +{ + PHAL_DATA_TYPE hal; + struct PHY_DM_STRUCT *phydm; + u32 val = 0; + + hal = GET_HAL_DATA(adapter); + phydm = &hal->odmpriv; + + val = config_phydm_read_rf_reg_8821c(phydm, path, addr, mask); + if (!config_phydm_read_rf_check_8821c(val)) + RTW_INFO(FUNC_ADPT_FMT ": read RF reg path=%d addr=0x%x mask=0x%x FAIL!\n", + FUNC_ADPT_ARG(adapter), path, addr, mask); + return val; +} + +void rtl8821c_write_rf_reg(PADAPTER adapter, u8 path, u32 addr, u32 mask, u32 val) +{ + PHAL_DATA_TYPE hal; + struct PHY_DM_STRUCT *phydm; + u8 ret; + + hal = GET_HAL_DATA(adapter); + phydm = &hal->odmpriv; + + ret = config_phydm_write_rf_reg_8821c(phydm, path, addr, mask, val); + if (_FALSE == ret) + RTW_INFO(FUNC_ADPT_FMT ": write RF reg path=%d addr=0x%x mask=0x%x val=0x%x FAIL!\n", + FUNC_ADPT_ARG(adapter), path, addr, mask, val); + +} + +void rtl8821c_set_tx_power_level(PADAPTER adapter, u8 channel) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u8 path = ODM_RF_PATH_A; + struct PHY_DM_STRUCT *phydm = &hal->odmpriv; + struct _FAST_ANTENNA_TRAINNING_ *pDM_FatTable = &phydm->dm_fat_table; + + /*((hal->RFEType == 2) || (hal->RFEType == 4) || (hal->RFEType == 7))*/ + if ((channel <= 14) && (SWITCH_TO_BTG == query_phydm_default_rf_set_8821c(phydm))) + path = ODM_RF_PATH_B; + + /*if (adapter->registrypriv.mp_mode == 1)*/ + + phy_set_tx_power_index_by_rate_section(adapter, path, channel, CCK); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, OFDM); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, HT_MCS0_MCS7); + phy_set_tx_power_index_by_rate_section(adapter, path, channel, VHT_1SSMCS0_1SSMCS9); +} + +void rtl8821c_get_tx_power_level(PADAPTER adapter, s32 *power) +{ +} + +/* + * Parameters: + * padatper + * powerindex power index for rate + * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" + * rate data rate, type "enum MGN_RATE" + */ +void rtl8821c_set_tx_power_index(PADAPTER adapter, u32 powerindex, u8 rfpath, u8 rate) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *phydm = &hal->odmpriv; + u8 shift = 0; + u8 hw_rate_idx; + static u32 index = 0; + + /*hw_rate_idx = PHY_GetRateIndexOfTxPowerByRate(rate);*/ + hw_rate_idx = MRateToHwRate(rate); + + if (hw_rate_idx > DESC_RATEVHTSS1MCS9) { + RTW_ERR(FUNC_ADPT_FMT"warn rate(%s)\n", FUNC_ADPT_ARG(adapter), HDATA_RATE(hw_rate_idx)); + rtw_warn_on(1); + } + + if (rfpath > ODM_RF_PATH_A) { + rfpath = ODM_RF_PATH_A; + } + /* + * For 8821C, phydm api use 4 bytes txagc value + * driver must combine every four 1 byte to one 4 byte and send to phydm api + */ + shift = hw_rate_idx % 4; + index |= ((powerindex & 0xff) << (shift * 8)); + + if (shift == 3) { + hw_rate_idx = hw_rate_idx - 3; + + if (!config_phydm_write_txagc_8821c(phydm, index, rfpath, hw_rate_idx)) { + RTW_ERR(FUNC_ADPT_FMT" (power index:0x%02x, rfpath:%d, rate:0x%02x, disable api:%d) wite TX-AGC failed\n", + FUNC_ADPT_ARG(adapter), index, rfpath, hw_rate_idx, phydm->is_disable_phy_api); + + rtw_warn_on(1); + } + index = 0; + } + if (MGN_VHT1SS_MCS9 == rate) { + if (!config_phydm_write_txagc_8821c(phydm, index, rfpath, MRateToHwRate(MGN_VHT1SS_MCS8))) { + RTW_ERR(FUNC_ADPT_FMT" (power index:0x%02x, rfpath:%d, rate:0x%02x, disable api:%d) wite TX-AGC failed\n", + FUNC_ADPT_ARG(adapter), index, rfpath, hw_rate_idx, phydm->is_disable_phy_api); + + rtw_warn_on(1); + } + index = 0; + } + +} + +static u8 rtl8821c_phy_get_current_tx_num(PADAPTER adapter, u8 rate) +{ + u8 tx_num = 0; + + if ((rate >= MGN_MCS8 && rate <= MGN_MCS15) || + (rate >= MGN_VHT2SS_MCS0 && rate <= MGN_VHT2SS_MCS9)) + tx_num = RF_2TX; + else + tx_num = RF_1TX; + + return tx_num; +} + +/* + * Parameters: + * padatper + * rfpath Antenna(RF) path, type "enum odm_rf_radio_path_e" + * rate data rate, type "enum MGN_RATE" + * bandwidth Bandwidth, type "enum _CHANNEL_WIDTH" + * channel Channel number + * + * Rteurn: + * tx_power power index for rate + */ +u8 rtl8821c_get_tx_power_index(PADAPTER adapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + u8 base_idx = 0, power_idx = 0; + s8 by_rate_diff = 0, limit = 0, tpt_offset = 0, extra_bias = 0; + u8 tx_num = rtl8821c_phy_get_current_tx_num(adapter, rate); + u8 bIn24G = _FALSE; + + base_idx = PHY_GetTxPowerIndexBase(adapter, rfpath, rate, bandwidth, channel, &bIn24G); + + by_rate_diff = PHY_GetTxPowerByRate(adapter, (u8)(!bIn24G), rfpath, tx_num, rate); + limit = PHY_GetTxPowerLimit(adapter, adapter->registrypriv.RegPwrTblSel, (BAND_TYPE)(!bIn24G), + hal->current_channel_bw, rfpath, rate, hal->current_channel); + + /* tpt_offset += PHY_GetTxPowerTrackingOffset(adapter, rfpath, rate); */ + + if (tic) { + tic->base = base_idx; + tic->by_rate = by_rate_diff; + tic->limit = limit; + tic->tpt = tpt_offset; + tic->ebias = extra_bias; + } + + by_rate_diff = by_rate_diff > limit ? limit : by_rate_diff; + power_idx = base_idx + by_rate_diff + tpt_offset + extra_bias; + + if (power_idx > MAX_POWER_INDEX) + power_idx = MAX_POWER_INDEX; + + return power_idx; +} + +/* + * Description: + * Check need to switch band or not + * Parameters: + * channelToSW channel wiii be switch to + * Return: + * _TRUE need to switch band + * _FALSE not need to switch band + */ +static u8 need_switch_band(PADAPTER adapter, u8 channelToSW) +{ + u8 u1tmp = 0; + u8 ret_value = _TRUE; + u8 Band = BAND_ON_5G, BandToSW = BAND_ON_5G; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + Band = hal->current_band_type; + + /* Use current swich channel to judge Band Type and switch Band if need */ + if (channelToSW > 14) + BandToSW = BAND_ON_5G; + else + BandToSW = BAND_ON_2_4G; + + if (BandToSW != Band) { + /* record current band type for other hal use */ + hal->current_band_type = (BAND_TYPE)BandToSW; + ret_value = _TRUE; + } else + ret_value = _FALSE; + + return ret_value; +} + +static u8 get_pri_ch_id(PADAPTER adapter) +{ + u8 pri_ch_idx = 0; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + + if (hal->current_channel_bw == CHANNEL_WIDTH_80) { + /* primary channel is at lower subband of 80MHz & 40MHz */ + if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + pri_ch_idx = VHT_DATA_SC_20_LOWEST_OF_80MHZ; + /* primary channel is at lower subband of 80MHz & upper subband of 40MHz */ + else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ; + /* primary channel is at upper subband of 80MHz & lower subband of 40MHz */ + else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ; + /* primary channel is at upper subband of 80MHz & upper subband of 40MHz */ + else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + pri_ch_idx = VHT_DATA_SC_20_UPPERST_OF_80MHZ; + else { + if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + pri_ch_idx = VHT_DATA_SC_40_LOWER_OF_80MHZ; + else if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + pri_ch_idx = VHT_DATA_SC_40_UPPER_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } + } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) { + /* primary channel is at upper subband of 40MHz */ + if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + pri_ch_idx = VHT_DATA_SC_20_UPPER_OF_80MHZ; + /* primary channel is at lower subband of 40MHz */ + else if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + pri_ch_idx = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else + RTW_INFO("SCMapping: DONOT CARE Mode Setting\n"); + } + + return pri_ch_idx; +} + +static void mac_switch_bandwidth(PADAPTER adapter, u8 pri_ch_idx) +{ + u8 channel = 0, bw = 0; + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + int err; + + channel = hal->current_channel; + bw = hal->current_channel_bw; + err = rtw_halmac_set_bandwidth(adapter_to_dvobj(adapter), channel, pri_ch_idx, bw); + if (err) { + RTW_INFO(FUNC_ADPT_FMT ": (channel=%d, pri_ch_idx=%d, bw=%d) fail\n", + FUNC_ADPT_ARG(adapter), channel, pri_ch_idx, bw); + } +} +u32 phy_get_tx_bbswing_8812c(_adapter *adapter, BAND_TYPE band, u8 rf_path) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + s8 bbSwing_2G = -1 * GetRegTxBBSwing_2G(adapter); + s8 bbSwing_5G = -1 * GetRegTxBBSwing_5G(adapter); + u32 out = 0x200; + const s8 AUTO = -1; + + if (pHalData->bautoload_fail_flag) { + if (band == BAND_ON_2_4G) { + pRFCalibrateInfo->bb_swing_diff_2g = bbSwing_2G; + if (bbSwing_2G == 0) + out = 0x200; /* 0 dB */ + else if (bbSwing_2G == -3) + out = 0x16A; /* -3 dB */ + else if (bbSwing_2G == -6) + out = 0x101; /* -6 dB */ + else if (bbSwing_2G == -9) + out = 0x0B6; /* -9 dB */ + else { + if (pHalData->ExternalPA_2G) { + pRFCalibrateInfo->bb_swing_diff_2g = -3; + out = 0x16A; + } else { + pRFCalibrateInfo->bb_swing_diff_2g = 0; + out = 0x200; + } + } + } else if (band == BAND_ON_5G) { + pRFCalibrateInfo->bb_swing_diff_5g = bbSwing_5G; + if (bbSwing_5G == 0) + out = 0x200; /* 0 dB */ + else if (bbSwing_5G == -3) + out = 0x16A; /* -3 dB */ + else if (bbSwing_5G == -6) + out = 0x101; /* -6 dB */ + else if (bbSwing_5G == -9) + out = 0x0B6; /* -9 dB */ + else { + if (pHalData->external_pa_5g) { + pRFCalibrateInfo->bb_swing_diff_5g = -3; + out = 0x16A; + } else { + pRFCalibrateInfo->bb_swing_diff_5g = 0; + out = 0x200; + } + } + } else { + pRFCalibrateInfo->bb_swing_diff_2g = -3; + pRFCalibrateInfo->bb_swing_diff_5g = -3; + out = 0x16A; /* -3 dB */ + } + } else { + u32 swing = 0, onePathSwing = 0; + + if (band == BAND_ON_2_4G) { + if (GetRegTxBBSwing_2G(adapter) == AUTO) + swing = pHalData->tx_bbswing_24G; + else if (bbSwing_2G == 0) + swing = 0x00; /* 0 dB */ + else if (bbSwing_2G == -3) + swing = 0x55; /* -3 dB */ + else if (bbSwing_2G == -6) + swing = 0xAA; /* -6 dB */ + else if (bbSwing_2G == -9) + swing = 0xFF; /* -9 dB */ + else + swing = 0x00; + } else { + if (GetRegTxBBSwing_5G(adapter) == AUTO) + swing = pHalData->tx_bbswing_5G; + else if (bbSwing_5G == 0) + swing = 0x00; /* 0 dB */ + else if (bbSwing_5G == -3) + swing = 0x55; /* -3 dB */ + else if (bbSwing_5G == -6) + swing = 0xAA; /* -6 dB */ + else if (bbSwing_5G == -9) + swing = 0xFF; /* -9 dB */ + else + swing = 0x00; + } + + if (rf_path == ODM_RF_PATH_A) + onePathSwing = (swing & 0x3) >> 0; /* 0xC6/C7[1:0] */ + + if (onePathSwing == 0x0) { + if (band == BAND_ON_2_4G) + pRFCalibrateInfo->bb_swing_diff_2g = 0; + else + pRFCalibrateInfo->bb_swing_diff_5g = 0; + out = 0x200; /* 0 dB */ + } else if (onePathSwing == 0x1) { + if (band == BAND_ON_2_4G) + pRFCalibrateInfo->bb_swing_diff_2g = -3; + else + pRFCalibrateInfo->bb_swing_diff_5g = -3; + out = 0x16A; /* -3 dB */ + } else if (onePathSwing == 0x2) { + if (band == BAND_ON_2_4G) + pRFCalibrateInfo->bb_swing_diff_2g = -6; + else + pRFCalibrateInfo->bb_swing_diff_5g = -6; + out = 0x101; /* -6 dB */ + } else if (onePathSwing == 0x3) { + if (band == BAND_ON_2_4G) + pRFCalibrateInfo->bb_swing_diff_2g = -9; + else + pRFCalibrateInfo->bb_swing_diff_5g = -9; + out = 0x0B6; /* -9 dB */ + } + } + + /* RTW_INFO("<=== PHY_GetTxBBSwing_8812C, out = 0x%X\n", out); */ + + return out; +} + +void phy_set_bb_swing_by_band_8812c(_adapter *adapter, u8 band, u8 previous_band) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + s8 BBDiffBetweenBand = 0; + struct PHY_DM_STRUCT *pDM_Odm = &pHalData->odmpriv; + struct odm_rf_calibration_structure *pRFCalibrateInfo = &(pDM_Odm->rf_calibrate_info); + + phy_set_bb_reg(adapter, rA_TxScale_Jaguar, 0xFFE00000, + phy_get_tx_bbswing_8812c(adapter, (BAND_TYPE)band, ODM_RF_PATH_A)); /* 0xC1C[31:21] */ + + /* When TxPowerTrack is ON, we should take care of the change of BB swing. */ + /* That is, reset all info to trigger Tx power tracking. */ + { + + if (band != previous_band) { + BBDiffBetweenBand = (pRFCalibrateInfo->bb_swing_diff_2g - pRFCalibrateInfo->bb_swing_diff_5g); + BBDiffBetweenBand = (band == BAND_ON_2_4G) ? BBDiffBetweenBand : (-1 * BBDiffBetweenBand); + pRFCalibrateInfo->default_ofdm_index += BBDiffBetweenBand * 2; + } + + odm_clear_txpowertracking_state(pDM_Odm); + } + +} + +void phy_switch_wireless_band_8821c(_adapter *adapter) +{ + u8 ret = 0; + PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &hal_data->odmpriv; + u8 current_band = hal_data->current_band_type; + + if (need_switch_band(adapter, hal_data->current_channel) == _TRUE) { + if (hal_data->EEPROMBluetoothCoexist) { + struct mlme_ext_priv *mlmeext; + + /* switch band under site survey or not, must notify to BT COEX */ + mlmeext = &adapter->mlmeextpriv; + if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE) + rtw_btcoex_switchband_notify(_TRUE, hal_data->current_band_type); + else + rtw_btcoex_switchband_notify(_FALSE, hal_data->current_band_type); + } else + rtw_btcoex_wifionly_switchband_notify(adapter); + + /* hal->current_channel is center channel of pmlmeext->cur_channel(primary channel) */ + ret = config_phydm_switch_band_8821c(pDM_Odm, hal_data->current_channel); + + if (!ret) { + RTW_ERR("%s: config_phydm_switch_band_8821c fail\n", __func__); + rtw_warn_on(1); + return; + } + phy_set_bb_swing_by_band_8812c(adapter, hal_data->current_band_type, current_band); + } +} + +/* + * Description: + * Set channel & bandwidth & offset + */ +void rtl8821c_switch_chnl_and_set_bw(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter); + struct PHY_DM_STRUCT *pDM_Odm = &hal->odmpriv; + u8 center_ch = 0, ret = 0; + + if (adapter->bNotifyChannelChange) { + RTW_INFO("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", + __FUNCTION__, + hal->bSwChnl, + hal->current_channel, + hal->bSetChnlBW, + hal->current_channel_bw); + } + + if (RTW_CANNOT_RUN(adapter)) { + hal->bSwChnlAndSetBWInProgress = _FALSE; + return; + } + + /* set channel & Bandwidth register */ + /* 1. set switch band register if need to switch band */ + phy_switch_wireless_band_8821c(adapter); + + /* 2. set channel register */ + if (hal->bSwChnl) { + ret = config_phydm_switch_channel_8821c(pDM_Odm, hal->current_channel); + hal->bSwChnl = _FALSE; + + if (!ret) { + RTW_INFO("%s: config_phydm_switch_channel_8821c fail\n", __FUNCTION__); + rtw_warn_on(1); + return; + } + } + phydm_config_kfree(pDM_Odm, hal->current_channel); + + /* 3. set Bandwidth register */ + if (hal->bSetChnlBW) { + /* get primary channel index */ + u8 pri_ch_idx = get_pri_ch_id(adapter); + + /* 3.1 set MAC register */ + mac_switch_bandwidth(adapter, pri_ch_idx); + + /* 3.2 set BB/RF registet */ + ret = config_phydm_switch_bandwidth_8821c(pDM_Odm, pri_ch_idx, hal->current_channel_bw); + hal->bSetChnlBW = _FALSE; + + if (!ret) { + RTW_INFO("%s: config_phydm_switch_bandwidth_8821c fail\n", __FUNCTION__); + rtw_warn_on(1); + return; + } + } + + /* TX Power Setting */ + /* odm_clear_txpowertracking_state(pDM_Odm); */ + rtw_hal_set_tx_power_level(adapter, hal->current_channel); + + /* IQK */ + if ((hal->bNeedIQK == _TRUE) + || (adapter->registrypriv.mp_mode == 1)) { + #ifdef CONFIG_IQK_MONITOR + u32 iqk_start_time = rtw_get_current_time(); + #endif + + phy_iq_calibrate_8821c(pDM_Odm, _FALSE); + + #ifdef CONFIG_IQK_MONITOR + RTW_INFO(ADPT_FMT" switch CH(%d) DO IQK : %d ms\n", + ADPT_ARG(adapter), hal->current_channel, rtw_get_passing_time_ms(iqk_start_time)); + #endif + hal->bNeedIQK = _FALSE; + } +} + +/* + * Description: + * Store channel setting to hal date + * Parameters: + * bSwitchChannel swith channel or not + * bSetBandWidth set band or not + * ChannelNum center channel + * ChnlWidth bandwidth + * ChnlOffsetOf40MHz channel offset for 40MHz Bandwidth + * ChnlOffsetOf80MHz channel offset for 80MHz Bandwidth + * CenterFrequencyIndex1 center channel index + */ + +void rtl8821c_handle_sw_chnl_and_set_bw( + PADAPTER Adapter, u8 bSwitchChannel, u8 bSetBandWidth, + u8 ChannelNum, CHANNEL_WIDTH ChnlWidth, u8 ChnlOffsetOf40MHz, + u8 ChnlOffsetOf80MHz, u8 CenterFrequencyIndex1) +{ + PHAL_DATA_TYPE hal = GET_HAL_DATA(Adapter); + u8 tmpChannel = hal->current_channel; + CHANNEL_WIDTH tmpBW = hal->current_channel_bw; + u8 tmpnCur40MhzPrimeSC = hal->nCur40MhzPrimeSC; + u8 tmpnCur80MhzPrimeSC = hal->nCur80MhzPrimeSC; + u8 tmpCenterFrequencyIndex1 = hal->CurrentCenterFrequencyIndex1; + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + + /* check swchnl or setbw */ + if (!bSwitchChannel && !bSetBandWidth) { + RTW_INFO("%s: not switch channel and not set bandwidth\n", __FUNCTION__); + return; + } + + /* skip switch channel operation for current channel & ChannelNum(will be switch) are the same */ + if (bSwitchChannel) { + if (hal->current_channel != ChannelNum) { + if (HAL_IsLegalChannel(Adapter, ChannelNum)) + hal->bSwChnl = _TRUE; + else + return; + } + } + + /* check set BandWidth */ + if (bSetBandWidth) { + /* initial channel bw setting */ + if (hal->bChnlBWInitialized == _FALSE) { + hal->bChnlBWInitialized = _TRUE; + hal->bSetChnlBW = _TRUE; + } else if ((hal->current_channel_bw != ChnlWidth) || /* check whether need set band or not */ + (hal->nCur40MhzPrimeSC != ChnlOffsetOf40MHz) || + (hal->nCur80MhzPrimeSC != ChnlOffsetOf80MHz) || + (hal->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1)) + hal->bSetChnlBW = _TRUE; + } + + /* return if not need set bandwidth nor channel after check*/ + if (!hal->bSetChnlBW && !hal->bSwChnl && hal->bNeedIQK != _TRUE) + return; + + /* set channel number to hal data */ + if (hal->bSwChnl) { + hal->current_channel = ChannelNum; + hal->CurrentCenterFrequencyIndex1 = ChannelNum; + } + + /* set bandwidth info to hal data */ + if (hal->bSetChnlBW) { + hal->current_channel_bw = ChnlWidth; + hal->nCur40MhzPrimeSC = ChnlOffsetOf40MHz; + hal->nCur80MhzPrimeSC = ChnlOffsetOf80MHz; + hal->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1; + } + + /* switch channel & bandwidth */ + if (!RTW_CANNOT_RUN(Adapter)) + rtl8821c_switch_chnl_and_set_bw(Adapter); + else { + if (hal->bSwChnl) { + hal->current_channel = tmpChannel; + hal->CurrentCenterFrequencyIndex1 = tmpChannel; + } + + if (hal->bSetChnlBW) { + hal->current_channel_bw = tmpBW; + hal->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC; + hal->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC; + hal->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1; + } + } +} + +/* + * Description: + * Change channel, bandwidth & offset + * Parameters: + * center_ch center channel + * bw bandwidth + * offset40 channel offset for 40MHz Bandwidth + * offset80 channel offset for 80MHz Bandwidth + */ +void rtl8821c_set_channel_bw(PADAPTER adapter, u8 center_ch, CHANNEL_WIDTH bw, u8 offset40, u8 offset80) +{ + rtl8821c_handle_sw_chnl_and_set_bw(adapter, _TRUE, _TRUE, center_ch, bw, offset40, offset80, center_ch); +} + +void rtl8821c_notch_filter_switch(PADAPTER adapter, bool enable) +{ + if (enable) + RTW_INFO("%s: Enable notch filter\n", __FUNCTION__); + else + RTW_INFO("%s: Disable notch filter\n", __FUNCTION__); +} + +/* + * Description: + * Config RF path + * + * Parameters: + * adapter pointer of struct _ADAPTER + */ +void rtl8821c_mp_config_rfpath(PADAPTER adapter) +{ + PHAL_DATA_TYPE hal; + PMPT_CONTEXT mpt; + ANTENNA_PATH anttx, antrx; + enum odm_rf_path_e rxant; + + hal = GET_HAL_DATA(adapter); + mpt = &adapter->mppriv.mpt_ctx; + anttx = hal->antenna_tx_path; + antrx = hal->AntennaRxPath; + RTW_INFO("+Config RF Path, tx=0x%x rx=0x%x\n", anttx, antrx); + RTW_INFO("-Config RF Path Finish\n"); +} + diff --git a/drivers/staging/rtl8821ce/include/HalPwrSeqCmd.h b/drivers/staging/rtl8821ce/include/HalPwrSeqCmd.h new file mode 100644 index 000000000000..60240265e11b --- /dev/null +++ b/drivers/staging/rtl8821ce/include/HalPwrSeqCmd.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HALPWRSEQCMD_H__ +#define __HALPWRSEQCMD_H__ + +#include <drv_types.h> + +/*---------------------------------------------*/ +/* 3 The value of cmd: 4 bits + *---------------------------------------------*/ +#define PWR_CMD_READ 0x00 +/* offset: the read register offset + * msk: the mask of the read value + * value: N/A, left by 0 + * note: dirver shall implement this function by read & msk */ + +#define PWR_CMD_WRITE 0x01 +/* offset: the read register offset + * msk: the mask of the write bits + * value: write value + * note: driver shall implement this cmd by read & msk after write */ + +#define PWR_CMD_POLLING 0x02 +/* offset: the read register offset + * msk: the mask of the polled value + * value: the value to be polled, masked by the msd field. + * note: driver shall implement this cmd by + * do { + * if( (Read(offset) & msk) == (value & msk) ) + * break; + * } while(not timeout); */ + +#define PWR_CMD_DELAY 0x03 +/* offset: the value to delay + * msk: N/A + * value: the unit of delay, 0: us, 1: ms */ + +#define PWR_CMD_END 0x04 +/* offset: N/A + * msk: N/A + * value: N/A */ + +/*---------------------------------------------*/ +/* 3 The value of base: 4 bits + *--------------------------------------------- + * define the base address of each block */ +#define PWR_BASEADDR_MAC 0x00 +#define PWR_BASEADDR_USB 0x01 +#define PWR_BASEADDR_PCIE 0x02 +#define PWR_BASEADDR_SDIO 0x03 + +/*---------------------------------------------*/ +/* 3 The value of interface_msk: 4 bits + *---------------------------------------------*/ +#define PWR_INTF_SDIO_MSK BIT(0) +#define PWR_INTF_USB_MSK BIT(1) +#define PWR_INTF_PCI_MSK BIT(2) +#define PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +/*---------------------------------------------*/ +/* 3 The value of fab_msk: 4 bits + *---------------------------------------------*/ +#define PWR_FAB_TSMC_MSK BIT(0) +#define PWR_FAB_UMC_MSK BIT(1) +#define PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +/*---------------------------------------------*/ +/* 3 The value of cut_msk: 8 bits + *---------------------------------------------*/ +#define PWR_CUT_TESTCHIP_MSK BIT(0) +#define PWR_CUT_A_MSK BIT(1) +#define PWR_CUT_B_MSK BIT(2) +#define PWR_CUT_C_MSK BIT(3) +#define PWR_CUT_D_MSK BIT(4) +#define PWR_CUT_E_MSK BIT(5) +#define PWR_CUT_F_MSK BIT(6) +#define PWR_CUT_G_MSK BIT(7) +#define PWR_CUT_ALL_MSK 0xFF + +typedef enum _PWRSEQ_CMD_DELAY_UNIT_ { + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +} PWRSEQ_DELAY_UNIT; + +typedef struct _WL_PWR_CFG_ { + u16 offset; + u8 cut_msk; + u8 fab_msk:4; + u8 interface_msk:4; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 value; +} WLAN_PWR_CFG, *PWLAN_PWR_CFG; + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) ((__PWR_CMD).offset) +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) ((__PWR_CMD).cut_msk) +#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) ((__PWR_CMD).fab_msk) +#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) ((__PWR_CMD).interface_msk) +#define GET_PWR_CFG_BASE(__PWR_CMD) ((__PWR_CMD).base) +#define GET_PWR_CFG_CMD(__PWR_CMD) ((__PWR_CMD).cmd) +#define GET_PWR_CFG_MASK(__PWR_CMD) ((__PWR_CMD).msk) +#define GET_PWR_CFG_VALUE(__PWR_CMD) ((__PWR_CMD).value) + +/* ******************************************************************************** + * Prototype of protected function. + * ******************************************************************************** */ +u8 HalPwrSeqCmdParsing( + PADAPTER padapter, + u8 CutVersion, + u8 FabVersion, + u8 InterfaceType, + WLAN_PWR_CFG PwrCfgCmd[]); + +#endif diff --git a/drivers/staging/rtl8821ce/include/HalVerDef.h b/drivers/staging/rtl8821ce/include/HalVerDef.h new file mode 100644 index 000000000000..57a0403b9714 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/HalVerDef.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_VERSION_DEF_H__ +#define __HAL_VERSION_DEF_H__ + +#define TRUE _TRUE +#define FALSE _FALSE + +/* HAL_IC_TYPE_E */ +typedef enum tag_HAL_IC_Type_Definition { + CHIP_8192S = 0, + CHIP_8188C = 1, + CHIP_8192C = 2, + CHIP_8192D = 3, + CHIP_8723A = 4, + CHIP_8188E = 5, + CHIP_8812 = 6, + CHIP_8821 = 7, + CHIP_8723B = 8, + CHIP_8192E = 9, + CHIP_8814A = 10, + CHIP_8703B = 11, + CHIP_8188F = 12, + CHIP_8822B = 13, + CHIP_8723D = 14, + CHIP_8821C = 15 +} HAL_IC_TYPE_E; + +/* HAL_CHIP_TYPE_E */ +typedef enum tag_HAL_CHIP_Type_Definition { + TEST_CHIP = 0, + NORMAL_CHIP = 1, + FPGA = 2, +} HAL_CHIP_TYPE_E; + +/* HAL_CUT_VERSION_E */ +typedef enum tag_HAL_Cut_Version_Definition { + A_CUT_VERSION = 0, + B_CUT_VERSION = 1, + C_CUT_VERSION = 2, + D_CUT_VERSION = 3, + E_CUT_VERSION = 4, + F_CUT_VERSION = 5, + G_CUT_VERSION = 6, + H_CUT_VERSION = 7, + I_CUT_VERSION = 8, + J_CUT_VERSION = 9, + K_CUT_VERSION = 10, +} HAL_CUT_VERSION_E; + +/* HAL_Manufacturer */ +typedef enum tag_HAL_Manufacturer_Version_Definition { + CHIP_VENDOR_TSMC = 0, + CHIP_VENDOR_UMC = 1, + CHIP_VENDOR_SMIC = 2, +} HAL_VENDOR_E; + +typedef enum tag_HAL_RF_Type_Definition { + RF_TYPE_1T1R = 0, + RF_TYPE_1T2R = 1, + RF_TYPE_2T2R = 2, + RF_TYPE_2T3R = 3, + RF_TYPE_2T4R = 4, + RF_TYPE_3T3R = 5, + RF_TYPE_3T4R = 6, + RF_TYPE_4T4R = 7, +} HAL_RF_TYPE_E; + +typedef struct tag_HAL_VERSION { + HAL_IC_TYPE_E ICType; + HAL_CHIP_TYPE_E ChipType; + HAL_CUT_VERSION_E CUTVersion; + HAL_VENDOR_E VendorType; + HAL_RF_TYPE_E RFType; + u8 ROMVer; +} HAL_VERSION, *PHAL_VERSION; + +/* VERSION_8192C VersionID; + * HAL_VERSION VersionID; */ + +/* Get element */ +#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType)) +#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType)) +#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType)) +#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType)) +#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion)) +#define GET_CVID_ROM_VERSION(version) ((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK) + +/* ---------------------------------------------------------------------------- + * Common Macro. -- + * ---------------------------------------------------------------------------- + * HAL_VERSION VersionID */ + +/* HAL_IC_TYPE_E */ +#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? TRUE : FALSE) +#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE) +#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E) ? TRUE : FALSE) +#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812) ? TRUE : FALSE) +#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821) ? TRUE : FALSE) +#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE) +#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B) ? TRUE : FALSE) +#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B) ? TRUE : FALSE) +#define IS_8822B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8822B) ? TRUE : FALSE) +#define IS_8821C_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821C) ? TRUE : FALSE) +#define IS_8723D_SERIES(version)\ + ((GET_CVID_IC_TYPE(version) == CHIP_8723D) ? TRUE : FALSE) +/* HAL_CHIP_TYPE_E */ +#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? TRUE : FALSE) +#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? TRUE : FALSE) + +/* HAL_CUT_VERSION_E */ +#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE) +#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE) +#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE) +#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE) +#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE) +#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE) +#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE) +#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE) +#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE) + +/* HAL_VENDOR_E */ +#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? TRUE : FALSE) +#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? TRUE : FALSE) +#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC) ? TRUE : FALSE) + +/* HAL_RF_TYPE_E */ +#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? TRUE : FALSE) +#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? TRUE : FALSE) +#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? TRUE : FALSE) +#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R) ? TRUE : FALSE) +#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R) ? TRUE : FALSE) +#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R) ? TRUE : FALSE) + +/* ---------------------------------------------------------------------------- + * Chip version Macro. -- + * ---------------------------------------------------------------------------- */ +#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->version_id) == B_CUT_VERSION) ? TRUE : FALSE) + +#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->version_id)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->version_id)) ? TRUE : FALSE) : FALSE) + +#endif diff --git a/drivers/staging/rtl8821ce/include/autoconf.h b/drivers/staging/rtl8821ce/include/autoconf.h new file mode 100644 index 000000000000..3dcb11c80c19 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/autoconf.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/***** temporarily flag *******/ +/* #define CONFIG_DISABLE_ODM */ + +/***** temporarily flag *******/ +/* + * Public Generalal Config + */ +#define AUTOCONF_INCLUDED +#define DRV_NAME "rtl8821ce" + +/*#define CONFIG_LPS*/ + + /*#define CONFIG_LPS_LCLK*/ /* 32K */ + + + + /* for ODM and outsrc BT-Coex */ + diff --git a/drivers/staging/rtl8821ce/include/basic_types.h b/drivers/staging/rtl8821ce/include/basic_types.h new file mode 100644 index 000000000000..411302b60402 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/basic_types.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __BASIC_TYPES_H__ +#define __BASIC_TYPES_H__ + +#define SUCCESS 0 +#define FAIL (-1) + +#ifndef TRUE + #define _TRUE 1 +#else + #define _TRUE TRUE +#endif + +#ifndef FALSE + #define _FALSE 0 +#else + #define _FALSE FALSE +#endif + +#include <linux/version.h> +#include <linux/types.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/utsname.h> +#define IN +#define OUT +#define VOID void +#define NDIS_OID uint +#define NDIS_STATUS uint + +typedef signed int sint; + +#ifndef PVOID +typedef void *PVOID; +/* #define PVOID (void *) */ +#endif + +#define UCHAR u8 +#define USHORT u16 +#define UINT u32 +#define ULONG u32 + +typedef void (*proc_t)(void *); + +typedef __kernel_size_t SIZE_T; +typedef __kernel_ssize_t SSIZE_T; +#define FIELD_OFFSET(s, field) ((SSIZE_T)&((s *)(0))->field) + +#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) +#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) + +#define SIZE_PTR SIZE_T +#define SSIZE_PTR SSIZE_T + +/* +* Continuous bits starting from least significant bit +* Example: +* BIT_LEN_MASK_32(0) => 0x00000000 +* BIT_LEN_MASK_32(1) => 0x00000001 +* BIT_LEN_MASK_32(2) => 0x00000003 +* BIT_LEN_MASK_32(32) => 0xFFFFFFFF +*/ +#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen)))) +#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen)))) +#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen)))) + +/* +* Continuous bits starting from least significant bit +* Example: +* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 +* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 +*/ +#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))) +#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))) +#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))) + +/* +* Convert LE data to host byte order +*/ +#define EF1Byte (u8) +#define EF2Byte le16_to_cpu +#define EF4Byte le32_to_cpu + +/* +* Read LE data from memory to host byte order +*/ +#define ReadLE4Byte(_ptr) le32_to_cpu(*((u32 *)(_ptr))) +#define ReadLE2Byte(_ptr) le16_to_cpu(*((u16 *)(_ptr))) +#define ReadLE1Byte(_ptr) (*((u8 *)(_ptr))) + +/* +* Read BE data from memory to host byte order +*/ +#define ReadBEE4Byte(_ptr) be32_to_cpu(*((u32 *)(_ptr))) +#define ReadBE2Byte(_ptr) be16_to_cpu(*((u16 *)(_ptr))) +#define ReadBE1Byte(_ptr) (*((u8 *)(_ptr))) + +/* +* Write host byte order data to memory in LE order +*/ +#define WriteLE4Byte(_ptr, _val) ((*((u32 *)(_ptr))) = cpu_to_le32(_val)) +#define WriteLE2Byte(_ptr, _val) ((*((u16 *)(_ptr))) = cpu_to_le16(_val)) +#define WriteLE1Byte(_ptr, _val) ((*((u8 *)(_ptr))) = ((u8)(_val))) + +/* +* Write host byte order data to memory in BE order +*/ +#define WriteBE4Byte(_ptr, _val) ((*((u32 *)(_ptr))) = cpu_to_be32(_val)) +#define WriteBE2Byte(_ptr, _val) ((*((u16 *)(_ptr))) = cpu_to_be16(_val)) +#define WriteBE1Byte(_ptr, _val) ((*((u8 *)(_ptr))) = ((u8)(_val))) + +/* +* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system. +*/ +#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart)))) +#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart)))) +#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart)))) + +/* +* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system. +*/ +#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart)))) +#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart)))) +#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart)))) + +/* +* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to +* 4-byte value in host byte ordering. +*/ +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen)) + +#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen)) + +#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen)) + +/* +* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to +* 4-byte value in host byte ordering. +*/ +#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen)) + +#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen)) + +#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen)) + +/* +* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering +* and return the result in 4-byte value in host byte ordering. +*/ +#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + (LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen))) + +#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + (LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen))) + +#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + (LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))) + +/* +* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering +* and return the result in 4-byte value in host byte ordering. +*/ +#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + (BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen))) + +#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + (BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen))) + +#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + (BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))) + +/* +* Set subfield of little-endian 4-byte value to specified value. +*/ +#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 32) \ + WriteLE4Byte(__pStart, __Value); \ + else { \ + WriteLE4Byte(__pStart, \ + LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 16) \ + WriteLE2Byte(__pStart, __Value); \ + else { \ + WriteLE2Byte(__pStart, \ + LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 8) \ + WriteLE1Byte(__pStart, __Value); \ + else { \ + WriteLE1Byte(__pStart, \ + LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +/* +* Set subfield of big-endian 4-byte value to specified value. +*/ +#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 32) \ + WriteBE4Byte(__pStart, __Value); \ + else { \ + WriteBE4Byte(__pStart, \ + BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 16) \ + WriteBE2Byte(__pStart, __Value); \ + else { \ + WriteBE2Byte(__pStart, \ + BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 8) \ + WriteBE1Byte(__pStart, __Value); \ + else { \ + WriteBE1Byte(__pStart, \ + BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +/* Get the N-bytes aligment offset from the current length */ +#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) + +typedef unsigned char BOOLEAN, *PBOOLEAN, boolean; + +#define TEST_FLAG(__Flag, __testFlag) (((__Flag) & (__testFlag)) != 0) +#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag) +#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag)) +#define CLEAR_FLAGS(__Flag) ((__Flag) = 0) +#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags)) + +#endif /* __BASIC_TYPES_H__ */ diff --git a/drivers/staging/rtl8821ce/include/byteorder/big_endian.h b/drivers/staging/rtl8821ce/include/byteorder/big_endian.h new file mode 100644 index 000000000000..a099d8c97bd5 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/byteorder/big_endian.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN + #define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD + #define __BIG_ENDIAN_BITFIELD +#endif + +#include <byteorder/swab.h> + +#define __constant_htonl(x) ((__u32)(x)) +#define __constant_ntohl(x) ((__u32)(x)) +#define __constant_htons(x) ((__u16)(x)) +#define __constant_ntohs(x) ((__u16)(x)) +#define __constant_cpu_to_le64(x) ___constant_swab64((x)) +#define __constant_le64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_le32(x) ___constant_swab32((x)) +#define __constant_le32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_le16(x) ___constant_swab16((x)) +#define __constant_le16_to_cpu(x) ___constant_swab16((x)) +#define __constant_cpu_to_be64(x) ((__u64)(x)) +#define __constant_be64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_be32(x) ((__u32)(x)) +#define __constant_be32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_be16(x) ((__u16)(x)) +#define __constant_be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64(x) __swab64((x)) +#define __le64_to_cpu(x) __swab64((x)) +#define __cpu_to_le32(x) __swab32((x)) +#define __le32_to_cpu(x) __swab32((x)) +#define __cpu_to_le16(x) __swab16((x)) +#define __le16_to_cpu(x) __swab16((x)) +#define __cpu_to_be64(x) ((__u64)(x)) +#define __be64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_be32(x) ((__u32)(x)) +#define __be32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_be16(x) ((__u16)(x)) +#define __be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64p(x) __swab64p((x)) +#define __le64_to_cpup(x) __swab64p((x)) +#define __cpu_to_le32p(x) __swab32p((x)) +#define __le32_to_cpup(x) __swab32p((x)) +#define __cpu_to_le16p(x) __swab16p((x)) +#define __le16_to_cpup(x) __swab16p((x)) +#define __cpu_to_be64p(x) (*(__u64 *)(x)) +#define __be64_to_cpup(x) (*(__u64 *)(x)) +#define __cpu_to_be32p(x) (*(__u32 *)(x)) +#define __be32_to_cpup(x) (*(__u32 *)(x)) +#define __cpu_to_be16p(x) (*(__u16 *)(x)) +#define __be16_to_cpup(x) (*(__u16 *)(x)) +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do {} while (0) +#define __be64_to_cpus(x) do {} while (0) +#define __cpu_to_be32s(x) do {} while (0) +#define __be32_to_cpus(x) do {} while (0) +#define __cpu_to_be16s(x) do {} while (0) +#define __be16_to_cpus(x) do {} while (0) + +#include <byteorder/generic.h> + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ diff --git a/drivers/staging/rtl8821ce/include/byteorder/generic.h b/drivers/staging/rtl8821ce/include/byteorder/generic.h new file mode 100644 index 000000000000..d1724e372d76 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/byteorder/generic.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder_generic.h + * Generic Byte-reordering support + * + * Francois-Rene Rideau <fare@xxxxxxxxx> 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau <fare@xxxxxxxxx> 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau <fare@xxxxxxxxx> 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by <asm/byteorder.h>: + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + + /* + * inside the kernel, we can use nicknames; + * outside of it, we must avoid POSIX namespace pollution... + */ + #define cpu_to_le64 __cpu_to_le64 + #define le64_to_cpu __le64_to_cpu + #define cpu_to_le32 __cpu_to_le32 + #define le32_to_cpu __le32_to_cpu + #define cpu_to_le16 __cpu_to_le16 + #define le16_to_cpu __le16_to_cpu + #define cpu_to_be64 __cpu_to_be64 + #define be64_to_cpu __be64_to_cpu + #define cpu_to_be32 __cpu_to_be32 + #define be32_to_cpu __be32_to_cpu + #define cpu_to_be16 __cpu_to_be16 + #define be16_to_cpu __be16_to_cpu + #define cpu_to_le64p __cpu_to_le64p + #define le64_to_cpup __le64_to_cpup + #define cpu_to_le32p __cpu_to_le32p + #define le32_to_cpup __le32_to_cpup + #define cpu_to_le16p __cpu_to_le16p + #define le16_to_cpup __le16_to_cpup + #define cpu_to_be64p __cpu_to_be64p + #define be64_to_cpup __be64_to_cpup + #define cpu_to_be32p __cpu_to_be32p + #define be32_to_cpup __be32_to_cpup + #define cpu_to_be16p __cpu_to_be16p + #define be16_to_cpup __be16_to_cpup + #define cpu_to_le64s __cpu_to_le64s + #define le64_to_cpus __le64_to_cpus + #define cpu_to_le32s __cpu_to_le32s + #define le32_to_cpus __le32_to_cpus + #define cpu_to_le16s __cpu_to_le16s + #define le16_to_cpus __le16_to_cpus + #define cpu_to_be64s __cpu_to_be64s + #define be64_to_cpus __be64_to_cpus + #define cpu_to_be32s __cpu_to_be32s + #define be32_to_cpus __be32_to_cpus + #define cpu_to_be16s __cpu_to_be16s + #define be16_to_cpus __be16_to_cpus + +/* + * Handle ntohl and suches. These have various compatibility + * issues - like we want to give the prototype even though we + * also have a macro for them in case some strange program + * wants to take the address of the thing or something.. + * + * Note that these used to return a "long" in libc5, even though + * long is often 64-bit these days.. Thus the casts. + * + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +/* + * Do the prototypes. Somebody might want to take the + * address or some such sick thing.. + */ + extern __u32 ntohl(__u32); + extern __u32 htonl(__u32); + extern unsigned short int ntohs(unsigned short int); + extern unsigned short int htons(unsigned short int); + +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL) + + #define ___htonl(x) __cpu_to_be32(x) + #define ___htons(x) __cpu_to_be16(x) + #define ___ntohl(x) __be32_to_cpu(x) + #define ___ntohs(x) __be16_to_cpu(x) + + #define htonl(x) ___htonl(x) + #define ntohl(x) ___ntohl(x) + #define htons(x) ___htons(x) + #define ntohs(x) ___ntohs(x) + +#endif /* OPTIMIZE */ + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ diff --git a/drivers/staging/rtl8821ce/include/byteorder/swab.h b/drivers/staging/rtl8821ce/include/byteorder/swab.h new file mode 100644 index 000000000000..41bf070ba0ee --- /dev/null +++ b/drivers/staging/rtl8821ce/include/byteorder/swab.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H + +#if !defined(CONFIG_PLATFORM_MSTAR) +#ifndef __u16 + typedef unsigned short __u16; +#endif + +#ifndef __u32 + typedef unsigned int __u32; +#endif + +#ifndef __u8 + typedef unsigned char __u8; +#endif + +#ifndef __u64 + typedef unsigned long long __u64; +#endif + +__inline static __u16 ___swab16(__u16 x) +{ + __u16 __x = x; + return + (__u16)( + (((__u16)(__x)&(__u16)0x00ffU) << 8) | + (((__u16)(__x)&(__u16)0xff00U) >> 8)); + +} + +__inline static __u32 ___swab32(__u32 x) +{ + __u32 __x = (x); + return (__u32)( + (((__u32)(__x)&(__u32)0x000000ffUL) << 24) | + (((__u32)(__x)&(__u32)0x0000ff00UL) << 8) | + (((__u32)(__x)&(__u32)0x00ff0000UL) >> 8) | + (((__u32)(__x)&(__u32)0xff000000UL) >> 24)); +} + +__inline static __u64 ___swab64(__u64 x) +{ + __u64 __x = (x); + + return + (__u64)(\ + (__u64)(((__u64)(__x)&(__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(__x)&(__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(__x)&(__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(__x)&(__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(__x)&(__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(__x)&(__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(__x)&(__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(__x)&(__u64)0xff00000000000000ULL) >> 56)); + \ +} +#endif /* CONFIG_PLATFORM_MSTAR */ + +#ifndef __arch__swab16 +__inline static __u16 __arch__swab16(__u16 x) +{ + return ___swab16(x); +} + +#endif + +#ifndef __arch__swab32 +__inline static __u32 __arch__swab32(__u32 x) +{ + __u32 __tmp = (x) ; + return ___swab32(__tmp); +} +#endif + +#ifndef __arch__swab64 + +__inline static __u64 __arch__swab64(__u64 x) +{ + __u64 __tmp = (x) ; + return ___swab64(__tmp); +} + +#endif + +#ifndef __swab16 + #define __swab16(x) __fswab16(x) + #define __swab32(x) __fswab32(x) + #define __swab64(x) __fswab64(x) +#endif /* __swab16 */ + + __inline static const __u16 __fswab16(__u16 x) +{ + return __arch__swab16(x); +} + __inline static const __u32 __fswab32(__u32 x) +{ + return __arch__swab32(x); +} + + #define swab16 __swab16 + #define swab32 __swab32 + #define swab64 __swab64 + #define swab16p __swab16p + #define swab32p __swab32p + #define swab64p __swab64p + #define swab16s __swab16s + #define swab32s __swab32s + #define swab64s __swab64s + +#endif /* _LINUX_BYTEORDER_SWAB_H */ diff --git a/drivers/staging/rtl8821ce/include/byteorder/swabb.h b/drivers/staging/rtl8821ce/include/byteorder/swabb.h new file mode 100644 index 000000000000..b4150cdb1aeb --- /dev/null +++ b/drivers/staging/rtl8821ce/include/byteorder/swabb.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_SWABB_H +#define _LINUX_BYTEORDER_SWABB_H + +/* + * linux/byteorder/swabb.h + * SWAp Bytes Bizarrely + * swaHHXX[ps]?(foo) + * + * Support for obNUXIous pdp-endian and other bizarre architectures. + * Will Linux ever run on such ancient beasts? if not, this file + * will be but a programming pearl. Still, it's a reminder that we + * shouldn't be making too many assumptions when trying to be portable. + * + */ + +/* + * Meaning of the names I chose (vaxlinux people feel free to correct them): + * swahw32 swap 16-bit half-words in a 32-bit word + * swahb32 swap 8-bit halves of each 16-bit half-word in a 32-bit word + * + * No 64-bit support yet. I don't know NUXI conventions for long longs. + * I guarantee it will be a mess when it's there, though :-> + * It will be even worse if there are conflicting 64-bit conventions. + * Hopefully, no one ever used 64-bit objects on NUXI machines. + * + */ + +#define ___swahw32(x) \ + ({ \ + __u32 __x = (x); \ + ((__u32)(\ + (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \ + (((__u32)(__x) & (__u32)0xffff0000UL) >> 16))); \ + }) +#define ___swahb32(x) \ + ({ \ + __u32 __x = (x); \ + ((__u32)(\ + (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \ + (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8))); \ + }) + +#define ___constant_swahw32(x) \ + ((__u32)(\ + (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ + (((__u32)(x) & (__u32)0xffff0000UL) >> 16))) +#define ___constant_swahb32(x) \ + ((__u32)(\ + (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ + (((__u32)(x) & (__u32)0xff00ff00UL) >> 8))) + +/* + * provide defaults when no architecture-specific optimization is detected + */ +#ifndef __arch__swahw32 + #define __arch__swahw32(x) ___swahw32(x) +#endif +#ifndef __arch__swahb32 + #define __arch__swahb32(x) ___swahb32(x) +#endif + +#ifndef __arch__swahw32p + #define __arch__swahw32p(x) __swahw32(*(x)) +#endif +#ifndef __arch__swahb32p + #define __arch__swahb32p(x) __swahb32(*(x)) +#endif + +#ifndef __arch__swahw32s + #define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0) +#endif +#ifndef __arch__swahb32s + #define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0) +#endif + +/* + * Allow constant folding + */ +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) +# define __swahw32(x) \ + (__builtin_constant_p((__u32)(x)) ? \ + ___swahw32((x)) : \ + __fswahw32((x))) +# define __swahb32(x) \ + (__builtin_constant_p((__u32)(x)) ? \ + ___swahb32((x)) : \ + __fswahb32((x))) +#else +# define __swahw32(x) __fswahw32(x) +# define __swahb32(x) __fswahb32(x) +#endif /* OPTIMIZE */ + +__inline static__ __const__ __u32 __fswahw32(__u32 x) +{ + return __arch__swahw32(x); +} +__inline static__ __u32 __swahw32p(__u32 *x) +{ + return __arch__swahw32p(x); +} +__inline static__ void __swahw32s(__u32 *addr) +{ + __arch__swahw32s(addr); +} + +__inline static__ __const__ __u32 __fswahb32(__u32 x) +{ + return __arch__swahb32(x); +} +__inline static__ __u32 __swahb32p(__u32 *x) +{ + return __arch__swahb32p(x); +} +__inline static__ void __swahb32s(__u32 *addr) +{ + __arch__swahb32s(addr); +} + +#ifdef __BYTEORDER_HAS_U64__ + /* + * Not supported yet + */ +#endif /* __BYTEORDER_HAS_U64__ */ + + #define swahw32 __swahw32 + #define swahb32 __swahb32 + #define swahw32p __swahw32p + #define swahb32p __swahb32p + #define swahw32s __swahw32s + #define swahb32s __swahb32s + +#endif /* _LINUX_BYTEORDER_SWABB_H */ diff --git a/drivers/staging/rtl8821ce/include/circ_buf.h b/drivers/staging/rtl8821ce/include/circ_buf.h new file mode 100644 index 000000000000..488430c01a07 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/circ_buf.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __CIRC_BUF_H_ +#define __CIRC_BUF_H_ 1 + +#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) + +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +#endif //_CIRC_BUF_H_ + diff --git a/drivers/staging/rtl8821ce/include/cmd_osdep.h b/drivers/staging/rtl8821ce/include/cmd_osdep.h new file mode 100644 index 000000000000..ee8005f2acaf --- /dev/null +++ b/drivers/staging/rtl8821ce/include/cmd_osdep.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __CMD_OSDEP_H_ +#define __CMD_OSDEP_H_ + +extern sint _rtw_init_cmd_priv(struct cmd_priv *pcmdpriv); +extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv); +extern void _rtw_free_evt_priv(struct evt_priv *pevtpriv); +extern void _rtw_free_cmd_priv(struct cmd_priv *pcmdpriv); +extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head); +extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue); + +#endif diff --git a/drivers/staging/rtl8821ce/include/custom_gpio.h b/drivers/staging/rtl8821ce/include/custom_gpio.h new file mode 100644 index 000000000000..40dacba9061e --- /dev/null +++ b/drivers/staging/rtl8821ce/include/custom_gpio.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __CUSTOM_GPIO_H__ +#define __CUSTOM_GPIO_H___ + +#include <drv_conf.h> +#include <osdep_service.h> + + + #include <drv_types_linux.h> + +typedef enum cust_gpio_modes { + WLAN_PWDN_ON, + WLAN_PWDN_OFF, + WLAN_POWER_ON, + WLAN_POWER_OFF, + WLAN_BT_PWDN_ON, + WLAN_BT_PWDN_OFF +} cust_gpio_modes_t; + +extern int rtw_wifi_gpio_init(void); +extern int rtw_wifi_gpio_deinit(void); +extern void rtw_wifi_gpio_wlan_ctrl(int onoff); + +#endif diff --git a/drivers/staging/rtl8821ce/include/drv_conf.h b/drivers/staging/rtl8821ce/include/drv_conf.h new file mode 100644 index 000000000000..76c5dde6be76 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/drv_conf.h @@ -0,0 +1,165 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_CONF_H__ +#define __DRV_CONF_H__ +#include "autoconf.h" +#include "hal_ic_cfg.h" + + +/* Older Android kernel doesn't has CONFIG_ANDROID defined, + * add this to force CONFIG_ANDROID defined */ + +/* +#if defined(CONFIG_HAS_EARLYSUSPEND) && defined(CONFIG_RESUME_IN_WORKQUEUE) + #warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" + #undef CONFIG_RESUME_IN_WORKQUEUE +#endif + +#if defined(CONFIG_ANDROID_POWER) && defined(CONFIG_RESUME_IN_WORKQUEUE) + #warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" + #undef CONFIG_RESUME_IN_WORKQUEUE +#endif +*/ + +#define RTW_SCAN_SPARSE_MIRACAST 1 +#define RTW_SCAN_SPARSE_BG 0 +#define RTW_SCAN_SPARSE_ROAMING_ACTIVE 1 + +#ifndef CONFIG_RTW_HIQ_FILTER + #define CONFIG_RTW_HIQ_FILTER 1 +#endif + +#ifndef CONFIG_RTW_FORCE_IGI_LB + #define CONFIG_RTW_FORCE_IGI_LB 0 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_DML + #define CONFIG_RTW_ADAPTIVITY_DML 0 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF + #define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI + #define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF + #define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0 +#endif + +#ifndef CONFIG_RTW_EXCL_CHS + #define CONFIG_RTW_EXCL_CHS {0} +#endif + +#ifndef CONFIG_RTW_DFS_REGION_DOMAIN + #define CONFIG_RTW_DFS_REGION_DOMAIN 0 +#endif + +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS {0xFF, 0xFF, 0xFF, 0xFF} +#endif +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS {0xFF, 0xFF, 0xFF, 0xFF} +#endif +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS {0xFF, 0xFF, 0xFF, 0xFF} +#endif +#ifndef CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS + #define CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS {0xFF, 0xFF, 0xFF, 0xFF} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A + #define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B + #define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C + #define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D + #define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A + #define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B + #define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C + #define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D + #define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G + #define CONFIG_RTW_AMPLIFIER_TYPE_2G 0 +#endif + +#ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G + #define CONFIG_RTW_AMPLIFIER_TYPE_5G 0 +#endif + +#ifndef CONFIG_RTW_RFE_TYPE + #define CONFIG_RTW_RFE_TYPE 64 +#endif + +#ifndef CONFIG_RTW_GLNA_TYPE + #define CONFIG_RTW_GLNA_TYPE 0 +#endif + +#ifndef CONFIG_RTW_PLL_REF_CLK_SEL + #define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F +#endif + +#ifndef CONFIG_IFACE_NUMBER + #define CONFIG_IFACE_NUMBER 1 +#endif + +#define MACID_NUM_SW_LIMIT 32 +#define SEC_CAM_ENT_NUM_SW_LIMIT 32 + +/* + Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20 + If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle, + power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP. +*/ +/*#define CONFIG_DEAUTH_BEFORE_CONNECT */ + +/*#define CONFIG_WEXT_DONT_JOIN_BYSSID */ +/* #include <rtl871x_byteorder.h> */ + +/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */ + +/*Don't release SDIO irq in suspend/resume procedure*/ +#define CONFIG_RTW_SDIO_KEEP_IRQ 0 + +#endif /* __DRV_CONF_H__ */ diff --git a/drivers/staging/rtl8821ce/include/drv_types.h b/drivers/staging/rtl8821ce/include/drv_types.h new file mode 100644 index 000000000000..d9925f8509d3 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/drv_types.h @@ -0,0 +1,1005 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*------------------------------------------------------------------------------- + + For type defines and data structure defines + +--------------------------------------------------------------------------------*/ + +#ifndef __DRV_TYPES_H__ +#define __DRV_TYPES_H__ + +#include <drv_conf.h> +#include <basic_types.h> +#include <osdep_service.h> +#include <wlan_bssdef.h> +#include <wifi.h> +#include <ieee80211.h> + + + #include <drv_types_linux.h> + +enum _NIC_VERSION { + + RTL8711_NIC, + RTL8712_NIC, + RTL8713_NIC, + RTL8716_NIC + +}; + +typedef struct _ADAPTER _adapter, ADAPTER, *PADAPTER; + +#include <rtw_debug.h> +#include <rtw_rf.h> + + #include <rtw_ht.h> + + #include <rtw_vht.h> + +#include <rtw_cmd.h> +#include <cmd_osdep.h> +#include <rtw_security.h> +#include <rtw_xmit.h> +#include <xmit_osdep.h> +#include <rtw_recv.h> + + +#include <recv_osdep.h> +#include <rtw_efuse.h> +#include <rtw_sreset.h> +#include <hal_intf.h> +#include <hal_com.h> +#include<hal_com_h2c.h> +#include <hal_com_led.h> +#include "../hal/hal_dm.h" +#include <rtw_qos.h> +#include <rtw_pwrctrl.h> +#include <rtw_mlme.h> +#include <mlme_osdep.h> +#include <rtw_io.h> +#include <rtw_ioctl.h> +#include <rtw_ioctl_set.h> +#include <rtw_ioctl_query.h> +#include <rtw_ioctl_rtl.h> +#include <osdep_intf.h> +#include <rtw_eeprom.h> +#include <sta_info.h> +#include <rtw_event.h> +#include <rtw_mlme_ext.h> +#include <rtw_mi.h> +#include <rtw_ap.h> +#include <rtw_efuse.h> +#include <rtw_version.h> +#include <rtw_odm.h> + + +#include <rtw_p2p.h> + + + #include <rtw_mp.h> + + #include <rtw_br_ext.h> + + +#include <ip.h> +#include <if_ether.h> +#include <ethernet.h> +#include <circ_buf.h> + +#include <rtw_android.h> + +#include <rtw_btcoex_wifionly.h> + #include <rtw_btcoex.h> + +#define SPEC_DEV_ID_NONE BIT(0) +#define SPEC_DEV_ID_DISABLE_HT BIT(1) +#define SPEC_DEV_ID_ENABLE_PS BIT(2) +#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) +#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) +#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) + +struct specific_device_id { + + u32 flags; + + u16 idVendor; + u16 idProduct; + +}; + +struct registry_priv { + u8 chip_version; + u8 rfintfs; + u8 lbkmode; + u8 hci; + NDIS_802_11_SSID ssid; + u8 network_mode; /* infra, ad-hoc, auto */ + u8 channel;/* ad-hoc support requirement */ + u8 wireless_mode;/* A, B, G, auto */ + u8 scan_mode;/* active, passive */ + u8 radio_enable; + u8 preamble;/* long, short, auto */ + u8 vrtl_carrier_sense;/* Enable, Disable, Auto */ + u8 vcs_type;/* RTS/CTS, CTS-to-self */ + u16 rts_thresh; + u16 frag_thresh; + u8 adhoc_tx_pwr; + u8 soft_ap; + u8 power_mgnt; + u8 ips_mode; + u8 lps_level; + u8 smart_ps; + u8 usb_rxagg_mode; + u8 dynamic_agg_enable; + u8 long_retry_lmt; + u8 short_retry_lmt; + u16 busy_thresh; + u8 ack_policy; + u8 mp_mode; + u8 mp_dm; + u8 software_encrypt; + u8 software_decrypt; + u8 acm_method; + /* UAPSD */ + u8 wmm_enable; + u8 uapsd_enable; + u8 uapsd_max_sp; + u8 uapsd_acbk_en; + u8 uapsd_acbe_en; + u8 uapsd_acvi_en; + u8 uapsd_acvo_en; + + WLAN_BSSID_EX dev_network; + + u8 tx_bw_mode; + + u8 ht_enable; + /* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz */ + /* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 */ + /* 0x21 means enable 2.4G 40MHz & 5G 80MHz */ + u8 bw_mode; + u8 ampdu_enable;/* for tx */ + u8 rx_stbc; + u8 rx_ampdu_amsdu;/* Rx A-MPDU Supports A-MSDU is permitted */ + u8 tx_ampdu_amsdu;/* Tx A-MPDU Supports A-MSDU is permitted */ + u8 rx_ampdu_sz_limit_by_nss_bw[4][4]; /* 1~4SS, BW20~BW160 */ + /* Short GI support Bit Map */ + /* BIT0 - 20MHz, 1: support, 0: non-support */ + /* BIT1 - 40MHz, 1: support, 0: non-support */ + /* BIT2 - 80MHz, 1: support, 0: non-support */ + /* BIT3 - 160MHz, 1: support, 0: non-support */ + u8 short_gi; + /* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ + u8 ldpc_cap; + /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ + u8 stbc_cap; + /* + * BIT0: Enable VHT SU Beamformer + * BIT1: Enable VHT SU Beamformee + * BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer + * BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee + * BIT4: Enable HT Beamformer + * BIT5: Enable HT Beamformee + */ + u8 beamform_cap; + u8 beamformer_rf_num; + u8 beamformee_rf_num; + + u8 vht_enable; /* 0:disable, 1:enable, 2:auto */ + u8 ampdu_factor; + u8 vht_rx_mcs_map[2]; + + u8 lowrate_two_xmit; + + u8 rf_config ; + u8 low_power ; + + u8 wifi_spec;/* !turbo_mode */ + u8 special_rf_path; /* 0: 2T2R ,1: only turn on path A 1T1R */ + char alpha2[2]; + u8 channel_plan; + u8 excl_chs[MAX_CHANNEL_NUM]; + u8 full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/ + + u8 btcoex; + u8 bt_iso; + u8 bt_sco; + u8 bt_ampdu; + u8 ant_num; + u8 single_ant_path; + BOOLEAN bAcceptAddbaReq; + + u8 antdiv_cfg; + u8 antdiv_type; + u8 drv_ant_band_switch; + + u8 switch_usb_mode; + + u8 usbss_enable;/* 0:disable,1:enable */ + u8 hwpdn_mode;/* 0:disable,1:enable,2:decide by EFUSE config */ + u8 hwpwrp_detect;/* 0:disable,1:enable */ + + u8 hw_wps_pbc;/* 0:disable,1:enable */ + + + u8 max_roaming_times; /* the max number driver will try to roaming */ + + + u8 enable80211d; + + u8 ifname[16]; + u8 if2name[16]; + + u8 notch_filter; + + + u8 force_igi_lb; + + /* for pll reference clock selction */ + u8 pll_ref_clk_sel; + + /* define for tx power adjust */ + u8 RegEnableTxPowerLimit; + u8 RegEnableTxPowerByRate; + u8 RegPowerBase; + u8 RegPwrTblSel; + + u8 target_tx_pwr_valid; + s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM]; + s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1]; + + s8 TxBBSwing_2G; + s8 TxBBSwing_5G; + u8 AmplifierType_2G; + u8 AmplifierType_5G; + u8 bEn_RFE; + u8 RFE_Type; + u8 PowerTracking_Type; + u8 GLNA_Type; + u8 check_fw_ps; + u8 RegPwrTrimEnable; + + u8 load_phy_file; + u8 RegDecryptCustomFile; + u8 qos_opt_enable; + + u8 hiq_filter; + u8 adaptivity_en; + u8 adaptivity_mode; + u8 adaptivity_dml; + u8 adaptivity_dc_backoff; + s8 adaptivity_th_l2h_ini; + s8 adaptivity_th_edcca_hl_diff; + + u8 boffefusemask; + BOOLEAN bFileMaskEfuse; + u32 reg_rxgain_offset_2g; + u32 reg_rxgain_offset_5gl; + u32 reg_rxgain_offset_5gm; + u32 reg_rxgain_offset_5gh; + + + u8 en_napi; + u8 en_gro; + + bool default_patterns_en; + u8 check_hw_status; + + u32 pci_aspm_config; +}; + +/* For registry parameters */ +#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv, field)) +#define RGTRY_SZ(field) sizeof(((struct registry_priv *) 0)->field) + +#define GetRegAmplifierType2G(_Adapter) (_Adapter->registrypriv.AmplifierType_2G) +#define GetRegAmplifierType5G(_Adapter) (_Adapter->registrypriv.AmplifierType_5G) + +#define GetRegTxBBSwing_2G(_Adapter) (_Adapter->registrypriv.TxBBSwing_2G) +#define GetRegTxBBSwing_5G(_Adapter) (_Adapter->registrypriv.TxBBSwing_5G) + +#define GetRegbENRFEType(_Adapter) (_Adapter->registrypriv.bEn_RFE) +#define GetRegRFEType(_Adapter) (_Adapter->registrypriv.RFE_Type) +#define GetRegGLNAType(_Adapter) (_Adapter->registrypriv.GLNA_Type) +#define GetRegPowerTrackingType(_Adapter) (_Adapter->registrypriv.PowerTracking_Type) + +#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX, field)) +#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field) + +#define BW_MODE_2G(bw_mode) ((bw_mode) & 0x0F) +#define BW_MODE_5G(bw_mode) ((bw_mode) >> 4) +#define REGSTY_BW_2G(regsty) BW_MODE_2G((regsty)->bw_mode) +#define REGSTY_BW_5G(regsty) BW_MODE_5G((regsty)->bw_mode) +#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw)) +#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw)) + +#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0) +#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2) + +typedef struct rtw_if_operations { + int __must_check (*read)(struct dvobj_priv *d, unsigned int addr, void *buf, + size_t len, bool fixed); + int __must_check (*write)(struct dvobj_priv *d, unsigned int addr, void *buf, + size_t len, bool fixed); +} RTW_IF_OPS, *PRTW_IF_OPS; + + #include <drv_types_pci.h> + + #define is_primary_adapter(adapter) (1) + #define is_vir_adapter(adapter) (0) + #define get_hw_port(adapter) (HW_PORT0) +#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0]) +#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums) +#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id]) + +#define GetDefaultAdapter(padapter) padapter + +enum _IFACE_ID { + IFACE_ID0, /*PRIMARY_ADAPTER*/ + IFACE_ID1, + IFACE_ID2, + IFACE_ID3, + IFACE_ID4, + IFACE_ID5, + IFACE_ID6, + IFACE_ID7, + IFACE_ID_MAX, +}; + +#define VIF_START_ID 1 + + +struct debug_priv { + u32 dbg_sdio_free_irq_error_cnt; + u32 dbg_sdio_alloc_irq_error_cnt; + u32 dbg_sdio_free_irq_cnt; + u32 dbg_sdio_alloc_irq_cnt; + u32 dbg_sdio_deinit_error_cnt; + u32 dbg_sdio_init_error_cnt; + u32 dbg_suspend_error_cnt; + u32 dbg_suspend_cnt; + u32 dbg_resume_cnt; + u32 dbg_resume_error_cnt; + u32 dbg_deinit_fail_cnt; + u32 dbg_carddisable_cnt; + u32 dbg_carddisable_error_cnt; + u32 dbg_ps_insuspend_cnt; + u32 dbg_dev_unload_inIPS_cnt; + u32 dbg_wow_leave_ps_fail_cnt; + u32 dbg_scan_pwr_state_cnt; + u32 dbg_downloadfw_pwr_state_cnt; + u32 dbg_fw_read_ps_state_fail_cnt; + u32 dbg_leave_ips_fail_cnt; + u32 dbg_leave_lps_fail_cnt; + u32 dbg_h2c_leave32k_fail_cnt; + u32 dbg_diswow_dload_fw_fail_cnt; + u32 dbg_enwow_dload_fw_fail_cnt; + u32 dbg_ips_drvopen_fail_cnt; + u32 dbg_poll_fail_cnt; + u32 dbg_rpwm_toogle_cnt; + u32 dbg_rpwm_timeout_fail_cnt; + u32 dbg_sreset_cnt; + u32 dbg_fw_mem_dl_error_cnt; + u64 dbg_rx_fifo_last_overflow; + u64 dbg_rx_fifo_curr_overflow; + u64 dbg_rx_fifo_diff_overflow; + u64 dbg_rx_ampdu_drop_count; + u64 dbg_rx_ampdu_forced_indicate_count; + u64 dbg_rx_ampdu_loss_count; + u64 dbg_rx_dup_mgt_frame_drop_count; + u64 dbg_rx_ampdu_window_shift_cnt; + u64 dbg_rx_conflic_mac_addr_cnt; +}; + +struct rtw_traffic_statistics { + /* tx statistics */ + u64 tx_bytes; + u64 tx_pkts; + u64 tx_drop; + u64 cur_tx_bytes; + u64 last_tx_bytes; + u32 cur_tx_tp; /* Tx throughput in MBps. */ + + /* rx statistics */ + u64 rx_bytes; + u64 rx_pkts; + u64 rx_drop; + u64 cur_rx_bytes; + u64 last_rx_bytes; + u32 cur_rx_tp; /* Rx throughput in MBps. */ +}; + +#define SEC_CAP_CHK_BMC BIT0 + +#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH BIT0 + +struct sec_cam_bmp { + u32 m0; +}; + +struct cam_ctl_t { + _lock lock; + + u8 sec_cap; + u32 flags; + + u8 num; + struct sec_cam_bmp used; + + _mutex sec_cam_access_mutex; +}; + +struct sec_cam_ent { + u16 ctrl; + u8 mac[ETH_ALEN]; + u8 key[16]; +}; + +#define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" +#define KEY_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ + ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \ + ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] + +struct macid_bmp { + u32 m0; +#if (MACID_NUM_SW_LIMIT > 32) + u32 m1; +#endif +#if (MACID_NUM_SW_LIMIT > 64) + u32 m2; +#endif +#if (MACID_NUM_SW_LIMIT > 96) + u32 m3; +#endif +}; + +struct macid_ctl_t { + _lock lock; + u8 num; + struct macid_bmp used; + struct macid_bmp bmc; + struct macid_bmp if_g[CONFIG_IFACE_NUMBER]; + u8 iface_bmc[CONFIG_IFACE_NUMBER];/*for bc-sta of AP or Adhoc mode*/ + struct macid_bmp ch_g[2]; /* 2 ch concurrency */ + u8 h2c_msr[MACID_NUM_SW_LIMIT]; + u8 bw[MACID_NUM_SW_LIMIT]; + u8 vht_en[MACID_NUM_SW_LIMIT]; + u32 rate_bmp0[MACID_NUM_SW_LIMIT]; + u32 rate_bmp1[MACID_NUM_SW_LIMIT]; + struct sta_info *sta[MACID_NUM_SW_LIMIT]; +}; + +/* used for rf_ctl_t.rate_bmp_cck_ofdm */ +#define RATE_BMP_CCK 0x000F +#define RATE_BMP_OFDM 0xFFF0 +#define RATE_BMP_HAS_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK) +#define RATE_BMP_HAS_OFDM(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_OFDM) +#define RATE_BMP_GET_CCK(_bmp_cck_ofdm) (_bmp_cck_ofdm & RATE_BMP_CCK) +#define RATE_BMP_GET_OFDM(_bmp_cck_ofdm) ((_bmp_cck_ofdm & RATE_BMP_OFDM) >> 4) + +/* used for rf_ctl_t.rate_bmp_ht_by_bw */ +#define RATE_BMP_HT_1SS 0x000000FF +#define RATE_BMP_HT_2SS 0x0000FF00 +#define RATE_BMP_HT_3SS 0x00FF0000 +#define RATE_BMP_HT_4SS 0xFF000000 +#define RATE_BMP_HAS_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS) +#define RATE_BMP_HAS_HT_2SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_2SS) +#define RATE_BMP_HAS_HT_3SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_3SS) +#define RATE_BMP_HAS_HT_4SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_4SS) +#define RATE_BMP_GET_HT_1SS(_bmp_ht) (_bmp_ht & RATE_BMP_HT_1SS) +#define RATE_BMP_GET_HT_2SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_2SS) >> 8) +#define RATE_BMP_GET_HT_3SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_3SS) >> 16) +#define RATE_BMP_GET_HT_4SS(_bmp_ht) ((_bmp_ht & RATE_BMP_HT_4SS) >> 24) + +/* used for rf_ctl_t.rate_bmp_vht_by_bw */ +#define RATE_BMP_VHT_1SS 0x000003FF +#define RATE_BMP_VHT_2SS 0x000FFC00 +#define RATE_BMP_VHT_3SS 0x3FF00000 +#define RATE_BMP_HAS_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS) +#define RATE_BMP_HAS_VHT_2SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_2SS) +#define RATE_BMP_HAS_VHT_3SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_3SS) +#define RATE_BMP_GET_VHT_1SS(_bmp_vht) (_bmp_vht & RATE_BMP_VHT_1SS) +#define RATE_BMP_GET_VHT_2SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_2SS) >> 10) +#define RATE_BMP_GET_VHT_3SS(_bmp_vht) ((_bmp_vht & RATE_BMP_VHT_3SS) >> 20) + +struct rf_ctl_t { + /* used for debug or by tx power limit */ + u16 rate_bmp_cck_ofdm; /* 20MHz */ + u32 rate_bmp_ht_by_bw[2]; /* 20MHz, 40MHz. 4SS supported */ + u32 rate_bmp_vht_by_bw[4]; /* 20MHz, 40MHz, 80MHz, 160MHz. up to 3SS supported */ + + /* used by tx power limit */ + u8 highest_ht_rate_bw_bmp; + u8 highest_vht_rate_bw_bmp; + +}; + +#define RTW_CAC_STOPPED 0 +#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED) +#define IS_CH_WAITING(rfctl) (!IS_CAC_STOPPED(rfctl) && time_after((unsigned long)(rfctl)->cac_end_time, (unsigned long)rtw_get_current_time())) +#define IS_UNDER_CAC(rfctl) (IS_CH_WAITING(rfctl) && time_after((unsigned long)rtw_get_current_time(), (unsigned long)(rfctl)->cac_start_time)) + + +struct halmac_indicator { + struct submit_ctx *sctx; + u8 *buffer; + u32 buf_size; + u32 ret_size; + u32 status; +}; + +struct halmacpriv { + /* flags */ + + /* For asynchronous functions */ + struct halmac_indicator *indicator; + +}; + +struct dvobj_priv { + /*-------- below is common data --------*/ + u8 chip_type; + u8 HardwareType; + u8 interface_type;/*USB,SDIO,SPI,PCI*/ + + ATOMIC_T bSurpriseRemoved; + ATOMIC_T bDriverStopped; + + s32 processing_dev_remove; + + struct debug_priv drv_dbg; + + _mutex hw_init_mutex; + _mutex h2c_fwcmd_mutex; + + + _mutex setch_mutex; + _mutex setbw_mutex; + _mutex rf_read_reg_mutex; + + unsigned char oper_channel; /* saved channel info when call set_channel_bw */ + unsigned char oper_bwmode; + unsigned char oper_ch_offset;/* PRIME_CHNL_OFFSET */ + u32 on_oper_ch_time; + + _adapter *padapters[CONFIG_IFACE_NUMBER];/*IFACE_ID_MAX*/ + u8 iface_nums; /* total number of ifaces used runtime */ + struct mi_state iface_state; + + u8 nr_ap_if; /* total interface s number of ap/go mode. */ + u32 inter_bcn_space; /* unit:ms */ + _queue ap_if_q; + + struct macid_ctl_t macid_ctl; + + struct cam_ctl_t cam_ctl; + struct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT]; + + + struct rf_ctl_t rf_ctl; + + /* For 92D, DMDP have 2 interface. */ + u8 InterfaceNumber; + u8 NumInterfaces; + + /* In /Out Pipe information */ + int RtInPipe[2]; + int RtOutPipe[4]; + u8 Queue2Pipe[HW_QUEUE_ENTRY];/* for out pipe mapping */ + + u8 irq_alloc; + ATOMIC_T continual_io_error; + + ATOMIC_T disable_func; + + u8 xmit_block; + _lock xmit_block_lock; + + struct pwrctrl_priv pwrctl_priv; + + struct rtw_traffic_statistics traffic_stat; + + _thread_hdl_ rtnl_lock_holder; + + + _timer dynamic_chk_timer; /* dynamic/periodic check timer */ + + void *halmac; + struct halmacpriv hmpriv; + + /*-------- below is for SDIO INTERFACE --------*/ + +#ifdef INTF_DATA + INTF_DATA intf_data; +#endif +#ifdef INTF_OPS + INTF_OPS intf_ops; +#endif + /*-------- below is for PCIE INTERFACE --------*/ + + struct pci_dev *ppcidev; + + /* PCI MEM map */ + unsigned long pci_mem_end; /* shared mem end */ + unsigned long pci_mem_start; /* shared mem start */ + + /* PCI IO map */ + unsigned long pci_base_addr; /* device I/O address */ + + + /* PciBridge */ + struct pci_priv pcipriv; + + unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */ + u16 irqline; + u8 irq_enabled; + RT_ISR_CONTENT isr_content; + _lock irq_th_lock; + + /* ASPM */ + u8 const_pci_aspm; + u8 const_amdpci_aspm; + u8 const_hwsw_rfoff_d3; + u8 const_support_pciaspm; + /* pci-e bridge */ + u8 const_hostpci_aspm_setting; + /* pci-e device */ + u8 const_devicepci_aspm_setting; + u8 b_support_aspm; /* If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. */ + u8 b_support_backdoor; + u8 bdma64; + +}; + +#define DEV_STA_NUM(_dvobj) MSTATE_STA_NUM(&((_dvobj)->iface_state)) +#define DEV_STA_LD_NUM(_dvobj) MSTATE_STA_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_STA_LG_NUM(_dvobj) MSTATE_STA_LG_NUM(&((_dvobj)->iface_state)) +#define DEV_AP_NUM(_dvobj) MSTATE_AP_NUM(&((_dvobj)->iface_state)) +#define DEV_AP_LD_NUM(_dvobj) MSTATE_AP_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_ADHOC_NUM(_dvobj) MSTATE_ADHOC_NUM(&((_dvobj)->iface_state)) +#define DEV_ADHOC_LD_NUM(_dvobj) MSTATE_ADHOC_LD_NUM(&((_dvobj)->iface_state)) +#define DEV_WPS_NUM(_dvobj) MSTATE_WPS_NUM(&((_dvobj)->iface_state)) +#define DEV_ROCH_NUM(_dvobj) MSTATE_ROCH_NUM(&((_dvobj)->iface_state)) +#define DEV_MGMT_TX_NUM(_dvobj) MSTATE_MGMT_TX_NUM(&((_dvobj)->iface_state)) +#define DEV_U_CH(_dvobj) MSTATE_U_CH(&((_dvobj)->iface_state)) +#define DEV_U_BW(_dvobj) MSTATE_U_BW(&((_dvobj)->iface_state)) +#define DEV_U_OFFSET(_dvobj) MSTATE_U_OFFSET(&((_dvobj)->iface_state)) + +#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv)) +#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv) +#define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl)) +#define dvobj_to_sec_camctl(dvobj) (&(dvobj->cam_ctl)) +#define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv)) +#define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl)) +#define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl) + +static inline void dev_set_surprise_removed(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bSurpriseRemoved, _TRUE); +} +static inline void dev_clr_surprise_removed(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bSurpriseRemoved, _FALSE); +} +static inline void dev_set_drv_stopped(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bDriverStopped, _TRUE); +} +static inline void dev_clr_drv_stopped(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->bDriverStopped, _FALSE); +} +#define dev_is_surprise_removed(dvobj) (ATOMIC_READ(&dvobj->bSurpriseRemoved) == _TRUE) +#define dev_is_drv_stopped(dvobj) (ATOMIC_READ(&dvobj->bDriverStopped) == _TRUE) + +__maybe_unused static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) +{ + /* todo: get interface type from dvobj and the return the dev accordingly */ + return &dvobj->ppcidev->dev; +} + +_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj); +_adapter *dvobj_get_unregisterd_adapter(struct dvobj_priv *dvobj); +_adapter *dvobj_get_adapter_by_addr(struct dvobj_priv *dvobj, u8 *addr); +#define dvobj_get_primary_adapter(dvobj) ((dvobj)->padapters[IFACE_ID0]) + +enum _hw_port { + HW_PORT0, + HW_PORT1, + HW_PORT2, + HW_PORT3, + HW_PORT4, + MAX_HW_PORT, +}; + +enum _ADAPTER_TYPE { + PRIMARY_ADAPTER, + VIRTUAL_ADAPTER, + MAX_ADAPTER = 0xFF, +}; + +typedef enum _DRIVER_STATE { + DRIVER_NORMAL = 0, + DRIVER_DISAPPEAR = 1, + DRIVER_REPLACE_DONGLE = 2, +} DRIVER_STATE; + +enum _NAPI_STATE { + NAPI_DISABLE = 0, + NAPI_ENABLE = 1, +}; + + + +struct tsf_info { + u8 sync_port;/*tsf sync from portx*/ + u8 offset; /*tsf timer offset*/ +}; + +#define ADAPTER_TX_BW_2G(adapter) BW_MODE_2G((adapter)->driver_tx_bw_mode) +#define ADAPTER_TX_BW_5G(adapter) BW_MODE_5G((adapter)->driver_tx_bw_mode) + +struct _ADAPTER { + int DriverState;/* for disable driver using module, use dongle to replace module. */ + int pid[3];/* process id from UI, 0:wps, 1:hostapd, 2:dhcpcd */ + int bDongle;/* build-in module or external dongle */ + + _list list; + + struct dvobj_priv *dvobj; + struct mlme_priv mlmepriv; + struct mlme_ext_priv mlmeextpriv; + struct cmd_priv cmdpriv; + struct evt_priv evtpriv; + /* struct io_queue *pio_queue; */ + struct io_priv iopriv; + struct xmit_priv xmitpriv; + struct recv_priv recvpriv; + struct sta_priv stapriv; + struct security_priv securitypriv; + _lock security_key_mutex; /* add for CONFIG_IEEE80211W, none 11w also can use */ + struct registry_priv registrypriv; + + struct led_priv ledpriv; + + struct napi_struct napi; + u8 napi_state; + + struct mp_priv mppriv; + + + struct hostapd_priv *phostapdpriv; + + u32 setband; + ATOMIC_T bandskip; + + struct wifidirect_info wdinfo; + + struct wifi_display_info wfd_info; + + ERROR_CODE LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */ + + PVOID HalData; + u32 hal_data_sz; + struct hal_ops hal_func; + + u32 IsrContent; + u32 ImrContent; + + u8 EepromAddressSize; + u8 bDriverIsGoingToUnload; + u8 init_adpt_in_progress; + u8 bHaltInProgress; + _thread_hdl_ cmdThread; + _thread_hdl_ evtThread; + _thread_hdl_ xmitThread; + _thread_hdl_ recvThread; + + u8 registered; + + u32(*intf_init)(struct dvobj_priv *dvobj); + void (*intf_deinit)(struct dvobj_priv *dvobj); + int (*intf_alloc_irq)(struct dvobj_priv *dvobj); + void (*intf_free_irq)(struct dvobj_priv *dvobj); + + void (*intf_start)(_adapter *adapter); + void (*intf_stop)(_adapter *adapter); + + _nic_hdl pnetdev; + char old_ifname[IFNAMSIZ]; + + /* used by rtw_rereg_nd_name related function */ + struct rereg_nd_name_data { + _nic_hdl old_pnetdev; + char old_ifname[IFNAMSIZ]; + u8 old_ips_mode; + u8 old_bRegUseLed; + } rereg_nd_name_priv; + + u8 ndev_unregistering; + int bup; + struct net_device_stats stats; + struct iw_statistics iwstats; + struct proc_dir_entry *dir_dev;/* for proc directory */ + struct proc_dir_entry *dir_odm; + + + + u8 mac_addr[ETH_ALEN]; + int net_closed; + + u8 netif_up; + + u8 bFWReady; + u8 bBTFWReady; + u8 bLinkInfoDump; + u8 bRxRSSIDisplay; + /* Added by Albert 2012/10/26 */ + /* The driver will show up the desired channel number when this flag is 1. */ + u8 bNotifyChannelChange; + /* Added by Albert 2012/12/06 */ + /* The driver will show the current P2P status when the upper application reads it. */ + u8 bShowGetP2PState; + + u8 isprimary; /* is primary adapter or not */ + /* notes: + ** if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER + ** if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for VIRTUAL_ADAPTER + ** refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff.*/ + u8 adapter_type;/*be used in Multi-interface to recognize whether is PRIMARY_ADAPTER or not(PRIMARY_ADAPTER/VIRTUAL_ADAPTER) .*/ + u8 hw_port; /*interface port type, it depends on HW port */ + struct tsf_info tsf; + + /*extend to support multi interface*/ + /*IFACE_ID0 is equals to PRIMARY_ADAPTER + IFACE_ID1 is equals to VIRTUAL_ADAPTER*/ + u8 iface_id; + + _lock br_ext_lock; + /* unsigned int macclone_completed; */ + struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; + int pppoe_connection_in_progress; + unsigned char pppoe_addr[MACADDRLEN]; + unsigned char scdb_mac[MACADDRLEN]; + unsigned char scdb_ip[4]; + struct nat25_network_db_entry *scdb_entry; + unsigned char br_mac[MACADDRLEN]; + unsigned char br_ip[4]; + + struct br_ext_info ethBrExtInfo; + + + + /* for debug purpose */ + u8 fix_rate; + u8 fix_bw; + u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */ + u8 power_offset; + u8 driver_tx_bw_mode; + u8 rsvd_page_offset; + u8 rsvd_page_num; + + u8 driver_vcs_en; /* Enable=1, Disable=0 driver control vrtl_carrier_sense for tx */ + u8 driver_vcs_type;/* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ + u8 driver_ampdu_spacing;/* driver control AMPDU Density for peer sta's rx */ + u8 driver_rx_ampdu_factor;/* 0xff: disable drv ctrl, 0:8k, 1:16k, 2:32k, 3:64k; */ + u8 driver_rx_ampdu_spacing; /* driver control Rx AMPDU Density */ + u8 fix_rx_ampdu_accept; + u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */ + u8 driver_tx_max_agg_num; /*fix tx desc max agg num , 0xff: disable drv ctrl*/ + unsigned char in_cta_test; + + +}; + +#define adapter_to_dvobj(adapter) ((adapter)->dvobj) +#define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter))) +#define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter))) +#define adapter_wdev_data(adapter) (&((adapter)->wdev_data)) +#if defined(RTW_SINGLE_WIPHY) +#define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter)) +#else +#define adapter_to_wiphy(adapter) ((adapter)->wiphy) +#endif + +#define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter))) + +#define adapter_mac_addr(adapter) (adapter->mac_addr) + +#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv) +#define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo) + +#define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type) +#define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType) +#define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type) + +#define rtw_get_mi_nums(adapter) (((PADAPTER)adapter)->dvobj->iface_nums) + +static inline void rtw_set_surprise_removed(_adapter *padapter) +{ + dev_set_surprise_removed(adapter_to_dvobj(padapter)); +} +static inline void rtw_clr_surprise_removed(_adapter *padapter) +{ + dev_clr_surprise_removed(adapter_to_dvobj(padapter)); +} +static inline void rtw_set_drv_stopped(_adapter *padapter) +{ + dev_set_drv_stopped(adapter_to_dvobj(padapter)); +} +static inline void rtw_clr_drv_stopped(_adapter *padapter) +{ + dev_clr_drv_stopped(adapter_to_dvobj(padapter)); +} +#define rtw_is_surprise_removed(padapter) (dev_is_surprise_removed(adapter_to_dvobj(padapter))) +#define rtw_is_drv_stopped(padapter) (dev_is_drv_stopped(adapter_to_dvobj(padapter))) + +/* + * Function disabled. + * */ +#define DF_TX_BIT BIT0 /*write_port_cancel*/ +#define DF_RX_BIT BIT1 /*read_port_cancel*/ +#define DF_IO_BIT BIT2 + +/* #define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) */ +/* #define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) */ +__inline static void RTW_DISABLE_FUNC(_adapter *padapter, int func_bit) +{ + int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); + df |= func_bit; + ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); +} + +__inline static void RTW_ENABLE_FUNC(_adapter *padapter, int func_bit) +{ + int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); + df &= ~(func_bit); + ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); +} + +#define RTW_CANNOT_RUN(padapter) \ + (rtw_is_surprise_removed(padapter) || \ + rtw_is_drv_stopped(padapter)) + +#define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit)) + +#define RTW_CANNOT_IO(padapter) \ + (rtw_is_surprise_removed(padapter) || \ + RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT)) + +#define RTW_CANNOT_RX(padapter) \ + (RTW_CANNOT_RUN(padapter) || \ + RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT)) + +#define RTW_CANNOT_TX(padapter) \ + (RTW_CANNOT_RUN(padapter) || \ + RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT)) + + +int rtw_suspend_free_assoc_resource(_adapter *padapter); + +/* HCI Related header file */ +#include <pci_osintf.h> +#include <pci_ops.h> +#include <pci_hal.h> + +#endif /* __DRV_TYPES_H__ */ diff --git a/drivers/staging/rtl8821ce/include/drv_types_linux.h b/drivers/staging/rtl8821ce/include/drv_types_linux.h new file mode 100644 index 000000000000..4c14a8b519cd --- /dev/null +++ b/drivers/staging/rtl8821ce/include/drv_types_linux.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_TYPES_LINUX_H__ +#define __DRV_TYPES_LINUX_H__ + +#endif diff --git a/drivers/staging/rtl8821ce/include/drv_types_pci.h b/drivers/staging/rtl8821ce/include/drv_types_pci.h new file mode 100644 index 000000000000..8bc734190fa2 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/drv_types_pci.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_TYPES_PCI_H__ +#define __DRV_TYPES_PCI_H__ + + #include <linux/pci.h> + +#define INTEL_VENDOR_ID 0x8086 +#define SIS_VENDOR_ID 0x1039 +#define ATI_VENDOR_ID 0x1002 +#define ATI_DEVICE_ID 0x7914 +#define AMD_VENDOR_ID 0x1022 + +#define PCI_MAX_BRIDGE_NUMBER 255 +#define PCI_MAX_DEVICES 32 +#define PCI_MAX_FUNCTION 8 + +#define PCI_CONF_ADDRESS 0x0CF8 /* PCI Configuration Space Address */ +#define PCI_CONF_DATA 0x0CFC /* PCI Configuration Space Data */ + +#define PCI_CLASS_BRIDGE_DEV 0x06 +#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 + +#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10 + +#define U1DONTCARE 0xFF +#define U2DONTCARE 0xFFFF +#define U4DONTCARE 0xFFFFFFFF + +#define PCI_VENDER_ID_REALTEK 0x10ec + +#define HAL_HW_PCI_8180_DEVICE_ID 0x8180 +#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 /* 8185 or 8185b */ +#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 /* 8185b */ +#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 /* 8185b */ +#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 /* 8190 */ +#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 /* 8723E */ +#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 /* 8192 PCI-E */ +#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 /* 8192 SE */ +#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 /* 8192 SE */ +#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 /* 8191 SE Crab */ +#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 /* 8191 SE RE */ +#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 /* 8191 SE Unicron */ +#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 /* 8190 PCI for Ceraga */ +#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 /* 8190 Cardbus for Ceraga */ +#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 /* 8192e PCIE for Ceraga */ +#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 /* 8192e Express Card for Ceraga */ +#define HAL_HW_PCI_700F_DEVICE_ID 0x700F +#define HAL_HW_PCI_701F_DEVICE_ID 0x701F +#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304 +#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179 + +#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 /* 8190 support 16 pages of IO registers */ +#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 /* 8192 support 16 pages of IO registers */ +#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 /* 8192 support 16 pages of IO registers */ +#define HAL_HW_PCI_REVISION_ID_8192SE 0x10 +#define HAL_HW_PCI_REVISION_ID_8192CE 0x1 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 /* 8192 support 16 pages of IO registers */ +#define HAL_HW_PCI_REVISION_ID_8192DE 0x0 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 /* 8192 support 16 pages of IO registers */ + +enum pci_bridge_vendor { + PCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */ + PCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */ + PCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */ + PCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */ + PCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */ + PCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */ +} ; + +/* copy this data structor defination from MSDN SDK */ +typedef struct _PCI_COMMON_CONFIG { + u16 VendorID; + u16 DeviceID; + u16 Command; + u16 Status; + u8 RevisionID; + u8 ProgIf; + u8 SubClass; + u8 BaseClass; + u8 CacheLineSize; + u8 LatencyTimer; + u8 HeaderType; + u8 BIST; + + union { + struct _PCI_HEADER_TYPE_0 { + u32 BaseAddresses[6]; + u32 CIS; + u16 SubVendorID; + u16 SubSystemID; + u32 ROMBaseAddress; + u8 CapabilitiesPtr; + u8 Reserved1[3]; + u32 Reserved2; + + u8 InterruptLine; + u8 InterruptPin; + u8 MinimumGrant; + u8 MaximumLatency; + } type0; + } u; + + u8 DeviceSpecific[108]; +} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG; + +typedef struct _RT_PCI_CAPABILITIES_HEADER { + u8 CapabilityID; + u8 Next; +} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER; + +struct pci_priv { + BOOLEAN pci_clk_req; + + u8 pciehdr_offset; + /* PCIeCap is only differece between B-cut and C-cut. */ + /* Configuration Space offset 72[7:4] */ + /* 0: A/B cut */ + /* 1: C cut and later. */ + u8 pcie_cap; + u8 linkctrl_reg; + + u8 busnumber; + u8 devnumber; + u8 funcnumber; + + u8 pcibridge_busnum; + u8 pcibridge_devnum; + u8 pcibridge_funcnum; + u8 pcibridge_vendor; + u16 pcibridge_vendorid; + u16 pcibridge_deviceid; + u8 pcibridge_pciehdr_offset; + u8 pcibridge_linkctrlreg; + + u8 amd_l1_patch; +}; + +typedef struct _RT_ISR_CONTENT { + union { + u32 IntArray[2]; + u32 IntReg4Byte; + u16 IntReg2Byte; + }; +} RT_ISR_CONTENT, *PRT_ISR_CONTENT; + +/* #define RegAddr(addr) (addr + 0xB2000000UL) */ +/* some platform macros will def here */ +static inline void NdisRawWritePortUlong(u32 port, u32 val) +{ + outl(val, port); + /* writel(val, (u8 *)RegAddr(port)); */ +} + +static inline void NdisRawWritePortUchar(u32 port, u8 val) +{ + outb(val, port); + /* writeb(val, (u8 *)RegAddr(port)); */ +} + +static inline void NdisRawReadPortUchar(u32 port, u8 *pval) +{ + *pval = inb(port); + /* *pval = readb((u8 *)RegAddr(port)); */ +} + +static inline void NdisRawReadPortUshort(u32 port, u16 *pval) +{ + *pval = inw(port); + /* *pval = readw((u8 *)RegAddr(port)); */ +} + +static inline void NdisRawReadPortUlong(u32 port, u32 *pval) +{ + *pval = inl(port); + /* *pval = readl((u8 *)RegAddr(port)); */ +} + +#endif diff --git a/drivers/staging/rtl8821ce/include/ethernet.h b/drivers/staging/rtl8821ce/include/ethernet.h new file mode 100644 index 000000000000..560eaf511ea0 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/ethernet.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*! \file */ +#ifndef __INC_ETHERNET_H +#define __INC_ETHERNET_H + +#define ETHERNET_ADDRESS_LENGTH 6 /* !< Ethernet Address Length */ +#define ETHERNET_HEADER_SIZE 14 /* !< Ethernet Header Length */ +#define LLC_HEADER_SIZE 6 /* !< LLC Header Length */ +#define TYPE_LENGTH_FIELD_SIZE 2 /* !< Type/Length Size */ +#define MINIMUM_ETHERNET_PACKET_SIZE 60 /* !< Minimum Ethernet Packet Size */ +#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 /* !< Maximum Ethernet Packet Size */ + +#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01) != 0) /* !< Is Multicast Address? */ +#define RT_ETH_IS_BROADCAST(_pAddr) (\ + ((UCHAR *)(_pAddr))[0] == 0xff && \ + ((UCHAR *)(_pAddr))[1] == 0xff && \ + ((UCHAR *)(_pAddr))[2] == 0xff && \ + ((UCHAR *)(_pAddr))[3] == 0xff && \ + ((UCHAR *)(_pAddr))[4] == 0xff && \ + ((UCHAR *)(_pAddr))[5] == 0xff) /* !< Is Broadcast Address? */ + +#endif /* #ifndef __INC_ETHERNET_H */ diff --git a/drivers/staging/rtl8821ce/include/h2clbk.h b/drivers/staging/rtl8821ce/include/h2clbk.h new file mode 100644 index 000000000000..ac0479dee514 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/h2clbk.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _H2CLBK_H_ + +void _lbk_cmd(PADAPTER Adapter); + +void _lbk_rsp(PADAPTER Adapter); + +void _lbk_evt(IN PADAPTER Adapter); + +void h2c_event_callback(unsigned char *dev, unsigned char *pbuf); diff --git a/drivers/staging/rtl8821ce/include/hal_btcoex.h b/drivers/staging/rtl8821ce/include/hal_btcoex.h new file mode 100644 index 000000000000..de73d225355e --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_btcoex.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_BTCOEX_H__ +#define __HAL_BTCOEX_H__ + +#include <drv_types.h> + +/* Some variables can't get from outsrc BT-Coex, + * so we need to save here */ +typedef struct _BT_COEXIST { + u8 bBtExist; + u8 btTotalAntNum; + u8 btChipType; + u8 bInitlized; + u8 btAntisolation; +} BT_COEXIST, *PBT_COEXIST; + +void DBG_BT_INFO(u8 *dbgmsg); + +void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist); +u8 hal_btcoex_IsBtExist(PADAPTER padapter); +u8 hal_btcoex_IsBtDisabled(PADAPTER); +void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType); +void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum); + +u8 hal_btcoex_Initialize(PADAPTER padapter); +void hal_btcoex_PowerOnSetting(PADAPTER padapter); +void hal_btcoex_PowerOffSetting(PADAPTER padapter); +void hal_btcoex_PreLoadFirmware(PADAPTER padapter); +void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly); + +void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type); +void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type); +void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type); +void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action); +void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus); +void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType); +void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state); +void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); +void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); +void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state); +void hal_btcoex_HaltNotify(PADAPTER padapter, u8 do_halt); +void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter); + +void hal_btcoex_Hanlder(PADAPTER padapter); + +s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter); +s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter); +u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter); +void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual); +u8 hal_btcoex_1Ant(PADAPTER padapter); +u8 hal_btcoex_IsBtControlLps(PADAPTER); +u8 hal_btcoex_IsLpsOn(PADAPTER); +u8 hal_btcoex_RpwmVal(PADAPTER); +u8 hal_btcoex_LpsVal(PADAPTER); +u32 hal_btcoex_GetRaMask(PADAPTER); +void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen); +void hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize); +void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule); +u32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize); +u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER); +u8 hal_btcoex_IsBtLinkExist(PADAPTER); +void hal_btcoex_SetBtPatchVersion(PADAPTER, u16 btHciVer, u16 btPatchVer); +void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion); +void hal_btcoex_SendScanNotify(PADAPTER, u8 type); +void hal_btcoex_StackUpdateProfileInfo(void); +void hal_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON); +void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype); + int hal_btcoex_AntIsolationConfig_ParaFile(IN PADAPTER Adapter, IN char *pFileName); + int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char *buffer); +u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); +u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); +void hal_btcoex_set_rfe_type(u8 type); +void hal_btcoex_switchband_notify(u8 under_scan, u8 band_type); + +#endif /* !__HAL_BTCOEX_H__ */ diff --git a/drivers/staging/rtl8821ce/include/hal_btcoex_wifionly.h b/drivers/staging/rtl8821ce/include/hal_btcoex_wifionly.h new file mode 100644 index 000000000000..89b3ad5321c9 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_btcoex_wifionly.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HALBTC_WIFIONLY_H__ +#define __HALBTC_WIFIONLY_H__ + +#include <drv_types.h> +#include <hal_data.h> + +typedef enum _WIFIONLY_CHIP_INTERFACE { + WIFIONLY_INTF_UNKNOWN = 0, + WIFIONLY_INTF_PCI = 1, + WIFIONLY_INTF_USB = 2, + WIFIONLY_INTF_SDIO = 3, + WIFIONLY_INTF_MAX +} WIFIONLY_CHIP_INTERFACE, *PWIFIONLY_CHIP_INTERFACE; + +typedef enum _WIFIONLY_CUSTOMER_ID { + CUSTOMER_NORMAL = 0, + CUSTOMER_HP_1 = 1 +} WIFIONLY_CUSTOMER_ID, *PWIFIONLY_CUSTOMER_ID; + +struct wifi_only_haldata { + u16 customer_id; + u8 efuse_pg_antnum; + u8 efuse_pg_antpath; + u8 rfe_type; + u8 ant_div_cfg; +}; + +struct wifi_only_cfg { + PVOID Adapter; + struct wifi_only_haldata haldata_info; + WIFIONLY_CHIP_INTERFACE chip_interface; +}; + +void halwifionly_write1byte(PVOID pwifionlyContext, u32 RegAddr, u8 Data); +void halwifionly_write2byte(PVOID pwifionlyContext, u32 RegAddr, u16 Data); +void halwifionly_write4byte(PVOID pwifionlyContext, u32 RegAddr, u32 Data); +u8 halwifionly_read1byte(PVOID pwifionlyContext, u32 RegAddr); +u16 halwifionly_read2byte(PVOID pwifionlyContext, u32 RegAddr); +u32 halwifionly_read4byte(PVOID pwifionlyContext, u32 RegAddr); +void halwifionly_bitmaskwrite1byte(PVOID pwifionlyContext, u32 regAddr, u8 bitMask, u8 data); +void halwifionly_phy_set_rf_reg(PVOID pwifionlyContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); +void halwifionly_phy_set_bb_reg(PVOID pwifionlyContext, u32 RegAddr, u32 BitMask, u32 Data); +void hal_btcoex_wifionly_switchband_notify(PADAPTER padapter); +void hal_btcoex_wifionly_scan_notify(PADAPTER padapter); +void hal_btcoex_wifionly_hw_config(PADAPTER padapter); +void hal_btcoex_wifionly_initlizevariables(PADAPTER padapter); +#endif diff --git a/drivers/staging/rtl8821ce/include/hal_com.h b/drivers/staging/rtl8821ce/include/hal_com.h new file mode 100644 index 000000000000..a596df87131b --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_com.h @@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COMMON_H__ +#define __HAL_COMMON_H__ + +#include "HalVerDef.h" +#include "hal_pg.h" +#include "hal_phy.h" +#include "hal_phy_reg.h" +#include "hal_com_reg.h" +#include "hal_com_phycfg.h" +#include "../hal/hal_com_c2h.h" + +/*------------------------------ Tx Desc definition Macro ------------------------*/ +/* #pragma mark -- Tx Desc related definition. -- */ +/* ---------------------------------------------------------------------------- + * ----------------------------------------------------------- + * Rate + * ----------------------------------------------------------- + * CCK Rates, TxHT = 0 */ +#define DESC_RATE1M 0x00 +#define DESC_RATE2M 0x01 +#define DESC_RATE5_5M 0x02 +#define DESC_RATE11M 0x03 + +/* OFDM Rates, TxHT = 0 */ +#define DESC_RATE6M 0x04 +#define DESC_RATE9M 0x05 +#define DESC_RATE12M 0x06 +#define DESC_RATE18M 0x07 +#define DESC_RATE24M 0x08 +#define DESC_RATE36M 0x09 +#define DESC_RATE48M 0x0a +#define DESC_RATE54M 0x0b + +/* MCS Rates, TxHT = 1 */ +#define DESC_RATEMCS0 0x0c +#define DESC_RATEMCS1 0x0d +#define DESC_RATEMCS2 0x0e +#define DESC_RATEMCS3 0x0f +#define DESC_RATEMCS4 0x10 +#define DESC_RATEMCS5 0x11 +#define DESC_RATEMCS6 0x12 +#define DESC_RATEMCS7 0x13 +#define DESC_RATEMCS8 0x14 +#define DESC_RATEMCS9 0x15 +#define DESC_RATEMCS10 0x16 +#define DESC_RATEMCS11 0x17 +#define DESC_RATEMCS12 0x18 +#define DESC_RATEMCS13 0x19 +#define DESC_RATEMCS14 0x1a +#define DESC_RATEMCS15 0x1b +#define DESC_RATEMCS16 0x1C +#define DESC_RATEMCS17 0x1D +#define DESC_RATEMCS18 0x1E +#define DESC_RATEMCS19 0x1F +#define DESC_RATEMCS20 0x20 +#define DESC_RATEMCS21 0x21 +#define DESC_RATEMCS22 0x22 +#define DESC_RATEMCS23 0x23 +#define DESC_RATEMCS24 0x24 +#define DESC_RATEMCS25 0x25 +#define DESC_RATEMCS26 0x26 +#define DESC_RATEMCS27 0x27 +#define DESC_RATEMCS28 0x28 +#define DESC_RATEMCS29 0x29 +#define DESC_RATEMCS30 0x2A +#define DESC_RATEMCS31 0x2B +#define DESC_RATEVHTSS1MCS0 0x2C +#define DESC_RATEVHTSS1MCS1 0x2D +#define DESC_RATEVHTSS1MCS2 0x2E +#define DESC_RATEVHTSS1MCS3 0x2F +#define DESC_RATEVHTSS1MCS4 0x30 +#define DESC_RATEVHTSS1MCS5 0x31 +#define DESC_RATEVHTSS1MCS6 0x32 +#define DESC_RATEVHTSS1MCS7 0x33 +#define DESC_RATEVHTSS1MCS8 0x34 +#define DESC_RATEVHTSS1MCS9 0x35 +#define DESC_RATEVHTSS2MCS0 0x36 +#define DESC_RATEVHTSS2MCS1 0x37 +#define DESC_RATEVHTSS2MCS2 0x38 +#define DESC_RATEVHTSS2MCS3 0x39 +#define DESC_RATEVHTSS2MCS4 0x3A +#define DESC_RATEVHTSS2MCS5 0x3B +#define DESC_RATEVHTSS2MCS6 0x3C +#define DESC_RATEVHTSS2MCS7 0x3D +#define DESC_RATEVHTSS2MCS8 0x3E +#define DESC_RATEVHTSS2MCS9 0x3F +#define DESC_RATEVHTSS3MCS0 0x40 +#define DESC_RATEVHTSS3MCS1 0x41 +#define DESC_RATEVHTSS3MCS2 0x42 +#define DESC_RATEVHTSS3MCS3 0x43 +#define DESC_RATEVHTSS3MCS4 0x44 +#define DESC_RATEVHTSS3MCS5 0x45 +#define DESC_RATEVHTSS3MCS6 0x46 +#define DESC_RATEVHTSS3MCS7 0x47 +#define DESC_RATEVHTSS3MCS8 0x48 +#define DESC_RATEVHTSS3MCS9 0x49 +#define DESC_RATEVHTSS4MCS0 0x4A +#define DESC_RATEVHTSS4MCS1 0x4B +#define DESC_RATEVHTSS4MCS2 0x4C +#define DESC_RATEVHTSS4MCS3 0x4D +#define DESC_RATEVHTSS4MCS4 0x4E +#define DESC_RATEVHTSS4MCS5 0x4F +#define DESC_RATEVHTSS4MCS6 0x50 +#define DESC_RATEVHTSS4MCS7 0x51 +#define DESC_RATEVHTSS4MCS8 0x52 +#define DESC_RATEVHTSS4MCS9 0x53 + +#define HDATA_RATE(rate)\ + (rate == DESC_RATE1M) ? "CCK_1M" :\ + (rate == DESC_RATE2M) ? "CCK_2M" :\ + (rate == DESC_RATE5_5M) ? "CCK5_5M" :\ + (rate == DESC_RATE11M) ? "CCK_11M" :\ + (rate == DESC_RATE6M) ? "OFDM_6M" :\ + (rate == DESC_RATE9M) ? "OFDM_9M" :\ + (rate == DESC_RATE12M) ? "OFDM_12M" :\ + (rate == DESC_RATE18M) ? "OFDM_18M" :\ + (rate == DESC_RATE24M) ? "OFDM_24M" :\ + (rate == DESC_RATE36M) ? "OFDM_36M" :\ + (rate == DESC_RATE48M) ? "OFDM_48M" :\ + (rate == DESC_RATE54M) ? "OFDM_54M" :\ + (rate == DESC_RATEMCS0) ? "MCS0" :\ + (rate == DESC_RATEMCS1) ? "MCS1" :\ + (rate == DESC_RATEMCS2) ? "MCS2" :\ + (rate == DESC_RATEMCS3) ? "MCS3" :\ + (rate == DESC_RATEMCS4) ? "MCS4" :\ + (rate == DESC_RATEMCS5) ? "MCS5" :\ + (rate == DESC_RATEMCS6) ? "MCS6" :\ + (rate == DESC_RATEMCS7) ? "MCS7" :\ + (rate == DESC_RATEMCS8) ? "MCS8" :\ + (rate == DESC_RATEMCS9) ? "MCS9" :\ + (rate == DESC_RATEMCS10) ? "MCS10" :\ + (rate == DESC_RATEMCS11) ? "MCS11" :\ + (rate == DESC_RATEMCS12) ? "MCS12" :\ + (rate == DESC_RATEMCS13) ? "MCS13" :\ + (rate == DESC_RATEMCS14) ? "MCS14" :\ + (rate == DESC_RATEMCS15) ? "MCS15" :\ + (rate == DESC_RATEMCS16) ? "MCS16" :\ + (rate == DESC_RATEMCS17) ? "MCS17" :\ + (rate == DESC_RATEMCS18) ? "MCS18" :\ + (rate == DESC_RATEMCS19) ? "MCS19" :\ + (rate == DESC_RATEMCS20) ? "MCS20" :\ + (rate == DESC_RATEMCS21) ? "MCS21" :\ + (rate == DESC_RATEMCS22) ? "MCS22" :\ + (rate == DESC_RATEMCS23) ? "MCS23" :\ + (rate == DESC_RATEVHTSS1MCS0) ? "VHTSS1MCS0" :\ + (rate == DESC_RATEVHTSS1MCS1) ? "VHTSS1MCS1" :\ + (rate == DESC_RATEVHTSS1MCS2) ? "VHTSS1MCS2" :\ + (rate == DESC_RATEVHTSS1MCS3) ? "VHTSS1MCS3" :\ + (rate == DESC_RATEVHTSS1MCS4) ? "VHTSS1MCS4" :\ + (rate == DESC_RATEVHTSS1MCS5) ? "VHTSS1MCS5" :\ + (rate == DESC_RATEVHTSS1MCS6) ? "VHTSS1MCS6" :\ + (rate == DESC_RATEVHTSS1MCS7) ? "VHTSS1MCS7" :\ + (rate == DESC_RATEVHTSS1MCS8) ? "VHTSS1MCS8" :\ + (rate == DESC_RATEVHTSS1MCS9) ? "VHTSS1MCS9" :\ + (rate == DESC_RATEVHTSS2MCS0) ? "VHTSS2MCS0" :\ + (rate == DESC_RATEVHTSS2MCS1) ? "VHTSS2MCS1" :\ + (rate == DESC_RATEVHTSS2MCS2) ? "VHTSS2MCS2" :\ + (rate == DESC_RATEVHTSS2MCS3) ? "VHTSS2MCS3" :\ + (rate == DESC_RATEVHTSS2MCS4) ? "VHTSS2MCS4" :\ + (rate == DESC_RATEVHTSS2MCS5) ? "VHTSS2MCS5" :\ + (rate == DESC_RATEVHTSS2MCS6) ? "VHTSS2MCS6" :\ + (rate == DESC_RATEVHTSS2MCS7) ? "VHTSS2MCS7" :\ + (rate == DESC_RATEVHTSS2MCS8) ? "VHTSS2MCS8" :\ + (rate == DESC_RATEVHTSS2MCS9) ? "VHTSS2MCS9" :\ + (rate == DESC_RATEVHTSS3MCS0) ? "VHTSS3MCS0" :\ + (rate == DESC_RATEVHTSS3MCS1) ? "VHTSS3MCS1" :\ + (rate == DESC_RATEVHTSS3MCS2) ? "VHTSS3MCS2" :\ + (rate == DESC_RATEVHTSS3MCS3) ? "VHTSS3MCS3" :\ + (rate == DESC_RATEVHTSS3MCS4) ? "VHTSS3MCS4" :\ + (rate == DESC_RATEVHTSS3MCS5) ? "VHTSS3MCS5" :\ + (rate == DESC_RATEVHTSS3MCS6) ? "VHTSS3MCS6" :\ + (rate == DESC_RATEVHTSS3MCS7) ? "VHTSS3MCS7" :\ + (rate == DESC_RATEVHTSS3MCS8) ? "VHTSS3MCS8" :\ + (rate == DESC_RATEVHTSS3MCS9) ? "VHTSS3MCS9" : "UNKNOWN" + +enum { + UP_LINK, + DOWN_LINK, +}; +typedef enum _RT_MEDIA_STATUS { + RT_MEDIA_DISCONNECT = 0, + RT_MEDIA_CONNECT = 1 +} RT_MEDIA_STATUS; + +#define MAX_DLFW_PAGE_SIZE 4096 /* @ page : 4k bytes */ +typedef enum _FIRMWARE_SOURCE { + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, /* from header file */ +} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; + +typedef enum _CH_SW_USE_CASE { + CH_SW_USE_CASE_TDLS = 0, + CH_SW_USE_CASE_MCC = 1 +} CH_SW_USE_CASE; + +typedef enum _WAKEUP_REASON{ + RX_PAIRWISEKEY = 0x01, + RX_GTK = 0x02, + RX_FOURWAY_HANDSHAKE = 0x03, + RX_DISASSOC = 0x04, + RX_DEAUTH = 0x08, + RX_ARP_REQUEST = 0x09, + FW_DECISION_DISCONNECT = 0x10, + RX_MAGIC_PKT = 0x21, + RX_UNICAST_PKT = 0x22, + RX_PATTERN_PKT = 0x23, + RTD3_SSID_MATCH = 0x24, + RX_REALWOW_V2_WAKEUP_PKT = 0x30, + RX_REALWOW_V2_ACK_LOST = 0x31, + ENABLE_FAIL_DMA_IDLE = 0x40, + ENABLE_FAIL_DMA_PAUSE = 0x41, + RTIME_FAIL_DMA_IDLE = 0x42, + RTIME_FAIL_DMA_PAUSE = 0x43, + RX_PNO = 0x55, + AP_OFFLOAD_WAKEUP = 0x66, + CLK_32K_UNLOCK = 0xFD, + CLK_32K_LOCK = 0xFE +}WAKEUP_REASON; + +/* + * Queue Select Value in TxDesc + * */ +#define QSLT_BK 0x2/* 0x01 */ +#define QSLT_BE 0x0 +#define QSLT_VI 0x5/* 0x4 */ +#define QSLT_VO 0x7/* 0x6 */ +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. + * #define MAX_TX_QUEUE 9 */ + +#define TX_SELE_HQ BIT(0) /* High Queue */ +#define TX_SELE_LQ BIT(1) /* Low Queue */ +#define TX_SELE_NQ BIT(2) /* Normal Queue */ +#define TX_SELE_EQ BIT(3) /* Extern Queue */ + +#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0)) +#define PageNum_256(_Len) (u32)(((_Len)>>8) + ((_Len) & 0xFF ? 1 : 0)) +#define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len) & 0x1FF ? 1 : 0)) +#define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1 : 0)) + +struct dbg_rx_counter { + u32 rx_pkt_ok; + u32 rx_pkt_crc_error; + u32 rx_pkt_drop; + u32 rx_ofdm_fa; + u32 rx_cck_fa; + u32 rx_ht_fa; +}; + + + +void rtw_dump_mac_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter); +void rtw_dump_phy_rx_counters(_adapter *padapter, struct dbg_rx_counter *rx_counter); +void rtw_reset_mac_rx_counters(_adapter *padapter); +void rtw_reset_phy_rx_counters(_adapter *padapter); +void rtw_reset_phy_trx_ok_counters(_adapter *padapter); + + +void dump_chip_info(HAL_VERSION ChipVersion); +void rtw_hal_config_rftype(PADAPTER padapter); + +#define BAND_CAP_2G BIT0 +#define BAND_CAP_5G BIT1 +#define BAND_CAP_BIT_NUM 2 + +#define BW_CAP_5M BIT0 +#define BW_CAP_10M BIT1 +#define BW_CAP_20M BIT2 +#define BW_CAP_40M BIT3 +#define BW_CAP_80M BIT4 +#define BW_CAP_160M BIT5 +#define BW_CAP_80_80M BIT6 +#define BW_CAP_BIT_NUM 7 + +#define PROTO_CAP_11B BIT0 +#define PROTO_CAP_11G BIT1 +#define PROTO_CAP_11N BIT2 +#define PROTO_CAP_11AC BIT3 +#define PROTO_CAP_BIT_NUM 4 + +#define WL_FUNC_P2P BIT0 +#define WL_FUNC_MIRACAST BIT1 +#define WL_FUNC_TDLS BIT2 +#define WL_FUNC_FTM BIT3 +#define WL_FUNC_BIT_NUM 4 + +int hal_spec_init(_adapter *adapter); +void dump_hal_spec(void *sel, _adapter *adapter); + +bool hal_chk_band_cap(_adapter *adapter, u8 cap); +bool hal_chk_bw_cap(_adapter *adapter, u8 cap); +bool hal_chk_proto_cap(_adapter *adapter, u8 cap); +bool hal_is_band_support(_adapter *adapter, u8 band); +bool hal_is_bw_support(_adapter *adapter, u8 bw); +bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode); +u8 hal_largest_bw(_adapter *adapter, u8 in_bw); + +bool hal_chk_wl_func(_adapter *adapter, u8 func); + +u8 hal_com_config_channel_plan( + IN PADAPTER padapter, + IN char *hw_alpha2, + IN u8 hw_chplan, + IN char *sw_alpha2, + IN u8 sw_chplan, + IN u8 def_chplan, + IN BOOLEAN AutoLoadFail +); + +int hal_config_macaddr(_adapter *adapter, bool autoload_fail); + +BOOLEAN +HAL_IsLegalChannel( + IN PADAPTER Adapter, + IN u32 Channel +); + +u8 MRateToHwRate(u8 rate); + +u8 hw_rate_to_m_rate(u8 rate); + +void HalSetBrateCfg( + IN PADAPTER Adapter, + IN u8 *mBratesOS, + OUT u16 *pBrateCfg); + +BOOLEAN +Hal_MappingOutPipe( + IN PADAPTER pAdapter, + IN u8 NumOutPipe +); + +void rtw_dump_fw_info(void *sel, _adapter *adapter); +void rtw_restore_mac_addr(_adapter *adapter);/*set mac addr when hal_init for all iface*/ +void rtw_hal_dump_macaddr(void *sel, _adapter *adapter); + +void rtw_init_hal_com_default_value(PADAPTER Adapter); + + +void rtw_hal_c2h_pkt_pre_hdl(_adapter *adapter, u8 *buf, u16 len); +void rtw_hal_c2h_pkt_hdl(_adapter *adapter, u8 *buf, u16 len); + +u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta); +u8 rtw_get_mgntframe_raid(_adapter *adapter, unsigned char network_type); +void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta); + +/* access HW only */ +u32 rtw_sec_read_cam(_adapter *adapter, u8 addr); +void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata); +void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key); +void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void rtw_sec_clr_cam_ent(_adapter *adapter, u8 id); +bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id); + +void rtw_hal_set_msr(_adapter *adapter, u8 net_type); +void rtw_hal_set_macaddr_port(_adapter *adapter, u8 *val); +void rtw_hal_get_macaddr_port(_adapter *adapter, u8 *mac_addr); + +void rtw_hal_set_bssid(_adapter *adapter, u8 *val); + +void hw_var_port_switch(_adapter *adapter); + +void SetHwReg(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg(PADAPTER padapter, u8 variable, u8 *val); +void rtw_hal_check_rxfifo_full(_adapter *adapter); +void rtw_hal_reqtxrpt(_adapter *padapter, u8 macid); + +u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); +u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); + +BOOLEAN +eqNByte( + u8 *str1, + u8 *str2, + u32 num +); + +u32 +MapCharToHexDigit( + IN char chTmp +); + +BOOLEAN +GetHexValueFromString( + IN char *szStr, + IN OUT u32 *pu4bVal, + IN OUT u32 *pu4bMove +); + +BOOLEAN +GetFractionValueFromString( + IN char *szStr, + IN OUT u8 *pInteger, + IN OUT u8 *pFraction, + IN OUT u32 *pu4bMove +); + +BOOLEAN +IsCommentString( + IN char *szStr +); + +BOOLEAN +ParseQualifiedString( + IN char *In, + IN OUT u32 *Start, + OUT char *Out, + IN char LeftQualifier, + IN char RightQualifier +); + +BOOLEAN +GetU1ByteIntegerFromStringInDecimal( + IN char *Str, + IN OUT u8 *pInt +); + +BOOLEAN +isAllSpaceOrTab( + u8 *data, + u8 size +); + +void linked_info_dump(_adapter *padapter, u8 benable); + void rtw_get_raw_rssi_info(void *sel, _adapter *padapter); + void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel); + +void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe); +#define HWSET_MAX_SIZE 1024 +#define EFUSE_FILE_COLUMN_NUM 16 + +int check_phy_efuse_tx_power_info_valid(PADAPTER padapter); +int hal_efuse_macaddr_offset(_adapter *adapter); +int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr); +void rtw_dump_cur_efuse(PADAPTER padapter); + + +void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer); +u8 rtw_hal_busagg_qsel_check(_adapter *padapter, u8 pre_qsel, u8 next_qsel); +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2); +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet); + + +void rtw_get_noise(_adapter *padapter); +u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid); +u8 rtw_get_current_tx_sgi(_adapter *padapter, u8 macid); +void rtw_hal_construct_NullFunctionData(PADAPTER, u8 *pframe, u32 *pLength, u8 *StaAddr, u8 bQoS, u8 AC, u8 bEosp, u8 bForcePowerSave); + +void rtw_hal_set_fw_rsvd_page(_adapter *adapter, bool finished); + + + +s8 rtw_hal_ch_sw_iqk_info_search(_adapter *padapter, u8 central_chnl, u8 bw_mode); +void rtw_hal_ch_sw_iqk_info_backup(_adapter *adapter); +void rtw_hal_ch_sw_iqk_info_restore(_adapter *padapter, u8 ch_sw_use_case); + + +typedef enum _HAL_PHYDM_OPS { + HAL_PHYDM_DIS_ALL_FUNC, + HAL_PHYDM_FUNC_SET, + HAL_PHYDM_FUNC_CLR, + HAL_PHYDM_ABILITY_BK, + HAL_PHYDM_ABILITY_RESTORE, + HAL_PHYDM_ABILITY_SET, + HAL_PHYDM_ABILITY_GET, +} HAL_PHYDM_OPS; + +#define DYNAMIC_FUNC_DISABLE (0x0) +u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability); + +#define rtw_phydm_func_disable_all(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0) + +#define rtw_phydm_func_for_offchannel(adapter) \ + do { \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ + if (rtw_odm_adaptivity_needed(adapter)) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ + } while (0) + +#define rtw_phydm_func_set(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ability) + +#define rtw_phydm_func_clr(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability) + +#define rtw_phydm_ability_backup(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0) + +#define rtw_phydm_ability_restore(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0) + +#define rtw_phydm_ability_set(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_SET, ability) + +static inline u32 rtw_phydm_ability_get(_adapter *adapter) +{ + return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0); +} + +extern char *rtw_phy_file_path; +extern char rtw_phy_para_file_path[PATH_LENGTH_MAX]; +#define GetLineFromBuffer(buffer) strsep(&buffer, "\r\n") + +void update_IOT_info(_adapter *padapter); + + +void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap); +void rtw_hal_correct_tsf(_adapter *padapter, u8 hw_port, u64 tsf); + +void ResumeTxBeacon(_adapter *padapter); +void StopTxBeacon(_adapter *padapter); + + + + +int rtw_hal_get_rsvd_page(_adapter *adapter, u32 page_offset, u32 page_num, u8 *buffer, u32 buffer_size); + +void rtw_dump_phy_cap(void *sel, _adapter *adapter); +void rtw_dump_rsvd_page(void *sel, _adapter *adapter, u8 page_offset, u8 page_num); + + +void rtw_set_p2p_ps_offload_cmd(_adapter *adapter, u8 p2p_ps_state); + +#endif /* __HAL_COMMON_H__ */ diff --git a/drivers/staging/rtl8821ce/include/hal_com_h2c.h b/drivers/staging/rtl8821ce/include/hal_com_h2c.h new file mode 100644 index 000000000000..4fe4043a31d9 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_com_h2c.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __COMMON_H2C_H__ +#define __COMMON_H2C_H__ + +/* --------------------------------------------------------------------------------------------------------- + * ---------------------------------- H2C CMD DEFINITION ------------------------------------------------ + * --------------------------------------------------------------------------------------------------------- + * 88e, 8723b, 8812, 8821, 92e use the same FW code base */ +enum h2c_cmd { + /* Common Class: 000 */ + H2C_RSVD_PAGE = 0x00, + H2C_MEDIA_STATUS_RPT = 0x01, + H2C_SCAN_ENABLE = 0x02, + H2C_KEEP_ALIVE = 0x03, + H2C_DISCON_DECISION = 0x04, + H2C_PSD_OFFLOAD = 0x05, + H2C_CUSTOMER_STR_REQ = 0x06, + H2C_AP_OFFLOAD = 0x08, + H2C_BCN_RSVDPAGE = 0x09, + H2C_PROBERSP_RSVDPAGE = 0x0A, + H2C_FCS_RSVDPAGE = 0x10, + H2C_FCS_INFO = 0x11, + H2C_AP_WOW_GPIO_CTRL = 0x13, + H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C, + + /* PoweSave Class: 001 */ + H2C_SET_PWR_MODE = 0x20, + H2C_PS_TUNING_PARA = 0x21, + H2C_PS_TUNING_PARA2 = 0x22, + H2C_P2P_LPS_PARAM = 0x23, + H2C_P2P_PS_OFFLOAD = 0x24, + H2C_PS_SCAN_ENABLE = 0x25, + H2C_SAP_PS_ = 0x26, + H2C_INACTIVE_PS_ = 0x27, /* Inactive_PS */ + H2C_FWLPS_IN_IPS_ = 0x28, + + /* Dynamic Mechanism Class: 010 */ + H2C_MACID_CFG = 0x40, + H2C_TXBF = 0x41, + H2C_RSSI_SETTING = 0x42, + H2C_AP_REQ_TXRPT = 0x43, + H2C_INIT_RATE_COLLECT = 0x44, + H2C_IQ_CALIBRATION = 0x45, + + H2C_RA_MASK_3SS = 0x46,/* for 8814A */ + H2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */ + H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */ + + H2C_FW_TRACE_EN = 0x49, + + /* BT Class: 011 */ + H2C_B_TYPE_TDMA = 0x60, + H2C_BT_INFO = 0x61, + H2C_FORCE_BT_TXPWR = 0x62, + H2C_BT_IGNORE_WLANACT = 0x63, + H2C_DAC_SWING_VALUE = 0x64, + H2C_ANT_SEL_RSV = 0x65, + H2C_WL_OPMODE = 0x66, + H2C_BT_MP_OPER = 0x67, + H2C_BT_CONTROL = 0x68, + H2C_BT_WIFI_CTRL = 0x69, + H2C_BT_FW_PATCH = 0x6A, + /* WOWLAN Class: 100 */ + H2C_WOWLAN = 0x80, + H2C_REMOTE_WAKE_CTRL = 0x81, + H2C_AOAC_GLOBAL_INFO = 0x82, + H2C_AOAC_RSVD_PAGE = 0x83, + H2C_AOAC_RSVD_PAGE2 = 0x84, + H2C_D0_SCAN_OFFLOAD_CTRL = 0x85, + H2C_D0_SCAN_OFFLOAD_INFO = 0x86, + H2C_CHNL_SWITCH_OFFLOAD = 0x87, + H2C_AOAC_RSVDPAGE3 = 0x88, + H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A, + H2C_P2P_OFFLOAD = 0x8B, + + H2C_RESET_TSF = 0xC0, + H2C_BCNHWSEQ = 0xC5, + H2C_CUSTOMER_STR_W1 = 0xC6, + H2C_CUSTOMER_STR_W2 = 0xC7, + H2C_CUSTOMER_STR_W3 = 0xC8, + H2C_MAXID, +}; + +#define H2C_INACTIVE_PS_LEN 3 +#define H2C_RSVDPAGE_LOC_LEN 5 +#define H2C_MEDIA_STATUS_RPT_LEN 3 +#define H2C_KEEP_ALIVE_CTRL_LEN 2 +#define H2C_DISCON_DECISION_LEN 3 +#define H2C_AP_OFFLOAD_LEN 3 +#define H2C_AP_WOW_GPIO_CTRL_LEN 4 +#define H2C_AP_PS_LEN 2 +#define H2C_PWRMODE_LEN 7 +#define H2C_PSTUNEPARAM_LEN 4 +#define H2C_MACID_CFG_LEN 7 +#define H2C_BTMP_OPER_LEN 5 +#define H2C_WOWLAN_LEN 5 +#define H2C_REMOTE_WAKE_CTRL_LEN 3 +#define H2C_AOAC_GLOBAL_INFO_LEN 2 +#define H2C_AOAC_RSVDPAGE_LOC_LEN 7 +#define H2C_SCAN_OFFLOAD_CTRL_LEN 4 +#define H2C_BT_FW_PATCH_LEN 6 +#define H2C_RSSI_SETTING_LEN 4 +#define H2C_AP_REQ_TXRPT_LEN 3 +#define H2C_FORCE_BT_TXPWR_LEN 3 +#define H2C_BCN_RSVDPAGE_LEN 5 +#define H2C_PROBERSP_RSVDPAGE_LEN 5 +#define H2C_P2PRSVDPAGE_LOC_LEN 5 +#define H2C_P2P_OFFLOAD_LEN 3 + +#define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0) +#define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5]) +#define cpIpAddr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3]) + + +/* _RSVDPAGE_LOC_CMD_0x00 */ +#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +/* _MEDIA_STATUS_RPT_PARM_CMD_0x01 */ +#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 3, 0, 3, (__Value)) + +#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1) +#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1) +#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1) +#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4) + +#define H2C_MSR_ROLE_RSVD 0 +#define H2C_MSR_ROLE_STA 1 +#define H2C_MSR_ROLE_AP 2 +#define H2C_MSR_ROLE_GC 3 +#define H2C_MSR_ROLE_GO 4 +#define H2C_MSR_ROLE_TDLS 5 +#define H2C_MSR_ROLE_ADHOC 6 +#define H2C_MSR_ROLE_MAX 7 + +extern const char *const _h2c_msr_role_str[]; +#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)]) + +#define H2C_MSR_FMT "%s %s%s" +#define H2C_MSR_ARG(h2c_msr) \ + GET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? " C" : "", \ + h2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \ + GET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? " MSINK" : " MSRC") : "" + +s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end); +s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid); +s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end); + +/* _KEEP_ALIVE_CMD_0x03 */ +#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 3, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +/* _DISCONNECT_DECISION_CMD_0x04 */ +#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_DISCONDECISION_PORT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 3, __Value) +#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) + + +/* _AP_Offload 0x08 */ +#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +/* _BCN_RsvdPage 0x09 */ +#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +/* _Probersp_RsvdPage 0x0a */ +#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +/* _Probersp_RsvdPage 0x13 */ +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +/* _AP_PS 0x26 */ +#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + + + +/* CHNL SWITCH OPER OFFLOAD 0x1C */ +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 2, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 2, 3, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value) + + +/* _WoWLAN PARAM_CMD_0x80 */ +#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) +#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) +#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value) +#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value) +#define SET_H2CCMD_WOWLAN_DISABLE_UPHY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_HST2DEV_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 1, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_DURATION_MS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value) +#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value) +#define SET_H2CCMD_WOWLAN_UNIT_FOR_UPHY_DISABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 3, 1, __Value) +#define SET_H2CCMD_WOWLAN_TAKE_PDN_UPHY_DIS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 4, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_INPUT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 5, 1, __Value) + +/* _REMOTE_WAKEUP_CMD_0x81 */ +#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_TKIP_OFFLOAD_EN(__pH2CCmd, __Value) \ + SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 3, 1, __Value) + +#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value) + +/* AOAC_GLOBAL_INFO_0x82 */ +#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +/* AOAC_RSVDPAGE_LOC_0x83 */ +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +/* AOAC_RSVDPAGE_2_0x84 */ + +/* AOAC_RSVDPAGE_3_0x88 */ +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_AOAC_REPORT(__pH2CCmd, __Value) \ + SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 8, __Value) + + + + +/* --------------------------------------------------------------------------------------------------------- + * ------------------------------------------- Structure -------------------------------------------------- + * --------------------------------------------------------------------------------------------------------- */ +typedef struct _RSVDPAGE_LOC { + u8 LocProbeRsp; + u8 LocPsPoll; + u8 LocNullData; + u8 LocQosNull; + u8 LocBTQosNull; + u8 LocApOffloadBCN; +} RSVDPAGE_LOC, *PRSVDPAGE_LOC; + +#endif +void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size); +u8 rtw_hal_set_fw_media_status_cmd(_adapter *adapter, u8 mstatus, u8 macid); diff --git a/drivers/staging/rtl8821ce/include/hal_com_led.h b/drivers/staging/rtl8821ce/include/hal_com_led.h new file mode 100644 index 000000000000..ba635700f61e --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_com_led.h @@ -0,0 +1,258 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COMMON_LED_H_ +#define __HAL_COMMON_LED_H_ + +#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) + +/* ******************************************************************************** + * LED Behavior Constant. + * ******************************************************************************** + * Default LED behavior. + * */ +#define LED_BLINK_NORMAL_INTERVAL 100 +#define LED_BLINK_SLOWLY_INTERVAL 200 +#define LED_BLINK_LONG_INTERVAL 400 +#define LED_INITIAL_INTERVAL 1800 + +/* LED Customerization */ + +/* NETTRONIX */ +#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100 +#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000 + +/* PORNET */ +#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000 +#define LED_BLINK_NORMAL_INTERVAL_PORNET 100 +#define LED_BLINK_FAST_INTERVAL_BITLAND 30 + +/* AzWave. */ +#define LED_CM2_BLINK_ON_INTERVAL 250 +#define LED_CM2_BLINK_OFF_INTERVAL 4750 +#define LED_CM8_BLINK_OFF_INTERVAL 3750 /* for QMI */ + +/* RunTop */ +#define LED_RunTop_BLINK_INTERVAL 300 + +/* ALPHA */ +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 /* add by ylb 20121012 for customer led for alpha */ +#define LED_BLINK_LINK_INTERVAL_ALPHA 500 /* 500 */ +#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 /* 150 */ +#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 +#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 + +/* 111122 by hpfan: Customized for Xavi */ +#define LED_CM11_BLINK_INTERVAL 300 +#define LED_CM11_LINK_ON_INTERVEL 3000 + +/* Netgear */ +#define LED_BLINK_LINK_INTERVAL_NETGEAR 500 +#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR 1000 + +#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR 100 +#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR 500 + +/* Belkin AC950 */ +#define LED_BLINK_LINK_INTERVAL_ON_BELKIN 200 +#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN 100 +#define LED_BLINK_ERROR_INTERVAL_BELKIN 100 + +/* by chiyokolin for Azurewave */ +#define LED_CM12_BLINK_INTERVAL_5Mbps 160 +#define LED_CM12_BLINK_INTERVAL_10Mbps 80 +#define LED_CM12_BLINK_INTERVAL_20Mbps 50 +#define LED_CM12_BLINK_INTERVAL_40Mbps 40 +#define LED_CM12_BLINK_INTERVAL_80Mbps 30 +#define LED_CM12_BLINK_INTERVAL_MAXMbps 25 + +/* Dlink */ +#define LED_BLINK_NO_LINK_INTERVAL 1000 +#define LED_BLINK_LINK_IDEL_INTERVAL 100 + +#define LED_BLINK_SCAN_ON_INTERVAL 30 +#define LED_BLINK_SCAN_OFF_INTERVAL 300 + +#define LED_WPS_BLINK_ON_INTERVAL_DLINK 30 +#define LED_WPS_BLINK_OFF_INTERVAL_DLINK 300 +#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK 5000 + +/* ******************************************************************************** + * LED object. + * ******************************************************************************** */ + +typedef enum _LED_CTL_MODE { + LED_CTL_POWER_ON = 1, + LED_CTL_LINK = 2, + LED_CTL_NO_LINK = 3, + LED_CTL_TX = 4, + LED_CTL_RX = 5, + LED_CTL_SITE_SURVEY = 6, + LED_CTL_POWER_OFF = 7, + LED_CTL_START_TO_LINK = 8, + LED_CTL_START_WPS = 9, + LED_CTL_STOP_WPS = 10, + LED_CTL_START_WPS_BOTTON = 11, /* added for runtop */ + LED_CTL_STOP_WPS_FAIL = 12, /* added for ALPHA */ + LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, /* added for BELKIN */ + LED_CTL_CONNECTION_NO_TRANSFER = 14, +} LED_CTL_MODE; + +typedef enum _LED_STATE { + LED_UNKNOWN = 0, + RTW_LED_ON = 1, + RTW_LED_OFF = 2, + LED_BLINK_NORMAL = 3, + LED_BLINK_SLOWLY = 4, + LED_BLINK_POWER_ON = 5, + LED_BLINK_SCAN = 6, /* LED is blinking during scanning period, the # of times to blink is depend on time for scanning. */ + LED_BLINK_NO_LINK = 7, /* LED is blinking during no link state. */ + LED_BLINK_StartToBlink = 8, /* Customzied for Sercomm Printer Server case */ + LED_BLINK_TXRX = 9, + LED_BLINK_WPS = 10, /* LED is blinkg during WPS communication */ + LED_BLINK_WPS_STOP = 11, /* for ALPHA */ + LED_BLINK_WPS_STOP_OVERLAP = 12, /* for BELKIN */ + LED_BLINK_RUNTOP = 13, /* Customized for RunTop */ + LED_BLINK_CAMEO = 14, + LED_BLINK_XAVI = 15, + LED_BLINK_ALWAYS_ON = 16, + LED_BLINK_LINK_IN_PROCESS = 17, /* Customized for Belkin AC950 */ + LED_BLINK_AUTH_ERROR = 18, /* Customized for Belkin AC950 */ + LED_BLINK_Azurewave_5Mbps = 19, + LED_BLINK_Azurewave_10Mbps = 20, + LED_BLINK_Azurewave_20Mbps = 21, + LED_BLINK_Azurewave_40Mbps = 22, + LED_BLINK_Azurewave_80Mbps = 23, + LED_BLINK_Azurewave_MAXMbps = 24, + LED_BLINK_LINK_IDEL = 25, + LED_BLINK_WPS_LINKED = 26, +} LED_STATE; + +typedef enum _LED_PIN { + LED_PIN_GPIO0, + LED_PIN_LED0, + LED_PIN_LED1, + LED_PIN_LED2 +} LED_PIN; + +/* ******************************************************************************** + * PCIE LED Definition. + * ******************************************************************************** */ +typedef enum _LED_STRATEGY_PCIE { + SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ + SW_LED_MODE1, /* SW control for PCI Express */ + SW_LED_MODE2, /* SW control for Cameo. */ + SW_LED_MODE3, /* SW contorl for RunTop. */ + SW_LED_MODE4, /* SW control for Netcore */ + SW_LED_MODE5, /* added by vivi, for led new mode, DLINK */ + SW_LED_MODE6, /* added by vivi, for led new mode, PRONET */ + SW_LED_MODE7, /* added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec */ + SW_LED_MODE8, /* added by chiyokolin, for QMI */ + SW_LED_MODE9, /* added by chiyokolin, for BITLAND-LENOVO, PCI Express Minicard Spec Rev.1.1 */ + SW_LED_MODE10, /* added by chiyokolin, for Edimax-ASUS */ + SW_LED_MODE11, /* added by hpfan, for Xavi */ + SW_LED_MODE12, /* added by chiyokolin, for Azurewave */ + HW_LED, /* HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) */ +} LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE; + +typedef struct _LED_PCIE { + PADAPTER padapter; + + LED_PIN LedPin; /* Identify how to implement this SW led. */ + + LED_STATE CurrLedState; /* Current LED state. */ + BOOLEAN bLedOn; /* TRUE if LED is ON, FALSE if LED is OFF. */ + + BOOLEAN bLedBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */ + BOOLEAN bLedWPSBlinkInProgress; /* TRUE if it is blinking, FALSE o.w.. */ + + BOOLEAN bLedSlowBlinkInProgress;/* added by vivi, for led new mode */ + u32 BlinkTimes; /* Number of times to toggle led state for blinking. */ + LED_STATE BlinkingLedState; /* Next state for blinking, either LED_ON or LED_OFF are. */ + + _timer BlinkTimer; /* Timer object for led blinking. */ +} LED_PCIE, *PLED_PCIE; + +typedef struct _LED_PCIE LED_DATA, *PLED_DATA; +typedef enum _LED_STRATEGY_PCIE LED_STRATEGY, *PLED_STRATEGY; + +VOID +LedControlPCIE( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +); + +VOID +gen_RefreshLedState( + IN PADAPTER Adapter); + +/* ******************************************************************************** + * USB LED Definition. + * ******************************************************************************** */ + +struct led_priv { + /* add for led controll */ + LED_DATA SwLed0; + LED_DATA SwLed1; + LED_DATA SwLed2; + LED_STRATEGY LedStrategy; + u8 bRegUseLed; + void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction); + void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed); + void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed); + /* add for led controll */ +}; + +#define rtw_led_control(adapter, LedAction) + +#define SwLedOn(adapter, pLed) \ + do { \ + if ((adapter)->ledpriv.SwLedOn) \ + (adapter)->ledpriv.SwLedOn((adapter), (pLed)); \ + } while (0) + +#define SwLedOff(adapter, pLed) \ + do { \ + if ((adapter)->ledpriv.SwLedOff) \ + (adapter)->ledpriv.SwLedOff((adapter), (pLed)); \ + } while (0) + +void BlinkTimerCallback(void *data); +void BlinkWorkItemCallback(_workitem *work); + +void ResetLedStatus(PLED_DATA pLed); + +void +InitLed( + _adapter *padapter, + PLED_DATA pLed, + LED_PIN LedPin +); + +void +DeInitLed( + PLED_DATA pLed +); + +/* hal... */ +extern void BlinkHandler(PLED_DATA pLed); + +#endif /* __RTW_LED_H_ */ diff --git a/drivers/staging/rtl8821ce/include/hal_com_phycfg.h b/drivers/staging/rtl8821ce/include/hal_com_phycfg.h new file mode 100644 index 000000000000..40a9bc36eb3b --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_com_phycfg.h @@ -0,0 +1,324 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COM_PHYCFG_H__ +#define __HAL_COM_PHYCFG_H__ + +#define PathA 0x0 /* Useless */ +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +typedef enum _RF_TX_NUM { + RF_1TX = 0, + RF_2TX, + RF_3TX, + RF_4TX, + RF_MAX_TX_NUM, + RF_TX_NUM_NONIMPLEMENT, +} RF_TX_NUM; + +#define MAX_POWER_INDEX 0x3F + +typedef enum _REGULATION_TXPWR_LMT { + TXPWR_LMT_FCC = 0, + TXPWR_LMT_MKK = 1, + TXPWR_LMT_ETSI = 2, + TXPWR_LMT_WW = 3, + + TXPWR_LMT_MAX_REGULATION_NUM = 4 +} REGULATION_TXPWR_LMT; + +#define TX_PWR_LMT_REF_VHT_FROM_HT BIT0 +#define TX_PWR_LMT_REF_HT_FROM_VHT BIT1 + +/*------------------------------Define structure----------------------------*/ +typedef struct _BB_REGISTER_DEFINITION { + u32 rfintfs; /* set software control: */ + /* 0x870~0x877[8 bytes] */ + + u32 rfintfo; /* output data: */ + /* 0x860~0x86f [16 bytes] */ + + u32 rfintfe; /* output enable: */ + /* 0x860~0x86f [16 bytes] */ + + u32 rf3wireOffset; /* LSSI data: */ + /* 0x840~0x84f [16 bytes] */ + + u32 rfHSSIPara2; /* wire parameter control2 : */ + /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] */ + + u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ + /* 0x8a0~0x8af [16 bytes] */ + + u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for Path A and B */ + +} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; + +/* ---------------------------------------------------------------------- */ +u8 +PHY_GetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN u8 TxNum, + IN RATE_SECTION RateSection +); + +VOID +PHY_GetRateValuesOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Value, + OUT u8 *Rate, + OUT s8 *PwrByRateVal, + OUT u8 *RateNum +); + +u8 +PHY_GetRateIndexOfTxPowerByRate( + IN u8 Rate +); + +VOID +phy_set_tx_power_index_by_rate_section( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Channel, + IN u8 RateSection +); + +s8 +_PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 RateIndex +); + +s8 +PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 RateIndex +); + + +VOID +PHY_SetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate, + IN s8 Value +); + +VOID +phy_set_tx_power_level_by_path( + IN PADAPTER Adapter, + IN u8 channel, + IN u8 path +); + +VOID +PHY_SetTxPowerIndexByRateArray( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + IN u8 *Rates, + IN u8 RateArraySize +); + +VOID +PHY_InitTxPowerByRate( + IN PADAPTER pAdapter +); + +VOID +phy_store_tx_power_by_rate( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +); + +VOID +PHY_TxPowerByRateConfiguration( + IN PADAPTER pAdapter +); + +u8 +PHY_GetTxPowerIndexBase( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + OUT PBOOLEAN bIn24G +); + +s8 +PHY_GetTxPowerLimit( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel +); + +s8 +PHY_GetTxPowerLimit_no_sc( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel +); + + +VOID +PHY_ConvertTxPowerLimitToPowerIndex( + IN PADAPTER Adapter +); + +VOID +PHY_InitTxPowerLimit( + IN PADAPTER Adapter +); + +s8 +PHY_GetTxPowerTrackingOffset( + PADAPTER pAdapter, + u8 Rate, + u8 RFPath +); + +struct txpwr_idx_comp { + u8 base; + s8 by_rate; + s8 limit; + s8 tpt; + s8 ebias; +}; + +u8 +phy_get_tx_power_index( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel +); + +VOID +PHY_SetTxPowerIndex( + IN PADAPTER pAdapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate +); + +void dump_tx_power_idx_title(void *sel, _adapter *adapter); +void dump_tx_power_idx_by_path_rs(void *sel, _adapter *adapter, u8 rfpath, u8 rs); +void dump_tx_power_idx(void *sel, _adapter *adapter); + +bool phy_is_tx_power_limit_needed(_adapter *adapter); +bool phy_is_tx_power_by_rate_needed(_adapter *adapter); +int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file); +int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file); +void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file); +void phy_reload_tx_power_ext_info(_adapter *adapter); +void phy_reload_default_tx_power_ext_info(_adapter *adapter); + +const struct map_t *hal_pg_txpwr_def_info(_adapter *adapter); + +void dump_pg_txpwr_info_2g(void *sel, TxPowerInfo24G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt); +void dump_pg_txpwr_info_5g(void *sel, TxPowerInfo5G *txpwr_info, u8 rfpath_num, u8 max_tx_cnt); + +void dump_hal_txpwr_info_2g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); +void dump_hal_txpwr_info_5g(void *sel, _adapter *adapter, u8 rfpath_num, u8 max_tx_cnt); + +void hal_load_txpwr_info( + _adapter *adapter, + TxPowerInfo24G *pwr_info_2g, + TxPowerInfo5G *pwr_info_5g, + u8 *pg_data +); + +void dump_tx_power_ext_info(void *sel, _adapter *adapter); +void dump_target_tx_power(void *sel, _adapter *adapter); +void dump_tx_power_by_rate(void *sel, _adapter *adapter); +void dump_tx_power_limit(void *sel, _adapter *adapter); + +int rtw_get_phy_file_path(_adapter *adapter, const char *file_name); + +#define MAC_FILE_FW_NIC "FW_NIC.bin" +#define MAC_FILE_FW_WW_IMG "FW_WoWLAN.bin" +#define PHY_FILE_MAC_REG "MAC_REG.txt" + +#define PHY_FILE_AGC_TAB "AGC_TAB.txt" +#define PHY_FILE_PHY_REG "PHY_REG.txt" +#define PHY_FILE_PHY_REG_MP "PHY_REG_MP.txt" +#define PHY_FILE_PHY_REG_PG "PHY_REG_PG.txt" + +#define PHY_FILE_RADIO_A "RadioA.txt" +#define PHY_FILE_RADIO_B "RadioB.txt" +#define PHY_FILE_RADIO_C "RadioC.txt" +#define PHY_FILE_RADIO_D "RadioD.txt" +#define PHY_FILE_TXPWR_TRACK "TxPowerTrack.txt" +#define PHY_FILE_TXPWR_LMT "TXPWR_LMT.txt" + +#define PHY_FILE_WIFI_ANT_ISOLATION "wifi_ant_isolation.txt" + +#define MAX_PARA_FILE_BUF_LEN 25600 + +#define LOAD_MAC_PARA_FILE BIT0 +#define LOAD_BB_PARA_FILE BIT1 +#define LOAD_BB_PG_PARA_FILE BIT2 +#define LOAD_BB_MP_PARA_FILE BIT3 +#define LOAD_RF_PARA_FILE BIT4 +#define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5 +#define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6 + +int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char *pFileName); +int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u32 ConfigType); +int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName); +int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char *pFileName); +int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char *pFileName, IN u8 eRFPath); +int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char *pFileName); +int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName); +void phy_free_filebuf_mask(_adapter *padapter, u8 mask); +void phy_free_filebuf(_adapter *padapter); + +#endif /* __HAL_COMMON_H__ */ diff --git a/drivers/staging/rtl8821ce/include/hal_com_reg.h b/drivers/staging/rtl8821ce/include/hal_com_reg.h new file mode 100644 index 000000000000..10449b455853 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_com_reg.h @@ -0,0 +1,1110 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COMMON_REG_H__ +#define __HAL_COMMON_REG_H__ + +#define MAC_ADDR_LEN 6 + +#define HAL_NAV_UPPER_UNIT 128 /* micro-second */ + +/* 8188E PKT_BUFF_ACCESS_CTRL value */ +#define TXPKT_BUF_SELECT 0x69 +#define RXPKT_BUF_SELECT 0xA5 +#define DISABLE_TRXPKT_BUF_ACCESS 0x0 + + +/* ---------------------------------------------------------------------------- + * Rate Definition + * ---------------------------------------------------------------------------- */ +/* CCK */ +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +/* OFDM */ +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +/* MCS 1 Spatial Stream */ +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +/* MCS 2 Spatial Stream */ +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 + +/* CCK */ +#define RATE_1M BIT(0) +#define RATE_2M BIT(1) +#define RATE_5_5M BIT(2) +#define RATE_11M BIT(3) +/* OFDM */ +#define RATE_6M BIT(4) +#define RATE_9M BIT(5) +#define RATE_12M BIT(6) +#define RATE_18M BIT(7) +#define RATE_24M BIT(8) +#define RATE_36M BIT(9) +#define RATE_48M BIT(10) +#define RATE_54M BIT(11) +/* MCS 1 Spatial Stream */ +#define RATE_MCS0 BIT(12) +#define RATE_MCS1 BIT(13) +#define RATE_MCS2 BIT(14) +#define RATE_MCS3 BIT(15) +#define RATE_MCS4 BIT(16) +#define RATE_MCS5 BIT(17) +#define RATE_MCS6 BIT(18) +#define RATE_MCS7 BIT(19) +/* MCS 2 Spatial Stream */ +#define RATE_MCS8 BIT(20) +#define RATE_MCS9 BIT(21) +#define RATE_MCS10 BIT(22) +#define RATE_MCS11 BIT(23) +#define RATE_MCS12 BIT(24) +#define RATE_MCS13 BIT(25) +#define RATE_MCS14 BIT(26) +#define RATE_MCS15 BIT(27) + +/* ALL CCK Rate */ +#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) +#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M | RATR_24M|\ + RATR_36M | RATR_48M | RATR_54M) +#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | RATR_MCS3 |\ + RATR_MCS4 | RATR_MCS5 | RATR_MCS6 | RATR_MCS7) +#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | RATR_MCS11|\ + RATR_MCS12 | RATR_MCS13 | RATR_MCS14 | RATR_MCS15) + +#define RATE_BITMAP_ALL 0xFFFFF + +/* Only use CCK 1M rate for ACK */ +#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 +#define RATE_RRSR_WITHOUT_CCK 0xFFFF0 + +/* ---------------------------------------------------------------------------- + * BW_OPMODE bits (Offset 0x603, 8bit) + * ---------------------------------------------------------------------------- */ +#define BW_OPMODE_20MHZ BIT(2) +#define BW_OPMODE_5G BIT(1) + +/* ---------------------------------------------------------------------------- + * CAM Config Setting (offset 0x680, 1 byte) + * ---------------------------------------------------------------------------- */ +#define CAM_VALID BIT(15) +#define CAM_NOTVALID 0x0000 +#define CAM_USEDK BIT(5) + +#define CAM_CONTENT_COUNT 8 + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 + +#define TOTAL_CAM_ENTRY 32 +#define HALF_CAM_ENTRY 16 + +#define CAM_CONFIG_USEDK _TRUE +#define CAM_CONFIG_NO_USEDK _FALSE + +#define CAM_WRITE BIT(16) +#define CAM_READ 0x00000000 +#define CAM_POLLINIG BIT(31) + +/* + * 10. Power Save Control Registers + * */ +#define WOW_PMEN BIT(0) /* Power management Enable. */ +#define WOW_WOMEN BIT(1) /* WoW function on or off. */ +#define WOW_MAGIC BIT(2) /* Magic packet */ +#define WOW_UWF BIT(3) /* Unicast Wakeup frame. */ + +/* + * 12. Host Interrupt Status Registers + * + * ---------------------------------------------------------------------------- + * 8190 IMR/ISR bits + * ---------------------------------------------------------------------------- */ +#define IMR8190_DISABLED 0x0 +#define IMR_DISABLED 0x0 +/* IMR DW0 Bit 0-31 */ +#define IMR_BCNDMAINT6 BIT(31) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5 BIT(30) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4 BIT(29) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3 BIT(28) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2 BIT(27) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1 BIT(26) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK8 BIT(25) /* Beacon Queue DMA OK Interrupt 8 */ +#define IMR_BCNDOK7 BIT(24) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6 BIT(23) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5 BIT(22) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4 BIT(21) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3 BIT(20) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2 BIT(19) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1 BIT(18) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_TIMEOUT2 BIT(17) /* Timeout interrupt 2 */ +#define IMR_TIMEOUT1 BIT(16) /* Timeout interrupt 1 */ +#define IMR_TXFOVW BIT(15) /* Transmit FIFO Overflow */ +#define IMR_PSTIMEOUT BIT(14) /* Power save time out interrupt */ +#define IMR_BcnInt BIT(13) /* Beacon DMA Interrupt 0 */ +#define IMR_RXFOVW BIT(12) /* Receive FIFO Overflow */ +#define IMR_RDU BIT(11) /* Receive Descriptor Unavailable */ +#define IMR_ATIMEND BIT(10) /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */ +#define IMR_BDOK BIT(9) /* Beacon Queue DMA OK Interrupt */ +#define IMR_HIGHDOK BIT(8) /* High Queue DMA OK Interrupt */ +#define IMR_TBDOK BIT(7) /* Transmit Beacon OK interrupt */ +#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK Interrupt */ +#define IMR_TBDER BIT(5) /* For 92C, Transmit Beacon Error Interrupt */ +#define IMR_BKDOK BIT(4) /* AC_BK DMA OK Interrupt */ +#define IMR_BEDOK BIT(3) /* AC_BE DMA OK Interrupt */ +#define IMR_VIDOK BIT(2) /* AC_VI DMA OK Interrupt */ +#define IMR_VODOK BIT(1) /* AC_VO DMA Interrupt */ +#define IMR_ROK BIT(0) /* Receive DMA OK Interrupt */ + +/* 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) */ +#define IMR_TSF_BIT32_TOGGLE BIT(15) +#define IMR_BcnInt_E BIT(12) +#define IMR_TXERR BIT(11) +#define IMR_RXERR BIT(10) +#define IMR_C2HCMD BIT(9) +#define IMR_CPWM BIT(8) +/* RSVD [2-7] */ +#define IMR_OCPINT BIT(1) +#define IMR_WLANOFF BIT(0) + +/* ---------------------------------------------------------------------------- + * 8723E series PCIE Host IMR/ISR bit + * ---------------------------------------------------------------------------- */ +/* IMR DW0 Bit 0-31 */ +#define PHIMR_TIMEOUT2 BIT(31) +#define PHIMR_TIMEOUT1 BIT(30) +#define PHIMR_PSTIMEOUT BIT(29) +#define PHIMR_GTINT4 BIT(28) +#define PHIMR_GTINT3 BIT(27) +#define PHIMR_TXBCNERR BIT(26) +#define PHIMR_TXBCNOK BIT(25) +#define PHIMR_TSF_BIT32_TOGGLE BIT(24) +#define PHIMR_BCNDMAINT3 BIT(23) +#define PHIMR_BCNDMAINT2 BIT(22) +#define PHIMR_BCNDMAINT1 BIT(21) +#define PHIMR_BCNDMAINT0 BIT(20) +#define PHIMR_BCNDOK3 BIT(19) +#define PHIMR_BCNDOK2 BIT(18) +#define PHIMR_BCNDOK1 BIT(17) +#define PHIMR_BCNDOK0 BIT(16) +#define PHIMR_HSISR_IND_ON BIT(15) +#define PHIMR_BCNDMAINT_E BIT(14) +#define PHIMR_ATIMEND_E BIT(13) +#define PHIMR_ATIM_CTW_END BIT(12) +#define PHIMR_HISRE_IND BIT(11) /* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */ +#define PHIMR_C2HCMD BIT(10) +#define PHIMR_CPWM2 BIT(9) +#define PHIMR_CPWM BIT(8) +#define PHIMR_HIGHDOK BIT(7) /* High Queue DMA OK Interrupt */ +#define PHIMR_MGNTDOK BIT(6) /* Management Queue DMA OK Interrupt */ +#define PHIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ +#define PHIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ +#define PHIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ +#define PHIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ +#define PHIMR_RDU BIT(1) /* Receive Descriptor Unavailable */ +#define PHIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ + +/* PCIE Host Interrupt Status Extension bit */ +#define PHIMR_BCNDMAINT7 BIT(23) +#define PHIMR_BCNDMAINT6 BIT(22) +#define PHIMR_BCNDMAINT5 BIT(21) +#define PHIMR_BCNDMAINT4 BIT(20) +#define PHIMR_BCNDOK7 BIT(19) +#define PHIMR_BCNDOK6 BIT(18) +#define PHIMR_BCNDOK5 BIT(17) +#define PHIMR_BCNDOK4 BIT(16) +/* bit12 15: RSVD */ +#define PHIMR_TXERR BIT(11) +#define PHIMR_RXERR BIT(10) +#define PHIMR_TXFOVW BIT(9) +#define PHIMR_RXFOVW BIT(8) +/* bit2-7: RSVD */ +#define PHIMR_OCPINT BIT(1) +/* bit0: RSVD */ + +#define UHIMR_TIMEOUT2 BIT(31) +#define UHIMR_TIMEOUT1 BIT(30) +#define UHIMR_PSTIMEOUT BIT(29) +#define UHIMR_GTINT4 BIT(28) +#define UHIMR_GTINT3 BIT(27) +#define UHIMR_TXBCNERR BIT(26) +#define UHIMR_TXBCNOK BIT(25) +#define UHIMR_TSF_BIT32_TOGGLE BIT(24) +#define UHIMR_BCNDMAINT3 BIT(23) +#define UHIMR_BCNDMAINT2 BIT(22) +#define UHIMR_BCNDMAINT1 BIT(21) +#define UHIMR_BCNDMAINT0 BIT(20) +#define UHIMR_BCNDOK3 BIT(19) +#define UHIMR_BCNDOK2 BIT(18) +#define UHIMR_BCNDOK1 BIT(17) +#define UHIMR_BCNDOK0 BIT(16) +#define UHIMR_HSISR_IND BIT(15) +#define UHIMR_BCNDMAINT_E BIT(14) +/* RSVD BIT(13) */ +#define UHIMR_CTW_END BIT(12) +/* RSVD BIT(11) */ +#define UHIMR_C2HCMD BIT(10) +#define UHIMR_CPWM2 BIT(9) +#define UHIMR_CPWM BIT(8) +#define UHIMR_HIGHDOK BIT(7) /* High Queue DMA OK Interrupt */ +#define UHIMR_MGNTDOK BIT(6) /* Management Queue DMA OK Interrupt */ +#define UHIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */ +#define UHIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */ +#define UHIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */ +#define UHIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */ +#define UHIMR_RDU BIT(1) /* Receive Descriptor Unavailable */ +#define UHIMR_ROK BIT(0) /* Receive DMA OK Interrupt */ + +/* USB Host Interrupt Status Extension bit */ +#define UHIMR_BCNDMAINT7 BIT(23) +#define UHIMR_BCNDMAINT6 BIT(22) +#define UHIMR_BCNDMAINT5 BIT(21) +#define UHIMR_BCNDMAINT4 BIT(20) +#define UHIMR_BCNDOK7 BIT(19) +#define UHIMR_BCNDOK6 BIT(18) +#define UHIMR_BCNDOK5 BIT(17) +#define UHIMR_BCNDOK4 BIT(16) +/* bit14-15: RSVD */ +#define UHIMR_ATIMEND_E BIT(13) +#define UHIMR_ATIMEND BIT(12) +#define UHIMR_TXERR BIT(11) +#define UHIMR_RXERR BIT(10) +#define UHIMR_TXFOVW BIT(9) +#define UHIMR_RXFOVW BIT(8) +/* bit2-7: RSVD */ +#define UHIMR_OCPINT BIT(1) +/* bit0: RSVD */ + +#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ +#define HAL_NIC_UNPLUG_PCI_ISR 0xEAEAEAEA /* The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */ + +/* ---------------------------------------------------------------------------- + * 8188 IMR/ISR bits + * ---------------------------------------------------------------------------- */ +#define IMR_DISABLED_88E 0x0 +/* IMR DW0(0x0060-0063) Bit 0-31 */ +#define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */ +#define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */ +#define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ +#define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ +#define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */ +#define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */ +#define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */ +#define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */ +#define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */ +#define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ +#define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ +#define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */ +#define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ +#define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ +#define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ +#define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */ +#define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */ +#define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */ +#define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */ +#define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */ +#define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */ +#define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */ +#define IMR_ROK_88E BIT(0) /* Receive DMA OK */ + +/* IMR DW1(0x00B4-00B7) Bit 0-31 */ +#define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */ +#define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */ +#define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */ +#define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */ +#define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */ +#define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */ +#define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */ +#define IMR_BCNDOK7_88E BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_88E BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_88E BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_88E BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_88E BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_88E BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_88E BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ +#define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Extension for Win7 */ +#define IMR_TXERR_88E BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ +#define IMR_RXERR_88E BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ +#define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */ +#define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */ + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +/* ---------------------------------------------------------------------------- */ +/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ +/* ---------------------------------------------------------------------------- */ +/* Note: +* The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, +* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. +* 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. +* By Bruce, 2011-09-22. */ +#define StopBecon BIT(6) +#define StopHigh BIT(5) +#define StopMgt BIT(4) +#define StopBK BIT(3) +#define StopBE BIT(2) +#define StopVI BIT(1) +#define StopVO BIT(0) + +/* ---------------------------------------------------------------------------- + * 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) + * ---------------------------------------------------------------------------- */ +#define RCR_APPFCS BIT(31) /* WMAC append FCS after pauload */ +#define RCR_APP_MIC BIT(30) /* MACRX will retain the MIC at the bottom of the packet. */ +#define RCR_APP_ICV BIT(29) /* MACRX will retain the ICV at the bottom of the packet. */ +#define RCR_APP_PHYST_RXFF BIT(28) /* PHY Status is appended before RX packet in RXFF */ +#define RCR_APP_BA_SSN BIT(27) /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ +#define RCR_VHT_DACK BIT(26) /* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */ +#define RCR_TCPOFLD_EN BIT(25) /* Enable TCP checksum offload */ +#define RCR_ENMBID BIT(24) /* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */ +#define RCR_LSIGEN BIT(23) /* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */ +#define RCR_MFBEN BIT(22) /* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */ +#define RCR_DISCHKPPDLLEN BIT(21) /* Do not check PPDU while the PPDU length is smaller than 14 byte. */ +#define RCR_PKTCTL_DLEN BIT(20) /* While rx path dead lock occurs, reset rx path */ +#define RCR_DISGCLK BIT(19) /* Disable macrx clock gating control (no used) */ +#define RCR_TIM_PARSER_EN BIT(18) /* RX Beacon TIM Parser. */ +#define RCR_BC_MD_EN BIT(17) /* Broadcast data packet more data bit check interrupt enable.*/ +#define RCR_UC_MD_EN BIT(16) /* Unicast data packet more data bit check interrupt enable. */ +#define RCR_RXSK_PERPKT BIT(15) /* Executing key search per MPDU */ +#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC = 1 MFC-->HTC = 0 */ +#define RCR_AMF BIT(13) /* Accept management type frame */ +#define RCR_ACF BIT(12) /* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */ +#define RCR_ADF BIT(11) /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */ +#define RCR_DISDECMYPKT BIT(10) /* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */ +#define RCR_AICV BIT(9) /* Accept ICV error packet */ +#define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */ +#define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet (Rx beacon, probe rsp) */ +#define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match packet (Data) */ +#define RCR_APWRMGT BIT(5) /* Accept power management packet */ +#define RCR_ADD3 BIT(4) /* Accept address 3 match packet */ +#define RCR_AB BIT(3) /* Accept broadcast packet */ +#define RCR_AM BIT(2) /* Accept multicast packet */ +#define RCR_APM BIT(1) /* Accept physical match packet */ +#define RCR_AAP BIT(0) /* Accept all unicast packet */ + +/* ----------------------------------------------------- + * + * 0x0000h ~ 0x00FFh System Configuration + * + * ----------------------------------------------------- */ + +/* 2 SYS_ISO_CTRL */ +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + +/* 2 SYS_FUNC_EN */ +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_EN_25_1 BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +/* 2 APS_FSMCO */ +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +/* 2 SYS_CLKR */ +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + +/* 2 9346CR /REG_SYS_EEPROM_CTRL */ +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROMSEL BIT(4) +#define EEPROM_EN BIT(5) + +/* 2 RF_CTRL */ +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +/* 2 LDOV12D_CTRL */ +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + +/* 2 EFUSE_TEST (For RTL8723 partially) */ +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8) | BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + +/* 2 8051FWDL + * 2 MCUFWDL */ +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define CPU_DL_READY BIT(15) /* add flag by gw for fw download ready 20130826 */ +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + +/* 2 REG_SYS_CFG */ +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define SW_OFFLOAD_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define EXT_VENDOR_ID (BIT(18) | BIT(19)) /* Currently only for RTL8723B */ +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) /* RTL ID */ +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) +#define RF_TYPE_ID BIT(27) + +#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ +#define SPS_SEL BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */ + +#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ +#define CHIP_VER_RTL_SHIFT 12 +#define EXT_VENDOR_ID_SHIFT 18 + +/* 2 REG_GPIO_OUTSTS (For RTL8723 only) */ +#define EFS_HCI_SEL (BIT(0) | BIT(1)) +#define PAD_HCI_SEL (BIT(2) | BIT(3)) +#define HCI_SEL (BIT(4) | BIT(5)) +#define PKG_SEL_HCI BIT(6) +#define FEN_GPS BIT(7) +#define FEN_BT BIT(8) +#define FEN_WL BIT(9) +#define FEN_PCI BIT(10) +#define FEN_USB BIT(11) +#define BTRF_HWPDN_N BIT(12) +#define WLRF_HWPDN_N BIT(13) +#define PDN_BT_N BIT(14) +#define PDN_GPS_N BIT(15) +#define BT_CTL_HWPDN BIT(16) +#define GPS_CTL_HWPDN BIT(17) +#define PPHY_SUSB BIT(20) +#define UPHY_SUSB BIT(21) +#define PCI_SUSEN BIT(22) +#define USB_SUSEN BIT(23) +#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) + +/* ----------------------------------------------------- + * + * 0x0100h ~ 0x01FFh MACTOP General Configuration + * + * ----------------------------------------------------- */ + +/* 2 Function Enable Registers + * 2 CR */ +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ + +/* Network type */ +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + +/* 2 PBP - Page Size Register */ +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + +/* 2 TX/RXDMA */ +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +/* For normal driver, 0x10C */ +#define _TXDMA_CMQ_MAP(x) (((x) & 0x3) << 16) +#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8) +#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6) +#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4) + +#define QUEUE_EXTRA 0 +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + +/* 2 TRXFF_BNDY */ + +/* 2 LLT_INIT */ +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +/* ----------------------------------------------------- + * + * 0x0200h ~ 0x027Fh TXDMA Configuration + * + * ----------------------------------------------------- */ +/* 2 RQPN */ +#define _HPQ(x) ((x) & 0xFF) +#define _LPQ(x) (((x) & 0xFF) << 8) +#define _PUBQ(x) (((x) & 0xFF) << 16) +#define _NPQ(x) ((x) & 0xFF) /* NOTE: in RQPN_NPQ register */ +#define _EPQ(x) (((x) & 0xFF) << 16) /* NOTE: in RQPN_EPQ register */ + +#define HPQ_PUBLIC_DIS BIT(24) +#define LPQ_PUBLIC_DIS BIT(25) +#define LD_RQPN BIT(31) + +/* 2 TDECTL */ +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + +/* 2 TXDMA_OFFSET_CHK */ +#define DROP_DATA_EN BIT(9) + +/* 2 AUTO_LLT */ +#define BIT_SHIFT_TXPKTNUM 24 +#define BIT_MASK_TXPKTNUM 0xff +#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) + +#define BIT_TDE_DBG_SEL BIT(23) +#define BIT_AUTO_INIT_LLT BIT(16) + +#define BIT_SHIFT_Tx_OQT_free_space 8 +#define BIT_MASK_Tx_OQT_free_space 0xff +#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space) + +/* ----------------------------------------------------- + * + * 0x0120h ~ 0x0123h RX DMA Configuration + * + * ----------------------------------------------------- */ +#define BIT_FS_RXDONE_INT_EN BIT(16) + +/* REG_RXPKT_NUM (Offset 0x0284) */ +#define BIT_RW_RELEASE_EN BIT(18) + +/* ----------------------------------------------------- + * + * 0x0280h ~ 0x028Bh RX DMA Configuration + * + * ----------------------------------------------------- */ + +/* 2 REG_RXDMA_CONTROL, 0x0286h + * Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before + * this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. + * #define RXPKT_RELEASE_POLL BIT(0) + * Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in + * this bit. FW can start releasing packets after RXDMA entering idle mode. + * #define RXDMA_IDLE BIT(1) + * When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host + * completed, and stop DMA packet to host. RXDMA will then report Default: 0; + * #define RW_RELEASE_EN BIT(2) */ + +/* 2 REG_RXPKT_NUM, 0x0284 */ +#define RXPKT_RELEASE_POLL BIT(16) +#define RXDMA_IDLE BIT(17) +#define RW_RELEASE_EN BIT(18) + +/* ----------------------------------------------------- + * + * 0x0400h ~ 0x047Fh Protocol Configuration + * + * ----------------------------------------------------- */ +/* 2 FWHW_TXQ_CTRL */ +#define EN_AMPDU_RTY_NEW BIT(7) + +/* 2 SPEC SIFS */ +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +/* 2 RL */ +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +/* ----------------------------------------------------- + * + * 0x0500h ~ 0x05FFh EDCA Configuration + * + * ----------------------------------------------------- */ + +/* 2 EDCA setting */ +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) + +/* 2 BCN_CTRL */ +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) +#define STOP_BCNQ BIT(6) +#define DIS_RX_BSSID_FIT BIT(6) + +#define DIS_ATIM BIT(0) +#define DIS_BCNQ_SUB BIT(1) +#define DIS_TSF_UDT BIT(4) + +/* The same function but different bit field. */ +#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) +#define DIS_TSF_UDT0_TEST_CHIP BIT(5) + +/* 2 ACMHWCTRL */ +#define AcmHw_HwEn BIT(0) +#define AcmHw_BeqEn BIT(1) +#define AcmHw_ViqEn BIT(2) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) +#define AcmHw_ViqStatus BIT(5) +#define AcmHw_VoqStatus BIT(6) + +/* 2 */ /* REG_DUAL_TSF_RST (0x553) */ +#define DUAL_TSF_RST_P2P BIT(4) + +/* 2 */ /* REG_NOA_DESC_SEL (0x5CF) */ +#define NOA_DESC_SEL_0 0 +#define NOA_DESC_SEL_1 BIT(4) + +/* ----------------------------------------------------- + * + * 0x0600h ~ 0x07FFh WMAC Configuration + * + * ----------------------------------------------------- */ + +/* 2 APSD_CTRL */ +#define APSDOFF BIT(6) + +/* 2 TCR */ +#define TSFRST BIT(0) +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) + +/* 2 RCR */ +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define FORCEACK BIT(26) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +#define APP_FCS BIT(31) + +/* 2 SECCFG */ +#define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ +#define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ +#define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ +#define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ +#define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ +#define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ +#define SCR_TXBCUSEDK BIT(6) /* Force Tx Broadcast packets Use Default Key */ +#define SCR_RXBCUSEDK BIT(7) /* Force Rx Broadcast packets Use Default Key */ +#define SCR_CHK_KEYID BIT(8) +#define SCR_CHK_BMC BIT(9) /* add option to support a2+keyid+bcm */ + +/*REG_MBIDCAMCFG (Offset 0x0628/0x62C)*/ +#define BIT_MBIDCAM_POLL BIT(31) +#define BIT_MBIDCAM_WT_EN BIT(30) + +#define MBIDCAM_ADDR_MASK 0x1F +#define MBIDCAM_ADDR_SHIFT 24 + +#define BIT_MBIDCAM_VALID BIT(23) +#define BIT_LSIC_TXOP_EN BIT(17) +#define BIT_CTS_EN BIT(16) + +/* ----------------------------------------------------- + * + * SDIO Bus Specification + * + * ----------------------------------------------------- */ + +/* I/O bus domain address mapping */ +#define SDIO_LOCAL_BASE 0x10250000 +#define WLAN_IOREG_BASE 0x10260000 +#define FIRMWARE_FIFO_BASE 0x10270000 +#define TX_HIQ_BASE 0x10310000 +#define TX_MIQ_BASE 0x10320000 +#define TX_LOQ_BASE 0x10330000 +#define TX_EPQ_BASE 0x10350000 +#define RX_RX0FF_BASE 0x10340000 + +/* SDIO host local register space mapping. */ +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ +#define WLAN_RX0FF_MSK 0x0003 + +#define SDIO_WITHOUT_REF_DEVICE_ID 0 /* Without reference to the SDIO Device ID */ +#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ +#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ +#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ +#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ +#define WLAN_TX_EXQ_DEVICE_ID 3 /* 0b[16], 011b[15:13] */ +#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ +#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ + +/* SDIO Tx Free Page Index */ +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ +#define SDIO_MAX_RX_QUEUE 1 + +#define SDIO_REG_TX_CTRL 0x0000 /* SDIO Tx Control */ +#define SDIO_REG_HIMR 0x0014 /* SDIO Host Interrupt Mask */ +#define SDIO_REG_HISR 0x0018 /* SDIO Host Interrupt Service Routine */ +#define SDIO_REG_HCPWM 0x0019 /* HCI Current Power Mode */ +#define SDIO_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */ +#define SDIO_REG_OQT_FREE_PG 0x001E /* OQT Free Page */ +#define SDIO_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */ +#define SDIO_REG_HCPWM1 0x0024 /* HCI Current Power Mode 1 */ +#define SDIO_REG_HCPWM2 0x0026 /* HCI Current Power Mode 2 */ +#define SDIO_REG_FREE_TXPG_SEQ 0x0028 /* Free Tx Page Sequence */ +#define SDIO_REG_HTSFR_INFO 0x0030 /* HTSF Informaion */ +#define SDIO_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */ +#define SDIO_REG_HRPWM2 0x0082 /* HCI Request Power Mode 2 */ +#define SDIO_REG_HPS_CLKR 0x0084 /* HCI Power Save Clock */ +#define SDIO_REG_HSUS_CTRL 0x0086 /* SDIO HCI Suspend Control */ +#define SDIO_REG_HIMR_ON 0x0090 /* SDIO Host Extension Interrupt Mask Always */ +#define SDIO_REG_HISR_ON 0x0091 /* SDIO Host Extension Interrupt Status Always */ + +#define SDIO_HIMR_DISABLED 0 + +/* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */ +#define SDIO_HIMR_RX_REQUEST_MSK BIT(0) +#define SDIO_HIMR_AVAL_MSK BIT(1) +#define SDIO_HIMR_TXERR_MSK BIT(2) +#define SDIO_HIMR_RXERR_MSK BIT(3) +#define SDIO_HIMR_TXFOVW_MSK BIT(4) +#define SDIO_HIMR_RXFOVW_MSK BIT(5) +#define SDIO_HIMR_TXBCNOK_MSK BIT(6) +#define SDIO_HIMR_TXBCNERR_MSK BIT(7) +#define SDIO_HIMR_BCNERLY_INT_MSK BIT(16) +#define SDIO_HIMR_C2HCMD_MSK BIT(17) +#define SDIO_HIMR_CPWM1_MSK BIT(18) +#define SDIO_HIMR_CPWM2_MSK BIT(19) +#define SDIO_HIMR_HSISR_IND_MSK BIT(20) +#define SDIO_HIMR_GTINT3_IND_MSK BIT(21) +#define SDIO_HIMR_GTINT4_IND_MSK BIT(22) +#define SDIO_HIMR_PSTIMEOUT_MSK BIT(23) +#define SDIO_HIMR_OCPINT_MSK BIT(24) +#define SDIO_HIMR_ATIMEND_MSK BIT(25) +#define SDIO_HIMR_ATIMEND_E_MSK BIT(26) +#define SDIO_HIMR_CTWEND_MSK BIT(27) + +/* RTL8188E SDIO Specific */ +#define SDIO_HIMR_MCU_ERR_MSK BIT(28) +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29) + +/* SDIO Host Interrupt Service Routine */ +#define SDIO_HISR_RX_REQUEST BIT(0) +#define SDIO_HISR_AVAL BIT(1) +#define SDIO_HISR_TXERR BIT(2) +#define SDIO_HISR_RXERR BIT(3) +#define SDIO_HISR_TXFOVW BIT(4) +#define SDIO_HISR_RXFOVW BIT(5) +#define SDIO_HISR_TXBCNOK BIT(6) +#define SDIO_HISR_TXBCNERR BIT(7) +#define SDIO_HISR_BCNERLY_INT BIT(16) +#define SDIO_HISR_C2HCMD BIT(17) +#define SDIO_HISR_CPWM1 BIT(18) +#define SDIO_HISR_CPWM2 BIT(19) +#define SDIO_HISR_HSISR_IND BIT(20) +#define SDIO_HISR_GTINT3_IND BIT(21) +#define SDIO_HISR_GTINT4_IND BIT(22) +#define SDIO_HISR_PSTIMEOUT BIT(23) +#define SDIO_HISR_OCPINT BIT(24) +#define SDIO_HISR_ATIMEND BIT(25) +#define SDIO_HISR_ATIMEND_E BIT(26) +#define SDIO_HISR_CTWEND BIT(27) + +/* RTL8188E SDIO Specific */ +#define SDIO_HISR_MCU_ERR BIT(28) +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29) + +#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ + SDIO_HISR_RXERR |\ + SDIO_HISR_TXFOVW |\ + SDIO_HISR_RXFOVW |\ + SDIO_HISR_TXBCNOK |\ + SDIO_HISR_TXBCNERR |\ + SDIO_HISR_C2HCMD |\ + SDIO_HISR_CPWM1 |\ + SDIO_HISR_CPWM2 |\ + SDIO_HISR_HSISR_IND |\ + SDIO_HISR_GTINT3_IND |\ + SDIO_HISR_GTINT4_IND |\ + SDIO_HISR_PSTIMEOUT |\ + SDIO_HISR_OCPINT) + +/* SDIO HCI Suspend Control Register */ +#define HCI_RESUME_PWR_RDY BIT(1) +#define HCI_SUS_CTRL BIT(0) + +/* SDIO Tx FIFO related */ +#define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */ +#define SDIO_TX_FIFO_PAGE_SZ 128 + + #define MAX_TX_AGG_PACKET_NUMBER 0xFF + #define MAX_TX_AGG_PACKET_NUMBER_8812 64 + +/* ----------------------------------------------------- + * + * 0xFE00h ~ 0xFE55h USB Configuration + * + * ----------------------------------------------------- */ + +/* 2 USB Information (0xFE17) */ +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +/* 2 Special Option */ +#define USB_AGG_EN BIT(3) + +/* 0; Use interrupt endpoint to upload interrupt pkt + * 1; Use bulk endpoint to upload interrupt pkt, */ +#define INT_BULK_SEL BIT(4) + +/* 2REG_C2HEVT_CLEAR */ +#define C2H_EVT_HOST_CLOSE 0x00 /* Set by driver and notify FW that the driver has read the C2H command message */ +#define C2H_EVT_FW_CLOSE 0xFF /* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */ + +/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ +#define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source */ +#define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control */ +#define WL_FUNC_EN BIT(2) /* WiFi function enable */ +#define WL_HWROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW PDn source */ +#define BT_HWPDN_EN BIT(16) /* Enable GPIO[11] as BT HW PDn source */ +#define BT_HWPDN_SL BIT(17) /* BT HW PDn polarity control */ +#define BT_FUNC_EN BIT(18) /* BT function enable */ +#define BT_HWROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS RF HW PDn source */ +#define GPS_HWPDN_EN BIT(20) /* Enable GPIO[10] as GPS HW PDn source */ +#define GPS_HWPDN_SL BIT(21) /* GPS HW PDn polarity control */ +#define GPS_FUNC_EN BIT(22) /* GPS function enable */ + +/* 3 REG_LIFECTRL_CTRL */ +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3) +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2) +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1) +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0) + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ + +/* 2 8192D PartNo. */ +#define PARTNO_92D_NIC (BIT7 | BIT6) +#define PARTNO_92D_NIC_REMARK (BIT5 | BIT4) +#define PARTNO_SINGLE_BAND_VS BIT(3) +#define PARTNO_SINGLE_BAND_VS_REMARK BIT(1) +#define PARTNO_CONCURRENT_BAND_VC (BIT3 | BIT2) +#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1 | BIT0) + +/* ******************************************************** + * General definitions + * ******************************************************** */ + +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175) +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723D 255 + +#define POLLING_LLT_THRESHOLD 20 + #define POLLING_READY_TIMEOUT_COUNT 1000 + +/* GPIO BIT */ +#define HAL_8812A_HW_GPIO_WPS_BIT BIT(2) +#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) +#define HAL_8192EU_HW_GPIO_WPS_BIT BIT(7) +#define HAL_8188E_HW_GPIO_WPS_BIT BIT(7) + +#endif /* __HAL_COMMON_H__ */ diff --git a/drivers/staging/rtl8821ce/include/hal_data.h b/drivers/staging/rtl8821ce/include/hal_data.h new file mode 100644 index 000000000000..e035205a6c42 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_data.h @@ -0,0 +1,819 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_DATA_H__ +#define __HAL_DATA_H__ + + +#include "../hal/phydm/phydm_precomp.h" + #include <hal_btcoex.h> +/* + * <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. + * */ +typedef enum _RT_MULTI_FUNC { + RT_MULTI_FUNC_NONE = 0x00, + RT_MULTI_FUNC_WIFI = 0x01, + RT_MULTI_FUNC_BT = 0x02, + RT_MULTI_FUNC_GPS = 0x04, +} RT_MULTI_FUNC, *PRT_MULTI_FUNC; +/* + * <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. + * */ +typedef enum _RT_POLARITY_CTL { + RT_POLARITY_LOW_ACT = 0, + RT_POLARITY_HIGH_ACT = 1, +} RT_POLARITY_CTL, *PRT_POLARITY_CTL; + +/* For RTL8723 regulator mode. by tynli. 2011.01.14. */ +typedef enum _RT_REGULATOR_MODE { + RT_SWITCHING_REGULATOR = 0, + RT_LDO_REGULATOR = 1, +} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; + +/* + * Interface type. + * */ +typedef enum _INTERFACE_SELECT_PCIE { + INTF_SEL0_SOLO_MINICARD = 0, /* WiFi solo-mCard */ + INTF_SEL1_BT_COMBO_MINICARD = 1, /* WiFi+BT combo-mCard */ + INTF_SEL2_PCIe = 2, /* PCIe Card */ +} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; + +typedef enum _INTERFACE_SELECT_USB { + INTF_SEL0_USB = 0, /* USB */ + INTF_SEL1_USB_High_Power = 1, /* USB with high power PA */ + INTF_SEL2_MINICARD = 2, /* Minicard */ + INTF_SEL3_USB_Solo = 3, /* USB solo-Slim module */ + INTF_SEL4_USB_Combo = 4, /* USB Combo-Slim module */ + INTF_SEL5_USB_Combo_MF = 5, /* USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card */ +} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; + +typedef enum _RT_AMPDU_BRUST_MODE { + RT_AMPDU_BRUST_NONE = 0, + RT_AMPDU_BRUST_92D = 1, + RT_AMPDU_BRUST_88E = 2, + RT_AMPDU_BRUST_8812_4 = 3, + RT_AMPDU_BRUST_8812_8 = 4, + RT_AMPDU_BRUST_8812_12 = 5, + RT_AMPDU_BRUST_8812_15 = 6, + RT_AMPDU_BRUST_8723B = 7, +} RT_AMPDU_BRUST, *PRT_AMPDU_BRUST_MODE; + +/* Tx Power Limit Table Size */ +#define MAX_REGULATION_NUM 4 +#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 +#define MAX_2_4G_BANDWIDTH_NUM 2 +#define MAX_RATE_SECTION_NUM 10 +#define MAX_5G_BANDWIDTH_NUM 4 + +#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ +#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ + +/* ###### duplicate code,will move to ODM ######### */ +/* #define IQK_MAC_REG_NUM 4 */ +/* #define IQK_ADDA_REG_NUM 16 */ + +/* #define IQK_BB_REG_NUM 10 */ +#define IQK_BB_REG_NUM_92C 9 +#define IQK_BB_REG_NUM_92D 10 +#define IQK_BB_REG_NUM_test 6 + +#define IQK_Matrix_Settings_NUM_92D (1+24+21) + +/* #define HP_THERMAL_NUM 8 */ +/* ###### duplicate code,will move to ODM ######### */ + + +#define EFUSE_MAX_SIZE 1024 + +#define Mac_OFDM_OK 0x00000000 +#define Mac_OFDM_Fail 0x10000000 +#define Mac_OFDM_FasleAlarm 0x20000000 +#define Mac_CCK_OK 0x30000000 +#define Mac_CCK_Fail 0x40000000 +#define Mac_CCK_FasleAlarm 0x50000000 +#define Mac_HT_OK 0x60000000 +#define Mac_HT_Fail 0x70000000 +#define Mac_HT_FasleAlarm 0x90000000 +#define Mac_DropPacket 0xA0000000 + +/* For store initial value of BB register */ +typedef struct _BB_INIT_REGISTER { + u16 offset; + u32 value; + +} BB_INIT_REGISTER, *PBB_INIT_REGISTER; + +#define PAGE_SIZE_128 128 +#define PAGE_SIZE_256 256 +#define PAGE_SIZE_512 512 + +#define HCI_SUS_ENTER 0 +#define HCI_SUS_LEAVING 1 +#define HCI_SUS_LEAVE 2 +#define HCI_SUS_ENTERING 3 +#define HCI_SUS_ERR 4 + + +#define EFUSE_FILE_UNUSED 0 +#define EFUSE_FILE_FAILED 1 +#define EFUSE_FILE_LOADED 2 + +#define MACADDR_FILE_UNUSED 0 +#define MACADDR_FILE_FAILED 1 +#define MACADDR_FILE_LOADED 2 + +#define KFREE_FLAG_ON BIT(0) +#define KFREE_FLAG_THERMAL_K_ON BIT(1) + +#define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 +#define MAX_IQK_INFO_BACKUP_REG_NUM 10 + +struct kfree_data_t { + u8 flag; + s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; + + s8 pa_bias_5g[RF_PATH_MAX]; + s8 pad_bias_5g[RF_PATH_MAX]; + s8 thermal; +}; + +bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); + +struct hal_spec_t { + char *ic_name; + u8 macid_num; + + u8 sec_cam_ent_num; + u8 sec_cap; + + u8 rfpath_num_2g:4; /* used for tx power index path */ + u8 rfpath_num_5g:4; /* used for tx power index path */ + + u8 max_tx_cnt; + u8 tx_nss_num:4; + u8 rx_nss_num:4; + u8 band_cap; /* value of BAND_CAP_XXX */ + u8 bw_cap; /* value of BW_CAP_XXX */ + u8 port_num; + u8 proto_cap; /* value of PROTO_CAP_XXX */ + u8 wl_func; /* value of WL_FUNC_XXX */ + u8 hci_type; /* value of HCI Type */ +}; + +#define HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) ((_spec)->rfpath_num_2g > (_path)) +#define HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) ((_spec)->rfpath_num_5g > (_path)) +#define HAL_SPEC_CHK_RF_PATH(_spec, _band, _path) ( \ + _band == BAND_ON_2_4G ? HAL_SPEC_CHK_RF_PATH_2G(_spec, _path) : \ + _band == BAND_ON_5G ? HAL_SPEC_CHK_RF_PATH_5G(_spec, _path) : 0) + +#define HAL_SPEC_CHK_TX_CNT(_spec, _cnt_idx) ((_spec)->max_tx_cnt > (_cnt_idx)) + +struct phy_spec_t { + u32 trx_cap; + u32 stbc_cap; + u32 ldpc_cap; + u32 txbf_param; + u32 txbf_cap; +}; +struct hal_iqk_reg_backup { + u8 central_chnl; + u8 bw_mode; + u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; +}; + +typedef struct hal_p2p_ps_para { + /*DW0*/ + u8 offload_en:1; + u8 role:1; + u8 ctwindow_en:1; + u8 noa_en:1; + u8 noa_sel:1; + u8 all_sta_sleep:1; + u8 discovery:1; + u8 rsvd2:1; + u8 p2p_port_id; + u8 p2p_group; + u8 p2p_macid; + + /*DW1*/ + u8 ctwindow_length; + u8 rsvd3; + u8 rsvd4; + u8 rsvd5; + + /*DW2*/ + u32 noa_duration_para; + + /*DW3*/ + u32 noa_interval_para; + + /*DW4*/ + u32 noa_start_time_para; + + /*DW5*/ + u32 noa_count_para; +} HAL_P2P_PS_PARA, *PHAL_P2P_PS_PARA; + +typedef struct hal_com_data { + HAL_VERSION version_id; + RT_MULTI_FUNC MultiFunc; /* For multi-function consideration. */ + RT_POLARITY_CTL PolarityCtl; /* For Wifi PDn Polarity control. */ + RT_REGULATOR_MODE RegulatorMode; /* switching regulator or LDO */ + u8 hw_init_completed; + /****** FW related ******/ + u32 firmware_size; + u16 firmware_version; + u16 FirmwareVersionRev; + u16 firmware_sub_version; + u16 FirmwareSignature; + u8 RegFWOffload; + u8 fw_ractrl; + u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ + u8 LastHMEBoxNum; /* H2C - for host message to fw */ + + /****** current WIFI_PHY values ******/ + WIRELESS_MODE CurrentWirelessMode; + CHANNEL_WIDTH current_channel_bw; + BAND_TYPE current_band_type; /* 0:2.4G, 1:5G */ + BAND_TYPE BandSet; + u8 current_channel; + u8 cch_20; + u8 cch_40; + u8 cch_80; + u8 CurrentCenterFrequencyIndex1; + u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ + u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ + BOOLEAN bSwChnlAndSetBWInProgress; + u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ + u16 BasicRateSet; + u32 ReceiveConfig; + u8 rx_tsf_addr_filter_config; /* for 8822B/8821C USE */ + BOOLEAN bSwChnl; + BOOLEAN bSetChnlBW; + BOOLEAN bSWToBW40M; + BOOLEAN bSWToBW80M; + BOOLEAN bChnlBWInitialized; + u32 BackUp_BB_REG_4_2nd_CCA[3]; + /****** rf_ctrl *****/ + u8 rf_chip; + u8 rf_type; + u8 PackageType; + u8 NumTotalRFPath; + u8 antenna_test; + + /****** Debug ******/ + u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ + u8 u1ForcedIgiLb; /* forced IGI lower bound */ + u8 bDumpRxPkt; + u8 bDumpTxPkt; + u8 bDisableTXPowerTraining; + u8 dis_turboedca; + + /****** EEPROM setting.******/ + u8 bautoload_fail_flag; + u8 efuse_file_status; + u8 macaddr_file_status; + u8 EepromOrEfuse; + u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ + u8 InterfaceSel; /* board type kept in eFuse */ + u16 CustomerID; + + u16 EEPROMVID; + u16 EEPROMSVID; + u16 EEPROMDID; + u16 EEPROMSMID; + u8 EEPROMCustomerID; + u8 EEPROMSubCustomerID; + u8 EEPROMVersion; + u8 EEPROMRegulatory; + u8 eeprom_thermal_meter; + u8 EEPROMBluetoothCoexist; + u8 EEPROMBluetoothType; + u8 EEPROMBluetoothAntNum; + u8 EEPROMBluetoothAntIsolation; + u8 EEPROMBluetoothRadioShared; + u8 EEPROMMACAddr[ETH_ALEN]; + u8 tx_bbswing_24G; + u8 tx_bbswing_5G; + u8 efuse0x3d7; /* efuse[0x3D7] */ + u8 efuse0x3d8; /* efuse[0x3D8] */ + + + u8 EfuseUsedPercentage; + u16 EfuseUsedBytes; + /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ + EFUSE_HAL EfuseHal; + + /*---------------------------------------------------------------------------------*/ + /* 2.4G TX power info for target TX power*/ + u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; + u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; + s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + + /* 5G TX power info for target TX power*/ + u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; + u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; + s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + + u8 Regulation2_4G; + u8 Regulation5G; + + /******************************** + * TX power by rate table at most 4RF path. + * The register is + * + * VHT TX power by rate off setArray = + * Band:-2G&5G = 0 / 1 + * RF: at most 4*4 = ABCD=0/1/2/3 + * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 + **********************************/ + + u8 txpwr_by_rate_undefined_band_path[TX_PWR_BY_RATE_NUM_BAND] + [TX_PWR_BY_RATE_NUM_RF]; + + s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RATE]; + + /* --------------------------------------------------------------------------------- */ + + u8 tx_pwr_lmt_5g_20_40_ref; + + /* Power Limit Table for 2.4G */ + s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] + [MAX_2_4G_BANDWIDTH_NUM] + [MAX_RATE_SECTION_NUM] + [CENTER_CH_2G_NUM] + [MAX_RF_PATH]; + + /* Power Limit Table for 5G */ + s8 TxPwrLimit_5G[MAX_REGULATION_NUM] + [MAX_5G_BANDWIDTH_NUM] + [MAX_RATE_SECTION_NUM] + [CENTER_CH_5G_ALL_NUM] + [MAX_RF_PATH]; + + + /* Store the original power by rate value of the base of each rate section of rf path A & B */ + u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; + u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; + + u8 txpwr_by_rate_loaded:1; + u8 txpwr_by_rate_from_file:1; + u8 txpwr_limit_loaded:1; + u8 txpwr_limit_from_file:1; + u8 rf_power_tracking_type; + + /* Read/write are allow for following hardware information variables */ + u8 crystal_cap; + + u8 PAType_2G; + u8 PAType_5G; + u8 LNAType_2G; + u8 LNAType_5G; + u8 ExternalPA_2G; + u8 ExternalLNA_2G; + u8 external_pa_5g; + u8 external_lna_5g; + u16 TypeGLNA; + u16 TypeGPA; + u16 TypeALNA; + u16 TypeAPA; + u16 rfe_type; + + u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ + u32 ac_param_be; /* Original parameter for BE, use for EDCA turbo. */ + u8 is_turbo_edca; + u8 prv_traffic_idx; + BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; /* Radio A/B/C/D */ + + u32 RfRegChnlVal[MAX_RF_PATH]; + + /* RDG enable */ + BOOLEAN bRDGEnable; + + u8 RegTxPause; + /* Beacon function related global variable. */ + u8 RegBcnCtrlVal; + u8 RegFwHwTxQCtrl; + u8 RegReg542; + u8 RegCR_1; + u8 Reg837; + u16 RegRRSR; + + /****** antenna diversity ******/ + u8 AntDivCfg; + u8 with_extenal_ant_switch; + u8 b_fix_tx_ant; + u8 AntDetection; + u8 TRxAntDivType; + u8 ant_path; /* for 8723B s0/s1 selection */ + u32 antenna_tx_path; /* Antenna path Tx */ + u32 AntennaRxPath; /* Antenna path Rx */ + u8 sw_antdiv_bl_state; + + /******** PHY DM & DM Section **********/ + u8 DM_Type; + _lock IQKSpinLock; + u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; + /* Upper and Lower Signal threshold for Rate Adaptive*/ + int entry_min_undecorated_smoothed_pwdb; + int entry_max_undecorated_smoothed_pwdb; + int min_undecorated_pwdb_for_dm; + struct PHY_DM_STRUCT odmpriv; + u8 bIQKInitialized; + u8 bNeedIQK; + u8 IQK_MP_Switch; + /******** PHY DM & DM Section **********/ + + /* 2010/08/09 MH Add CU power down mode. */ + BOOLEAN pwrdown; + + /* Add for dual MAC 0--Mac0 1--Mac1 */ + u32 interfaceIndex; + + u8 p2p_ps_offload; + /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ + u8 bMacPwrCtrlOn; + u8 hci_sus_state; + + u8 RegIQKFWOffload; + struct submit_ctx iqk_sctx; + + RT_AMPDU_BRUST AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ + + u8 OutEpQueueSel; + u8 OutEpNumber; + + + /* */ + /* EEPROM setting. */ + /* */ + u32 TransmitConfig; + u32 IntrMaskToSet[2]; + u32 IntArray[4]; + u32 IntrMask[4]; + u32 SysIntArray[1]; + u32 SysIntrMask[1]; + u32 IntrMaskReg[2]; + u32 IntrMaskDefault[4]; + + BOOLEAN bL1OffSupport; + BOOLEAN bSupportBackDoor; + u32 pci_backdoor_ctrl; + + u8 bDefaultAntenna; + + u8 bInterruptMigration; + u8 bDisableTxInt; + + u16 RxTag; + + struct sreset_priv srestpriv; + + /* For bluetooth co-existance */ + BT_COEXIST bt_coexist; + + char para_file_buf[MAX_PARA_FILE_BUF_LEN]; + char *mac_reg; + u32 mac_reg_len; + char *bb_phy_reg; + u32 bb_phy_reg_len; + char *bb_agc_tab; + u32 bb_agc_tab_len; + char *bb_phy_reg_pg; + u32 bb_phy_reg_pg_len; + char *bb_phy_reg_mp; + u32 bb_phy_reg_mp_len; + char *rf_radio_a; + u32 rf_radio_a_len; + char *rf_radio_b; + u32 rf_radio_b_len; + char *rf_tx_pwr_track; + u32 rf_tx_pwr_track_len; + char *rf_tx_pwr_lmt; + u32 rf_tx_pwr_lmt_len; + + + struct hal_spec_t hal_spec; + struct phy_spec_t phy_spec; + u8 RfKFreeEnable; + u8 RfKFree_ch_group; + BOOLEAN bCCKinCH14; + BB_INIT_REGISTER RegForRecover[5]; + +#if defined(RTL8814AE_SW_BCN) + BOOLEAN bCorrectBCN; +#endif + u32 RxGainOffset[4]; /*{2G, 5G_Low, 5G_Middle, G_High}*/ + u8 BackUp_IG_REG_4_Chnl_Section[4]; /*{A,B,C,D}*/ + + struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; + + u8 drv_rsvd_page_number; + + + u8 not_xmitframe_fw_dl; /*not use xmitframe to download fw*/ +} HAL_DATA_COMMON, *PHAL_DATA_COMMON; + +typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; +#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) +#define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) +#define GET_ODM(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->odmpriv)) + +#define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath) +#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) +#define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type) +#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) + +#define SUPPORT_HW_RADIO_DETECT(Adapter) (RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD || \ + RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo || \ + RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) + +#define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) +#define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) +#define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) +#define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) + + +int rtw_halmac_deinit_adapter(struct dvobj_priv *); + +/* alias for phydm coding style */ +#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance +#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold +#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack +#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage +#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 +#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 +#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar +#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar + +#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW +#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter +#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 +#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter +#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE +#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 +#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter +#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack +#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE +#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW +#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl +#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock +#define REG_FPGA1_TX_INFO rFPGA1_TxInfo +#define REG_IQK_AGC_CONT rIQK_AGC_Cont +#define REG_IQK_AGC_PTS rIQK_AGC_Pts +#define REG_IQK_AGC_RSP rIQK_AGC_Rsp +#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable +#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold +#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta +#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar +#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable +#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 +#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance +#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance +#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 +#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance +#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance +#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE +#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE + +/*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/ +#define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar +/*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/ +#define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar +#define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar +/*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/ +#define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar +/*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/ +#define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar +/*#define REG_A_TX_AGC rA_TXAGC*/ +#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar +#define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar +/*#define REG_B_BBSWING rB_BBSWING*/ +/*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/ +#define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar +/*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/ +#define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar +/*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/ +#define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar +/*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/ +#define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar +/*#define REG_B_TX_AGC rB_TXAGC*/ +#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar +#define REG_BLUE_TOOTH rBlue_Tooth +#define REG_CCK_0_AFE_SETTING rCCK0_AFESetting +/*#define REG_C_BBSWING rC_BBSWING*/ +/*#define REG_C_TX_AGC rC_TXAGC*/ +#define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2 +#define REG_CONFIG_ANT_A rConfig_AntA +#define REG_CONFIG_ANT_B rConfig_AntB +#define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA +#define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB +#define REG_DPDT_CONTROL rDPDT_control +/*#define REG_D_BBSWING rD_BBSWING*/ +/*#define REG_D_TX_AGC rD_TXAGC*/ +#define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2 +#define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4 +#define REG_FPGA0_IQK rFPGA0_IQK +#define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction +#define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport +#define REG_FPGA0_RFMOD rFPGA0_RFMOD +#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage +#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW +#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter +#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1 +#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter +#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE +#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1 +#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter +#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack +#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE +#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW +#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl +#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock +#define REG_FPGA1_TX_INFO rFPGA1_TxInfo +#define REG_IQK_AGC_CONT rIQK_AGC_Cont +#define REG_IQK_AGC_PTS rIQK_AGC_Pts +#define REG_IQK_AGC_RSP rIQK_AGC_Rsp +#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable +#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold +#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta +#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar +#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable +#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1 +#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance +#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance +#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1 +#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance +#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance +#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE +#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE +#define REG_PMPD_ANAEN rPMPD_ANAEN +#define REG_PDP_ANT_A rPdp_AntA +#define REG_PDP_ANT_A_4 rPdp_AntA_4 +#define REG_PDP_ANT_B rPdp_AntB +#define REG_PDP_ANT_B_4 rPdp_AntB_4 +#define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar +#define REG_RX_CCK rRx_CCK +#define REG_RX_IQK rRx_IQK +#define REG_RX_IQK_PI_A rRx_IQK_PI_A +#define REG_RX_IQK_PI_B rRx_IQK_PI_B +#define REG_RX_IQK_TONE_A rRx_IQK_Tone_A +#define REG_RX_IQK_TONE_B rRx_IQK_Tone_B +#define REG_RX_OFDM rRx_OFDM +#define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2 +#define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2 +#define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2 +#define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2 +#define REG_RX_TO_RX rRx_TO_Rx +#define REG_RX_WAIT_CCA rRx_Wait_CCA +#define REG_RX_WAIT_RIFS rRx_Wait_RIFS +#define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch +/*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/ +#define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar +/*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/ +#define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar +#define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL +#define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar +#define REG_SLEEP rSleep +#define REG_STANDBY rStandby +#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar +#define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32 +#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar +#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar +#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar +#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar +#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar +#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar +#define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00 +#define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04 +#define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08 +#define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12 +#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar +#define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06 +#define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24 +#define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11 +#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar +#define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32 +#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar +#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar +#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar +#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar +#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar +#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar +#define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00 +#define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04 +#define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08 +#define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12 +#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar +#define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06 +#define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24 +#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar +#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar +#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar +#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar +#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar +#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar +#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar +#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar +#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar +#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar +#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar +#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar +#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar +#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar +#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar +#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar +#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar +#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar +#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar +#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar +#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar +#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar +#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar +#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar +#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar +#define REG_TX_PATH_JAGUAR rTxPath_Jaguar +#define REG_TX_CCK_BBON rTx_CCK_BBON +#define REG_TX_CCK_RFON rTx_CCK_RFON +#define REG_TX_IQK rTx_IQK +#define REG_TX_IQK_PI_A rTx_IQK_PI_A +#define REG_TX_IQK_PI_B rTx_IQK_PI_B +#define REG_TX_IQK_TONE_A rTx_IQK_Tone_A +#define REG_TX_IQK_TONE_B rTx_IQK_Tone_B +#define REG_TX_OFDM_BBON rTx_OFDM_BBON +#define REG_TX_OFDM_RFON rTx_OFDM_RFON +#define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A +#define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B +#define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A +#define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B +#define REG_TX_TO_RX rTx_To_Rx +#define REG_TX_TO_TX rTx_To_Tx +#define REG_APK rAPK +#define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar + +#define rf_welut_jaguar RF_WeLut_Jaguar +#define rf_mode_table_addr RF_ModeTableAddr +#define rf_mode_table_data0 RF_ModeTableData0 +#define rf_mode_table_data1 RF_ModeTableData1 + +#define RX_SMOOTH_FACTOR Rx_Smooth_Factor + +#endif /* __HAL_DATA_H__ */ diff --git a/drivers/staging/rtl8821ce/include/hal_ic_cfg.h b/drivers/staging/rtl8821ce/include/hal_ic_cfg.h new file mode 100644 index 000000000000..452ea325947c --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_ic_cfg.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_IC_CFG_H__ +#define __HAL_IC_CFG_H__ + +#define POWER_TRAINING_ACTIVE 0 + +#define CONFIG_SUPPORT_FIFO_DUMP + +#endif /*__HAL_IC_CFG_H__*/ diff --git a/drivers/staging/rtl8821ce/include/hal_intf.h b/drivers/staging/rtl8821ce/include/hal_intf.h new file mode 100644 index 000000000000..858c189d13db --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_intf.h @@ -0,0 +1,655 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_INTF_H__ +#define __HAL_INTF_H__ + +enum RTL871X_HCI_TYPE { + RTW_PCIE = BIT0, + RTW_USB = BIT1, + RTW_SDIO = BIT2, + RTW_GSPI = BIT3, +}; + +enum _CHIP_TYPE { + + NULL_CHIP_TYPE, + RTL8188E, + RTL8192E, + RTL8812, + RTL8821, /* RTL8811 */ + RTL8723B, + RTL8814A, + RTL8703B, + RTL8188F, + RTL8822B, + RTL8723D, + RTL8821C, + MAX_CHIP_TYPE +}; + +enum fw_mem { + FW_EMEM, + FW_IMEM, + FW_DMEM, +}; + +extern const u32 _chip_type_to_odm_ic_type[]; +#define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)]) + +typedef enum _HAL_HW_TIMER_TYPE { + HAL_TIMER_NONE = 0, + HAL_TIMER_TXBF = 1, + HAL_TIMER_EARLYMODE = 2, +} HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE; + +typedef enum _HW_VARIABLES { + HW_VAR_MEDIA_STATUS, + HW_VAR_SET_OPMODE, + HW_VAR_MAC_ADDR, + HW_VAR_BSSID, + HW_VAR_INIT_RTS_RATE, + HW_VAR_BASIC_RATE, + HW_VAR_TXPAUSE, + HW_VAR_BCN_FUNC, + HW_VAR_CORRECT_TSF, + HW_VAR_CHECK_BSSID, + HW_VAR_MLME_DISCONNECT, + HW_VAR_MLME_SITESURVEY, + HW_VAR_MLME_JOIN, + HW_VAR_ON_RCR_AM, + HW_VAR_OFF_RCR_AM, + HW_VAR_BEACON_INTERVAL, + HW_VAR_SLOT_TIME, + HW_VAR_RESP_SIFS, + HW_VAR_ACK_PREAMBLE, + HW_VAR_SEC_CFG, + HW_VAR_SEC_DK_CFG, + HW_VAR_BCN_VALID, + HW_VAR_RF_TYPE, + /* PHYDM odm->SupportAbility */ + HW_VAR_CAM_EMPTY_ENTRY, + HW_VAR_CAM_INVALID_ALL, + HW_VAR_AC_PARAM_VO, + HW_VAR_AC_PARAM_VI, + HW_VAR_AC_PARAM_BE, + HW_VAR_AC_PARAM_BK, + HW_VAR_ACM_CTRL, + HW_VAR_AMPDU_MIN_SPACE, + HW_VAR_AMPDU_FACTOR, + HW_VAR_RXDMA_AGG_PG_TH, + HW_VAR_SET_RPWM, + HW_VAR_CPWM, + HW_VAR_H2C_FW_PWRMODE, + HW_VAR_H2C_PS_TUNE_PARAM, + HW_VAR_H2C_FW_JOINBSSRPT, + HW_VAR_FWLPS_RF_ON, + HW_VAR_H2C_FW_P2P_PS_OFFLOAD, + HW_VAR_TRIGGER_GPIO_0, + HW_VAR_BT_SET_COEXIST, + HW_VAR_BT_ISSUE_DELBA, + HW_VAR_SWITCH_EPHY_WoWLAN, + HW_VAR_EFUSE_USAGE, + HW_VAR_EFUSE_BYTES, + HW_VAR_EFUSE_BT_USAGE, + HW_VAR_EFUSE_BT_BYTES, + HW_VAR_FIFO_CLEARN_UP, + HW_VAR_RESTORE_HW_SEQ, + HW_VAR_CHECK_TXBUF, + HW_VAR_PCIE_STOP_TX_DMA, + HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ + HW_VAR_HCI_SUS_STATE, + /* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */ + /* Unit in microsecond. 0 means disable this function. */ + HW_VAR_RPWM_TOG, + HW_VAR_SYS_CLKR, + HW_VAR_NAV_UPPER, + HW_VAR_RPT_TIMER_SETTING, + HW_VAR_TX_RPT_MAX_MACID, + HW_VAR_CHK_HI_QUEUE_EMPTY, + HW_VAR_DL_BCN_SEL, + HW_VAR_AMPDU_MAX_TIME, + HW_VAR_WIRELESS_MODE, + HW_VAR_USB_MODE, + HW_VAR_PORT_SWITCH, + HW_VAR_DO_IQK, + HW_VAR_DM_IN_LPS, + HW_VAR_SET_REQ_FW_PS, + HW_VAR_FW_PS_STATE, + HW_VAR_SOUNDING_ENTER, + HW_VAR_SOUNDING_LEAVE, + HW_VAR_SOUNDING_RATE, + HW_VAR_SOUNDING_STATUS, + HW_VAR_SOUNDING_FW_NDPA, + HW_VAR_SOUNDING_CLK, + HW_VAR_SOUNDING_SET_GID_TABLE, + HW_VAR_SOUNDING_CSI_REPORT, + /*Add by YuChen for TXBF HW timer*/ + HW_VAR_HW_REG_TIMER_INIT, + HW_VAR_HW_REG_TIMER_RESTART, + HW_VAR_HW_REG_TIMER_START, + HW_VAR_HW_REG_TIMER_STOP, + /*Add by YuChen for TXBF HW timer*/ + HW_VAR_DL_RSVD_PAGE, + HW_VAR_MACID_LINK, + HW_VAR_MACID_NOLINK, + HW_VAR_MACID_SLEEP, + HW_VAR_MACID_WAKEUP, + HW_VAR_DUMP_MAC_QUEUE_INFO, + HW_VAR_ASIX_IOT, + HW_VAR_EN_HW_UPDATE_TSF, + HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, + HW_VAR_CH_SW_IQK_INFO_BACKUP, + HW_VAR_CH_SW_IQK_INFO_RESTORE, + + HW_VAR_DBI, + HW_VAR_MDIO, + HW_VAR_L1OFF_CAPABILITY, + HW_VAR_L1OFF_NIC_SUPPORT, +} HW_VARIABLES; + +typedef enum _HAL_DEF_VARIABLE { + HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, + HAL_DEF_IS_SUPPORT_ANT_DIV, + HAL_DEF_DRVINFO_SZ, + HAL_DEF_MAX_RECVBUF_SZ, + HAL_DEF_RX_PACKET_OFFSET, + HAL_DEF_RX_DMA_SZ_WOW, + HAL_DEF_RX_DMA_SZ, + HAL_DEF_RX_PAGE_SIZE, + HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */ + HAL_DEF_RA_DECISION_RATE, + HAL_DEF_RA_SGI, + HAL_DEF_PT_PWR_STATUS, + HAL_DEF_TX_LDPC, /* LDPC support */ + HAL_DEF_RX_LDPC, /* LDPC support */ + HAL_DEF_TX_STBC, /* TX STBC support */ + HAL_DEF_RX_STBC, /* RX STBC support */ + HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit Compressed Steering Capable */ + HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */ + HAL_DEF_VHT_MU_BEAMFORMER, /* VHT MU Beamformer support */ + HAL_DEF_VHT_MU_BEAMFORMEE, /* VHT MU Beamformee support */ + HAL_DEF_BEAMFORMER_CAP, + HAL_DEF_BEAMFORMEE_CAP, + HW_VAR_MAX_RX_AMPDU_FACTOR, + HW_DEF_RA_INFO_DUMP, + HAL_DEF_DBG_DUMP_TXPKT, + + HAL_DEF_TX_PAGE_SIZE, + HAL_DEF_TX_PAGE_BOUNDARY, + HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN, + HAL_DEF_ANT_DETECT,/* to do for 8723a */ + HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, /* Determine if the L1 Backdoor setting is turned on. */ + HAL_DEF_PCI_AMD_L1_SUPPORT, + HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */ + HAL_DEF_MACID_SLEEP, /* Support for MACID sleep */ + HAL_DEF_DBG_DIS_PWT, /* disable Tx power training or not. */ + HAL_DEF_EFUSE_USAGE, /* Get current EFUSE utilization. 2008.12.19. Added by Roger. */ + HAL_DEF_EFUSE_BYTES, + HW_VAR_BEST_AMPDU_DENSITY, +} HAL_DEF_VARIABLE; + +typedef enum _HAL_ODM_VARIABLE { + HAL_ODM_STA_INFO, + HAL_ODM_P2P_STATE, + HAL_ODM_WIFI_DISPLAY_STATE, + HAL_ODM_NOISE_MONITOR, + HAL_ODM_REGULATION, + HAL_ODM_INITIAL_GAIN, + HAL_ODM_FA_CNT_DUMP, + HAL_ODM_DBG_FLAG, + HAL_ODM_DBG_LEVEL, + HAL_ODM_RX_INFO_DUMP, + HAL_ODM_RX_Dframe_INFO, +} HAL_ODM_VARIABLE; + +typedef enum _HAL_INTF_PS_FUNC { + HAL_USB_SELECT_SUSPEND, + HAL_MAX_ID, +} HAL_INTF_PS_FUNC; + +typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); + +struct txpwr_idx_comp; + +struct macid_cfg { + u8 mac_id; + u8 rate_id; + u8 bandwidth; + u8 short_gi; + u8 ignore_bw; + u8 rsvd; + u16 rsvd1; + u64 ra_mask; +}; + +struct hal_ops { + /*** initialize section ***/ + void (*read_chip_version)(_adapter *padapter); + void (*init_default_value)(_adapter *padapter); + void (*intf_chip_configure)(_adapter *padapter); + u8 (*read_adapter_info)(_adapter *padapter); + u32(*hal_power_on)(_adapter *padapter); + void (*hal_power_off)(_adapter *padapter); + u32(*hal_init)(_adapter *padapter); + u32(*hal_deinit)(_adapter *padapter); + void (*dm_init)(_adapter *padapter); + void (*dm_deinit)(_adapter *padapter); + + /*** xmit section ***/ + s32(*init_xmit_priv)(_adapter *padapter); + void (*free_xmit_priv)(_adapter *padapter); + s32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe); + /* + * mgnt_xmit should be implemented to run in interrupt context + */ + s32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe); + s32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe); + void (*run_thread)(_adapter *padapter); + void (*cancel_thread)(_adapter *padapter); + + /*** recv section ***/ + s32(*init_recv_priv)(_adapter *padapter); + void (*free_recv_priv)(_adapter *padapter); + u32(*inirp_init)(_adapter *padapter); + u32(*inirp_deinit)(_adapter *padapter); + /*** interrupt hdl section ***/ + void (*enable_interrupt)(_adapter *padapter); + void (*disable_interrupt)(_adapter *padapter); + u8(*check_ips_status)(_adapter *padapter); + s32(*interrupt_handler)(_adapter *padapter); + void (*irp_reset)(_adapter *padapter); + /*** DM section ***/ + + void (*InitSwLeds)(_adapter *padapter); + void (*DeInitSwLeds)(_adapter *padapter); + + void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); + + void (*set_tx_power_level_handler)(_adapter *padapter, u8 channel); + void (*get_tx_power_level_handler)(_adapter *padapter, s32 *powerlevel); + + void (*set_tx_power_index_handler)(_adapter *padapter, u32 powerindex, u8 rfpath, u8 rate); + u8(*get_tx_power_index_handler)(_adapter *padapter, u8 rfpath, u8 rate, u8 bandwidth, u8 channel, struct txpwr_idx_comp *tic); + + void (*hal_dm_watchdog)(_adapter *padapter); + + void (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val); + + void (*GetHwRegHandler)(_adapter *padapter, u8 variable, u8 *val); + + u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + + u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + + void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2); + void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); + + void (*update_ra_mask_handler)(_adapter *padapter, struct sta_info *psta, struct macid_cfg *h2c_macid_cfg); + void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter); + + u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); + + u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask); + void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); + u32(*read_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask); + void (*write_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); + + + void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState); + void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState); + void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest); + void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); + u16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest); + int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); + int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + + void (*sreset_init_value)(_adapter *padapter); + void (*sreset_reset_value)(_adapter *padapter); + void (*silentreset)(_adapter *padapter); + void (*sreset_xmit_status_check)(_adapter *padapter); + void (*sreset_linked_status_check)(_adapter *padapter); + u8(*sreset_get_wifi_status)(_adapter *padapter); + bool (*sreset_inprogress)(_adapter *padapter); + + + void (*hal_notch_filter)(_adapter *adapter, bool enable); + void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length); + void (*reqtxrpt)(_adapter *padapter, u8 macid); + s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); + void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); + s32(*fw_dl)(_adapter *adapter); + s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem); + + void (*clear_interrupt)(_adapter *padapter); + u8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan); + void (*fw_correct_bcn)(PADAPTER padapter); + + u8(*init_mac_register)(PADAPTER); + u8(*init_phy)(PADAPTER); + + void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable); + +}; + +typedef enum _RT_EEPROM_TYPE { + EEPROM_93C46, + EEPROM_93C56, + EEPROM_BOOT_EFUSE, +} RT_EEPROM_TYPE, *PRT_EEPROM_TYPE; + +#define RF_CHANGE_BY_INIT 0 +#define RF_CHANGE_BY_IPS BIT28 +#define RF_CHANGE_BY_PS BIT29 +#define RF_CHANGE_BY_HW BIT30 +#define RF_CHANGE_BY_SW BIT31 + +typedef enum _HARDWARE_TYPE { + HARDWARE_TYPE_RTL8188EE, + HARDWARE_TYPE_RTL8188EU, + HARDWARE_TYPE_RTL8188ES, + /* NEW_GENERATION_IC */ + HARDWARE_TYPE_RTL8192EE, + HARDWARE_TYPE_RTL8192EU, + HARDWARE_TYPE_RTL8192ES, + HARDWARE_TYPE_RTL8812E, + HARDWARE_TYPE_RTL8812AU, + HARDWARE_TYPE_RTL8811AU, + HARDWARE_TYPE_RTL8821E, + HARDWARE_TYPE_RTL8821U, + HARDWARE_TYPE_RTL8821S, + HARDWARE_TYPE_RTL8723BE, + HARDWARE_TYPE_RTL8723BU, + HARDWARE_TYPE_RTL8723BS, + HARDWARE_TYPE_RTL8814AE, + HARDWARE_TYPE_RTL8814AU, + HARDWARE_TYPE_RTL8814AS, + HARDWARE_TYPE_RTL8821BE, + HARDWARE_TYPE_RTL8821BU, + HARDWARE_TYPE_RTL8821BS, + HARDWARE_TYPE_RTL8822BE, + HARDWARE_TYPE_RTL8822BU, + HARDWARE_TYPE_RTL8822BS, + HARDWARE_TYPE_RTL8703BE, + HARDWARE_TYPE_RTL8703BU, + HARDWARE_TYPE_RTL8703BS, + HARDWARE_TYPE_RTL8188FE, + HARDWARE_TYPE_RTL8188FU, + HARDWARE_TYPE_RTL8188FS, + HARDWARE_TYPE_RTL8723DE, + HARDWARE_TYPE_RTL8723DU, + HARDWARE_TYPE_RTL8723DS, + HARDWARE_TYPE_RTL8821CE, + HARDWARE_TYPE_RTL8821CU, + HARDWARE_TYPE_RTL8821CS, + HARDWARE_TYPE_MAX, +} HARDWARE_TYPE; + +#define IS_NEW_GENERATION_IC(_Adapter) (rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE) +/* + * RTL8188E Series + * */ +#define IS_HARDWARE_TYPE_8188EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE) +#define IS_HARDWARE_TYPE_8188EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU) +#define IS_HARDWARE_TYPE_8188ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES) +#define IS_HARDWARE_TYPE_8188E(_Adapter) \ + (IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter)) + +/* RTL8812 Series */ +#define IS_HARDWARE_TYPE_8812E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E) +#define IS_HARDWARE_TYPE_8812AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU) +#define IS_HARDWARE_TYPE_8812(_Adapter) \ + (IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter)) + +/* RTL8821 Series */ +#define IS_HARDWARE_TYPE_8821E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E) +#define IS_HARDWARE_TYPE_8811AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU) +#define IS_HARDWARE_TYPE_8821U(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \ + rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU) +#define IS_HARDWARE_TYPE_8821S(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S) +#define IS_HARDWARE_TYPE_8821(_Adapter) \ + (IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter)) + +#define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \ + (IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter)) + +/* RTL8192E Series */ +#define IS_HARDWARE_TYPE_8192EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE) +#define IS_HARDWARE_TYPE_8192EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU) +#define IS_HARDWARE_TYPE_8192ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES) + +#define IS_HARDWARE_TYPE_8192E(_Adapter) \ + (IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter)) + +#define IS_HARDWARE_TYPE_8723BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE) +#define IS_HARDWARE_TYPE_8723BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU) +#define IS_HARDWARE_TYPE_8723BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS) + +#define IS_HARDWARE_TYPE_8723B(_Adapter) \ + (IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter)) + +/* RTL8814A Series */ +#define IS_HARDWARE_TYPE_8814AE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE) +#define IS_HARDWARE_TYPE_8814AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU) +#define IS_HARDWARE_TYPE_8814AS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS) + +#define IS_HARDWARE_TYPE_8814A(_Adapter) \ + (IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter)) + +/* RTL8703B Series */ +#define IS_HARDWARE_TYPE_8703BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE) +#define IS_HARDWARE_TYPE_8703BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS) +#define IS_HARDWARE_TYPE_8703BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU) +#define IS_HARDWARE_TYPE_8703B(_Adapter) \ + (IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter)) + +/* RTL8723D Series */ +#define IS_HARDWARE_TYPE_8723DE(_Adapter)\ + (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE) +#define IS_HARDWARE_TYPE_8723DS(_Adapter)\ + (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS) +#define IS_HARDWARE_TYPE_8723DU(_Adapter)\ + (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU) +#define IS_HARDWARE_TYPE_8723D(_Adapter)\ + (IS_HARDWARE_TYPE_8723DE(_Adapter) || \ + IS_HARDWARE_TYPE_8723DU(_Adapter) || \ + IS_HARDWARE_TYPE_8723DS(_Adapter)) + +/* RTL8188F Series */ +#define IS_HARDWARE_TYPE_8188FE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE) +#define IS_HARDWARE_TYPE_8188FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS) +#define IS_HARDWARE_TYPE_8188FU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU) +#define IS_HARDWARE_TYPE_8188F(_Adapter) \ + (IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter)) + +#define IS_HARDWARE_TYPE_8821BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE) +#define IS_HARDWARE_TYPE_8821BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU) +#define IS_HARDWARE_TYPE_8821BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS) + +#define IS_HARDWARE_TYPE_8821B(_Adapter) \ + (IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter)) + +#define IS_HARDWARE_TYPE_8822BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE) +#define IS_HARDWARE_TYPE_8822BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU) +#define IS_HARDWARE_TYPE_8822BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS) +#define IS_HARDWARE_TYPE_8822B(_Adapter) \ + (IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter)) + +#define IS_HARDWARE_TYPE_8821CE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE) +#define IS_HARDWARE_TYPE_8821CU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU) +#define IS_HARDWARE_TYPE_8821CS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS) +#define IS_HARDWARE_TYPE_8821C(_Adapter) \ + (IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter)) + +#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter) \ + (IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter)) + +#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) \ + (IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter)) + +typedef enum _wowlan_subcode { + WOWLAN_ENABLE = 0, + WOWLAN_DISABLE = 1, + WOWLAN_AP_ENABLE = 2, + WOWLAN_AP_DISABLE = 3, + WOWLAN_PATTERN_CLEAN = 4 +} wowlan_subcode; + +struct wowlan_ioctl_param { + unsigned int subcode; + unsigned int subcode_value; + unsigned int wakeup_reason; +}; + +u8 rtw_hal_data_init(_adapter *padapter); +void rtw_hal_data_deinit(_adapter *padapter); + +void rtw_hal_def_value_init(_adapter *padapter); + +void rtw_hal_free_data(_adapter *padapter); + +void rtw_hal_dm_init(_adapter *padapter); +void rtw_hal_dm_deinit(_adapter *padapter); +void rtw_hal_sw_led_init(_adapter *padapter); +void rtw_hal_sw_led_deinit(_adapter *padapter); + +u32 rtw_hal_power_on(_adapter *padapter); +void rtw_hal_power_off(_adapter *padapter); + +uint rtw_hal_init(_adapter *padapter); +uint rtw_hal_deinit(_adapter *padapter); +void rtw_hal_stop(_adapter *padapter); +void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); +void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); + +void rtw_hal_chip_configure(_adapter *padapter); +u8 rtw_hal_read_chip_info(_adapter *padapter); +void rtw_hal_read_chip_version(_adapter *padapter); + +u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); +u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + +void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, BOOLEAN bSet); +void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1, PVOID pValue2); + +void rtw_hal_enable_interrupt(_adapter *padapter); +void rtw_hal_disable_interrupt(_adapter *padapter); + +u8 rtw_hal_check_ips_status(_adapter *padapter); + +u32 rtw_hal_inirp_init(_adapter *padapter); +u32 rtw_hal_inirp_deinit(_adapter *padapter); + +void rtw_hal_irp_reset(_adapter *padapter); +void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data); +u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr); +void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data); +u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr); +u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter); +u8 rtw_hal_pci_l1off_capability(_adapter *padapter); + +u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); + +s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); + +s32 rtw_hal_init_xmit_priv(_adapter *padapter); +void rtw_hal_free_xmit_priv(_adapter *padapter); + +s32 rtw_hal_init_recv_priv(_adapter *padapter); +void rtw_hal_free_recv_priv(_adapter *padapter); + +void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level, u8 is_update_bw); +void rtw_update_ramask(_adapter *padapter, struct sta_info *psta, u32 mac_id, u8 rssi_level, u8 is_update_bw); + +void rtw_hal_start_thread(_adapter *padapter); +void rtw_hal_stop_thread(_adapter *padapter); + +void rtw_hal_bcn_related_reg_setting(_adapter *padapter); + +u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask); +void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); +u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); +void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); + +#define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) +#define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data)) +#define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask)) +#define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) + +#define phy_set_mac_reg phy_set_bb_reg +#define phy_query_mac_reg phy_query_bb_reg + +s32 rtw_hal_interrupt_handler(_adapter *padapter); + +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); +void rtw_hal_dm_watchdog(_adapter *padapter); +void rtw_hal_dm_watchdog_in_lps(_adapter *padapter); + +void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel); +void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel); + + +void rtw_hal_sreset_init(_adapter *padapter); +void rtw_hal_sreset_reset(_adapter *padapter); +void rtw_hal_sreset_reset_value(_adapter *padapter); +void rtw_hal_sreset_xmit_status_check(_adapter *padapter); +void rtw_hal_sreset_linked_status_check(_adapter *padapter); +u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter); +bool rtw_hal_sreset_inprogress(_adapter *padapter); + + + + +void rtw_hal_notch_filter(_adapter *adapter, bool enable); + + +bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload); + +s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); + +s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter); + +s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid); +s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid); + +s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); +void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); +u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan); + + +void rtw_hal_fw_correct_bcn(_adapter *padapter); +s32 rtw_hal_fw_dl(_adapter *padapter); + +void rtw_hal_set_tx_power_index(PADAPTER, u32 powerindex, u8 rfpath, u8 rate); +u8 rtw_hal_get_tx_power_index(PADAPTER, u8 rfpath, u8 rate, u8 bandwidth, u8 channel,struct txpwr_idx_comp *tic); + +u8 rtw_hal_ops_check(_adapter *padapter); + + u8 rtw_hal_init_mac_register(PADAPTER); + u8 rtw_hal_init_phy(PADAPTER); +s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem); + +#endif /* __HAL_INTF_H__ */ diff --git a/drivers/staging/rtl8821ce/include/hal_pg.h b/drivers/staging/rtl8821ce/include/hal_pg.h new file mode 100644 index 000000000000..e88726f6e308 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_pg.h @@ -0,0 +1,776 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PG_H__ +#define __HAL_PG_H__ + +#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F +#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0 + +#define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F +#define PPG_THERMAL_OFFSET_MASK 0x1F +#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) +#define KFREE_BB_GAIN_2G_TXB_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TXB_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x10) ? ((_ppg_v) >> 5) : (-((_ppg_v) >> 5)))) +#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) +#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) + +/* **************************************************** + * EEPROM/Efuse PG Offset for 88EE/88EU/88ES + * **************************************************** */ +#define EEPROM_TX_PWR_INX_88E 0x10 + +#define EEPROM_ChannelPlan_88E 0xB8 +#define EEPROM_XTAL_88E 0xB9 +#define EEPROM_THERMAL_METER_88E 0xBA +#define EEPROM_IQK_LCK_88E 0xBB + +#define EEPROM_RF_BOARD_OPTION_88E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 +#define EEPROM_RF_BT_SETTING_88E 0xC3 +#define EEPROM_VERSION_88E 0xC4 +#define EEPROM_CustomID_88E 0xC5 +#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 +#define EEPROM_COUNTRY_CODE_88E 0xCB + +/* RTL88EE */ +#define EEPROM_MAC_ADDR_88EE 0xD0 +#define EEPROM_VID_88EE 0xD6 +#define EEPROM_DID_88EE 0xD8 +#define EEPROM_SVID_88EE 0xDA +#define EEPROM_SMID_88EE 0xDC + +/* RTL88EU */ +#define EEPROM_MAC_ADDR_88EU 0xD7 +#define EEPROM_VID_88EU 0xD0 +#define EEPROM_PID_88EU 0xD2 +#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 /* 8188EU, 8192EU, 8812AU is the same */ +#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104 + +/* RTL88ES */ +#define EEPROM_MAC_ADDR_88ES 0x11A +/* **************************************************** + * EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES + * **************************************************** */ +#define GET_PG_KFREE_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E 0x1F6 +#define PPG_THERMAL_OFFSET_8192E 0x1F5 + +/* 0x10 ~ 0x63 = TX power area. */ +#define EEPROM_TX_PWR_INX_8192E 0x10 + +#define EEPROM_ChannelPlan_8192E 0xB8 +#define EEPROM_XTAL_8192E 0xB9 +#define EEPROM_THERMAL_METER_8192E 0xBA +#define EEPROM_IQK_LCK_8192E 0xBB +#define EEPROM_2G_5G_PA_TYPE_8192E 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF + +#define EEPROM_RF_BOARD_OPTION_8192E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8192E 0xC2 +#define EEPROM_RF_BT_SETTING_8192E 0xC3 +#define EEPROM_VERSION_8192E 0xC4 +#define EEPROM_CustomID_8192E 0xC5 +#define EEPROM_TX_BBSWING_2G_8192E 0xC6 +#define EEPROM_TX_BBSWING_5G_8192E 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8192E 0xC9 +#define EEPROM_RFE_OPTION_8192E 0xCA +#define EEPROM_RFE_OPTION_8188E 0xCA +#define EEPROM_COUNTRY_CODE_8192E 0xCB + +/* RTL8192EE */ +#define EEPROM_MAC_ADDR_8192EE 0xD0 +#define EEPROM_VID_8192EE 0xD6 +#define EEPROM_DID_8192EE 0xD8 +#define EEPROM_SVID_8192EE 0xDA +#define EEPROM_SMID_8192EE 0xDC + +/* RTL8192EU */ +#define EEPROM_MAC_ADDR_8192EU 0xD7 +#define EEPROM_VID_8192EU 0xD0 +#define EEPROM_PID_8192EU 0xD2 +#define EEPROM_PA_TYPE_8192EU 0xBC +#define EEPROM_LNA_TYPE_2G_8192EU 0xBD +#define EEPROM_LNA_TYPE_5G_8192EU 0xBF + +/* RTL8192ES */ +#define EEPROM_MAC_ADDR_8192ES 0x11A +/* **************************************************** + * EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS + * **************************************************** + * 0x10 ~ 0x63 = TX power area. */ +#define EEPROM_USB_MODE_8812 0x08 +#define EEPROM_TX_PWR_INX_8812 0x10 + +#define EEPROM_ChannelPlan_8812 0xB8 +#define EEPROM_XTAL_8812 0xB9 +#define EEPROM_THERMAL_METER_8812 0xBA +#define EEPROM_IQK_LCK_8812 0xBB +#define EEPROM_2G_5G_PA_TYPE_8812 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812 0xBF + +#define EEPROM_RF_BOARD_OPTION_8812 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8812 0xC2 +#define EEPROM_RF_BT_SETTING_8812 0xC3 +#define EEPROM_VERSION_8812 0xC4 +#define EEPROM_CustomID_8812 0xC5 +#define EEPROM_TX_BBSWING_2G_8812 0xC6 +#define EEPROM_TX_BBSWING_5G_8812 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8812 0xC9 +#define EEPROM_RFE_OPTION_8812 0xCA +#define EEPROM_COUNTRY_CODE_8812 0xCB + +/* RTL8812AE */ +#define EEPROM_MAC_ADDR_8812AE 0xD0 +#define EEPROM_VID_8812AE 0xD6 +#define EEPROM_DID_8812AE 0xD8 +#define EEPROM_SVID_8812AE 0xDA +#define EEPROM_SMID_8812AE 0xDC + +/* RTL8812AU */ +#define EEPROM_MAC_ADDR_8812AU 0xD7 +#define EEPROM_VID_8812AU 0xD0 +#define EEPROM_PID_8812AU 0xD2 +#define EEPROM_PA_TYPE_8812AU 0xBC +#define EEPROM_LNA_TYPE_2G_8812AU 0xBD +#define EEPROM_LNA_TYPE_5G_8812AU 0xBF + +/* RTL8814AU */ +#define EEPROM_MAC_ADDR_8814AU 0xD8 +#define EEPROM_VID_8814AU 0xD0 +#define EEPROM_PID_8814AU 0xD2 +#define EEPROM_PA_TYPE_8814AU 0xBC +#define EEPROM_LNA_TYPE_2G_8814AU 0xBD +#define EEPROM_LNA_TYPE_5G_8814AU 0xBF + +/* RTL8814AE */ +#define EEPROM_MAC_ADDR_8814AE 0xD0 +#define EEPROM_VID_8814AE 0xD6 +#define EEPROM_DID_8814AE 0xD8 +#define EEPROM_SVID_8814AE 0xDA +#define EEPROM_SMID_8814AE 0xDC + +/* **************************************************** + * EEPROM/Efuse PG Offset for 8814AU + * **************************************************** */ +#define GET_PG_KFREE_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) +#define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2) + +#define KFREE_GAIN_DATA_LENGTH_8814A 22 + +#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A 0x3EE + +#define PPG_THERMAL_OFFSET_8814A 0x3EF + +#define EEPROM_TX_PWR_INX_8814 0x10 +#define EEPROM_USB_MODE_8814A 0x0E +#define EEPROM_ChannelPlan_8814 0xB8 +#define EEPROM_XTAL_8814 0xB9 +#define EEPROM_THERMAL_METER_8814 0xBA +#define EEPROM_IQK_LCK_8814 0xBB + +#define EEPROM_PA_TYPE_8814 0xBC +#define EEPROM_LNA_TYPE_AB_2G_8814 0xBD +#define EEPROM_LNA_TYPE_CD_2G_8814 0xBE +#define EEPROM_LNA_TYPE_AB_5G_8814 0xBF +#define EEPROM_LNA_TYPE_CD_5G_8814 0xC0 +#define EEPROM_RF_BOARD_OPTION_8814 0xC1 +#define EEPROM_RF_BT_SETTING_8814 0xC3 +#define EEPROM_VERSION_8814 0xC4 +#define EEPROM_CustomID_8814 0xC5 +#define EEPROM_TX_BBSWING_2G_8814 0xC6 +#define EEPROM_TX_BBSWING_5G_8814 0xC7 +#define EEPROM_TRX_ANTENNA_OPTION_8814 0xC9 +#define EEPROM_RFE_OPTION_8814 0xCA +#define EEPROM_COUNTRY_CODE_8814 0xCB + +/*Extra Info for 8814A Initial Gain Fine Tune suggested by Willis, JIRA: MP123*/ +#define EEPROM_IG_OFFSET_4_AB_2G_8814A 0x120 +#define EEPROM_IG_OFFSET_4_CD_2G_8814A 0x121 +#define EEPROM_IG_OFFSET_4_AB_5GL_8814A 0x122 +#define EEPROM_IG_OFFSET_4_CD_5GL_8814A 0x123 +#define EEPROM_IG_OFFSET_4_AB_5GM_8814A 0x124 +#define EEPROM_IG_OFFSET_4_CD_5GM_8814A 0x125 +#define EEPROM_IG_OFFSET_4_AB_5GH_8814A 0x126 +#define EEPROM_IG_OFFSET_4_CD_5GH_8814A 0x127 + +/* **************************************************** + * EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS + * **************************************************** */ + +#define GET_PG_KFREE_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A 0x1F6 +#define PPG_THERMAL_OFFSET_8821A 0x1F5 +#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A 0x1F4 +#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A 0x1F3 +#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A 0x1F2 +#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1 +#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0 + +#define EEPROM_TX_PWR_INX_8821 0x10 + +#define EEPROM_ChannelPlan_8821 0xB8 +#define EEPROM_XTAL_8821 0xB9 +#define EEPROM_THERMAL_METER_8821 0xBA +#define EEPROM_IQK_LCK_8821 0xBB + +#define EEPROM_RF_BOARD_OPTION_8821 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8821 0xC2 +#define EEPROM_RF_BT_SETTING_8821 0xC3 +#define EEPROM_VERSION_8821 0xC4 +#define EEPROM_CustomID_8821 0xC5 +#define EEPROM_RF_ANTENNA_OPT_8821 0xC9 + +/* RTL8821AE */ +#define EEPROM_MAC_ADDR_8821AE 0xD0 +#define EEPROM_VID_8821AE 0xD6 +#define EEPROM_DID_8821AE 0xD8 +#define EEPROM_SVID_8821AE 0xDA +#define EEPROM_SMID_8821AE 0xDC + +/* RTL8821AU */ +#define EEPROM_PA_TYPE_8821AU 0xBC +#define EEPROM_LNA_TYPE_8821AU 0xBF + +/* RTL8821AS */ +#define EEPROM_MAC_ADDR_8821AS 0x11A + +/* RTL8821AU */ +#define EEPROM_MAC_ADDR_8821AU 0x107 +#define EEPROM_VID_8821AU 0x100 +#define EEPROM_PID_8821AU 0x102 + +/* **************************************************** + * EEPROM/Efuse PG Offset for 8192 SE/SU + * **************************************************** */ +#define EEPROM_VID_92SE 0x0A +#define EEPROM_DID_92SE 0x0C +#define EEPROM_SVID_92SE 0x0E +#define EEPROM_SMID_92SE 0x10 + +#define EEPROM_MAC_ADDR_92S 0x12 + +#define EEPROM_TSSI_A_92SE 0x74 +#define EEPROM_TSSI_B_92SE 0x75 + +#define EEPROM_Version_92SE 0x7C + +#define EEPROM_VID_92SU 0x08 +#define EEPROM_PID_92SU 0x0A + +#define EEPROM_Version_92SU 0x50 +#define EEPROM_TSSI_A_92SU 0x6b +#define EEPROM_TSSI_B_92SU 0x6c + +/* ==================================================== + EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS + ==================================================== + */ + +#define GET_PG_KFREE_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE +#define PPG_THERMAL_OFFSET_8188F 0xEF + +/* 0x10 ~ 0x63 = TX power area. */ +#define EEPROM_TX_PWR_INX_8188F 0x10 + +#define EEPROM_ChannelPlan_8188F 0xB8 +#define EEPROM_XTAL_8188F 0xB9 +#define EEPROM_THERMAL_METER_8188F 0xBA +#define EEPROM_IQK_LCK_8188F 0xBB +#define EEPROM_2G_5G_PA_TYPE_8188F 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F 0xBF + +#define EEPROM_RF_BOARD_OPTION_8188F 0xC1 +#define EEPROM_FEATURE_OPTION_8188F 0xC2 +#define EEPROM_RF_BT_SETTING_8188F 0xC3 +#define EEPROM_VERSION_8188F 0xC4 +#define EEPROM_CustomID_8188F 0xC5 +#define EEPROM_TX_BBSWING_2G_8188F 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8188F 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8188F 0xC9 +#define EEPROM_RFE_OPTION_8188F 0xCA +#define EEPROM_COUNTRY_CODE_8188F 0xCB +#define EEPROM_CUSTOMER_ID_8188F 0x7F +#define EEPROM_SUBCUSTOMER_ID_8188F 0x59 + +/* RTL8188FU */ +#define EEPROM_MAC_ADDR_8188FU 0xD7 +#define EEPROM_VID_8188FU 0xD0 +#define EEPROM_PID_8188FU 0xD2 +#define EEPROM_PA_TYPE_8188FU 0xBC +#define EEPROM_LNA_TYPE_2G_8188FU 0xBD +#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4 + +/* RTL8188FS */ +#define EEPROM_MAC_ADDR_8188FS 0x11A +#define EEPROM_Voltage_ADDR_8188F 0x8 + +/* **************************************************** + * EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS + * **************************************************** + * 0x10 ~ 0x63 = TX power area. */ +#define EEPROM_TX_PWR_INX_8723B 0x10 + +#define EEPROM_ChannelPlan_8723B 0xB8 +#define EEPROM_XTAL_8723B 0xB9 +#define EEPROM_THERMAL_METER_8723B 0xBA +#define EEPROM_IQK_LCK_8723B 0xBB +#define EEPROM_2G_5G_PA_TYPE_8723B 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B 0xBF + +#define EEPROM_RF_BOARD_OPTION_8723B 0xC1 +#define EEPROM_FEATURE_OPTION_8723B 0xC2 +#define EEPROM_RF_BT_SETTING_8723B 0xC3 +#define EEPROM_VERSION_8723B 0xC4 +#define EEPROM_CustomID_8723B 0xC5 +#define EEPROM_TX_BBSWING_2G_8723B 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8723B 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8723B 0xC9 +#define EEPROM_RFE_OPTION_8723B 0xCA +#define EEPROM_COUNTRY_CODE_8723B 0xCB + +/* RTL8723BE */ +#define EEPROM_MAC_ADDR_8723BE 0xD0 +#define EEPROM_VID_8723BE 0xD6 +#define EEPROM_DID_8723BE 0xD8 +#define EEPROM_SVID_8723BE 0xDA +#define EEPROM_SMID_8723BE 0xDC + +/* RTL8723BU */ +#define EEPROM_MAC_ADDR_8723BU 0x107 +#define EEPROM_VID_8723BU 0x100 +#define EEPROM_PID_8723BU 0x102 +#define EEPROM_PA_TYPE_8723BU 0xBC +#define EEPROM_LNA_TYPE_2G_8723BU 0xBD + +/* RTL8723BS */ +#define EEPROM_MAC_ADDR_8723BS 0x11A +#define EEPROM_Voltage_ADDR_8723B 0x8 + +/* **************************************************** + * EEPROM/Efuse PG Offset for 8703B + * **************************************************** */ +#define GET_PG_KFREE_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B 0xEE +#define PPG_THERMAL_OFFSET_8703B 0xEF + +#define EEPROM_TX_PWR_INX_8703B 0x10 + +#define EEPROM_ChannelPlan_8703B 0xB8 +#define EEPROM_XTAL_8703B 0xB9 +#define EEPROM_THERMAL_METER_8703B 0xBA +#define EEPROM_IQK_LCK_8703B 0xBB +#define EEPROM_2G_5G_PA_TYPE_8703B 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B 0xBF + +#define EEPROM_RF_BOARD_OPTION_8703B 0xC1 +#define EEPROM_FEATURE_OPTION_8703B 0xC2 +#define EEPROM_RF_BT_SETTING_8703B 0xC3 +#define EEPROM_VERSION_8703B 0xC4 +#define EEPROM_CustomID_8703B 0xC5 +#define EEPROM_TX_BBSWING_2G_8703B 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8703B 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8703B 0xC9 +#define EEPROM_RFE_OPTION_8703B 0xCA +#define EEPROM_COUNTRY_CODE_8703B 0xCB + +/* RTL8703BU */ +#define EEPROM_MAC_ADDR_8703BU 0x107 +#define EEPROM_VID_8703BU 0x100 +#define EEPROM_PID_8703BU 0x102 +#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU 0x104 +#define EEPROM_PA_TYPE_8703BU 0xBC +#define EEPROM_LNA_TYPE_2G_8703BU 0xBD + +/* RTL8703BS */ +#define EEPROM_MAC_ADDR_8703BS 0x11A +#define EEPROM_Voltage_ADDR_8703B 0x8 + +/* + * ==================================================== + * EEPROM/Efuse PG Offset for 8822B + * ==================================================== + */ +#define EEPROM_TX_PWR_INX_8822B 0x10 + +#define EEPROM_ChannelPlan_8822B 0xB8 +#define EEPROM_XTAL_8822B 0xB9 +#define EEPROM_THERMAL_METER_8822B 0xBA +#define EEPROM_IQK_LCK_8822B 0xBB +#define EEPROM_2G_5G_PA_TYPE_8822B 0xBC +/* PATH A & PATH B */ +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBD +/* PATH C & PATH D */ +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8822B 0xBE +/* PATH A & PATH B */ +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822B 0xBF +/* PATH C & PATH D */ +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8822B 0xC0 + +#define EEPROM_RF_BOARD_OPTION_8822B 0xC1 +#define EEPROM_FEATURE_OPTION_8822B 0xC2 +#define EEPROM_RF_BT_SETTING_8822B 0xC3 +#define EEPROM_VERSION_8822B 0xC4 +#define EEPROM_CustomID_8822B 0xC5 +#define EEPROM_TX_BBSWING_2G_8822B 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8822B 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8822B 0xC9 +#define EEPROM_RFE_OPTION_8822B 0xCA +#define EEPROM_COUNTRY_CODE_8822B 0xCB + +/* RTL8822BU */ +#define EEPROM_MAC_ADDR_8822BU 0x107 +#define EEPROM_VID_8822BU 0x100 +#define EEPROM_PID_8822BU 0x102 +#define EEPROM_USB_OPTIONAL_FUNCTION0_8822BU 0x104 +#define EEPROM_USB_MODE_8822BU 0x06 + +/* RTL8822BS */ +#define EEPROM_MAC_ADDR_8822BS 0x11A + +/* RTL8822BE */ +#define EEPROM_MAC_ADDR_8822BE 0xD0 +/* + * ==================================================== + * EEPROM/Efuse PG Offset for 8821C + * ==================================================== + */ +#define EEPROM_TX_PWR_INX_8821C 0x10 + +#define EEPROM_CHANNEL_PLAN_8821C 0xB8 +#define EEPROM_XTAL_8821C 0xB9 +#define EEPROM_THERMAL_METER_8821C 0xBA +#define EEPROM_IQK_LCK_8821C 0xBB +#define EEPROM_2G_5G_PA_TYPE_8821C 0xBC +/* PATH A & PATH B */ +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8821C 0xBD +/* PATH C & PATH D */ +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_CD_8821C 0xBE +/* PATH A & PATH B */ +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8821C 0xBF +/* PATH C & PATH D */ +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_CD_8821C 0xC0 + +#define EEPROM_RF_BOARD_OPTION_8821C 0xC1 +#define EEPROM_FEATURE_OPTION_8821C 0xC2 +#define EEPROM_RF_BT_SETTING_8821C 0xC3 +#define EEPROM_VERSION_8821C 0xC4 +#define EEPROM_CUSTOMER_ID_8821C 0xC5 +#define EEPROM_TX_BBSWING_2G_8821C 0xC6 +#define EEPROM_TX_BBSWING_5G_8821C 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8821C 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8821C 0xC9 +#define EEPROM_RFE_OPTION_8821C 0xCA +#define EEPROM_COUNTRY_CODE_8821C 0xCB + +/* RTL8821CU */ +#define EEPROM_MAC_ADDR_8821CU 0x107 +#define EEPROM_VID_8821CU 0x100 +#define EEPROM_PID_8821CU 0x102 +#define EEPROM_USB_OPTIONAL_FUNCTION0_8821CU 0x104 +#define EEPROM_USB_MODE_8821CU 0x06 + +/* RTL8821CS */ +#define EEPROM_MAC_ADDR_8821CS 0x11A + +/* RTL8821CE */ +#define EEPROM_MAC_ADDR_8821CE 0xD0 +/* **************************************************** + * EEPROM/Efuse PG Offset for 8723D + * **************************************************** */ +#define GET_PG_KFREE_ON_8723D(_pg_m) \ + LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8723D(_pg_m) \ + LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_8723D_S1 0 +#define PPG_8723D_S0 1 + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8723D 0xEE +#define PPG_BB_GAIN_2G_TX_OFFSET_8723D 0x1EE +#define PPG_THERMAL_OFFSET_8723D 0xEF + +#define EEPROM_TX_PWR_INX_8723D 0x10 + +#define EEPROM_ChannelPlan_8723D 0xB8 +#define EEPROM_XTAL_8723D 0xB9 +#define EEPROM_THERMAL_METER_8723D 0xBA +#define EEPROM_IQK_LCK_8723D 0xBB +#define EEPROM_2G_5G_PA_TYPE_8723D 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723D 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723D 0xBF + +#define EEPROM_RF_BOARD_OPTION_8723D 0xC1 +#define EEPROM_FEATURE_OPTION_8723D 0xC2 +#define EEPROM_RF_BT_SETTING_8723D 0xC3 +#define EEPROM_VERSION_8723D 0xC4 +#define EEPROM_CustomID_8723D 0xC5 +#define EEPROM_TX_BBSWING_2G_8723D 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8723D 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8723D 0xC9 +#define EEPROM_RFE_OPTION_8723D 0xCA +#define EEPROM_COUNTRY_CODE_8723D 0xCB + +/* RTL8723DE */ +#define EEPROM_MAC_ADDR_8723DE 0xD0 +#define EEPROM_VID_8723DE 0xD6 +#define EEPROM_DID_8723DE 0xD8 +#define EEPROM_SVID_8723DE 0xDA +#define EEPROM_SMID_8723DE 0xDC + +/* RTL8723DU */ +#define EEPROM_MAC_ADDR_8723DU 0x107 +#define EEPROM_VID_8723DU 0x100 +#define EEPROM_PID_8723DU 0x102 +#define EEPROM_USB_OPTIONAL_FUNCTION0_8723DU 0x104 + +/* RTL8723BS */ +#define EEPROM_MAC_ADDR_8723DS 0x11A +#define EEPROM_Voltage_ADDR_8723D 0x8 + +/* **************************************************** + * EEPROM/Efuse Value Type + * **************************************************** */ +#define EETYPE_TX_PWR 0x0 +/* **************************************************** + * EEPROM/Efuse Default Value + * **************************************************** */ +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_DEFAULT_EXT 0xFF /* Reserved for Realtek */ +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_CCX 0x10 +#define EEPROM_CID_QMI 0x0D +#define EEPROM_CID_WHQL 0xFE + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB +#define EEPROM_CHANNEL_PLAN_CHIAN 0XC +#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD +#define EEPROM_CHANNEL_PLAN_KOREA 0xE +#define EEPROM_CHANNEL_PLAN_TURKEY 0xF +#define EEPROM_CHANNEL_PLAN_JAPAN 0x10 +#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11 +#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13 +#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14 + +#define EEPROM_USB_OPTIONAL1 0xE +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +#define RTL_EEPROM_ID 0x8129 +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_ThermalMeter 0x12 +#define EEPROM_Default_ThermalMeter_92SU 0x7 +#define EEPROM_Default_ThermalMeter_88E 0x18 +#define EEPROM_Default_ThermalMeter_8812 0x18 +#define EEPROM_Default_ThermalMeter_8192E 0x1A +#define EEPROM_Default_ThermalMeter_8723B 0x18 +#define EEPROM_Default_ThermalMeter_8703B 0x18 +#define EEPROM_Default_ThermalMeter_8723D 0x18 +#define EEPROM_Default_ThermalMeter_8188F 0x18 +#define EEPROM_Default_ThermalMeter_8814A 0x18 + +#define EEPROM_Default_CrystalCap 0x0 +#define EEPROM_Default_CrystalCap_8723A 0x20 +#define EEPROM_Default_CrystalCap_88E 0x20 +#define EEPROM_Default_CrystalCap_8812 0x20 +#define EEPROM_Default_CrystalCap_8814 0x20 +#define EEPROM_Default_CrystalCap_8192E 0x20 +#define EEPROM_Default_CrystalCap_8723B 0x20 +#define EEPROM_Default_CrystalCap_8703B 0x20 +#define EEPROM_Default_CrystalCap_8723D 0x20 +#define EEPROM_Default_CrystalCap_8188F 0x20 +#define EEPROM_Default_CrystalFreq 0x0 +#define EEPROM_Default_TxPowerLevel_92C 0x22 +#define EEPROM_Default_TxPowerLevel_2G 0x2C +#define EEPROM_Default_TxPowerLevel_5G 0x22 +#define EEPROM_Default_TxPowerLevel 0x22 +#define EEPROM_Default_HT40_2SDiff 0x0 +#define EEPROM_Default_HT20_Diff 2 +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4 +#define EEPROM_Default_HT40_PwrMaxOffset 0 +#define EEPROM_Default_HT20_PwrMaxOffset 0 + +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_CustomerID_8188E 0x00 +#define EEPROM_Default_SubCustomerID 0xCD +#define EEPROM_Default_Version 0 + +#define EEPROM_Default_externalPA_C9 0x00 +#define EEPROM_Default_externalPA_CC 0xFF +#define EEPROM_Default_internalPA_SP3T_C9 0xAA +#define EEPROM_Default_internalPA_SP3T_CC 0xAF +#define EEPROM_Default_internalPA_SPDT_C9 0xAA + #define EEPROM_Default_internalPA_SPDT_CC 0xA0 +#define EEPROM_Default_PAType 0 +#define EEPROM_Default_LNAType 0 + +/* New EFUSE default value */ +#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F +#define EEPROM_DEFAULT_BOARD_OPTION 0x00 +#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF +#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF +#define EEPROM_DEFAULT_RFE_OPTION 0x04 +#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 +#define EEPROM_DEFAULT_BT_OPTION 0x10 + +#define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00 + +/* PCIe related */ +#define EEPROM_PCIE_DEV_CAP_01 0xE0 /* Express device capability in PCIe configuration space, i.e., map to offset 0x74 */ +#define EEPROM_PCIE_DEV_CAP_02 0xE1 /* Express device capability in PCIe configuration space, i.e., map to offset 0x75 */ + +/* + * For VHT series TX power by rate table. + * VHT TX power by rate off setArray = + * Band:-2G&5G = 0 / 1 + * RF: at most 4*4 = ABCD=0/1/2/3 + * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 + * */ +#define TX_PWR_BY_RATE_NUM_BAND 2 +#define TX_PWR_BY_RATE_NUM_RF 4 +#define TX_PWR_BY_RATE_NUM_RATE 84 + +#define TXPWR_LMT_MAX_RF 4 + +/* ---------------------------------------------------------------------------- + * EEPROM/EFUSE data structure definition. + * ---------------------------------------------------------------------------- */ + +/* For 88E new structure */ + +/* +2.4G: +{ +{1,2}, +{3,4,5}, +{6,7,8}, +{9,10,11}, +{12,13}, +{14} +} + +5G: +{ +{36,38,40}, +{44,46,48}, +{52,54,56}, +{60,62,64}, +{100,102,104}, +{108,110,112}, +{116,118,120}, +{124,126,128}, +{132,134,136}, +{140,142,144}, +{149,151,153}, +{157,159,161}, +{173,175,177}, +} +*/ +#define MAX_RF_PATH 4 +#define RF_PATH_MAX MAX_RF_PATH +#define MAX_CHNL_GROUP_24G 6 +#define MAX_CHNL_GROUP_5G 14 + +/* It must always set to 4, otherwise read efuse table sequence will be wrong. */ +#define MAX_TX_COUNT 4 + +typedef struct _TxPowerInfo24G { + u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + /* If only one tx, only BW20 and OFDM are used. */ + s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +} TxPowerInfo24G, *PTxPowerInfo24G; + +typedef struct _TxPowerInfo5G { + u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; + /* If only one tx, only BW20, OFDM, BW80 and BW160 are used. */ + s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +} TxPowerInfo5G, *PTxPowerInfo5G; + +typedef enum _BT_Ant_NUM { + Ant_x2 = 0, + Ant_x1 = 1 +} BT_Ant_NUM, *PBT_Ant_NUM; + +typedef enum _BT_CoType { + BT_2WIRE = 0, + BT_ISSC_3WIRE = 1, + BT_ACCEL = 2, + BT_CSR_BC4 = 3, + BT_CSR_BC8 = 4, + BT_RTL8756 = 5, + BT_RTL8723A = 6, + BT_RTL8821 = 7, + BT_RTL8723B = 8, + BT_RTL8192E = 9, + BT_RTL8814A = 10, + BT_RTL8812A = 11, + BT_RTL8703B = 12, + BT_RTL8822B = 13, + BT_RTL8723D = 14, + BT_RTL8821C = 15 +} BT_CoType, *PBT_CoType; + +typedef enum _BT_RadioShared { + BT_Radio_Shared = 0, + BT_Radio_Individual = 1, +} BT_RadioShared, *PBT_RadioShared; + +#endif diff --git a/drivers/staging/rtl8821ce/include/hal_phy.h b/drivers/staging/rtl8821ce/include/hal_phy.h new file mode 100644 index 000000000000..35298a2d25e9 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_phy.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_PHY_H__ +#define __HAL_PHY_H__ + + #define HAL_FW_ENABLE 1 + #define HAL_MAC_ENABLE 1 + #define HAL_BB_ENABLE 1 + #define HAL_RF_ENABLE 1 + +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG_88E 0xFF +#define RF6052_MAX_REG_92C 0x7F + +#define RF6052_MAX_REG \ + ((RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C) + +#define GET_RF6052_REAL_MAX_REG(_Adapter) \ + (IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C) + +#define RF6052_MAX_PATH 2 + +/* + * Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected. + * Added by Roger, 2013.05.22. + * */ +#define ANT_DETECT_BY_SINGLE_TONE BIT0 +#define ANT_DETECT_BY_RSSI BIT1 +#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE) +#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI) + +/*--------------------------Define Parameters-------------------------------*/ +typedef enum _RF_TYPE { + RF_TYPE_MIN = 0, /* 0 */ + RF_8225 = 1, /* 1 11b/g RF for verification only */ + RF_8256 = 2, /* 2 11b/g/n */ + RF_8258 = 3, /* 3 11a/b/g/n RF */ + RF_6052 = 4, /* 4 11b/g/n RF */ + RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */ + RF_TYPE_MAX +} RF_TYPE_E, *PRF_TYPE_E; + +#define TX_1S 0 +#define TX_2S 1 +#define TX_3S 2 +#define TX_4S 3 + +typedef enum _ANTENNA_PATH { + ANTENNA_NONE = 0, + ANTENNA_D = 1, + ANTENNA_C = 2, + ANTENNA_CD = 3, + ANTENNA_B = 4, + ANTENNA_BD = 5, + ANTENNA_BC = 6, + ANTENNA_BCD = 7, + ANTENNA_A = 8, + ANTENNA_AD = 9, + ANTENNA_AC = 10, + ANTENNA_ACD = 11, + ANTENNA_AB = 12, + ANTENNA_ABD = 13, + ANTENNA_ABC = 14, + ANTENNA_ABCD = 15 +} ANTENNA_PATH; + +typedef enum _RF_CONTENT { + radioa_txt = 0x1000, + radiob_txt = 0x1001, + radioc_txt = 0x1002, + radiod_txt = 0x1003 +} RF_CONTENT; + +typedef enum _BaseBand_Config_Type { + BaseBand_Config_PHY_REG = 0, /* Radio Path A */ + BaseBand_Config_AGC_TAB = 1, /* Radio Path B */ + BaseBand_Config_AGC_TAB_2G = 2, + BaseBand_Config_AGC_TAB_5G = 3, + BaseBand_Config_PHY_REG_PG +} BaseBand_Config_Type, *PBaseBand_Config_Type; + +typedef enum _HW_BLOCK { + HW_BLOCK_MAC = 0, + HW_BLOCK_PHY0 = 1, + HW_BLOCK_PHY1 = 2, + HW_BLOCK_RF = 3, + HW_BLOCK_MAXIMUM = 4, /* Never use this */ +} HW_BLOCK_E, *PHW_BLOCK_E; + +typedef enum _WIRELESS_MODE { + WIRELESS_MODE_UNKNOWN = 0x00, + WIRELESS_MODE_A = 0x01, + WIRELESS_MODE_B = 0x02, + WIRELESS_MODE_G = 0x04, + WIRELESS_MODE_AUTO = 0x08, + WIRELESS_MODE_N_24G = 0x10, + WIRELESS_MODE_N_5G = 0x20, + WIRELESS_MODE_AC_5G = 0x40, + WIRELESS_MODE_AC_24G = 0x80, + WIRELESS_MODE_AC_ONLY = 0x100, +} WIRELESS_MODE; + +typedef enum _SwChnlCmdID { + CmdID_End, + CmdID_SetTxPowerLevel, + CmdID_BBRegWrite10, + CmdID_WritePortUlong, + CmdID_WritePortUshort, + CmdID_WritePortUchar, + CmdID_RF_WriteReg, +} SwChnlCmdID; + +typedef struct _SwChnlCmd { + SwChnlCmdID CmdID; + u32 Para1; + u32 Para2; + u32 msDelay; +} SwChnlCmd; + +typedef struct _R_ANTENNA_SELECT_OFDM { + u32 r_tx_antenna:4; + u32 r_ant_l:4; + u32 r_ant_non_ht:4; + u32 r_ant_ht1:4; + u32 r_ant_ht2:4; + u32 r_ant_ht_s1:4; + u32 r_ant_non_ht_s1:4; + u32 OFDM_TXSC:2; + u32 Reserved:2; +} R_ANTENNA_SELECT_OFDM; + +typedef struct _R_ANTENNA_SELECT_CCK { + u8 r_cckrx_enable_2:2; + u8 r_cckrx_enable:2; + u8 r_ccktx_enable:4; +} R_ANTENNA_SELECT_CCK; + +typedef struct RF_Shadow_Compare_Map { + /* Shadow register value */ + u32 Value; + /* Compare or not flag */ + u8 Compare; + /* Record If it had ever modified unpredicted */ + u8 ErrorOrNot; + /* Recorver Flag */ + u8 Recorver; + /* */ + u8 Driver_Write; +} RF_SHADOW_T; + +/*--------------------------Exported Function prototype---------------------*/ + +u32 +PHY_CalculateBitShift( + u32 BitMask +); + +u32 +PHY_RFShadowRead( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset); + +VOID +PHY_RFShadowWrite( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u32 Data); + +BOOLEAN +PHY_RFShadowCompare( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset); + +VOID +PHY_RFShadowRecorver( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset); + +VOID +PHY_RFShadowCompareAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRecorverAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowCompareFlagSet( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u8 Type); + +VOID +PHY_RFShadowRecorverFlagSet( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u8 Type); + +VOID +PHY_RFShadowCompareFlagSetAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRecorverFlagSetAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRefresh( + IN PADAPTER Adapter); + +#endif /* __HAL_COMMON_H__ */ diff --git a/drivers/staging/rtl8821ce/include/hal_phy_reg.h b/drivers/staging/rtl8821ce/include/hal_phy_reg.h new file mode 100644 index 000000000000..c2cfbed0dffb --- /dev/null +++ b/drivers/staging/rtl8821ce/include/hal_phy_reg.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_PHY_REG_H__ +#define __HAL_PHY_REG_H__ + +/* for PutRFRegsetting & GetRFRegSetting BitMask + * #if (RTL92SE_FPGA_VERIFY == 1) + * #define bRFRegOffsetMask 0xfff + * #else */ +#define bRFRegOffsetMask 0xfffff +/* #endif */ + +#endif /* __HAL_PHY_REG_H__ */ diff --git a/drivers/staging/rtl8821ce/include/ieee80211.h b/drivers/staging/rtl8821ce/include/ieee80211.h new file mode 100644 index 000000000000..f46a42b6157e --- /dev/null +++ b/drivers/staging/rtl8821ce/include/ieee80211.h @@ -0,0 +1,1618 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __IEEE80211_H +#define __IEEE80211_H + +#define MGMT_QUEUE_NUM 5 + +#define ETH_ALEN 6 +#define ETH_TYPE_LEN 2 +#define PAYLOAD_TYPE_LEN 1 + +#define NET80211_TU_TO_US 1024 /* unit:us */ +#define DEFAULT_BCN_INTERVAL 100 /* 100 ms */ + + +#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) + +/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ +enum { + RTL871X_HOSTAPD_FLUSH = 1, + RTL871X_HOSTAPD_ADD_STA = 2, + RTL871X_HOSTAPD_REMOVE_STA = 3, + RTL871X_HOSTAPD_GET_INFO_STA = 4, + /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */ + RTL871X_HOSTAPD_GET_WPAIE_STA = 5, + RTL871X_SET_ENCRYPTION = 6, + RTL871X_GET_ENCRYPTION = 7, + RTL871X_HOSTAPD_SET_FLAGS_STA = 8, + RTL871X_HOSTAPD_GET_RID = 9, + RTL871X_HOSTAPD_SET_RID = 10, + RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11, + RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12, + RTL871X_HOSTAPD_MLME = 13, + RTL871X_HOSTAPD_SCAN_REQ = 14, + RTL871X_HOSTAPD_STA_CLEAR_STATS = 15, + RTL871X_HOSTAPD_SET_BEACON = 16, + RTL871X_HOSTAPD_SET_WPS_BEACON = 17, + RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18, + RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19, + RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20, + RTL871X_HOSTAPD_SET_MACADDR_ACL = 21, + RTL871X_HOSTAPD_ACL_ADD_STA = 22, + RTL871X_HOSTAPD_ACL_REMOVE_STA = 23, +}; + +/* STA flags */ +#define WLAN_STA_AUTH BIT(0) +#define WLAN_STA_ASSOC BIT(1) +#define WLAN_STA_PS BIT(2) +#define WLAN_STA_TIM BIT(3) +#define WLAN_STA_PERM BIT(4) +#define WLAN_STA_AUTHORIZED BIT(5) +#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ +#define WLAN_STA_SHORT_PREAMBLE BIT(7) +#define WLAN_STA_PREAUTH BIT(8) +#define WLAN_STA_WME BIT(9) +#define WLAN_STA_MFP BIT(10) +#define WLAN_STA_HT BIT(11) +#define WLAN_STA_WPS BIT(12) +#define WLAN_STA_MAYBE_WPS BIT(13) +#define WLAN_STA_VHT BIT(14) +#define WLAN_STA_NONERP BIT(31) + + +#define IEEE_CMD_SET_WPA_PARAM 1 +#define IEEE_CMD_SET_WPA_IE 2 +#define IEEE_CMD_SET_ENCRYPTION 3 +#define IEEE_CMD_MLME 4 + +#define IEEE_PARAM_WPA_ENABLED 1 +#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 +#define IEEE_PARAM_DROP_UNENCRYPTED 3 +#define IEEE_PARAM_PRIVACY_INVOKED 4 +#define IEEE_PARAM_AUTH_ALGS 5 +#define IEEE_PARAM_IEEE_802_1X 6 +#define IEEE_PARAM_WPAX_SELECT 7 + +#define AUTH_ALG_OPEN_SYSTEM 0x1 +#define AUTH_ALG_SHARED_KEY 0x2 +#define AUTH_ALG_LEAP 0x00000004 + +#define IEEE_MLME_STA_DEAUTH 1 +#define IEEE_MLME_STA_DISASSOC 2 + +#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 +#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 +#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 +#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 +#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 +#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 + +#define IEEE_CRYPT_ALG_NAME_LEN 16 + +#define WPA_CIPHER_NONE BIT(0) +#define WPA_CIPHER_WEP40 BIT(1) +#define WPA_CIPHER_WEP104 BIT(2) +#define WPA_CIPHER_TKIP BIT(3) +#define WPA_CIPHER_CCMP BIT(4) + +#define WPA_SELECTOR_LEN 4 +extern u8 RTW_WPA_OUI_TYPE[] ; +extern u16 RTW_WPA_VERSION ; +extern u8 WPA_AUTH_KEY_MGMT_NONE[]; +extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +extern u8 WPA_CIPHER_SUITE_NONE[]; +extern u8 WPA_CIPHER_SUITE_WEP40[]; +extern u8 WPA_CIPHER_SUITE_TKIP[]; +extern u8 WPA_CIPHER_SUITE_WRAP[]; +extern u8 WPA_CIPHER_SUITE_CCMP[]; +extern u8 WPA_CIPHER_SUITE_WEP104[]; + +#define RSN_HEADER_LEN 4 +#define RSN_SELECTOR_LEN 4 + +extern u16 RSN_VERSION_BSD; +extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +extern u8 RSN_CIPHER_SUITE_NONE[]; +extern u8 RSN_CIPHER_SUITE_WEP40[]; +extern u8 RSN_CIPHER_SUITE_TKIP[]; +extern u8 RSN_CIPHER_SUITE_WRAP[]; +extern u8 RSN_CIPHER_SUITE_CCMP[]; +extern u8 RSN_CIPHER_SUITE_WEP104[]; + +typedef enum _RATEID_IDX_ { + RATEID_IDX_BGN_40M_2SS = 0, + RATEID_IDX_BGN_40M_1SS = 1, + RATEID_IDX_BGN_20M_2SS_BN = 2, + RATEID_IDX_BGN_20M_1SS_BN = 3, + RATEID_IDX_GN_N2SS = 4, + RATEID_IDX_GN_N1SS = 5, + RATEID_IDX_BG = 6, + RATEID_IDX_G = 7, + RATEID_IDX_B = 8, + RATEID_IDX_VHT_2SS = 9, + RATEID_IDX_VHT_1SS = 10, + RATEID_IDX_MIX1 = 11, + RATEID_IDX_MIX2 = 12, + RATEID_IDX_VHT_3SS = 13, + RATEID_IDX_BGN_3SS = 14, +} RATEID_IDX, *PRATEID_IDX; + +typedef enum _RATR_TABLE_MODE { + RATR_INX_WIRELESS_NGB = 0, /* BGN 40 Mhz 2SS 1SS */ + RATR_INX_WIRELESS_NG = 1, /* GN or N */ + RATR_INX_WIRELESS_NB = 2, /* BGN 20 Mhz 2SS 1SS or BN */ + RATR_INX_WIRELESS_N = 3, + RATR_INX_WIRELESS_GB = 4, + RATR_INX_WIRELESS_G = 5, + RATR_INX_WIRELESS_B = 6, + RATR_INX_WIRELESS_MC = 7, + RATR_INX_WIRELESS_AC_N = 8, +} RATR_TABLE_MODE, *PRATR_TABLE_MODE; + +enum NETWORK_TYPE { + WIRELESS_INVALID = 0, + /* Sub-Element */ + WIRELESS_11B = BIT(0), /* tx: cck only , rx: cck only, hw: cck */ + WIRELESS_11G = BIT(1), /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */ + WIRELESS_11A = BIT(2), /* tx: ofdm only, rx: ofdm only, hw: ofdm only */ + WIRELESS_11_24N = BIT(3), /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */ + WIRELESS_11_5N = BIT(4), /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */ + WIRELESS_AUTO = BIT(5), + WIRELESS_11AC = BIT(6), + + /* Combination */ + /* Type for current wireless mode */ + WIRELESS_11BG = (WIRELESS_11B | WIRELESS_11G), /* tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm */ + WIRELESS_11G_24N = (WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm */ + WIRELESS_11A_5N = (WIRELESS_11A | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ + WIRELESS_11B_24N = (WIRELESS_11B | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ + WIRELESS_11BG_24N = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), /* tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck */ + WIRELESS_11_24AC = (WIRELESS_11G | WIRELESS_11AC), + WIRELESS_11_5AC = (WIRELESS_11A | WIRELESS_11AC), + + /* Type for registry default wireless mode */ + WIRELESS_11AGN = (WIRELESS_11A | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */ + WIRELESS_11ABGN = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N), + WIRELESS_MODE_24G = (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N), + WIRELESS_MODE_5G = (WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC), + WIRELESS_MODE_MAX = (WIRELESS_11A | WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N | WIRELESS_11_5N | WIRELESS_11AC), +}; + +#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G +#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G + +#define IsLegacyOnly(NetType) ((NetType) == ((NetType) & (WIRELESS_11BG | WIRELESS_11A))) + +#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) +#define is_supported_5g(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) + +#define IsEnableHWCCK(NetType) IsSupported24G(NetType) +#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11_24N | SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) + +#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) +#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) +#define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType) + +#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) +#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G | WIRELESS_11A) ? _TRUE : _FALSE) +#define is_supported_ht(NetType) ((NetType) & (WIRELESS_11_24N | WIRELESS_11_5N) ? _TRUE : _FALSE) + +#define is_supported_vht(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE) + +typedef struct ieee_param { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + union { + struct { + u8 name; + u32 value; + } wpa_param; + struct { + u32 len; + u8 reserved[32]; + u8 data[0]; + } wpa_ie; + struct { + int command; + int reason_code; + } mlme; + struct { + u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; + u8 set_tx; + u32 err; + u8 idx; + u8 seq[8]; /* sequence counter (set: RX, get: TX) */ + u16 key_len; + u8 key[0]; + } crypt; + struct { + u16 aid; + u16 capability; + int flags; + u8 tx_supp_rates[16]; + struct rtw_ieee80211_ht_cap ht_cap; + } add_sta; + struct { + u8 reserved[2];/* for set max_num_sta */ + u8 buf[0]; + } bcn_ie; + + } u; +} ieee_param; + +typedef struct ieee_param_ex { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + u8 data[0]; +} ieee_param_ex; + +struct sta_data { + u16 aid; + u16 capability; + int flags; + u32 sta_set; + u8 tx_supp_rates[16]; + u32 tx_supp_rates_len; + struct rtw_ieee80211_ht_cap ht_cap; + u64 rx_pkts; + u64 rx_bytes; + u64 rx_drops; + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; +}; + + +#define IEEE80211_DATA_LEN 2304 +/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section + 6.2.1.1.2. + + The figure in section 7.1.2 suggests a body size of up to 2312 + bytes is allowed, which is a bit confusing, I suspect this + represents the 2304 bytes of real data, plus a possible 8 bytes of + WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ + +#define IEEE80211_HLEN 30 +#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) + +/* this is stolen from ipw2200 driver */ +#define IEEE_IBSS_MAC_HASH_SIZE 31 + +struct ieee_ibss_seq { + u8 mac[ETH_ALEN]; + u16 seq_num; + u16 frag_num; + unsigned long packet_time; + _list list; +}; + + +struct rtw_ieee80211_hdr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; +} __attribute__((packed)); + +struct rtw_ieee80211_hdr_3addr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; +} __attribute__((packed)); + +struct rtw_ieee80211_hdr_qos { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; + u16 qc; +} __attribute__((packed)); + +struct rtw_ieee80211_hdr_3addr_qos { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u16 qc; +} __attribute__((packed)); + +struct eapol { + u8 snap[6]; + u16 ethertype; + u8 version; + u8 type; + u16 length; +} __attribute__((packed)); + + +enum eap_type { + EAP_PACKET = 0, + EAPOL_START, + EAPOL_LOGOFF, + EAPOL_KEY, + EAPOL_ENCAP_ASF_ALERT +}; + +#define IEEE80211_3ADDR_LEN 24 +#define IEEE80211_4ADDR_LEN 30 +#define IEEE80211_FCS_LEN 4 + +#define MIN_FRAG_THRESHOLD 256U +#define MAX_FRAG_THRESHOLD 2346U + +/* Frame control field constants */ +#define RTW_IEEE80211_FCTL_VERS 0x0003 +#define RTW_IEEE80211_FCTL_FTYPE 0x000c +#define RTW_IEEE80211_FCTL_STYPE 0x00f0 +#define RTW_IEEE80211_FCTL_TODS 0x0100 +#define RTW_IEEE80211_FCTL_FROMDS 0x0200 +#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 +#define RTW_IEEE80211_FCTL_RETRY 0x0800 +#define RTW_IEEE80211_FCTL_PM 0x1000 +#define RTW_IEEE80211_FCTL_MOREDATA 0x2000 +#define RTW_IEEE80211_FCTL_PROTECTED 0x4000 +#define RTW_IEEE80211_FCTL_ORDER 0x8000 +#define RTW_IEEE80211_FCTL_CTL_EXT 0x0f00 + +#define RTW_IEEE80211_FTYPE_MGMT 0x0000 +#define RTW_IEEE80211_FTYPE_CTL 0x0004 +#define RTW_IEEE80211_FTYPE_DATA 0x0008 +#define RTW_IEEE80211_FTYPE_EXT 0x000c + +/* management */ +#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000 +#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010 +#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020 +#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 +#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 +#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 +#define RTW_IEEE80211_STYPE_BEACON 0x0080 +#define RTW_IEEE80211_STYPE_ATIM 0x0090 +#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 +#define RTW_IEEE80211_STYPE_AUTH 0x00B0 +#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 +#define RTW_IEEE80211_STYPE_ACTION 0x00D0 + +/* control */ +#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060 +#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080 +#define RTW_IEEE80211_STYPE_BACK 0x0090 +#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 +#define RTW_IEEE80211_STYPE_RTS 0x00B0 +#define RTW_IEEE80211_STYPE_CTS 0x00C0 +#define RTW_IEEE80211_STYPE_ACK 0x00D0 +#define RTW_IEEE80211_STYPE_CFEND 0x00E0 +#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 + +/* data */ +#define RTW_IEEE80211_STYPE_DATA 0x0000 +#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 +#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 +#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 +#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 +#define RTW_IEEE80211_STYPE_CFACK 0x0050 +#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 +#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 +#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0 +#define RTW_IEEE80211_STYPE_QOS_NULLFUNC 0x00C0 +#define RTW_IEEE80211_STYPE_QOS_CFACK 0x00D0 +#define RTW_IEEE80211_STYPE_QOS_CFPOLL 0x00E0 +#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL 0x00F0 + +/* sequence control field */ +#define RTW_IEEE80211_SCTL_FRAG 0x000F +#define RTW_IEEE80211_SCTL_SEQ 0xFFF0 + +#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) +#define RTW_ERP_INFO_USE_PROTECTION BIT(1) +#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) + +/* QoS,QOS */ +#define NORMAL_ACK 0 +#define NO_ACK 1 +#define NON_EXPLICIT_ACK 2 +#define BLOCK_ACK 3 + +#ifndef ETH_P_PAE + #define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#endif /* ETH_P_PAE */ + +#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ + +#define ETH_P_ECONET 0x0018 + +#ifndef ETH_P_80211_RAW + #define ETH_P_80211_RAW (ETH_P_ECONET + 1) +#endif + +/* IEEE 802.11 defines */ + +#define P80211_OUI_LEN 3 + + +struct ieee80211_snap_hdr { + + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ + +} __attribute__((packed)); + + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE) +#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE) + +#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) + +#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) +#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ) + +/* Authentication algorithms */ +#define WLAN_AUTH_OPEN 0 +#define WLAN_AUTH_SHARED_KEY 1 + +#define WLAN_AUTH_CHALLENGE_LEN 128 + +#define WLAN_CAPABILITY_BSS (1<<0) +#define WLAN_CAPABILITY_IBSS (1<<1) +#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) +#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) +#define WLAN_CAPABILITY_PRIVACY (1<<4) +#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) +#define WLAN_CAPABILITY_PBCC (1<<6) +#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) +#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) + +/* Status codes */ +#define WLAN_STATUS_SUCCESS 0 +#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 +#define WLAN_STATUS_CAPS_UNSUPPORTED 10 +#define WLAN_STATUS_REASSOC_NO_ASSOC 11 +#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 +#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 +#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 +#define WLAN_STATUS_CHALLENGE_FAIL 15 +#define WLAN_STATUS_AUTH_TIMEOUT 16 +#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 +#define WLAN_STATUS_ASSOC_DENIED_RATES 18 +/* 802.11b */ +#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 +#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 +#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 + +/* Reason codes */ +#define WLAN_REASON_UNSPECIFIED 1 +#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 +#define WLAN_REASON_DEAUTH_LEAVING 3 +#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 +#define WLAN_REASON_DISASSOC_AP_BUSY 5 +#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 +#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 +#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 +#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#define WLAN_REASON_ACTIVE_ROAM 65533 +#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 +#define WLAN_REASON_EXPIRATION_CHK 65535 + +/* Information Element IDs */ +#define WLAN_EID_SSID 0 +#define WLAN_EID_SUPP_RATES 1 +#define WLAN_EID_FH_PARAMS 2 +#define WLAN_EID_DS_PARAMS 3 +#define WLAN_EID_CF_PARAMS 4 +#define WLAN_EID_TIM 5 +#define WLAN_EID_IBSS_PARAMS 6 +#define WLAN_EID_CHALLENGE 16 +/* EIDs defined by IEEE 802.11h - START */ +#define WLAN_EID_PWR_CONSTRAINT 32 +#define WLAN_EID_PWR_CAPABILITY 33 +#define WLAN_EID_TPC_REQUEST 34 +#define WLAN_EID_TPC_REPORT 35 +#define WLAN_EID_SUPPORTED_CHANNELS 36 +#define WLAN_EID_CHANNEL_SWITCH 37 +#define WLAN_EID_MEASURE_REQUEST 38 +#define WLAN_EID_MEASURE_REPORT 39 +#define WLAN_EID_QUITE 40 +#define WLAN_EID_IBSS_DFS 41 +/* EIDs defined by IEEE 802.11h - END */ +#define WLAN_EID_ERP_INFO 42 +#define WLAN_EID_HT_CAP 45 +#define WLAN_EID_RSN 48 +#define WLAN_EID_EXT_SUPP_RATES 50 +#define WLAN_EID_MOBILITY_DOMAIN 54 +#define WLAN_EID_FAST_BSS_TRANSITION 55 +#define WLAN_EID_TIMEOUT_INTERVAL 56 +#define WLAN_EID_RIC_DATA 57 +#define WLAN_EID_HT_OPERATION 61 +#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62 +#define WLAN_EID_20_40_BSS_COEXISTENCE 72 +#define WLAN_EID_20_40_BSS_INTOLERANT 73 +#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 +#define WLAN_EID_MMIE 76 +#define WLAN_EID_VENDOR_SPECIFIC 221 +#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) +#define WLAN_EID_VHT_CAPABILITY 191 +#define WLAN_EID_VHT_OPERATION 192 +#define WLAN_EID_VHT_OP_MODE_NOTIFY 199 + +#define IEEE80211_MGMT_HDR_LEN 24 +#define IEEE80211_DATA_HDR3_LEN 24 +#define IEEE80211_DATA_HDR4_LEN 30 + +#define IEEE80211_STATMASK_SIGNAL (1<<0) +#define IEEE80211_STATMASK_RSSI (1<<1) +#define IEEE80211_STATMASK_NOISE (1<<2) +#define IEEE80211_STATMASK_RATE (1<<3) +#define IEEE80211_STATMASK_WEMASK 0x7 + +#define IEEE80211_CCK_MODULATION (1<<0) +#define IEEE80211_OFDM_MODULATION (1<<1) + +#define IEEE80211_24GHZ_BAND (1<<0) +#define IEEE80211_52GHZ_BAND (1<<1) + +#define IEEE80211_CCK_RATE_LEN 4 +#define IEEE80211_NUM_OFDM_RATESLEN 8 + +#define IEEE80211_CCK_RATE_1MB 0x02 +#define IEEE80211_CCK_RATE_2MB 0x04 +#define IEEE80211_CCK_RATE_5MB 0x0B +#define IEEE80211_CCK_RATE_11MB 0x16 +#define IEEE80211_OFDM_RATE_LEN 8 +#define IEEE80211_OFDM_RATE_6MB 0x0C +#define IEEE80211_OFDM_RATE_9MB 0x12 +#define IEEE80211_OFDM_RATE_12MB 0x18 +#define IEEE80211_OFDM_RATE_18MB 0x24 +#define IEEE80211_OFDM_RATE_24MB 0x30 +#define IEEE80211_OFDM_RATE_36MB 0x48 +#define IEEE80211_OFDM_RATE_48MB 0x60 +#define IEEE80211_OFDM_RATE_54MB 0x6C +#define IEEE80211_BASIC_RATE_MASK 0x80 + +#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) +#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) +#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) +#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) +#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) +#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) +#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) +#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) +#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) +#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) +#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) +#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) + +#define IEEE80211_CCK_RATES_MASK 0x0000000F +#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ + IEEE80211_CCK_RATE_2MB_MASK) +#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ + IEEE80211_CCK_RATE_5MB_MASK | \ + IEEE80211_CCK_RATE_11MB_MASK) + +#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 +#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ + IEEE80211_OFDM_RATE_12MB_MASK | \ + IEEE80211_OFDM_RATE_24MB_MASK) +#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ + IEEE80211_OFDM_RATE_9MB_MASK | \ + IEEE80211_OFDM_RATE_18MB_MASK | \ + IEEE80211_OFDM_RATE_36MB_MASK | \ + IEEE80211_OFDM_RATE_48MB_MASK | \ + IEEE80211_OFDM_RATE_54MB_MASK) +#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ + IEEE80211_CCK_DEFAULT_RATES_MASK) + +#define IEEE80211_NUM_OFDM_RATES 8 +#define IEEE80211_NUM_CCK_RATES 4 +#define IEEE80211_OFDM_SHIFT_MASK_A 4 + +enum MGN_RATE { + MGN_1M = 0x02, + MGN_2M = 0x04, + MGN_5_5M = 0x0B, + MGN_6M = 0x0C, + MGN_9M = 0x12, + MGN_11M = 0x16, + MGN_12M = 0x18, + MGN_18M = 0x24, + MGN_24M = 0x30, + MGN_36M = 0x48, + MGN_48M = 0x60, + MGN_54M = 0x6C, + MGN_MCS32 = 0x7F, + MGN_MCS0, + MGN_MCS1, + MGN_MCS2, + MGN_MCS3, + MGN_MCS4, + MGN_MCS5, + MGN_MCS6, + MGN_MCS7, + MGN_MCS8, + MGN_MCS9, + MGN_MCS10, + MGN_MCS11, + MGN_MCS12, + MGN_MCS13, + MGN_MCS14, + MGN_MCS15, + MGN_MCS16, + MGN_MCS17, + MGN_MCS18, + MGN_MCS19, + MGN_MCS20, + MGN_MCS21, + MGN_MCS22, + MGN_MCS23, + MGN_MCS24, + MGN_MCS25, + MGN_MCS26, + MGN_MCS27, + MGN_MCS28, + MGN_MCS29, + MGN_MCS30, + MGN_MCS31, + MGN_VHT1SS_MCS0, + MGN_VHT1SS_MCS1, + MGN_VHT1SS_MCS2, + MGN_VHT1SS_MCS3, + MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, + MGN_VHT1SS_MCS6, + MGN_VHT1SS_MCS7, + MGN_VHT1SS_MCS8, + MGN_VHT1SS_MCS9, + MGN_VHT2SS_MCS0, + MGN_VHT2SS_MCS1, + MGN_VHT2SS_MCS2, + MGN_VHT2SS_MCS3, + MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, + MGN_VHT2SS_MCS6, + MGN_VHT2SS_MCS7, + MGN_VHT2SS_MCS8, + MGN_VHT2SS_MCS9, + MGN_VHT3SS_MCS0, + MGN_VHT3SS_MCS1, + MGN_VHT3SS_MCS2, + MGN_VHT3SS_MCS3, + MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, + MGN_VHT3SS_MCS6, + MGN_VHT3SS_MCS7, + MGN_VHT3SS_MCS8, + MGN_VHT3SS_MCS9, + MGN_VHT4SS_MCS0, + MGN_VHT4SS_MCS1, + MGN_VHT4SS_MCS2, + MGN_VHT4SS_MCS3, + MGN_VHT4SS_MCS4, + MGN_VHT4SS_MCS5, + MGN_VHT4SS_MCS6, + MGN_VHT4SS_MCS7, + MGN_VHT4SS_MCS8, + MGN_VHT4SS_MCS9, + MGN_UNKNOWN +}; + +#define IS_HT_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31) +#define IS_VHT_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9) +#define IS_CCK_RATE(_rate) ((_rate) == MGN_1M || (_rate) == MGN_2M || (_rate) == MGN_5_5M || (_rate) == MGN_11M) +#define IS_OFDM_RATE(_rate) ((_rate) >= MGN_6M && (_rate) <= MGN_54M && (_rate) != MGN_11M) + +#define IS_HT1SS_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS7) +#define IS_HT2SS_RATE(_rate) ((_rate) >= MGN_MCS8 && (_rate) <= MGN_MCS15) +#define IS_HT3SS_RATE(_rate) ((_rate) >= MGN_MCS16 && (_rate) <= MGN_MCS23) +#define IS_HT4SS_RATE(_rate) ((_rate) >= MGN_MCS24 && (_rate) <= MGN_MCS31) + +#define IS_VHT1SS_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT1SS_MCS9) +#define IS_VHT2SS_RATE(_rate) ((_rate) >= MGN_VHT2SS_MCS0 && (_rate) <= MGN_VHT2SS_MCS9) +#define IS_VHT3SS_RATE(_rate) ((_rate) >= MGN_VHT3SS_MCS0 && (_rate) <= MGN_VHT3SS_MCS9) +#define IS_VHT4SS_RATE(_rate) ((_rate) >= MGN_VHT4SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9) + +#define IS_1T_RATE(_rate) (IS_CCK_RATE((_rate)) || IS_OFDM_RATE((_rate)) || IS_HT1SS_RATE((_rate)) || IS_VHT1SS_RATE((_rate))) +#define IS_2T_RATE(_rate) (IS_HT2SS_RATE((_rate)) || IS_VHT2SS_RATE((_rate))) +#define IS_3T_RATE(_rate) (IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate))) +#define IS_4T_RATE(_rate) (IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate))) + +#define MGN_RATE_STR(_rate) \ + (_rate == MGN_1M) ? "CCK_1M" : \ + (_rate == MGN_2M) ? "CCK_2M" : \ + (_rate == MGN_5_5M) ? "CCK_5.5M" : \ + (_rate == MGN_11M) ? "CCK_11M" : \ + (_rate == MGN_6M) ? "OFDM_6M" : \ + (_rate == MGN_9M) ? "OFDM_9M" : \ + (_rate == MGN_12M) ? "OFDM_12M" : \ + (_rate == MGN_18M) ? "OFDM_18M" : \ + (_rate == MGN_24M) ? "OFDM_24M" : \ + (_rate == MGN_36M) ? "OFDM_36M" : \ + (_rate == MGN_48M) ? "OFDM_48M" : \ + (_rate == MGN_54M) ? "OFDM_54M" : \ + (_rate == MGN_MCS32) ? "MCS32" : \ + (_rate == MGN_MCS0) ? "MCS0" : \ + (_rate == MGN_MCS1) ? "MCS1" : \ + (_rate == MGN_MCS2) ? "MCS2" : \ + (_rate == MGN_MCS3) ? "MCS3" : \ + (_rate == MGN_MCS4) ? "MCS4" : \ + (_rate == MGN_MCS5) ? "MCS5" : \ + (_rate == MGN_MCS6) ? "MCS6" : \ + (_rate == MGN_MCS7) ? "MCS7" : \ + (_rate == MGN_MCS8) ? "MCS8" : \ + (_rate == MGN_MCS9) ? "MCS9" : \ + (_rate == MGN_MCS10) ? "MCS10" : \ + (_rate == MGN_MCS11) ? "MCS11" : \ + (_rate == MGN_MCS12) ? "MCS12" : \ + (_rate == MGN_MCS13) ? "MCS13" : \ + (_rate == MGN_MCS14) ? "MCS14" : \ + (_rate == MGN_MCS15) ? "MCS15" : \ + (_rate == MGN_MCS16) ? "MCS16" : \ + (_rate == MGN_MCS17) ? "MCS17" : \ + (_rate == MGN_MCS18) ? "MCS18" : \ + (_rate == MGN_MCS19) ? "MCS19" : \ + (_rate == MGN_MCS20) ? "MCS20" : \ + (_rate == MGN_MCS21) ? "MCS21" : \ + (_rate == MGN_MCS22) ? "MCS22" : \ + (_rate == MGN_MCS23) ? "MCS23" : \ + (_rate == MGN_MCS24) ? "MCS24" : \ + (_rate == MGN_MCS25) ? "MCS25" : \ + (_rate == MGN_MCS26) ? "MCS26" : \ + (_rate == MGN_MCS27) ? "MCS27" : \ + (_rate == MGN_MCS28) ? "MCS28" : \ + (_rate == MGN_MCS29) ? "MCS29" : \ + (_rate == MGN_MCS30) ? "MCS30" : \ + (_rate == MGN_MCS31) ? "MCS31" : \ + (_rate == MGN_VHT1SS_MCS0) ? "VHT1SMCS0" : \ + (_rate == MGN_VHT1SS_MCS1) ? "VHT1SMCS1" : \ + (_rate == MGN_VHT1SS_MCS2) ? "VHT1SMCS2" : \ + (_rate == MGN_VHT1SS_MCS3) ? "VHT1SMCS3" : \ + (_rate == MGN_VHT1SS_MCS4) ? "VHT1SMCS4" : \ + (_rate == MGN_VHT1SS_MCS5) ? "VHT1SMCS5" : \ + (_rate == MGN_VHT1SS_MCS6) ? "VHT1SMCS6" : \ + (_rate == MGN_VHT1SS_MCS7) ? "VHT1SMCS7" : \ + (_rate == MGN_VHT1SS_MCS8) ? "VHT1SMCS8" : \ + (_rate == MGN_VHT1SS_MCS9) ? "VHT1SMCS9" : \ + (_rate == MGN_VHT2SS_MCS0) ? "VHT2SMCS0" : \ + (_rate == MGN_VHT2SS_MCS1) ? "VHT2SMCS1" : \ + (_rate == MGN_VHT2SS_MCS2) ? "VHT2SMCS2" : \ + (_rate == MGN_VHT2SS_MCS3) ? "VHT2SMCS3" : \ + (_rate == MGN_VHT2SS_MCS4) ? "VHT2SMCS4" : \ + (_rate == MGN_VHT2SS_MCS5) ? "VHT2SMCS5" : \ + (_rate == MGN_VHT2SS_MCS6) ? "VHT2SMCS6" : \ + (_rate == MGN_VHT2SS_MCS7) ? "VHT2SMCS7" : \ + (_rate == MGN_VHT2SS_MCS8) ? "VHT2SMCS8" : \ + (_rate == MGN_VHT2SS_MCS9) ? "VHT2SMCS9" : \ + (_rate == MGN_VHT3SS_MCS0) ? "VHT3SMCS0" : \ + (_rate == MGN_VHT3SS_MCS1) ? "VHT3SMCS1" : \ + (_rate == MGN_VHT3SS_MCS2) ? "VHT3SMCS2" : \ + (_rate == MGN_VHT3SS_MCS3) ? "VHT3SMCS3" : \ + (_rate == MGN_VHT3SS_MCS4) ? "VHT3SMCS4" : \ + (_rate == MGN_VHT3SS_MCS5) ? "VHT3SMCS5" : \ + (_rate == MGN_VHT3SS_MCS6) ? "VHT3SMCS6" : \ + (_rate == MGN_VHT3SS_MCS7) ? "VHT3SMCS7" : \ + (_rate == MGN_VHT3SS_MCS8) ? "VHT3SMCS8" : \ + (_rate == MGN_VHT3SS_MCS9) ? "VHT3SMCS9" : \ + (_rate == MGN_VHT4SS_MCS0) ? "VHT4SMCS0" : \ + (_rate == MGN_VHT4SS_MCS1) ? "VHT4SMCS1" : \ + (_rate == MGN_VHT4SS_MCS2) ? "VHT4SMCS2" : \ + (_rate == MGN_VHT4SS_MCS3) ? "VHT4SMCS3" : \ + (_rate == MGN_VHT4SS_MCS4) ? "VHT4SMCS4" : \ + (_rate == MGN_VHT4SS_MCS5) ? "VHT4SMCS5" : \ + (_rate == MGN_VHT4SS_MCS6) ? "VHT4SMCS6" : \ + (_rate == MGN_VHT4SS_MCS7) ? "VHT4SMCS7" : \ + (_rate == MGN_VHT4SS_MCS8) ? "VHT4SMCS8" : \ + (_rate == MGN_VHT4SS_MCS9) ? "VHT4SMCS9" : "UNKNOWN" + +typedef enum _RATE_SECTION { + CCK = 0, + OFDM = 1, + HT_MCS0_MCS7 = 2, + HT_MCS8_MCS15 = 3, + HT_MCS16_MCS23 = 4, + HT_MCS24_MCS31 = 5, + HT_1SS = HT_MCS0_MCS7, + HT_2SS = HT_MCS8_MCS15, + HT_3SS = HT_MCS16_MCS23, + HT_4SS = HT_MCS24_MCS31, + VHT_1SSMCS0_1SSMCS9 = 6, + VHT_2SSMCS0_2SSMCS9 = 7, + VHT_3SSMCS0_3SSMCS9 = 8, + VHT_4SSMCS0_4SSMCS9 = 9, + VHT_1SS = VHT_1SSMCS0_1SSMCS9, + VHT_2SS = VHT_2SSMCS0_2SSMCS9, + VHT_3SS = VHT_3SSMCS0_3SSMCS9, + VHT_4SS = VHT_4SSMCS0_4SSMCS9, + RATE_SECTION_NUM, +} RATE_SECTION; + +const char *rate_section_str(u8 section); + +#define IS_CCK_RATE_SECTION(section) ((section) == CCK) +#define IS_OFDM_RATE_SECTION(section) ((section) == OFDM) +#define IS_HT_RATE_SECTION(section) ((section) >= HT_1SS && (section) <= HT_4SS) +#define IS_VHT_RATE_SECTION(section) ((section) >= VHT_1SS && (section) <= VHT_4SS) + +#define IS_1T_RATE_SECTION(section) ((section) == CCK || (section) == OFDM || (section) == HT_1SS || (section) == VHT_1SS) +#define IS_2T_RATE_SECTION(section) ((section) == HT_2SS || (section) == VHT_2SS) +#define IS_3T_RATE_SECTION(section) ((section) == HT_3SS || (section) == VHT_3SS) +#define IS_4T_RATE_SECTION(section) ((section) == HT_4SS || (section) == VHT_4SS) + +extern u8 mgn_rates_cck[]; +extern u8 mgn_rates_ofdm[]; +extern u8 mgn_rates_mcs0_7[]; +extern u8 mgn_rates_mcs8_15[]; +extern u8 mgn_rates_mcs16_23[]; +extern u8 mgn_rates_mcs24_31[]; +extern u8 mgn_rates_vht1ss[]; +extern u8 mgn_rates_vht2ss[]; +extern u8 mgn_rates_vht3ss[]; +extern u8 mgn_rates_vht4ss[]; + +struct rate_section_ent { + u8 tx_num; /* value of RF_TX_NUM */ + u8 rate_num; + u8 *rates; +}; + +extern struct rate_section_ent rates_by_sections[]; + +#define rate_section_to_tx_num(section) (rates_by_sections[(section)].tx_num) +#define rate_section_rate_num(section) (rates_by_sections[(section)].rate_num) + +/* NOTE: This data is for statistical purposes; not all hardware provides this + * information for frames received. Not setting these will not cause + * any adverse affects. */ +struct ieee80211_rx_stats { + /* u32 mac_time[2]; */ + s8 rssi; + u8 signal; + u8 noise; + u8 received_channel; + u16 rate; /* in 100 kbps */ + /* u8 control; */ + u8 mask; + u8 freq; + u16 len; +}; + +/* IEEE 802.11 requires that STA supports concurrent reception of at least + * three fragmented frames. This define can be increased to support more + * concurrent frames, but it should be noted that each entry can consume about + * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ +#define IEEE80211_FRAG_CACHE_LEN 4 + +struct ieee80211_frag_entry { + u32 first_frag_time; + uint seq; + uint last_frag; + uint qos; /* jackson */ + uint tid; /* jackson */ + struct sk_buff *skb; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; +}; + +struct ieee80211_stats { + uint tx_unicast_frames; + uint tx_multicast_frames; + uint tx_fragments; + uint tx_unicast_octets; + uint tx_multicast_octets; + uint tx_deferred_transmissions; + uint tx_single_retry_frames; + uint tx_multiple_retry_frames; + uint tx_retry_limit_exceeded; + uint tx_discards; + uint rx_unicast_frames; + uint rx_multicast_frames; + uint rx_fragments; + uint rx_unicast_octets; + uint rx_multicast_octets; + uint rx_fcs_errors; + uint rx_discards_no_buffer; + uint tx_discards_wrong_sa; + uint rx_discards_undecryptable; + uint rx_message_in_msg_fragments; + uint rx_message_in_bad_msg_fragments; +}; +struct ieee80211_softmac_stats { + uint rx_ass_ok; + uint rx_ass_err; + uint rx_probe_rq; + uint tx_probe_rs; + uint tx_beacons; + uint rx_auth_rq; + uint rx_auth_rs_ok; + uint rx_auth_rs_err; + uint tx_auth_rq; + uint no_auth_rs; + uint no_ass_rs; + uint tx_ass_rq; + uint rx_ass_rq; + uint tx_probe_rq; + uint reassoc; + uint swtxstop; + uint swtxawake; +}; + +#define SEC_KEY_1 (1<<0) +#define SEC_KEY_2 (1<<1) +#define SEC_KEY_3 (1<<2) +#define SEC_KEY_4 (1<<3) +#define SEC_ACTIVE_KEY (1<<4) +#define SEC_AUTH_MODE (1<<5) +#define SEC_UNICAST_GROUP (1<<6) +#define SEC_LEVEL (1<<7) +#define SEC_ENABLED (1<<8) + +#define SEC_LEVEL_0 0 /* None */ +#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ +#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ +#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ +#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ + +#define WEP_KEYS 4 +#define WEP_KEY_LEN 13 + + + +struct ieee80211_security { + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1; + u8 key_sizes[WEP_KEYS]; + u8 keys[WEP_KEYS][WEP_KEY_LEN]; + u8 level; + u16 flags; +} __attribute__((packed)); + + +/* + + 802.11 data frame from AP + + ,-------------------------------------------------------------------. +Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | + |------|------|---------|---------|---------|------|---------|------| +Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | + | | tion | (BSSID) | | | ence | data | | + `-------------------------------------------------------------------' + +Total: 28-2340 bytes + +*/ + +struct ieee80211_header_data { + u16 frame_ctl; + u16 duration_id; + u8 addr1[6]; + u8 addr2[6]; + u8 addr3[6]; + u16 seq_ctrl; +}; + +#define BEACON_PROBE_SSID_ID_POSITION 12 + +/* Management Frame Information Element Types */ +#define MFIE_TYPE_SSID 0 +#define MFIE_TYPE_RATES 1 +#define MFIE_TYPE_FH_SET 2 +#define MFIE_TYPE_DS_SET 3 +#define MFIE_TYPE_CF_SET 4 +#define MFIE_TYPE_TIM 5 +#define MFIE_TYPE_IBSS_SET 6 +#define MFIE_TYPE_CHALLENGE 16 +#define MFIE_TYPE_ERP 42 +#define MFIE_TYPE_RSN 48 +#define MFIE_TYPE_RATES_EX 50 +#define MFIE_TYPE_GENERIC 221 + + +struct ieee80211_info_element_hdr { + u8 id; + u8 len; +} __attribute__((packed)); + +struct ieee80211_info_element { + u8 id; + u8 len; + u8 data[0]; +} __attribute__((packed)); + +/* + * These are the data types that can make up management packets + * + u16 auth_algorithm; + u16 auth_sequence; + u16 beacon_interval; + u16 capability; + u8 current_ap[ETH_ALEN]; + u16 listen_interval; + struct { + u16 association_id:14, reserved:2; + } __attribute__ ((packed)); + u32 time_stamp[2]; + u16 reason; + u16 status; +*/ + +#define IEEE80211_DEFAULT_TX_ESSID "Penguin" +#define IEEE80211_DEFAULT_BASIC_RATE 10 + + +struct ieee80211_authentication { + struct ieee80211_header_data header; + u16 algorithm; + u16 transaction; + u16 status; + /* struct ieee80211_info_element_hdr info_element; */ +} __attribute__((packed)); + +struct ieee80211_probe_response { + struct ieee80211_header_data header; + u32 time_stamp[2]; + u16 beacon_interval; + u16 capability; + struct ieee80211_info_element info_element; +} __attribute__((packed)); + +struct ieee80211_probe_request { + struct ieee80211_header_data header; + /*struct ieee80211_info_element info_element;*/ +} __attribute__((packed)); + +struct ieee80211_assoc_request_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 listen_interval; + /* u8 current_ap[ETH_ALEN]; */ + struct ieee80211_info_element_hdr info_element; +} __attribute__((packed)); + +struct ieee80211_assoc_response_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 status; + u16 aid; + /* struct ieee80211_info_element info_element; supported rates */ +} __attribute__((packed)); + +struct ieee80211_txb { + u8 nr_frags; + u8 encrypted; + u16 reserved; + u16 frag_size; + u16 payload_size; + struct sk_buff *fragments[0]; +}; + +/* SWEEP TABLE ENTRIES NUMBER*/ +#define MAX_SWEEP_TAB_ENTRIES 42 +#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 +/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs + * only use 8, and then use extended rates for the remaining supported + * rates. Other APs, however, stick all of their supported rates on the + * main rates information element... */ +#define MAX_RATES_LENGTH ((u8)12) +#define MAX_RATES_EX_LENGTH ((u8)16) +#define MAX_NETWORK_COUNT 128 +#define IEEE80211_SOFTMAC_SCAN_TIME 400 +/* (HZ / 2) */ +#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) + +#define CRC_LENGTH 4U + +#define MAX_WPA_IE_LEN (256) +#define MAX_WPS_IE_LEN (512) +#define MAX_P2P_IE_LEN (256) +#define MAX_WFD_IE_LEN (128) + +#define NETWORK_EMPTY_ESSID (1<<0) +#define NETWORK_HAS_OFDM (1<<1) +#define NETWORK_HAS_CCK (1<<2) + +#define IEEE80211_DTIM_MBCAST 4 +#define IEEE80211_DTIM_UCAST 2 +#define IEEE80211_DTIM_VALID 1 +#define IEEE80211_DTIM_INVALID 0 + +#define IEEE80211_PS_DISABLED 0 +#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST +#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST +#define IW_ESSID_MAX_SIZE 32 +/* +join_res: +-1: authentication fail +-2: association fail +> 0: TID +*/ + + +enum ieee80211_state { + + /* the card is not linked at all */ + IEEE80211_NOLINK = 0, + + /* IEEE80211_ASSOCIATING* are for BSS client mode + * the driver shall not perform RX filtering unless + * the state is LINKED. + * The driver shall just check for the state LINKED and + * defaults to NOLINK for ALL the other states (including + * LINKED_SCANNING) + */ + + /* the association procedure will start (wq scheduling)*/ + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATING_RETRY, + + /* the association procedure is sending AUTH request*/ + IEEE80211_ASSOCIATING_AUTHENTICATING, + + /* the association procedure has successfully authentcated + * and is sending association request + */ + IEEE80211_ASSOCIATING_AUTHENTICATED, + + /* the link is ok. the card associated to a BSS or linked + * to a ibss cell or acting as an AP and creating the bss + */ + IEEE80211_LINKED, + + /* same as LINKED, but the driver shall apply RX filter + * rules as we are in NO_LINK mode. As the card is still + * logically linked, but it is doing a syncro site survey + * then it will be back to LINKED state. + */ + IEEE80211_LINKED_SCANNING, + +}; + +#define DEFAULT_MAX_SCAN_AGE (15 * HZ) +#define DEFAULT_FTS 2346 +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] +#define MAC_SFMT "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx" +#define MAC_SARG(x) ((u8*)(x)),((u8*)(x)) + 1,((u8*)(x)) + 2,((u8*)(x)) + 3,((u8*)(x)) + 4,((u8*)(x)) + 5 +#define IP_FMT "%d.%d.%d.%d" +#define IP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3] +#define PORT_FMT "%u" +#define PORT_ARG(x) ntohs(*((u16 *)(x))) + +extern __inline int is_multicast_mac_addr(const u8 *addr) +{ + return (addr[0] != 0xff) && (0x01 & addr[0]); +} + +extern __inline int is_broadcast_mac_addr(const u8 *addr) +{ + return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ + (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); +} + +extern __inline int is_zero_mac_addr(const u8 *addr) +{ + return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) && \ + (addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00)); +} + +#define CFG_IEEE80211_RESERVE_FCS (1<<0) +#define CFG_IEEE80211_COMPUTE_FCS (1<<1) + +typedef struct tx_pending_t { + int frag; + struct ieee80211_txb *txb; +} tx_pending_t; + +#define TID_NUM 16 + +#define IEEE_A (1<<0) +#define IEEE_B (1<<1) +#define IEEE_G (1<<2) +#define IEEE_MODE_MASK (IEEE_A | IEEE_B | IEEE_G) + +/* Baron move to ieee80211.c */ +int ieee80211_is_empty_essid(const char *essid, int essid_len); +int ieee80211_get_hdrlen(u16 fc); + + +/* Action category code */ +enum rtw_ieee80211_category { + RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, + RTW_WLAN_CATEGORY_QOS = 1, + RTW_WLAN_CATEGORY_DLS = 2, + RTW_WLAN_CATEGORY_BACK = 3, + RTW_WLAN_CATEGORY_PUBLIC = 4, /* IEEE 802.11 public action frames */ + RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, + RTW_WLAN_CATEGORY_FT = 6, + RTW_WLAN_CATEGORY_HT = 7, + RTW_WLAN_CATEGORY_SA_QUERY = 8, + RTW_WLAN_CATEGORY_WNM = 10, + RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, /* add for CONFIG_IEEE80211W, none 11w also can use */ + RTW_WLAN_CATEGORY_TDLS = 12, + RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, /* add for CONFIG_IEEE80211W, none 11w also can use */ + RTW_WLAN_CATEGORY_WMM = 17, + RTW_WLAN_CATEGORY_VHT = 21, + RTW_WLAN_CATEGORY_P2P = 0x7f,/* P2P action frames */ +}; + +/* SPECTRUM_MGMT action code */ +enum rtw_ieee80211_spectrum_mgmt_actioncode { + RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, + RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1, + RTW_WLAN_ACTION_SPCT_TPC_REQ = 2, + RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3, + RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4, + RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, +}; + +enum _PUBLIC_ACTION { + ACT_PUBLIC_BSSCOEXIST = 0, /* 20/40 BSS Coexistence */ + ACT_PUBLIC_DSE_ENABLE = 1, + ACT_PUBLIC_DSE_DEENABLE = 2, + ACT_PUBLIC_DSE_REG_LOCATION = 3, + ACT_PUBLIC_EXT_CHL_SWITCH = 4, + ACT_PUBLIC_DSE_MSR_REQ = 5, + ACT_PUBLIC_DSE_MSR_RPRT = 6, + ACT_PUBLIC_MP = 7, /* Measurement Pilot */ + ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, + ACT_PUBLIC_VENDOR = 9, /* for WIFI_DIRECT */ + ACT_PUBLIC_GAS_INITIAL_REQ = 10, + ACT_PUBLIC_GAS_INITIAL_RSP = 11, + ACT_PUBLIC_GAS_COMEBACK_REQ = 12, + ACT_PUBLIC_GAS_COMEBACK_RSP = 13, + ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, + ACT_PUBLIC_LOCATION_TRACK = 15, + ACT_PUBLIC_MAX +}; + +/* BACK action code */ +enum rtw_ieee80211_back_actioncode { + RTW_WLAN_ACTION_ADDBA_REQ = 0, + RTW_WLAN_ACTION_ADDBA_RESP = 1, + RTW_WLAN_ACTION_DELBA = 2, +}; + +/* HT features action code */ +enum rtw_ieee80211_ht_actioncode { + RTW_WLAN_ACTION_HT_NOTI_CHNL_WIDTH = 0, + RTW_WLAN_ACTION_HT_SM_PS = 1, + RTW_WLAN_ACTION_HT_PSMP = 2, + RTW_WLAN_ACTION_HT_SET_PCO_PHASE = 3, + RTW_WLAN_ACTION_HT_CSI = 4, + RTW_WLAN_ACTION_HT_NON_COMPRESS_BEAMFORMING = 5, + RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING = 6, + RTW_WLAN_ACTION_HT_ASEL_FEEDBACK = 7, +}; + +/* BACK (block-ack) parties */ +enum rtw_ieee80211_back_parties { + RTW_WLAN_BACK_RECIPIENT = 0, + RTW_WLAN_BACK_INITIATOR = 1, + RTW_WLAN_BACK_TIMER = 2, +}; + +/*20/40 BSS Coexistence element */ +#define RTW_WLAN_20_40_BSS_COEX_INFO_REQ BIT(0) +#define RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL BIT(1) +#define RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ BIT(2) +#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_REQ BIT(3) +#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_GRNT BIT(4) + +/* VHT features action code */ +enum rtw_ieee80211_vht_actioncode { + RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING = 0, + RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT = 1, + RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2, +}; + +/*IEEE 802.11r action code*/ + +#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) + * 00:50:F2 */ + #define WME_OUI_TYPE 2 +#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 +#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 +#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 +#define WME_VERSION 1 + +#define WME_ACTION_CODE_SETUP_REQUEST 0 +#define WME_ACTION_CODE_SETUP_RESPONSE 1 +#define WME_ACTION_CODE_TEARDOWN 2 + +#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0 +#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1 +#define WME_SETUP_RESPONSE_STATUS_REFUSED 3 + +#define WME_TSPEC_DIRECTION_UPLINK 0 +#define WME_TSPEC_DIRECTION_DOWNLINK 1 +#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3 + +#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ + +#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ + +/** + * enum rtw_ieee80211_channel_flags - channel flags + * + * Channel flags set by the regulatory control code. + * + * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled. + * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted + * on this channel. + * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel. + * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel. + * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel + * is not permitted. + * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel + * is not permitted. + */ +enum rtw_ieee80211_channel_flags { + RTW_IEEE80211_CHAN_DISABLED = 1 << 0, + RTW_IEEE80211_CHAN_PASSIVE_SCAN = 1 << 1, + RTW_IEEE80211_CHAN_NO_IBSS = 1 << 2, + RTW_IEEE80211_CHAN_RADAR = 1 << 3, + RTW_IEEE80211_CHAN_NO_HT40PLUS = 1 << 4, + RTW_IEEE80211_CHAN_NO_HT40MINUS = 1 << 5, +}; + +#define RTW_IEEE80211_CHAN_NO_HT40 \ + (RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS) + +/* Represent channel details, subset of ieee80211_channel */ +struct rtw_ieee80211_channel { + /* enum ieee80211_band band; */ + /* u16 center_freq; */ + u16 hw_value; + u32 flags; + /* int max_antenna_gain; */ + /* int max_power; */ + /* int max_reg_power; */ + /* bool beacon_found; */ + /* u32 orig_flags; */ + /* int orig_mag; */ + /* int orig_mpwr; */ +}; + +#define CHAN_FMT \ + /*"band:%d, "*/ \ + /*"center_freq:%u, "*/ \ + "hw_value:%u, " \ + "flags:0x%08x" \ + /*"max_antenna_gain:%d\n"*/ \ + /*"max_power:%d\n"*/ \ + /*"max_reg_power:%d\n"*/ \ + /*"beacon_found:%u\n"*/ \ + /*"orig_flags:0x%08x\n"*/ \ + /*"orig_mag:%d\n"*/ \ + /*"orig_mpwr:%d\n"*/ + +#define CHAN_ARG(channel) \ + /*(channel)->band*/ \ + /*, (channel)->center_freq*/ \ + (channel)->hw_value \ + , (channel)->flags \ + /*, (channel)->max_antenna_gain*/ \ + /*, (channel)->max_power*/ \ + /*, (channel)->max_reg_power*/ \ + /*, (channel)->beacon_found*/ \ + /*, (channel)->orig_flags*/ \ + /*, (channel)->orig_mag*/ \ + /*, (channel)->orig_mpwr*/ \ + +/* Parsed Information Elements */ +struct rtw_ieee802_11_elems { + u8 *ssid; + u8 ssid_len; + u8 *supp_rates; + u8 supp_rates_len; + u8 *fh_params; + u8 fh_params_len; + u8 *ds_params; + u8 ds_params_len; + u8 *cf_params; + u8 cf_params_len; + u8 *tim; + u8 tim_len; + u8 *ibss_params; + u8 ibss_params_len; + u8 *challenge; + u8 challenge_len; + u8 *erp_info; + u8 erp_info_len; + u8 *ext_supp_rates; + u8 ext_supp_rates_len; + u8 *wpa_ie; + u8 wpa_ie_len; + u8 *rsn_ie; + u8 rsn_ie_len; + u8 *wme; + u8 wme_len; + u8 *wme_tspec; + u8 wme_tspec_len; + u8 *wps_ie; + u8 wps_ie_len; + u8 *power_cap; + u8 power_cap_len; + u8 *supp_channels; + u8 supp_channels_len; + u8 *mdie; + u8 mdie_len; + u8 *ftie; + u8 ftie_len; + u8 *timeout_int; + u8 timeout_int_len; + u8 *ht_capabilities; + u8 ht_capabilities_len; + u8 *ht_operation; + u8 ht_operation_len; + u8 *vendor_ht_cap; + u8 vendor_ht_cap_len; + u8 *vht_capabilities; + u8 vht_capabilities_len; + u8 *vht_operation; + u8 vht_operation_len; + u8 *vht_op_mode_notify; + u8 vht_op_mode_notify_len; +}; + +typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; + +ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, + struct rtw_ieee802_11_elems *elems, + int show_errors); + +u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); +u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); + +enum secondary_ch_offset { + SCN = 0, /* no secondary channel */ + SCA = 1, /* secondary channel above */ + SCB = 3, /* secondary channel below */ +}; +u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset); +u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset); +u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt); +u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset); +u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence); + +u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit); +u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); +int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); + +void rtw_set_supported_rate(u8 *SupportedRates, uint mode) ; + +unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit); +unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit); +int rtw_get_wpa_cipher_suite(u8 *s); +int rtw_get_wpa2_cipher_suite(u8 *s); +int rtw_get_wapi_ie(u8 *in_ie, uint in_len, u8 *wapi_ie, u16 *wapi_len); +int rtw_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); +int rtw_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); + +int rtw_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie, u16 *wpa_len); + +u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type); +u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); +u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id , u8 *buf_content, uint *len_content); + +/** + * for_each_ie - iterate over continuous IEs + * @ie: + * @buf: + * @buf_len: + */ +#define for_each_ie(ie, buf, buf_len) \ + for (ie = (void *)buf; (((u8 *)ie) - ((u8 *)buf) + 1) < buf_len; ie = (void *)(((u8 *)ie) + *(((u8 *)ie)+1) + 2)) + +void dump_ies(void *sel, u8 *buf, u32 buf_len); + +void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len); + +void dump_wps_ie(void *sel, u8 *ie, u32 ie_len); + +void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset); + +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset); + +bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a + , u8 ch_b, u8 bw_b, u8 offset_b); +void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset); + +u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len); +int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie); +void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len); +u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); +u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); +u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); +uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg); +uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id); +u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen); +void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex); +void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); + +void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len); +u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); +u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); +uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg); +uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id); +u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen); +void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex); +void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); + +uint rtw_get_rateset_len(u8 *rateset); + +struct registry_priv; +int rtw_generate_ie(struct registry_priv *pregistrypriv); + +int rtw_get_bit_value_from_ieee_value(u8 val); + +uint rtw_is_cckrates_included(u8 *rate); + +uint rtw_is_cckratesonly_included(u8 *rate); + +int rtw_check_network_type(unsigned char *rate, int ratelen, int channel); + +void rtw_get_bcn_info(struct wlan_network *pnetwork); + +u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit); +void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr); + +u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char *MCS_rate); +u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set); +u32 rtw_ht_mcs_set_to_bitmap(u8 *mcs_set, u8 nss); + +int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8 *category, u8 *action); +const char *action_public_str(u8 action); + +u8 key_2char2num(u8 hch, u8 lch); +u8 str_2char2num(u8 hch, u8 lch); +void macstr2num(u8 *dst, u8 *src); +u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); +int wifirate2_ratetbl_inx(unsigned char rate); + +#endif /* IEEE80211_H */ diff --git a/drivers/staging/rtl8821ce/include/ieee80211_ext.h b/drivers/staging/rtl8821ce/include/ieee80211_ext.h new file mode 100644 index 000000000000..c6da7da3f598 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/ieee80211_ext.h @@ -0,0 +1,289 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __IEEE80211_EXT_H +#define __IEEE80211_EXT_H + +#include <drv_conf.h> +#include <osdep_service.h> +#include <drv_types.h> + +#define WMM_OUI_TYPE 2 +#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0 +#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1 +#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2 +#define WMM_VERSION 1 + +#define WPA_PROTO_WPA BIT(0) +#define WPA_PROTO_RSN BIT(1) + +#define WPA_KEY_MGMT_IEEE8021X BIT(0) +#define WPA_KEY_MGMT_PSK BIT(1) +#define WPA_KEY_MGMT_NONE BIT(2) +#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3) +#define WPA_KEY_MGMT_WPA_NONE BIT(4) + +#define WPA_CAPABILITY_PREAUTH BIT(0) +#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6) +#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9) + +#define PMKID_LEN 16 + +struct wpa_ie_hdr { + u8 elem_id; + u8 len; + u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ + u8 version[2]; /* little endian */ +} __attribute__((packed)); + +struct rsn_ie_hdr { + u8 elem_id; /* WLAN_EID_RSN */ + u8 len; + u8 version[2]; /* little endian */ +} __attribute__((packed)); + +struct wme_ac_parameter { +#ifdef __LITTLE_ENDIAN + /* byte 1 */ + u8 aifsn:4, + acm:1, + aci:2, + reserved:1; + + /* byte 2 */ + u8 eCWmin:4, + eCWmax:4; +#else + /* byte 1 */ + u8 reserved:1, + aci:2, + acm:1, + aifsn:4; + + /* byte 2 */ + u8 eCWmax:4, + eCWmin:4; +#else +#error "Please fix <endian.h>" +#endif + + /* bytes 3 & 4 */ + u16 txopLimit; +} __attribute__((packed)); + +struct wme_parameter_element { + /* required fields for WME version 1 */ + u8 oui[3]; + u8 oui_type; + u8 oui_subtype; + u8 version; + u8 acInfo; + u8 reserved; + struct wme_ac_parameter ac[4]; + +} __attribute__((packed)); + +#define WPA_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define WPA_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define WPA_PUT_LE32(a, val) \ + do { \ + (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[0] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val)) +/* #define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) */ + +/* Action category code */ +enum ieee80211_category { + WLAN_CATEGORY_SPECTRUM_MGMT = 0, + WLAN_CATEGORY_QOS = 1, + WLAN_CATEGORY_DLS = 2, + WLAN_CATEGORY_BACK = 3, + WLAN_CATEGORY_HT = 7, + WLAN_CATEGORY_WMM = 17, +}; + +/* SPECTRUM_MGMT action code */ +enum ieee80211_spectrum_mgmt_actioncode { + WLAN_ACTION_SPCT_MSR_REQ = 0, + WLAN_ACTION_SPCT_MSR_RPRT = 1, + WLAN_ACTION_SPCT_TPC_REQ = 2, + WLAN_ACTION_SPCT_TPC_RPRT = 3, + WLAN_ACTION_SPCT_CHL_SWITCH = 4, + WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, +}; + +/* BACK action code */ +enum ieee80211_back_actioncode { + WLAN_ACTION_ADDBA_REQ = 0, + WLAN_ACTION_ADDBA_RESP = 1, + WLAN_ACTION_DELBA = 2, +}; + +/* HT features action code */ +enum ieee80211_ht_actioncode { + WLAN_ACTION_NOTIFY_CH_WIDTH = 0, + WLAN_ACTION_SM_PS = 1, + WLAN_ACTION_PSPM = 2, + WLAN_ACTION_PCO_PHASE = 3, + WLAN_ACTION_MIMO_CSI_MX = 4, + WLAN_ACTION_MIMO_NONCP_BF = 5, + WLAN_ACTION_MIMP_CP_BF = 6, + WLAN_ACTION_ASEL_INDICATES_FB = 7, + WLAN_ACTION_HI_INFO_EXCHG = 8, +}; + +/* BACK (block-ack) parties */ +enum ieee80211_back_parties { + WLAN_BACK_RECIPIENT = 0, + WLAN_BACK_INITIATOR = 1, + WLAN_BACK_TIMER = 2, +}; + +struct ieee80211_mgmt { + u16 frame_control; + u16 duration; + u8 da[6]; + u8 sa[6]; + u8 bssid[6]; + u16 seq_ctrl; + union { + struct { + u16 auth_alg; + u16 auth_transaction; + u16 status_code; + /* possibly followed by Challenge text */ + u8 variable[0]; + } __attribute__((packed)) auth; + struct { + u16 reason_code; + } __attribute__((packed)) deauth; + struct { + u16 capab_info; + u16 listen_interval; + /* followed by SSID and Supported rates */ + u8 variable[0]; + } __attribute__((packed)) assoc_req; + struct { + u16 capab_info; + u16 status_code; + u16 aid; + /* followed by Supported rates */ + u8 variable[0]; + } __attribute__((packed)) assoc_resp, reassoc_resp; + struct { + u16 capab_info; + u16 listen_interval; + u8 current_ap[6]; + /* followed by SSID and Supported rates */ + u8 variable[0]; + } __attribute__((packed)) reassoc_req; + struct { + u16 reason_code; + } __attribute__((packed)) disassoc; + struct { + __le64 timestamp; + u16 beacon_int; + u16 capab_info; + /* followed by some of SSID, Supported rates, + * FH Params, DS Params, CF Params, IBSS Params, TIM */ + u8 variable[0]; + } __attribute__((packed)) beacon; + struct { + /* only variable items: SSID, Supported rates */ + u8 variable[0]; + } __attribute__((packed)) probe_req; + struct { + __le64 timestamp; + u16 beacon_int; + u16 capab_info; + /* followed by some of SSID, Supported rates, + * FH Params, DS Params, CF Params, IBSS Params */ + u8 variable[0]; + } __attribute__((packed)) probe_resp; + struct { + u8 category; + union { + struct { + u8 action_code; + u8 dialog_token; + u8 status_code; + u8 variable[0]; + } __attribute__((packed)) wme_action; + struct { + u8 action_code; + u8 dialog_token; + u16 capab; + u16 timeout; + u16 start_seq_num; + } __attribute__((packed)) addba_req; + struct { + u8 action_code; + u8 dialog_token; + u16 status; + u16 capab; + u16 timeout; + } __attribute__((packed)) addba_resp; + struct { + u8 action_code; + u16 params; + u16 reason_code; + } __attribute__((packed)) delba; + struct { + u8 action_code; + /* capab_info for open and confirm, + * reason for close + */ + u16 aux; + /* Followed in plink_confirm by status + * code, AID and supported rates, + * and directly by supported rates in + * plink_open and plink_close + */ + u8 variable[0]; + } __attribute__((packed)) plink_action; + struct { + u8 action_code; + u8 variable[0]; + } __attribute__((packed)) mesh_action; + } __attribute__((packed)) u; + } __attribute__((packed)) action; + } __attribute__((packed)) u; +} __attribute__((packed)); + +/* mgmt header + 1 byte category code */ +#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u) + +#endif diff --git a/drivers/staging/rtl8821ce/include/if_ether.h b/drivers/staging/rtl8821ce/include/if_ether.h new file mode 100644 index 000000000000..84eef825ae5c --- /dev/null +++ b/drivers/staging/rtl8821ce/include/if_ether.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _LINUX_IF_ETHER_H +#define _LINUX_IF_ETHER_H + +/* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble + * and FCS/CRC (frame check sequence). + */ + +#define ETH_ALEN 6 /* Octets in one ethernet addr */ +#define ETH_HLEN 14 /* Total octets in header. */ +#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ +#define ETH_DATA_LEN 1500 /* Max. octets in payload */ +#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ + +/* + * These are the defined Ethernet Protocol ID's. + */ + +#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */ +#define ETH_P_PUP 0x0200 /* Xerox PUP packet */ +#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */ +#define ETH_P_IP 0x0800 /* Internet Protocol packet */ +#define ETH_P_X25 0x0805 /* CCITT X.25 */ +#define ETH_P_ARP 0x0806 /* Address Resolution packet */ +#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ +#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ +#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ +#define ETH_P_DEC 0x6000 /* DEC Assigned proto */ +#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ +#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ +#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */ +#define ETH_P_LAT 0x6004 /* DEC LAT */ +#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */ +#define ETH_P_CUST 0x6006 /* DEC Customer use */ +#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */ +#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */ +#define ETH_P_ATALK 0x809B /* Appletalk DDP */ +#define ETH_P_AARP 0x80F3 /* Appletalk AARP */ +#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ +#define ETH_P_IPX 0x8137 /* IPX over DIX */ +#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */ +#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */ +#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */ +#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */ +#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport + * over Ethernet + */ + +/* + * Non DIX types. Won't clash for 1500 types. + */ + +#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */ +#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */ +#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */ +#define ETH_P_802_2 0x0004 /* 802.2 frames */ +#define ETH_P_SNAP 0x0005 /* Internal only */ +#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */ +#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/ +#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */ +#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */ +#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/ +#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */ +#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@xxxxxxxx) */ +#define ETH_P_CONTROL 0x0016 /* Card specific control frames */ +#define ETH_P_IRDA 0x0017 /* Linux-IrDA */ +#define ETH_P_ECONET 0x0018 /* Acorn Econet */ + +/* + * This is an Ethernet frame header. + */ + +struct ethhdr { + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + unsigned short h_proto; /* packet type ID field */ +}; + +struct _vlan { + unsigned short h_vlan_TCI; /* Encapsulates priority and VLAN ID */ + unsigned short h_vlan_encapsulated_proto; +}; + +#define get_vlan_id(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI)) & 0xfff) +#define get_vlan_priority(pvlan) ((ntohs((unsigned short)pvlan->h_vlan_TCI))>>13) +#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short)pvlan->h_vlan_encapsulated_proto)) + +#endif /* _LINUX_IF_ETHER_H */ diff --git a/drivers/staging/rtl8821ce/include/ip.h b/drivers/staging/rtl8821ce/include/ip.h new file mode 100644 index 000000000000..67f36f80f7e2 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/ip.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_IP_H +#define _LINUX_IP_H + +/* SOL_IP socket options */ + +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_MINCOST 0x02 + +#define IPTOS_PREC_MASK 0xE0 +#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + +/* IP options */ +#define IPOPT_COPY 0x80 +#define IPOPT_CLASS_MASK 0x60 +#define IPOPT_NUMBER_MASK 0x1f + +#define IPOPT_COPIED(o) ((o)&IPOPT_COPY) +#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK) +#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK) + +#define IPOPT_CONTROL 0x00 +#define IPOPT_RESERVED1 0x20 +#define IPOPT_MEASUREMENT 0x40 +#define IPOPT_RESERVED2 0x60 + +#define IPOPT_END (0 | IPOPT_CONTROL) +#define IPOPT_NOOP (1 | IPOPT_CONTROL) +#define IPOPT_SEC (2 | IPOPT_CONTROL | IPOPT_COPY) +#define IPOPT_LSRR (3 | IPOPT_CONTROL | IPOPT_COPY) +#define IPOPT_TIMESTAMP (4 | IPOPT_MEASUREMENT) +#define IPOPT_RR (7 | IPOPT_CONTROL) +#define IPOPT_SID (8 | IPOPT_CONTROL | IPOPT_COPY) +#define IPOPT_SSRR (9 | IPOPT_CONTROL | IPOPT_COPY) +#define IPOPT_RA (20 | IPOPT_CONTROL | IPOPT_COPY) + +#define IPVERSION 4 +#define MAXTTL 255 +#define IPDEFTTL 64 + +/* struct timestamp, struct route and MAX_ROUTES are removed. + + REASONS: it is clear that nobody used them because: + - MAX_ROUTES value was wrong. + - "struct route" was wrong. + - "struct timestamp" had fatally misaligned bitfields and was completely unusable. + */ + +#define IPOPT_OPTVAL 0 +#define IPOPT_OLEN 1 +#define IPOPT_OFFSET 2 +#define IPOPT_MINOFF 4 +#define MAX_IPOPTLEN 40 +#define IPOPT_NOP IPOPT_NOOP +#define IPOPT_EOL IPOPT_END +#define IPOPT_TS IPOPT_TIMESTAMP + +#define IPOPT_TS_TSONLY 0 /* timestamps only */ +#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */ +#define IPOPT_TS_PRESPEC 3 /* specified modules only */ + + +struct ip_options { + __u32 faddr; /* Saved first hop address */ + unsigned char optlen; + unsigned char srr; + unsigned char rr; + unsigned char ts; + unsigned char is_setbyuser:1, /* Set by setsockopt? */ + is_data:1, /* Options in __data, rather than skb */ + is_strictroute:1, /* Strict source route */ + srr_is_hit:1, /* Packet destination addr was our one */ + is_changed:1, /* IP checksum more not valid */ + rr_needaddr:1, /* Need to record addr of outgoing dev */ + ts_needtime:1, /* Need to record timestamp */ + ts_needaddr:1; /* Need to record addr of outgoing dev */ + unsigned char router_alert; + unsigned char __pad1; + unsigned char __pad2; + unsigned char __data[0]; +}; + +#define optlength(opt) (sizeof(struct ip_options) + opt->optlen) + +struct iphdr { +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 ihl:4, + version:4; +#elif defined (__BIG_ENDIAN_BITFIELD) + __u8 version:4, + ihl:4; +#else +#error "Please fix <asm/byteorder.h>" +#endif + __u8 tos; + __u16 tot_len; + __u16 id; + __u16 frag_off; + __u8 ttl; + __u8 protocol; + __u16 check; + __u32 saddr; + __u32 daddr; + /*The options start here. */ +}; + +#endif /* _LINUX_IP_H */ diff --git a/drivers/staging/rtl8821ce/include/linux/wireless.h b/drivers/staging/rtl8821ce/include/linux/wireless.h new file mode 100644 index 000000000000..5de60ef76f15 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/linux/wireless.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _LINUX_WIRELESS_H +#define _LINUX_WIRELESS_H + +/***************************** INCLUDES *****************************/ + + #define __user + /* typedef uint16_t __u16; */ + #include <sys/socket.h> /* for "struct sockaddr" et al */ + #include <net/if.h> /* for IFNAMSIZ and co... */ + +/****************************** TYPES ******************************/ +/* --------------------------- SUBTYPES --------------------------- */ +/* + * For all data larger than 16 octets, we need to use a + * pointer to memory allocated in user space. + */ +struct iw_point { + void __user *pointer; /* Pointer to the data (in user space) */ + __u16 length; /* number of fields or size in bytes */ + __u16 flags; /* Optional params */ +}; + +/* ------------------------ IOCTL REQUEST ------------------------ */ +/* + * This structure defines the payload of an ioctl, and is used + * below. + * + * Note that this structure should fit on the memory footprint + * of iwreq (which is the same as ifreq), which mean a max size of + * 16 octets = 128 bits. Warning, pointers might be 64 bits wide... + * You should check this when increasing the structures defined + * above in this file... + */ +union iwreq_data { + /* Config - generic */ + char name[IFNAMSIZ]; + /* Name : used to verify the presence of wireless extensions. + * Name of the protocol/provider... */ + + struct iw_point data; /* Other large parameters */ +}; + +/* + * The structure to exchange data for ioctl. + * This structure is the same as 'struct ifreq', but (re)defined for + * convenience... + * Do I need to remind you about structure size (32 octets) ? + */ +struct iwreq { + union { + char ifrn_name[IFNAMSIZ]; /* if name, e.g. "eth0" */ + } ifr_ifrn; + + /* Data part (defined just above) */ + union iwreq_data u; +}; + +#endif /* _LINUX_WIRELESS_H */ diff --git a/drivers/staging/rtl8821ce/include/mlme_osdep.h b/drivers/staging/rtl8821ce/include/mlme_osdep.h new file mode 100644 index 000000000000..c7be286433bf --- /dev/null +++ b/drivers/staging/rtl8821ce/include/mlme_osdep.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __MLME_OSDEP_H_ +#define __MLME_OSDEP_H_ + +#if defined(PLATFORM_MPIXEL) + extern int time_after(u32 now, u32 old); +#endif + +extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); +extern void rtw_os_indicate_connect(_adapter *adapter); +void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted); +extern void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie); + +void rtw_reset_securitypriv(_adapter *adapter); + +#endif /* _MLME_OSDEP_H_ */ diff --git a/drivers/staging/rtl8821ce/include/mp_custom_oid.h b/drivers/staging/rtl8821ce/include/mp_custom_oid.h new file mode 100644 index 000000000000..e0cc9f64f60e --- /dev/null +++ b/drivers/staging/rtl8821ce/include/mp_custom_oid.h @@ -0,0 +1,350 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __CUSTOM_OID_H +#define __CUSTOM_OID_H + +/* by Owen + * 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit + * 0xFF818500 - 0xFF81850F RTL8185 Setup Utility + * 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility */ + +/* */ + +/* by Owen for Production Kit + * For Production Kit with Agilent Equipments + * in order to make our custom oids hopefully somewhat unique + * we will use 0xFF (indicating implementation specific OID) + * 81(first byte of non zero Realtek unique identifier) + * 80 (second byte of non zero Realtek unique identifier) + * XX (the custom OID number - providing 255 possible custom oids) */ + +#define OID_RT_PRO_RESET_DUT 0xFF818000 +#define OID_RT_PRO_SET_DATA_RATE 0xFF818001 +#define OID_RT_PRO_START_TEST 0xFF818002 +#define OID_RT_PRO_STOP_TEST 0xFF818003 +#define OID_RT_PRO_SET_PREAMBLE 0xFF818004 +#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005 +#define OID_RT_PRO_SET_FILTER_BB 0xFF818006 +#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007 +#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008 +#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009 +#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A + +#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D +#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E +#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F +#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010 +#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011 +#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012 +#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013 +#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014 +#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015 +#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016 +#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017 +#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018 +#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019 +#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A +#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B +#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C +#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D +#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E +#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F +#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020 +#define OID_RT_PRO_WRITE_EEPROM 0xFF818021 +#define OID_RT_PRO_READ_EEPROM 0xFF818022 +#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023 +#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024 +#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025 +#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026 +#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027 +#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028 +#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029 +#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A +#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C +/* added by Owen on 04/08/03 for Cameo's request */ +#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D +#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E +#define OID_RT_PRO_SET_MODULATION 0xFF81802F +/* */ + +/* Sean */ +#define OID_RT_DRIVER_OPTION 0xFF818080 +#define OID_RT_RF_OFF 0xFF818081 +#define OID_RT_AUTH_STATUS 0xFF818082 + +/* ************************************************************************ */ +#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B +#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C +#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B +#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043 +/* ************************************************************************ */ + +/* by Owen for RTL8185 Phy Status Report Utility */ +#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580 +#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 +#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 +#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583 +#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 +#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585 +#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 +/* */ + +/* by Owen on 03/09/19-03/09/22 for RTL8185 */ +#define OID_RT_WIRELESS_MODE 0xFF818500 +#define OID_RT_SUPPORTED_RATES 0xFF818501 +#define OID_RT_DESIRED_RATES 0xFF818502 +#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503 +/* */ + +#define OID_RT_GET_CONNECT_STATE 0xFF030001 +#define OID_RT_RESCAN 0xFF030002 +#define OID_RT_SET_KEY_LENGTH 0xFF030003 +#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004 + +#define OID_RT_SET_CHANNEL 0xFF010182 +#define OID_RT_SET_SNIFFER_MODE 0xFF010183 +#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184 +#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185 +#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186 +#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187 +#define OID_RT_GET_TX_RETRY 0xFF010188 +#define OID_RT_GET_RX_RETRY 0xFF010189 +#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A/* S */ +#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B/* S */ + +#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190 +#define OID_RT_GET_TX_BEACON_OK 0xFF010191 +#define OID_RT_GET_TX_BEACON_ERR 0xFF010192 +#define OID_RT_GET_RX_ICV_ERR 0xFF010193 +#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194 +#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195 +#define OID_RT_GET_PREAMBLE_MODE 0xFF010196 +#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197 +#define OID_RT_GET_AP_IP 0xFF010198 +#define OID_RT_GET_CHANNELPLAN 0xFF010199 +#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A +#define OID_RT_SET_BCN_INTVL 0xFF01019B +#define OID_RT_GET_RF_VENDER 0xFF01019C +#define OID_RT_DEDICATE_PROBE 0xFF01019D +#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E + +#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F + +#define OID_RT_GET_CCA_ERR 0xFF0101A0 +#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1 +#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2 + +#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3 +#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4 + +/* by Owen on 03/31/03 for Cameo's request */ +#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5 +/* */ +#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5 +#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6 +#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7 +#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8 +#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9 +#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA +#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB +#define OID_RT_GET_CHANNEL 0xFF0101AC + +#define OID_RT_SET_CHANNELPLAN 0xFF0101AD +#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE +#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF +#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0 +#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1 +#define OID_RT_GET_IS_ROAMING 0xFF0101B2 +#define OID_RT_GET_IS_PRIVACY 0xFF0101B3 +#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4 +#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5 +#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6 +#define OID_RT_RESET_LOG 0xFF0101B7 +#define OID_RT_GET_LOG 0xFF0101B8 +#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9 +#define OID_RT_GET_HEADER_FAIL 0xFF0101BA +#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB +#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC +#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD +#define OID_RT_GET_TX_INFO 0xFF0101BE +#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF +#define OID_RT_RF_READ_WRITE 0xFF0101C0 + +/* For Netgear request. 2005.01.13, by rcnjko. */ +#define OID_RT_FORCED_DATA_RATE 0xFF0101C1 +#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2 +/* For Netgear request. 2005.02.17, by rcnjko. */ +#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3 +/* For AZ project. 2005.06.27, by rcnjko. */ +#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4 + +/* Vincent 8185MP */ +#define OID_RT_PRO_RX_FILTER 0xFF0111C0 + +/* Andy TEST + * #define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 + * #define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 */ +#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1 +#define OID_CE_USB_READ_REGISTRY 0xFF0111C2 + +#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3 +#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4 +#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5 +#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6 +#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7 +#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8 +#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9 +#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA + +/* AP OID */ +#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300 +#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301 +#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302 +#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303 +#define OID_RT_AP_SUPPORTED 0xFF010304 /* Determine if driver supports AP mode. 2004.08.27, by rcnjko. */ +#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 /* Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. */ + +/* 8187MP. 2004.09.06, by rcnjko. */ +#define OID_RT_PRO8187_WI_POLL 0xFF818780 +#define OID_RT_PRO_WRITE_BB_REG 0xFF818781 +#define OID_RT_PRO_READ_BB_REG 0xFF818782 +#define OID_RT_PRO_WRITE_RF_REG 0xFF818783 +#define OID_RT_PRO_READ_RF_REG 0xFF818784 + +/* Meeting House. added by Annie, 2005-07-20. */ +#define OID_RT_MH_VENDER_ID 0xFFEDC100 + +/* 8711 MP OID added 20051230. */ +#define OID_RT_PRO8711_JOIN_BSS 0xFF871100/* S */ + +#define OID_RT_PRO_READ_REGISTER 0xFF871101 /* Q */ +#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 /* S */ + +#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 /* Q */ +#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 /* S */ + +#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 /* S */ + +#define OID_RT_PRO_READ16_EEPROM 0xFF871106 /* Q */ +#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 /* S */ + +#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 /* S */ +#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 /* Q */ + +#define OID_RT_PRO8711_WI_POLL 0xFF87110A /* Q */ +#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B /* Q */ +#define OID_RT_RD_ATTRIB_MEM 0xFF87110C/* Q */ +#define OID_RT_WR_ATTRIB_MEM 0xFF87110D/* S */ + +/* Method 2 for H2C/C2H */ +#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 /* S */ +#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 /* Q */ +#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 /* S */ +#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 /* Q */ +#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114/* Q */ + +#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 /* Q, S */ + +#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 /* S */ +#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 /* Q, S */ +#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 /* Q */ +#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 /* Q */ + +#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A /* S */ +#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B /* Q */ +#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C /* S */ +#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D /* Q */ +#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E /* S */ +#define OID_RT_POLL_RX_STATUS 0xFF87111F /* Q */ + +#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 /* Q, S */ +#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121/* S */ +#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122/* S */ +#define OID_RT_PRO_READ_TSSI 0xFF871123/* S */ +#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124/* S */ + +#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 /* Q */ +#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 /* S */ + +/* Method 2 , using workitem */ +#define OID_RT_SET_READ_REG 0xFF871181 /* S */ +#define OID_RT_SET_WRITE_REG 0xFF871182 /* S */ +#define OID_RT_SET_BURST_READ_REG 0xFF871183 /* S */ +#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 /* S */ +#define OID_RT_SET_WRITE_TXCMD 0xFF871185 /* S */ +#define OID_RT_SET_READ16_EEPROM 0xFF871186 /* S */ +#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 /* S */ +#define OID_RT_QRY_POLL_WKITEM 0xFF871188 /* Q */ + +/* For SDIO INTERFACE only */ +#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 /* Q, S */ +#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1 + +/* For USB INTERFACE only */ +#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 /* Q, S */ +#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 /* S */ +#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 /* S */ +#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 /* Q */ +#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 /* Q */ + +#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB /* S */ +#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC /* S */ +#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE + +#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 /* Q, S */ +#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 /* S */ +#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 /* S */ +#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 /* Q */ + +#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 /* Q, S */ + +#define OID_RT_PRO_READ_EFUSE 0xFF871205 /* Q */ +#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 /* S */ +#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 /* Q, S */ +#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 /* Q */ + +#define OID_RT_SET_BANDWIDTH 0xFF871209 /* S */ +#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A /* S */ + +#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B /* S */ + +#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C /* Q */ + +#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D /* S */ + +#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E /* S */ + +#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F /* S */ + +#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 /* Q */ + +#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 /* S */ +#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 /* Q */ +#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 /* Q */ + +#define OID_RT_SET_POWER_DOWN 0xFF871214 /* S */ + +#define OID_RT_GET_POWER_MODE 0xFF871215 /* Q */ + +#define OID_RT_PRO_EFUSE 0xFF871216 /* Q, S */ +#define OID_RT_PRO_EFUSE_MAP 0xFF871217 /* Q, S */ + +#endif /* #ifndef __CUSTOM_OID_H */ diff --git a/drivers/staging/rtl8821ce/include/nic_spec.h b/drivers/staging/rtl8821ce/include/nic_spec.h new file mode 100644 index 000000000000..d22ae1a16689 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/nic_spec.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __NIC_SPEC_H__ +#define __NIC_SPEC_H__ + +#include <drv_conf.h> + +#define RTL8711_MCTRL_ (0x20000) +#define RTL8711_UART_ (0x30000) +#define RTL8711_TIMER_ (0x40000) +#define RTL8711_FINT_ (0x50000) +#define RTL8711_HINT_ (0x50000) +#define RTL8711_GPIO_ (0x60000) +#define RTL8711_WLANCTRL_ (0x200000) +#define RTL8711_WLANFF_ (0xe00000) +#define RTL8711_HCICTRL_ (0x600000) +#define RTL8711_SYSCFG_ (0x620000) +#define RTL8711_SYSCTRL_ (0x620000) +#define RTL8711_MCCTRL_ (0x020000) + +#include <rtl8711_regdef.h> + +#include <rtl8711_bitdef.h> + +#endif /* __RTL8711_SPEC_H__ */ diff --git a/drivers/staging/rtl8821ce/include/osdep_intf.h b/drivers/staging/rtl8821ce/include/osdep_intf.h new file mode 100644 index 000000000000..dbaeaa4d6f10 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/osdep_intf.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __OSDEP_INTF_H_ +#define __OSDEP_INTF_H_ + +struct intf_priv { + + u8 *intf_dev; + u32 max_iosz; /* USB2.0: 128, USB1.1: 64, SDIO:64 */ + u32 max_xmitsz; /* USB2.0: unlimited, SDIO:512 */ + u32 max_recvsz; /* USB2.0: unlimited, SDIO:512 */ + + volatile u8 *io_rwmem; + volatile u8 *allocated_io_rwmem; + u32 io_wsz; /* unit: 4bytes */ + u32 io_rsz;/* unit: 4bytes */ + u8 intf_status; + + void (*_bus_io)(u8 *priv); + + /* + Under Sync. IRP (SDIO/USB) + A protection mechanism is necessary for the io_rwmem(read/write protocol) + + Under Async. IRP (SDIO/USB) + The protection mechanism is through the pending queue. + */ + + _mutex ioctl_mutex; +}; + +#ifdef CONFIG_R871X_TEST + int rtw_start_pseudo_adhoc(_adapter *padapter); + int rtw_stop_pseudo_adhoc(_adapter *padapter); +#endif + +struct dvobj_priv *devobj_init(void); +void devobj_deinit(struct dvobj_priv *pdvobj); + +u8 rtw_init_drv_sw(_adapter *padapter); +u8 rtw_free_drv_sw(_adapter *padapter); +u8 rtw_reset_drv_sw(_adapter *padapter); +void rtw_dev_unload(PADAPTER padapter); + +u32 rtw_start_drv_threads(_adapter *padapter); +void rtw_stop_drv_threads(_adapter *padapter); +void rtw_cancel_all_timer(_adapter *padapter); + +uint loadparam(_adapter *adapter); + +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); + +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); +struct net_device *rtw_init_netdev(_adapter *padapter); + +void rtw_os_ndev_free(_adapter *adapter); +int rtw_os_ndev_init(_adapter *adapter, const char *name); +void rtw_os_ndev_deinit(_adapter *adapter); +void rtw_os_ndev_unregister(_adapter *adapter); +void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj); +int rtw_os_ndevs_init(struct dvobj_priv *dvobj); +void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj); +u16 rtw_recv_select_queue(struct sk_buff *skb); +int rtw_ndev_notifier_register(void); +void rtw_ndev_notifier_unregister(void); + +u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj); +void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl); + +void rtw_ips_dev_unload(_adapter *padapter); + +int rtw_ips_pwr_up(_adapter *padapter); +void rtw_ips_pwr_down(_adapter *padapter); + + +void rtw_ndev_destructor(_nic_hdl ndev); + + +int rtw_suspend_common(_adapter *padapter); +int rtw_resume_common(_adapter *padapter); + +#endif /* _OSDEP_INTF_H_ */ diff --git a/drivers/staging/rtl8821ce/include/osdep_service.h b/drivers/staging/rtl8821ce/include/osdep_service.h new file mode 100644 index 000000000000..72fa97108baf --- /dev/null +++ b/drivers/staging/rtl8821ce/include/osdep_service.h @@ -0,0 +1,570 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __OSDEP_SERVICE_H_ +#define __OSDEP_SERVICE_H_ + +#define _FAIL 0 +#define _SUCCESS 1 +#define RTW_RX_HANDLED 2 +#define RTW_RFRAME_UNAVAIL 3 +#define RTW_RFRAME_PKT_UNAVAIL 4 +#define RTW_RBUF_UNAVAIL 5 +#define RTW_RBUF_PKT_UNAVAIL 6 +#define RTW_SDIO_READ_PORT_FAIL 7 + +/* #define RTW_STATUS_TIMEDOUT -110 */ + +#undef _TRUE +#define _TRUE 1 + +#undef _FALSE +#define _FALSE 0 + +#include <linux/version.h> +#include <linux/sched/signal.h> +#include <linux/sched/types.h> +#include <osdep_service_linux.h> + +#ifndef BIT + #define BIT(x) (1 << (x)) +#endif + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x0100000000 +#define BIT33 0x0200000000 +#define BIT34 0x0400000000 +#define BIT35 0x0800000000 +#define BIT36 0x1000000000 + +extern int RTW_STATUS_CODE(int error_code); + +/* flags used for rtw_mstat_update() */ +enum mstat_f { + /* type: 0x00ff */ + MSTAT_TYPE_VIR = 0x00, + MSTAT_TYPE_PHY = 0x01, + MSTAT_TYPE_SKB = 0x02, + MSTAT_TYPE_USB = 0x03, + MSTAT_TYPE_MAX = 0x04, + + /* func: 0xff00 */ + MSTAT_FUNC_UNSPECIFIED = 0x00 << 8, + MSTAT_FUNC_IO = 0x01 << 8, + MSTAT_FUNC_TX_IO = 0x02 << 8, + MSTAT_FUNC_RX_IO = 0x03 << 8, + MSTAT_FUNC_TX = 0x04 << 8, + MSTAT_FUNC_RX = 0x05 << 8, + MSTAT_FUNC_CFG_VENDOR = 0x06 << 8, + MSTAT_FUNC_MAX = 0x07 << 8, +}; + +#define mstat_tf_idx(flags) ((flags) & 0xff) +#define mstat_ff_idx(flags) (((flags) & 0xff00) >> 8) + +typedef enum mstat_status { + MSTAT_ALLOC_SUCCESS = 0, + MSTAT_ALLOC_FAIL, + MSTAT_FREE +} MSTAT_STATUS; + +#ifdef DBG_MEM_ALLOC +void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); +void rtw_mstat_dump(void *sel); +u8 *dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +u8 *dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); +u8 *dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +u8 *dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); + +struct sk_buff *dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); +int dbg_rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); +gro_result_t dbg_rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); +void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line); + +#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f) & 0xff00) | MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) + +#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f) & 0xff00) | MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_netif_receive_skb(ndev, skb) dbg_rtw_netif_receive_skb(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_napi_gro_receive(napi, skb) dbg_rtw_napi_gro_receive(napi, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) + +#else /* DBG_MEM_ALLOC */ +#define rtw_mstat_update(flag, status, sz) do {} while (0) +#define rtw_mstat_dump(sel) do {} while (0) +u8 *_rtw_vmalloc(u32 sz); +u8 *_rtw_zvmalloc(u32 sz); +void _rtw_vmfree(u8 *pbuf, u32 sz); +u8 *_rtw_zmalloc(u32 sz); +u8 *_rtw_malloc(u32 sz); +void _rtw_mfree(u8 *pbuf, u32 sz); + +struct sk_buff *_rtw_skb_alloc(u32 sz); +void _rtw_skb_free(struct sk_buff *skb); +struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb); +struct sk_buff *_rtw_skb_clone(struct sk_buff *skb); +int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb); +int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb); +gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb); +void _rtw_skb_queue_purge(struct sk_buff_head *list); + +#define rtw_vmalloc(sz) _rtw_vmalloc((sz)) +#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) +#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz)) +#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz)) +#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz)) +#define rtw_malloc(sz) _rtw_malloc((sz)) +#define rtw_zmalloc(sz) _rtw_zmalloc((sz)) +#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) +#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz)) +#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) +#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) + +#define rtw_skb_alloc(size) _rtw_skb_alloc((size)) +#define rtw_skb_free(skb) _rtw_skb_free((skb)) +#define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size)) +#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb)) +#define rtw_skb_copy(skb) _rtw_skb_copy((skb)) +#define rtw_skb_clone(skb) _rtw_skb_clone((skb)) +#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb)) +#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb)) +#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb) +#define rtw_netif_receive_skb(ndev, skb) _rtw_netif_receive_skb(ndev, skb) +#define rtw_napi_gro_receive(napi, skb) _rtw_napi_gro_receive(napi, skb) +#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head) +#endif /* DBG_MEM_ALLOC */ + +extern void *rtw_malloc2d(int h, int w, size_t size); +extern void rtw_mfree2d(void *pbuf, int h, int w, int size); + +extern void _rtw_memcpy(void *dec, const void *sour, u32 sz); +extern void _rtw_memmove(void *dst, const void *src, u32 sz); +extern int _rtw_memcmp(const void *dst, const void *src, u32 sz); +extern void _rtw_memset(void *pbuf, int c, u32 sz); + +extern void _rtw_init_listhead(_list *list); +extern u32 rtw_is_list_empty(_list *phead); +extern void rtw_list_insert_head(_list *plist, _list *phead); +extern void rtw_list_insert_tail(_list *plist, _list *phead); +#ifndef PLATFORM_FREEBSD +extern void rtw_list_delete(_list *plist); +#endif /* PLATFORM_FREEBSD */ + +extern void _rtw_init_sema(_sema *sema, int init_val); +extern void _rtw_free_sema(_sema *sema); +extern void _rtw_up_sema(_sema *sema); +extern u32 _rtw_down_sema(_sema *sema); +extern void _rtw_mutex_init(_mutex *pmutex); +extern void _rtw_mutex_free(_mutex *pmutex); +#ifndef PLATFORM_FREEBSD +extern void _rtw_spinlock_init(_lock *plock); +#endif /* PLATFORM_FREEBSD */ +extern void _rtw_spinlock_free(_lock *plock); +extern void _rtw_spinlock(_lock *plock); +extern void _rtw_spinunlock(_lock *plock); +extern void _rtw_spinlock_ex(_lock *plock); +extern void _rtw_spinunlock_ex(_lock *plock); + +extern void _rtw_init_queue(_queue *pqueue); +extern void _rtw_deinit_queue(_queue *pqueue); +extern u32 _rtw_queue_empty(_queue *pqueue); +extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement); + +extern u32 rtw_get_current_time(void); +extern u32 rtw_systime_to_ms(u32 systime); +extern u32 rtw_ms_to_systime(u32 ms); +extern s32 rtw_get_passing_time_ms(u32 start); +extern s32 rtw_get_time_interval_ms(u32 start, u32 end); + +extern void rtw_sleep_schedulable(int ms); + +extern void rtw_msleep_os(int ms); +extern void rtw_usleep_os(int us); + +extern u32 rtw_atoi(u8 *s); + +#ifdef DBG_DELAY_OS +#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__) +#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) +extern void _rtw_mdelay_os(int ms, const char *func, const int line); +extern void _rtw_udelay_os(int us, const char *func, const int line); +#else +extern void rtw_mdelay_os(int ms); +extern void rtw_udelay_os(int us); +#endif + +extern void rtw_yield_os(void); + +extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx); + +__inline static unsigned char _cancel_timer_ex(_timer *ptimer) +{ + u8 bcancelled; + + _cancel_timer(ptimer, &bcancelled); + + return bcancelled; +} + +static __inline void thread_enter(char *name) +{ + allow_signal(SIGTERM); +} +void thread_exit(_completion *comp); +void _rtw_init_completion(_completion *comp); +void _rtw_wait_for_comp_timeout(_completion *comp); +void _rtw_wait_for_comp(_completion *comp); +#define rtw_wait_for_thread_stop(_comp) _rtw_wait_for_comp_timeout(_comp) + +bool rtw_thread_stop(_thread_hdl_ th); +bool rtw_thread_should_stop(void); + +__inline static void flush_signals_thread(void) +{ + if (signal_pending(current)) + flush_signals(current); +} + +__inline static _OS_STATUS res_to_status(sint res) +{ + return res; +} + +__inline static void rtw_dump_stack(void) +{ + dump_stack(); +} + +#define rtw_warn_on(condition) WARN_ON(condition) + +__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4) +{ + return _TRUE; +} +#define RTW_DIV_ROUND_UP(n, d) DIV_ROUND_UP(n, d) + +#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) +#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0 : 1)) << 2) + +__inline static u32 _RND4(u32 sz) +{ + + u32 val; + + val = ((sz >> 2) + ((sz & 3) ? 1 : 0)) << 2; + + return val; + +} + +__inline static u32 _RND8(u32 sz) +{ + + u32 val; + + val = ((sz >> 3) + ((sz & 7) ? 1 : 0)) << 3; + + return val; + +} + +__inline static u32 _RND128(u32 sz) +{ + + u32 val; + + val = ((sz >> 7) + ((sz & 127) ? 1 : 0)) << 7; + + return val; + +} + +__inline static u32 _RND256(u32 sz) +{ + + u32 val; + + val = ((sz >> 8) + ((sz & 255) ? 1 : 0)) << 8; + + return val; + +} + +__inline static u32 _RND512(u32 sz) +{ + + u32 val; + + val = ((sz >> 9) + ((sz & 511) ? 1 : 0)) << 9; + + return val; + +} + +__inline static u32 bitshift(u32 bitmask) +{ + u32 i; + + for (i = 0; i <= 31; i++) + if (((bitmask >> i) & 0x1) == 1) + break; + + return i; +} + +static inline int largest_bit(u32 bitmask) +{ + int i; + + for (i = 31; i >= 0; i--) + if (bitmask & BIT(i)) + break; + + return i; +} + +#define rtw_min(a, b) ((a > b) ? b : a) +#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b))) +#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b))) + +#ifndef MAC_FMT +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#endif +#ifndef MAC_ARG +#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] +#endif + +extern void rtw_suspend_lock_init(void); +extern void rtw_suspend_lock_uninit(void); +extern void rtw_lock_suspend(void); +extern void rtw_unlock_suspend(void); +extern void rtw_lock_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_ext_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_rx_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_resume_scan_timeout(u32 timeout_ms); +extern void rtw_resume_lock_suspend(void); +extern void rtw_resume_unlock_suspend(void); + +extern void ATOMIC_SET(ATOMIC_T *v, int i); +extern int ATOMIC_READ(ATOMIC_T *v); +extern void ATOMIC_ADD(ATOMIC_T *v, int i); +extern void ATOMIC_SUB(ATOMIC_T *v, int i); +extern void ATOMIC_INC(ATOMIC_T *v); +extern void ATOMIC_DEC(ATOMIC_T *v); +extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); +extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); +extern int ATOMIC_INC_RETURN(ATOMIC_T *v); +extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); + +/* File operation APIs, just for linux now */ +extern int rtw_is_file_readable(const char *path); +extern int rtw_is_file_readable_with_size(const char *path, u32 *sz); +extern int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz); +extern int rtw_store_to_file(const char *path, u8 *buf, u32 sz); + +#ifndef PLATFORM_FREEBSD +extern void rtw_free_netdev(struct net_device *netdev); +#endif /* PLATFORM_FREEBSD */ + +extern u64 rtw_modular64(u64 x, u64 y); +extern u64 rtw_division64(u64 x, u64 y); +extern u32 rtw_random32(void); + +/* Macros for handling unaligned memory accesses */ + +#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1])) +#define RTW_PUT_BE16(a, val) \ + do { \ + (a)[0] = ((u16) (val)) >> 8; \ + (a)[1] = ((u16) (val)) & 0xff; \ + } while (0) + +#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0])) +#define RTW_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ + ((u32) (a)[2])) +#define RTW_PUT_BE24(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[2] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ + (((u32) (a)[2]) << 8) | ((u32) (a)[3])) +#define RTW_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \ + (((u32) (a)[1]) << 8) | ((u32) (a)[0])) +#define RTW_PUT_LE32(a, val) \ + do { \ + (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[0] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \ + (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \ + (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \ + (((u64) (a)[6]) << 8) | ((u64) (a)[7])) +#define RTW_PUT_BE64(a, val) \ + do { \ + (a)[0] = (u8) (((u64) (val)) >> 56); \ + (a)[1] = (u8) (((u64) (val)) >> 48); \ + (a)[2] = (u8) (((u64) (val)) >> 40); \ + (a)[3] = (u8) (((u64) (val)) >> 32); \ + (a)[4] = (u8) (((u64) (val)) >> 24); \ + (a)[5] = (u8) (((u64) (val)) >> 16); \ + (a)[6] = (u8) (((u64) (val)) >> 8); \ + (a)[7] = (u8) (((u64) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \ + (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ + (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ + (((u64) (a)[1]) << 8) | ((u64) (a)[0])) + +void rtw_buf_free(u8 **buf, u32 *buf_len); +void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); + +struct rtw_cbuf { + u32 write; + u32 read; + u32 size; + void *bufs[0]; +}; + +bool rtw_cbuf_full(struct rtw_cbuf *cbuf); +bool rtw_cbuf_empty(struct rtw_cbuf *cbuf); +bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf); +void *rtw_cbuf_pop(struct rtw_cbuf *cbuf); +struct rtw_cbuf *rtw_cbuf_alloc(u32 size); +void rtw_cbuf_free(struct rtw_cbuf *cbuf); + +struct map_seg_t { + u16 sa; + u16 len; + u8 *c; +}; + +struct map_t { + u16 len; + u16 seg_num; + u8 init_value; + struct map_seg_t *segs; +}; + +#define MAPSEG_ARRAY_ENT(_sa, _len, _c, arg...) \ + { .sa = _sa, .len = _len, .c = (u8[_len]){ _c, ##arg}, } + +#define MAPSEG_PTR_ENT(_sa, _len, _p) \ + { .sa = _sa, .len = _len, .c = _p, } + +#define MAP_ENT(_len, _seg_num, _init_v, _seg, arg...) \ + { .len = _len, .seg_num = _seg_num, .init_value = _init_v, .segs = (struct map_seg_t[_seg_num]){ _seg, ##arg}, } + +int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf); +u8 map_read8(const struct map_t *map, u16 offset); + +/* String handler */ + +BOOLEAN is_null(char c); +BOOLEAN is_all_null(char *c, int len); +BOOLEAN is_eol(char c); +BOOLEAN is_space(char c); +BOOLEAN IsHexDigit(char chTmp); +BOOLEAN is_alpha(char chTmp); +char alpha_to_upper(char c); + +/* + * Write formatted output to sized buffer + */ +#define rtw_sprintf(buf, size, format, arg...) snprintf(buf, size, format, ##arg) + +#endif diff --git a/drivers/staging/rtl8821ce/include/osdep_service_linux.h b/drivers/staging/rtl8821ce/include/osdep_service_linux.h new file mode 100644 index 000000000000..3b87948b88a6 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/osdep_service_linux.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __OSDEP_LINUX_SERVICE_H_ +#define __OSDEP_LINUX_SERVICE_H_ + +#include <linux/version.h> +#include <linux/spinlock.h> +#include <linux/compiler.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/kref.h> +#include <linux/netdevice.h> +#include <linux/skbuff.h> +#include <linux/circ_buf.h> +#include <asm/uaccess.h> +#include <asm/byteorder.h> +#include <asm/atomic.h> +#include <asm/io.h> +#include <linux/semaphore.h> +#include <linux/sem.h> +#include <linux/sched.h> +#include <linux/etherdevice.h> +#include <linux/wireless.h> +#include <net/iw_handler.h> +#include <linux/if_arp.h> +#include <linux/rtnetlink.h> +#include <linux/delay.h> +#include <linux/interrupt.h> /* for struct tasklet_struct */ +#include <linux/ip.h> +#include <linux/kthread.h> +#include <linux/list.h> +#include <linux/vmalloc.h> + +#include <uapi/linux/limits.h> + +/* Monitor mode */ +#include <net/ieee80211_radiotap.h> +#include <linux/ieee80211.h> +#include <linux/fs.h> + +typedef struct semaphore _sema; +typedef spinlock_t _lock; +typedef struct mutex _mutex; +struct rtw_timer_list { + struct timer_list timer; + void (*function)(void *); + void *arg; +}; + +typedef struct rtw_timer_list _timer; +typedef struct completion _completion; + +struct __queue { + struct list_head queue; + _lock lock; +}; + +typedef struct sk_buff _pkt; +typedef unsigned char _buffer; + +typedef struct __queue _queue; +typedef struct list_head _list; +typedef int _OS_STATUS; +/* typedef u32 _irqL; */ +typedef unsigned long _irqL; +typedef struct net_device *_nic_hdl; + +typedef void *_thread_hdl_; +typedef int thread_return; +typedef void *thread_context; + +typedef void timer_hdl_return; +typedef void *timer_hdl_context; + +typedef struct work_struct _workitem; + +__inline static _list *get_next(_list *list) +{ + return list->next; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return &(queue->queue); +} + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_lock_bh(plock); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_unlock_bh(plock); +} + +__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + int ret = 0; + ret = mutex_lock_interruptible(pmutex); + return ret; +} + +__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + mutex_unlock(pmutex); +} + +__inline static void rtw_list_delete(_list *plist) +{ + list_del_init(plist); +} + +static inline void timer_hdl(struct timer_list *in_timer) +{ + _timer *ptimer = from_timer(ptimer, in_timer, timer); + ptimer->function(ptimer->arg); +} + +__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx) +{ + ptimer->function = pfunc; + ptimer->arg = cntx; + timer_setup(&ptimer->timer, timer_hdl, 0); +} + +__inline static void _set_timer(_timer *ptimer, u32 delay_time) +{ + mod_timer(&ptimer->timer , (jiffies + (delay_time * HZ / 1000))); +} + +__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled) +{ + *bcancelled = del_timer_sync(&ptimer->timer) == 1 ? 1 : 0; +} + +static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) +{ + INIT_WORK(pwork, pfunc); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + schedule_work(pwork); +} + +__inline static void _cancel_workitem_sync(_workitem *pwork) +{ + cancel_work_sync(pwork); +} +/* + * Global Mutex: can only be used at PASSIVE level. + * */ + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ + { \ + while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1) { \ + atomic_dec((atomic_t *)&(_MutexCounter)); \ + msleep(10); \ + } \ + } + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ + { \ + atomic_dec((atomic_t *)&(_MutexCounter)); \ + } + +static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) +{ + return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3))); +} + +static inline void rtw_netif_wake_queue(struct net_device *pnetdev) +{ + netif_tx_wake_all_queues(pnetdev); +} + +static inline void rtw_netif_start_queue(struct net_device *pnetdev) +{ + netif_tx_start_all_queues(pnetdev); +} + +static inline void rtw_netif_stop_queue(struct net_device *pnetdev) +{ + netif_tx_stop_all_queues(pnetdev); +} +static inline void rtw_netif_carrier_on(struct net_device *pnetdev) +{ + netif_device_attach(pnetdev); + netif_carrier_on(pnetdev); +} +static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2) +{ + int len = 0; + len += snprintf(dst + len, dst_len - len, "%s", src1); + len += snprintf(dst + len, dst_len - len, "%s", src2); + + return len; +} + +#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)), (sig), 1) + +/* Suspend lock prevent system from going suspend */ + +/* limitation of path length */ +#define PATH_LENGTH_MAX PATH_MAX + +/* Atomic integer operations */ +#define ATOMIC_T atomic_t + +#define rtw_netdev_priv(netdev) (((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv) + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) ndev->name +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) (adapter->pnetdev ? adapter->pnetdev->name : NULL) +#define FUNC_NDEV_FMT "%s(%s)" +#define FUNC_NDEV_ARG(ndev) __func__, ndev->name +#define FUNC_ADPT_FMT "%s(%s)" +#define FUNC_ADPT_ARG(adapter) __func__, (adapter->pnetdev ? adapter->pnetdev->name : NULL) + +struct rtw_netdev_priv_indicator { + void *priv; + u32 sizeof_priv; +}; +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv); +extern struct net_device *rtw_alloc_etherdev(int sizeof_priv); + +#define STRUCT_PACKED __attribute__ ((packed)) + +#endif diff --git a/drivers/staging/rtl8821ce/include/pci_hal.h b/drivers/staging/rtl8821ce/include/pci_hal.h new file mode 100644 index 000000000000..0e9b8ae53081 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/pci_hal.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PCI_HAL_H__ +#define __PCI_HAL_H__ + +u8 rtw_set_hal_ops(_adapter *padapter); + +#endif /* __PCIE_HAL_H__ */ diff --git a/drivers/staging/rtl8821ce/include/pci_ops.h b/drivers/staging/rtl8821ce/include/pci_ops.h new file mode 100644 index 000000000000..901406549e9c --- /dev/null +++ b/drivers/staging/rtl8821ce/include/pci_ops.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PCI_OPS_H_ +#define __PCI_OPS_H_ + + void rtl8821ce_set_intf_ops(struct _io_ops *pops); + +#endif diff --git a/drivers/staging/rtl8821ce/include/pci_osintf.h b/drivers/staging/rtl8821ce/include/pci_osintf.h new file mode 100644 index 000000000000..4b1524d49035 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/pci_osintf.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PCI_OSINTF_H +#define __PCI_OSINTF_H + + +#define PCI_BC_CLK_REQ BIT0 +#define PCI_BC_ASPM_L0s BIT1 +#define PCI_BC_ASPM_L1 BIT2 +#define PCI_BC_ASPM_L1Off BIT3 +//#define PCI_BC_ASPM_LTR BIT4 +//#define PCI_BC_ASPM_OBFF BIT5 + +void rtw_pci_disable_aspm(_adapter *padapter); +void rtw_pci_enable_aspm(_adapter *padapter); +void PlatformClearPciPMEStatus(PADAPTER Adapter); +void rtw_pci_aspm_config(_adapter *padapter); +void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 eanble); + +#endif diff --git a/drivers/staging/rtl8821ce/include/recv_osdep.h b/drivers/staging/rtl8821ce/include/recv_osdep.h new file mode 100644 index 000000000000..d325235e9349 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/recv_osdep.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RECV_OSDEP_H_ +#define __RECV_OSDEP_H_ + +extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); +extern void _rtw_free_recv_priv(struct recv_priv *precvpriv); + +extern s32 rtw_recv_entry(union recv_frame *precv_frame); +extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); +extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt); + +extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame); + +extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame); + +struct sta_info; +extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup); + +int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter); +int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe); +void rtw_os_recv_resource_free(struct recv_priv *precvpriv); + +int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb); +int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb); +void rtw_os_free_recvframe(union recv_frame *precvframe); + +int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); +int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); + +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata); +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib); + +void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); + +#include <linux/netdevice.h> /* struct napi_struct */ + +int rtw_recv_napi_poll(struct napi_struct *, int budget); + +#endif /* */ diff --git a/drivers/staging/rtl8821ce/include/rtl8821c_dm.h b/drivers/staging/rtl8821ce/include/rtl8821c_dm.h new file mode 100644 index 000000000000..c4d9135e3fdd --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtl8821c_dm.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8812C_DM_H__ +#define __RTL8812C_DM_H__ + +void rtl8821c_phy_init_dm_priv(PADAPTER); +void rtl8821c_phy_deinit_dm_priv(PADAPTER p) {} +void rtl8821c_phy_init_haldm(PADAPTER); +void rtl8821c_phy_haldm_watchdog(PADAPTER); +void rtl8821c_phy_haldm_in_lps(PADAPTER); +void rtl8821c_phy_haldm_watchdog_in_lps(PADAPTER); + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtl8821c_hal.h b/drivers/staging/rtl8821ce/include/rtl8821c_hal.h new file mode 100644 index 000000000000..fcfc5977ccfd --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtl8821c_hal.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL8821C_HAL_H_ +#define _RTL8821C_HAL_H_ + +#include <osdep_service.h> /* BIT(x) */ +#include "../hal/halmac/halmac_api.h" /* MAC REG definition */ +#include "hal_data.h" +#include "rtl8821c_spec.h" +#include "../hal/rtl8821c/hal8821c_fw.h" + +#include <rtl8821ce_hal.h> + +#define RX_FIFO_EXPANDING 0 + +#define MAX_RECVBUF_SZ (4096 + RX_FIFO_EXPANDING) /* about 4K */ + +void init_hal_spec_rtl8821c(PADAPTER); +/* MP Functions */ +void rtl8821c_phy_init_haldm(PADAPTER); /* rtw_mp.c */ +void rtl8821c_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ +void rtl8821c_mp_config_rfpath(PADAPTER); /* hal_mp.c */ + +#endif /* _RTL8821C_HAL_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtl8821c_spec.h b/drivers/staging/rtl8821ce/include/rtl8821c_spec.h new file mode 100644 index 000000000000..f269ea27b67e --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtl8821c_spec.h @@ -0,0 +1,197 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#ifndef __RTL8821C_SPEC_H__ +#define __RTL8821C_SPEC_H__ + +#define EFUSE_MAP_SIZE HALMAC_EFUSE_SIZE_8821C + +/* + * MAC Register definition + */ +#define REG_AFE_XTAL_CTRL REG_AFE_CTRL1_8821C /* hal_com.c & phydm */ +#define REG_AFE_PLL_CTRL REG_AFE_CTRL2_8821C /* hal_com.c & phydm */ +#define REG_MAC_PHY_CTRL REG_AFE_CTRL3_8821C /* phydm only */ +#define REG_LEDCFG0 REG_LED_CFG_8821C /* rtw_mp.c */ +#define MSR (REG_CR_8821C + 2) /* rtw_mp.c */ +#define MSR1 REG_CR_EXT_8821C /* rtw_mp.c & hal_com.c */ +#define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ +#define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ +#define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8821C/* hal_com.c */ +#define REG_TSFTR1 REG_FREERUN_CNT_8821C /* hal_com.c */ +#define REG_RXFLTMAP2 REG_RXFLTMAP_8821C /* rtw_mp.c */ +#define REG_WOWLAN_WAKE_REASON 0x01C7 +#define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8821C + +/* RXERR_RPT, for rtw_mp.c */ +#define RXERR_TYPE_OFDM_PPDU 0 +#define RXERR_TYPE_OFDM_FALSE_ALARM 2 +#define RXERR_TYPE_OFDM_MPDU_OK 0 +#define RXERR_TYPE_OFDM_MPDU_FAIL 1 +#define RXERR_TYPE_CCK_PPDU 3 +#define RXERR_TYPE_CCK_FALSE_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 3 +#define RXERR_TYPE_CCK_MPDU_FAIL 4 +#define RXERR_TYPE_HT_PPDU 8 +#define RXERR_TYPE_HT_FALSE_ALARM 9 +#define RXERR_TYPE_HT_MPDU_TOTAL 6 +#define RXERR_TYPE_HT_MPDU_OK 6 +#define RXERR_TYPE_HT_MPDU_FAIL 7 +#define RXERR_TYPE_RX_FULL_DROP 10 + +#define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8821C +#define RXERR_RPT_RST BIT_RXERR_RPT_RST_8821C +#define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8821C(type) \ + | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8821C : 0)) + +/* + * BB Register definition + */ +#define rPMAC_Reset 0x100 /* hal_mp.c */ + +#define rFPGA0_RFMOD 0x800 +#define rFPGA0_TxInfo 0x804 +#define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ +#define rFPGA0_TxGainStage 0x80C /* phydm only */ +#define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ +#define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ +#define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ +#define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ +#define rTxAGC_B_Mcs03_Mcs00 0x83C +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84C +#define rFPGA0_XA_RFInterfaceOE 0x860 +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86C +#define rFPGA0_XAB_RFInterfaceSW 0x870 +#define rFPGA0_XAB_RFParameter 0x878 +#define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ +#define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ +#define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8821c_phy.c) */ + +#define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ +#define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ + +#define rFPGA1_TxInfo 0x90C /* hal_mp.c */ +#define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ + +#define rCCK0_System 0xA00 +#define rCCK0_AFESetting 0xA04 + +#define rCCK0_DSPParameter2 0xA1C +#define rCCK0_TxFilter1 0xA20 +#define rCCK0_TxFilter2 0xA24 +#define rCCK0_DebugPort 0xA28 +#define rCCK0_FalseAlarmReport 0xA2C + +#define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ +#define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ + +#define rOFDM0_TRxPathEnable 0xC04 +#define rOFDM0_TRMuxPar 0xC08 +#define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ +#define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ +#define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ +#define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ +#define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ +#define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ +#define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ +#define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ +#define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ + +#define rOFDM1_LSTF 0xD00 +#define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ +#define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8821c_phy.c) */ +#define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8821c_phy.c) */ +#define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8821c_phy.c) */ +#define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8821c_phy.c) */ + +#define rTxAGC_A_Rate18_06 0xE00 +#define rTxAGC_A_Rate54_24 0xE04 +#define rTxAGC_A_CCK1_Mcs32 0xE08 +#define rTxAGC_A_Mcs03_Mcs00 0xE10 +#define rTxAGC_A_Mcs07_Mcs04 0xE14 +#define rTxAGC_A_Mcs11_Mcs08 0xE18 +#define rTxAGC_A_Mcs15_Mcs12 0xE1C +#define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ +#define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ +#define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8821c_phy.c) */ +#define rB_RFE_Pinmux_Jaguar 0xEB0 /* hal_mp.c */ + +/* Page1(0x100) */ +#define bBBResetB 0x100 + +/* Page8(0x800) */ +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 +/* Reg 0x80C rFPGA0_TxGainStage */ +#define bXBTxAGC 0xF00 +#define bXCTxAGC 0xF000 +#define bXDTxAGC 0xF0000 + +/* PageA(0xA00) */ +#define bCCKBBMode 0x3 + +#define bCCKScramble 0x8 +#define bCCKTxRate 0x3000 + +/* General */ +#define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ +#define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ +#define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ +#define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ +#define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ +#define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ +#define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ + +#define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ +#define bDisable 0x0 /* rtw_mp.c */ + +#define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ + +#define Rx_Smooth_Factor 20 /* phydm only */ + +/* + * RF Register definition + */ +#define RF_AC 0x00 +#define RF_AC_Jaguar 0x00 /* hal_mp.c */ +#define RF_CHNLBW 0x18 /* rtl8821c_phy.c */ +#define RF_0x52 0x52 + +struct hw_port_reg { + u32 net_type; /*reg_offset*/ + u8 net_type_shift; + u32 macaddr; /*reg_offset*/ + u32 bssid; /*reg_offset*/ + u32 bcn_ctl; /*reg_offset*/ + u32 tsf_rst; /*reg_offset*/ + u8 tsf_rst_bit; + u32 bcn_space; /*reg_offset*/ + u8 bcn_space_shift; + u16 bcn_space_mask; + u32 ps_aid; /*reg_offset*/ +}; + +#endif /* __RTL8192E_SPEC_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtl8821ce_hal.h b/drivers/staging/rtl8821ce/include/rtl8821ce_hal.h new file mode 100644 index 000000000000..870f08313154 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtl8821ce_hal.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL8821CE_HAL_H_ +#define _RTL8821CE_HAL_H_ + +#include <drv_types.h> /* PADAPTER */ + +/* rtl8821ce_ops.c */ +void rtl8821ce_set_hal_ops(PADAPTER); + +#endif /* _RTL8821CE_HAL_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_android.h b/drivers/staging/rtl8821ce/include/rtw_android.h new file mode 100644 index 000000000000..775bb54ba3e5 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_android.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __RTW_ANDROID_H__ +#define __RTW_ANDROID_H__ + +enum ANDROID_WIFI_CMD { + ANDROID_WIFI_CMD_START, + ANDROID_WIFI_CMD_STOP, + ANDROID_WIFI_CMD_SCAN_ACTIVE, + ANDROID_WIFI_CMD_SCAN_PASSIVE, + ANDROID_WIFI_CMD_RSSI, + ANDROID_WIFI_CMD_LINKSPEED, + ANDROID_WIFI_CMD_RXFILTER_START, + ANDROID_WIFI_CMD_RXFILTER_STOP, + ANDROID_WIFI_CMD_RXFILTER_ADD, + ANDROID_WIFI_CMD_RXFILTER_REMOVE, + ANDROID_WIFI_CMD_BTCOEXSCAN_START, + ANDROID_WIFI_CMD_BTCOEXSCAN_STOP, + ANDROID_WIFI_CMD_BTCOEXMODE, + ANDROID_WIFI_CMD_SETSUSPENDOPT, + ANDROID_WIFI_CMD_P2P_DEV_ADDR, + ANDROID_WIFI_CMD_SETFWPATH, + ANDROID_WIFI_CMD_SETBAND, + ANDROID_WIFI_CMD_GETBAND, + ANDROID_WIFI_CMD_COUNTRY, + ANDROID_WIFI_CMD_P2P_SET_NOA, + ANDROID_WIFI_CMD_P2P_GET_NOA, + ANDROID_WIFI_CMD_P2P_SET_PS, + ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE, + + ANDROID_WIFI_CMD_MIRACAST, + + + ANDROID_WIFI_CMD_MACADDR, + + ANDROID_WIFI_CMD_BLOCK_SCAN, + ANDROID_WIFI_CMD_BLOCK, + + ANDROID_WIFI_CMD_WFD_ENABLE, + ANDROID_WIFI_CMD_WFD_DISABLE, + + ANDROID_WIFI_CMD_WFD_SET_TCPPORT, + ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT, + ANDROID_WIFI_CMD_WFD_SET_DEVTYPE, + ANDROID_WIFI_CMD_CHANGE_DTIM, + ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL, + ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA, + ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA, + ANDROID_WIFI_CMD_P2P_DISABLE, + ANDROID_WIFI_CMD_DRIVERVERSION, + ANDROID_WIFI_CMD_MAX +}; + +int rtw_android_cmdstr_to_num(char *cmdstr); +int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd); + +#endif /* __RTW_ANDROID_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_ap.h b/drivers/staging/rtl8821ce/include/rtw_ap.h new file mode 100644 index 000000000000..8690b4e5e501 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_ap.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_AP_H_ +#define __RTW_AP_H_ + + +/* external function */ +extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta); +extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta); + +void init_mlme_ap_info(_adapter *padapter); +void free_mlme_ap_info(_adapter *padapter); +/* void update_BCNTIM(_adapter *padapter); */ +void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); +void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); +void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag); +#define update_beacon(adapter, ie_id, oui, tx) _update_beacon((adapter), (ie_id), (oui), (tx), __func__) +void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level, u8 is_update_bw); +void expire_timeout_chk(_adapter *padapter); +void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); +void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter); +void start_bss_network(_adapter *padapter, struct createbss_parm *parm); +int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); +void rtw_ap_restore_network(_adapter *padapter); + +void rtw_set_macaddr_acl(_adapter *adapter, int mode); +int rtw_acl_add_sta(_adapter *adapter, const u8 *addr); +int rtw_acl_remove_sta(_adapter *adapter, const u8 *addr); + +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta); +int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid); +int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx); + +void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type); +void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta); +u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta); +void sta_info_update(_adapter *padapter, struct sta_info *psta); +void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue); +int rtw_sta_flush(_adapter *padapter, bool enqueue); +int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset); +void start_ap_mode(_adapter *padapter); +void stop_ap_mode(_adapter *padapter); + +void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset); +bool rtw_ap_chbw_decision(_adapter *adapter, s16 req_ch, s8 req_bw, s8 req_offset, u8 *ch, u8 *bw, u8 *offset, u8 *chbw_allow); + + + +#endif +void update_bmc_sta(_adapter *padapter); + +void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field); +void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len); +int rtw_ht_operation_update(_adapter *padapter); + diff --git a/drivers/staging/rtl8821ce/include/rtw_beamforming.h b/drivers/staging/rtl8821ce/include/rtw_beamforming.h new file mode 100644 index 000000000000..a34c2347d7dc --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_beamforming.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2016 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_BEAMFORMING_H_ +#define __RTW_BEAMFORMING_H_ + + +#endif /*__RTW_BEAMFORMING_H_*/ diff --git a/drivers/staging/rtl8821ce/include/rtw_br_ext.h b/drivers/staging/rtl8821ce/include/rtw_br_ext.h new file mode 100644 index 000000000000..abce7042ae00 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_br_ext.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_BR_EXT_H_ +#define _RTW_BR_EXT_H_ + +#define MACADDRLEN 6 +#define _DEBUG_ERR RTW_INFO +#define _DEBUG_INFO /* RTW_INFO */ +#define DEBUG_WARN RTW_INFO +#define DEBUG_INFO /* RTW_INFO */ +#define DEBUG_ERR RTW_INFO +/* #define GET_MY_HWADDR ((GET_MIB(priv))->dot11OperationEntry.hwaddr) */ +#define GET_MY_HWADDR(padapter) (adapter_mac_addr(padapter)) + +#define NAT25_HASH_BITS 4 +#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS) +#define NAT25_AGEING_TIME 300 + + #define MAX_NETWORK_ADDR_LEN 17 + +struct nat25_network_db_entry { + struct nat25_network_db_entry *next_hash; + struct nat25_network_db_entry **pprev_hash; + atomic_t use_count; + unsigned char macAddr[6]; + unsigned long ageing_timer; + unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; +}; + +enum NAT25_METHOD { + NAT25_MIN, + NAT25_CHECK, + NAT25_INSERT, + NAT25_LOOKUP, + NAT25_PARSE, + NAT25_MAX +}; + +struct br_ext_info { + unsigned int nat25_disable; + unsigned int macclone_enable; + unsigned int dhcp_bcst_disable; + int addPPPoETag; /* 1: Add PPPoE relay-SID, 0: disable */ + unsigned char nat25_dmzMac[MACADDRLEN]; + unsigned int nat25sc_disable; +}; + +void nat25_db_cleanup(_adapter *priv); + +#endif /* _RTW_BR_EXT_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_bt_mp.h b/drivers/staging/rtl8821ce/include/rtw_bt_mp.h new file mode 100644 index 000000000000..1229b8ddaacd --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_bt_mp.h @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __RTW_BT_MP_H +#define __RTW_BT_MP_H + + +#pragma pack(1) + +/* definition for BT_UP_OP_BT_READY */ +#define MP_BT_NOT_READY 0 +#define MP_BT_READY 1 + +/* definition for BT_UP_OP_BT_SET_MODE */ +typedef enum _MP_BT_MODE { + MP_BT_MODE_RF_TXRX_TEST_MODE = 0, + MP_BT_MODE_BT20_DUT_TEST_MODE = 1, + MP_BT_MODE_BT40_DIRECT_TEST_MODE = 2, + MP_BT_MODE_CONNECT_TEST_MODE = 3, + MP_BT_MODE_MAX +} MP_BT_MODE, *PMP_BT_MODE; + +/* definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER */ +typedef struct _BT_TXRX_PARAMETERS { + u1Byte txrxChannel; + u4Byte txrxTxPktCnt; + u1Byte txrxTxPktInterval; + u1Byte txrxPayloadType; + u1Byte txrxPktType; + u2Byte txrxPayloadLen; + u4Byte txrxPktHeader; + u1Byte txrxWhitenCoeff; + u1Byte txrxBdaddr[6]; + u1Byte txrxTxGainIndex; +} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS; + +/* txrxPktType */ +typedef enum _MP_BT_PKT_TYPE { + MP_BT_PKT_DH1 = 0, + MP_BT_PKT_DH3 = 1, + MP_BT_PKT_DH5 = 2, + MP_BT_PKT_2DH1 = 3, + MP_BT_PKT_2DH3 = 4, + MP_BT_PKT_2DH5 = 5, + MP_BT_PKT_3DH1 = 6, + MP_BT_PKT_3DH3 = 7, + MP_BT_PKT_3DH5 = 8, + MP_BT_PKT_LE = 9, + MP_BT_PKT_MAX +} MP_BT_PKT_TYPE, *PMP_BT_PKT_TYPE; +/* txrxPayloadType */ +typedef enum _MP_BT_PAYLOAD_TYPE { + MP_BT_PAYLOAD_01010101 = 0, + MP_BT_PAYLOAD_ALL_1 = 1, + MP_BT_PAYLOAD_ALL_0 = 2, + MP_BT_PAYLOAD_11110000 = 3, + MP_BT_PAYLOAD_PRBS9 = 4, + MP_BT_PAYLOAD_MAX = 8, +} MP_BT_PAYLOAD_TYPE, *PMP_BT_PAYLOAD_TYPE; + +/* definition for BT_UP_OP_BT_TEST_CTRL */ +typedef enum _MP_BT_TEST_CTRL { + MP_BT_TEST_STOP_ALL_TESTS = 0, + MP_BT_TEST_START_RX_TEST = 1, + MP_BT_TEST_START_PACKET_TX_TEST = 2, + MP_BT_TEST_START_CONTINUOUS_TX_TEST = 3, + MP_BT_TEST_START_INQUIRY_SCAN_TEST = 4, + MP_BT_TEST_START_PAGE_SCAN_TEST = 5, + MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST = 6, + MP_BT_TEST_START_LEGACY_CONNECT_TEST = 7, + MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR = 8, + MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER = 9, + MP_BT_TEST_MAX +} MP_BT_TEST_CTRL, *PMP_BT_TEST_CTRL; + +typedef enum _RTL_EXT_C2H_EVT { + EXT_C2H_WIFI_FW_ACTIVE_RSP = 0, + EXT_C2H_TRIG_BY_BT_FW = 1, + MAX_EXT_C2HEVENT +} RTL_EXT_C2H_EVT; + +/* OP codes definition between the user layer and driver */ +typedef enum _BT_CTRL_OPCODE_UPPER { + BT_UP_OP_BT_READY = 0x00, + BT_UP_OP_BT_SET_MODE = 0x01, + BT_UP_OP_BT_SET_TX_RX_PARAMETER = 0x02, + BT_UP_OP_BT_SET_GENERAL = 0x03, + BT_UP_OP_BT_GET_GENERAL = 0x04, + BT_UP_OP_BT_TEST_CTRL = 0x05, + BT_UP_OP_TEST_BT = 0x06, + BT_UP_OP_MAX +} BT_CTRL_OPCODE_UPPER, *PBT_CTRL_OPCODE_UPPER; + +typedef enum _BT_SET_GENERAL { + BT_GSET_REG = 0x00, + BT_GSET_RESET = 0x01, + BT_GSET_TARGET_BD_ADDR = 0x02, + BT_GSET_TX_PWR_FINETUNE = 0x03, + BT_SET_TRACKING_INTERVAL = 0x04, + BT_SET_THERMAL_METER = 0x05, + BT_ENABLE_CFO_TRACKING = 0x06, + BT_GSET_UPDATE_BT_PATCH = 0x07, + BT_GSET_MAX +} BT_SET_GENERAL, *PBT_SET_GENERAL; + +typedef enum _BT_GET_GENERAL { + BT_GGET_REG = 0x00, + BT_GGET_STATUS = 0x01, + BT_GGET_REPORT = 0x02, + BT_GGET_AFH_MAP = 0x03, + BT_GGET_AFH_STATUS = 0x04, + BT_GGET_MAX +} BT_GET_GENERAL, *PBT_GET_GENERAL; + +/* definition for BT_UP_OP_BT_SET_GENERAL */ +typedef enum _BT_REG_TYPE { + BT_REG_RF = 0, + BT_REG_MODEM = 1, + BT_REG_BLUEWIZE = 2, + BT_REG_VENDOR = 3, + BT_REG_LE = 4, + BT_REG_MAX +} BT_REG_TYPE, *PBT_REG_TYPE; + +/* definition for BT_LO_OP_GET_AFH_MAP */ +typedef enum _BT_AFH_MAP_TYPE { + BT_AFH_MAP_RESULT = 0, + BT_AFH_MAP_WIFI_PSD_ONLY = 1, + BT_AFH_MAP_WIFI_CH_BW_ONLY = 2, + BT_AFH_MAP_BT_PSD_ONLY = 3, + BT_AFH_MAP_HOST_CLASSIFICATION_ONLY = 4, + BT_AFH_MAP_MAX +} BT_AFH_MAP_TYPE, *PBT_AFH_MAP_TYPE; + +/* definition for BT_UP_OP_BT_GET_GENERAL */ +typedef enum _BT_REPORT_TYPE { + BT_REPORT_RX_PACKET_CNT = 0, + BT_REPORT_RX_ERROR_BITS = 1, + BT_REPORT_RSSI = 2, + BT_REPORT_CFO_HDR_QUALITY = 3, + BT_REPORT_CONNECT_TARGET_BD_ADDR = 4, + BT_REPORT_MAX +} BT_REPORT_TYPE, *PBT_REPORT_TYPE; + +VOID +MPTBT_Test( + IN PADAPTER Adapter, + IN u1Byte opCode, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3 +); + +NDIS_STATUS +MPTBT_SendOidBT( + IN PADAPTER pAdapter, + IN PVOID InformationBuffer, + IN ULONG InformationBufferLength, + OUT PULONG BytesRead, + OUT PULONG BytesNeeded +); + +VOID +MPTBT_FwC2hBtMpCtrl( + PADAPTER Adapter, + pu1Byte tmpBuf, + u1Byte length +); + +void MPh2c_timeout_handle(void *FunctionContext); + +VOID mptbt_BtControlProcess( + PADAPTER Adapter, + PVOID pInBuf +); + +#define BT_H2C_MAX_RETRY 1 +#define BT_MAX_C2H_LEN 20 + +typedef struct _BT_REQ_CMD { + UCHAR opCodeVer; + UCHAR OpCode; + USHORT paraLength; + UCHAR pParamStart[100]; +} BT_REQ_CMD, *PBT_REQ_CMD; + +typedef struct _BT_RSP_CMD { + USHORT status; + USHORT paraLength; + UCHAR pParamStart[100]; +} BT_RSP_CMD, *PBT_RSP_CMD; + +typedef struct _BT_H2C { + u1Byte opCodeVer:4; + u1Byte reqNum:4; + u1Byte opCode; + u1Byte buf[100]; +} BT_H2C, *PBT_H2C; + +typedef struct _BT_EXT_C2H { + u1Byte extendId; + u1Byte statusCode:4; + u1Byte retLen:4; + u1Byte opCodeVer:4; + u1Byte reqNum:4; + u1Byte buf[100]; +} BT_EXT_C2H, *PBT_EXT_C2H; + +typedef enum _BT_OPCODE_STATUS { + BT_OP_STATUS_SUCCESS = 0x00, /* Success */ + BT_OP_STATUS_VERSION_MISMATCH = 0x01, + BT_OP_STATUS_UNKNOWN_OPCODE = 0x02, + BT_OP_STATUS_ERROR_PARAMETER = 0x03, + BT_OP_STATUS_MAX +} BT_OPCODE_STATUS, *PBT_OPCODE_STATUS; + +/* OP codes definition between driver and bt fw */ +typedef enum _BT_CTRL_OPCODE_LOWER { + BT_LO_OP_GET_BT_VERSION = 0x00, + BT_LO_OP_RESET = 0x01, + BT_LO_OP_TEST_CTRL = 0x02, + BT_LO_OP_SET_BT_MODE = 0x03, + BT_LO_OP_SET_CHNL_TX_GAIN = 0x04, + BT_LO_OP_SET_PKT_TYPE_LEN = 0x05, + BT_LO_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, + BT_LO_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, + BT_LO_OP_SET_PKT_HEADER = 0x08, + BT_LO_OP_SET_WHITENCOEFF = 0x09, + BT_LO_OP_SET_BD_ADDR_L = 0x0a, + BT_LO_OP_SET_BD_ADDR_H = 0x0b, + BT_LO_OP_WRITE_REG_ADDR = 0x0c, + BT_LO_OP_WRITE_REG_VALUE = 0x0d, + BT_LO_OP_GET_BT_STATUS = 0x0e, + BT_LO_OP_GET_BD_ADDR_L = 0x0f, + BT_LO_OP_GET_BD_ADDR_H = 0x10, + BT_LO_OP_READ_REG = 0x11, + BT_LO_OP_SET_TARGET_BD_ADDR_L = 0x12, + BT_LO_OP_SET_TARGET_BD_ADDR_H = 0x13, + BT_LO_OP_SET_TX_POWER_CALIBRATION = 0x14, + BT_LO_OP_GET_RX_PKT_CNT_L = 0x15, + BT_LO_OP_GET_RX_PKT_CNT_H = 0x16, + BT_LO_OP_GET_RX_ERROR_BITS_L = 0x17, + BT_LO_OP_GET_RX_ERROR_BITS_H = 0x18, + BT_LO_OP_GET_RSSI = 0x19, + BT_LO_OP_GET_CFO_HDR_QUALITY_L = 0x1a, + BT_LO_OP_GET_CFO_HDR_QUALITY_H = 0x1b, + BT_LO_OP_GET_TARGET_BD_ADDR_L = 0x1c, + BT_LO_OP_GET_TARGET_BD_ADDR_H = 0x1d, + BT_LO_OP_GET_AFH_MAP_L = 0x1e, + BT_LO_OP_GET_AFH_MAP_M = 0x1f, + BT_LO_OP_GET_AFH_MAP_H = 0x20, + BT_LO_OP_GET_AFH_STATUS = 0x21, + BT_LO_OP_SET_TRACKING_INTERVAL = 0x22, + BT_LO_OP_SET_THERMAL_METER = 0x23, + BT_LO_OP_ENABLE_CFO_TRACKING = 0x24, + BT_LO_OP_MAX +} BT_CTRL_OPCODE_LOWER, *PBT_CTRL_OPCODE_LOWER; + + +#endif /* #ifndef __INC_MPT_BT_H */ diff --git a/drivers/staging/rtl8821ce/include/rtw_btcoex.h b/drivers/staging/rtl8821ce/include/rtw_btcoex.h new file mode 100644 index 000000000000..b01777a70ec4 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_btcoex.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_BTCOEX_H__ +#define __RTW_BTCOEX_H__ + +#include <drv_types.h> + +/* For H2C: H2C_BT_MP_OPER. Return status definition to the user layer */ +typedef enum _BT_CTRL_STATUS { + BT_STATUS_SUCCESS = 0x00, /* Success */ + BT_STATUS_BT_OP_SUCCESS = 0x01, /* bt fw op execution success */ + BT_STATUS_H2C_SUCCESS = 0x02, /* H2c success */ + BT_STATUS_H2C_FAIL = 0x03, /* H2c fail */ + BT_STATUS_H2C_LENGTH_EXCEEDED = 0x04, /* H2c command length exceeded */ + BT_STATUS_H2C_TIMTOUT = 0x05, /* H2c timeout */ + BT_STATUS_H2C_BT_NO_RSP = 0x06, /* H2c sent, bt no rsp */ + BT_STATUS_C2H_SUCCESS = 0x07, /* C2h success */ + BT_STATUS_C2H_REQNUM_MISMATCH = 0x08, /* bt fw wrong rsp */ + BT_STATUS_OPCODE_U_VERSION_MISMATCH = 0x08, /* Upper layer OP code version mismatch. */ + BT_STATUS_OPCODE_L_VERSION_MISMATCH = 0x0a, /* Lower layer OP code version mismatch. */ + BT_STATUS_UNKNOWN_OPCODE_U = 0x0b, /* Unknown Upper layer OP code */ + BT_STATUS_UNKNOWN_OPCODE_L = 0x0c, /* Unknown Lower layer OP code */ + BT_STATUS_PARAMETER_FORMAT_ERROR_U = 0x0d, /* Wrong parameters sent by upper layer. */ + BT_STATUS_PARAMETER_FORMAT_ERROR_L = 0x0e, /* bt fw parameter format is not consistency */ + BT_STATUS_PARAMETER_OUT_OF_RANGE_U = 0x0f, /* uppery layer parameter value is out of range */ + BT_STATUS_PARAMETER_OUT_OF_RANGE_L = 0x10, /* bt fw parameter value is out of range */ + BT_STATUS_UNKNOWN_STATUS_L = 0x11, /* bt returned an defined status code */ + BT_STATUS_UNKNOWN_STATUS_H = 0x12, /* driver need to do error handle or not handle-well. */ + BT_STATUS_WRONG_LEVEL = 0x13, /* should be under passive level */ + BT_STATUS_NOT_IMPLEMENT = 0x14, /* op code not implemented yet */ + BT_STATUS_BT_STACK_OP_SUCCESS = 0x15, /* bt stack op execution success */ + BT_STATUS_BT_STACK_NOT_SUPPORT = 0x16, /* stack version not support this. */ + BT_STATUS_BT_STACK_SEND_HCI_EVENT_FAIL = 0x17, /* send hci event fail */ + BT_STATUS_BT_STACK_NOT_BIND = 0x18, /* stack not bind wifi driver */ + BT_STATUS_BT_STACK_NO_RSP = 0x19, /* stack doesn't have any rsp. */ + BT_STATUS_MAX +} BT_CTRL_STATUS, *PBT_CTRL_STATUS; + +typedef enum _BTCOEX_SUSPEND_STATE { + BTCOEX_SUSPEND_STATE_RESUME = 0x0, + BTCOEX_SUSPEND_STATE_SUSPEND = 0x1, + BTCOEX_SUSPEND_STATE_SUSPEND_KEEP_ANT = 0x2, + BTCOEX_SUSPEND_STATE_MAX +} BTCOEX_SUSPEND_STATE, *PBTCOEX_SUSPEND_STATE; + +#define SET_BT_MP_OPER_RET(OpCode, StatusCode) ((OpCode << 8) | StatusCode) +#define GET_OP_CODE_FROM_BT_MP_OPER_RET(RetCode) ((RetCode & 0xF0) >> 8) +#define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) (RetCode & 0x0F) +#define CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode, StatusCode) (GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) == StatusCode) + +#define PACKET_NORMAL 0 +#define PACKET_DHCP 1 +#define PACKET_ARP 2 +#define PACKET_EAPOL 3 + +void rtw_btcoex_Initialize(PADAPTER); +void rtw_btcoex_PowerOnSetting(PADAPTER padapter); +void rtw_btcoex_PowerOffSetting(PADAPTER padapter); +void rtw_btcoex_PreLoadFirmware(PADAPTER padapter); +void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly); +void rtw_btcoex_IpsNotify(PADAPTER, u8 type); +void rtw_btcoex_LpsNotify(PADAPTER, u8 type); +void rtw_btcoex_ScanNotify(PADAPTER, u8 type); +void rtw_btcoex_ConnectNotify(PADAPTER, u8 action); +void rtw_btcoex_MediaStatusNotify(PADAPTER, u8 mediaStatus); +void rtw_btcoex_SpecialPacketNotify(PADAPTER, u8 pktType); +void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state); +void rtw_btcoex_BtInfoNotify(PADAPTER, u8 length, u8 *tmpBuf); +void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf); +void rtw_btcoex_SuspendNotify(PADAPTER, u8 state); +void rtw_btcoex_HaltNotify(PADAPTER); +void rtw_btcoex_switchband_notify(u8 under_scan, u8 band_type); +void rtw_btcoex_SwitchBtTRxMask(PADAPTER); +void rtw_btcoex_Switch(PADAPTER, u8 enable); +u8 rtw_btcoex_IsBtDisabled(PADAPTER); +void rtw_btcoex_Handler(PADAPTER); +s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter); +s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER); +u32 rtw_btcoex_GetAMPDUSize(PADAPTER); +void rtw_btcoex_SetManualControl(PADAPTER, u8 bmanual); +u8 rtw_btcoex_1Ant(PADAPTER); +u8 rtw_btcoex_IsBtControlLps(PADAPTER); +u8 rtw_btcoex_IsLpsOn(PADAPTER); +u8 rtw_btcoex_RpwmVal(PADAPTER); +u8 rtw_btcoex_LpsVal(PADAPTER); +u32 rtw_btcoex_GetRaMask(PADAPTER); +void rtw_btcoex_RecordPwrMode(PADAPTER, u8 *pCmdBuf, u8 cmdLen); +void rtw_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize); +void rtw_btcoex_SetDBG(PADAPTER, u32 *pDbgModule); +u32 rtw_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize); +u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER); +u8 rtw_btcoex_IsBtLinkExist(PADAPTER); +void rtw_btcoex_pta_off_on_notify(PADAPTER padapter, u8 bBTON); + +u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); +u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); +u8 rtw_btcoex_get_bt_coexist(PADAPTER padapter); +u8 rtw_btcoex_get_chip_type(PADAPTER padapter); +u8 rtw_btcoex_get_pg_ant_num(PADAPTER padapter); +u8 rtw_btcoex_get_pg_single_ant_path(PADAPTER padapter); +u8 rtw_btcoex_get_pg_rfe_type(PADAPTER padapter); +u8 rtw_btcoex_is_tfbga_package_type(PADAPTER padapter); +u8 rtw_btcoex_get_ant_div_cfg(PADAPTER padapter); + +/* ================================================== + * Below Functions are called by BT-Coex + * ================================================== */ +void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter); +void rtw_btcoex_LPS_Enter(PADAPTER padapter); +u8 rtw_btcoex_LPS_Leave(PADAPTER padapter); + +#endif /* __RTW_BTCOEX_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_btcoex_wifionly.h b/drivers/staging/rtl8821ce/include/rtw_btcoex_wifionly.h new file mode 100644 index 000000000000..ddbb82f0869f --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_btcoex_wifionly.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_BTCOEX_WIFIONLY_H__ +#define __RTW_BTCOEX_WIFIONLY_H__ + +void rtw_btcoex_wifionly_switchband_notify(PADAPTER padapter); +void rtw_btcoex_wifionly_scan_notify(PADAPTER padapter); +void rtw_btcoex_wifionly_hw_config(PADAPTER padapter); +void rtw_btcoex_wifionly_initialize(PADAPTER padapter); +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_byteorder.h b/drivers/staging/rtl8821ce/include/rtw_byteorder.h new file mode 100644 index 000000000000..672abc69c1ab --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_byteorder.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL871X_BYTEORDER_H_ +#define _RTL871X_BYTEORDER_H_ + +#if defined(CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN) + #error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n" +#endif + +#if defined(CONFIG_LITTLE_ENDIAN) + #include <linux/byteorder/little_endian.h> +#elif defined (CONFIG_BIG_ENDIAN) + #include <linux/byteorder/big_endian.h> +#else + # error "Must be LITTLE/BIG Endian Host" +#endif + +#endif /* _RTL871X_BYTEORDER_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_cmd.h b/drivers/staging/rtl8821ce/include/rtw_cmd.h new file mode 100644 index 000000000000..5b7bb55ab090 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_cmd.h @@ -0,0 +1,993 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_CMD_H_ +#define __RTW_CMD_H_ + +#define C2H_MEM_SZ (16*1024) + +#define FREE_CMDOBJ_SZ 128 + +#define MAX_CMDSZ 1024 +#define MAX_RSPSZ 512 +#define MAX_EVTSZ 1024 + + #define CMDBUFF_ALIGN_SZ 512 + +struct cmd_obj { + _adapter *padapter; + u16 cmdcode; + u8 res; + u8 *parmbuf; + u32 cmdsz; + u8 *rsp; + u32 rspsz; + struct submit_ctx *sctx; + u8 no_io; + /* _sema cmd_sem; */ + _list list; +}; + +/* cmd flags */ +enum { + RTW_CMDF_DIRECTLY = BIT0, + RTW_CMDF_WAIT_ACK = BIT1, +}; + +struct cmd_priv { + _sema cmd_queue_sema; + /* _sema cmd_done_sema; */ + /*_sema terminate_cmdthread_sema;*/ + _sema start_cmdthread_sema; + _completion cmdthread_comp; + _queue cmd_queue; + u8 cmd_seq; + u8 *cmd_buf; /* shall be non-paged, and 4 bytes aligned */ + u8 *cmd_allocated_buf; + u8 *rsp_buf; /* shall be non-paged, and 4 bytes aligned */ + u8 *rsp_allocated_buf; + u32 cmd_issued_cnt; + u32 cmd_done_cnt; + u32 rsp_cnt; + ATOMIC_T cmdthd_running; + /* u8 cmdthd_running; */ + u8 stop_req; + _adapter *padapter; + _mutex sctx_mutex; +}; + + +struct evt_priv { + + + + ATOMIC_T event_seq; + u8 *evt_buf; /* shall be non-paged, and 4 bytes aligned */ + u8 *evt_allocated_buf; + u32 evt_done_cnt; + +}; + +#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ + do {\ + _rtw_init_listhead(&pcmd->list);\ + pcmd->cmdcode = code;\ + pcmd->parmbuf = (u8 *)(pparm);\ + pcmd->cmdsz = sizeof (*pparm);\ + pcmd->rsp = NULL;\ + pcmd->rspsz = 0;\ + } while (0) + +#define init_h2fwcmd_w_parm_no_parm_rsp(pcmd, code) \ + do {\ + _rtw_init_listhead(&pcmd->list);\ + pcmd->cmdcode = code;\ + pcmd->parmbuf = NULL;\ + pcmd->cmdsz = 0;\ + pcmd->rsp = NULL;\ + pcmd->rspsz = 0;\ + } while (0) + +struct P2P_PS_Offload_t { + u8 Offload_En:1; + u8 role:1; /* 1: Owner, 0: Client */ + u8 CTWindow_En:1; + u8 NoA0_En:1; + u8 NoA1_En:1; + u8 AllStaSleep:1; /* Only valid in Owner */ + u8 discovery:1; + u8 rsvd:1; +}; + +struct P2P_PS_CTWPeriod_t { + u8 CTWPeriod; /* TU */ +}; + + +extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); +extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); +extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); + + +void rtw_stop_cmd_thread(_adapter *adapter); +thread_return rtw_cmd_thread(thread_context context); + +extern u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv); +extern void rtw_free_cmd_priv(struct cmd_priv *pcmdpriv); + +extern u32 rtw_init_evt_priv(struct evt_priv *pevtpriv); +extern void rtw_free_evt_priv(struct evt_priv *pevtpriv); +extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); +extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); +u8 p2p_protocol_wk_cmd(_adapter *padapter, int intCmdType); + +enum rtw_drvextra_cmd_id { + NONE_WK_CID, + STA_MSTATUS_RPT_WK_CID, + DYNAMIC_CHK_WK_CID, + DM_CTRL_WK_CID, + PBC_POLLING_WK_CID, + POWER_SAVING_CTRL_WK_CID,/* IPS,AUTOSuspend */ + LPS_CTRL_WK_CID, + ANT_SELECT_WK_CID, + P2P_PS_WK_CID, + P2P_PROTO_WK_CID, + CHECK_HIQ_WK_CID,/* for softap mode, check hi queue if empty */ + INTEl_WIDI_WK_CID, + C2H_WK_CID, + RTP_TIMER_CFG_WK_CID, + RESET_SECURITYPRIV, /* add for CONFIG_IEEE80211W, none 11w also can use */ + FREE_ASSOC_RESOURCES, /* add for CONFIG_IEEE80211W, none 11w also can use */ + DM_IN_LPS_WK_CID, + DM_RA_MSK_WK_CID, /* add for STA update RAMask when bandwith change. */ + BEAMFORMING_WK_CID, + LPS_CHANGE_DTIM_CID, + BTINFO_WK_CID, + DFS_MASTER_WK_CID, + SESSION_TRACKER_WK_CID, + EN_HW_UPDATE_TSF_WK_CID, + TEST_H2C_CID, + MP_CMD_WK_CID, + CUSTOMER_STR_WK_CID, + MAX_WK_CID +}; + +enum LPS_CTRL_TYPE { + LPS_CTRL_SCAN = 0, + LPS_CTRL_JOINBSS = 1, + LPS_CTRL_CONNECT = 2, + LPS_CTRL_DISCONNECT = 3, + LPS_CTRL_SPECIAL_PACKET = 4, + LPS_CTRL_LEAVE = 5, + LPS_CTRL_TRAFFIC_BUSY = 6, + LPS_CTRL_TX_TRAFFIC_LEAVE = 7, + LPS_CTRL_RX_TRAFFIC_LEAVE = 8, + LPS_CTRL_ENTER = 9, + LPS_CTRL_LEAVE_CFG80211_PWRMGMT = 10, +}; + +enum STAKEY_TYPE { + GROUP_KEY = 0, + UNICAST_KEY = 1, + TDLS_KEY = 2, +}; + +enum RFINTFS { + SWSI, + HWSI, + HWPI, +}; + +/* +Caller Mode: Infra, Ad-HoC(C) + +Notes: To enter USB suspend mode + +Command Mode + +*/ +struct usb_suspend_parm { + u32 action;/* 1: sleep, 0:resume */ +}; + +/* +Caller Mode: Infra, Ad-HoC + +Notes: To join a known BSS. + +Command-Event Mode + +*/ + +/* +Caller Mode: Infra, Ad-Hoc + +Notes: To join the specified bss + +Command Event Mode + +*/ +struct joinbss_parm { + WLAN_BSSID_EX network; +}; + +/* +Caller Mode: Infra, Ad-HoC(C) + +Notes: To disconnect the current associated BSS + +Command Mode + +*/ +struct disconnect_parm { + u32 deauth_timeout_ms; +}; + +/* +Caller Mode: AP, Ad-HoC(M) + +Notes: To create a BSS + +Command Mode +*/ +struct createbss_parm { + bool adhoc; + + /* used by AP mode now */ + s16 req_ch; + s8 req_bw; + s8 req_offset; +}; + + +struct setopmode_parm { + u8 mode; + u8 rsvd[3]; +}; + +/* +Caller Mode: AP, Ad-HoC, Infra + +Notes: To ask RTL8711 performing site-survey + +Command-Event Mode + +*/ + +#define RTW_SSID_SCAN_AMOUNT 9 /* for WEXT_CSCAN_AMOUNT 9 */ +#define RTW_CHANNEL_SCAN_AMOUNT (14+37) +struct sitesurvey_parm { + sint scan_mode; /* active: 1, passive: 0 */ + /* sint bsslimit; // 1 ~ 48 */ + u8 ssid_num; + u8 ch_num; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; +}; + +/* +Caller Mode: Any + +Notes: To set the auth type of RTL8711. open/shared/802.1x + +Command Mode + +*/ +struct setauth_parm { + u8 mode; /* 0: legacy open, 1: legacy shared 2: 802.1x */ + u8 _1x; /* 0: PSK, 1: TLS */ + u8 rsvd[2]; +}; + +/* +Caller Mode: Infra + +a. algorithm: wep40, wep104, tkip & aes +b. keytype: grp key/unicast key +c. key contents + +when shared key ==> keyid is the camid +when 802.1x ==> keyid [0:1] ==> grp key +when 802.1x ==> keyid > 2 ==> unicast key + +*/ +struct setkey_parm { + u8 algorithm; /* encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 */ + u8 keyid; + u8 grpkey; /* 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x */ + u8 set_tx; /* 1: main tx key for wep. 0: other key. */ + u8 key[16]; /* this could be 40 or 104 */ +}; + +/* +When in AP or Ad-Hoc mode, this is used to +allocate an sw/hw entry for a newly associated sta. + +Command + +when shared key ==> algorithm/keyid + +*/ +struct set_stakey_parm { + u8 addr[ETH_ALEN]; + u8 algorithm; + u8 keyid; + u8 key[16]; +}; + +struct set_stakey_rsp { + u8 addr[ETH_ALEN]; + u8 keyid; + u8 rsvd; +}; + +/* +Caller Ad-Hoc/AP + +Command -Rsp(AID == CAMID) mode + +This is to force fw to add an sta_data entry per driver's request. + +FW will write an cam entry associated with it. + +*/ +struct set_assocsta_parm { + u8 addr[ETH_ALEN]; +}; + +struct set_assocsta_rsp { + u8 cam_id; + u8 rsvd[3]; +}; + +/* + Caller Ad-Hoc/AP + Command mode + This is to force fw to del an sta_data entry per driver's request + FW will invalidate the cam entry associated with it. +*/ +struct del_assocsta_parm { + u8 addr[ETH_ALEN]; +}; + +/* +Caller Mode: AP/Ad-HoC(M) + +Notes: To notify fw that given staid has changed its power state + +Command Mode + +*/ +struct setstapwrstate_parm { + u8 staid; + u8 status; + u8 hwaddr[6]; +}; + +/* +Caller Mode: Any + +Notes: To setup the basic rate of RTL8711 + +Command Mode + +*/ +struct setbasicrate_parm { + u8 basicrates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To read the current basic rate + +Command-Rsp Mode + +*/ +struct getbasicrate_parm { + u32 rsvd; +}; + +struct getbasicrate_rsp { + u8 basicrates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To setup the data rate of RTL8711 + +Command Mode + +*/ +struct setdatarate_parm { + u8 mac_id; + u8 datarates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To read the current data rate + +Command-Rsp Mode + +*/ +struct getdatarate_parm { + u32 rsvd; + +}; +struct getdatarate_rsp { + u8 datarates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To set the channel/modem/band +This command will be used when channel/modem/band is changed. + +Command Mode + +*/ +struct setphy_parm { + u8 rfchannel; + u8 modem; +}; + +/* +Caller Mode: Any + +Notes: To get the current setting of channel/modem/band + +Command-Rsp Mode + +*/ +struct getphy_parm { + u32 rsvd; + +}; +struct getphy_rsp { + u8 rfchannel; + u8 modem; +}; + +struct readBB_parm { + u8 offset; +}; +struct readBB_rsp { + u8 value; +}; + +struct readTSSI_parm { + u8 offset; +}; +struct readTSSI_rsp { + u8 value; +}; + +struct readMAC_parm { + u8 len; + u32 addr; +}; + +struct writeBB_parm { + u8 offset; + u8 value; +}; + +struct readRF_parm { + u8 offset; +}; +struct readRF_rsp { + u32 value; +}; + +struct writeRF_parm { + u32 offset; + u32 value; +}; + +struct getrfintfs_parm { + u8 rfintfs; +}; + +struct Tx_Beacon_param { + WLAN_BSSID_EX network; +}; + +/* + Notes: This command is used for H2C/C2H loopback testing + + mac[0] == 0 + ==> CMD mode, return H2C_SUCCESS. + The following condition must be ture under CMD mode + mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0; + s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7; + s2 == (b1 << 8 | b0); + + mac[0] == 1 + ==> CMD_RSP mode, return H2C_SUCCESS_RSP + + The rsp layout shall be: + rsp: parm: + mac[0] = mac[5]; + mac[1] = mac[4]; + mac[2] = mac[3]; + mac[3] = mac[2]; + mac[4] = mac[1]; + mac[5] = mac[0]; + s0 = s1; + s1 = swap16(s0); + w0 = swap32(w1); + b0 = b1 + s2 = s0 + s1 + b1 = b0 + w1 = w0 + + mac[0] == 2 + ==> CMD_EVENT mode, return H2C_SUCCESS + The event layout shall be: + event: parm: + mac[0] = mac[5]; + mac[1] = mac[4]; + mac[2] = event's sequence number, starting from 1 to parm's marc[3] + mac[3] = mac[2]; + mac[4] = mac[1]; + mac[5] = mac[0]; + s0 = swap16(s0) - event.mac[2]; + s1 = s1 + event.mac[2]; + w0 = swap32(w0); + b0 = b1 + s2 = s0 + event.mac[2] + b1 = b0 + w1 = swap32(w1) - event.mac[2]; + + parm->mac[3] is the total event counts that host requested. + + event will be the same with the cmd's param. + +*/ + + +/* CMD param Formart for driver extra cmd handler */ +struct drvextra_cmd_parm { + int ec_id; /* extra cmd id */ + int type; /* Can use this field as the type id or command size */ + int size; /* buffer size */ + unsigned char *pbuf; +}; + +/*------------------- Below are used for RF/BB tunning ---------------------*/ + +struct setantenna_parm { + u8 tx_antset; + u8 rx_antset; + u8 tx_antenna; + u8 rx_antenna; +}; + +struct enrateadaptive_parm { + u32 en; +}; + +struct settxagctbl_parm { + u32 txagc[MAX_RATES_LENGTH]; +}; + +struct gettxagctbl_parm { + u32 rsvd; +}; +struct gettxagctbl_rsp { + u32 txagc[MAX_RATES_LENGTH]; +}; + +struct setagcctrl_parm { + u32 agcctrl; /* 0: pure hw, 1: fw */ +}; + +struct setssup_parm { + u32 ss_ForceUp[MAX_RATES_LENGTH]; +}; + +struct getssup_parm { + u32 rsvd; +}; +struct getssup_rsp { + u8 ss_ForceUp[MAX_RATES_LENGTH]; +}; + +struct setssdlevel_parm { + u8 ss_DLevel[MAX_RATES_LENGTH]; +}; + +struct getssdlevel_parm { + u32 rsvd; +}; +struct getssdlevel_rsp { + u8 ss_DLevel[MAX_RATES_LENGTH]; +}; + +struct setssulevel_parm { + u8 ss_ULevel[MAX_RATES_LENGTH]; +}; + +struct getssulevel_parm { + u32 rsvd; +}; +struct getssulevel_rsp { + u8 ss_ULevel[MAX_RATES_LENGTH]; +}; + +struct setcountjudge_parm { + u8 count_judge[MAX_RATES_LENGTH]; +}; + +struct getcountjudge_parm { + u32 rsvd; +}; +struct getcountjudge_rsp { + u8 count_judge[MAX_RATES_LENGTH]; +}; + +struct setratable_parm { + u8 ss_ForceUp[NumRates]; + u8 ss_ULevel[NumRates]; + u8 ss_DLevel[NumRates]; + u8 count_judge[NumRates]; +}; + +struct getratable_parm { + uint rsvd; +}; +struct getratable_rsp { + u8 ss_ForceUp[NumRates]; + u8 ss_ULevel[NumRates]; + u8 ss_DLevel[NumRates]; + u8 count_judge[NumRates]; +}; + +/* to get TX,RX retry count */ +struct gettxretrycnt_parm { + unsigned int rsvd; +}; +struct gettxretrycnt_rsp { + unsigned long tx_retrycnt; +}; + +struct getrxretrycnt_parm { + unsigned int rsvd; +}; +struct getrxretrycnt_rsp { + unsigned long rx_retrycnt; +}; + +/* to get BCNOK,BCNERR count */ +struct getbcnokcnt_parm { + unsigned int rsvd; +}; +struct getbcnokcnt_rsp { + unsigned long bcnokcnt; +}; + +struct getbcnerrcnt_parm { + unsigned int rsvd; +}; +struct getbcnerrcnt_rsp { + unsigned long bcnerrcnt; +}; + +/* to get current TX power level */ +struct getcurtxpwrlevel_parm { + unsigned int rsvd; +}; +struct getcurtxpwrlevel_rsp { + unsigned short tx_power; +}; + +struct setprobereqextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setassocreqextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setproberspextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setassocrspextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct addBaReq_parm { + unsigned int tid; + u8 addr[ETH_ALEN]; +}; + +struct addBaRsp_parm { + unsigned int tid; + unsigned int start_seq; + u8 addr[ETH_ALEN]; + u8 status; + u8 size; +}; + +/*H2C Handler index: 46 */ +struct set_ch_parm { + u8 ch; + u8 bw; + u8 ch_offset; +}; + + +/*H2C Handler index: 59 */ +struct SetChannelPlan_param { + const struct country_chplan *country_ent; + u8 channel_plan; +}; + +/*H2C Handler index: 60 */ +struct LedBlink_param { + PVOID pLed; +}; + +/*H2C Handler index: 61 */ +struct SetChannelSwitch_param { + u8 new_ch_no; +}; + +/*H2C Handler index: 62 */ +struct TDLSoption_param { + u8 addr[ETH_ALEN]; + u8 option; +}; + +/*H2C Handler index: 64 */ +struct RunInThread_param { + void (*func)(void *); + void *context; +}; + +#define GEN_CMD_CODE(cmd) cmd ## _CMD_ + +/* + +Result: +0x00: success +0x01: sucess, and check Response. +0x02: cmd ignored due to duplicated sequcne number +0x03: cmd dropped due to invalid cmd code +0x04: reserved. + +*/ + +#define H2C_RSP_OFFSET 512 + +#define H2C_SUCCESS 0x00 +#define H2C_SUCCESS_RSP 0x01 +#define H2C_DUPLICATED 0x02 +#define H2C_DROPPED 0x03 +#define H2C_PARAMETERS_ERROR 0x04 +#define H2C_REJECTED 0x05 +#define H2C_CMD_OVERFLOW 0x06 +#define H2C_RESERVED 0x07 +#define H2C_ENQ_HEAD 0x08 +#define H2C_ENQ_HEAD_FAIL 0x09 + +extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr); +extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action); +u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num); + +u8 rtw_create_ibss_cmd(_adapter *adapter, int flags); +u8 rtw_startbss_cmd(_adapter *adapter, int flags); +u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, s16 req_ch, s8 req_bw, s8 req_offset); + +extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch); + +struct sta_info; +extern u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue); +extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue); + +extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network *pnetwork); +u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, int flags); +extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue); +extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); +extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); +extern u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr); +extern void rtw_usb_catc_trigger_cmd(_adapter *padapter, const char *caller); +extern u8 rtw_setbbreg_cmd(_adapter *padapter, u8 offset, u8 val); +extern u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val); +extern u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval); +extern u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval); +extern u8 rtw_setrfintfs_cmd(_adapter *padapter, u8 mode); +extern u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table); +extern u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval); + +extern u8 rtw_gettssi_cmd(_adapter *padapter, u8 offset, u8 *pval); +extern u8 rtw_setfwdig_cmd(_adapter *padapter, u8 type); +extern u8 rtw_setfwra_cmd(_adapter *padapter, u8 type); + +extern u8 rtw_addbareq_cmd(_adapter *padapter, u8 tid, u8 *addr); +extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq); +/* add for CONFIG_IEEE80211W, none 11w also can use */ +extern u8 rtw_reset_securitypriv_cmd(_adapter *padapter); +extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter); +extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter); + +u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue); +u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter); +u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim); + + + +u8 rtw_dm_ra_mask_wk_cmd(_adapter *padapter, u8 *psta); + +extern u8 rtw_ps_cmd(_adapter *padapter); + +u8 rtw_chk_hi_queue_cmd(_adapter *padapter); + +u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); + +u8 rtw_test_h2c_cmd(_adapter *adapter, u8 *buf, u8 len); + +u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter); + +u8 rtw_set_ch_cmd(_adapter *padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue); + +u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig); +u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig); + +extern u8 rtw_led_blink_cmd(_adapter *padapter, PVOID pLed); +extern u8 rtw_set_csa_cmd(_adapter *padapter, u8 new_ch_no); +extern u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option); + +u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags); + +u8 rtw_c2h_packet_wk_cmd(_adapter *adapter, u8 *c2h_evt, u16 length); + +u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void *), void *context); + +u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta); +u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); + +u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); + +extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +void rtw_create_ibss_post_hdl(_adapter *padapter, int status); +extern void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_readtssi_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); + +extern void rtw_setstaKey_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_getrttbl_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_getmacreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); + +struct _cmd_callback { + u32 cmd_code; + void (*callback)(_adapter *padapter, struct cmd_obj *cmd); +}; + +enum rtw_h2c_cmd { + GEN_CMD_CODE(_Read_MACREG) , /*0*/ + GEN_CMD_CODE(_Write_MACREG) , + GEN_CMD_CODE(_Read_BBREG) , + GEN_CMD_CODE(_Write_BBREG) , + GEN_CMD_CODE(_Read_RFREG) , + GEN_CMD_CODE(_Write_RFREG) , /*5*/ + GEN_CMD_CODE(_Read_EEPROM) , + GEN_CMD_CODE(_Write_EEPROM) , + GEN_CMD_CODE(_Read_EFUSE) , + GEN_CMD_CODE(_Write_EFUSE) , + + GEN_CMD_CODE(_Read_CAM) , /*10*/ + GEN_CMD_CODE(_Write_CAM) , + GEN_CMD_CODE(_setBCNITV), + GEN_CMD_CODE(_setMBIDCFG), + GEN_CMD_CODE(_JoinBss), /*14*/ + GEN_CMD_CODE(_DisConnect) , /*15*/ + GEN_CMD_CODE(_CreateBss) , + GEN_CMD_CODE(_SetOpMode) , + GEN_CMD_CODE(_SiteSurvey), /*18*/ + GEN_CMD_CODE(_SetAuth) , + + GEN_CMD_CODE(_SetKey) , /*20*/ + GEN_CMD_CODE(_SetStaKey) , + GEN_CMD_CODE(_SetAssocSta) , + GEN_CMD_CODE(_DelAssocSta) , + GEN_CMD_CODE(_SetStaPwrState) , + GEN_CMD_CODE(_SetBasicRate) , /*25*/ + GEN_CMD_CODE(_GetBasicRate) , + GEN_CMD_CODE(_SetDataRate) , + GEN_CMD_CODE(_GetDataRate) , + GEN_CMD_CODE(_SetPhyInfo) , + + GEN_CMD_CODE(_GetPhyInfo) , /*30*/ + GEN_CMD_CODE(_SetPhy) , + GEN_CMD_CODE(_GetPhy) , + GEN_CMD_CODE(_readRssi) , + GEN_CMD_CODE(_readGain) , + GEN_CMD_CODE(_SetAtim) , /*35*/ + GEN_CMD_CODE(_SetPwrMode) , + GEN_CMD_CODE(_JoinbssRpt), + GEN_CMD_CODE(_SetRaTable) , + GEN_CMD_CODE(_GetRaTable) , + + GEN_CMD_CODE(_GetCCXReport), /*40*/ + GEN_CMD_CODE(_GetDTMReport), + GEN_CMD_CODE(_GetTXRateStatistics), + GEN_CMD_CODE(_SetUsbSuspend), + GEN_CMD_CODE(_SetH2cLbk), + GEN_CMD_CODE(_AddBAReq) , /*45*/ + GEN_CMD_CODE(_SetChannel), /*46*/ + GEN_CMD_CODE(_SetTxPower), + GEN_CMD_CODE(_SwitchAntenna), + GEN_CMD_CODE(_SetCrystalCap), + GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/ + + GEN_CMD_CODE(_SetSingleToneTx),/*51*/ + GEN_CMD_CODE(_SetCarrierSuppressionTx), + GEN_CMD_CODE(_SetContinuousTx), + GEN_CMD_CODE(_SwitchBandwidth), /*54*/ + GEN_CMD_CODE(_TX_Beacon), /*55*/ + + GEN_CMD_CODE(_Set_MLME_EVT), /*56*/ + GEN_CMD_CODE(_Set_Drv_Extra), /*57*/ + GEN_CMD_CODE(_Set_H2C_MSG), /*58*/ + + GEN_CMD_CODE(_SetChannelPlan), /*59*/ + GEN_CMD_CODE(_LedBlink), /*60*/ + + GEN_CMD_CODE(_SetChannelSwitch), /*61*/ + GEN_CMD_CODE(_TDLS), /*62*/ + GEN_CMD_CODE(_ChkBMCSleepq), /*63*/ + + GEN_CMD_CODE(_RunInThreadCMD), /*64*/ + GEN_CMD_CODE(_AddBARsp) , /*65*/ + + MAX_H2CCMD +}; + +#define _GetMACReg_CMD_ _Read_MACREG_CMD_ +#define _SetMACReg_CMD_ _Write_MACREG_CMD_ +#define _GetBBReg_CMD_ _Read_BBREG_CMD_ +#define _SetBBReg_CMD_ _Write_BBREG_CMD_ +#define _GetRFReg_CMD_ _Read_RFREG_CMD_ +#define _SetRFReg_CMD_ _Write_RFREG_CMD_ + +#define CMD_FMT "cmd=%d,%d,%d" +#define CMD_ARG(cmd) \ + (cmd)->cmdcode, \ + (cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->ec_id : ((cmd)->cmdcode == GEN_CMD_CODE(_Set_MLME_EVT) ? ((struct C2HEvent_Header *)(cmd)->parmbuf)->ID : 0), \ + (cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->type : 0 + +#endif /* _CMD_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_debug.h b/drivers/staging/rtl8821ce/include/rtw_debug.h new file mode 100644 index 000000000000..f61aa06820a3 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_debug.h @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_DEBUG_H__ +#define __RTW_DEBUG_H__ + +/* driver log level*/ +enum { + _DRV_NONE_ = 0, + _DRV_ALWAYS_ = 1, + _DRV_ERR_ = 2, + _DRV_WARNING_ = 3, + _DRV_INFO_ = 4, + _DRV_DEBUG_ = 5, + _DRV_MAX_ = 6 +}; + +#define DRIVER_PREFIX "RTW: " + +#define RTW_PRINT(x, ...) do {} while (0) +#define RTW_ERR(x, ...) do {} while (0) +#define RTW_WARN(x,...) do {} while (0) +#define RTW_INFO(x,...) do {} while (0) +#define RTW_DBG(x,...) do {} while (0) +#define RTW_PRINT_SEL(x,...) do {} while (0) +#define _RTW_PRINT(x, ...) do {} while (0) +#define _RTW_ERR(x, ...) do {} while (0) +#define _RTW_WARN(x,...) do {} while (0) +#define _RTW_INFO(x,...) do {} while (0) +#define _RTW_DBG(x,...) do {} while (0) +#define _RTW_PRINT_SEL(x,...) do {} while (0) + +#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) +#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) +#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) +#define _RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) +#define _RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) do {} while (0) + +#define RTW_DBG_EXPR(EXPR) do {} while (0) + +#define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */ + +/* don't use these 3 APIs anymore, will be removed later */ +#define RT_TRACE(_Comp, _Level, Fmt) do {} while (0) + +#undef _dbgdump +#undef _seqdump + +#define _dbgdump printk +#define _seqdump seq_printf + +#ifndef _OS_INTFS_C_ +extern uint rtw_drv_log_level; +#endif + +#if defined(_dbgdump) + +/* with driver-defined prefix */ +#undef RTW_PRINT +#define RTW_PRINT(fmt, arg...) \ + do {\ + if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\ + _dbgdump(DRIVER_PREFIX fmt, ##arg);\ + } \ + } while (0) + +#undef RTW_ERR +#define RTW_ERR(fmt, arg...) \ + do {\ + if (_DRV_ERR_ <= rtw_drv_log_level) {\ + _dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\ + } \ + } while (0) + +#undef RTW_WARN +#define RTW_WARN(fmt, arg...) \ + do {\ + if (_DRV_WARNING_ <= rtw_drv_log_level) {\ + _dbgdump(DRIVER_PREFIX"WARN " fmt, ##arg);\ + } \ + } while (0) + +#undef RTW_INFO +#define RTW_INFO(fmt, arg...) \ + do {\ + if (_DRV_INFO_ <= rtw_drv_log_level) {\ + _dbgdump(DRIVER_PREFIX fmt, ##arg);\ + } \ + } while (0) + +#undef RTW_DBG +#define RTW_DBG(fmt, arg...) \ + do {\ + if (_DRV_DEBUG_ <= rtw_drv_log_level) {\ + _dbgdump(DRIVER_PREFIX fmt, ##arg);\ + } \ + } while (0) + +#undef RTW_INFO_DUMP +#define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ + do {\ + if (_DRV_INFO_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + } while (0) + +#undef RTW_DBG_DUMP +#define RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ + do {\ + if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + } while (0) + +#undef RTW_PRINT_DUMP +#define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) \ + do {\ + if (_DRV_ALWAYS_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + } while (0) + +/* without driver-defined prefix */ +#undef _RTW_PRINT +#define _RTW_PRINT(fmt, arg...) \ + do {\ + if (_DRV_ALWAYS_ <= rtw_drv_log_level) {\ + _dbgdump(fmt, ##arg);\ + } \ + } while (0) + +#undef _RTW_ERR +#define _RTW_ERR(fmt, arg...) \ + do {\ + if (_DRV_ERR_ <= rtw_drv_log_level) {\ + _dbgdump(fmt, ##arg);\ + } \ + } while (0) + +#undef _RTW_WARN +#define _RTW_WARN(fmt, arg...) \ + do {\ + if (_DRV_WARNING_ <= rtw_drv_log_level) {\ + _dbgdump(fmt, ##arg);\ + } \ + } while (0) + +#undef _RTW_INFO +#define _RTW_INFO(fmt, arg...) \ + do {\ + if (_DRV_INFO_ <= rtw_drv_log_level) {\ + _dbgdump(fmt, ##arg);\ + } \ + } while (0) + +#undef _RTW_DBG +#define _RTW_DBG(fmt, arg...) \ + do {\ + if (_DRV_DEBUG_ <= rtw_drv_log_level) {\ + _dbgdump(fmt, ##arg);\ + } \ + } while (0) + +#undef _RTW_INFO_DUMP +#define _RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ + if (_DRV_INFO_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump(_TitleString); \ + for (__i = 0; __i<(int)_HexDataLen; __i++) \ + { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } + +#undef _RTW_DBG_DUMP +#define _RTW_DBG_DUMP(_TitleString, _HexData, _HexDataLen) \ + if (_DRV_DEBUG_ <= rtw_drv_log_level) { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump(_TitleString); \ + for (__i = 0; __i<(int)_HexDataLen; __i++) \ + { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } + +/* other debug APIs */ +#undef RTW_DBG_EXPR +#define RTW_DBG_EXPR(EXPR) do { if (_DRV_DEBUG_ <= rtw_drv_log_level) EXPR; } while (0) + +#endif /* defined(_dbgdump) */ + +#if defined(_seqdump) +/* dump message to selected 'stream' with driver-defined prefix */ +#undef RTW_PRINT_SEL +#define RTW_PRINT_SEL(sel, fmt, arg...) \ + do {\ + if (sel == RTW_DBGDUMP)\ + RTW_PRINT(fmt, ##arg); \ + else {\ + _seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \ + } \ + } while (0) + +/* dump message to selected 'stream' */ +#undef _RTW_PRINT_SEL +#define _RTW_PRINT_SEL(sel, fmt, arg...) \ + do {\ + if (sel == RTW_DBGDUMP)\ + _RTW_PRINT(fmt, ##arg); \ + else {\ + _seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \ + } \ + } while (0) + +/* dump message to selected 'stream' */ +#undef _RTW_DUMP_SEL +#define _RTW_DUMP_SEL(sel, _HexData, _HexDataLen) \ + do {\ + if (sel == RTW_DBGDUMP) {\ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } \ + else {\ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _seqdump(sel, "%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _seqdump(sel, "\n"); \ + } \ + _seqdump(sel, "\n"); \ + } \ + } while (0) + +#endif /* defined(_seqdump) */ + +#ifdef CONFIG_DBG_COUNTER + #define DBG_COUNTER(counter) counter++ +#else + #define DBG_COUNTER(counter) +#endif + +void dump_drv_version(void *sel); +void dump_log_level(void *sel); +void dump_drv_cfg(void *sel); + +void mac_reg_dump(void *sel, _adapter *adapter); +void bb_reg_dump(void *sel, _adapter *adapter); +void bb_reg_dump_ex(void *sel, _adapter *adapter); +void rf_reg_dump(void *sel, _adapter *adapter); + +void rtw_sink_rtp_seq_dbg(_adapter *adapter, _pkt *pkt); + +struct sta_info; +void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta); + +struct dvobj_priv; +void dump_tx_rate_bmp(void *sel, struct dvobj_priv *dvobj); +void dump_adapters_status(void *sel, struct dvobj_priv *dvobj); + +struct sec_cam_ent; +void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id); +void dump_sec_cam_ent_title(void *sel, u8 has_id); +void dump_sec_cam(void *sel, _adapter *adapter); +void dump_sec_cam_cache(void *sel, _adapter *adapter); + +bool rtw_fwdl_test_trigger_chksum_fail(void); +bool rtw_fwdl_test_trigger_wintint_rdy_fail(void); +bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void); +u32 rtw_get_wait_hiq_empty_ms(void); +void rtw_sta_linking_test_set_start(void); +bool rtw_sta_linking_test_wait_done(void); +bool rtw_sta_linking_test_force_fail(void); + +void dump_regsty_rx_ampdu_size_limit(void *sel, _adapter *adapter); + +void rtw_dump_dft_phy_cap(void *sel, _adapter *adapter); +void rtw_get_dft_phy_cap(void *sel, _adapter *adapter); +void rtw_dump_drv_phy_cap(void *sel, _adapter *adapter); + +#endif /* __RTW_DEBUG_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_eeprom.h b/drivers/staging/rtl8821ce/include/rtw_eeprom.h new file mode 100644 index 000000000000..8cbce7cf871a --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_eeprom.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_EEPROM_H__ +#define __RTW_EEPROM_H__ + +#define RTL8712_EEPROM_ID 0x8712 +/* #define EEPROM_MAX_SIZE 256 */ + +#define HWSET_MAX_SIZE_128 128 +#define HWSET_MAX_SIZE_256 256 +#define HWSET_MAX_SIZE_512 512 +#define HWSET_MAX_SIZE_1024 1024 + +#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_1024 + +#define CLOCK_RATE 50 /* 100us */ + +/* - EEPROM opcodes */ +#define EEPROM_READ_OPCODE 06 +#define EEPROM_WRITE_OPCODE 05 +#define EEPROM_ERASE_OPCODE 07 +#define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */ +#define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */ + +/* Country codes */ +#define USA 0x555320 +#define EUROPE 0x1 /* temp, should be provided later */ +#define JAPAN 0x2 /* temp, should be provided later */ + +/* + * Customer ID, note that: + * This variable is initiailzed through EEPROM or registry, + * however, its definition may be different with that in EEPROM for + * EEPROM size consideration. So, we have to perform proper translation between them. + * Besides, CustomerID of registry has precedence of that of EEPROM. + * defined below. 060703, by rcnjko. + * */ +typedef enum _RT_CUSTOMER_ID { + RT_CID_DEFAULT = 0, + RT_CID_8187_ALPHA0 = 1, + RT_CID_8187_SERCOMM_PS = 2, + RT_CID_8187_HW_LED = 3, + RT_CID_8187_NETGEAR = 4, + RT_CID_WHQL = 5, + RT_CID_819x_CAMEO = 6, + RT_CID_819x_RUNTOP = 7, + RT_CID_819x_Senao = 8, + RT_CID_TOSHIBA = 9, /* Merge by Jacken, 2008/01/31. */ + RT_CID_819x_Netcore = 10, + RT_CID_Nettronix = 11, + RT_CID_DLINK = 12, + RT_CID_PRONET = 13, + RT_CID_COREGA = 14, + RT_CID_CHINA_MOBILE = 15, + RT_CID_819x_ALPHA = 16, + RT_CID_819x_Sitecom = 17, + RT_CID_CCX = 18, /* It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. */ + RT_CID_819X_LENOVO = 19, + RT_CID_819x_QMI = 20, + RT_CID_819x_Edimax_Belkin = 21, + RT_CID_819x_Sercomm_Belkin = 22, + RT_CID_819x_CAMEO1 = 23, + RT_CID_819x_MSI = 24, + RT_CID_819X_ACER = 25, + RT_CID_819x_AzWave_ASUS = 26, + RT_CID_819x_AzWave = 27, /* For AzWave in PCIe, The ID is AzWave use and not only Asus */ + RT_CID_819x_HP = 28, + RT_CID_819x_WNC_COREGA = 29, + RT_CID_819x_Arcadyan_Belkin = 30, + RT_CID_819x_SAMSUNG = 31, + RT_CID_819x_CLEVO = 32, + RT_CID_819x_DELL = 33, + RT_CID_819x_PRONETS = 34, + RT_CID_819x_Edimax_ASUS = 35, + RT_CID_NETGEAR = 36, + RT_CID_PLANEX = 37, + RT_CID_CC_C = 38, + RT_CID_819x_Xavi = 39, + RT_CID_LENOVO_CHINA = 40, + RT_CID_INTEL_CHINA = 41, + RT_CID_TPLINK_HPWR = 42, + RT_CID_819x_Sercomm_Netgear = 43, + RT_CID_819x_ALPHA_Dlink = 44,/* add by ylb 20121012 for customer led for alpha */ + RT_CID_WNC_NEC = 45,/* add by page for NEC */ + RT_CID_DNI_BUFFALO = 46,/* add by page for NEC */ +} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; + +extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data); +extern u16 eeprom_read16(_adapter *padapter, u16 reg); +extern void read_eeprom_content(_adapter *padapter); +extern void eeprom_read_sz(_adapter *padapter, u16 reg, u8 *data, u32 sz); + +extern void read_eeprom_content_by_attrib(_adapter *padapter); + + +#endif /* __RTL871X_EEPROM_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_efuse.h b/drivers/staging/rtl8821ce/include/rtw_efuse.h new file mode 100644 index 000000000000..22f102591333 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_efuse.h @@ -0,0 +1,238 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_EFUSE_H__ +#define __RTW_EFUSE_H__ + +#define EFUSE_ERROE_HANDLE 1 + +#define PG_STATE_HEADER 0x01 +#define PG_STATE_WORD_0 0x02 +#define PG_STATE_WORD_1 0x04 +#define PG_STATE_WORD_2 0x08 +#define PG_STATE_WORD_3 0x10 +#define PG_STATE_DATA 0x20 + +#define PG_SWBYTE_H 0x01 +#define PG_SWBYTE_L 0x02 + +#define PGPKT_DATA_SIZE 8 + +#define EFUSE_WIFI 0 +#define EFUSE_BT 1 + +enum _EFUSE_DEF_TYPE { + TYPE_EFUSE_MAX_SECTION = 0, + TYPE_EFUSE_REAL_CONTENT_LEN = 1, + TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, + TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, + TYPE_EFUSE_MAP_LEN = 4, + TYPE_EFUSE_PROTECT_BYTES_BANK = 5, + TYPE_EFUSE_CONTENT_LEN_BANK = 6, +}; + +#define EFUSE_MAX_MAP_LEN 1024 + +#define EFUSE_MAX_HW_SIZE 1024 +#define EFUSE_MAX_SECTION_BASE 16 + +/*RTL8822B 8821C BT EFUSE Define 1 BANK 128 size logical map 1024*/ +#define BANK_NUM 1 +#define EFUSE_BT_REAL_BANK_CONTENT_LEN 128 +#define EFUSE_BT_REAL_CONTENT_LEN (EFUSE_BT_REAL_BANK_CONTENT_LEN * BANK_NUM) +#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */ +#define EFUSE_BT_MAX_SECTION (EFUSE_BT_MAP_LEN / 8) +#define EFUSE_PROTECT_BYTES_BANK 16 +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_BT_REAL_CONTENT_LEN) + +#define EXT_HEADER(header) ((header & 0x1F) == 0x0F) +#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) +#define GET_HDR_OFFSET_2_0(header) ((header & 0xE0) >> 5) + +#define EFUSE_REPEAT_THRESHOLD_ 3 + +#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset)) +#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset)) +#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt()) +#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt()) +#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset)) +#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset)) + +#define IS_MASKED(ic, txt, offset) (IS_MASKED_MP(ic, txt, offset)) +#define GET_MASK_ARRAY_LEN(ic, txt) (GET_MASK_ARRAY_LEN_MP(ic, txt)) +#define GET_MASK_ARRAY(ic, txt, out) do { GET_MASK_ARRAY_MP(ic, txt, out); } while (0) + +/* ********************************************* + * The following is for BT Efuse definition + * ********************************************* */ +#define EFUSE_BT_MAX_MAP_LEN 1024 +#define EFUSE_MAX_BANK 4 +#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) +/* ********************************************* + *--------------------------Define Parameters-------------------------------*/ +#define EFUSE_MAX_WORD_UNIT 4 + +/*------------------------------Define structure----------------------------*/ +typedef struct PG_PKT_STRUCT_A { + u8 offset; + u8 word_en; + u8 data[8]; + u8 word_cnts; +} PGPKT_STRUCT, *PPGPKT_STRUCT; + +typedef enum { + ERR_SUCCESS = 0, + ERR_DRIVER_FAILURE, + ERR_IO_FAILURE, + ERR_WI_TIMEOUT, + ERR_WI_BUSY, + ERR_BAD_FORMAT, + ERR_INVALID_DATA, + ERR_NOT_ENOUGH_SPACE, + ERR_WRITE_PROTECT, + ERR_READ_BACK_FAIL, + ERR_OUT_OF_RANGE +} ERROR_CODE; + +/*------------------------------Define structure----------------------------*/ +typedef struct _EFUSE_HAL { + u8 fakeEfuseBank; + u32 fakeEfuseUsedBytes; + u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]; + u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; + u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; + u32 EfuseUsedBytes; + u8 EfuseUsedPercentage; + + u16 BTEfuseUsedBytes; + u8 BTEfuseUsedPercentage; + u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + u16 fakeBTEfuseUsedBytes; + u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + /* EFUSE Configuration, initialized in HAL_CmnInitPGData(). */ + const u16 MaxSecNum_WiFi; + const u16 MaxSecNum_BT; + const u16 WordUnit; + const u16 PhysicalLen_WiFi; + const u16 PhysicalLen_BT; + const u16 LogicalLen_WiFi; + const u16 LogicalLen_BT; + const u16 BankSize; + const u16 TotalBankNum; + const u16 BankNum_WiFi; + const u16 BankNum_BT; + const u16 OOBProtectBytes; + const u16 ProtectBytes; + const u16 BankAvailBytes; + const u16 TotalAvailBytes_WiFi; + const u16 TotalAvailBytes_BT; + const u16 HeaderRetry; + const u16 DataRetry; + + ERROR_CODE Status; + +} EFUSE_HAL, *PEFUSE_HAL; + +extern u8 maskfileBuffer[64]; + +/*------------------------Export global variable----------------------------*/ +extern u8 fakeEfuseBank; +extern u32 fakeEfuseUsedBytes; +extern u8 fakeEfuseContent[]; +extern u8 fakeEfuseInitMap[]; +extern u8 fakeEfuseModifiedMap[]; + +extern u32 BTEfuseUsedBytes; +extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +extern u8 BTEfuseInitMap[]; +extern u8 BTEfuseModifiedMap[]; + +extern u32 fakeBTEfuseUsedBytes; +extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +extern u8 fakeBTEfuseInitMap[]; +extern u8 fakeBTEfuseModifiedMap[]; +/*------------------------Export global variable----------------------------*/ +u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size); +u16 efuse_bt_GetMaxSize(PADAPTER padapter); +u16 efuse_GetavailableSize(PADAPTER adapter); + +u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size); +u16 efuse_GetMaxSize(PADAPTER padapter); +u8 rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data); +u8 rtw_efuse_bt_access(PADAPTER adapter, u8 write, u16 addr, u16 cnts, u8 *data); + +u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); + +u16 Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); +u8 Efuse_CalculateWordCnts(u8 word_en); +void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ; +void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); +u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); +u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); + +void BTEfuse_PowerSwitch(PADAPTER pAdapter, u8 bWrite, u8 PwrState); +void Efuse_PowerSwitch(PADAPTER pAdapter, u8 bWrite, u8 PwrState); +int Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); +int Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); +void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); +u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); +void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); +void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value); + +VOID hal_ReadEFuse_BT_logic_map( + PADAPTER padapter, + u16 _offset, + u16 _size_byte, + u8 *pbuf +); +u8 EfusePgPacketWrite_BT( + PADAPTER pAdapter, + u8 offset, + u8 word_en, + u8 *pData, + u8 bPseudoTest); +u16 rtw_get_efuse_mask_arraylen(PADAPTER pAdapter); +void rtw_efuse_mask_array(PADAPTER pAdapter, u8 *pArray); + +#define MAC_HIDDEN_MAX_BW_NUM 8 +extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[]; +#define mac_hidden_max_bw_to_hal_bw_cap(max_bw) (((max_bw) >= MAC_HIDDEN_MAX_BW_NUM) ? 0 : _mac_hidden_max_bw_to_hal_bw_cap[(max_bw)]) + +#define MAC_HIDDEN_PROTOCOL_NUM 4 +extern const u8 _mac_hidden_proto_to_hal_proto_cap[]; +#define mac_hidden_proto_to_hal_proto_cap(proto) (((proto) >= MAC_HIDDEN_PROTOCOL_NUM) ? 0 : _mac_hidden_proto_to_hal_proto_cap[(proto)]) + +u8 mac_hidden_wl_func_to_hal_wl_func(u8 func); + +u8 rtw_efuse_file_read(PADAPTER padapter, u8 *filepatch, u8 *buf, u32 len); +u32 rtw_read_efuse_from_file(const char *path, u8 *buf, int map_size); +u32 rtw_read_macaddr_from_file(const char *path, u8 *buf); + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_event.h b/drivers/staging/rtl8821ce/include/rtw_event.h new file mode 100644 index 000000000000..a31f89ce422a --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_event.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_EVENT_H_ +#define _RTW_EVENT_H_ + + +/* +Used to report a bss has been scanned + +*/ +struct survey_event { + WLAN_BSSID_EX bss; +}; + +/* +Used to report that the requested site survey has been done. + +bss_cnt indicates the number of bss that has been reported. + +*/ +struct surveydone_event { + unsigned int bss_cnt; + +}; + +/* +Used to report the link result of joinning the given bss + +join_res: +-1: authentication fail +-2: association fail +> 0: TID + +*/ +struct joinbss_event { + struct wlan_network network; +}; + +/* +Used to report a given STA has joinned the created BSS. +It is used in AP/Ad-HoC(M) mode. + +*/ +struct stassoc_event { + unsigned char macaddr[6]; +}; + +struct stadel_event { + unsigned char macaddr[6]; + unsigned char rsvd[2]; /* for reason */ + unsigned char locally_generated; + int mac_id; +}; + +struct addba_event { + unsigned int tid; +}; + +struct wmm_event { + unsigned char wmm; +}; + + +#define GEN_EVT_CODE(event) event ## _EVT_ + +struct fwevent { + u32 parmsize; + void (*event_callback)(_adapter *dev, u8 *pbuf); +}; + +#define C2HEVENT_SZ 32 + +struct event_node { + unsigned char *node; + unsigned char evt_code; + unsigned short evt_sz; + volatile int *caller_ff_tail; + int caller_ff_sz; +}; + +struct c2hevent_queue { + volatile int head; + volatile int tail; + struct event_node nodes[C2HEVENT_SZ]; + unsigned char seq; +}; + +#define NETWORK_QUEUE_SZ 4 + +struct network_queue { + volatile int head; + volatile int tail; + WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ]; +}; + +#endif /* _WLANEVENT_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_ht.h b/drivers/staging/rtl8821ce/include/rtw_ht.h new file mode 100644 index 000000000000..baa49cae0b04 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_ht.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_HT_H_ +#define _RTW_HT_H_ + +struct ht_priv { + u8 ht_option; + u8 ampdu_enable;/* for enable Tx A-MPDU */ + u8 tx_amsdu_enable;/* for enable Tx A-MSDU */ + u8 bss_coexist;/* for 20/40 Bss coexist */ + + /* u8 baddbareq_issued[16]; */ + u32 tx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */ + u32 rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */ + + u8 rx_ampdu_min_spacing; + + u8 ch_offset;/* PRIME_CHNL_OFFSET */ + u8 sgi_20m; + u8 sgi_40m; + + /* for processing Tx A-MPDU */ + u8 agg_enable_bitmap; + /* u8 ADDBA_retry_count; */ + u8 candidate_tid_bitmap; + + u8 ldpc_cap; + u8 stbc_cap; + u8 beamform_cap; + u8 smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + + struct rtw_ieee80211_ht_cap ht_cap; + +}; + +typedef enum AGGRE_SIZE { + HT_AGG_SIZE_8K = 0, + HT_AGG_SIZE_16K = 1, + HT_AGG_SIZE_32K = 2, + HT_AGG_SIZE_64K = 3, + VHT_AGG_SIZE_128K = 4, + VHT_AGG_SIZE_256K = 5, + VHT_AGG_SIZE_512K = 6, + VHT_AGG_SIZE_1024K = 7, +} AGGRE_SIZE_E, *PAGGRE_SIZE_E; + +typedef enum _RT_HT_INF0_CAP { + RT_HT_CAP_USE_TURBO_AGGR = 0x01, + RT_HT_CAP_USE_LONG_PREAMBLE = 0x02, + RT_HT_CAP_USE_AMPDU = 0x04, + RT_HT_CAP_USE_WOW = 0x8, + RT_HT_CAP_USE_SOFTAP = 0x10, + RT_HT_CAP_USE_92SE = 0x20, + RT_HT_CAP_USE_88C_92C = 0x40, + RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, /* AP team request to reserve this bit, by Emily */ +} RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY; + +typedef enum _RT_HT_INF1_CAP { + RT_HT_CAP_USE_VIDEO_CLIENT = 0x01, + RT_HT_CAP_USE_JAGUAR_BCUT = 0x02, + RT_HT_CAP_USE_JAGUAR_CCUT = 0x04, +} RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY; + +#define LDPC_HT_ENABLE_RX BIT0 +#define LDPC_HT_ENABLE_TX BIT1 +#define LDPC_HT_TEST_TX_ENABLE BIT2 +#define LDPC_HT_CAP_TX BIT3 + +#define STBC_HT_ENABLE_RX BIT0 +#define STBC_HT_ENABLE_TX BIT1 +#define STBC_HT_TEST_TX_ENABLE BIT2 +#define STBC_HT_CAP_TX BIT3 + +#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ +#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ +#define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */ +#define BEAMFORMING_HT_BEAMFORMER_STEER_NUM (BIT4 | BIT5) +#define BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP (BIT6 | BIT7) + +/* ------------------------------------------------------------ + * The HT Control field + * ------------------------------------------------------------ */ +#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 6, 2, _val) +#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 0, 1, _val) +#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+3, 0, 1) + +/* 20/40 BSS Coexist */ +#define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val) +#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1) + +/* HT Capabilities Info field */ +#define HT_CAP_ELE_CAP_INFO(_pEleStart) ((u8 *)(_pEleStart)) +#define GET_HT_CAP_ELE_LDPC_CAP(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1) +#define GET_HT_CAP_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 1, 1) +#define GET_HT_CAP_ELE_SM_PS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 2, 2) +#define GET_HT_CAP_ELE_GREENFIELD(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 4, 1) +#define GET_HT_CAP_ELE_SHORT_GI20M(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 5, 1) +#define GET_HT_CAP_ELE_SHORT_GI40M(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 6, 1) +#define GET_HT_CAP_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 7, 1) +#define GET_HT_CAP_ELE_RX_STBC(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 0, 2) +#define GET_HT_CAP_ELE_DELAYED_BA(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 2, 1) +#define GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 3, 1) +#define GET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 4, 1) +#define GET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 6, 1) +#define GET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 7, 1) + +#define SET_HT_CAP_ELE_LDPC_CAP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val) +#define SET_HT_CAP_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 1, 1, _val) +#define SET_HT_CAP_ELE_SM_PS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 2, 2, _val) +#define SET_HT_CAP_ELE_GREENFIELD(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 4, 1, _val) +#define SET_HT_CAP_ELE_SHORT_GI20M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 5, 1, _val) +#define SET_HT_CAP_ELE_SHORT_GI40M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 6, 1, _val) +#define SET_HT_CAP_ELE_TX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 7, 1, _val) +#define SET_HT_CAP_ELE_RX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val) +#define SET_HT_CAP_ELE_DELAYED_BA(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val) +#define SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val) +#define SET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 4, 1, _val) +#define SET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 6, 1, _val) +#define SET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 7, 1, _val) + +/* A-MPDU Parameters field */ +#define HT_CAP_ELE_AMPDU_PARA(_pEleStart) (((u8 *)(_pEleStart))+2) +#define GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 0, 2) +#define GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 2, 3) + +#define HT_AMPDU_PARA_FMT "%02x " \ + "MAX AMPDU len:%u bytes, MIN MPDU Start Spacing:%u" + +#define HT_AMPDU_PARA_ARG(x) \ + *((u8 *)(x)) \ + , (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \ + , GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2) + +/* Supported MCS Set field */ +#define HT_CAP_ELE_SUP_MCS_SET(_pEleStart) (((u8 *)(_pEleStart))+3) +#define HT_CAP_ELE_RX_MCS_MAP(_pEleStart) HT_CAP_ELE_SUP_MCS_SET(_pEleStart) +#define GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(_pEleStart) LE_BITS_TO_2BYTE(((u8 *)(_pEleStart))+13, 0, 10) +#define GET_HT_CAP_ELE_TX_MCS_DEF(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 0, 1) +#define GET_HT_CAP_ELE_TRX_MCS_NEQ(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 1, 1) +#define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2) +#define GET_HT_CAP_ELE_TX_UEQM(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1) + +#define HT_SUP_MCS_SET_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x" \ + /* "\n%02x%02x%02x%02x%02x%02x" */\ + " %uMbps %s%s%s" +#define HT_SUP_MCS_SET_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ + ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9] \ + /*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\ + , GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \ + , GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \ + , GET_HT_CAP_ELE_TRX_MCS_NEQ(((u8 *)x)-3) ? "TRX_MCS_NEQ " : "" \ + , GET_HT_CAP_ELE_TX_UEQM(((u8 *)x)-3) ? "TX_UEQM " : "" + +/* TXBF Capabilities */ +#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val)) +#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val)) +#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val)) +#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val)) +#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val)) +#define SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 27, 2, ((u8)_val)) + +#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 10, 1) +#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 15, 2) +#define GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 23, 2) +#define GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 27, 2) + +/* HT Operation element */ + +#define GET_HT_OP_ELE_PRI_CHL(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 8) +#define SET_HT_OP_ELE_PRI_CHL(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 8, _val) + +/* HT Operation Info field */ +#define HT_OP_ELE_OP_INFO(_pEleStart) (((u8 *)(_pEleStart)) + 1) +#define GET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2) +#define GET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1) +#define GET_HT_OP_ELE_RIFS_MODE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1) +#define GET_HT_OP_ELE_HT_PROTECT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2) +#define GET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1) +#define GET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1) +#define GET_HT_OP_ELE_DUAL_BEACON(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1) +#define GET_HT_OP_ELE_DUAL_CTS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1) +#define GET_HT_OP_ELE_STBC_BEACON(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1) +#define GET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1) +#define GET_HT_OP_ELE_PCO_ACTIVE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1) +#define GET_HT_OP_ELE_PCO_PHASE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1) + +#define SET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val) +#define SET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val) +#define SET_HT_OP_ELE_RIFS_MODE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val) +#define SET_HT_OP_ELE_HT_PROTECT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val) +#define SET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1, _val) +#define SET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1, _val) +#define SET_HT_OP_ELE_DUAL_BEACON(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1, _val) +#define SET_HT_OP_ELE_DUAL_CTS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1, _val) +#define SET_HT_OP_ELE_STBC_BEACON(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1, _val) +#define SET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1, _val) +#define SET_HT_OP_ELE_PCO_ACTIVE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1, _val) +#define SET_HT_OP_ELE_PCO_PHASE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1, _val) + +#endif /* _RTL871X_HT_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_io.h b/drivers/staging/rtl8821ce/include/rtw_io.h new file mode 100644 index 000000000000..5313b6f73694 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_io.h @@ -0,0 +1,404 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _RTW_IO_H_ +#define _RTW_IO_H_ + +#define NUM_IOREQ 8 + + #define MAX_PROT_SZ (64-16) + +#define _IOREADY 0 +#define _IO_WAIT_COMPLETE 1 +#define _IO_WAIT_RSP 2 + +/* IO COMMAND TYPE */ +#define _IOSZ_MASK_ (0x7F) +#define _IO_WRITE_ BIT(7) +#define _IO_FIXED_ BIT(8) +#define _IO_BURST_ BIT(9) +#define _IO_BYTE_ BIT(10) +#define _IO_HW_ BIT(11) +#define _IO_WORD_ BIT(12) +#define _IO_SYNC_ BIT(13) +#define _IO_CMDMASK_ (0x1F80) + +/* + For prompt mode accessing, caller shall free io_req + Otherwise, io_handler will free io_req +*/ + +/* IO STATUS TYPE */ +#define _IO_ERR_ BIT(2) +#define _IO_SUCCESS_ BIT(1) +#define _IO_DONE_ BIT(0) + +#define IO_RD32 (_IO_SYNC_ | _IO_WORD_) +#define IO_RD16 (_IO_SYNC_ | _IO_HW_) +#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) + +#define IO_RD32_ASYNC (_IO_WORD_) +#define IO_RD16_ASYNC (_IO_HW_) +#define IO_RD8_ASYNC (_IO_BYTE_) + +#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) +#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) +#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) + +#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) +#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) +#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) + +/* + + Only Sync. burst accessing is provided. + +*/ + +#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) +#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ((x) & _IOSZ_MASK_)) + +/* below is for the intf_option bit defition... */ + +#define _INTF_ASYNC_ BIT(0) /* support async io */ + +struct intf_priv; +struct intf_hdl; +struct io_queue; + +struct _io_ops { + u8(*_read8)(struct intf_hdl *pintfhdl, u32 addr); + u16(*_read16)(struct intf_hdl *pintfhdl, u32 addr); + u32(*_read32)(struct intf_hdl *pintfhdl, u32 addr); + + int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); + + int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + + void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + + void (*_sync_irp_protocol_rw)(struct io_queue *pio_q); + + u32(*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); + + u32(*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + u32(*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + + u32(*_write_scsi)(struct intf_hdl *pintfhdl, u32 cnt, u8 *pmem); + + void (*_read_port_cancel)(struct intf_hdl *pintfhdl); + void (*_write_port_cancel)(struct intf_hdl *pintfhdl); + +}; + +struct io_req { + _list list; + u32 addr; + volatile u32 val; + u32 command; + u32 status; + u8 *pbuf; + _sema sema; + + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt); + u8 *cnxt; +}; + +struct intf_hdl { + _adapter *padapter; + struct dvobj_priv *pintf_dev;/* pointer to &(padapter->dvobjpriv); */ + + struct _io_ops io_ops; +}; + +struct reg_protocol_rd { + +#ifdef __LITTLE_ENDIAN + + /* DW1 */ + u32 NumOfTrans:4; + u32 Reserved1:4; + u32 Reserved2:24; + /* DW2 */ + u32 ByteCount:7; + u32 WriteEnable:1; /* 0:read, 1:write */ + u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ + u32 BurstMode:1; + u32 Byte1Access:1; + u32 Byte2Access:1; + u32 Byte4Access:1; + u32 Reserved3:3; + u32 Reserved4:16; + /* DW3 */ + u32 BusAddress; + /* DW4 */ + /* u32 Value; */ +#else + + /* DW1 */ + u32 Reserved1:4; + u32 NumOfTrans:4; + + u32 Reserved2:24; + + /* DW2 */ + u32 WriteEnable:1; + u32 ByteCount:7; + + u32 Reserved3:3; + u32 Byte4Access:1; + + u32 Byte2Access:1; + u32 Byte1Access:1; + u32 BurstMode:1; + u32 FixOrContinuous:1; + + u32 Reserved4:16; + + /* DW3 */ + u32 BusAddress; + + /* DW4 */ + /* u32 Value; */ + +#endif + +}; + +struct reg_protocol_wt { + +#ifdef __LITTLE_ENDIAN + + /* DW1 */ + u32 NumOfTrans:4; + u32 Reserved1:4; + u32 Reserved2:24; + /* DW2 */ + u32 ByteCount:7; + u32 WriteEnable:1; /* 0:read, 1:write */ + u32 FixOrContinuous:1; /* 0:continuous, 1: Fix */ + u32 BurstMode:1; + u32 Byte1Access:1; + u32 Byte2Access:1; + u32 Byte4Access:1; + u32 Reserved3:3; + u32 Reserved4:16; + /* DW3 */ + u32 BusAddress; + /* DW4 */ + u32 Value; + +#else + /* DW1 */ + u32 Reserved1:4; + u32 NumOfTrans:4; + + u32 Reserved2:24; + + /* DW2 */ + u32 WriteEnable:1; + u32 ByteCount:7; + + u32 Reserved3:3; + u32 Byte4Access:1; + + u32 Byte2Access:1; + u32 Byte1Access:1; + u32 BurstMode:1; + u32 FixOrContinuous:1; + + u32 Reserved4:16; + + /* DW3 */ + u32 BusAddress; + + /* DW4 */ + u32 Value; + +#endif + +}; +#define MAX_CONTINUAL_IO_ERR 4 + +int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj); +void rtw_reset_continual_io_error(struct dvobj_priv *dvobj); + +/* +Below is the data structure used by _io_handler + +*/ + +struct io_queue { + _lock lock; + _list free_ioreqs; + _list pending; /* The io_req list that will be served in the single protocol read/write. */ + _list processing; + u8 *free_ioreqs_buf; /* 4-byte aligned */ + u8 *pallocated_free_ioreqs_buf; + struct intf_hdl intf; +}; + +struct io_priv { + + _adapter *padapter; + + struct intf_hdl intf; + +}; + +extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); +extern void sync_ioreq_enqueue(struct io_req *preq, struct io_queue *ioqueue); +extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); + +extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue); +extern struct io_req *alloc_ioreq(struct io_queue *pio_q); + +extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl); +extern void unregister_intf_hdl(struct intf_hdl *pintfhdl); + +extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); + +extern u8 _rtw_read8(_adapter *adapter, u32 addr); +extern u16 _rtw_read16(_adapter *adapter, u32 addr); +extern u32 _rtw_read32(_adapter *adapter, u32 addr); +extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void _rtw_read_port_cancel(_adapter *adapter); + +extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val); +extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val); +extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val); +extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata); + +extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val); +extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val); +extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val); + +extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms); +extern void _rtw_write_port_cancel(_adapter *adapter); + +#define match_read_sniff_ranges(addr, len) _FALSE +#define match_write_sniff_ranges(addr, len) _FALSE +#define match_rf_read_sniff_ranges(path, addr, mask) _FALSE +#define match_rf_write_sniff_ranges(path, addr, mask) _FALSE +#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) +#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) +#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) +#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) +#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) +#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) + +#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) +#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) +#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) +#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data)) + +#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) +#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) +#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) + +#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem)) +#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) +#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) +#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) + + +extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem); + +/* ioreq */ +extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval); +extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval); +extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval); +extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val); +extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val); +extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val); + +extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); + +extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); + +extern void async_write8(_adapter *adapter, u32 addr, u8 val, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern void async_write16(_adapter *adapter, u32 addr, u16 val, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern void async_write32(_adapter *adapter, u32 addr, u32 val, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); + +extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); + +int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter, struct _io_ops *pops)); + +extern uint alloc_io_queue(_adapter *adapter); +extern void free_io_queue(_adapter *adapter); +extern void async_bus_io(struct io_queue *pio_q); +extern void bus_sync_io(struct io_queue *pio_q); +extern u32 _ioreq2rwmem(struct io_queue *pio_q); +extern void dev_power_down(_adapter *Adapter, u8 bpwrup); + +/* +#define RTL_R8(reg) rtw_read8(padapter, reg) +#define RTL_R16(reg) rtw_read16(padapter, reg) +#define RTL_R32(reg) rtw_read32(padapter, reg) +#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8) +#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16) +#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32) +*/ + +/* +#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8) +#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16) +#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32) + +#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32) +#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg) +*/ + +#define PlatformEFIOWrite1Byte(_a, _b, _c) \ + rtw_write8(_a, _b, _c) +#define PlatformEFIOWrite2Byte(_a, _b, _c) \ + rtw_write16(_a, _b, _c) +#define PlatformEFIOWrite4Byte(_a, _b, _c) \ + rtw_write32(_a, _b, _c) + +#define PlatformEFIORead1Byte(_a, _b) \ + rtw_read8(_a, _b) +#define PlatformEFIORead2Byte(_a, _b) \ + rtw_read16(_a, _b) +#define PlatformEFIORead4Byte(_a, _b) \ + rtw_read32(_a, _b) + +#endif /* _RTL8711_IO_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_ioctl.h b/drivers/staging/rtl8821ce/include/rtw_ioctl.h new file mode 100644 index 000000000000..983db5b7f350 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_ioctl.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_IOCTL_H_ +#define _RTW_IOCTL_H_ + +/* 00 - Success +* 11 - Error */ +#define STATUS_SUCCESS (0x00000000L) +#define STATUS_PENDING (0x00000103L) + +#define STATUS_UNSUCCESSFUL (0xC0000001L) +#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) +#define STATUS_NOT_SUPPORTED (0xC00000BBL) + +#define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS) +#define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING) +#define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L) +#define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L) +#define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L) +#define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L) + +#define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL) +#define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) +#define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L) +#define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L) +#define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L) +#define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L) +#define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L) +#define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L) +#define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L) +#define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL) +#define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL) +#define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL) +#define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL) +#define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL) +#define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED) +#define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL) +#define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L) +#define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L) +#define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L) +#define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L) +#define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L) +#define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L) +#define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L) +#define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L) +#define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L) +#define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L) +#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL) +#define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL) +#define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL) +#define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL) +#define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL) +#define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL) + +#define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L) +#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) +#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) +#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) +#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) /* cause 27 */ +#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) /* cause 35, 45 */ +#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) /* cause 37 */ +#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) /* cause 49 */ +#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) /* cause 93 */ +#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) /* cause 3 */ + +#ifndef OID_802_11_CAPABILITY + #define OID_802_11_CAPABILITY 0x0d010122 +#endif + +#ifndef OID_802_11_PMKID + #define OID_802_11_PMKID 0x0d010123 +#endif + +/* For DDK-defined OIDs */ +#define OID_NDIS_SEG1 0x00010100 +#define OID_NDIS_SEG2 0x00010200 +#define OID_NDIS_SEG3 0x00020100 +#define OID_NDIS_SEG4 0x01010100 +#define OID_NDIS_SEG5 0x01020100 +#define OID_NDIS_SEG6 0x01020200 +#define OID_NDIS_SEG7 0xFD010100 +#define OID_NDIS_SEG8 0x0D010100 +#define OID_NDIS_SEG9 0x0D010200 +#define OID_NDIS_SEG10 0x0D020200 + +#define SZ_OID_NDIS_SEG1 23 +#define SZ_OID_NDIS_SEG2 3 +#define SZ_OID_NDIS_SEG3 6 +#define SZ_OID_NDIS_SEG4 6 +#define SZ_OID_NDIS_SEG5 4 +#define SZ_OID_NDIS_SEG6 8 +#define SZ_OID_NDIS_SEG7 7 +#define SZ_OID_NDIS_SEG8 36 +#define SZ_OID_NDIS_SEG9 24 +#define SZ_OID_NDIS_SEG10 19 + +/* For Realtek-defined OIDs */ +#define OID_MP_SEG1 0xFF871100 +#define OID_MP_SEG2 0xFF818000 + +#define OID_MP_SEG3 0xFF818700 +#define OID_MP_SEG4 0xFF011100 + +enum oid_type { + QUERY_OID, + SET_OID +}; + +struct oid_funs_node { + unsigned int oid_start; /* the starting number for OID */ + unsigned int oid_end; /* the ending number for OID */ + struct oid_obj_priv *node_array; + unsigned int array_sz; /* the size of node_array */ + int query_counter; /* count the number of query hits for this segment */ + int set_counter; /* count the number of set hits for this segment */ +}; + +struct oid_par_priv { + void *adapter_context; + NDIS_OID oid; + void *information_buf; + u32 information_buf_len; + u32 *bytes_rw; + u32 *bytes_needed; + enum oid_type type_of_oid; + u32 dbg; +}; + +struct oid_obj_priv { + unsigned char dbg; /* 0: without OID debug message 1: with OID debug message */ + NDIS_STATUS(*oidfuns)(struct oid_par_priv *poid_par_priv); +}; + + +extern struct iw_handler_def rtw_handlers_def; + +extern void rtw_request_wps_pbc_event(_adapter *padapter); + +extern NDIS_STATUS drv_query_info( + IN _nic_hdl MiniportAdapterContext, + IN NDIS_OID Oid, + IN void *InformationBuffer, + IN u32 InformationBufferLength, + OUT u32 *BytesWritten, + OUT u32 *BytesNeeded +); + +extern NDIS_STATUS drv_set_info( + IN _nic_hdl MiniportAdapterContext, + IN NDIS_OID Oid, + IN void *InformationBuffer, + IN u32 InformationBufferLength, + OUT u32 *BytesRead, + OUT u32 *BytesNeeded +); + +#endif /* #ifndef __INC_CEINFO_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_ioctl_query.h b/drivers/staging/rtl8821ce/include/rtw_ioctl_query.h new file mode 100644 index 000000000000..69b81d98a4ba --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_ioctl_query.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_IOCTL_QUERY_H_ +#define _RTW_IOCTL_QUERY_H_ + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_ioctl_rtl.h b/drivers/staging/rtl8821ce/include/rtw_ioctl_rtl.h new file mode 100644 index 000000000000..176dbe237586 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_ioctl_rtl.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_IOCTL_RTL_H_ +#define _RTW_IOCTL_RTL_H_ + +/* ************** oid_rtl_seg_01_01 ************** */ +NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv *poid_par_priv);/* 84 */ +NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv *poid_par_priv); /* 8a */ +NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv *poid_par_priv); /* 8b */ + +NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv *poid_par_priv);/* 93 */ +NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv *poid_par_priv); + +/* ************** oid_rtl_seg_01_03 section start ************** */ +NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv *poid_par_priv); + +/* oid_rtl_seg_01_11 */ +NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv *poid_par_priv); + +/* ************** oid_rtl_seg_03_00 section start ************** */ +NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv *poid_par_priv); + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_ioctl_set.h b/drivers/staging/rtl8821ce/include/rtw_ioctl_set.h new file mode 100644 index 000000000000..f1fad86db34f --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_ioctl_set.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_IOCTL_SET_H_ +#define __RTW_IOCTL_SET_H_ + +typedef u8 NDIS_802_11_PMKID_VALUE[16]; + +typedef struct _BSSIDInfo { + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_PMKID_VALUE PMKID; +} BSSIDInfo, *PBSSIDInfo; + +u8 rtw_set_802_11_add_key(_adapter *padapter, NDIS_802_11_KEY *key); +u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode); +u8 rtw_set_802_11_bssid(_adapter *padapter, u8 *bssid); +u8 rtw_set_802_11_add_wep(_adapter *padapter, NDIS_802_11_WEP *wep); +u8 rtw_set_802_11_disassociate(_adapter *padapter); +u8 rtw_set_802_11_bssid_list_scan(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num, struct rtw_ieee80211_channel *ch, int ch_num); +u8 rtw_set_802_11_infrastructure_mode(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); +u8 rtw_set_802_11_remove_wep(_adapter *padapter, u32 keyindex); +u8 rtw_set_802_11_ssid(_adapter *padapter, NDIS_802_11_SSID *ssid); +u8 rtw_set_802_11_connect(_adapter *padapter, u8 *bssid, NDIS_802_11_SSID *ssid); +u8 rtw_set_802_11_remove_key(_adapter *padapter, NDIS_802_11_REMOVE_KEY *key); + +u8 rtw_validate_bssid(u8 *bssid); +u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); + +u16 rtw_get_cur_max_rate(_adapter *adapter); +int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode); +int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan); +int rtw_set_country(_adapter *adapter, const char *country_code); +int rtw_set_band(_adapter *adapter, u8 band); + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_iol.h b/drivers/staging/rtl8821ce/include/rtw_iol.h new file mode 100644 index 000000000000..82d3a00e84b9 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_iol.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_IOL_H_ +#define __RTW_IOL_H_ + +struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter); +int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len); +int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary); +int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); +bool rtw_IOL_applied(ADAPTER *adapter); +int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us); +int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms); +int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame); + +#ifdef CONFIG_IOL_NEW_GENERATION +#define IOREG_CMD_END_LEN 4 + +struct ioreg_cfg { + u8 length; + u8 cmd_id; + u16 address; + u32 data; + u32 mask; +}; +enum ioreg_cmd { + IOREG_CMD_LLT = 0x01, + IOREG_CMD_REFUSE = 0x02, + IOREG_CMD_EFUSE_PATH = 0x03, + IOREG_CMD_WB_REG = 0x04, + IOREG_CMD_WW_REG = 0x05, + IOREG_CMD_WD_REG = 0x06, + IOREG_CMD_W_RF = 0x07, + IOREG_CMD_DELAY_US = 0x10, + IOREG_CMD_DELAY_MS = 0x11, + IOREG_CMD_END = 0xFF, +}; +void read_efuse_from_txpktbuf(ADAPTER *adapter, int bcnhead, u8 *content, u16 *size); + +int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask); +int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask); +int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask); +int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask); +#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), (mask)) +#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), (mask)) +#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value, mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), (mask)) +#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value, mask) _rtw_IOL_append_WRF_cmd((xmit_frame), (rf_path), (addr), (value), (mask)) + +u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame); +void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter, int buf_len, u8 *pbuf); + +#ifdef CONFIG_IOL_IOREG_CFG_DBG +struct cmd_cmp { + u16 addr; + u32 value; +}; +#endif + +#else /* CONFIG_IOL_NEW_GENERATION */ + +typedef struct _io_offload_cmd { + u8 rsvd0; + u8 cmd; + u16 address; + u32 value; +} IO_OFFLOAD_CMD, IOL_CMD; + +#define IOL_CMD_LLT 0x00 +/* #define IOL_CMD_R_EFUSE 0x01 */ +#define IOL_CMD_WB_REG 0x02 +#define IOL_CMD_WW_REG 0x03 +#define IOL_CMD_WD_REG 0x04 +/* #define IOL_CMD_W_RF 0x05 */ +#define IOL_CMD_DELAY_US 0x80 +#define IOL_CMD_DELAY_MS 0x81 +/* #define IOL_CMD_DELAY_S 0x82 */ +#define IOL_CMD_END 0x83 + +/***************************************************** +CMD Address Value +(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB) +****************************************************** +IOL_CMD_LLT - B7: PGBNDY +IOL_CMD_R_EFUSE - - +IOL_CMD_WB_REG 0x0~0xFFFF B7 +IOL_CMD_WW_REG 0x0~0xFFFF B6~B7 +IOL_CMD_WD_REG 0x0~0xFFFF B4~B7 +IOL_CMD_W_RF RF Reg B5~B7 +IOL_CMD_DELAY_US - B6~B7 +IOL_CMD_DELAY_MS - B6~B7 +IOL_CMD_DELAY_S - B6~B7 +IOL_CMD_END - - +******************************************************/ +int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value); +int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value); +int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value); + +int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms); +int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms); + +#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value)) +#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value)) +#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value)) +#endif /* CONFIG_IOL_NEW_GENERATION */ + +#endif /* __RTW_IOL_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_mcc.h b/drivers/staging/rtl8821ce/include/rtw_mcc.h new file mode 100644 index 000000000000..69ed6f0174d6 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mcc.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2015 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + ******************************************************************************/ diff --git a/drivers/staging/rtl8821ce/include/rtw_mem.h b/drivers/staging/rtl8821ce/include/rtw_mem.h new file mode 100644 index 000000000000..791bbb7f41ec --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mem.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MEM_H__ +#define __RTW_MEM_H__ + +#include <drv_conf.h> +#include <basic_types.h> +#include <osdep_service.h> + +#ifdef CONFIG_PLATFORM_MSTAR_HIGH + #define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */ +#else + #define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */ +#endif /* CONFIG_PLATFORM_MSTAR_HIGH */ +#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16 + +u16 rtw_rtkm_get_buff_size(void); +u8 rtw_rtkm_get_nr_recv_skb(void); +struct u8 *rtw_alloc_revcbuf_premem(void); +struct sk_buff *rtw_alloc_skb_premem(u16 in_size); +int rtw_free_skb_premem(struct sk_buff *pskb); + +#endif /* __RTW_MEM_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_mi.h b/drivers/staging/rtl8821ce/include/rtw_mi.h new file mode 100644 index 000000000000..c1082f468ecb --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mi.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MI_H_ +#define __RTW_MI_H_ + +void rtw_mi_update_union_chan_inf(_adapter *adapter, u8 ch, u8 offset , u8 bw); +int rtw_mi_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); +int rtw_mi_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); + +struct mi_state { + u8 sta_num; /*WIFI_FW_STATION_STATE*/ + u8 ld_sta_num; /*WIFI_FW_STATION_STATE |_FW_LINKED*/ + u8 lg_sta_num; /*WIFI_FW_STATION_STATE |_FW_UNDER_LINKING*/ + u8 ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED*/ + u8 ld_ap_num; /*WIFI_FW_AP_STATE|_FW_LINKED && asoc_sta_count > 2*/ + u8 adhoc_num; /* WIFI_FW_ADHOC_STATE */ + u8 ld_adhoc_num; /* WIFI_FW_ADHOC_STATE && asoc_sta_count > 2 */ + u8 uwps_num; /*WIFI_UNDER_WPS*/ + + + u8 union_ch; + u8 union_bw; + u8 union_offset; +}; + +#define MSTATE_STA_NUM(_mstate) ((_mstate)->sta_num) +#define MSTATE_STA_LD_NUM(_mstate) ((_mstate)->ld_sta_num) +#define MSTATE_STA_LG_NUM(_mstate) ((_mstate)->lg_sta_num) +#define MSTATE_AP_NUM(_mstate) ((_mstate)->ap_num) +#define MSTATE_AP_LD_NUM(_mstate) ((_mstate)->ld_ap_num) +#define MSTATE_ADHOC_NUM(_mstate) ((_mstate)->adhoc_num) +#define MSTATE_ADHOC_LD_NUM(_mstate) ((_mstate)->ld_adhoc_num) +#define MSTATE_WPS_NUM(_mstate) ((_mstate)->uwps_num) + +#define MSTATE_ROCH_NUM(_mstate) 0 + +#define MSTATE_MGMT_TX_NUM(_mstate) 0 + +#define MSTATE_U_CH(_mstate) ((_mstate)->union_ch) +#define MSTATE_U_BW(_mstate) ((_mstate)->union_bw) +#define MSTATE_U_OFFSET(_mstate) ((_mstate)->union_offset) + +#define rtw_mi_get_union_chan(adapter) adapter_to_dvobj(adapter)->iface_state.union_ch +#define rtw_mi_get_union_bw(adapter) adapter_to_dvobj(adapter)->iface_state.union_bw +#define rtw_mi_get_union_offset(adapter) adapter_to_dvobj(adapter)->iface_state.union_offset + +#define rtw_mi_get_assoced_sta_num(adapter) DEV_STA_LD_NUM(adapter_to_dvobj(adapter)) +#define rtw_mi_get_ap_num(adapter) DEV_AP_NUM(adapter_to_dvobj(adapter)) + +/* For now, not return union_ch/bw/offset */ +void rtw_mi_status(_adapter *adapter, struct mi_state *mstate); +void rtw_mi_status_no_self(_adapter *adapter, struct mi_state *mstate); + +void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); + +u8 rtw_mi_mp_mode_check(_adapter *padapter); + +u8 rtw_mi_netif_stop_queue(_adapter *padapter, bool carrier_off); +u8 rtw_mi_buddy_netif_stop_queue(_adapter *padapter, bool carrier_off); + +u8 rtw_mi_netif_wake_queue(_adapter *padapter); +u8 rtw_mi_buddy_netif_wake_queue(_adapter *padapter); + +u8 rtw_mi_netif_carrier_on(_adapter *padapter); +u8 rtw_mi_buddy_netif_carrier_on(_adapter *padapter); + +void rtw_mi_scan_abort(_adapter *adapter, bool bwait); +void rtw_mi_buddy_scan_abort(_adapter *adapter, bool bwait); +void rtw_mi_start_drv_threads(_adapter *adapter); +void rtw_mi_buddy_start_drv_threads(_adapter *adapter); +void rtw_mi_stop_drv_threads(_adapter *adapter); +void rtw_mi_buddy_stop_drv_threads(_adapter *adapter); +void rtw_mi_cancel_all_timer(_adapter *adapter); +void rtw_mi_buddy_cancel_all_timer(_adapter *adapter); +void rtw_mi_reset_drv_sw(_adapter *adapter); +void rtw_mi_buddy_reset_drv_sw(_adapter *adapter); + +extern void rtw_intf_start(_adapter *adapter); +extern void rtw_intf_stop(_adapter *adapter); +void rtw_mi_intf_start(_adapter *adapter); +void rtw_mi_buddy_intf_start(_adapter *adapter); +void rtw_mi_intf_stop(_adapter *adapter); +void rtw_mi_buddy_intf_stop(_adapter *adapter); + +void rtw_mi_suspend_free_assoc_resource(_adapter *adapter); +void rtw_mi_buddy_suspend_free_assoc_resource(_adapter *adapter); + +#define rtw_mi_set_scan_deny(adapter, ms) do {} while (0) +#define rtw_mi_buddy_set_scan_deny(adapter, ms) do {} while (0) + +u8 rtw_mi_is_scan_deny(_adapter *adapter); +u8 rtw_mi_buddy_is_scan_deny(_adapter *adapter); + +u8 rtw_mi_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); +u8 rtw_mi_buddy_issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); + +void rtw_mi_beacon_update(_adapter *padapter); +void rtw_mi_buddy_beacon_update(_adapter *padapter); + +void rtw_mi_hal_dump_macaddr(_adapter *padapter); +void rtw_mi_buddy_hal_dump_macaddr(_adapter *padapter); + +void rtw_mi_xmit_tasklet_schedule(_adapter *padapter); +void rtw_mi_buddy_xmit_tasklet_schedule(_adapter *padapter); + +u8 rtw_mi_busy_traffic_check(_adapter *padapter, bool check_sc_interval); +u8 rtw_mi_buddy_busy_traffic_check(_adapter *padapter, bool check_sc_interval); + +u8 rtw_mi_check_mlmeinfo_state(_adapter *padapter, u32 state); +u8 rtw_mi_buddy_check_mlmeinfo_state(_adapter *padapter, u32 state); + +u8 rtw_mi_check_fwstate(_adapter *padapter, sint state); +u8 rtw_mi_buddy_check_fwstate(_adapter *padapter, sint state); +enum { + MI_LINKED, + MI_ASSOC, + MI_UNDER_WPS, + MI_AP_MODE, + MI_AP_ASSOC, + MI_ADHOC, + MI_ADHOC_ASSOC, + MI_STA_NOLINK, /* this is misleading, but not used now */ + MI_STA_LINKED, + MI_STA_LINKING, +}; +u8 rtw_mi_check_status(_adapter *adapter, u8 type); + +void dump_dvobj_mi_status(void *sel, const char *fun_name, _adapter *adapter); +void dump_mi_status(void *sel, struct dvobj_priv *dvobj); + +u8 rtw_mi_traffic_statistics(_adapter *padapter); +u8 rtw_mi_check_miracast_enabled(_adapter *padapter); + + +void rtw_mi_adapter_reset(_adapter *padapter); +void rtw_mi_buddy_adapter_reset(_adapter *padapter); + +u8 rtw_mi_dynamic_check_timer_handlder(_adapter *padapter); +u8 rtw_mi_buddy_dynamic_check_timer_handlder(_adapter *padapter); + +u8 rtw_mi_dev_unload(_adapter *padapter); +u8 rtw_mi_buddy_dev_unload(_adapter *padapter); + +extern void rtw_iface_dynamic_chk_wk_hdl(_adapter *padapter); +u8 rtw_mi_dynamic_chk_wk_hdl(_adapter *padapter); +u8 rtw_mi_buddy_dynamic_chk_wk_hdl(_adapter *padapter); + +u8 rtw_mi_os_xmit_schedule(_adapter *padapter); +u8 rtw_mi_buddy_os_xmit_schedule(_adapter *padapter); + +u8 rtw_mi_report_survey_event(_adapter *padapter, union recv_frame *precv_frame); +u8 rtw_mi_buddy_report_survey_event(_adapter *padapter, union recv_frame *precv_frame); + +extern void sreset_start_adapter(_adapter *padapter); +extern void sreset_stop_adapter(_adapter *padapter); +u8 rtw_mi_sreset_adapter_hdl(_adapter *padapter, u8 bstart); +u8 rtw_mi_buddy_sreset_adapter_hdl(_adapter *padapter, u8 bstart); + +u8 rtw_mi_tx_beacon_hdl(_adapter *padapter); +u8 rtw_mi_buddy_tx_beacon_hdl(_adapter *padapter); + +u8 rtw_mi_set_tx_beacon_cmd(_adapter *padapter); +u8 rtw_mi_buddy_set_tx_beacon_cmd(_adapter *padapter); + +u8 rtw_mi_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); +u8 rtw_mi_buddy_p2p_chk_state(_adapter *padapter, enum P2P_STATE p2p_state); +u8 rtw_mi_stay_in_p2p_mode(_adapter *padapter); +u8 rtw_mi_buddy_stay_in_p2p_mode(_adapter *padapter); + +_adapter *rtw_get_iface_by_id(_adapter *padapter, u8 iface_id); +_adapter *rtw_get_iface_by_macddr(_adapter *padapter, u8 *mac_addr); +_adapter *rtw_get_iface_by_hwport(_adapter *padapter, u8 hw_port); + +void rtw_mi_buddy_clone_bcmc_packet(_adapter *padapter, union recv_frame *precvframe, u8 *pphy_status); + +/*API be create temporary for MI, caller is interrupt-handler, PCIE's interrupt handler cannot apply to multi-AP*/ +_adapter *rtw_mi_get_ap_adapter(_adapter *padapter); + +void rtw_mi_update_ap_bmc_camid(_adapter *padapter, u8 camid_a, u8 camid_b); + +#endif /*__RTW_MI_H_*/ diff --git a/drivers/staging/rtl8821ce/include/rtw_mlme.h b/drivers/staging/rtl8821ce/include/rtw_mlme.h new file mode 100644 index 000000000000..901b9e36731c --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mlme.h @@ -0,0 +1,885 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MLME_H_ +#define __RTW_MLME_H_ + +#define MAX_BSS_CNT 128 +/* #define MAX_JOIN_TIMEOUT 2000 */ +/* #define MAX_JOIN_TIMEOUT 2500 */ +#define MAX_JOIN_TIMEOUT 6500 + +/* Commented by Albert 20101105 + * Increase the scanning timeout because of increasing the SURVEY_TO value. */ + +#define SCANNING_TIMEOUT 8000 + +#ifdef PALTFORM_OS_WINCE +#define SCANQUEUE_LIFETIME 12000000 /* unit:us */ +#else +#define SCANQUEUE_LIFETIME 20000 /* 20sec, unit:msec */ +#endif + +#define WIFI_NULL_STATE 0x00000000 +#define WIFI_ASOC_STATE 0x00000001 /* Linked */ +#define WIFI_REASOC_STATE 0x00000002 +#define WIFI_SLEEP_STATE 0x00000004 +#define WIFI_STATION_STATE 0x00000008 +#define WIFI_AP_STATE 0x00000010 +#define WIFI_ADHOC_STATE 0x00000020 +#define WIFI_ADHOC_MASTER_STATE 0x00000040 +#define WIFI_UNDER_LINKING 0x00000080 +#define WIFI_UNDER_WPS 0x00000100 +/*#define WIFI_UNDEFINED_STATE 0x00000200*/ +#define WIFI_STA_ALIVE_CHK_STATE 0x00000400 +#define WIFI_SITE_MONITOR 0x00000800 /* under site surveying */ +#define WIFI_WDS 0x00001000 +#define WIFI_WDS_RX_BEACON 0x00002000 /* already rx WDS AP beacon */ +#define WIFI_AUTOCONF 0x00004000 +#define WIFI_AUTOCONF_IND 0x00008000 +#define WIFI_MP_STATE 0x00010000 +#define WIFI_MP_CTX_BACKGROUND 0x00020000 /* in continuous tx background */ +#define WIFI_MP_CTX_ST 0x00040000 /* in continuous tx with single-tone */ +#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 /* pending in continuous tx background due to out of skb */ +#define WIFI_MP_CTX_CCK_HW 0x00100000 /* in continuous tx */ +#define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continuous tx with carrier suppression */ +#define WIFI_MP_LPBK_STATE 0x00400000 +#define WIFI_OP_CH_SWITCHING 0x00800000 +/*#define WIFI_UNDEFINED_STATE 0x01000000*/ +/*#define WIFI_UNDEFINED_STATE 0x02000000*/ +/*#define WIFI_UNDEFINED_STATE 0x04000000*/ +/*#define WIFI_UNDEFINED_STATE 0x08000000*/ +/*#define WIFI_UNDEFINED_STATE 0x10000000*/ +/*#define WIFI_UNDEFINED_STATE 0x20000000*/ +/*#define WIFI_UNDEFINED_STATE 0x40000000*/ +#define WIFI_MONITOR_STATE 0x80000000 + +#define MIRACAST_DISABLED 0 +#define MIRACAST_SOURCE BIT0 +#define MIRACAST_SINK BIT1 + +#define MIRACAST_MODE_REVERSE(mode) \ + ((((mode) & MIRACAST_SOURCE) ? MIRACAST_SINK : 0) | (((mode) & MIRACAST_SINK) ? MIRACAST_SOURCE : 0)) + +bool is_miracast_enabled(_adapter *adapter); +bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode); +const char *get_miracast_mode_str(int mode); +void rtw_wfd_st_switch(struct sta_info *sta, bool on); + +#define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv)) + +#define MLME_IS_STA(adapter) (MLME_STATE((adapter)) & WIFI_STATION_STATE) +#define MLME_IS_AP(adapter) (MLME_STATE((adapter)) & WIFI_AP_STATE) +#define MLME_IS_ADHOC(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_STATE) +#define MLME_IS_ADHOC_MASTER(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_MASTER_STATE) +#define MLME_IS_MONITOR(adapter) (MLME_STATE((adapter)) & WIFI_MONITOR_STATE) +#define MLME_IS_MP(adapter) (MLME_STATE((adapter)) & WIFI_MP_STATE) + #define MLME_IS_PD(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_DEVICE) + #define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT) + #define MLME_IS_GO(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_GO) + +#define MLME_IS_ROCH(adapter) 0 + +#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE) +#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK) + +#define MLME_IS_MGMT_TX(adapter) 0 + +#define MLME_STATE_FMT "%s%s%s%s%s%s%s%s%s%s%s%s" +#define MLME_STATE_ARG(adapter) \ + MLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? " GC" : " STA") : \ + MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : \ + MLME_IS_ADHOC((adapter)) ? " ADHOC" : \ + MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : \ + MLME_IS_MONITOR((adapter)) ? " MONITOR" : \ + MLME_IS_MP((adapter)) ? " MP" : "", \ + MLME_IS_PD((adapter)) ? " PD" : "", \ + MLME_IS_MSRC((adapter)) ? " MSRC" : "", \ + MLME_IS_MSINK((adapter)) ? " MSINK" : "", \ + (MLME_STATE((adapter)) & WIFI_SITE_MONITOR) ? " SCAN" : "", \ + (MLME_STATE((adapter)) & WIFI_UNDER_LINKING) ? " LINKING" : "", \ + (MLME_STATE((adapter)) & WIFI_ASOC_STATE) ? " ASOC" : "", \ + (MLME_STATE((adapter)) & WIFI_OP_CH_SWITCHING) ? " OP_CH_SW" : "", \ + (MLME_STATE((adapter)) & WIFI_UNDER_WPS) ? " WPS" : "", \ + MLME_IS_ROCH((adapter)) ? " ROCH" : "", \ + MLME_IS_MGMT_TX((adapter)) ? " MGMT_TX" : "", \ + (MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : "" + +#define _FW_UNDER_LINKING WIFI_UNDER_LINKING +#define _FW_LINKED WIFI_ASOC_STATE +#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR + +enum dot11AuthAlgrthmNum { + dot11AuthAlgrthm_Open = 0, + dot11AuthAlgrthm_Shared, + dot11AuthAlgrthm_8021X, + dot11AuthAlgrthm_Auto, + dot11AuthAlgrthm_WAPI, + dot11AuthAlgrthm_MaxNum +}; + +/* Scan type including active and passive scan. */ +typedef enum _RT_SCAN_TYPE { + SCAN_PASSIVE, + SCAN_ACTIVE, + SCAN_MIX, +} RT_SCAN_TYPE, *PRT_SCAN_TYPE; + +#define WIFI_FREQUENCY_BAND_AUTO 0 +#define WIFI_FREQUENCY_BAND_5GHZ 1 +#define WIFI_FREQUENCY_BAND_2GHZ 2 + +#define rtw_band_valid(band) ((band) <= WIFI_FREQUENCY_BAND_2GHZ) + +enum DriverInterface { + DRIVER_WEXT = 1, + DRIVER_CFG80211 = 2 +}; + +enum SCAN_RESULT_TYPE { + SCAN_RESULT_P2P_ONLY = 0, /* Will return all the P2P devices. */ + SCAN_RESULT_ALL = 1, /* Will return all the scanned device, include AP. */ + SCAN_RESULT_WFD_TYPE = 2 /* Will just return the correct WFD device. */ + /* If this device is Miracast sink device, it will just return all the Miracast source devices. */ +}; + +/* + +there are several "locks" in mlme_priv, +since mlme_priv is a shared resource between many threads, +like ISR/Call-Back functions, the OID handlers, and even timer functions. + +Each _queue has its own locks, already. +Other items are protected by mlme_priv.lock. + +To avoid possible dead lock, any thread trying to modifiying mlme_priv +SHALL not lock up more than one locks at a time! + +*/ + +#define traffic_threshold 10 +#define traffic_scan_period 500 + +typedef struct _RT_LINK_DETECT_T { + u32 NumTxOkInPeriod; + u32 NumRxOkInPeriod; + u32 NumRxUnicastOkInPeriod; + BOOLEAN bBusyTraffic; + BOOLEAN bTxBusyTraffic; + BOOLEAN bRxBusyTraffic; + BOOLEAN bHigherBusyTraffic; /* For interrupt migration purpose. */ + BOOLEAN bHigherBusyRxTraffic; /* We may disable Tx interrupt according as Rx traffic. */ + BOOLEAN bHigherBusyTxTraffic; /* We may disable Tx interrupt according as Tx traffic. */ + /* u8 TrafficBusyState; */ + u8 TrafficTransitionCount; + u32 LowPowerTransitionCount; +} RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; + +struct profile_info { + u8 ssidlen; + u8 ssid[WLAN_SSID_MAXLEN]; + u8 peermac[ETH_ALEN]; +}; + +struct tx_invite_req_info { + u8 token; + u8 benable; + u8 go_ssid[WLAN_SSID_MAXLEN]; + u8 ssidlen; + u8 go_bssid[ETH_ALEN]; + u8 peer_macaddr[ETH_ALEN]; + u8 operating_ch; /* This information will be set by using the p2p_set op_ch=x */ + u8 peer_ch; /* The listen channel for peer P2P device */ + +}; + +struct tx_invite_resp_info { + u8 token; /* Used to record the dialog token of p2p invitation request frame. */ +}; + + +struct wifi_display_info { + u16 wfd_enable; /* Eanble/Disable the WFD function. */ + u16 init_rtsp_ctrlport; /* init value of rtsp_ctrlport when WFD enable */ + u16 rtsp_ctrlport; /* TCP port number at which the this WFD device listens for RTSP messages, 0 when WFD disable */ + u16 tdls_rtsp_ctrlport; /* rtsp_ctrlport used by tdls, will sync when rtsp_ctrlport is changed by user */ + u16 peer_rtsp_ctrlport; /* TCP port number at which the peer WFD device listens for RTSP messages */ + /* This filed should be filled when receiving the gropu negotiation request */ + + u8 peer_session_avail; /* WFD session is available or not for the peer wfd device. */ + /* This variable will be set when sending the provisioning discovery request to peer WFD device. */ + /* And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. */ + u8 ip_address[4]; + u8 peer_ip_address[4]; + u8 wfd_pc; /* WFD preferred connection */ + /* 0 -> Prefer to use the P2P for WFD connection on peer side. */ + /* 1 -> Prefer to use the TDLS for WFD connection on peer side. */ + + u8 wfd_device_type; /* WFD Device Type */ + /* 0 -> WFD Source Device */ + /* 1 -> WFD Primary Sink Device */ + enum SCAN_RESULT_TYPE scan_result_type; /* Used when P2P is enable. This parameter will impact the scan result. */ + u8 op_wfd_mode; + u8 stack_wfd_mode; +}; + +struct tx_provdisc_req_info { + u16 wps_config_method_request; /* Used when sending the provisioning request frame */ + u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ + NDIS_802_11_SSID ssid; + u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ + u8 peerIFAddr[ETH_ALEN]; /* Peer interface address */ + u8 benable; /* This provision discovery request frame is trigger to send or not */ +}; + +struct rx_provdisc_req_info { /* When peer device issue prov_disc_req first, we should store the following informations */ + u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ + u8 strconfig_method_desc_of_prov_disc_req[4]; /* description for the config method located in the provisioning discovery request frame. */ + /* The UI must know this information to know which config method the remote p2p device is requiring. */ +}; + +struct tx_nego_req_info { + u16 peer_channel_num[2]; /* The channel number which the receiver stands. */ + u8 peerDevAddr[ETH_ALEN]; /* Peer device address */ + u8 benable; /* This negoitation request frame is trigger to send or not */ + u8 peer_ch; /* The listen channel for peer P2P device */ +}; + +struct group_id_info { + u8 go_device_addr[ETH_ALEN]; /* The GO's device address of this P2P group */ + u8 ssid[WLAN_SSID_MAXLEN]; /* The SSID of this P2P group */ +}; + +struct scan_limit_info { + u8 scan_op_ch_only; /* When this flag is set, the driver should just scan the operation channel */ + u8 operation_ch[5]; /* Store additional channel 1,6,11 for Android 4.2 IOT & Nexus 4 */ +}; + + + +struct wifidirect_info { + _adapter *padapter; + _timer find_phase_timer; + _timer restore_p2p_state_timer; + + /* Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. */ + _timer pre_tx_scan_timer; + _timer reset_ch_sitesurvey; + _timer reset_ch_sitesurvey2; /* Just for resetting the scan limit function by using p2p nego */ + struct tx_provdisc_req_info tx_prov_disc_info; + struct rx_provdisc_req_info rx_prov_disc_info; + struct tx_invite_req_info invitereq_info; + struct profile_info profileinfo[P2P_MAX_PERSISTENT_GROUP_NUM]; /* Store the profile information of persistent group */ + struct tx_invite_resp_info inviteresp_info; + struct tx_nego_req_info nego_req_info; + struct group_id_info groupid_info; /* Store the group id information when doing the group negotiation handshake. */ + struct scan_limit_info rx_invitereq_info; /* Used for get the limit scan channel from the Invitation procedure */ + struct scan_limit_info p2p_info; /* Used for get the limit scan channel from the P2P negotiation handshake */ + struct wifi_display_info *wfd_info; + + + enum P2P_ROLE role; + enum P2P_STATE pre_p2p_state; + enum P2P_STATE p2p_state; + u8 device_addr[ETH_ALEN]; /* The device address should be the mac address of this device. */ + u8 interface_addr[ETH_ALEN]; + u8 social_chan[4]; + u8 listen_channel; + u8 operating_channel; + u8 listen_dwell; /* This value should be between 1 and 3 */ + u8 support_rate[8]; + u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; + u8 intent; /* should only include the intent value. */ + u8 p2p_peer_interface_addr[ETH_ALEN]; + u8 p2p_peer_device_addr[ETH_ALEN]; + u8 peer_intent; /* Included the intent value and tie breaker value. */ + u8 device_name[WPS_MAX_DEVICE_NAME_LEN]; /* Device name for displaying on searching device screen */ + u8 device_name_len; + u8 profileindex; /* Used to point to the index of profileinfo array */ + u8 peer_operating_ch; + u8 find_phase_state_exchange_cnt; + u16 device_password_id_for_nego; /* The device password ID for group negotation */ + u8 negotiation_dialog_token; + u8 nego_ssid[WLAN_SSID_MAXLEN]; /* SSID information for group negotitation */ + u8 nego_ssidlen; + u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; + u8 p2p_group_ssid_len; + u8 persistent_supported; /* Flag to know the persistent function should be supported or not. */ + /* In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. */ + /* 0: disable */ + /* 1: enable */ + u8 session_available; /* Flag to set the WFD session available to enable or disable "by Sigma" */ + /* In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. */ + /* 0: disable */ + /* 1: enable */ + + u8 wfd_tdls_enable; /* Flag to enable or disable the TDLS by WFD Sigma */ + /* 0: disable */ + /* 1: enable */ + u8 wfd_tdls_weaksec; /* Flag to enable or disable the weak security function for TDLS by WFD Sigma */ + /* 0: disable */ + /* In this case, the driver can't issue the tdsl setup request frame. */ + /* 1: enable */ + /* In this case, the driver can issue the tdls setup request frame */ + /* even the current security is weak security. */ + + enum P2P_WPSINFO ui_got_wps_info; /* This field will store the WPS value (PIN value or PBC) that UI had got from the user. */ + u16 supported_wps_cm; /* This field describes the WPS config method which this driver supported. */ + /* The value should be the combination of config method defined in page104 of WPS v2.0 spec. */ + u8 external_uuid; /* UUID flag */ + u8 uuid[16]; /* UUID */ + uint channel_list_attr_len; /* This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. */ + u8 channel_list_attr[100]; /* This field will contain the body of P2P Channel List attribute of group negotitation response frame. */ + /* We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. */ + u8 driver_interface; /* Indicate DRIVER_WEXT or DRIVER_CFG80211 */ + + enum P2P_PS_MODE p2p_ps_mode; /* indicate p2p ps mode */ + enum P2P_PS_STATE p2p_ps_state; /* indicate p2p ps state */ + u8 noa_index; /* Identifies and instance of Notice of Absence timing. */ + u8 ctwindow; /* Client traffic window. A period of time in TU after TBTT. */ + u8 opp_ps; /* opportunistic power save. */ + u8 noa_num; /* number of NoA descriptor in P2P IE. */ + u8 noa_count[P2P_MAX_NOA_NUM]; /* Count for owner, Type of client. */ + u32 noa_duration[P2P_MAX_NOA_NUM]; /* Max duration for owner, preferred or min acceptable duration for client. */ + u32 noa_interval[P2P_MAX_NOA_NUM]; /* Length of interval for owner, preferred or max acceptable interval of client. */ + u32 noa_start_time[P2P_MAX_NOA_NUM]; /* schedule expressed in terms of the lower 4 bytes of the TSF timer. */ +}; + +struct tdls_ss_record { /* signal strength record */ + u8 macaddr[ETH_ALEN]; + u8 RxPWDBAll; + u8 is_tdls_sta; /* _TRUE: direct link sta, _FALSE: else */ +}; + +struct tdls_temp_mgmt { + u8 initiator; /* 0: None, 1: we initiate, 2: peer initiate */ + u8 peer_addr[ETH_ALEN]; +}; + + +struct tdls_info { + u8 ap_prohibited; + u8 ch_switch_prohibited; + u8 link_established; + u8 sta_cnt; + u8 sta_maximum; /* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */ + struct tdls_ss_record ss_record; + + u8 ch_sensing; + u8 cur_channel; + u8 collect_pkt_num[MAX_CHANNEL_NUM]; + _lock cmd_lock; + _lock hdl_lock; + u8 watchdog_count; + u8 dev_discovered; /* WFD_TDLS: for sigma test */ + u8 tdls_enable; + + /* Let wpa_supplicant to setup*/ + u8 driver_setup; + struct wifi_display_info *wfd_info; +}; + +struct tdls_txmgmt { + u8 peer[ETH_ALEN]; + u8 action_code; + u8 dialog_token; + u16 status_code; + u8 *buf; + size_t len; +}; + +/* used for mlme_priv.roam_flags */ +enum { + RTW_ROAM_ON_EXPIRED = BIT0, + RTW_ROAM_ON_RESUME = BIT1, + RTW_ROAM_ACTIVE = BIT2, +}; + +struct beacon_keys { + u8 ssid[IW_ESSID_MAX_SIZE]; + u32 ssid_len; + u8 bcn_channel; + u16 ht_cap_info; + u8 ht_info_infos_0_sco; /* bit0 & bit1 in infos[0] is second channel offset */ + int encryp_protocol; + int pairwise_cipher; + int group_cipher; + int is_8021x; +}; + +struct mlme_priv { + + _lock lock; + sint fw_state; /* shall we protect this variable? maybe not necessarily... */ + u8 bScanInProcess; + u8 to_join; /* flag */ + u8 to_roam; /* roaming trying times */ + struct wlan_network *roam_network; /* the target of active roam */ + u8 roam_flags; + u8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */ + u32 roam_scan_int_ms; /* scan interval for active roam */ + u32 roam_scanr_exp_ms; /* scan result expire time in ms for roam */ + u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */ + u8 roam_rssi_threshold; + bool need_to_roam; + + u8 *nic_hdl; + + _list *pscanned; + _queue free_bss_pool; + _queue scanned_queue; + u8 *free_bss_buf; + u32 num_of_scanned; + + NDIS_802_11_SSID assoc_ssid; + u8 assoc_bssid[6]; + + struct wlan_network cur_network; + struct wlan_network *cur_network_scanned; + + /* bcn check info */ + struct beacon_keys cur_beacon_keys; /* save current beacon keys */ + struct beacon_keys new_beacon_keys; /* save new beacon keys */ + u8 new_beacon_cnts; /* if new_beacon_cnts >= threshold, ap beacon is changed */ + + + /* uint wireless_mode; no used, remove it */ + + u32 auto_scan_int_ms; + + _timer assoc_timer; + + uint assoc_by_bssid; + uint assoc_by_rssi; + + _timer scan_to_timer; /* driver itself handles scan_timeout status. */ + u32 scan_start_time; /* used to evaluate the time spent in scanning */ + + + struct qos_priv qospriv; + + + /* Number of non-HT AP/stations */ + int num_sta_no_ht; + + /* Number of HT AP/stations 20 MHz */ + /* int num_sta_ht_20mhz; */ + + int num_FortyMHzIntolerant; + + struct ht_priv htpriv; + + + struct vht_priv vhtpriv; + + + RT_LINK_DETECT_T LinkDetectInfo; + + u8 acm_mask; /* for wmm acm mask */ + const struct country_chplan *country_ent; + u8 ChannelPlan; + RT_SCAN_TYPE scan_mode; /* active: 1, passive: 0 */ + + u8 *wps_probe_req_ie; + u32 wps_probe_req_ie_len; + + u8 ext_capab_ie_data[8];/*currently for ap mode only*/ + u8 ext_capab_ie_len; + + /* Number of associated Non-ERP stations (i.e., stations using 802.11b + * in 802.11g BSS) */ + int num_sta_non_erp; + + /* Number of associated stations that do not support Short Slot Time */ + int num_sta_no_short_slot_time; + + /* Number of associated stations that do not support Short Preamble */ + int num_sta_no_short_preamble; + + ATOMIC_T olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/ + + /* Number of HT associated stations that do not support greenfield */ + int num_sta_ht_no_gf; + + /* Number of associated non-HT stations */ + /* int num_sta_no_ht; */ + + /* Number of HT associated stations 20 MHz */ + int num_sta_ht_20mhz; + + /* number of associated stations 40MHz intolerant */ + int num_sta_40mhz_intolerant; + + /* Overlapping BSS information */ + ATOMIC_T olbc_ht; + + int ht_20mhz_width_req; + int ht_intolerant_ch_reported; + u16 ht_op_mode; + u8 sw_to_20mhz; /*switch to 20Mhz BW*/ + + u8 *assoc_req; + u32 assoc_req_len; + + u8 *assoc_rsp; + u32 assoc_rsp_len; + + /* u8 *wps_probe_req_ie; */ + /* u32 wps_probe_req_ie_len; */ + + u8 *wps_beacon_ie; + u32 wps_beacon_ie_len; + + u8 *wps_probe_resp_ie; + u32 wps_probe_resp_ie_len; + + u8 *wps_assoc_resp_ie; + u32 wps_assoc_resp_ie_len; + + u8 *p2p_beacon_ie; + u32 p2p_beacon_ie_len; + + u8 *p2p_probe_req_ie; + u32 p2p_probe_req_ie_len; + + u8 *p2p_probe_resp_ie; + u32 p2p_probe_resp_ie_len; + + u8 *p2p_go_probe_resp_ie; /* for GO */ + u32 p2p_go_probe_resp_ie_len; /* for GO */ + + u8 *p2p_assoc_req_ie; + u32 p2p_assoc_req_ie_len; + + u8 *p2p_assoc_resp_ie; + u32 p2p_assoc_resp_ie_len; + + _lock bcn_update_lock; + u8 update_bcn; + + u8 ori_ch; + u8 ori_bw; + u8 ori_offset; + + + + u32 lastscantime; + + +}; + +#define mlme_set_scan_to_timer(mlme, ms) \ + do { \ + /* RTW_INFO("%s set_scan_to_timer(%p, %d)\n", __FUNCTION__, (mlme), (ms)); */ \ + _set_timer(&(mlme)->scan_to_timer, (ms)); \ + } while (0) + +#define rtw_mlme_set_auto_scan_int(adapter, ms) \ + do { \ + adapter->mlmepriv.auto_scan_int_ms = ms; \ + } while (0) + +#define RTW_AUTO_SCAN_REASON_UNSPECIFIED 0 +#define RTW_AUTO_SCAN_REASON_2040_BSS BIT0 +#define RTW_AUTO_SCAN_REASON_ACS BIT1 +#define RTW_AUTO_SCAN_REASON_ROAM BIT2 + +void rtw_mlme_reset_auto_scan_int(_adapter *adapter, u8 *reason); + + +struct hostapd_priv { + _adapter *padapter; + + +}; + +extern int hostapd_mode_init(_adapter *padapter); +extern void hostapd_mode_unload(_adapter *padapter); + +extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf); +extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); +void rtw_sta_mstatus_report(_adapter *adapter); +extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf); + +thread_return event_thread(thread_context context); + +extern void rtw_free_network_queue(_adapter *adapter, u8 isfreeall); +extern int rtw_init_mlme_priv(_adapter *adapter);/* (struct mlme_priv *pmlmepriv); */ + +extern void rtw_free_mlme_priv(struct mlme_priv *pmlmepriv); + +extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv); +extern sint rtw_set_key(_adapter *adapter, struct security_priv *psecuritypriv, sint keyid, u8 set_tx, bool enqueue); +extern sint rtw_set_auth(_adapter *adapter, struct security_priv *psecuritypriv); + +__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv) +{ + /* if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid */ + /* if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address */ + return pmlmepriv->cur_network.network.MacAddress; +} + +__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + if ((state == WIFI_NULL_STATE) && + (pmlmepriv->fw_state == WIFI_NULL_STATE)) + return _TRUE; + + if (pmlmepriv->fw_state & state) + return _TRUE; + + return _FALSE; +} + +__inline static sint get_fwstate(struct mlme_priv *pmlmepriv) +{ + return pmlmepriv->fw_state; +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + * + * ### NOTE:#### (!!!!) + * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock + */ +extern void rtw_mi_update_iface_status(struct mlme_priv *pmlmepriv, sint state); + +static inline void set_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + pmlmepriv->fw_state |= state; + + /*bScanInProcess hook in phydm*/ + if (_FW_UNDER_SURVEY == state) + pmlmepriv->bScanInProcess = _TRUE; + + rtw_mi_update_iface_status(pmlmepriv, state); +} +static inline void init_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + pmlmepriv->fw_state = state; + + /*bScanInProcess hook in phydm*/ + if (_FW_UNDER_SURVEY == state) + pmlmepriv->bScanInProcess = _TRUE; + + rtw_mi_update_iface_status(pmlmepriv, state); +} + +static inline void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) +{ + pmlmepriv->fw_state &= ~state; + + /*bScanInProcess hook in phydm*/ + if (_FW_UNDER_SURVEY == state) + pmlmepriv->bScanInProcess = _FALSE; + + rtw_mi_update_iface_status(pmlmepriv, state); +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + */ +static inline void clr_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + _clr_fwstate_(pmlmepriv, state); + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +static inline void up_scanned_network(struct mlme_priv *pmlmepriv) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned++; + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} +u8 rtw_is_adapter_up(_adapter *padapter); + +__inline static void down_scanned_network(struct mlme_priv *pmlmepriv) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned--; + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned = val; + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); +extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); +extern void rtw_disconnect_hdl_under_linked(_adapter *adapter, struct sta_info *psta, u8 free_assoc); +extern void rtw_generate_random_ibss(u8 *pibss); +extern struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr); +extern struct wlan_network *rtw_get_oldest_wlan_network(_queue *scanned_queue); +struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); +struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); + +extern void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue); +extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); +extern void rtw_indicate_connect(_adapter *adapter); +void rtw_indicate_scan_done(_adapter *padapter, bool aborted); + +void rtw_drv_scan_by_self(_adapter *padapter, u8 reason); +void rtw_scan_wait_completed(_adapter *adapter); +u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms); +void rtw_scan_abort_no_wait(_adapter *adapter); +void rtw_scan_abort(_adapter *adapter); + +extern int rtw_restruct_sec_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len); +extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len); +extern void rtw_init_registrypriv_dev_network(_adapter *adapter); + +extern void rtw_update_registrypriv_dev_network(_adapter *adapter); + +extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); + +extern void rtw_join_timeout_handler(void *ctx); +extern void rtw_scan_timeout_handler(void *ctx); + +extern void rtw_dynamic_check_timer_handlder(void *ctx); +extern void rtw_iface_dynamic_check_timer_handlder(_adapter *adapter); + +#define rtw_is_scan_deny(adapter) _FALSE +#define rtw_clear_scan_deny(adapter) do {} while (0) +#define rtw_set_scan_deny(adapter, ms) do {} while (0) + +void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); + +#define MLME_BEACON_IE 0 +#define MLME_PROBE_REQ_IE 1 +#define MLME_PROBE_RESP_IE 2 +#define MLME_GO_PROBE_RESP_IE 3 +#define MLME_ASSOC_REQ_IE 4 +#define MLME_ASSOC_RESP_IE 5 + + +/* extern struct wlan_network* _rtw_dequeue_network(_queue *queue); */ + +extern struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv); + +extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall); +extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork); + +extern struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr); + +extern void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall); + +extern sint rtw_if_up(_adapter *padapter); + +sint rtw_linked_check(_adapter *padapter); + +u8 *rtw_get_capability_from_ie(u8 *ie); +u8 *rtw_get_timestampe_from_ie(u8 *ie); +u8 *rtw_get_beacon_interval_from_ie(u8 *ie); + +void rtw_joinbss_reset(_adapter *padapter); + +void rtw_ht_use_default_setting(_adapter *padapter); +void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len); +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel); +void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel); +void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len); + +int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork); +int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature); + +#define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags) +#define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags) +#define rtw_clr_roam_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.roam_flags &= ~flags); \ + } while (0) + +#define rtw_set_roam_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.roam_flags |= flags); \ + } while (0) + +#define rtw_assign_roam_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.roam_flags = flags); \ + } while (0) + +void _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network); +void rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network); +void rtw_set_to_roam(_adapter *adapter, u8 to_roam); +u8 rtw_dec_to_roam(_adapter *adapter); +u8 rtw_to_roam(_adapter *adapter); +int rtw_select_roaming_candidate(struct mlme_priv *pmlmepriv); + +bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset); + +struct sta_media_status_rpt_cmd_parm { + struct sta_info *sta; + bool connected; +}; + +void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected); +u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected); +void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm); + + +#define IPV4_SRC(_iphdr) (((u8 *)(_iphdr)) + 12) +#define IPV4_DST(_iphdr) (((u8 *)(_iphdr)) + 16) +#define GET_IPV4_IHL(_iphdr) BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4) +#define GET_IPV4_PROTOCOL(_iphdr) BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 9, 0, 8) +#define GET_IPV4_SRC(_iphdr) BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 12, 0, 32) +#define GET_IPV4_DST(_iphdr) BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 16, 0, 32) + +#define GET_UDP_SRC(_udphdr) BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 0, 0, 16) +#define GET_UDP_DST(_udphdr) BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 2, 0, 16) + +#define TCP_SRC(_tcphdr) (((u8 *)(_tcphdr)) + 0) +#define TCP_DST(_tcphdr) (((u8 *)(_tcphdr)) + 2) +#define GET_TCP_SRC(_tcphdr) BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 0, 0, 16) +#define GET_TCP_DST(_tcphdr) BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 2, 0, 16) +#define GET_TCP_SEQ(_tcphdr) BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 4, 0, 32) +#define GET_TCP_ACK_SEQ(_tcphdr) BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 8, 0, 32) +#define GET_TCP_DOFF(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 12, 4, 4) +#define GET_TCP_FIN(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 0, 1) +#define GET_TCP_SYN(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 1, 1) +#define GET_TCP_RST(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 2, 1) +#define GET_TCP_PSH(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 3, 1) +#define GET_TCP_ACK(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 4, 1) +#define GET_TCP_URG(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 5, 1) +#define GET_TCP_ECE(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 6, 1) +#define GET_TCP_CWR(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 7, 1) + +#endif /* __RTL871X_MLME_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_mlme_ext.h b/drivers/staging/rtl8821ce/include/rtw_mlme_ext.h new file mode 100644 index 000000000000..f3e5184c944d --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mlme_ext.h @@ -0,0 +1,1085 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MLME_EXT_H_ +#define __RTW_MLME_EXT_H_ + +/* Commented by Albert 20101105 + * Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) + * The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. + * So, this driver tried to extend the dwell time for each scanning channel. + * This will increase the chance to receive the probe response from SoftAP. */ + +#define SURVEY_TO (100) +#define REAUTH_TO (300) /* (50) */ +#define REASSOC_TO (300) /* (50) */ +/* #define DISCONNECT_TO (3000) */ +#define ADDBA_TO (2000) + +#define LINKED_TO (1) /* unit:2 sec, 1x2 = 2 sec */ + +#define REAUTH_LIMIT (4) +#define REASSOC_LIMIT (4) +#define READDBA_LIMIT (2) + +#define ROAMING_LIMIT 8 + +#define _HW_STATE_NOLINK_ 0x00 +#define _HW_STATE_ADHOC_ 0x01 +#define _HW_STATE_STATION_ 0x02 +#define _HW_STATE_AP_ 0x03 +#define _HW_STATE_MONITOR_ 0x04 + +#define _1M_RATE_ 0 +#define _2M_RATE_ 1 +#define _5M_RATE_ 2 +#define _11M_RATE_ 3 +#define _6M_RATE_ 4 +#define _9M_RATE_ 5 +#define _12M_RATE_ 6 +#define _18M_RATE_ 7 +#define _24M_RATE_ 8 +#define _36M_RATE_ 9 +#define _48M_RATE_ 10 +#define _54M_RATE_ 11 + +/******************************************************** +MCS rate definitions +*********************************************************/ +#define MCS_RATE_1R (0x000000ff) +#define MCS_RATE_2R (0x0000ffff) +#define MCS_RATE_3R (0x00ffffff) +#define MCS_RATE_4R (0xffffffff) +#define MCS_RATE_2R_13TO15_OFF (0x00001fff) + +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WMM_OUI[]; +extern unsigned char WPS_OUI[]; +extern unsigned char WFD_OUI[]; +extern unsigned char P2P_OUI[]; + +extern unsigned char WMM_INFO_OUI[]; +extern unsigned char WMM_PARA_OUI[]; + +typedef enum _RT_CHANNEL_DOMAIN { + /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ + RTW_CHPLAN_FCC = 0x00, + RTW_CHPLAN_IC = 0x01, + RTW_CHPLAN_ETSI = 0x02, + RTW_CHPLAN_SPAIN = 0x03, + RTW_CHPLAN_FRANCE = 0x04, + RTW_CHPLAN_MKK = 0x05, + RTW_CHPLAN_MKK1 = 0x06, + RTW_CHPLAN_ISRAEL = 0x07, + RTW_CHPLAN_TELEC = 0x08, + RTW_CHPLAN_GLOBAL_DOAMIN = 0x09, + RTW_CHPLAN_WORLD_WIDE_13 = 0x0A, + RTW_CHPLAN_TAIWAN = 0x0B, + RTW_CHPLAN_CHINA = 0x0C, + RTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D, + RTW_CHPLAN_KOREA = 0x0E, + RTW_CHPLAN_TURKEY = 0x0F, + RTW_CHPLAN_JAPAN = 0x10, + RTW_CHPLAN_FCC_NO_DFS = 0x11, + RTW_CHPLAN_JAPAN_NO_DFS = 0x12, + RTW_CHPLAN_WORLD_WIDE_5G = 0x13, + RTW_CHPLAN_TAIWAN_NO_DFS = 0x14, + + /* ===== 0x20 ~ 0x7F, new channel plan ===== */ + RTW_CHPLAN_WORLD_NULL = 0x20, + RTW_CHPLAN_ETSI1_NULL = 0x21, + RTW_CHPLAN_FCC1_NULL = 0x22, + RTW_CHPLAN_MKK1_NULL = 0x23, + RTW_CHPLAN_ETSI2_NULL = 0x24, + RTW_CHPLAN_FCC1_FCC1 = 0x25, + RTW_CHPLAN_WORLD_ETSI1 = 0x26, + RTW_CHPLAN_MKK1_MKK1 = 0x27, + RTW_CHPLAN_WORLD_KCC1 = 0x28, + RTW_CHPLAN_WORLD_FCC2 = 0x29, + RTW_CHPLAN_FCC2_NULL = 0x2A, + RTW_CHPLAN_WORLD_FCC3 = 0x30, + RTW_CHPLAN_WORLD_FCC4 = 0x31, + RTW_CHPLAN_WORLD_FCC5 = 0x32, + RTW_CHPLAN_WORLD_FCC6 = 0x33, + RTW_CHPLAN_FCC1_FCC7 = 0x34, + RTW_CHPLAN_WORLD_ETSI2 = 0x35, + RTW_CHPLAN_WORLD_ETSI3 = 0x36, + RTW_CHPLAN_MKK1_MKK2 = 0x37, + RTW_CHPLAN_MKK1_MKK3 = 0x38, + RTW_CHPLAN_FCC1_NCC1 = 0x39, + RTW_CHPLAN_FCC1_NCC2 = 0x40, + RTW_CHPLAN_GLOBAL_NULL = 0x41, + RTW_CHPLAN_ETSI1_ETSI4 = 0x42, + RTW_CHPLAN_FCC1_FCC2 = 0x43, + RTW_CHPLAN_FCC1_NCC3 = 0x44, + RTW_CHPLAN_WORLD_ETSI5 = 0x45, + RTW_CHPLAN_FCC1_FCC8 = 0x46, + RTW_CHPLAN_WORLD_ETSI6 = 0x47, + RTW_CHPLAN_WORLD_ETSI7 = 0x48, + RTW_CHPLAN_WORLD_ETSI8 = 0x49, + RTW_CHPLAN_WORLD_ETSI9 = 0x50, + RTW_CHPLAN_WORLD_ETSI10 = 0x51, + RTW_CHPLAN_WORLD_ETSI11 = 0x52, + RTW_CHPLAN_FCC1_NCC4 = 0x53, + RTW_CHPLAN_WORLD_ETSI12 = 0x54, + RTW_CHPLAN_FCC1_FCC9 = 0x55, + RTW_CHPLAN_WORLD_ETSI13 = 0x56, + RTW_CHPLAN_FCC1_FCC10 = 0x57, + RTW_CHPLAN_MKK2_MKK4 = 0x58, + RTW_CHPLAN_WORLD_ETSI14 = 0x59, + RTW_CHPLAN_FCC1_FCC5 = 0x60, + RTW_CHPLAN_FCC2_FCC7 = 0x61, + RTW_CHPLAN_FCC2_FCC1 = 0x62, + RTW_CHPLAN_WORLD_ETSI15 = 0x63, + RTW_CHPLAN_MKK2_MKK5 = 0x64, + RTW_CHPLAN_ETSI1_ETSI16 = 0x65, + RTW_CHPLAN_FCC1_FCC14 = 0x66, + RTW_CHPLAN_FCC1_FCC12 = 0x67, + RTW_CHPLAN_FCC2_FCC14 = 0x68, + RTW_CHPLAN_FCC2_FCC12 = 0x69, + RTW_CHPLAN_ETSI1_ETSI17 = 0x6A, + RTW_CHPLAN_WORLD_FCC16 = 0x6B, + RTW_CHPLAN_WORLD_FCC13 = 0x6C, + RTW_CHPLAN_FCC2_FCC15 = 0x6D, + RTW_CHPLAN_WORLD_FCC12 = 0x6E, + RTW_CHPLAN_NULL_ETSI8 = 0x6F, + RTW_CHPLAN_NULL_ETSI18 = 0x70, + RTW_CHPLAN_NULL_ETSI17 = 0x71, + RTW_CHPLAN_NULL_ETSI19 = 0x72, + + RTW_CHPLAN_MAX, + RTW_CHPLAN_REALTEK_DEFINE = 0x7F, +} RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN; + +typedef enum _RT_CHANNEL_DOMAIN_2G { + RTW_RD_2G_NULL = 0, + RTW_RD_2G_WORLD = 1, /* Worldwird 13 */ + RTW_RD_2G_ETSI1 = 2, /* Europe */ + RTW_RD_2G_FCC1 = 3, /* US */ + RTW_RD_2G_MKK1 = 4, /* Japan */ + RTW_RD_2G_ETSI2 = 5, /* France */ + RTW_RD_2G_GLOBAL = 6, /* Global domain */ + RTW_RD_2G_MKK2 = 7, /* Japan */ + RTW_RD_2G_FCC2 = 8, /* US */ + + RTW_RD_2G_MAX, +} RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; + +typedef enum _RT_CHANNEL_DOMAIN_5G { + RTW_RD_5G_NULL = 0, /* */ + RTW_RD_5G_ETSI1 = 1, /* Europe */ + RTW_RD_5G_ETSI2 = 2, /* Australia, New Zealand */ + RTW_RD_5G_ETSI3 = 3, /* Russia */ + RTW_RD_5G_FCC1 = 4, /* US */ + RTW_RD_5G_FCC2 = 5, /* FCC w/o DFS Channels */ + RTW_RD_5G_FCC3 = 6, /* Bolivia, Chile, El Salvador, Venezuela */ + RTW_RD_5G_FCC4 = 7, /* Venezuela */ + RTW_RD_5G_FCC5 = 8, /* China */ + RTW_RD_5G_FCC6 = 9, /* */ + RTW_RD_5G_FCC7 = 10, /* US Canada(w/o Weather radar) */ + RTW_RD_5G_KCC1 = 11, /* Korea */ + RTW_RD_5G_MKK1 = 12, /* Japan */ + RTW_RD_5G_MKK2 = 13, /* Japan (W52, W53) */ + RTW_RD_5G_MKK3 = 14, /* Japan (W56) */ + RTW_RD_5G_NCC1 = 15, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_NCC2 = 16, /* Taiwan, Band2, Band4 */ + RTW_RD_5G_NCC3 = 17, /* Taiwan w/o DFS, Band4 only */ + RTW_RD_5G_ETSI4 = 18, /* Europe w/o DFS, Band1 only */ + RTW_RD_5G_ETSI5 = 19, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC8 = 20, /* Latin America */ + RTW_RD_5G_ETSI6 = 21, /* Israel, Bahrain, Egypt, India, China, Malaysia */ + RTW_RD_5G_ETSI7 = 22, /* China */ + RTW_RD_5G_ETSI8 = 23, /* Jordan */ + RTW_RD_5G_ETSI9 = 24, /* Lebanon */ + RTW_RD_5G_ETSI10 = 25, /* Qatar */ + RTW_RD_5G_ETSI11 = 26, /* Russia */ + RTW_RD_5G_NCC4 = 27, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_ETSI12 = 28, /* Indonesia */ + RTW_RD_5G_FCC9 = 29, /* (w/o Weather radar) */ + RTW_RD_5G_ETSI13 = 30, /* (w/o Weather radar) */ + RTW_RD_5G_FCC10 = 31, /* Argentina(w/o Weather radar) */ + RTW_RD_5G_MKK4 = 32, /* Japan (W52) */ + RTW_RD_5G_ETSI14 = 33, /* Russia */ + RTW_RD_5G_FCC11 = 34, /* US(include CH144) */ + RTW_RD_5G_ETSI15 = 35, /* Malaysia */ + RTW_RD_5G_MKK5 = 36, /* Japan */ + RTW_RD_5G_ETSI16 = 37, /* Europe */ + RTW_RD_5G_ETSI17 = 38, /* Europe */ + RTW_RD_5G_FCC12 = 39, /* FCC */ + RTW_RD_5G_FCC13 = 40, /* FCC */ + RTW_RD_5G_FCC14 = 41, /* FCC w/o Weather radar(w/o 5600~5650MHz) */ + RTW_RD_5G_FCC15 = 42, /* FCC w/o Band3 */ + RTW_RD_5G_FCC16 = 43, /* FCC w/o Band3 */ + RTW_RD_5G_ETSI18 = 44, /* ETSI w/o DFS Band2&3 */ + RTW_RD_5G_ETSI19 = 45, /* Europe */ + + /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */ + RTW_RD_5G_OLD_FCC1, + RTW_RD_5G_OLD_NCC1, + RTW_RD_5G_OLD_KCC1, + + RTW_RD_5G_MAX, +} RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G; + +bool rtw_chplan_is_empty(u8 id); +#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan)) +#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20) + +typedef struct _RT_CHANNEL_PLAN { + unsigned char Channel[MAX_CHANNEL_NUM]; + unsigned char Len; +} RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN; + +struct ch_list_t { + u8 *len_ch; +}; + +#define CH_LIST_ENT(_len, arg...) \ + {.len_ch = (u8[_len + 1]) {_len, ##arg}, } + +#define CH_LIST_LEN(_ch_list) (_ch_list.len_ch[0]) +#define CH_LIST_CH(_ch_list, _i) (_ch_list.len_ch[_i + 1]) + +typedef struct _RT_CHANNEL_PLAN_MAP { + u8 Index2G; + u8 Index5G; + u8 regd; /* value of REGULATION_TXPWR_LMT */ +} RT_CHANNEL_PLAN_MAP, *PRT_CHANNEL_PLAN_MAP; + +#define CHPLAN_ENT(i2g, i5g, regd) {i2g, i5g, regd} + +enum Associated_AP { + atherosAP = 0, + broadcomAP = 1, + ciscoAP = 2, + marvellAP = 3, + ralinkAP = 4, + realtekAP = 5, + airgocapAP = 6, + unknownAP = 7, + maxAP, +}; + +typedef enum _HT_IOT_PEER { + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO = 6, + HT_IOT_PEER_MERU = 7, + HT_IOT_PEER_MARVELL = 8, + HT_IOT_PEER_REALTEK_SOFTAP = 9,/* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */ + HT_IOT_PEER_SELF_SOFTAP = 10, /* Self is SoftAP */ + HT_IOT_PEER_AIRGO = 11, + HT_IOT_PEER_INTEL = 12, + HT_IOT_PEER_RTK_APCLIENT = 13, + HT_IOT_PEER_REALTEK_81XX = 14, + HT_IOT_PEER_REALTEK_WOW = 15, + HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16, + HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17, + HT_IOT_PEER_MAX = 18 +} HT_IOT_PEER_E, *PHTIOT_PEER_E; + +struct mlme_handler { + unsigned int num; + char *str; + unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame); +}; + +struct action_handler { + unsigned int num; + char *str; + unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame); +}; + +enum SCAN_STATE { + SCAN_DISABLE = 0, + SCAN_START = 1, + SCAN_PS_ANNC_WAIT = 2, + SCAN_ENTER = 3, + SCAN_PROCESS = 4, + + /* backop */ + SCAN_BACKING_OP = 5, + SCAN_BACK_OP = 6, + SCAN_LEAVING_OP = 7, + SCAN_LEAVE_OP = 8, + + /* SW antenna diversity (before linked) */ + SCAN_SW_ANTDIV_BL = 9, + + /* legacy p2p */ + SCAN_TO_P2P_LISTEN = 10, + SCAN_P2P_LISTEN = 11, + + SCAN_COMPLETE = 12, + SCAN_STATE_MAX, +}; + +const char *scan_state_str(u8 state); + +enum ss_backop_flag { + SS_BACKOP_EN = BIT0, /* backop when linked */ + SS_BACKOP_EN_NL = BIT1, /* backop even when no linked */ + + SS_BACKOP_PS_ANNC = BIT4, + SS_BACKOP_TX_RESUME = BIT5, +}; + +struct ss_res { + u8 state; + u8 next_state; /* will set to state on next cmd hdl */ + int bss_cnt; + int channel_idx; + int scan_mode; + u16 scan_ch_ms; + u8 rx_ampdu_accept; + u8 rx_ampdu_size; + u8 igi_scan; + u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */ +#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + u8 is_sw_antdiv_bl_scan; +#endif + u8 ssid_num; + u8 ch_num; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; +}; + +/* #define AP_MODE 0x0C */ +/* #define STATION_MODE 0x08 */ +/* #define AD_HOC_MODE 0x04 */ +/* #define NO_LINK_MODE 0x00 */ + +#define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_ +#define WIFI_FW_STATION_STATE _HW_STATE_STATION_ +#define WIFI_FW_AP_STATE _HW_STATE_AP_ +#define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_ + +#define WIFI_FW_PRE_LINK 0x00000800 +#define WIFI_FW_AUTH_NULL 0x00000100 +#define WIFI_FW_AUTH_STATE 0x00000200 +#define WIFI_FW_AUTH_SUCCESS 0x00000400 + +#define WIFI_FW_ASSOC_STATE 0x00002000 +#define WIFI_FW_ASSOC_SUCCESS 0x00004000 + +#define WIFI_FW_LINKING_STATE (WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE) + +/* + * Usage: + * When one iface acted as AP mode and the other iface is STA mode and scanning, + * it should switch back to AP's operating channel periodically. + * Parameters info: + * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for + * RTW_BACK_OP_CH_MS milliseconds. + * Example: + * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1, + * RTW_SCAN_NUM_OF_CH is 8, RTW_BACK_OP_CH_MS is 300 + * When it's STA mode gets set_scan command, + * it would + * 1. Doing the scan on channel 1.2.3.4.5.6.7.8 + * 2. Back to channel 1 for 300 milliseconds + * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52 + * 4. Back to channel 1 for 300 milliseconds + * 5. ... and so on, till survey done. + */ +#if defined(CONFIG_ATMEL_RC_PATCH) + #define RTW_SCAN_NUM_OF_CH 2 + #define RTW_BACK_OP_CH_MS 200 +#else + #define RTW_SCAN_NUM_OF_CH 3 + #define RTW_BACK_OP_CH_MS 400 +#endif + +struct mlme_ext_info { + u32 state; +#ifdef CONFIG_MI_WITH_MBSSID_CAM + u8 hw_media_state; +#endif + u32 reauth_count; + u32 reassoc_count; + u32 link_count; + u32 auth_seq; + u32 auth_algo; /* 802.11 auth, could be open, shared, auto */ + u32 authModeToggle; + u32 enc_algo;/* encrypt algorithm; */ + u32 key_index; /* this is only valid for legendary wep, 0~3 for key id. */ + u32 iv; + u8 chg_txt[128]; + u16 aid; + u16 bcn_interval; + u16 capability; + u8 assoc_AP_vendor; + u8 slotTime; + u8 preamble_mode; + u8 WMM_enable; + u8 ERP_enable; + u8 ERP_IE; + u8 HT_enable; + u8 HT_caps_enable; + u8 HT_info_enable; + u8 HT_protection; + u8 turboMode_cts2self; + u8 turboMode_rtsen; + u8 SM_PS; + u8 agg_enable_bitmap; + u8 ADDBA_retry_count; + u8 candidate_tid_bitmap; + u8 dialogToken; + /* Accept ADDBA Request */ + BOOLEAN bAcceptAddbaReq; + u8 bwmode_updated; + u8 hidden_ssid_mode; + u8 VHT_enable; + + struct ADDBA_request ADDBA_req; + struct WMM_para_element WMM_param; + struct HT_caps_element HT_caps; + struct HT_info_element HT_info; + WLAN_BSSID_EX network;/* join network or bss_network, if in ap mode, it is the same to cur_network.network */ +}; + +/* The channel information about this channel including joining, scanning, and power constraints. */ +typedef struct _RT_CHANNEL_INFO { + u8 ChannelNum; /* The channel number. */ + RT_SCAN_TYPE ScanType; /* Scan type such as passive or active scan. */ + u32 rx_count; +} RT_CHANNEL_INFO, *PRT_CHANNEL_INFO; + +#define DFS_MASTER_TIMER_MS 100 +#define CAC_TIME_MS (60*1000) +#define CAC_TIME_CE_MS (10*60*1000) +#define NON_OCP_TIME_MS (30*60*1000) + +void rtw_rfctl_init(_adapter *adapter); + +#ifdef CONFIG_DFS_MASTER +struct rf_ctl_t; +#define CH_IS_NON_OCP(rt_ch_info) (time_after((unsigned long)(rt_ch_info)->non_ocp_end_time, (unsigned long)rtw_get_current_time())) +bool rtw_is_cac_reset_needed(_adapter *adapter, u8 ch, u8 bw, u8 offset); +bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); +bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl); +bool rtw_rfctl_is_tx_blocked_by_ch_waiting(struct rf_ctl_t *rfctl); +bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms); +u32 rtw_get_ch_waiting_ms(_adapter *adapter, u8 ch, u8 bw, u8 offset, u32 *r_non_ocp_ms, u32 *r_cac_ms); +void rtw_reset_cac(_adapter *adapter, u8 ch, u8 bw, u8 offset); +#else +#define CH_IS_NON_OCP(rt_ch_info) 0 +#define rtw_chset_is_ch_non_ocp(ch_set, ch, bw, offset) _FALSE +#define rtw_rfctl_is_tx_blocked_by_ch_waiting(rfctl) _FALSE +#endif + +enum { + RTW_CHF_2G = BIT0, + RTW_CHF_5G = BIT1, + RTW_CHF_DFS = BIT2, + RTW_CHF_LONG_CAC = BIT3, + RTW_CHF_NON_DFS = BIT4, + RTW_CHF_NON_LONG_CAC = BIT5, + RTW_CHF_NON_OCP = BIT6, +}; + +bool rtw_choose_shortest_waiting_ch(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags); + +void dump_country_chplan(void *sel, const struct country_chplan *ent); +void dump_country_chplan_map(void *sel); +void dump_chplan_id_list(void *sel); +void dump_chplan_test(void *sel); +void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set); +void dump_cur_chset(void *sel, _adapter *adapter); + +int rtw_chset_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch); +u8 rtw_chset_is_chbw_valid(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); + +bool rtw_mlme_band_check(_adapter *adapter, const u32 ch); + +enum { + BAND_24G = BIT0, + BAND_5G = BIT1, +}; +void RTW_SET_SCAN_BAND_SKIP(_adapter *padapter, int skip_band); +void RTW_CLR_SCAN_BAND_SKIP(_adapter *padapter, int skip_band); +int RTW_GET_SCAN_BAND_SKIP(_adapter *padapter); + +bool rtw_mlme_ignore_chan(_adapter *adapter, const u32 ch); + +/* P2P_MAX_REG_CLASSES - Maximum number of regulatory classes */ +#define P2P_MAX_REG_CLASSES 10 + +/* P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class */ +#define P2P_MAX_REG_CLASS_CHANNELS 20 + +/* struct p2p_channels - List of supported channels */ +struct p2p_channels { + /* struct p2p_reg_class - Supported regulatory class */ + struct p2p_reg_class { + /* reg_class - Regulatory class (IEEE 802.11-2007, Annex J) */ + u8 reg_class; + + /* channel - Supported channels */ + u8 channel[P2P_MAX_REG_CLASS_CHANNELS]; + + /* channels - Number of channel entries in use */ + size_t channels; + } reg_class[P2P_MAX_REG_CLASSES]; + + /* reg_classes - Number of reg_class entries in use */ + size_t reg_classes; +}; + +struct p2p_oper_class_map { + enum hw_mode {IEEE80211G, IEEE80211A} mode; + u8 op_class; + u8 min_chan; + u8 max_chan; + u8 inc; + enum { BW20, BW40PLUS, BW40MINUS } bw; +}; + +struct mlme_ext_priv { + _adapter *padapter; + u8 mlmeext_init; + ATOMIC_T event_seq; + u16 mgnt_seq; + + unsigned char cur_channel; + unsigned char cur_bwmode; + unsigned char cur_ch_offset;/* PRIME_CHNL_OFFSET */ + unsigned char cur_wireless_mode; /* NETWORK_TYPE */ + + unsigned char max_chan_nums; + RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; + struct p2p_channels channel_list; + unsigned char basicrate[NumRates]; + unsigned char datarate[NumRates]; + unsigned char default_supported_mcs_set[16]; + + struct ss_res sitesurvey_res; + struct mlme_ext_info mlmext_info;/* for sta/adhoc mode, including current scanning/connecting/connected related info. + * for ap mode, network includes ap's cap_info */ + _timer survey_timer; + _timer link_timer; + + u32 last_scan_time; + u8 scan_abort; + u8 tx_rate; /* TXRATE when USERATE is set. */ + + u32 retry; /* retry for issue probereq */ + + u64 TSFValue; + + /* for LPS-32K to adaptive bcn early and timeout */ + u8 adaptive_tsf_done; + u32 bcn_delay_cnt[9]; + u32 bcn_delay_ratio[9]; + u32 bcn_cnt; + u8 DrvBcnEarly; + u8 DrvBcnTimeOut; + + unsigned char bstart_bss; + + u8 update_channel_plan_by_ap_done; + /* recv_decache check for Action_public frame */ + u8 action_public_dialog_token; + u16 action_public_rxseq; + + /* #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + u8 active_keep_alive_check; + /* #endif */ +#ifdef DBG_FIXED_CHAN + u8 fixed_chan; +#endif + /* set hw sync bcn tsf register or not */ + u8 en_hw_update_tsf; +}; + +static inline u8 check_mlmeinfo_state(struct mlme_ext_priv *plmeext, sint state) +{ + if ((plmeext->mlmext_info.state & 0x03) == state) + return _TRUE; + + return _FALSE; +} + +#define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03) +#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state) +#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state) +#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state)) +#define mlmeext_set_scan_state(mlmeext, _state) \ + do { \ + ((mlmeext)->sitesurvey_res.state = (_state)); \ + ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + /* RTW_INFO("set_scan_state:%s\n", scan_state_str(_state)); */ \ + } while (0) + +#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state) +#define mlmeext_set_scan_next_state(mlmeext, _state) \ + do { \ + ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + /* RTW_INFO("set_scan_next_state:%s\n", scan_state_str(_state)); */ \ + } while (0) + +#define mlmeext_scan_backop_flags(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0) + +#define mlmeext_scan_backop_flags_sta(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0) + +#define mlmeext_scan_backop_flags_ap(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0) + +void init_mlme_default_rate_set(_adapter *padapter); +int init_mlme_ext_priv(_adapter *padapter); +int init_hw_mlme_ext(_adapter *padapter); +void free_mlme_ext_priv(struct mlme_ext_priv *pmlmeext); +extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); +struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv); + +/* void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); */ +#ifdef CONFIG_GET_RAID_BY_DRV +unsigned char networktype_to_raid(_adapter *adapter, struct sta_info *psta); +unsigned char networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta); +#endif +u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen); +void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len); +void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask); +void UpdateBrateTbl(_adapter *padapter, u8 *mBratesOS); +void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen); +void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch); + +void Set_MSR(_adapter *padapter, u8 type); + +u8 rtw_get_oper_ch(_adapter *adapter); +void rtw_set_oper_ch(_adapter *adapter, u8 ch); +u8 rtw_get_oper_bw(_adapter *adapter); +void rtw_set_oper_bw(_adapter *adapter, u8 bw); +u8 rtw_get_oper_choffset(_adapter *adapter); +void rtw_set_oper_choffset(_adapter *adapter, u8 offset); +u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset); +u32 rtw_get_on_oper_ch_time(_adapter *adapter); +u32 rtw_get_on_cur_ch_time(_adapter *adapter); + +u8 rtw_get_offset_by_chbw(u8 ch, u8 bw, u8 *r_offset); +u8 rtw_get_offset_by_ch(u8 channel); + +void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode); + +unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval); + +void _clear_cam_entry(_adapter *padapter, u8 entry); +void write_cam_from_cache(_adapter *adapter, u8 id); +void rtw_sec_cam_swap(_adapter *adapter, u8 cam_id_a, u8 cam_id_b); +void rtw_clean_dk_section(_adapter *adapter); +void rtw_clean_hw_dk_cam(_adapter *adapter); + +/* modify both HW and cache */ +void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_entry(_adapter *padapter, u8 id); + +/* modify cache only */ +void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_cache(_adapter *adapter, u8 id); + +void invalidate_cam_all(_adapter *padapter); +void CAM_empty_entry(PADAPTER Adapter, u8 ucIndex); + +void flush_all_cam_entry(_adapter *padapter); + +BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel); + +void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType); +u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid); +void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter *padapter, bool update_ie); + +int get_bsstype(unsigned short capability); +u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork); +u16 get_beacon_interval(WLAN_BSSID_EX *bss); + +int is_client_associated_to_ap(_adapter *padapter); +int is_client_associated_to_ibss(_adapter *padapter); +int is_IBSS_empty(_adapter *padapter); + +unsigned char check_assoc_AP(u8 *pframe, uint len); + +int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag); +void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag); +void WMMOnAssocRsp(_adapter *padapter); + +void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HTOnAssocRsp(_adapter *padapter); + +void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void VCS_update(_adapter *padapter, struct sta_info *psta); +void update_ldpc_stbc_cap(struct sta_info *psta); + +int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, + struct beacon_keys *recv_beacon); +int validate_beacon_len(u8 *pframe, uint len); +void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon); +int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len); +void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta); +void update_capinfo(PADAPTER Adapter, u16 updateCap); +void update_wireless_mode(_adapter *padapter); +void update_tx_basic_rate(_adapter *padapter, u8 modulation); +void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode); +int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num); + +/* for sta/adhoc mode */ +void update_sta_info(_adapter *padapter, struct sta_info *psta); +unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz); +unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz); +void Update_RA_Entry(_adapter *padapter, struct sta_info *psta); +void set_sta_rate(_adapter *padapter, struct sta_info *psta); + +unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated); + +unsigned char get_highest_rate_idx(u32 mask); +int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode); +unsigned int is_ap_in_tkip(_adapter *padapter); +unsigned int is_ap_in_wep(_adapter *padapter); +unsigned int should_forbid_n_rate(_adapter *padapter); + +bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap); +void _rtw_camctl_set_flags(_adapter *adapter, u32 flags); +void rtw_camctl_set_flags(_adapter *adapter, u32 flags); +void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags); +void rtw_camctl_clr_flags(_adapter *adapter, u32 flags); +bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags); + +struct sec_cam_bmp; +void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num); +void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map); + +bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id); +bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id); +s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk); +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used); +void rtw_camid_free(_adapter *adapter, u8 cam_id); +u8 rtw_get_sec_camid(_adapter *adapter, u8 max_bk_key_num, u8 *sec_key_id); + +struct macid_bmp; +struct macid_ctl_t; +void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num); +bool rtw_macid_is_set(struct macid_bmp *map, u8 id); +bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id); +bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id); +s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id); +s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id); +void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta); +void rtw_release_macid(_adapter *padapter, struct sta_info *psta); +u8 rtw_search_max_mac_id(_adapter *padapter); +void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr); +void rtw_macid_ctl_set_bw(struct macid_ctl_t *macid_ctl, u8 id, u8 bw); +void rtw_macid_ctl_set_vht_en(struct macid_ctl_t *macid_ctl, u8 id, u8 en); +void rtw_macid_ctl_set_rate_bmp0(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); +void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp); +void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl); +void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl); +u8 rtw_iface_bcmc_id_get(_adapter *padapter); + +u32 report_join_res(_adapter *padapter, int res); +void report_survey_event(_adapter *padapter, union recv_frame *precv_frame); +void report_surveydone_event(_adapter *padapter); +u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated); +void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr); +bool rtw_port_switch_chk(_adapter *adapter); +void report_wmm_edca_update(_adapter *padapter); + +void beacon_timing_control(_adapter *padapter); +u8 chk_bmc_sleepq_cmd(_adapter *padapter); +extern u8 set_tx_beacon_cmd(_adapter *padapter); +unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame); +void update_mgnt_tx_rate(_adapter *padapter, u8 rate); +void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib); +void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib); +void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe); +void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe); +s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); +s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe); +s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); + +void issue_probersp_p2p(_adapter *padapter, unsigned char *da); +void issue_p2p_provision_request(_adapter *padapter, u8 *pssid, u8 ussidlen, u8 *pdev_raddr); +void issue_p2p_GO_request(_adapter *padapter, u8 *raddr); +void issue_probereq_p2p(_adapter *padapter, u8 *da); +int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms); +void issue_p2p_invitation_response(_adapter *padapter, u8 *raddr, u8 dialogToken, u8 success); +void issue_p2p_invitation_request(_adapter *padapter, u8 *raddr); +void issue_beacon(_adapter *padapter, int timeout_ms); +void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq); +void _issue_assocreq(_adapter *padapter, u8 is_assoc); +void issue_assocreq(_adapter *padapter); +void issue_reassocreq(_adapter *padapter); +void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type); +void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status); +void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da); +s32 issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int try_cnt, int wait_ms); +int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); +s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode); +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms); +int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason); +int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms); +void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset); +void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid); +void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size); +u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms); +void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator); +int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms); + +int issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode); +int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms); + +unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force); +unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force); + +unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr); +unsigned int send_beacon(_adapter *padapter); + +void start_clnt_assoc(_adapter *padapter); +void start_clnt_auth(_adapter *padapter); +void start_clnt_join(_adapter *padapter); +void start_create_ibss(_adapter *padapter); + +unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame); +unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame); + +unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame); +#ifdef CONFIG_RTW_WNM +unsigned int on_action_wnm(_adapter *adapter, union recv_frame *rframe); +#endif + +#define RX_AMPDU_ACCEPT_INVALID 0xFF +#define RX_AMPDU_SIZE_INVALID 0xFF + +enum rx_ampdu_reason { + RX_AMPDU_DRV_FIXED = 1, + RX_AMPDU_BTCOEX = 2, /* not used, because BTCOEX has its own variable management */ + RX_AMPDU_DRV_SCAN = 3, +}; +u8 rtw_rx_ampdu_size(_adapter *adapter); +bool rtw_rx_ampdu_is_accept(_adapter *adapter); +bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason); +bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason); +u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size); +u8 rx_ampdu_size_sta_limit(_adapter *adapter, struct sta_info *sta); +u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size); +u16 rtw_rx_ampdu_apply(_adapter *adapter); + +unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame); +unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_ft(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); + +void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); +void mlmeext_sta_del_event_callback(_adapter *padapter); +void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta); + +void linked_status_chk(_adapter *padapter, u8 from_timer); + +void _linked_info_dump(_adapter *padapter); + +void survey_timer_hdl(void *ctx); +void link_timer_hdl(void *ctx); +void addba_timer_hdl(void *ctx); + +#define set_survey_timer(mlmeext, ms) \ + do { \ + /*RTW_INFO("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + _set_timer(&(mlmeext)->survey_timer, (ms)); \ + } while (0) + +#define set_link_timer(mlmeext, ms) \ + do { \ + /*RTW_INFO("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + _set_timer(&(mlmeext)->link_timer, (ms)); \ + } while (0) + +extern int cckrates_included(unsigned char *rate, int ratelen); +extern int cckratesonly_included(unsigned char *rate, int ratelen); + +extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr); + +extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); +extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext); +extern void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); +extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer); + +void rtw_join_done_chk_ch(_adapter *padapter, int join_res); + +int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); + +#ifdef CONFIG_PLATFORM_ARM_SUN8I + #define BUSY_TRAFFIC_SCAN_DENY_PERIOD 8000 +#else + #define BUSY_TRAFFIC_SCAN_DENY_PERIOD 12000 +#endif + +struct cmd_hdl { + uint parmsize; + u8(*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf); +}; + +u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf); +u8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf); +u8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf); + +u8 NULL_hdl(_adapter *padapter, u8 *pbuf); +u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf); +u8 disconnect_hdl(_adapter *padapter, u8 *pbuf); +u8 createbss_hdl(_adapter *padapter, u8 *pbuf); +u8 setopmode_hdl(_adapter *padapter, u8 *pbuf); +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf); +u8 setauth_hdl(_adapter *padapter, u8 *pbuf); +u8 setkey_hdl(_adapter *padapter, u8 *pbuf); +u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf); +u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf); +u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf); +u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf); +u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf); + +void rtw_ap_wep_pk_setting(_adapter *adapter, struct sta_info *psta); + +u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); +u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf); +u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf); +u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); +u8 set_ch_hdl(_adapter *padapter, u8 *pbuf); +u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); +u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); +u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); /* Kurt: Handling DFS channel switch announcement ie. */ +u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf); +u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf); +u8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf); + +#define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl}, +#define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd}, + +struct C2HEvent_Header { + +#ifdef __LITTLE_ENDIAN + unsigned int len:16; + unsigned int ID:8; + unsigned int seq:8; +#else + unsigned int seq:8; + unsigned int ID:8; + unsigned int len:16; +#endif + unsigned int rsvd; + +}; + +void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf); +void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf); + +enum rtw_c2h_event { + GEN_EVT_CODE(_Read_MACREG) = 0, /*0*/ + GEN_EVT_CODE(_Read_BBREG), + GEN_EVT_CODE(_Read_RFREG), + GEN_EVT_CODE(_Read_EEPROM), + GEN_EVT_CODE(_Read_EFUSE), + GEN_EVT_CODE(_Read_CAM), /*5*/ + GEN_EVT_CODE(_Get_BasicRate), + GEN_EVT_CODE(_Get_DataRate), + GEN_EVT_CODE(_Survey), /*8*/ + GEN_EVT_CODE(_SurveyDone), /*9*/ + + GEN_EVT_CODE(_JoinBss) , /*10*/ + GEN_EVT_CODE(_AddSTA), + GEN_EVT_CODE(_DelSTA), + GEN_EVT_CODE(_AtimDone) , + GEN_EVT_CODE(_TX_Report), + GEN_EVT_CODE(_CCX_Report), /*15*/ + GEN_EVT_CODE(_DTM_Report), + GEN_EVT_CODE(_TX_Rate_Statistics), + GEN_EVT_CODE(_C2HLBK), + GEN_EVT_CODE(_FWDBG), + GEN_EVT_CODE(_C2HFEEDBACK), /*20*/ + GEN_EVT_CODE(_ADDBA), + GEN_EVT_CODE(_C2HBCN), + GEN_EVT_CODE(_ReportPwrState), /* filen: only for PCIE, USB */ + GEN_EVT_CODE(_CloseRF), /* filen: only for PCIE, work around ASPM */ + GEN_EVT_CODE(_WMM), /*25*/ + MAX_C2HEVT +}; + +#ifdef _RTW_MLME_EXT_C_ + +static struct fwevent wlanevents[] = { + {0, rtw_dummy_event_callback}, /*0*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, &rtw_survey_event_callback}, /*8*/ + {sizeof(struct surveydone_event), &rtw_surveydone_event_callback}, /*9*/ + + {0, &rtw_joinbss_event_callback}, /*10*/ + {sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, + {sizeof(struct stadel_event), &rtw_stadel_event_callback}, + {0, &rtw_atimdone_event_callback}, + {0, rtw_dummy_event_callback}, + {0, NULL}, /*15*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, rtw_fwdbg_event_callback}, + {0, NULL}, /*20*/ + {0, NULL}, + {0, NULL}, + {0, &rtw_cpwm_event_callback}, + {0, NULL}, + {0, &rtw_wmm_event_callback}, /*25*/ +}; + +#endif/* _RTW_MLME_EXT_C_ */ + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_mp.h b/drivers/staging/rtl8821ce/include/rtw_mp.h new file mode 100644 index 000000000000..86a41c9e3cbc --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mp.h @@ -0,0 +1,829 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_MP_H_ +#define _RTW_MP_H_ + +#define RTWPRIV_VER_INFO 1 + +#define MAX_MP_XMITBUF_SZ 2048 +#define NR_MP_XMITFRAME 8 + +struct mp_xmit_frame { + _list list; + + struct pkt_attrib attrib; + + _pkt *pkt; + + int frame_tag; + + _adapter *padapter; + + uint mem[(MAX_MP_XMITBUF_SZ >> 2)]; +}; + +struct mp_wiparam { + u32 bcompleted; + u32 act_type; + u32 io_offset; + u32 io_value; +}; + +typedef void(*wi_act_func)(void *padapter); + +struct mp_tx { + u8 stop; + u32 count, sended; + u8 payload; + struct pkt_attrib attrib; + /* struct tx_desc desc; */ + /* u8 resvdtx[7]; */ + u8 desc[TXDESC_SIZE]; + u8 *pallocated_buf; + u8 *buf; + u32 buf_size, write_size; + _thread_hdl_ PktTxThread; +}; + +#define MP_MAX_LINES 1000 +#define MP_MAX_LINES_BYTES 256 +#define u1Byte u8 +#define s1Byte s8 +#define u4Byte u32 +#define s4Byte s32 +#define u1Byte u8 +#define pu1Byte u8* + +#define u2Byte u16 +#define pu2Byte u16* + +#define u4Byte u32 +#define pu4Byte u32* + +#define u8Byte u64 +#define pu8Byte u64* + +#define s1Byte s8 +#define ps1Byte s8* + +#define s2Byte s16 +#define ps2Byte s16* + +#define s4Byte s32 +#define ps4Byte s32* + +#define s8Byte s64 +#define ps8Byte s64* + +#define UCHAR u8 +#define USHORT u16 +#define UINT u32 +#define ULONG u32 +#define PULONG u32* + +typedef struct _RT_PMAC_PKT_INFO { + UCHAR MCS; + UCHAR Nss; + UCHAR Nsts; + UINT N_sym; + UCHAR SIGA2B3; +} RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO; + +typedef struct _RT_PMAC_TX_INFO { + u8 bEnPMacTx:1; /* 0: Disable PMac 1: Enable PMac */ + u8 Mode:3; /* 0: Packet TX 3:Continuous TX */ + u8 Ntx:4; /* 0-7 */ + u8 TX_RATE; /* MPT_RATE_E */ + u8 TX_RATE_HEX; + u8 TX_SC; + u8 bSGI:1; + u8 bSPreamble:1; + u8 bSTBC:1; + u8 bLDPC:1; + u8 NDP_sound:1; + u8 BandWidth:3; /* 0: 20 1:40 2:80Mhz */ + u8 m_STBC; /* bSTBC + 1 */ + USHORT PacketPeriod; + UINT PacketCount; + UINT PacketLength; + u8 PacketPattern; + USHORT SFD; + u8 SignalField; + u8 ServiceField; + USHORT LENGTH; + u8 CRC16[2]; + u8 LSIG[3]; + u8 HT_SIG[6]; + u8 VHT_SIG_A[6]; + u8 VHT_SIG_B[4]; + u8 VHT_SIG_B_CRC; + u8 VHT_Delimiter[4]; + u8 MacAddress[6]; +} RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO; + +typedef VOID (*MPT_WORK_ITEM_HANDLER)(IN PVOID Adapter); +typedef struct _MPT_CONTEXT { + /* Indicate if we have started Mass Production Test. */ + BOOLEAN bMassProdTest; + + /* Indicate if the driver is unloading or unloaded. */ + BOOLEAN bMptDrvUnload; + + _sema MPh2c_Sema; + _timer MPh2c_timeout_timer; + /* Event used to sync H2c for BT control */ + + BOOLEAN MptH2cRspEvent; + BOOLEAN MptBtC2hEvent; + BOOLEAN bMPh2c_timeout; + + /* 8190 PCI does not support NDIS_WORK_ITEM. */ + /* Work Item for Mass Production Test. */ + /* NDIS_WORK_ITEM MptWorkItem; + * RT_WORK_ITEM MptWorkItem; */ + /* Event used to sync the case unloading driver and MptWorkItem is still in progress. + * NDIS_EVENT MptWorkItemEvent; */ + /* To protect the following variables. + * NDIS_SPIN_LOCK MptWorkItemSpinLock; */ + /* Indicate a MptWorkItem is scheduled and not yet finished. */ + BOOLEAN bMptWorkItemInProgress; + /* An instance which implements function and context of MptWorkItem. */ + MPT_WORK_ITEM_HANDLER CurrMptAct; + + /* 1=Start, 0=Stop from UI. */ + ULONG MptTestStart; + /* _TEST_MODE, defined in MPT_Req2.h */ + ULONG MptTestItem; + /* Variable needed in each implementation of CurrMptAct. */ + ULONG MptActType; /* Type of action performed in CurrMptAct. */ + /* The Offset of IO operation is depend of MptActType. */ + ULONG MptIoOffset; + /* The Value of IO operation is depend of MptActType. */ + ULONG MptIoValue; + /* The RfPath of IO operation is depend of MptActType. */ + + ULONG mpt_rf_path; + + WIRELESS_MODE MptWirelessModeToSw; /* Wireless mode to switch. */ + u8 MptChannelToSw; /* Channel to switch. */ + u8 MptInitGainToSet; /* Initial gain to set. */ + /* ULONG bMptAntennaA; */ /* TRUE if we want to use antenna A. */ + ULONG MptBandWidth; /* bandwidth to switch. */ + + ULONG mpt_rate_index;/* rate index. */ + + /* Register value kept for Single Carrier Tx test. */ + u8 btMpCckTxPower; + /* Register value kept for Single Carrier Tx test. */ + u8 btMpOfdmTxPower; + /* For MP Tx Power index */ + u8 TxPwrLevel[4]; /* rf-A, rf-B*/ + u32 RegTxPwrLimit; + /* Content of RCR Regsiter for Mass Production Test. */ + ULONG MptRCR; + /* TRUE if we only receive packets with specific pattern. */ + BOOLEAN bMptFilterPattern; + /* Rx OK count, statistics used in Mass Production Test. */ + ULONG MptRxOkCnt; + /* Rx CRC32 error count, statistics used in Mass Production Test. */ + ULONG MptRxCrcErrCnt; + + BOOLEAN bCckContTx; /* TRUE if we are in CCK Continuous Tx test. */ + BOOLEAN bOfdmContTx; /* TRUE if we are in OFDM Continuous Tx test. */ + /* TRUE if we have start Continuous Tx test. */ + BOOLEAN is_start_cont_tx; + + /* TRUE if we are in Single Carrier Tx test. */ + BOOLEAN bSingleCarrier; + /* TRUE if we are in Carrier Suppression Tx Test. */ + + BOOLEAN is_carrier_suppression; + + /* TRUE if we are in Single Tone Tx test. */ + + BOOLEAN is_single_tone; + + /* ACK counter asked by K.Y.. */ + BOOLEAN bMptEnableAckCounter; + ULONG MptAckCounter; + + /* SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! */ + /* s1Byte BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */ + /* s1Byte BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */ + /* s4Byte RfReadLine[2]; */ + + u8 APK_bound[2]; /* for APK path A/path B */ + BOOLEAN bMptIndexEven; + + u8 backup0xc50; + u8 backup0xc58; + u8 backup0xc30; + u8 backup0x52_RF_A; + u8 backup0x52_RF_B; + + u4Byte backup0x58_RF_A; + u4Byte backup0x58_RF_B; + + u1Byte h2cReqNum; + u1Byte c2hBuf[32]; + + u1Byte btInBuf[100]; + ULONG mptOutLen; + u1Byte mptOutBuf[100]; + RT_PMAC_TX_INFO PMacTxInfo; + RT_PMAC_PKT_INFO PMacPktInfo; + u8 HWTxmode; + + BOOLEAN bldpc; + BOOLEAN bstbc; +} MPT_CONTEXT, *PMPT_CONTEXT; +/* #endif */ + +/* #define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) */ +enum { + WRITE_REG = 1, + READ_REG, + WRITE_RF, + READ_RF, + MP_START, + MP_STOP, + MP_RATE, + MP_CHANNEL, + MP_BANDWIDTH, + MP_TXPOWER, + MP_ANT_TX, + MP_ANT_RX, + MP_CTX, + MP_QUERY, + MP_ARX, + MP_PSD, + MP_PWRTRK, + MP_THER, + MP_IOCTL, + EFUSE_GET, + EFUSE_SET, + MP_RESET_STATS, + MP_DUMP, + MP_PHYPARA, + MP_SetRFPathSwh, + MP_QueryDrvStats, + CTA_TEST, + MP_DISABLE_BT_COEXIST, + MP_PwrCtlDM, + MP_GETVER, + MP_MON, + EFUSE_MASK, + EFUSE_FILE, + MP_TX, + MP_RX, + MP_IQK, + MP_LCK, + MP_HW_TX_MODE, + MP_GET_TXPOWER_INX, + MP_CUSTOMER_STR, + MP_NULL, + MP_SetBT, + MP_SD_IREAD, + MP_SD_IWRITE, +}; + +struct mp_priv { + _adapter *papdater; + + /* Testing Flag */ + u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */ + + u32 prev_fw_state; + + /* OID cmd handler */ + struct mp_wiparam workparam; + /* u8 act_in_progress; */ + + /* Tx Section */ + u8 TID; + u32 tx_pktcount; + u32 pktInterval; + u32 pktLength; + struct mp_tx tx; + + /* Rx Section */ + u32 rx_bssidpktcount; + u32 rx_pktcount; + u32 rx_pktcount_filter_out; + u32 rx_crcerrpktcount; + u32 rx_pktloss; + BOOLEAN rx_bindicatePkt; + struct recv_stat rxstat; + + /* RF/BB relative */ + u8 channel; + u8 bandwidth; + u8 prime_channel_offset; + u8 txpoweridx; + u8 rateidx; + u32 preamble; + /* u8 modem; */ + u32 CrystalCap; + /* u32 curr_crystalcap; */ + + u16 antenna_tx; + u16 antenna_rx; + /* u8 curr_rfpath; */ + + u8 check_mp_pkt; + + u8 bSetTxPower; + /* uint ForcedDataRate; */ + u8 mp_dm; + u8 mac_filter[ETH_ALEN]; + u8 bmac_filter; + + struct wlan_network mp_network; + NDIS_802_11_MAC_ADDRESS network_macaddr; + + u8 *pallocated_mp_xmitframe_buf; + u8 *pmp_xmtframe_buf; + _queue free_mp_xmitqueue; + u32 free_mp_xmitframe_cnt; + BOOLEAN bSetRxBssid; + BOOLEAN bTxBufCkFail; + BOOLEAN bRTWSmbCfg; + BOOLEAN bloopback; + BOOLEAN bloadefusemap; + + MPT_CONTEXT mpt_ctx; + + u8 *TXradomBuffer; +}; + +typedef struct _IOCMD_STRUCT_ { + u8 cmdclass; + u16 value; + u8 index; +} IOCMD_STRUCT; + +struct rf_reg_param { + u32 path; + u32 offset; + u32 value; +}; + +struct bb_reg_param { + u32 offset; + u32 value; +}; + +typedef struct _MP_FIRMWARE { + FIRMWARE_SOURCE eFWSource; + u8 *szFwBuffer; + u32 ulFwLength; +} RT_MP_FIRMWARE, *PRT_MP_FIRMWARE; + +/* *********************************************************************** */ + +#define LOWER _TRUE +#define RAISE _FALSE + +/* Hardware Registers */ +#define BB_REG_BASE_ADDR 0x800 + +/* MP variables */ +typedef enum _MP_MODE_ { + MP_OFF, + MP_ON, + MP_ERR, + MP_CONTINUOUS_TX, + MP_SINGLE_CARRIER_TX, + MP_CARRIER_SUPPRISSION_TX, + MP_SINGLE_TONE_TX, + MP_PACKET_TX, + MP_PACKET_RX +} MP_MODE; + +typedef enum _TEST_MODE { + TEST_NONE , + PACKETS_TX , + PACKETS_RX , + CONTINUOUS_TX , + OFDM_Single_Tone_TX , + CCK_Carrier_Suppression_TX +} TEST_MODE; + +typedef enum _MPT_BANDWIDTH { + MPT_BW_20MHZ = 0, + MPT_BW_40MHZ_DUPLICATE = 1, + MPT_BW_40MHZ_ABOVE = 2, + MPT_BW_40MHZ_BELOW = 3, + MPT_BW_40MHZ = 4, + MPT_BW_80MHZ = 5, + MPT_BW_80MHZ_20_ABOVE = 6, + MPT_BW_80MHZ_20_BELOW = 7, + MPT_BW_80MHZ_20_BOTTOM = 8, + MPT_BW_80MHZ_20_TOP = 9, + MPT_BW_80MHZ_40_ABOVE = 10, + MPT_BW_80MHZ_40_BELOW = 11, +} MPT_BANDWIDTHE, *PMPT_BANDWIDTH; + +#define MAX_RF_PATH_NUMS RF_PATH_MAX + +extern u8 mpdatarate[NumRates]; + +/* MP set force data rate base on the definition. */ +typedef enum _MPT_RATE_INDEX { + /* CCK rate. */ + MPT_RATE_1M = 1 , /* 0 */ + MPT_RATE_2M, + MPT_RATE_55M, + MPT_RATE_11M, /* 3 */ + + /* OFDM rate. */ + MPT_RATE_6M, /* 4 */ + MPT_RATE_9M, + MPT_RATE_12M, + MPT_RATE_18M, + MPT_RATE_24M, + MPT_RATE_36M, + MPT_RATE_48M, + MPT_RATE_54M, /* 11 */ + + /* HT rate. */ + MPT_RATE_MCS0, /* 12 */ + MPT_RATE_MCS1, + MPT_RATE_MCS2, + MPT_RATE_MCS3, + MPT_RATE_MCS4, + MPT_RATE_MCS5, + MPT_RATE_MCS6, + MPT_RATE_MCS7, /* 19 */ + MPT_RATE_MCS8, + MPT_RATE_MCS9, + MPT_RATE_MCS10, + MPT_RATE_MCS11, + MPT_RATE_MCS12, + MPT_RATE_MCS13, + MPT_RATE_MCS14, + MPT_RATE_MCS15, /* 27 */ + MPT_RATE_MCS16, + MPT_RATE_MCS17, /* #29 */ + MPT_RATE_MCS18, + MPT_RATE_MCS19, + MPT_RATE_MCS20, + MPT_RATE_MCS21, + MPT_RATE_MCS22, /* #34 */ + MPT_RATE_MCS23, + MPT_RATE_MCS24, + MPT_RATE_MCS25, + MPT_RATE_MCS26, + MPT_RATE_MCS27, /* #39 */ + MPT_RATE_MCS28, /* #40 */ + MPT_RATE_MCS29, /* #41 */ + MPT_RATE_MCS30, /* #42 */ + MPT_RATE_MCS31, /* #43 */ + /* VHT rate. Total: 20*/ + MPT_RATE_VHT1SS_MCS0 = 100,/* #44*/ + MPT_RATE_VHT1SS_MCS1, /* # */ + MPT_RATE_VHT1SS_MCS2, + MPT_RATE_VHT1SS_MCS3, + MPT_RATE_VHT1SS_MCS4, + MPT_RATE_VHT1SS_MCS5, + MPT_RATE_VHT1SS_MCS6, /* # */ + MPT_RATE_VHT1SS_MCS7, + MPT_RATE_VHT1SS_MCS8, + MPT_RATE_VHT1SS_MCS9, /* #53 */ + MPT_RATE_VHT2SS_MCS0, /* #54 */ + MPT_RATE_VHT2SS_MCS1, + MPT_RATE_VHT2SS_MCS2, + MPT_RATE_VHT2SS_MCS3, + MPT_RATE_VHT2SS_MCS4, + MPT_RATE_VHT2SS_MCS5, + MPT_RATE_VHT2SS_MCS6, + MPT_RATE_VHT2SS_MCS7, + MPT_RATE_VHT2SS_MCS8, + MPT_RATE_VHT2SS_MCS9, /* #63 */ + MPT_RATE_VHT3SS_MCS0, + MPT_RATE_VHT3SS_MCS1, + MPT_RATE_VHT3SS_MCS2, + MPT_RATE_VHT3SS_MCS3, + MPT_RATE_VHT3SS_MCS4, + MPT_RATE_VHT3SS_MCS5, + MPT_RATE_VHT3SS_MCS6, /* #126 */ + MPT_RATE_VHT3SS_MCS7, + MPT_RATE_VHT3SS_MCS8, + MPT_RATE_VHT3SS_MCS9, + MPT_RATE_VHT4SS_MCS0, + MPT_RATE_VHT4SS_MCS1, /* #131 */ + MPT_RATE_VHT4SS_MCS2, + MPT_RATE_VHT4SS_MCS3, + MPT_RATE_VHT4SS_MCS4, + MPT_RATE_VHT4SS_MCS5, + MPT_RATE_VHT4SS_MCS6, /* #136 */ + MPT_RATE_VHT4SS_MCS7, + MPT_RATE_VHT4SS_MCS8, + MPT_RATE_VHT4SS_MCS9, + MPT_RATE_LAST +} MPT_RATE_E, *PMPT_RATE_E; + +#define MAX_TX_PWR_INDEX_N_MODE 64 /* 0x3F */ + +#define MPT_IS_CCK_RATE(_value) (MPT_RATE_1M <= _value && _value <= MPT_RATE_11M) +#define MPT_IS_OFDM_RATE(_value) (MPT_RATE_6M <= _value && _value <= MPT_RATE_54M) +#define MPT_IS_HT_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31) +#define MPT_IS_HT_1S_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7) +#define MPT_IS_HT_2S_RATE(_value) (MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15) +#define MPT_IS_HT_3S_RATE(_value) (MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23) +#define MPT_IS_HT_4S_RATE(_value) (MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31) + +#define MPT_IS_VHT_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) +#define MPT_IS_VHT_1S_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9) +#define MPT_IS_VHT_2S_RATE(_value) (MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9) +#define MPT_IS_VHT_3S_RATE(_value) (MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9) +#define MPT_IS_VHT_4S_RATE(_value) (MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) + +#define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \ + (MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9)) +#define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \ + (MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9)) +#define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \ + (MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9)) + +typedef enum _POWER_MODE_ { + POWER_LOW = 0, + POWER_NORMAL +} POWER_MODE; + +/* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */ +typedef enum _OFDM_TX_MODE { + OFDM_ALL_OFF = 0, + OFDM_ContinuousTx = 1, + OFDM_SingleCarrier = 2, + OFDM_SingleTone = 4, +} OFDM_TX_MODE; + +#define RX_PKT_BROADCAST 1 +#define RX_PKT_DEST_ADDR 2 +#define RX_PKT_PHY_MATCH 3 + +typedef enum _ENCRY_CTRL_STATE_ { + HW_CONTROL, /* hw encryption& decryption */ + SW_CONTROL, /* sw encryption& decryption */ + HW_ENCRY_SW_DECRY, /* hw encryption & sw decryption */ + SW_ENCRY_HW_DECRY /* sw encryption & hw decryption */ +} ENCRY_CTRL_STATE; + +typedef enum _MPT_TXPWR_DEF { + MPT_CCK, + MPT_OFDM, /* L and HT OFDM */ + MPT_OFDM_AND_HT, + MPT_HT, + MPT_VHT +} MPT_TXPWR_DEF; + +#define IS_MPT_HT_RATE(_rate) (_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31) +#define IS_MPT_VHT_RATE(_rate) (_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9) +#define IS_MPT_CCK_RATE(_rate) (_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M) +#define IS_MPT_OFDM_RATE(_rate) (_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M) +/*************************************************************************/ + +extern s32 init_mp_priv(PADAPTER padapter); +extern void free_mp_priv(struct mp_priv *pmp_priv); +extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel); +extern void MPT_DeInitAdapter(PADAPTER padapter); +extern s32 mp_start_test(PADAPTER padapter); +extern void mp_stop_test(PADAPTER padapter); + +extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask); +extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); + +extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz); +extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz); +extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); +extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); +extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); +extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); + +void SetChannel(PADAPTER pAdapter); +void SetBandwidth(PADAPTER pAdapter); +int SetTxPower(PADAPTER pAdapter); +void SetAntenna(PADAPTER pAdapter); +void SetDataRate(PADAPTER pAdapter); +void SetAntenna(PADAPTER pAdapter); +s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther); +void GetThermalMeter(PADAPTER pAdapter, u8 *value); +void SetContinuousTx(PADAPTER pAdapter, u8 bStart); +void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); +void SetSingleToneTx(PADAPTER pAdapter, u8 bStart); +void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); +void PhySetTxPowerLevel(PADAPTER pAdapter); +void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc); +void SetPacketTx(PADAPTER padapter); +void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB); +void ResetPhyRxPktCount(PADAPTER pAdapter); +u32 GetPhyRxPktReceived(PADAPTER pAdapter); +u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter); +s32 SetPowerTracking(PADAPTER padapter, u8 enable); +void GetPowerTracking(PADAPTER padapter, u8 *enable); +u32 mp_query_psd(PADAPTER pAdapter, u8 *data); +void rtw_mp_trigger_iqk(PADAPTER padapter); +void rtw_mp_trigger_lck(PADAPTER padapter); + +void hal_mpt_SwitchRfSetting(PADAPTER pAdapter); +s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable); +void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable); +void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14); +void hal_mpt_SetChannel(PADAPTER pAdapter); +void hal_mpt_SetBandwidth(PADAPTER pAdapter); +void hal_mpt_SetTxPower(PADAPTER pAdapter); +void hal_mpt_SetDataRate(PADAPTER pAdapter); +void hal_mpt_SetAntenna(PADAPTER pAdapter); +s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); +void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter); +u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter); +void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value); +void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); +void mpt_ProSetPMacTx(PADAPTER Adapter); +void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain); +u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter); +ULONG mpt_ProQueryCalTxPower(PADAPTER pAdapter, u8 RfPath); +void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart); +u8 mpt_to_mgnt_rate(u32 MptRateIdx); +u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr); +u32 mp_join(PADAPTER padapter, u8 mode); +u32 hal_mpt_query_phytxok(PADAPTER pAdapter); + +void +PMAC_Get_Pkt_Param( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo +); +void +CCK_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo +); +void +PMAC_Nsym_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo +); +void +L_SIG_generator( + UINT N_SYM, /* Max: 750*/ + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo +); + +void HT_SIG_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo); + +void VHT_SIG_A_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo); + +void VHT_SIG_B_generator( + PRT_PMAC_TX_INFO pPMacTxInfo); + +void VHT_Delimiter_generator( + PRT_PMAC_TX_INFO pPMacTxInfo); + +int rtw_mp_write_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_read_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_write_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_read_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_start(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_stop(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_rate(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_channel(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_bandwidth(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_txpower_index(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_txpower(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_txpower(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_ant_tx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_ant_rx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_set_ctx_destAddr(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_ctx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_disable_bt_coexist(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_disable_bt_coexist(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_arx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_trx_query(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_pwrtrk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_psd(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_thermal(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_reset_stats(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_dump(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_phypara(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_SetRFPath(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_QueryDrv(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_PwrCtlDM(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_getver(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_mon(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_efuse_mask_file(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_SetBT(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra); +int rtw_mp_tx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_rx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_hwtx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +u8 HwRateToMPTRate(u8 rate); +int rtw_mp_iqk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_lck(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +#endif /* _RTW_MP_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_mp_ioctl.h b/drivers/staging/rtl8821ce/include/rtw_mp_ioctl.h new file mode 100644 index 000000000000..1e3287e426be --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mp_ioctl.h @@ -0,0 +1,301 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_MP_IOCTL_H_ +#define _RTW_MP_IOCTL_H_ + +#include <mp_custom_oid.h> +#include <rtw_mp.h> + +/* ------------------------------------------------------------------------------ */ +typedef struct CFG_DBG_MSG_STRUCT { + u32 DebugLevel; + u32 DebugComponent_H32; + u32 DebugComponent_L32; +} CFG_DBG_MSG_STRUCT, *PCFG_DBG_MSG_STRUCT; + +typedef struct _RW_REG { + u32 offset; + u32 width; + u32 value; +} mp_rw_reg, RW_Reg, *pRW_Reg; + +/* for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM */ +typedef struct _EEPROM_RW_PARAM { + u32 offset; + u16 value; +} eeprom_rw_param, EEPROM_RWParam, *pEEPROM_RWParam; + +typedef struct _EFUSE_ACCESS_STRUCT_ { + u16 start_addr; + u16 cnts; + u8 data[0]; +} EFUSE_ACCESS_STRUCT, *PEFUSE_ACCESS_STRUCT; + +typedef struct _BURST_RW_REG { + u32 offset; + u32 len; + u8 Data[256]; +} burst_rw_reg, Burst_RW_Reg, *pBurst_RW_Reg; + +typedef struct _USB_VendorReq { + u8 bRequest; + u16 wValue; + u16 wIndex; + u16 wLength; + u8 u8Dir;/* 0:OUT, 1:IN */ + u8 u8InData; +} usb_vendor_req, USB_VendorReq, *pUSB_VendorReq; + +typedef struct _DR_VARIABLE_STRUCT_ { + u8 offset; + u32 variable; +} DR_VARIABLE_STRUCT; + +/* int mp_start_joinbss(_adapter *padapter, NDIS_802_11_SSID *pssid); */ + +/* void _irqlevel_changed_(_irqL *irqlevel, BOOLEANunsigned char bLower); */ +#define _irqlevel_changed_(a, b) + +/* oid_rtl_seg_81_80_00 */ +NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_priv); +/* oid_rtl_seg_81_80_20 */ +NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv); + +/* oid_rtl_seg_81_87 */ +NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv); + +/* oid_rtl_seg_81_85 */ +NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv); + +/* oid_rtl_seg_87_11_00 */ +NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_write16_eeprom_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_wr_attrib_mem_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv); +/* oid_rtl_seg_87_11_20 */ +NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv); +/* oid_rtl_seg_87_11_50 */ +NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv); +/* oid_rtl_seg_87_11_F0 */ +NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv); + +/* oid_rtl_seg_87_12_00 */ +NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv); + + +extern struct oid_obj_priv oid_rtl_seg_81_80_00[32]; +extern struct oid_obj_priv oid_rtl_seg_81_80_20[16]; +extern struct oid_obj_priv oid_rtl_seg_81_80_40[6]; +extern struct oid_obj_priv oid_rtl_seg_81_80_80[3]; + +extern struct oid_obj_priv oid_rtl_seg_81_85[1]; +extern struct oid_obj_priv oid_rtl_seg_81_87[5]; + +extern struct oid_obj_priv oid_rtl_seg_87_11_00[32]; +extern struct oid_obj_priv oid_rtl_seg_87_11_20[5]; +extern struct oid_obj_priv oid_rtl_seg_87_11_50[2]; +extern struct oid_obj_priv oid_rtl_seg_87_11_80[1]; +extern struct oid_obj_priv oid_rtl_seg_87_11_B0[1]; +extern struct oid_obj_priv oid_rtl_seg_87_11_F0[16]; + +extern struct oid_obj_priv oid_rtl_seg_87_12_00[32]; + + +struct rwreg_param { + u32 offset; + u32 width; + u32 value; +}; + +struct bbreg_param { + u32 offset; + u32 phymask; + u32 value; +}; +/* +struct rfchannel_param{ + u32 ch; + u32 modem; +}; +*/ +struct txpower_param { + u32 pwr_index; +}; + +struct datarate_param { + u32 rate_index; +}; + +struct rfintfs_parm { + u32 rfintfs; +}; + +typedef struct _mp_xmit_parm_ { + u8 enable; + u32 count; + u16 length; + u8 payload_type; + u8 da[ETH_ALEN]; +} MP_XMIT_PARM, *PMP_XMIT_PARM; + +struct mp_xmit_packet { + u32 len; + u32 mem[MAX_MP_XMITBUF_SZ >> 2]; +}; + +struct psmode_param { + u32 ps_mode; + u32 smart_ps; +}; + +/* for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM */ +struct eeprom_rw_param { + u32 offset; + u16 value; +}; + +struct mp_ioctl_handler { + u32 paramsize; + u32(*handler)(struct oid_par_priv *poid_par_priv); + u32 oid; +}; + +struct mp_ioctl_param { + u32 subcode; + u32 len; + u8 data[0]; +}; + +#define GEN_MP_IOCTL_SUBCODE(code) _MP_IOCTL_ ## code ## _CMD_ + +enum RTL871X_MP_IOCTL_SUBCODE { + GEN_MP_IOCTL_SUBCODE(MP_START), /*0*/ + GEN_MP_IOCTL_SUBCODE(MP_STOP), + GEN_MP_IOCTL_SUBCODE(READ_REG), + GEN_MP_IOCTL_SUBCODE(WRITE_REG), + GEN_MP_IOCTL_SUBCODE(READ_BB_REG), + GEN_MP_IOCTL_SUBCODE(WRITE_BB_REG), /*5*/ + GEN_MP_IOCTL_SUBCODE(READ_RF_REG), + GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG), + GEN_MP_IOCTL_SUBCODE(SET_CHANNEL), + GEN_MP_IOCTL_SUBCODE(SET_TXPOWER), + GEN_MP_IOCTL_SUBCODE(SET_DATARATE), /*10*/ + GEN_MP_IOCTL_SUBCODE(SET_BANDWIDTH), + GEN_MP_IOCTL_SUBCODE(SET_ANTENNA), + GEN_MP_IOCTL_SUBCODE(CNTU_TX), + GEN_MP_IOCTL_SUBCODE(SC_TX), + GEN_MP_IOCTL_SUBCODE(CS_TX), /*15*/ + GEN_MP_IOCTL_SUBCODE(ST_TX), + GEN_MP_IOCTL_SUBCODE(IOCTL_XMIT_PACKET), + GEN_MP_IOCTL_SUBCODE(SET_RX_PKT_TYPE), + GEN_MP_IOCTL_SUBCODE(RESET_PHY_RX_PKT_CNT), + GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_RECV), /*20*/ + GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_ERROR), + GEN_MP_IOCTL_SUBCODE(READ16_EEPROM), + GEN_MP_IOCTL_SUBCODE(WRITE16_EEPROM), + GEN_MP_IOCTL_SUBCODE(EFUSE), + GEN_MP_IOCTL_SUBCODE(EFUSE_MAP), /*25*/ + GEN_MP_IOCTL_SUBCODE(GET_EFUSE_MAX_SIZE), + GEN_MP_IOCTL_SUBCODE(GET_EFUSE_CURRENT_SIZE), + GEN_MP_IOCTL_SUBCODE(GET_THERMAL_METER), + GEN_MP_IOCTL_SUBCODE(SET_PTM), + GEN_MP_IOCTL_SUBCODE(SET_POWER_DOWN), /*30*/ + GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO), + GEN_MP_IOCTL_SUBCODE(SET_DM_BT), /*32*/ + GEN_MP_IOCTL_SUBCODE(DEL_BA), /*33*/ + GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS), /*34*/ + MAX_MP_IOCTL_SUBCODE, +}; + +u32 mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv); + + +extern struct mp_ioctl_handler mp_ioctl_hdl[]; + + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_mp_phy_regdef.h b/drivers/staging/rtl8821ce/include/rtw_mp_phy_regdef.h new file mode 100644 index 000000000000..4ec28fa5bb21 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_mp_phy_regdef.h @@ -0,0 +1,1071 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/***************************************************************************** + * + * Module: __RTW_MP_PHY_REGDEF_H_ + * + * + * Note: 1. Define PMAC/BB register map + * 2. Define RF register map + * 3. PMAC/BB register bit mask. + * 4. RF reg bit mask. + * 5. Other BB/RF relative definition. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * 09/25/2008 MH 1. Add RL6052 register definition + * + *****************************************************************************/ +#ifndef __RTW_MP_PHY_REGDEF_H_ +#define __RTW_MP_PHY_REGDEF_H_ + +/*--------------------------Define Parameters-------------------------------*/ + +/* ************************************************************ + * 8192S Regsiter offset definition + * ************************************************************ */ + +/* + * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF + * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF + * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 + * 3. RF register 0x00-2E + * 4. Bit Mask for BB/RF register + * 5. Other defintion for BB/RF R/W + * */ + +/* + * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF + * 1. Page1(0x100) + * */ +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +/* + * 2. Page2(0x200) + * + * The following two definition are only used for USB interface. + * #define RF_BB_CMD_ADDR 0x02c0 */ /* RF/BB read/write command address. + * #define RF_BB_CMD_DATA 0x02c4 */ /* RF/BB read/write command data. */ + +/* + * 3. Page8(0x800) + * */ +#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */ + +#define rFPGA0_TxInfo 0x804 /* Status report?? */ +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ + +#define rFPGA0_RFTiming1 0x810 /* Useless now */ +#define rFPGA0_RFTiming2 0x814 +/* #define rFPGA0_XC_RFTiming 0x818 */ +/* #define rFPGA0_XD_RFTiming 0x81c */ + +#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rFPGA0_XC_HSSIParameter1 0x830 +#define rFPGA0_XC_HSSIParameter2 0x834 +#define rFPGA0_XD_HSSIParameter1 0x838 +#define rFPGA0_XD_HSSIParameter2 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rFPGA0_XC_LSSIParameter 0x848 +#define rFPGA0_XD_LSSIParameter 0x84c + +#define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rFPGA0_XC_RFInterfaceOE 0x868 +#define rFPGA0_XD_RFInterfaceOE 0x86c + +#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 /* Useless now */ +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 /* Useless now */ +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */ +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ + +/* + * 4. Page9(0x900) + * */ +#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */ + +#define rFPGA1_TxBlock 0x904 /* Useless now */ +#define rFPGA1_DebugSelect 0x908 /* Useless now */ +#define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */ +#define rS0S1_PathSwitch 0x948 + +/* + * 5. PageA(0xA00) + * + * Set Control channel to upper or lower. These settings are required only for 40MHz */ +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */ +#define rCCK0_CCA 0xa08 /* Disable init gain now */ /* Init gain */ + +#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ /* Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ +#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ +#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ +#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 /* 0xa57 */ +#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ +#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ + +/* + * 6. PageC(0xC00) + * */ +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ +#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */ +#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ +#define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ +#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ + +#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ +#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ +#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ +#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ + +#define rOFDM0_XAAGCCore1 0xc50 /* DIG */ +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_RxIQExtAnta 0xca0 + +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + +/* + * 7. PageD(0xD00) + * */ +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 /* No setting now */ +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ +#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ +#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ + +#define rOFDM_ShortCFOAB 0xdac /* No setting now */ +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + +/* + * 8. PageE(0xE00) + * */ +#define rTxAGC_Rate18_06 0xe00 +#define rTxAGC_Rate54_24 0xe04 +#define rTxAGC_CCK_Mcs32 0xe08 +#define rTxAGC_Mcs03_Mcs00 0xe10 +#define rTxAGC_Mcs07_Mcs04 0xe14 +#define rTxAGC_Mcs11_Mcs08 0xe18 +#define rTxAGC_Mcs15_Mcs12 0xe1c + +/* Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] */ +#define rRx_Wait_CCCA 0xe70 +#define rAnapar_Ctrl_BB 0xee0 + +/* + * 7. RF Register 0x00-0x2E (RF 8256) + * RF-0222D 0x00-3F + * + * Zebra1 */ +#define rZebra1_HSSIEnable 0x0 /* Useless now */ +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +/* #if (RTL92SE_FPGA_VERIFY == 1) */ +#define rZebra1_Channel 0x7 /* RF channel switch + * #else */ + +/* #endif */ +#define rZebra1_TxGain 0x8 /* Useless now */ +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +/* Zebra4 */ +#define rGlobalCtrl 0 /* Useless now */ +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +/* RTL8258 */ +#define rRTL8258_TxLPF 0x11 /* Useless now */ +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +/* + * RL6052 Register definition + * */ +#define RF_AC 0x00 /* */ + +#define RF_IQADJ_G1 0x01 /* */ +#define RF_IQADJ_G2 0x02 /* */ +#define RF_POW_TRSW 0x05 /* */ + +#define RF_GAIN_RX 0x06 /* */ +#define RF_GAIN_TX 0x07 /* */ + +#define RF_TXM_IDAC 0x08 /* */ +#define RF_BS_IQGEN 0x0F /* */ + +#define RF_MODE1 0x10 /* */ +#define RF_MODE2 0x11 /* */ + +#define RF_RX_AGC_HP 0x12 /* */ +#define RF_TX_AGC 0x13 /* */ +#define RF_BIAS 0x14 /* */ +#define RF_IPA 0x15 /* */ +#define RF_TXBIAS 0x16 +#define RF_POW_ABILITY 0x17 /* */ +#define RF_MODE_AG 0x18 /* */ +#define rRfChannel 0x18 /* RF channel and BW switch */ +#define RF_CHNLBW 0x18 /* RF channel and BW switch */ +#define RF_TOP 0x19 /* */ + +#define RF_RX_G1 0x1A /* */ +#define RF_RX_G2 0x1B /* */ + +#define RF_RX_BB2 0x1C /* */ +#define RF_RX_BB1 0x1D /* */ + +#define RF_RCK1 0x1E /* */ +#define RF_RCK2 0x1F /* */ + +#define RF_TX_G1 0x20 /* */ +#define RF_TX_G2 0x21 /* */ +#define RF_TX_G3 0x22 /* */ + +#define RF_TX_BB1 0x23 /* */ + +#define RF_T_METER 0x24 /* */ + +#define RF_SYN_G1 0x25 /* RF TX Power control */ +#define RF_SYN_G2 0x26 /* RF TX Power control */ +#define RF_SYN_G3 0x27 /* RF TX Power control */ +#define RF_SYN_G4 0x28 /* RF TX Power control */ +#define RF_SYN_G5 0x29 /* RF TX Power control */ +#define RF_SYN_G6 0x2A /* RF TX Power control */ +#define RF_SYN_G7 0x2B /* RF TX Power control */ +#define RF_SYN_G8 0x2C /* RF TX Power control */ + +#define RF_RCK_OS 0x30 /* RF TX PA control */ + +#define RF_TXPA_G1 0x31 /* RF TX PA control */ +#define RF_TXPA_G2 0x32 /* RF TX PA control */ +#define RF_TXPA_G3 0x33 /* RF TX PA control */ + +/* + * Bit Mask + * + * 1. Page1(0x100) */ +#define bBBResetB 0x100 /* Useless now? */ +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +/* 2. Page8(0x800) */ +#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 /* Useless now */ +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 /* Useless now */ +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf /* Reg0x814 */ +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 /* T2R */ +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 /* chane gain at continue Tx */ +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 /* Useless now + * #define bHWSISelect 0x8 */ +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ + +#define bRFSI_TRSW 0x20 /* Useless now */ +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + #define bLSSIReadAddress 0x7f800000 /* T65 RF */ +#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ + #define bLSSIReadBackData 0xfffff /* T65 RF */ +#define bLSSIReadOKFlag 0x1000 /* Useless now */ +#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ + +#define b80MClkDelay 0x18000000 /* Useless */ +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 /* Useless */ +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +/* 3. Page9(0x900) */ +#define bOFDMTxSC 0x30000000 /* Useless */ +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ +#define bDebugItem 0xff /* reset debug page and LWord */ +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +/* 4. PageA(0xA00) */ +#define bCCKBBMode 0x3 /* Useless */ +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ + +#define bCCKScramble 0x8 /* Useless */ +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ +#define bCCKFixedRxAGC 0x8000 +/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +/* 5. PageC(0xC00) */ +#define bNumOfSTF 0x3 /* Useless */ +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 /* the threshold for high power */ +#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +/* #define bRxMF_Hold 0x3800 */ +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +/* 6. PageE(0xE00) */ +#define bSTBCEn 0x4 /* Useless */ +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +/* #define bRxPath1 0x01 */ +/* #define bRxPath2 0x02 */ +/* #define bRxPath3 0x04 */ +/* #define bRxPath4 0x08 */ +/* #define bTxPath1 0x10 */ +/* #define bTxPath2 0x20 */ +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 /* total */ +#define bShortCFOFLength 11 /* fraction */ +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf /* Useless */ +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 /* Useless */ +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 /* Useless */ +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +#define bTxAGCRate18_06 0x7f7f7f7f /* Useless */ +#define bTxAGCRate54_24 0x7f7f7f7f +#define bTxAGCRateMCS32 0x7f +#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f +#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f +#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f +#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f + +/* Rx Pseduo noise */ +#define bRxPesudoNoiseOn 0x20000000 /* Useless */ +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +/* 7. RF Register + * Zebra1 */ +#define bZebra1_HSSIEnable 0x8 /* Useless */ +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +/* Zebra4 */ +#define bRTL8256RegModeCtrl1 0x100 /* Useless */ +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +/* RTL8258 */ +#define bRTL8258_TxLPFBW 0xc /* Useless */ +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + +/* + * Other Definition + * */ + +/* byte endable for sb_write */ +#define bByte0 0x1 /* Useless */ +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +/* for PutRegsetting & GetRegSetting BitMask */ +#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMaskH4Bits 0xf0000000 +#define bMaskH3Bytes 0xffffff00 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f +#define bMask12Bits 0xfff + +/* for PutRFRegsetting & GetRFRegSetting BitMask */ +/* #define bMask12Bits 0xfffff */ /* RF Reg mask bits */ +/* #define bMask20Bits 0xfffff */ /* RF Reg mask bits T65 RF */ +#define bRFRegOffsetMask 0xfffff +#define bEnable 0x1 /* Useless */ +#define bDisable 0x0 + +#define LeftAntenna 0x0 /* Useless */ +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 /* 500ms */ /* Useless */ +#define tUpdateRxCounter 100 /* 100ms */ + +#define rateCCK 0 /* Useless */ +#define rateOFDM 1 +#define rateHT 2 + +/* define Register-End */ +#define bPMAC_End 0x1ff /* Useless */ +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +/* define max debug item in each debug page + * #define bMaxItem_FPGA_PHY0 0x9 + * #define bMaxItem_FPGA_PHY1 0x3 + * #define bMaxItem_PHY_11B 0x16 + * #define bMaxItem_OFDM_PHY0 0x29 + * #define bMaxItem_OFDM_PHY1 0x0 */ + +#define bPMACControl 0x0 /* Useless */ +#define bWMACControl 0x1 +#define bWNICControl 0x2 + + +#define RCR_AAP BIT(0) /* accept all physical address */ +#define RCR_APM BIT(1) /* accept physical match */ +#define RCR_AM BIT(2) /* accept multicast */ +#define RCR_AB BIT(3) /* accept broadcast */ +#define RCR_ACRC32 BIT(5) /* accept error packet */ +#define RCR_9356SEL BIT(6) +#define RCR_AICV BIT(9) /* Accept ICV error packet */ +#define RCR_RXFTH0 (BIT(13) | BIT(14) | BIT(15)) /* Rx FIFO threshold */ +#define RCR_ADF BIT(18) /* Accept Data(frame type) frame */ +#define RCR_ACF BIT(19) /* Accept control frame */ +#define RCR_AMF BIT(20) /* Accept management frame */ +#define RCR_ADD3 BIT(21) +#define RCR_APWRMGT BIT(22) /* Accept power management packet */ +#define RCR_CBSSID BIT(23) /* Accept BSSID match packet */ +#define RCR_ENMARP BIT(28) /* enable mac auto reset phy */ +#define RCR_EnCS1 BIT(29) /* enable carrier sense method 1 */ +#define RCR_EnCS2 BIT(30) /* enable carrier sense method 2 */ +#define RCR_OnlyErlPkt BIT(31) /* Rx Early mode is performed for packet size greater than 1536 */ + +/*--------------------------Define Parameters-------------------------------*/ + +#endif /* __INC_HAL8192SPHYREG_H */ diff --git a/drivers/staging/rtl8821ce/include/rtw_odm.h b/drivers/staging/rtl8821ce/include/rtw_odm.h new file mode 100644 index 000000000000..a87ab2c59f48 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_odm.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_ODM_H__ +#define __RTW_ODM_H__ + +#include <drv_types.h> +#include "../hal/phydm/phydm_types.h" +/* +* This file provides utilities/wrappers for rtw driver to use ODM +*/ + +void rtw_odm_init_ic_type(_adapter *adapter); + +void rtw_odm_set_force_igi_lb(_adapter *adapter, u8 lb); +u8 rtw_odm_get_force_igi_lb(_adapter *adapter); + +void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter); + +bool rtw_odm_adaptivity_needed(_adapter *adapter); +void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter); +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 th_l2h_ini, s8 th_edcca_hl_diff, s8 th_l2h_ini_mode2, s8 th_edcca_hl_diff_mode2, u8 edcca_enable); +void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter); +void rtw_odm_acquirespinlock(_adapter *adapter, enum rt_spinlock_type type); +void rtw_odm_releasespinlock(_adapter *adapter, enum rt_spinlock_type type); + +u8 rtw_odm_get_dfs_domain(_adapter *adapter); +u8 rtw_odm_dfs_domain_unknown(_adapter *adapter); + +void rtw_odm_parse_rx_phy_status_chinfo(union recv_frame *rframe, u8 *phys); + +#endif /* __RTW_ODM_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_p2p.h b/drivers/staging/rtl8821ce/include/rtw_p2p.h new file mode 100644 index 000000000000..c251e52f92b9 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_p2p.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_P2P_H_ +#define __RTW_P2P_H_ + +u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 *pssid, u8 ussidlen, u8 *pdev_raddr); +u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code); +u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +int rtw_init_wifi_display_info(_adapter *padapter); +void rtw_wfd_enable(_adapter *adapter, bool on); +void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port); +void rtw_tdls_wfd_enable(_adapter *adapter, bool on); + +u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled); +u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); + +u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf); + +void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe); + +u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta); +u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe); +u8 process_p2p_group_negotation_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u8 process_p2p_group_negotation_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u8 process_p2p_group_negotation_confirm(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength); + +s32 p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType, u8 *buf); + +void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength); +void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state); +u8 p2p_ps_wk_cmd(_adapter *padapter, u8 p2p_ps_state, u8 enqueue); + + +void reset_global_wifidirect_info(_adapter *padapter); +void rtw_init_wifidirect_timers(_adapter *padapter); +void rtw_init_wifidirect_addrs(_adapter *padapter, u8 *dev_addr, u8 *iface_addr); +void init_wifidirect_info(_adapter *padapter, enum P2P_ROLE role); +int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role); + +static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) +{ + if (wdinfo->p2p_state != state) { + /* wdinfo->pre_p2p_state = wdinfo->p2p_state; */ + wdinfo->p2p_state = state; + } +} +static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) +{ + if (wdinfo->pre_p2p_state != state) + wdinfo->pre_p2p_state = state; +} +static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) +{ + if (wdinfo->role != role) + wdinfo->role = role; +} +static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo) +{ + return wdinfo->p2p_state; +} +static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo) +{ + return wdinfo->pre_p2p_state; +} +static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo) +{ + return wdinfo->role; +} +static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) +{ + return wdinfo->p2p_state == state; +} +static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) +{ + return wdinfo->role == role; +} + +#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) +#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) +#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) +/* #define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) */ + +#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) +#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo) +#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo) +#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state) +#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role) + +#define rtw_p2p_findphase_ex_set(wdinfo, value) \ + (wdinfo)->find_phase_state_exchange_cnt = (value) + +/* is this find phase exchange for social channel scan? */ +#define rtw_p2p_findphase_ex_is_social(wdinfo) \ + (wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST + +/* should we need find phase exchange anymore? */ +#define rtw_p2p_findphase_ex_is_needed(wdinfo) \ + ((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \ + (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE && \ + !(wdinfo)->rx_invitereq_info.scan_op_ch_only && \ + !(wdinfo)->p2p_info.scan_op_ch_only) + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_pwrctrl.h b/drivers/staging/rtl8821ce/include/rtw_pwrctrl.h new file mode 100644 index 000000000000..20fd426d12b7 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_pwrctrl.h @@ -0,0 +1,358 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_PWRCTRL_H_ +#define __RTW_PWRCTRL_H_ + +#define FW_PWR0 0 +#define FW_PWR1 1 +#define FW_PWR2 2 +#define FW_PWR3 3 + +#define HW_PWR0 7 +#define HW_PWR1 6 +#define HW_PWR2 2 +#define HW_PWR3 0 +#define HW_PWR4 8 + +#define FW_PWRMSK 0x7 + +#define XMIT_ALIVE BIT(0) +#define RECV_ALIVE BIT(1) +#define CMD_ALIVE BIT(2) +#define EVT_ALIVE BIT(3) +#define BTCOEX_ALIVE BIT(4) + + +enum Power_Mgnt { + PS_MODE_ACTIVE = 0 , + PS_MODE_MIN , + PS_MODE_MAX , + PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */ + PS_MODE_VOIP , + PS_MODE_UAPSD_WMM , + PS_MODE_UAPSD , + PS_MODE_IBSS , + PS_MODE_WWLAN , + PM_Radio_Off , + PM_Card_Disable , + PS_MODE_NUM, +}; + +enum lps_level { + LPS_NORMAL = 0, + LPS_LCLK, + LPS_PG, + LPS_LEVEL_MAX, +}; + + +/* + BIT[2:0] = HW state + BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state + BIT[4] = sub-state +*/ + +#define PS_DPS BIT(0) +#define PS_LCLK (PS_DPS) +#define PS_RF_OFF BIT(1) +#define PS_ALL_ON BIT(2) +#define PS_ST_ACTIVE BIT(3) + +#define PS_ISR_ENABLE BIT(4) +#define PS_IMR_ENABLE BIT(5) +#define PS_ACK BIT(6) +#define PS_TOGGLE BIT(7) + +#define PS_STATE_MASK (0x0F) +#define PS_STATE_HW_MASK (0x07) +#define PS_SEQ_MASK (0xc0) + +#define PS_STATE(x) (PS_STATE_MASK & (x)) +#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) +#define PS_SEQ(x) (PS_SEQ_MASK & (x)) + +#define PS_STATE_S0 (PS_DPS) +#define PS_STATE_S1 (PS_LCLK) +#define PS_STATE_S2 (PS_RF_OFF) +#define PS_STATE_S3 (PS_ALL_ON) +#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) + +#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) +#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) +#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) + +struct reportpwrstate_parm { + unsigned char mode; + unsigned char state; /* the CPWM value */ + unsigned short rsvd; +}; + +typedef _sema _pwrlock; + +__inline static void _init_pwrlock(_pwrlock *plock) +{ + _rtw_init_sema(plock, 1); +} + +__inline static void _free_pwrlock(_pwrlock *plock) +{ + _rtw_free_sema(plock); +} + +__inline static void _enter_pwrlock(_pwrlock *plock) +{ + _rtw_down_sema(plock); +} + +__inline static void _exit_pwrlock(_pwrlock *plock) +{ + _rtw_up_sema(plock); +} + +#define LPS_DELAY_TIME 1*HZ /* 1 sec */ + +#define EXE_PWR_NONE 0x01 +#define EXE_PWR_IPS 0x02 +#define EXE_PWR_LPS 0x04 + +/* RF state. */ +typedef enum _rt_rf_power_state { + rf_on, /* RF is on after RFSleep or RFOff */ + rf_sleep, /* 802.11 Power Save mode */ + rf_off, /* HW/SW Radio OFF or Inactive Power Save */ + /* =====Add the new RF state above this line===== */ + rf_max +} rt_rf_power_state; + +/* RF Off Level for IPS or HW/SW radio off */ +#define RT_RF_OFF_LEVL_ASPM BIT(0) /* PCI ASPM */ +#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /* PCI clock request */ +#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /* PCI D3 mode */ +#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) /* NIC halt, re-initialize hw parameters */ +#define RT_RF_OFF_LEVL_FREE_FW BIT(4) /* FW free, re-download the FW */ +#define RT_RF_OFF_LEVL_FW_32K BIT(5) /* FW in 32k */ +#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) /* Always enable ASPM and Clock Req in initialization. */ +#define RT_RF_LPS_DISALBE_2R BIT(30) /* When LPS is on, disable 2R if no packet is received or transmittd. */ +#define RT_RF_LPS_LEVEL_ASPM BIT(31) /* LPS with ASPM */ + +#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE) +#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG))) +#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG) + +/* ASPM OSC Control bit, added by Roger, 2013.03.29. */ +#define RT_PCI_ASPM_OSC_IGNORE 0 /* PCI ASPM ignore OSC control in default */ +#define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */ +#define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */ + +enum _PS_BBRegBackup_ { + PSBBREG_RF0 = 0, + PSBBREG_RF1, + PSBBREG_RF2, + PSBBREG_AFE0, + PSBBREG_TOTALCNT +}; + +enum { /* for ips_mode */ + IPS_NONE = 0, + IPS_NORMAL, + IPS_LEVEL_2, + IPS_NUM +}; + +/* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */ +typedef enum _PS_DENY_REASON { + PS_DENY_DRV_INITIAL = 0, + PS_DENY_SCAN, + PS_DENY_JOIN, + PS_DENY_DISCONNECT, + PS_DENY_SUSPEND, + PS_DENY_IOCTL, + PS_DENY_MGNT_TX, + PS_DENY_MONITOR_MODE, + PS_DENY_BEAMFORMING, /* Beamforming */ + PS_DENY_DRV_REMOVE = 30, + PS_DENY_OTHERS = 31 +} PS_DENY_REASON; + + + +struct aoac_report { + u8 iv[8]; + u8 replay_counter_eapol_key[8]; + u8 group_key[32]; + u8 key_index; + u8 security_type; +}; + +struct pwrctrl_priv { + _pwrlock lock; + _pwrlock check_32k_lock; + volatile u8 rpwm; /* requested power state for fw */ + volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */ + volatile u8 tog; /* toggling */ + volatile u8 cpwm_tog; /* toggling */ + + u8 pwr_mode; + u8 smart_ps; + u8 bcn_ant_mode; + u8 dtim; + + u32 alives; + _workitem cpwm_event; + _workitem dma_event; /*for handle un-synchronized tx dma*/ + u8 bpower_saving; /* for LPS/IPS */ + + u8 b_hw_radio_off; + u8 reg_rfoff; + u8 reg_pdnmode; /* powerdown mode */ + u32 rfoff_reason; + + /* RF OFF Level */ + u32 cur_ps_level; + u32 reg_rfps_level; + + uint ips_enter_cnts; + uint ips_leave_cnts; + uint lps_enter_cnts; + uint lps_leave_cnts; + + u8 ips_mode; + u8 ips_org_mode; + u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */ + uint bips_processing; + u32 ips_deny_time; /* will deny IPS when system time is smaller than this */ + u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */ + + /* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */ + /* Use PS_DENY_REASON to decide reason. */ + /* Don't access this variable directly without control function, */ + /* and this variable should be protected by lock. */ + u32 ps_deny; + + u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */ + + u8 fw_psmode_iface_id; + u8 bLeisurePs; + u8 LpsIdleCount; + u8 power_mgnt; + u8 org_power_mgnt; + u8 bFwCurrentInPSMode; + u32 DelayLPSLastTimeStamp; + s32 pnp_current_pwr_state; + u8 pnp_bstop_trx; + + u8 bInternalAutoSuspend; + u8 bInSuspend; + u8 bAutoResume; + u8 autopm_cnt; + u8 bSupportRemoteWakeup; + u8 wowlan_wake_reason; + u8 wowlan_last_wake_reason; + u8 wowlan_ap_mode; + u8 wowlan_mode; + u8 wowlan_p2p_mode; + u8 wowlan_pno_enable; + _timer pwr_state_check_timer; + int pwr_state_check_interval; + u8 pwr_state_check_cnts; + + int ps_flag; /* used by autosuspend */ + + rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */ + /* rt_rf_power_state current_rfpwrstate; */ + rt_rf_power_state change_rfpwrstate; + + u8 bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */ + u8 bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */ + u8 bkeepfwalive; + u8 brfoffbyhw; + unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; + + + + + + u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/ + u8 current_lps_hw_port_id; +}; + +#define rtw_get_ips_mode_req(pwrctl) \ + (pwrctl)->ips_mode_req + +#define rtw_ips_mode_req(pwrctl, ips_mode) \ + (pwrctl)->ips_mode_req = (ips_mode) + +#define RTW_PWR_STATE_CHK_INTERVAL 2000 + +#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \ + do { \ + /*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \ + _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \ + } while (0) + +#define rtw_set_pwr_state_check_timer(pwrctl) \ + _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval) + +extern void rtw_init_pwrctrl_priv(_adapter *adapter); +extern void rtw_free_pwrctrl_priv(_adapter *adapter); + + +extern void LeaveAllPowerSaveMode(PADAPTER Adapter); +extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter); +void _ips_enter(_adapter *padapter); +void ips_enter(_adapter *padapter); +int _ips_leave(_adapter *padapter); +int ips_leave(_adapter *padapter); + +void rtw_ps_processor(_adapter *padapter); + + +int rtw_fw_ps_state(PADAPTER padapter); + +s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms); +void LPS_Enter(PADAPTER padapter, const char *msg); +void LPS_Leave(PADAPTER padapter, const char *msg); +void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets); +void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg); +void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable); +void rtw_set_rpwm(_adapter *padapter, u8 val8); + + +#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE +#define rtw_is_do_late_resume(pwrpriv) _FALSE +#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0) +#define rtw_register_early_suspend(pwrpriv) do {} while (0) +#define rtw_unregister_early_suspend(pwrpriv) do {} while (0) + +u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); +void rtw_set_ips_deny(_adapter *padapter, u32 ms); +int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller); +#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__) +#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__) +int rtw_pm_set_ips(_adapter *padapter, u8 mode); +int rtw_pm_set_lps(_adapter *padapter, u8 mode); +int rtw_pm_set_lps_level(_adapter *padapter, u8 level); + +void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason); +void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason); +u32 rtw_ps_deny_get(PADAPTER padapter); + +#endif /* __RTL871X_PWRCTRL_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_qos.h b/drivers/staging/rtl8821ce/include/rtw_qos.h new file mode 100644 index 000000000000..fc5b464a8a08 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_qos.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _RTW_QOS_H_ +#define _RTW_QOS_H_ + +struct qos_priv { + + unsigned int qos_option; /* bit mask option: u-apsd, s-apsd, ts, block ack... */ + +}; + +#endif /* _RTL871X_QOS_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_recv.h b/drivers/staging/rtl8821ce/include/rtw_recv.h new file mode 100644 index 000000000000..1db64779e3ac --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_recv.h @@ -0,0 +1,634 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_RECV_H_ +#define _RTW_RECV_H_ + +#ifdef CONFIG_SINGLE_RECV_BUF + #define NR_RECVBUFF (1) +#else + #define NR_RECVBUFF (8) +#endif /* CONFIG_SINGLE_RECV_BUF */ + #define NR_PREALLOC_RECV_SKB 8 + + #define RTL_NAPI_WEIGHT (32) + +#define NR_RECVFRAME 256 + +#define RXFRAME_ALIGN 8 +#define RXFRAME_ALIGN_SZ (1<<RXFRAME_ALIGN) + +#define DRVINFO_SZ 4 /* unit is 8bytes */ + +#define MAX_RXFRAME_CNT 512 +#define MAX_RX_NUMBLKS (32) +#define RECVFRAME_HDR_ALIGN 128 +#define MAX_CONTINUAL_NORXPACKET_COUNT 4 /* In MAX_CONTINUAL_NORXPACKET_COUNT*2 sec , no rx traffict would issue DELBA*/ + +#define PHY_RSSI_SLID_WIN_MAX 100 +#define PHY_LINKQUALITY_SLID_WIN_MAX 20 + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define RX_MPDU_QUEUE 0 +#define RX_CMD_QUEUE 1 +#define RX_MAX_QUEUE 2 + +extern u8 SNAP_ETH_TYPE_IPX[]; +extern u8 SNAP_ETH_TYPE_APPLETALK_AARP[]; +extern u8 SNAP_ETH_TYPE_APPLETALK_DDP[]; +extern u8 SNAP_ETH_TYPE_TDLS[]; +extern u8 SNAP_HDR_APPLETALK_DDP[]; + +extern u8 oui_8021h[]; +extern u8 oui_rfc1042[]; + +extern u8 rtw_rfc1042_header[]; +extern u8 rtw_bridge_tunnel_header[]; + +#define MAX_SUBFRAME_COUNT 64 + +/* for Rx reordering buffer control */ +struct recv_reorder_ctrl { + _adapter *padapter; + u8 enable; + u16 indicate_seq;/* =wstart_b, init_value=0xffff */ + u16 wend_b; + u8 wsize_b; + u8 ampdu_size; + _queue pending_recvframe_queue; + _timer reordering_ctrl_timer; + u8 bReorderWaiting; +}; + +struct stainfo_rxcache { + u16 tid_rxseq[16]; + u8 iv[16][8]; +}; + +struct smooth_rssi_data { + u32 elements[100]; /* array to store values */ + u32 index; /* index to current array to store */ + u32 total_num; /* num of valid elements */ + u32 total_val; /* sum of valid elements */ +}; + +struct signal_stat { + u8 update_req; /* used to indicate */ + u8 avg_val; /* avg of valid elements */ + u32 total_num; /* num of valid elements */ + u32 total_val; /* sum of valid elements */ +}; + +struct phy_info { + u8 RxPWDBAll; + u8 SignalQuality; /* in 0-100 index. */ + s8 RxMIMOSignalQuality[4]; /* per-path's EVM */ + u8 RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ + u8 RxMIMOSignalStrength[4]; /* in 0~100 index */ + s16 Cfo_short[4]; /* per-path's Cfo_short */ + s16 Cfo_tail[4]; /* per-path's Cfo_tail */ + s8 RxPower; /* in dBm Translate from PWdB */ + s8 RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u8 BTRxRSSIPercentage; + u8 SignalStrength; /* in 0-100 index. */ + s8 RxPwr[4]; /* per-path's pwdb */ + s8 RxSNR[4]; + u8 RxCount:2; + u8 BandWidth:2; + u8 rxsc:4; + u8 btCoexPwrAdjust; + u8 channel; /* channel number---*/ + BOOLEAN bMuPacket; /* is MU packet or not---*/ + BOOLEAN bBeamformed; +}; + +struct rx_raw_rssi { + u8 data_rate; + u8 pwdball; + s8 pwr_all; + + u8 mimo_signal_strength[4];/* in 0~100 index */ + u8 mimo_signal_quality[4]; + + s8 ofdm_pwr[4]; + u8 ofdm_snr[4]; +}; + +struct rx_pkt_attrib { + u16 pkt_len; + u8 physt; + u8 drvinfo_sz; + u8 shift_sz; + u8 hdrlen; /* the WLAN Header Len */ + u8 to_fr_ds; + u8 amsdu; + u8 qos; + u8 priority; + u8 pw_save; + u8 mdata; + u16 seq_num; + u8 frag_num; + u8 mfrag; + u8 order; + u8 privacy; /* in frame_ctrl field */ + u8 bdecrypted; + u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */ + u8 iv_len; + u8 icv_len; + u8 crc_err; + u8 icv_err; + + u16 eth_type; + + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + u8 bssid[ETH_ALEN]; + + u8 ack_policy; + +/* #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX */ + u8 tcpchk_valid; /* 0: invalid, 1: valid */ + u8 ip_chkrpt; /* 0: incorrect, 1: correct */ + u8 tcp_chkrpt; /* 0: incorrect, 1: correct */ +/* #endif */ + u8 key_index; + + u8 data_rate; + u8 ch; /* RX channel */ + u8 bw; + u8 stbc; + u8 ldpc; + u8 sgi; + u8 pkt_rpt_type; + u32 tsfl; + u32 MacIDValidEntry[2]; /* 64 bits present 64 entry. */ + u8 ppdu_cnt; + + struct phy_info phy_info; +}; + +/* These definition is used for Rx packet reordering. */ +#define SN_LESS(a, b) (((a-b) & 0x800) != 0) +#define SN_EQUAL(a, b) (a == b) +/* #define REORDER_WIN_SIZE 128 */ +/* #define REORDER_ENTRY_NUM 128 */ +#define REORDER_WAIT_TIME (50) /* (ms) */ + +#define RECVBUFF_ALIGN_SZ 8 + + #define RX_WIFI_INFO_SIZE 24 + +#define RXDESC_SIZE 24 +#define RXDESC_OFFSET RXDESC_SIZE + +struct rx_buf_desc { + /* RX has exactly one segment */ + unsigned int dword[2]; +}; + +struct recv_stat { + unsigned int rxdw[8]; +}; + +#define EOR BIT(30) + +#define PCI_MAX_RX_QUEUE 1/* MSDU packet queue, Rx Command Queue */ +#define PCI_MAX_RX_COUNT 128 +#define RX_BD_NUM PCI_MAX_RX_COUNT /* alias */ + +struct rtw_rx_ring { + struct rx_buf_desc *buf_desc; + dma_addr_t dma; + unsigned int idx; + struct sk_buff *rx_buf[PCI_MAX_RX_COUNT]; +}; + +/* +accesser of recv_priv: rtw_recv_entry(dispatch / passive level); recv_thread(passive) ; returnpkt(dispatch) +; halt(passive) ; + +using enter_critical section to protect +*/ +struct recv_priv { + _lock lock; + + + /* _queue blk_strms[MAX_RX_NUMBLKS]; */ /* keeping the block ack frame until return ack */ + _queue free_recv_queue; + _queue recv_pending_queue; + _queue uc_swdec_pending_queue; + + u8 *pallocated_frame_buf; + u8 *precv_frame_buf; + + uint free_recvframe_cnt; + + _adapter *adapter; + + u32 is_any_non_be_pkts; + + u64 rx_bytes; + u64 rx_pkts; + u64 rx_drop; + + uint rx_icv_err; + uint rx_largepacket_crcerr; + uint rx_smallpacket_crcerr; + uint rx_middlepacket_crcerr; + + struct tasklet_struct irq_prepare_beacon_tasklet; + struct tasklet_struct recv_tasklet; + struct sk_buff_head free_recv_skb_queue; + struct sk_buff_head rx_skb_queue; + struct sk_buff_head rx_napi_skb_queue; +#ifdef CONFIG_RX_INDICATE_QUEUE + struct task rx_indicate_tasklet; + struct ifqueue rx_indicate_queue; +#endif /* CONFIG_RX_INDICATE_QUEUE */ + + + u8 *pallocated_recv_buf; + u8 *precv_buf; /* 4 alignment */ + _queue free_recv_buf_queue; + u32 free_recv_buf_queue_cnt; + + /* Rx */ + struct rtw_rx_ring rx_ring[PCI_MAX_RX_QUEUE]; + int rxringcount; /* size should be PCI_MAX_RX_QUEUE */ + u16 rxbuffersize; + + /* For display the phy informatiom */ + u8 is_signal_dbg; /* for debug */ + u8 signal_strength_dbg; /* for debug */ + + u8 signal_strength; + u8 signal_qual; + s8 rssi; /* translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); */ + struct rx_raw_rssi raw_rssi_info; + /* s8 rxpwdb; */ + s16 noise; + /* int RxSNRdB[2]; */ + /* s8 RxRssi[2]; */ + /* int FalseAlmCnt_all; */ + + _timer signal_stat_timer; + u32 signal_stat_sampling_interval; + /* u32 signal_stat_converging_constant; */ + struct signal_stat signal_qual_data; + struct signal_stat signal_strength_data; + u16 sink_udpport, pre_rtp_rxseq, cur_rtp_rxseq; + + BOOLEAN store_law_data_flag; +}; + +#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) + +struct sta_recv_priv { + + _lock lock; + sint option; + + /* _queue blk_strms[MAX_RX_NUMBLKS]; */ + _queue defrag_q; /* keeping the fragment frame until defrag */ + + struct stainfo_rxcache rxcache; + + /* uint sta_rx_bytes; */ + /* uint sta_rx_pkts; */ + /* uint sta_rx_fail; */ + +}; + +struct recv_buf { + _list list; + + _lock recvbuf_lock; + + u32 ref_cnt; + + PADAPTER adapter; + + u8 *pbuf; + u8 *pallocated_buf; + + u32 len; + u8 *phead; + u8 *pdata; + u8 *ptail; + u8 *pend; + + _pkt *pskb; +}; + +/* + head -----> + + data -----> + + payload + + tail -----> + + end -----> + + len = (unsigned int )(tail - data); + +*/ +struct recv_frame_hdr { + _list list; +#ifndef CONFIG_BSD_RX_USE_MBUF + struct sk_buff *pkt; + struct sk_buff *pkt_newalloc; +#else /* CONFIG_BSD_RX_USE_MBUF */ + _pkt *pkt; + _pkt *pkt_newalloc; +#endif /* CONFIG_BSD_RX_USE_MBUF */ + + _adapter *adapter; + + u8 fragcnt; + + int frame_tag; + + struct rx_pkt_attrib attrib; + + uint len; + u8 *rx_head; + u8 *rx_data; + u8 *rx_tail; + u8 *rx_end; + + void *precvbuf; + + /* */ + struct sta_info *psta; + + /* for A-MPDU Rx reordering buffer control */ + struct recv_reorder_ctrl *preorder_ctrl; + +}; + +union recv_frame { + + union { + _list list; + struct recv_frame_hdr hdr; + uint mem[RECVFRAME_HDR_ALIGN >> 2]; + } u; + + /* uint mem[MAX_RXSZ>>2]; */ + +}; + +bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset); + +typedef enum _RX_PACKET_TYPE { + NORMAL_RX,/* Normal rx packet */ + TX_REPORT1,/* CCX */ + TX_REPORT2,/* TX RPT */ + HIS_REPORT,/* USB HISR RPT */ + C2H_PACKET +} RX_PACKET_TYPE, *PRX_PACKET_TYPE; + +extern union recv_frame *_rtw_alloc_recvframe(_queue *pfree_recv_queue); /* get a free recv_frame from pfree_recv_queue */ +extern union recv_frame *rtw_alloc_recvframe(_queue *pfree_recv_queue); /* get a free recv_frame from pfree_recv_queue */ +extern void rtw_init_recvframe(union recv_frame *precvframe , struct recv_priv *precvpriv); +extern int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue); + +#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue) +extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); +extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); + +extern void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue); +u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter); + +sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); +sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); +struct recv_buf *rtw_dequeue_recvbuf(_queue *queue); + +void rtw_reordering_ctrl_timeout_handler(void *pcontext); + +void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat); +int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index); +void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index); + + +__inline static u8 *get_rxmem(union recv_frame *precvframe) +{ + /* always return rx_head... */ + if (precvframe == NULL) + return NULL; + + return precvframe->u.hdr.rx_head; +} + +__inline static u8 *get_rx_status(union recv_frame *precvframe) +{ + + return get_rxmem(precvframe); + +} + +__inline static u8 *get_recvframe_data(union recv_frame *precvframe) +{ + + /* alwasy return rx_data */ + if (precvframe == NULL) + return NULL; + + return precvframe->u.hdr.rx_data; + +} + +__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz) +{ + /* append data before rx_data */ + + /* add data to the start of recv_frame + * + * This function extends the used data area of the recv_frame at the buffer + * start. rx_data must be still larger than rx_head, after pushing. + */ + + if (precvframe == NULL) + return NULL; + + precvframe->u.hdr.rx_data -= sz ; + if (precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head) { + precvframe->u.hdr.rx_data += sz ; + return NULL; + } + + precvframe->u.hdr.len += sz; + + return precvframe->u.hdr.rx_data; + +} + +__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz) +{ + /* rx_data += sz; move rx_data sz bytes hereafter */ + + /* used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller */ + + if (precvframe == NULL) + return NULL; + + precvframe->u.hdr.rx_data += sz; + + if (precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) { + precvframe->u.hdr.rx_data -= sz; + return NULL; + } + + precvframe->u.hdr.len -= sz; + + return precvframe->u.hdr.rx_data; + +} + +__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz) +{ + /* rx_tai += sz; move rx_tail sz bytes hereafter */ + + /* used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller */ + /* after putting, rx_tail must be still larger than rx_end. */ + unsigned char *prev_rx_tail; + + /* RTW_INFO("recvframe_put: len=%d\n", sz); */ + + if (precvframe == NULL) + return NULL; + + prev_rx_tail = precvframe->u.hdr.rx_tail; + + precvframe->u.hdr.rx_tail += sz; + + if (precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) { + precvframe->u.hdr.rx_tail -= sz; + return NULL; + } + + precvframe->u.hdr.len += sz; + + return precvframe->u.hdr.rx_tail; + +} + +__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz) +{ + /* rmv data from rx_tail (by yitsen) */ + + /* used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller */ + /* after pulling, rx_end must be still larger than rx_data. */ + + if (precvframe == NULL) + return NULL; + + precvframe->u.hdr.rx_tail -= sz; + + if (precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) { + precvframe->u.hdr.rx_tail += sz; + return NULL; + } + + precvframe->u.hdr.len -= sz; + + return precvframe->u.hdr.rx_tail; + +} + +__inline static _buffer *get_rxbuf_desc(union recv_frame *precvframe) +{ + _buffer *buf_desc; + + if (precvframe == NULL) + return NULL; + + return buf_desc; +} + +__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem) +{ + /* due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame */ + /* from any given member of recv_frame. */ + /* rxmem indicates the any member/address in recv_frame */ + + return (union recv_frame *)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN); + +} + +__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt) +{ + + u8 *buf_star; + union recv_frame *precv_frame; + precv_frame = rxmem_to_recvframe((unsigned char *)buf_star); + + return precv_frame; +} + +__inline static u8 *pkt_to_recvmem(_pkt *pkt) +{ + /* return the rx_head */ + + union recv_frame *precv_frame = pkt_to_recvframe(pkt); + + return precv_frame->u.hdr.rx_head; + +} + +__inline static u8 *pkt_to_recvdata(_pkt *pkt) +{ + /* return the rx_data */ + + union recv_frame *precv_frame = pkt_to_recvframe(pkt); + + return precv_frame->u.hdr.rx_data; + +} + +__inline static sint get_recvframe_len(union recv_frame *precvframe) +{ + return precvframe->u.hdr.len; +} + +__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) +{ + s32 SignalPower; /* in dBm. */ + + /* Translate to dBm (x=y-100) */ + SignalPower = SignalStrengthIndex - 100; + + return SignalPower; +} + +struct sta_info; + +extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); + +extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); + +s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status); + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_rf.h b/drivers/staging/rtl8821ce/include/rtw_rf.h new file mode 100644 index 000000000000..80d09269df49 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_rf.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_RF_H_ +#define __RTW_RF_H_ + +#define NumRates (13) + +/* slot time for 11g */ +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + +#define CENTER_CH_2G_40M_NUM 9 +#define CENTER_CH_2G_NUM 14 +#define CENTER_CH_5G_20M_NUM 28 /* 20M center channels */ +#define CENTER_CH_5G_40M_NUM 14 /* 40M center channels */ +#define CENTER_CH_5G_80M_NUM 7 /* 80M center channels */ +#define CENTER_CH_5G_160M_NUM 3 /* 160M center channels */ +#define CENTER_CH_5G_ALL_NUM (CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM) + +#define MAX_CHANNEL_NUM_2G CENTER_CH_2G_NUM +#define MAX_CHANNEL_NUM_5G CENTER_CH_5G_20M_NUM +#define MAX_CHANNEL_NUM (MAX_CHANNEL_NUM_2G + MAX_CHANNEL_NUM_5G) + +extern u8 center_ch_2g[CENTER_CH_2G_NUM]; +extern u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM]; + +u8 center_chs_2g_num(u8 bw); +u8 center_chs_2g(u8 bw, u8 id); + +extern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM]; +extern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM]; +extern u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM]; +extern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM]; +extern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM]; + +u8 center_chs_5g_num(u8 bw); +u8 center_chs_5g(u8 bw, u8 id); + +u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset); + +u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num); + +u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group); + +typedef enum _CAPABILITY { + cESS = 0x0001, + cIBSS = 0x0002, + cPollable = 0x0004, + cPollReq = 0x0008, + cPrivacy = 0x0010, + cShortPreamble = 0x0020, + cPBCC = 0x0040, + cChannelAgility = 0x0080, + cSpectrumMgnt = 0x0100, + cQos = 0x0200, /* For HCCA, use with CF-Pollable and CF-PollReq */ + cShortSlotTime = 0x0400, + cAPSD = 0x0800, + cRM = 0x1000, /* RRM (Radio Request Measurement) */ + cDSSS_OFDM = 0x2000, + cDelayedBA = 0x4000, + cImmediateBA = 0x8000, +} CAPABILITY, *PCAPABILITY; + +enum _REG_PREAMBLE_MODE { + PREAMBLE_LONG = 1, + PREAMBLE_AUTO = 2, + PREAMBLE_SHORT = 3, +}; + +typedef enum _RF_PATH { + RF_PATH_A = 0, + RF_PATH_B = 1, + RF_PATH_C = 2, + RF_PATH_D = 3, +} RF_PATH, *PRF_PATH; + +#define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path)) + +/* Bandwidth Offset */ +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + +typedef enum _BAND_TYPE { + BAND_ON_2_4G = 0, + BAND_ON_5G = 1, + BAND_ON_BOTH = 2, + BAND_MAX = 3, +} BAND_TYPE, *PBAND_TYPE; + +extern const char *const _band_str[]; +#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)]) + +extern const u8 _band_to_band_cap[]; +#define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)]) + +/* Represent Channel Width in HT Capabilities + * */ +typedef enum _CHANNEL_WIDTH { + CHANNEL_WIDTH_20 = 0, + CHANNEL_WIDTH_40 = 1, + CHANNEL_WIDTH_80 = 2, + CHANNEL_WIDTH_160 = 3, + CHANNEL_WIDTH_80_80 = 4, + CHANNEL_WIDTH_MAX = 5, +} CHANNEL_WIDTH, *PCHANNEL_WIDTH; + +extern const char *const _ch_width_str[]; +#define ch_width_str(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_str[CHANNEL_WIDTH_MAX] : _ch_width_str[(bw)]) + +extern const u8 _ch_width_to_bw_cap[]; +#define ch_width_to_bw_cap(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] : _ch_width_to_bw_cap[(bw)]) + +/* + * Represent Extention Channel Offset in HT Capabilities + * This is available only in 40Mhz mode. + * */ +typedef enum _EXTCHNL_OFFSET { + EXTCHNL_OFFSET_NO_EXT = 0, + EXTCHNL_OFFSET_UPPER = 1, + EXTCHNL_OFFSET_NO_DEF = 2, + EXTCHNL_OFFSET_LOWER = 3, +} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET; + +typedef enum _VHT_DATA_SC { + VHT_DATA_SC_DONOT_CARE = 0, + VHT_DATA_SC_20_UPPER_OF_80MHZ = 1, + VHT_DATA_SC_20_LOWER_OF_80MHZ = 2, + VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3, + VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4, + VHT_DATA_SC_20_RECV1 = 5, + VHT_DATA_SC_20_RECV2 = 6, + VHT_DATA_SC_20_RECV3 = 7, + VHT_DATA_SC_20_RECV4 = 8, + VHT_DATA_SC_40_UPPER_OF_80MHZ = 9, + VHT_DATA_SC_40_LOWER_OF_80MHZ = 10, +} VHT_DATA_SC, *PVHT_DATA_SC_E; + +typedef enum _PROTECTION_MODE { + PROTECTION_MODE_AUTO = 0, + PROTECTION_MODE_FORCE_ENABLE = 1, + PROTECTION_MODE_FORCE_DISABLE = 2, +} PROTECTION_MODE, *PPROTECTION_MODE; + +typedef enum _RT_RF_TYPE_DEFINITION { + RF_1T2R = 0, + RF_2T4R = 1, + RF_2T2R = 2, + RF_1T1R = 3, + RF_2T2R_GREEN = 4, + RF_2T3R = 5, + RF_3T3R = 6, + RF_3T4R = 7, + RF_4T4R = 8, + + RF_TYPE_AUTO, +} RT_RF_TYPE_DEF_E; + +#define RF_TYPE_VALID(rf_type) (rf_type < RF_TYPE_AUTO) + +extern const u8 _rf_type_to_rf_tx_cnt[]; +#define rf_type_to_rf_tx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_tx_cnt[rf_type] : 0) + +extern const u8 _rf_type_to_rf_rx_cnt[]; +#define rf_type_to_rf_rx_cnt(rf_type) (RF_TYPE_VALID(rf_type) ? _rf_type_to_rf_rx_cnt[rf_type] : 0) + +int rtw_ch2freq(int chan); +int rtw_freq2ch(int freq); +bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo); + +#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */ +#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */ +#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */ +#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */ +#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */ +#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */ +#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */ +#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */ +#define RTW_MODULE_RTL8723DE_NGFF1630 BIT8 /* RTL8723DE(NGFF1630) */ + +#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF) + +struct country_chplan { + char alpha2[2]; + u8 chplan; + u8 en_11ac; +}; + +#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac) + +#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0 + +const struct country_chplan *rtw_get_chplan_from_country(const char *country_code); + +#define BB_GAIN_2G 0 +#define BB_GAIN_5GLB1 1 +#define BB_GAIN_5GLB2 2 +#define BB_GAIN_5GMB1 3 +#define BB_GAIN_5GMB2 4 +#define BB_GAIN_5GHB 5 + +#define BB_GAIN_NUM 6 + +int rtw_ch_to_bb_gain_sel(int ch); +void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset); +void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch); + +u8 rtw_is_5g_band1(u8 ch); +u8 rtw_is_5g_band2(u8 ch); +u8 rtw_is_5g_band3(u8 ch); +u8 rtw_is_5g_band4(u8 ch); + +u8 rtw_is_dfs_range(u32 hi, u32 lo); +u8 rtw_is_dfs_ch(u8 ch); +u8 rtw_is_dfs_chbw(u8 ch, u8 bw, u8 offset); +bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region); +bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region); + +#endif /* _RTL8711_RF_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_security.h b/drivers/staging/rtl8821ce/include/rtw_security.h new file mode 100644 index 000000000000..a7340182ca10 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_security.h @@ -0,0 +1,416 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_SECURITY_H_ +#define __RTW_SECURITY_H_ + +#define _NO_PRIVACY_ 0x0 +#define _WEP40_ 0x1 +#define _TKIP_ 0x2 +#define _TKIP_WTMIC_ 0x3 +#define _AES_ 0x4 +#define _WEP104_ 0x5 +#define _WEP_WPA_MIXED_ 0x07 /* WEP + WPA */ +#define _SMS4_ 0x06 +/* 802.11W use wrong key */ +#define IEEE80211W_RIGHT_KEY 0x0 +#define IEEE80211W_WRONG_KEY 0x1 +#define IEEE80211W_NO_KEY 0x2 + +#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) + +const char *security_type_str(u8 value); + +#define _WPA_IE_ID_ 0xdd +#define _WPA2_IE_ID_ 0x30 + +#define SHA256_MAC_LEN 32 +#define AES_BLOCK_SIZE 16 +#define AES_PRIV_SIZE (4 * 44) + +#define RTW_KEK_LEN 16 +#define RTW_KCK_LEN 16 +#define RTW_TKIP_MIC_LEN 8 +#define RTW_REPLAY_CTR_LEN 8 + +#define INVALID_SEC_MAC_CAM_ID 0xFF + +typedef enum { + ENCRYP_PROTOCOL_OPENSYS, /* open system */ + ENCRYP_PROTOCOL_WEP, /* WEP */ + ENCRYP_PROTOCOL_WPA, /* WPA */ + ENCRYP_PROTOCOL_WPA2, /* WPA2 */ + ENCRYP_PROTOCOL_WAPI, /* WAPI: Not support in this version */ + ENCRYP_PROTOCOL_MAX +} ENCRYP_PROTOCOL_E; + +#ifndef Ndis802_11AuthModeWPA2 +#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) +#endif + +#ifndef Ndis802_11AuthModeWPA2PSK +#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) +#endif + +union pn48 { + + u64 val; + +#ifdef __LITTLE_ENDIAN + +struct { + u8 TSC0; + u8 TSC1; + u8 TSC2; + u8 TSC3; + u8 TSC4; + u8 TSC5; + u8 TSC6; + u8 TSC7; +} _byte_; + +#else + +struct { + u8 TSC7; + u8 TSC6; + u8 TSC5; + u8 TSC4; + u8 TSC3; + u8 TSC2; + u8 TSC1; + u8 TSC0; +} _byte_; + +#endif + +}; + +union Keytype { + u8 skey[16]; + u32 lkey[4]; +}; + +typedef struct _RT_PMKID_LIST { + u8 bUsed; + u8 Bssid[6]; + u8 PMKID[16]; + u8 SsidBuf[33]; + u8 *ssid_octet; + u16 ssid_length; +} RT_PMKID_LIST, *PRT_PMKID_LIST; + +struct security_priv { + u32 dot11AuthAlgrthm; /* 802.11 auth, could be open, shared, 8021x and authswitch */ + u32 dot11PrivacyAlgrthm; /* This specify the privacy for shared auth. algorithm. */ + + /* WEP */ + u32 dot11PrivacyKeyIndex; /* this is only valid for legendary wep, 0~3 for key id. (tx key index) */ + union Keytype dot11DefKey[4]; /* this is only valid for def. key */ + u32 dot11DefKeylen[4]; + u8 dot11Def_camid[4]; + u8 key_mask; /* use to restore wep key after hal_init */ + + u32 dot118021XGrpPrivacy; /* This specify the privacy algthm. used for Grp key */ + u32 dot118021XGrpKeyid; /* key id used for Grp Key ( tx key index) */ + union Keytype dot118021XGrpKey[4]; /* 802.1x Group Key, for inx0 and inx1 */ + union Keytype dot118021XGrptxmickey[4]; + union Keytype dot118021XGrprxmickey[4]; + union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit. */ + union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv. */ + u8 iv_seq[4][8]; + /* extend security capabilities for AP_MODE */ + unsigned int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */ + unsigned int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */ + unsigned int wpa_group_cipher; + unsigned int wpa2_group_cipher; + unsigned int wpa_pairwise_cipher; + unsigned int wpa2_pairwise_cipher; + /*IEEE802.11-2012 Std. Table 8-101 AKM Suite Selectors*/ + u32 rsn_akm_suite_type; + + u8 wps_ie[MAX_WPS_IE_LEN];/* added in assoc req */ + int wps_ie_len; + + u8 binstallGrpkey; + u8 busetkipkey; + u8 bcheck_grpkey; + u8 bgrpkey_handshake; + + /* u8 packet_cnt; */ /* unused, removed */ + + s32 sw_encrypt;/* from registry_priv */ + s32 sw_decrypt;/* from registry_priv */ + + s32 hw_decrypted;/* if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. */ + + /* keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) */ + u32 ndisauthtype; /* NDIS_802_11_AUTHENTICATION_MODE */ + u32 ndisencryptstatus; /* NDIS_802_11_ENCRYPTION_STATUS */ + + NDIS_802_11_WEP ndiswep; + + u8 assoc_info[600]; + u8 szofcapability[256]; /* for wpa2 usage */ + u8 oidassociation[512]; /* for wpa/wpa2 usage */ + u8 authenticator_ie[256]; /* store ap security information element */ + u8 supplicant_ie[256]; /* store sta security information element */ + + /* for tkip countermeasure */ + u32 last_mic_err_time; + u8 btkip_countermeasure; + u8 btkip_wait_report; + u32 btkip_countermeasure_time; + + /* --------------------------------------------------------------------------- */ + /* For WPA2 Pre-Authentication. */ + /* --------------------------------------------------------------------------- */ + /* u8 RegEnablePreAuth; */ /* Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. */ + /* u8 EnablePreAuthentication; */ /* Current Value: Pre-Authentication enabled or not. */ + RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; /* Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. */ + u8 PMKIDIndex; + /* u32 PMKIDCount; */ /* Added by Annie, 2006-10-13. */ + /* u8 szCapability[256]; */ /* For WPA2-PSK using zero-config, by Annie, 2005-09-20. */ + + u8 bWepDefaultKeyIdxSet; +}; + +struct sha256_state { + u64 length; + u32 state[8], curlen; + u8 buf[64]; +}; + +#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\ + do {\ + switch (psecuritypriv->dot11AuthAlgrthm) {\ + case dot11AuthAlgrthm_Open:\ + case dot11AuthAlgrthm_Shared:\ + case dot11AuthAlgrthm_Auto:\ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ + break;\ + case dot11AuthAlgrthm_8021X:\ + if (bmcst)\ + encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\ + else\ + encry_algo = (u8) psta->dot118021XPrivacy;\ + break;\ + case dot11AuthAlgrthm_WAPI:\ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ + break;\ + } \ + } while (0) + +#define _AES_IV_LEN_ 8 + +#define SET_ICE_IV_LEN(iv_len, icv_len, encrypt)\ + do {\ + switch (encrypt) {\ + case _WEP40_:\ + case _WEP104_:\ + iv_len = 4;\ + icv_len = 4;\ + break;\ + case _TKIP_:\ + iv_len = 8;\ + icv_len = 4;\ + break;\ + case _AES_:\ + iv_len = 8;\ + icv_len = 8;\ + break;\ + case _SMS4_:\ + iv_len = 18;\ + icv_len = 16;\ + break;\ + default:\ + iv_len = 0;\ + icv_len = 0;\ + break;\ + } \ + } while (0) + +#define GET_TKIP_PN(iv, dot11txpn)\ + do {\ + dot11txpn._byte_.TSC0 = iv[2];\ + dot11txpn._byte_.TSC1 = iv[0];\ + dot11txpn._byte_.TSC2 = iv[4];\ + dot11txpn._byte_.TSC3 = iv[5];\ + dot11txpn._byte_.TSC4 = iv[6];\ + dot11txpn._byte_.TSC5 = iv[7];\ + } while (0) + +#define ROL32(A, n) (((A) << (n)) | (((A)>>(32-(n))) & ((1UL << (n)) - 1))) +#define ROR32(A, n) ROL32((A), 32-(n)) + +struct mic_data { + u32 K0, K1; /* Key */ + u32 L, R; /* Current state */ + u32 M; /* Message accumulator (single word) */ + u32 nBytesInM; /* # bytes in M */ +}; + +extern const u32 Te0[256]; +extern const u32 Te1[256]; +extern const u32 Te2[256]; +extern const u32 Te3[256]; +extern const u32 Te4[256]; +extern const u32 Td0[256]; +extern const u32 Td1[256]; +extern const u32 Td2[256]; +extern const u32 Td3[256]; +extern const u32 Td4[256]; +extern const u32 rcon[10]; +extern const u8 Td4s[256]; +extern const u8 rcons[10]; + +#define RCON(i) (rcons[(i)] << 24) + +static inline u32 rotr(u32 val, int bits) +{ + return (val >> bits) | (val << (32 - bits)); +} + +#define TE0(i) Te0[((i) >> 24) & 0xff] +#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) +#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) +#define TE3(i) rotr(Te0[(i) & 0xff], 24) +#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000) +#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000) +#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00) +#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff) +#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000) +#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000) +#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00) +#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff) +#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff) + +#define TD0(i) Td0[((i) >> 24) & 0xff] +#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) +#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) +#define TD3(i) rotr(Td0[(i) & 0xff], 24) +#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24) +#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16) +#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8) +#define TD44(i) (Td4s[(i) & 0xff]) +#define TD0_(i) Td0[(i) & 0xff] +#define TD1_(i) rotr(Td0[(i) & 0xff], 8) +#define TD2_(i) rotr(Td0[(i) & 0xff], 16) +#define TD3_(i) rotr(Td0[(i) & 0xff], 24) + +#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \ + ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) + +#define PUTU32(ct, st) { \ + (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \ + (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } + +#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ + (((u32) (a)[2]) << 8) | ((u32) (a)[3])) + +#define WPA_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define WPA_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define WPA_PUT_BE64(a, val) \ + do { \ + (a)[0] = (u8) (((u64) (val)) >> 56); \ + (a)[1] = (u8) (((u64) (val)) >> 48); \ + (a)[2] = (u8) (((u64) (val)) >> 40); \ + (a)[3] = (u8) (((u64) (val)) >> 32); \ + (a)[4] = (u8) (((u64) (val)) >> 24); \ + (a)[5] = (u8) (((u64) (val)) >> 16); \ + (a)[6] = (u8) (((u64) (val)) >> 8); \ + (a)[7] = (u8) (((u64) (val)) & 0xff); \ + } while (0) + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +/* the K array */ +static const unsigned long K[64] = { + 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, + 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, + 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, + 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, + 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, + 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, + 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, + 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, + 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, + 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, + 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, + 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, + 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL +}; + +/* Various logical functions */ +#define RORc(x, y) \ + (((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ + ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) +#define Ch(x, y, z) (z ^ (x & (y ^ z))) +#define Maj(x, y, z) (((x | y) & z) | (x & y)) +#define S(x, n) RORc((x), (n)) +#define R(x, n) (((x) & 0xFFFFFFFFUL)>>(n)) +#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) +#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) +#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) +#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) +#ifndef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif +void rtw_secmicsetkey(struct mic_data *pmicdata, u8 *key); +void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b); +void rtw_secmicappend(struct mic_data *pmicdata, u8 *src, u32 nBytes); +void rtw_secgetmic(struct mic_data *pmicdata, u8 *dst); + +void rtw_seccalctkipmic( + u8 *key, + u8 *header, + u8 *data, + u32 data_len, + u8 *Miccode, + u8 priority); + +u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe); +u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe); +void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe); + +u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); +u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); +void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); + +void rtw_sec_restore_wep_key(_adapter *adapter); +u8 rtw_handle_tkip_countermeasure(_adapter *adapter, const char *caller); + + +#endif /* __RTL871X_SECURITY_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_sreset.h b/drivers/staging/rtl8821ce/include/rtw_sreset.h new file mode 100644 index 000000000000..2940cb3a47ca --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_sreset.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_SRESET_H_ +#define _RTW_SRESET_H_ + +/* #include <drv_types.h> */ + +enum { + SRESET_TGP_NULL = 0, + SRESET_TGP_XMIT_STATUS = 1, + SRESET_TGP_LINK_STATUS = 2, +}; + +struct sreset_priv { + _mutex silentreset_mutex; + u8 silent_reset_inprogress; + u8 Wifi_Error_Status; + unsigned long last_tx_time; + unsigned long last_tx_complete_time; + + s32 dbg_trigger_point; +}; + +#define WIFI_STATUS_SUCCESS 0 +#define USB_VEN_REQ_CMD_FAIL BIT0 +#define USB_READ_PORT_FAIL BIT1 +#define USB_WRITE_PORT_FAIL BIT2 +#define WIFI_MAC_TXDMA_ERROR BIT3 +#define WIFI_TX_HANG BIT4 +#define WIFI_RX_HANG BIT5 +#define WIFI_IF_NOT_EXIST BIT6 + +void sreset_init_value(_adapter *padapter); +void sreset_reset_value(_adapter *padapter); +u8 sreset_get_wifi_status(_adapter *padapter); +void sreset_set_wifi_error_status(_adapter *padapter, u32 status); +void sreset_set_trigger_point(_adapter *padapter, s32 tgp); +bool sreset_inprogress(_adapter *padapter); +void sreset_reset(_adapter *padapter); + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_tdls.h b/drivers/staging/rtl8821ce/include/rtw_tdls.h new file mode 100644 index 000000000000..b8664cc43a1a --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_tdls.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_TDLS_H_ +#define __RTW_TDLS_H_ + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_version.h b/drivers/staging/rtl8821ce/include/rtw_version.h new file mode 100644 index 000000000000..c92820fe29bd --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_version.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#define DRIVERVERSION "v5.2.5.2.1_xxxx.20181112_beta" +#define BTCOEXVERSION "COEX20170310-1212" diff --git a/drivers/staging/rtl8821ce/include/rtw_vht.h b/drivers/staging/rtl8821ce/include/rtw_vht.h new file mode 100644 index 000000000000..09bb1fce44f0 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_vht.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_VHT_H_ +#define _RTW_VHT_H_ + +#define LDPC_VHT_ENABLE_RX BIT0 +#define LDPC_VHT_ENABLE_TX BIT1 +#define LDPC_VHT_TEST_TX_ENABLE BIT2 +#define LDPC_VHT_CAP_TX BIT3 + +#define STBC_VHT_ENABLE_RX BIT0 +#define STBC_VHT_ENABLE_TX BIT1 +#define STBC_VHT_TEST_TX_ENABLE BIT2 +#define STBC_VHT_CAP_TX BIT3 + +#define BEAMFORMING_VHT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */ +#define BEAMFORMING_VHT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */ +#define BEAMFORMING_VHT_MU_MIMO_AP_ENABLE BIT2 /*Declare our NIC support MU-MIMO AP mode*/ +#define BEAMFORMING_VHT_MU_MIMO_STA_ENABLE BIT3 /*Declare our NIC support MU-MIMO STA mode*/ +#define BEAMFORMING_VHT_BEAMFORMER_TEST BIT4 /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_VHT_BEAMFORMER_STS_CAP (BIT8 | BIT9 | BIT10) /*Asoc rsp cap*/ +#define BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM (BIT12 | BIT13 | BIT14) /*Asoc rsp cap*/ + +/* VHT capability info */ +#define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) +#define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) +#define SET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 1, _val) +#define SET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 1, _val) +#define SET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val) +#define SET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val) +#define SET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 0, 3, _val) +#define SET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 3, 1, _val) +#define SET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 4, 1, _val) +#define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val) +#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val) + +#define SET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 3, 1, _val) +#define SET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 4, 1, _val) +#define SET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 5, 1, _val) +#define SET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 1, _val) +#define SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+2, 7, 3, _val) /* B23~B25 */ +#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 2, 2, _val) +#define SET_VHT_CAPABILITY_ELE_MCS_RX_MAP(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+4, 0, 16, _val) /* B0~B15 indicate Rx MCS MAP, we write 0 to indicate MCS0~7. by page */ +#define SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+6, 0, 13, _val) +#define SET_VHT_CAPABILITY_ELE_MCS_TX_MAP(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+8, 0, 16, _val) /* B0~B15 indicate Tx MCS MAP, we write 0 to indicate MCS0~7. by page */ +#define SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+10, 0, 13, _val) + +#define GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 2) +#define GET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 2, 2) +#define GET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 4, 1) +#define GET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 5, 1) +#define GET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 6, 1) +#define GET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1) +#define GET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 3) +#define GET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 3, 1) +#define GET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 4, 1) +/*phydm-beamforming*/ +#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+1, 5, 3) +#define GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+2, 0, 3) +#define GET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 3, 1) +#define GET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 4, 1) +#define GET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 5, 1) +#define GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+2, 7, 3) +#define GET_VHT_CAPABILITY_ELE_RX_MCS(_pEleStart) ((_pEleStart)+4) +#define GET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+6, 0, 13) +#define GET_VHT_CAPABILITY_ELE_TX_MCS(_pEleStart) ((_pEleStart)+8) +#define GET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+10, 0, 13) + +/* VHT Operation Information Element */ +#define SET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 8, _val) +#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart+1, 0, 8, _val) +#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart+2, 0, 8, _val) +#define SET_VHT_OPERATION_ELE_BASIC_MCS_SET(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+3, 0, 16, _val) + +#define GET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 8) +#define GET_VHT_OPERATION_ELE_CENTER_FREQ1(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 8) +#define GET_VHT_OPERATION_ELE_CENTER_FREQ2(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 0, 8) + +/* VHT Operating Mode */ +#define SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) +#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 3, _val) +#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val) +#define GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 2) +#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 4, 3) +#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1) + +#define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val) +#define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1) + +struct vht_priv { + u8 vht_option; + + u8 ldpc_cap; + u8 stbc_cap; + u16 beamform_cap; + + u8 sgi_80m;/* short GI */ + u8 ampdu_len; + + u8 vht_op_mode_notify; + u8 vht_highest_rate; + u8 vht_mcs_map[2]; + + u8 vht_cap[32]; +}; + +u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map); +u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate); +u64 rtw_vht_mcs_map_to_bitmap(u8 *mcs_map, u8 nss); +void rtw_vht_use_default_setting(_adapter *padapter); +u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel); +u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw); +u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf); +void update_sta_vht_info_apmode(_adapter *padapter, PVOID psta); +void update_hw_vht_param(_adapter *padapter); +void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta); +u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); +void VHTOnAssocRsp(_adapter *padapter); +u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map); +void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map); + +#endif /* _RTW_VHT_H_ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_wapi.h b/drivers/staging/rtl8821ce/include/rtw_wapi.h new file mode 100644 index 000000000000..3e2950981710 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_wapi.h @@ -0,0 +1,212 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_WAPI_H +#define __INC_WAPI_H + +#define CONFIG_WAPI_SW_SMS4 +#define WAPI_DEBUG + +#define SMS4_MIC_LEN 16 +#define WAPI_EXT_LEN 18 +#define MAX_WAPI_IE_LEN 256 +#define sMacHdrLng 24 /* octets in data header, no WEP */ + +#ifdef WAPI_DEBUG + +/* WAPI trace debug */ +extern u32 wapi_debug_component; + +static inline void dump_buf(u8 *buf, u32 len) +{ + u32 i; + printk("-----------------Len %d----------------\n", len); + for (i = 0; i < len; i++) + printk("%2.2x-", *(buf + i)); + printk("\n"); +} + +#define WAPI_TRACE(component, x, args...) \ + do { if (wapi_debug_component & (component)) \ + printk(KERN_DEBUG "WAPI" ":" x "" , \ + ##args);\ + } while (0); + +#define WAPI_DATA(component, x, buf, len) \ + do { if (wapi_debug_component & (component)) { \ + printk("%s:\n", x);\ + dump_buf((buf), (len)); } \ + } while (0); + +#define RT_ASSERT_RET(_Exp) \ + if (!(_Exp)) { \ + printk("RTWLAN: "); \ + printk("Assertion failed! %s,%s, line=%d\n", \ + #_Exp, __FUNCTION__, __LINE__); \ + return; \ + } +#define RT_ASSERT_RET_VALUE(_Exp, Ret) \ + if (!(_Exp)) { \ + printk("RTWLAN: "); \ + printk("Assertion failed! %s,%s, line=%d\n", \ + #_Exp, __FUNCTION__, __LINE__); \ + return Ret; \ + } + +#else +#define RT_ASSERT_RET(_Exp) do {} while (0) +#define RT_ASSERT_RET_VALUE(_Exp, Ret) do {} while (0) +#define WAPI_TRACE(component, x, args...) do {} while (0) +#define WAPI_DATA(component, x, buf, len) do {} while (0) +#endif + +enum WAPI_DEBUG { + WAPI_INIT = 1, + WAPI_API = 1 << 1, + WAPI_TX = 1 << 2, + WAPI_RX = 1 << 3, + WAPI_MLME = 1 << 4, + WAPI_IOCTL = 1 << 5, + WAPI_ERR = 1 << 31 +}; + +#define WAPI_MAX_BKID_NUM 4 +#define WAPI_MAX_STAINFO_NUM 4 +#define WAPI_CAM_ENTRY_NUM 14 /* 28/2 = 14 */ + +typedef struct _RT_WAPI_BKID { + struct list_head list; + u8 bkid[16]; +} RT_WAPI_BKID, *PRT_WAPI_BKID; + +typedef struct _RT_WAPI_KEY { + u8 dataKey[16]; + u8 micKey[16]; + u8 keyId; + bool bSet; + bool bTxEnable; +} RT_WAPI_KEY, *PRT_WAPI_KEY; + +typedef enum _RT_WAPI_PACKET_TYPE { + WAPI_NONE = 0, + WAPI_PREAUTHENTICATE = 1, + WAPI_STAKEY_REQUEST = 2, + WAPI_AUTHENTICATE_ACTIVE = 3, + WAPI_ACCESS_AUTHENTICATE_REQUEST = 4, + WAPI_ACCESS_AUTHENTICATE_RESPONSE = 5, + WAPI_CERTIFICATE_AUTHENTICATE_REQUEST = 6, + WAPI_CERTIFICATE_AUTHENTICATE_RESPONSE = 7, + WAPI_USK_REQUEST = 8, + WAPI_USK_RESPONSE = 9, + WAPI_USK_CONFIRM = 10, + WAPI_MSK_NOTIFICATION = 11, + WAPI_MSK_RESPONSE = 12 +} RT_WAPI_PACKET_TYPE; + +typedef struct _RT_WAPI_STA_INFO { + struct list_head list; + u8 PeerMacAddr[6]; + RT_WAPI_KEY wapiUsk; + RT_WAPI_KEY wapiUskUpdate; + RT_WAPI_KEY wapiMsk; + RT_WAPI_KEY wapiMskUpdate; + u8 lastRxUnicastPN[16]; + u8 lastTxUnicastPN[16]; + u8 lastRxMulticastPN[16]; + u8 lastRxUnicastPNBEQueue[16]; + u8 lastRxUnicastPNBKQueue[16]; + u8 lastRxUnicastPNVIQueue[16]; + u8 lastRxUnicastPNVOQueue[16]; + bool bSetkeyOk; + bool bAuthenticateInProgress; + bool bAuthenticatorInUpdata; +} RT_WAPI_STA_INFO, *PRT_WAPI_STA_INFO; + +/* Added for HW wapi en/decryption */ +typedef struct _RT_WAPI_CAM_ENTRY { + /* RT_LIST_ENTRY list; */ + u8 IsUsed; + u8 entry_idx;/* for cam entry */ + u8 keyidx; /* 0 or 1,new or old key */ + u8 PeerMacAddr[6]; + u8 type; /* should be 110,wapi */ +} RT_WAPI_CAM_ENTRY, *PRT_WAPI_CAM_ENTRY; + +typedef struct _RT_WAPI_T { + /* BKID */ + RT_WAPI_BKID wapiBKID[WAPI_MAX_BKID_NUM]; + struct list_head wapiBKIDIdleList; + struct list_head wapiBKIDStoreList; + /* Key for Tx Multicast/Broadcast */ + RT_WAPI_KEY wapiTxMsk; + + /* sec related */ + u8 lastTxMulticastPN[16]; + /* STA list */ + RT_WAPI_STA_INFO wapiSta[WAPI_MAX_STAINFO_NUM]; + struct list_head wapiSTAIdleList; + struct list_head wapiSTAUsedList; + /* */ + bool bWapiEnable; + + /* store WAPI IE */ + u8 wapiIE[256]; + u8 wapiIELength; + bool bWapiPSK; + /* last sequece number for wai packet */ + u16 wapiSeqnumAndFragNum; + int extra_prefix_len; + int extra_postfix_len; + + RT_WAPI_CAM_ENTRY wapiCamEntry[WAPI_CAM_ENTRY_NUM]; +} RT_WAPI_T, *PRT_WAPI_T; + +typedef struct _WLAN_HEADER_WAPI_EXTENSION { + u8 KeyIdx; + u8 Reserved; + u8 PN[16]; +} WLAN_HEADER_WAPI_EXTENSION, *PWLAN_HEADER_WAPI_EXTENSION; + +u32 WapiComparePN(u8 *PN1, u8 *PN2); + +void rtw_wapi_init(_adapter *padapter); + +void rtw_wapi_free(_adapter *padapter); + +void rtw_wapi_disable_tx(_adapter *padapter); + +u8 rtw_wapi_is_wai_packet(_adapter *padapter, u8 *pkt_data); + +void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame); + +u8 rtw_wapi_check_for_drop(_adapter *padapter, union recv_frame *precv_frame); + +void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib); + +void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib); + +void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib); + +void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); + +void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr); + +void rtw_wapi_return_all_sta_info(_adapter *padapter); + +void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr); + +void rtw_wapi_clear_all_cam_entry(_adapter *padapter); + +void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey); + +int rtw_wapi_create_event_send(_adapter *padapter, u8 EventId, u8 *MacAddr, u8 *Buff, u16 BufLen); + +u32 rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe); + +u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe); + +void rtw_wapi_get_iv(_adapter *padapter, u8 *pRA, u8 *IV); + +u8 WapiIncreasePN(u8 *PN, u8 AddCount); + +bool rtw_wapi_drop_for_key_absent(_adapter *padapter, u8 *pRA); + +#endif diff --git a/drivers/staging/rtl8821ce/include/rtw_wifi_regd.h b/drivers/staging/rtl8821ce/include/rtw_wifi_regd.h new file mode 100644 index 000000000000..541a211f9511 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_wifi_regd.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2009-2010 Realtek Corporation. + * + *****************************************************************************/ + +#ifndef __RTW_WIFI_REGD_H__ +#define __RTW_WIFI_REGD_H__ + +struct country_code_to_enum_rd { + u16 countrycode; + const char *iso_name; +}; + +enum country_code_type_t { + COUNTRY_CODE_USER = 0, + + /*add new channel plan above this line */ + COUNTRY_CODE_MAX +}; + +int rtw_regd_init(_adapter *padapter); +void rtw_reg_notify_by_driver(_adapter *adapter); + +#endif /* __RTW_WIFI_REGD_H__ */ diff --git a/drivers/staging/rtl8821ce/include/rtw_xmit.h b/drivers/staging/rtl8821ce/include/rtw_xmit.h new file mode 100644 index 000000000000..a1609e305ca8 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/rtw_xmit.h @@ -0,0 +1,547 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_XMIT_H_ +#define _RTW_XMIT_H_ + + #define MAX_XMITBUF_SZ (1664) + #define NR_XMITBUFF (128) + + #define XMITBUF_ALIGN_SZ 4 + +/* xmit extension buff defination */ +#define MAX_XMIT_EXTBUF_SZ (1536) + +#ifdef CONFIG_SINGLE_XMIT_BUF + #define NR_XMIT_EXTBUFF (1) +#else + #define NR_XMIT_EXTBUFF (32) +#endif + +#define MAX_CMDBUF_SZ (5120) /* (4096) */ + +#define MAX_NUMBLKS (1) + +#define XMIT_VO_QUEUE (0) +#define XMIT_VI_QUEUE (1) +#define XMIT_BE_QUEUE (2) +#define XMIT_BK_QUEUE (3) + +#define VO_QUEUE_INX 0 +#define VI_QUEUE_INX 1 +#define BE_QUEUE_INX 2 +#define BK_QUEUE_INX 3 +#define BCN_QUEUE_INX 4 +#define MGT_QUEUE_INX 5 +#define HIGH_QUEUE_INX 6 +#define TXCMD_QUEUE_INX 7 + +#define HW_QUEUE_ENTRY 8 + + #define TX_BD_NUM (128+1) /* +1 result from ring buffer */ + +#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ + do {\ + pattrib_iv[0] = dot11txpn._byte_.TSC0;\ + pattrib_iv[1] = dot11txpn._byte_.TSC1;\ + pattrib_iv[2] = dot11txpn._byte_.TSC2;\ + pattrib_iv[3] = ((keyidx & 0x3)<<6);\ + dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val+1);\ + } while (0) + +#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ + do {\ + pattrib_iv[0] = dot11txpn._byte_.TSC1;\ + pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ + pattrib_iv[2] = dot11txpn._byte_.TSC0;\ + pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ + pattrib_iv[4] = dot11txpn._byte_.TSC2;\ + pattrib_iv[5] = dot11txpn._byte_.TSC3;\ + pattrib_iv[6] = dot11txpn._byte_.TSC4;\ + pattrib_iv[7] = dot11txpn._byte_.TSC5;\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ + } while (0) + +#define AES_IV(pattrib_iv, dot11txpn, keyidx)\ + do {\ + pattrib_iv[0] = dot11txpn._byte_.TSC0;\ + pattrib_iv[1] = dot11txpn._byte_.TSC1;\ + pattrib_iv[2] = 0;\ + pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ + pattrib_iv[4] = dot11txpn._byte_.TSC2;\ + pattrib_iv[5] = dot11txpn._byte_.TSC3;\ + pattrib_iv[6] = dot11txpn._byte_.TSC4;\ + pattrib_iv[7] = dot11txpn._byte_.TSC5;\ + dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val+1);\ + } while (0) + +/* Check if AMPDU Tx is supported or not. If it is supported, +* it need to check "amsdu in ampdu" is supported or not. +* (ampdu_en, amsdu_ampdu_en) = +* (0, x) : AMPDU is not enable, but AMSDU is valid to send. +* (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send. +* (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send. +*/ +#define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\ + ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) + +#define IS_AMSDU_AMPDU_VALID(pattrib)\ + !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE)) + +#define HWXMIT_ENTRY 4 + +/* For Buffer Descriptor ring architecture */ + #define TX_BUFFER_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */ + +#define TXDESC_SIZE 48 /* HALMAC_TX_DESC_SIZE_8821C */ + + + /* this section is defined for buffer descriptor ring architecture */ + #define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */ + /* tx desc and payload are in the same buf */ + #define TXDESC_OFFSET (TX_WIFI_INFO_SIZE) + +enum TXDESC_SC { + SC_DONT_CARE = 0x00, + SC_UPPER = 0x01, + SC_LOWER = 0x02, + SC_DUPLICATE = 0x03 +}; + + +struct tx_buf_desc { +#define TX_BUFFER_SEG_SIZE 2 /* in unit of DWORD */ + unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)]; +} __packed; + + +#define PCI_MAX_TX_QUEUE_COUNT 8 /* == HW_QUEUE_ENTRY */ + +struct rtw_tx_ring { + unsigned char qid; + struct tx_buf_desc *buf_desc; + dma_addr_t dma; + unsigned int idx; + unsigned int entries; + _queue queue; + u32 qlen; + u16 hw_rp_cache; +}; + +struct hw_xmit { + /* _lock xmit_lock; */ + /* _list pending; */ + _queue *sta_queue; + /* struct hw_txqueue *phwtxqueue; */ + /* sint txcmdcnt; */ + int accnt; +}; + +/* reduce size */ +struct pkt_attrib { + u8 type; + u8 subtype; + u8 bswenc; + u8 dhcp_pkt; + u16 ether_type; + u16 seqnum; + u8 hw_ssn_sel; /* for HW_SEQ0,1,2,3 */ + u16 pkt_hdrlen; /* the original 802.3 pkt header len */ + u16 hdrlen; /* the WLAN Header Len */ + u32 pktlen; /* the original 802.3 pkt raw_data len (not include ether_hdr data) */ + u32 last_txcmdsz; + u8 nr_frags; + u8 encrypt; /* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */ + u8 iv_len; + u8 icv_len; + u8 iv[18]; + u8 icv[16]; + u8 priority; + u8 ack_policy; + u8 mac_id; + u8 vcs_mode; /* virtual carrier sense method */ + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + u8 key_idx; + u8 qos_en; + u8 ht_en; + u8 raid;/* rate adpative id */ + u8 bwmode; + u8 ch_offset;/* PRIME_CHNL_OFFSET */ + u8 sgi;/* short GI */ + u8 ampdu_en;/* tx ampdu enable */ + u8 ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */ + u8 amsdu; + u8 amsdu_ampdu_en;/* tx amsdu in ampdu enable */ + u8 mdata;/* more data bit */ + u8 pctrl;/* per packet txdesc control enable */ + u8 triggered;/* for ap mode handling Power Saving sta */ + u8 qsel; + u8 order;/* order bit */ + u8 eosp; + u8 rate; + u8 intel_proxim; + u8 retry_ctrl; + u8 mbssid; + u8 ldpc; + u8 stbc; + struct sta_info *psta; + + u8 rtsen; + u8 cts2self; + union Keytype dot11tkiptxmickey; + /* union Keytype dot11tkiprxmickey; */ + union Keytype dot118021x_UncstKey; + + u8 key_type; + + u8 icmp_pkt; + + +}; + + +#define WLANHDR_OFFSET 64 + +#define NULL_FRAMETAG (0x0) +#define DATA_FRAMETAG 0x01 +#define L2_FRAMETAG 0x02 +#define MGNT_FRAMETAG 0x03 +#define AMSDU_FRAMETAG 0x04 + +#define EII_FRAMETAG 0x05 +#define IEEE8023_FRAMETAG 0x06 + +#define MP_FRAMETAG 0x07 + +#define TXAGG_FRAMETAG 0x08 + +enum { + XMITBUF_DATA = 0, + XMITBUF_MGNT = 1, + XMITBUF_CMD = 2, +}; + +bool rtw_xmit_ac_blocked(_adapter *adapter); + +struct submit_ctx { + u32 submit_time; /* */ + u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ + int status; /* status for operation */ + struct completion done; +}; + +enum { + RTW_SCTX_SUBMITTED = -1, + RTW_SCTX_DONE_SUCCESS = 0, + RTW_SCTX_DONE_UNKNOWN, + RTW_SCTX_DONE_TIMEOUT, + RTW_SCTX_DONE_BUF_ALLOC, + RTW_SCTX_DONE_BUF_FREE, + RTW_SCTX_DONE_WRITE_PORT_ERR, + RTW_SCTX_DONE_TX_DESC_NA, + RTW_SCTX_DONE_TX_DENY, + RTW_SCTX_DONE_CCX_PKT_FAIL, + RTW_SCTX_DONE_DRV_STOP, + RTW_SCTX_DONE_DEV_REMOVE, + RTW_SCTX_DONE_CMD_ERROR, + RTW_SCTX_DONE_CMD_DROP, + RTX_SCTX_CSTR_WAIT_RPT2, +}; + +void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms); +int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg); +void rtw_sctx_done_err(struct submit_ctx **sctx, int status); +void rtw_sctx_done(struct submit_ctx **sctx); + +struct xmit_buf { + _list list; + + _adapter *padapter; + + u8 *pallocated_buf; + + u8 *pbuf; + + void *priv_data; + + u16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */ + u16 flags; + u32 alloc_sz; + + u32 len; + + struct submit_ctx *sctx; + + /*struct tx_buf_desc *buf_desc;*/ + + +}; + +struct xmit_frame { + _list list; + + struct pkt_attrib attrib; + + _pkt *pkt; + + int frame_tag; + + _adapter *padapter; + + u8 *buf_addr; + + struct xmit_buf *pxmitbuf; + + u8 ack_report; + + u8 *alloc_addr; /* the actual address this xmitframe allocated */ + u8 ext_tag; /* 0:data, 1:mgmt */ + +}; + +struct tx_servq { + _list tx_pending; + _queue sta_pending; + int qcnt; +}; + +struct sta_xmit_priv { + _lock lock; + sint option; + sint apsd_setting; /* When bit mask is on, the associated edca queue supports APSD. */ + + /* struct tx_servq blk_q[MAX_NUMBLKS]; */ + struct tx_servq be_q; /* priority == 0,3 */ + struct tx_servq bk_q; /* priority == 1,2 */ + struct tx_servq vi_q; /* priority == 4,5 */ + struct tx_servq vo_q; /* priority == 6,7 */ + _list legacy_dz; + _list apsd; + + u16 txseq_tid[16]; + + /* uint sta_tx_bytes; */ + /* u64 sta_tx_pkts; */ + /* uint sta_tx_fail; */ + +}; + +struct hw_txqueue { + volatile sint head; + volatile sint tail; + volatile sint free_sz; /* in units of 64 bytes */ + volatile sint free_cmdsz; + volatile sint txsz[8]; + uint ff_hwaddr; + uint cmd_hwaddr; + sint ac_tag; +}; + +struct agg_pkt_info { + u16 offset; + u16 pkt_len; +}; + +enum cmdbuf_type { + CMDBUF_BEACON = 0x00, + CMDBUF_RSVD, + CMDBUF_MAX +}; + +u8 rtw_get_hwseq_no(_adapter *padapter); + +struct xmit_priv { + + _lock lock; + + _sema xmit_sema; + /*_sema terminate_xmitthread_sema;*/ + _completion xmitthread_comp; + + /* _queue blk_strms[MAX_NUMBLKS]; */ + _queue be_pending; + _queue bk_pending; + _queue vi_pending; + _queue vo_pending; + _queue bm_pending; + + /* _queue legacy_dz_queue; */ + /* _queue apsd_queue; */ + + u8 *pallocated_frame_buf; + u8 *pxmit_frame_buf; + uint free_xmitframe_cnt; + _queue free_xmit_queue; + + /* uint mapping_addr; */ + /* uint pkt_sz; */ + + u8 *xframe_ext_alloc_addr; + u8 *xframe_ext; + uint free_xframe_ext_cnt; + _queue free_xframe_ext_queue; + + /* struct hw_txqueue be_txqueue; */ + /* struct hw_txqueue bk_txqueue; */ + /* struct hw_txqueue vi_txqueue; */ + /* struct hw_txqueue vo_txqueue; */ + /* struct hw_txqueue bmc_txqueue; */ + + uint frag_len; + + _adapter *adapter; + + u8 vcs_setting; + u8 vcs; + u8 vcs_type; + /* u16 rts_thresh; */ + + u64 tx_bytes; + u64 tx_pkts; + u64 tx_drop; + u64 last_tx_pkts; + + struct hw_xmit *hwxmits; + u8 hwxmit_entry; + + u8 wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */ + + /* Tx */ + struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT]; + int txringcount[PCI_MAX_TX_QUEUE_COUNT]; + u8 beaconDMAing; /* flag of indicating beacon is transmiting to HW by DMA */ + struct tasklet_struct xmit_tasklet; + _queue free_xmitbuf_queue; + _queue pending_xmitbuf_queue; + u8 *pallocated_xmitbuf; + u8 *pxmitbuf; + uint free_xmitbuf_cnt; + + _queue free_xmit_extbuf_queue; + u8 *pallocated_xmit_extbuf; + u8 *pxmit_extbuf; + uint free_xmit_extbuf_cnt; + + struct xmit_buf pcmd_xmitbuf[CMDBUF_MAX]; + u8 hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */ + u16 nqos_ssn; + + int ack_tx; + _mutex ack_tx_mutex; + struct submit_ctx ack_tx_ops; + u8 seq_no; + + _lock lock_sctx; + + u8 stop_req; +}; + +extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type); +#define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD) +extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type); +#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON) + +extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + +extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + +void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); +extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); +extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); +extern s32 rtw_put_snap(u8 *data, u16 h_proto); + +extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); +struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv); +struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); +extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); +struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); +extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); + +extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); +extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); +#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) +extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); +s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag); +void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); + +s32 rtw_txframes_pending(_adapter *padapter); +s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib); +void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); + +s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); +void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv); + +void rtw_alloc_hwxmits(_adapter *padapter); +void rtw_free_hwxmits(_adapter *padapter); +s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); +s32 rtw_xmit(_adapter *padapter, _pkt **pkt); +bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); +sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); +void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); +void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); +void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); + +u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta); + +void rtw_get_adapter_tx_rate_bmp_by_bw(_adapter *adapter, u8 bw, u16 *r_bmp_cck_ofdm, u32 *r_bmp_ht, u32 *r_bmp_vht); +void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj); +u16 rtw_get_tx_rate_bmp_cck_ofdm(struct dvobj_priv *dvobj); +u32 rtw_get_tx_rate_bmp_ht_by_bw(struct dvobj_priv *dvobj, u8 bw); +u32 rtw_get_tx_rate_bmp_vht_by_bw(struct dvobj_priv *dvobj, u8 bw); +u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); +u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw); + +u8 query_ra_short_GI(struct sta_info *psta, u8 bw); + +u8 qos_acm(u8 acm_mask, u8 priority); + + + +u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); + +int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); +void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); + +enum XMIT_BLOCK_REASON { + XMIT_BLOCK_NONE = 0, + XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/ + XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/ + XMIT_BLOCK_MAX = 0xFF, +}; +void rtw_init_xmit_block(_adapter *padapter); +void rtw_deinit_xmit_block(_adapter *padapter); + +void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); +void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason); +bool rtw_is_xmit_blocked(_adapter *padapter); + +/* include after declaring struct xmit_buf, in order to avoid warning */ +#include <xmit_osdep.h> + +#endif /* _RTL871X_XMIT_H_ */ diff --git a/drivers/staging/rtl8821ce/include/sta_info.h b/drivers/staging/rtl8821ce/include/sta_info.h new file mode 100644 index 000000000000..8b96625693a0 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/sta_info.h @@ -0,0 +1,542 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __STA_INFO_H_ +#define __STA_INFO_H_ + +#define IBSS_START_MAC_ID 2 +#define NUM_STA MACID_NUM_SW_LIMIT + + + +#define NUM_ACL 16 +#define RTW_ACL_MODE_DISABLED 0 +#define RTW_ACL_MODE_ACCEPT_UNLESS_LISTED 1 +#define RTW_ACL_MODE_DENY_UNLESS_LISTED 2 +#define RTW_ACL_MODE_MAX 3 + +extern const char *const _acl_mode_str[]; +#define acl_mode_str(mode) (((mode) >= RTW_ACL_MODE_MAX) ? _acl_mode_str[RTW_ACL_MODE_DISABLED] : _acl_mode_str[(mode)]) + +#ifndef RTW_PRE_LINK_STA_NUM + #define RTW_PRE_LINK_STA_NUM 8 +#endif + +struct pre_link_sta_node_t { + u8 valid; + u8 addr[ETH_ALEN]; +}; + +struct pre_link_sta_ctl_t { + _lock lock; + u8 num; + struct pre_link_sta_node_t node[RTW_PRE_LINK_STA_NUM]; +}; + +enum sta_info_update_type { + STA_INFO_UPDATE_NONE = 0, + STA_INFO_UPDATE_BW = BIT(0), + STA_INFO_UPDATE_RATE = BIT(1), + STA_INFO_UPDATE_PROTECTION_MODE = BIT(2), + STA_INFO_UPDATE_CAP = BIT(3), + STA_INFO_UPDATE_HT_CAP = BIT(4), + STA_INFO_UPDATE_VHT_CAP = BIT(5), + STA_INFO_UPDATE_ALL = STA_INFO_UPDATE_BW + | STA_INFO_UPDATE_RATE + | STA_INFO_UPDATE_PROTECTION_MODE + | STA_INFO_UPDATE_CAP + | STA_INFO_UPDATE_HT_CAP + | STA_INFO_UPDATE_VHT_CAP, + STA_INFO_UPDATE_MAX +}; + +struct rtw_wlan_acl_node { + _list list; + u8 addr[ETH_ALEN]; + u8 valid; +}; + +struct wlan_acl_pool { + int mode; + int num; + struct rtw_wlan_acl_node aclnode[NUM_ACL]; + _queue acl_node_q; +}; + +typedef struct _RSSI_STA { + + s32 undecorated_smoothed_pwdb; + s32 undecorated_smoothed_cck; + s32 undecorated_smoothed_ofdm; + u8 ofdm_pkt; + u8 cck_pkt; + u16 cck_sum_power; + u8 is_send_rssi; + u64 packet_map; + u8 valid_bit; +} RSSI_STA, *PRSSI_STA; + +struct stainfo_stats { + + u64 rx_mgnt_pkts; + u64 rx_beacon_pkts; + u64 rx_probereq_pkts; + u64 rx_probersp_pkts; + u64 rx_probersp_bm_pkts; + u64 rx_probersp_uo_pkts; + u64 rx_ctrl_pkts; + u64 rx_data_pkts; + u64 rx_data_last_pkts; /* For Read & Clear requirement in proc_get_rx_stat() */ + u64 rx_data_qos_pkts[TID_NUM]; + u64 last_rx_mgnt_pkts; + u64 last_rx_beacon_pkts; + u64 last_rx_probereq_pkts; + u64 last_rx_probersp_pkts; + u64 last_rx_probersp_bm_pkts; + u64 last_rx_probersp_uo_pkts; + u64 last_rx_ctrl_pkts; + u64 last_rx_data_pkts; + u64 last_rx_data_qos_pkts[TID_NUM]; + u64 rx_bytes; + u64 rx_drops; + + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; + + u32 duplicate_cnt; /* Read & Clear, in proc_get_rx_stat() */ + u32 rxratecnt[128]; /* Read & Clear, in proc_get_rx_stat() */ + u32 tx_ok_cnt; /* Read & Clear, in proc_get_tx_stat() */ + u32 tx_fail_cnt; /* Read & Clear, in proc_get_tx_stat() */ + u32 tx_retry_cnt; /* Read & Clear, in proc_get_tx_stat() */ +}; + +#ifndef DBG_SESSION_TRACKER +#define DBG_SESSION_TRACKER 0 +#endif + +/* session tracker status */ +#define ST_STATUS_NONE 0 +#define ST_STATUS_CHECK BIT0 +#define ST_STATUS_ESTABLISH BIT1 +#define ST_STATUS_EXPIRE BIT2 + +#define ST_EXPIRE_MS (10 * 1000) + +struct session_tracker { + _list list; /* session_tracker_queue */ + u32 local_naddr; + u16 local_port; + u32 remote_naddr; + u16 remote_port; + u32 set_time; + u8 status; +}; + +/* session tracker cmd */ +#define ST_CMD_ADD 0 +#define ST_CMD_DEL 1 +#define ST_CMD_CHK 2 + +struct st_cmd_parm { + u8 cmd; + struct sta_info *sta; + u32 local_naddr; /* TODO: IPV6 */ + u16 local_port; + u32 remote_naddr; /* TODO: IPV6 */ + u16 remote_port; +}; + +typedef bool (*st_match_rule)(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); + +struct st_register { + u8 s_proto; + st_match_rule rule; +}; + +#define SESSION_TRACKER_REG_ID_WFD 0 +#define SESSION_TRACKER_REG_ID_NUM 1 + +struct st_ctl_t { + struct st_register reg[SESSION_TRACKER_REG_ID_NUM]; + _queue tracker_q; +}; + +void rtw_st_ctl_init(struct st_ctl_t *st_ctl); +void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl); +void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg); +void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id); +bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto); +bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl); + + +struct sta_info { + + _lock lock; + _list list; /* free_sta_queue */ + _list hash_list; /* sta_hash */ + /* _list asoc_list; */ /* 20061114 */ + /* _list sleep_list; */ /* sleep_q */ + /* _list wakeup_list; */ /* wakeup_q */ + _adapter *padapter; + + struct sta_xmit_priv sta_xmitpriv; + struct sta_recv_priv sta_recvpriv; + + _queue sleep_q; + unsigned int sleepq_len; + + uint state; + uint aid; + uint mac_id; + uint qos_option; + u8 hwaddr[ETH_ALEN]; + u16 hwseq; + u8 ra_rpt_linked; + + uint ieee8021x_blocked; /* 0: allowed, 1:blocked */ + uint dot118021XPrivacy; /* aes, tkip... */ + union Keytype dot11tkiptxmickey; + union Keytype dot11tkiprxmickey; + union Keytype dot118021x_UncstKey; + union pn48 dot11txpn; /* PN48 used for Unicast xmit */ + union pn48 dot11rxpn; /* PN48 used for Unicast recv. */ + + u8 bssrateset[16]; + u32 bssratelen; + s32 rssi; + s32 signal_quality; + + u8 cts2self; + u8 rtsen; + + u8 raid; + u8 init_rate; + u64 ra_mask; + u8 wireless_mode; /* NETWORK_TYPE */ + u8 bw_mode; + + u8 ldpc; + u8 stbc; + + + struct stainfo_stats sta_stats; + + /* for A-MPDU TX, ADDBA timeout check */ + _timer addba_retry_timer; + + /* for A-MPDU Rx reordering buffer control */ + struct recv_reorder_ctrl recvreorder_ctrl[TID_NUM]; + ATOMIC_T continual_no_rx_packet[TID_NUM]; + /* for A-MPDU Tx */ + /* unsigned char ampdu_txen_bitmap; */ + u16 BA_starting_seqctrl[16]; + + struct ht_priv htpriv; + + struct vht_priv vhtpriv; + + /* Notes: */ + /* STA_Mode: */ + /* curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO */ + /* scan_q: AP CAP/INFO */ + + /* AP_Mode: */ + /* curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO */ + /* sta_info: (AP & STA) CAP/INFO */ + + unsigned int expire_to; + + + _list asoc_list; + _list auth_list; + + unsigned int auth_seq; + unsigned int authalg; + unsigned char chg_txt[128]; + + u16 capability; + int flags; + + int dot8021xalg;/* 0:disable, 1:psk, 2:802.1x */ + int wpa_psk;/* 0:disable, bit(0): WPA, bit(1):WPA2 */ + int wpa_group_cipher; + int wpa2_group_cipher; + int wpa_pairwise_cipher; + int wpa2_pairwise_cipher; + + u8 bpairwise_key_installed; + + u8 wpa_ie[32]; + + u8 nonerp_set; + u8 no_short_slot_time_set; + u8 no_short_preamble_set; + u8 no_ht_gf_set; + u8 no_ht_set; + u8 ht_20mhz_set; + u8 ht_40mhz_intolerant; + + + u8 qos_info; + + u8 max_sp_len; + u8 uapsd_bk;/* BIT(0): Delivery enabled, BIT(1): Trigger enabled */ + u8 uapsd_be; + u8 uapsd_vi; + u8 uapsd_vo; + + u8 has_legacy_ac; + unsigned int sleepq_ac_len; + + /* p2p priv data */ + u8 is_p2p_device; + u8 p2p_status_code; + + /* p2p client info */ + u8 dev_addr[ETH_ALEN]; + /* u8 iface_addr[ETH_ALEN]; */ /* = hwaddr[ETH_ALEN] */ + u8 dev_cap; + u16 config_methods; + u8 primary_dev_type[8]; + u8 num_of_secdev_type; + u8 secdev_types_list[32];/* 32/8 == 4; */ + u16 dev_name_len; + u8 dev_name[32]; + + u8 op_wfd_mode; + + u8 under_exist_checking; + + u8 keep_alive_trycnt; + + + + + /* for DM */ + RSSI_STA rssi_stat; + + /* ODM_STA_INFO_T */ + /* ================ODM Relative Info======================= */ + /* Please be care, dont declare too much structure here. It will cost memory * STA support num. */ + /* */ + /* */ + /* 2011/10/20 MH Add for ODM STA info. */ + /* */ + /* Driver Write */ + u8 bValid; /* record the sta status link or not? */ + /* u8 WirelessMode; */ /* */ + u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ + /* ODM Write */ + /* 1 PHY_STATUS_INFO */ + u8 RSSI_Path[4]; /* */ + u8 RSSI_Ave; + u8 RXEVM[4]; + u8 RXSNR[4]; + + u8 rssi_level; /* for Refresh RA mask */ + /* ODM Write */ + /* 1 TX_INFO (may changed by IC) */ + /* TX_INFO_T pTxInfo; */ /* Define in IC folder. Move lower layer. */ + /* */ + /* ================ODM Relative Info======================= */ + /* */ + + /* To store the sequence number of received management frame */ + u16 RxMgmtFrameSeqNum; + + struct st_ctl_t st_ctl; + u8 max_agg_num_minimal_record; /*keep minimal tx desc max_agg_num setting*/ +}; + +#define sta_rx_pkts(sta) \ + (sta->sta_stats.rx_mgnt_pkts \ + + sta->sta_stats.rx_ctrl_pkts \ + + sta->sta_stats.rx_data_pkts) + +#define sta_last_rx_pkts(sta) \ + (sta->sta_stats.last_rx_mgnt_pkts \ + + sta->sta_stats.last_rx_ctrl_pkts \ + + sta->sta_stats.last_rx_data_pkts) + +#define sta_rx_data_pkts(sta) \ + (sta->sta_stats.rx_data_pkts) + +#define sta_rx_data_qos_pkts(sta, i) \ + (sta->sta_stats.rx_data_qos_pkts[i]) + +#define sta_last_rx_data_pkts(sta) \ + (sta->sta_stats.last_rx_data_pkts) + +#define sta_last_rx_data_qos_pkts(sta, i) \ + (sta->sta_stats.last_rx_data_qos_pkts[i]) + +#define sta_rx_mgnt_pkts(sta) \ + (sta->sta_stats.rx_mgnt_pkts) + +#define sta_last_rx_mgnt_pkts(sta) \ + (sta->sta_stats.last_rx_mgnt_pkts) + +#define sta_rx_beacon_pkts(sta) \ + (sta->sta_stats.rx_beacon_pkts) + +#define sta_last_rx_beacon_pkts(sta) \ + (sta->sta_stats.last_rx_beacon_pkts) + +#define sta_rx_probereq_pkts(sta) \ + (sta->sta_stats.rx_probereq_pkts) + +#define sta_last_rx_probereq_pkts(sta) \ + (sta->sta_stats.last_rx_probereq_pkts) + +#define sta_rx_probersp_pkts(sta) \ + (sta->sta_stats.rx_probersp_pkts) + +#define sta_last_rx_probersp_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_pkts) + +#define sta_rx_probersp_bm_pkts(sta) \ + (sta->sta_stats.rx_probersp_bm_pkts) + +#define sta_last_rx_probersp_bm_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_bm_pkts) + +#define sta_rx_probersp_uo_pkts(sta) \ + (sta->sta_stats.rx_probersp_uo_pkts) + +#define sta_last_rx_probersp_uo_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_uo_pkts) + +#define sta_update_last_rx_pkts(sta) \ + do { \ + sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ + sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \ + sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \ + sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \ + sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \ + sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \ + sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ + sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ + } while (0) + +#define STA_RX_PKTS_ARG(sta) \ + sta->sta_stats.rx_mgnt_pkts \ + , sta->sta_stats.rx_ctrl_pkts \ + , sta->sta_stats.rx_data_pkts + +#define STA_LAST_RX_PKTS_ARG(sta) \ + sta->sta_stats.last_rx_mgnt_pkts \ + , sta->sta_stats.last_rx_ctrl_pkts \ + , sta->sta_stats.last_rx_data_pkts + +#define STA_RX_PKTS_DIFF_ARG(sta) \ + sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \ + , sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \ + , sta->sta_stats.rx_data_pkts - sta->sta_stats.last_rx_data_pkts + +#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" + +#define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode +#define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode) + +struct sta_priv { + + u8 *pallocated_stainfo_buf; + u8 *pstainfo_buf; + _queue free_sta_queue; + + _lock sta_hash_lock; + _list sta_hash[NUM_STA]; + int asoc_sta_count; + _queue sleep_q; + _queue wakeup_q; + + _adapter *padapter; + + u32 adhoc_expire_to; + + _list asoc_list; + _list auth_list; + _lock asoc_list_lock; + _lock auth_list_lock; + u8 asoc_list_cnt; + u8 auth_list_cnt; + + unsigned int auth_to; /* sec, time to expire in authenticating. */ + unsigned int assoc_to; /* sec, time to expire before associating. */ + unsigned int expire_to; /* sec , time to expire after associated. */ + + /* pointers to STA info; based on allocated AID or NULL if AID free + * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 + * and so on + */ + struct sta_info *sta_aid[NUM_STA]; + + u16 sta_dz_bitmap;/* only support 15 stations, staion aid bitmap for sleeping sta. */ + u16 tim_bitmap;/* only support 15 stations, aid=0~15 mapping bit0~bit15 */ + + u16 max_num_sta; + + struct wlan_acl_pool acl_list; + + + + struct sta_info *c2h_sta; + struct submit_ctx *gotc2h; +}; + +__inline static u32 wifi_mac_hash(u8 *mac) +{ + u32 x; + + x = mac[0]; + x = (x << 2) ^ mac[1]; + x = (x << 2) ^ mac[2]; + x = (x << 2) ^ mac[3]; + x = (x << 2) ^ mac[4]; + x = (x << 2) ^ mac[5]; + + x ^= x >> 8; + x = x & (NUM_STA - 1); + + return x; +} + +extern u32 _rtw_init_sta_priv(struct sta_priv *pstapriv); +extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); + +#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0) +int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta); +struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset); + +extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); +extern void rtw_free_all_stainfo(_adapter *padapter); +extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); +extern u32 rtw_init_bcmc_stainfo(_adapter *padapter); +extern struct sta_info *rtw_get_bcmc_stainfo(_adapter *padapter); + +extern u8 rtw_access_ctrl(_adapter *adapter, u8 *mac_addr); +void dump_macaddr_acl(void *sel, _adapter *adapter); + +bool rtw_is_pre_link_sta(struct sta_priv *stapriv, u8 *addr); + +#endif /* _STA_INFO_H_ */ diff --git a/drivers/staging/rtl8821ce/include/wifi.h b/drivers/staging/rtl8821ce/include/wifi.h new file mode 100644 index 000000000000..f5afef4a7335 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/wifi.h @@ -0,0 +1,1193 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _WIFI_H_ +#define _WIFI_H_ + +#ifdef BIT +/* #error "BIT define occurred earlier elsewhere!\n" */ +#undef BIT +#endif +#define BIT(x) (1 << (x)) + +#define WLAN_ETHHDR_LEN 14 +#define WLAN_ETHADDR_LEN 6 +#define WLAN_IEEE_OUI_LEN 3 +#define WLAN_ADDR_LEN 6 +#define WLAN_CRC_LEN 4 +#define WLAN_BSSID_LEN 6 +#define WLAN_BSS_TS_LEN 8 +#define WLAN_HDR_A3_LEN 24 +#define WLAN_HDR_A4_LEN 30 +#define WLAN_HDR_A3_QOS_LEN 26 +#define WLAN_HDR_A4_QOS_LEN 32 +#define WLAN_SSID_MAXLEN 32 +#define WLAN_DATA_MAXLEN 2312 + +#define WLAN_A3_PN_OFFSET 24 +#define WLAN_A4_PN_OFFSET 30 + +#define WLAN_MIN_ETHFRM_LEN 60 +#define WLAN_MAX_ETHFRM_LEN 1514 +#define WLAN_ETHHDR_LEN 14 +#define WLAN_WMM_LEN 24 + +#define P80211CAPTURE_VERSION 0x80211001 + +/* This value is tested by WiFi 11n Test Plan 5.2.3. + * This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. */ +#define WiFiNavUpperUs 30000 /* 30 ms */ + +#ifdef GREEN_HILL +#pragma pack(1) +#endif + +enum WIFI_FRAME_TYPE { + WIFI_MGT_TYPE = (0), + WIFI_CTRL_TYPE = (BIT(2)), + WIFI_DATA_TYPE = (BIT(3)), + WIFI_QOS_DATA_TYPE = (BIT(7) | BIT(3)), /* !< QoS Data */ +}; + +enum WIFI_FRAME_SUBTYPE { + + /* below is for mgt frame */ + WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE), + WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), + WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), + WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), + WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), + WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), + WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), + WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), + WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), + WIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE), + + /* below is for control frame */ + WIFI_BF_REPORT_POLL = (BIT(6) | WIFI_CTRL_TYPE), + WIFI_NDPA = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), + WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), + + /* below is for data frame */ + WIFI_DATA = (0 | WIFI_DATA_TYPE), + WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), + WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), + WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), + WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), + WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), +}; + +enum WIFI_REASON_CODE { + _RSON_RESERVED_ = 0, + _RSON_UNSPECIFIED_ = 1, + _RSON_AUTH_NO_LONGER_VALID_ = 2, + _RSON_DEAUTH_STA_LEAVING_ = 3, + _RSON_INACTIVITY_ = 4, + _RSON_UNABLE_HANDLE_ = 5, + _RSON_CLS2_ = 6, + _RSON_CLS3_ = 7, + _RSON_DISAOC_STA_LEAVING_ = 8, + _RSON_ASOC_NOT_AUTH_ = 9, + + /* WPA reason */ + _RSON_INVALID_IE_ = 13, + _RSON_MIC_FAILURE_ = 14, + _RSON_4WAY_HNDSHK_TIMEOUT_ = 15, + _RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16, + _RSON_DIFF_IE_ = 17, + _RSON_MLTCST_CIPHER_NOT_VALID_ = 18, + _RSON_UNICST_CIPHER_NOT_VALID_ = 19, + _RSON_AKMP_NOT_VALID_ = 20, + _RSON_UNSUPPORT_RSNE_VER_ = 21, + _RSON_INVALID_RSNE_CAP_ = 22, + _RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23, + + /* belowing are Realtek definition */ + _RSON_PMK_NOT_AVAILABLE_ = 24, + _RSON_TDLS_TEAR_TOOFAR_ = 25, + _RSON_TDLS_TEAR_UN_RSN_ = 26, +}; + +/* IEEE 802.11h */ +#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10 +#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11 + +enum WIFI_STATUS_CODE { + _STATS_SUCCESSFUL_ = 0, + _STATS_FAILURE_ = 1, + _STATS_SEC_DISABLED_ = 5, + _STATS_NOT_IN_SAME_BSS_ = 7, + _STATS_CAP_FAIL_ = 10, + _STATS_NO_ASOC_ = 11, + _STATS_OTHER_ = 12, + _STATS_NO_SUPP_ALG_ = 13, + _STATS_OUT_OF_AUTH_SEQ_ = 14, + _STATS_CHALLENGE_FAIL_ = 15, + _STATS_AUTH_TIMEOUT_ = 16, + _STATS_UNABLE_HANDLE_STA_ = 17, + _STATS_RATE_FAIL_ = 18, + _STATS_REFUSED_TEMPORARILY_ = 30, + _STATS_DECLINE_REQ_ = 37, + _STATS_INVALID_PARAMETERS_ = 38, + _STATS_INVALID_RSNIE_ = 72, +}; + +/* entended */ +/* IEEE 802.11b */ +#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 +#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 +#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 +/* IEEE 802.11h */ +#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22 +#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23 +#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24 +/* IEEE 802.11g */ +#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25 +#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26 +#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27 +/* IEEE 802.11w */ +#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30 +#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31 +/* IEEE 802.11i */ +#define WLAN_STATUS_INVALID_IE 40 +#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41 +#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42 +#define WLAN_STATUS_AKMP_NOT_VALID 43 +#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44 +#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45 +#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46 +#define WLAN_STATUS_TS_NOT_CREATED 47 +#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48 +#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49 +#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50 +#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51 +/* IEEE 802.11r */ +#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52 +#define WLAN_STATUS_INVALID_PMKID 53 +#define WLAN_STATUS_INVALID_MDIE 54 +#define WLAN_STATUS_INVALID_FTIE 55 + +enum WIFI_REG_DOMAIN { + DOMAIN_FCC = 1, + DOMAIN_IC = 2, + DOMAIN_ETSI = 3, + DOMAIN_SPAIN = 4, + DOMAIN_FRANCE = 5, + DOMAIN_MKK = 6, + DOMAIN_ISRAEL = 7, + DOMAIN_MKK1 = 8, + DOMAIN_MKK2 = 9, + DOMAIN_MKK3 = 10, + DOMAIN_MAX +}; + +#define _TO_DS_ BIT(8) +#define _FROM_DS_ BIT(9) +#define _MORE_FRAG_ BIT(10) +#define _RETRY_ BIT(11) +#define _PWRMGT_ BIT(12) +#define _MORE_DATA_ BIT(13) +#define _PRIVACY_ BIT(14) +#define _ORDER_ BIT(15) + +#define SetToDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \ + } while (0) + +#define GetToDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0) + +#define ClearToDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \ + } while (0) + +#define SetFrDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \ + } while (0) + +#define GetFrDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0) + +#define ClearFrDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \ + } while (0) + +#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) + +#define SetMFrag(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \ + } while (0) + +#define GetMFrag(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0) + +#define ClearMFrag(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \ + } while (0) + +#define SetRetry(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \ + } while (0) + +#define GetRetry(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0) + +#define ClearRetry(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \ + } while (0) + +#define SetPwrMgt(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \ + } while (0) + +#define GetPwrMgt(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0) + +#define ClearPwrMgt(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \ + } while (0) + +#define SetMData(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \ + } while (0) + +#define GetMData(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0) + +#define ClearMData(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \ + } while (0) + +#define SetPrivacy(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \ + } while (0) + +#define GetPrivacy(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0) + +#define ClearPrivacy(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \ + } while (0) + +#define GetOrder(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) + +#define GetFrameType(pbuf) (le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2))) + +#define SetFrameType(pbuf, type) \ + do { \ + *(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \ + *(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \ + } while (0) + +#define get_frame_sub_type(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) + +#define set_frame_sub_type(pbuf, type) \ + do { \ + *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ + *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ + } while (0) + +#define GetSequence(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4) + +#define GetFragNum(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f) + +#define GetTupleCache(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22))) + +#define SetFragNum(pbuf, num) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ + ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \ + cpu_to_le16(0x0f & (num)); \ + } while (0) + +#define SetSeqNum(pbuf, num) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ + ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \ + le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \ + } while (0) + +#define set_duration(pbuf, dur) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \ + } while (0) + +#define SetPriority(pbuf, tid) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \ + } while (0) + +#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf) + +#define SetEOSP(pbuf, eosp) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16((eosp & 1) << 4); \ + } while (0) + +#define SetAckpolicy(pbuf, ack) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16((ack & 3) << 5); \ + } while (0) + +#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3) + +#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1) + +#define SetAMsdu(pbuf, amsdu) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16((amsdu & 1) << 7); \ + } while (0) + +#define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff) + +#define GetTid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1) | GetFrDs(pbuf)) == 3 ? 30 : 24))) & 0x000f) + +#define GetAddr1Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 4)) + +#define get_addr2_ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10)) + +#define GetAddr3Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 16)) + +#define GetAddr4Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 24)) + +#define MacAddr_isBcst(addr) \ + (\ + ((addr[0] == 0xff) && (addr[1] == 0xff) && \ + (addr[2] == 0xff) && (addr[3] == 0xff) && \ + (addr[4] == 0xff) && (addr[5] == 0xff)) ? _TRUE : _FALSE \ + ) + +__inline static int IS_MCAST(unsigned char *da) +{ + if ((*da) & 0x01) + return _TRUE; + else + return _FALSE; +} + +__inline static unsigned char *get_ra(unsigned char *pframe) +{ + unsigned char *ra; + ra = GetAddr1Ptr(pframe); + return ra; +} +__inline static unsigned char *get_ta(unsigned char *pframe) +{ + unsigned char *ta; + ta = get_addr2_ptr(pframe); + return ta; +} + +__inline static unsigned char *get_da(unsigned char *pframe) +{ + unsigned char *da; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: /* ToDs=0, FromDs=0 */ + da = GetAddr1Ptr(pframe); + break; + case 0x01: /* ToDs=0, FromDs=1 */ + da = GetAddr1Ptr(pframe); + break; + case 0x02: /* ToDs=1, FromDs=0 */ + da = GetAddr3Ptr(pframe); + break; + default: /* ToDs=1, FromDs=1 */ + da = GetAddr3Ptr(pframe); + break; + } + + return da; +} + +__inline static unsigned char *get_sa(unsigned char *pframe) +{ + unsigned char *sa; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: /* ToDs=0, FromDs=0 */ + sa = get_addr2_ptr(pframe); + break; + case 0x01: /* ToDs=0, FromDs=1 */ + sa = GetAddr3Ptr(pframe); + break; + case 0x02: /* ToDs=1, FromDs=0 */ + sa = get_addr2_ptr(pframe); + break; + default: /* ToDs=1, FromDs=1 */ + sa = GetAddr4Ptr(pframe); + break; + } + + return sa; +} + +__inline static unsigned char *get_hdr_bssid(unsigned char *pframe) +{ + unsigned char *sa = NULL; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: /* ToDs=0, FromDs=0 */ + sa = GetAddr3Ptr(pframe); + break; + case 0x01: /* ToDs=0, FromDs=1 */ + sa = get_addr2_ptr(pframe); + break; + case 0x02: /* ToDs=1, FromDs=0 */ + sa = GetAddr1Ptr(pframe); + break; + case 0x03: /* ToDs=1, FromDs=1 */ + sa = GetAddr1Ptr(pframe); + break; + } + + return sa; +} + +__inline static int IsFrameTypeCtrl(unsigned char *pframe) +{ + if (WIFI_CTRL_TYPE == GetFrameType(pframe)) + return _TRUE; + else + return _FALSE; +} +/*----------------------------------------------------------------------------- + Below is for the security related definition +------------------------------------------------------------------------------*/ +#define _RESERVED_FRAME_TYPE_ 0 +#define _SKB_FRAME_TYPE_ 2 +#define _PRE_ALLOCMEM_ 1 +#define _PRE_ALLOCHDR_ 3 +#define _PRE_ALLOCLLCHDR_ 4 +#define _PRE_ALLOCICVHDR_ 5 +#define _PRE_ALLOCMICHDR_ 6 + +#define _SIFSTIME_ ((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A) ? 16 : 10) +#define _ACKCTSLNG_ 14 /* 14 bytes long, including crclng */ +#define _CRCLNG_ 4 + +#define _ASOCREQ_IE_OFFSET_ 4 /* excluding wlan_hdr */ +#define _ASOCRSP_IE_OFFSET_ 6 +#define _REASOCREQ_IE_OFFSET_ 10 +#define _REASOCRSP_IE_OFFSET_ 6 +#define _PROBEREQ_IE_OFFSET_ 0 +#define _PROBERSP_IE_OFFSET_ 12 +#define _AUTH_IE_OFFSET_ 6 +#define _DEAUTH_IE_OFFSET_ 0 +#define _BEACON_IE_OFFSET_ 12 +#define _PUBLIC_ACTION_IE_OFFSET_ 8 + +#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ + +#define _SSID_IE_ 0 +#define _SUPPORTEDRATES_IE_ 1 +#define _DSSET_IE_ 3 +#define _TIM_IE_ 5 +#define _IBSS_PARA_IE_ 6 +#define _COUNTRY_IE_ 7 +#define _CHLGETXT_IE_ 16 +#define _SUPPORTED_CH_IE_ 36 +#define _CH_SWTICH_ANNOUNCE_ 37 /* Secondary Channel Offset */ +#define _RSN_IE_2_ 48 +#define _SSN_IE_1_ 221 +#define _ERPINFO_IE_ 42 +#define _EXT_SUPPORTEDRATES_IE_ 50 + +#define _HT_CAPABILITY_IE_ 45 +#define _MDIE_ 54 +#define _FTIE_ 55 +#define _TIMEOUT_ITVL_IE_ 56 +#define _SRC_IE_ 59 +#define _HT_EXTRA_INFO_IE_ 61 +#define _HT_ADD_INFO_IE_ 61 /* _HT_EXTRA_INFO_IE_ */ +#define _WAPI_IE_ 68 + +/* #define EID_BSSCoexistence 72 */ /* 20/40 BSS Coexistence + * #define EID_BSSIntolerantChlReport 73 */ +#define _RIC_Descriptor_IE_ 75 +#define _LINK_ID_IE_ 101 +#define _CH_SWITCH_TIMING_ 104 +#define _PTI_BUFFER_STATUS_ 106 +#define _EXT_CAP_IE_ 127 +#define _VENDOR_SPECIFIC_IE_ 221 + +#define _RESERVED47_ 47 + +typedef enum _ELEMENT_ID { + EID_SsId = 0, /* service set identifier (0:32) */ + EID_SupRates = 1, /* supported rates (1:8) */ + EID_FHParms = 2, /* FH parameter set (5) */ + EID_DSParms = 3, /* DS parameter set (1) */ + EID_CFParms = 4, /* CF parameter set (6) */ + EID_Tim = 5, /* Traffic Information Map (4:254) */ + EID_IbssParms = 6, /* IBSS parameter set (2) */ + EID_Country = 7, /* */ + + /* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */ + EID_QBSSLoad = 11, + EID_EDCAParms = 12, + EID_TSpec = 13, + EID_TClass = 14, + EID_Schedule = 15, + /* */ + + EID_Ctext = 16, /* challenge text*/ + EID_POWER_CONSTRAINT = 32, /* Power Constraint*/ + + /* vivi for WIFITest, 802.11h AP, 20100427 */ + /* 2010/12/26 MH The definition we can declare always!! */ + EID_PowerCap = 33, + EID_SupportedChannels = 36, + EID_ChlSwitchAnnounce = 37, + + EID_MeasureRequest = 38, /* Measurement Request */ + EID_MeasureReport = 39, /* Measurement Report */ + + EID_ERPInfo = 42, + + /* Form 7.3.2: Information elements in 802.11E/D13.0, page 46. */ + EID_TSDelay = 43, + EID_TCLASProc = 44, + EID_HTCapability = 45, + EID_QoSCap = 46, + /* */ + + EID_WPA2 = 48, + EID_ExtSupRates = 50, + + EID_FTIE = 55, /* Defined in 802.11r */ + EID_Timeout = 56, /* Defined in 802.11r */ + + EID_SupRegulatory = 59, /* Supported Requlatory Classes 802.11y */ + EID_HTInfo = 61, + EID_SecondaryChnlOffset = 62, + + EID_BSSCoexistence = 72, /* 20/40 BSS Coexistence */ + EID_BSSIntolerantChlReport = 73, + EID_OBSS = 74, /* Overlapping BSS Scan Parameters */ + + EID_LinkIdentifier = 101, /* Defined in 802.11z */ + EID_WakeupSchedule = 102, /* Defined in 802.11z */ + EID_ChnlSwitchTimeing = 104, /* Defined in 802.11z */ + EID_PTIControl = 105, /* Defined in 802.11z */ + EID_PUBufferStatus = 106, /* Defined in 802.11z */ + + EID_EXTCapability = 127, /* Extended Capabilities */ + /* From S19:Aironet IE and S21:AP IP address IE in CCX v1.13, p16 and p18. */ + EID_Aironet = 133, /* 0x85: Aironet Element for Cisco CCX */ + EID_CiscoIP = 149, /* 0x95: IP Address IE for Cisco CCX */ + + EID_CellPwr = 150, /* 0x96: Cell Power Limit IE. Ref. 0x96. */ + + EID_CCKM = 156, + + EID_Vendor = 221, /* 0xDD: Vendor Specific */ + + EID_WAPI = 68, + EID_VHTCapability = 191, /* Based on 802.11ac D2.0 */ + EID_VHTOperation = 192, /* Based on 802.11ac D2.0 */ + EID_AID = 197, /* Based on 802.11ac D4.0 */ + EID_OpModeNotification = 199, /* Based on 802.11ac D3.0 */ +} ELEMENT_ID, *PELEMENT_ID; + +/* --------------------------------------------------------------------------- + Below is the fixed elements... +-----------------------------------------------------------------------------*/ +#define _AUTH_ALGM_NUM_ 2 +#define _AUTH_SEQ_NUM_ 2 +#define _BEACON_ITERVAL_ 2 +#define _CAPABILITY_ 2 +#define _CURRENT_APADDR_ 6 +#define _LISTEN_INTERVAL_ 2 +#define _RSON_CODE_ 2 +#define _ASOC_ID_ 2 +#define _STATUS_CODE_ 2 +#define _TIMESTAMP_ 8 + +#define AUTH_ODD_TO 0 +#define AUTH_EVEN_TO 1 + +#define WLAN_ETHCONV_ENCAP 1 +#define WLAN_ETHCONV_RFC1042 2 +#define WLAN_ETHCONV_8021h 3 + +#define cap_ESS BIT(0) +#define cap_IBSS BIT(1) +#define cap_CFPollable BIT(2) +#define cap_CFRequest BIT(3) +#define cap_Privacy BIT(4) +#define cap_ShortPremble BIT(5) +#define cap_PBCC BIT(6) +#define cap_ChAgility BIT(7) +#define cap_SpecMgmt BIT(8) +#define cap_QoS BIT(9) +#define cap_ShortSlot BIT(10) + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11i / 802.1x +------------------------------------------------------------------------------*/ +#define _IEEE8021X_MGT_ 1 /* WPA */ +#define _IEEE8021X_PSK_ 2 /* WPA with pre-shared key */ + +/*----------------------------------------------------------------------------- + Below is the definition for WMM +------------------------------------------------------------------------------*/ +#define _WMM_IE_Length_ 7 /* for WMM STA */ +#define _WMM_Para_Element_Length_ 24 + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11n +------------------------------------------------------------------------------*/ + +#define set_order_bit(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ + } while (0) + +#define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) + +#define ACT_CAT_VENDOR 0x7F/* 127 */ + +/** + * struct rtw_ieee80211_bar - HT Block Ack Request + * + * This structure refers to "HT BlockAckReq" as + * described in 802.11n draft section 7.2.1.7.1 + */ +struct rtw_ieee80211_bar { + unsigned short frame_control; + unsigned short duration; + unsigned char ra[6]; + unsigned char ta[6]; + unsigned short control; + unsigned short start_seq_num; +} __attribute__((packed)); + +/* 802.11 BAR control masks */ +#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL 0x0000 +#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA 0x0004 + + +/** +* struct rtw_ieee80211_ht_cap - HT capabilities +* +* This structure refers to "HT capabilities element" as +* described in 802.11n draft section 7.3.2.52 +*/ + +struct rtw_ieee80211_ht_cap { + unsigned short cap_info; + unsigned char ampdu_params_info; + unsigned char supp_mcs_set[16]; + unsigned short extended_ht_cap_info; + unsigned int tx_BF_cap_info; + unsigned char antenna_selection_info; +} __attribute__((packed)); + +/** + * struct rtw_ieee80211_ht_cap - HT additional information + * + * This structure refers to "HT information element" as + * described in 802.11n draft section 7.3.2.53 + */ +struct ieee80211_ht_addt_info { + unsigned char control_chan; + unsigned char ht_param; + unsigned short operation_mode; + unsigned short stbc_param; + unsigned char basic_set[16]; +} __attribute__((packed)); + +struct HT_caps_element { + union { + struct { + unsigned short HT_caps_info; + unsigned char AMPDU_para; + unsigned char MCS_rate[16]; + unsigned short HT_ext_caps; + unsigned int Beamforming_caps; + unsigned char ASEL_caps; + } HT_cap_element; + unsigned char HT_cap[26]; + } u; +} __attribute__((packed)); + +struct HT_info_element { + unsigned char primary_channel; + unsigned char infos[5]; + unsigned char MCS_rate[16]; +} __attribute__((packed)); + +struct AC_param { + unsigned char ACI_AIFSN; + unsigned char CW; + unsigned short TXOP_limit; +} __attribute__((packed)); + +struct WMM_para_element { + unsigned char QoS_info; + unsigned char reserved; + struct AC_param ac_param[4]; +} __attribute__((packed)); + +struct ADDBA_request { + unsigned char dialog_token; + unsigned short BA_para_set; + unsigned short BA_timeout_value; + unsigned short BA_starting_seqctrl; +} __attribute__((packed)); + + +typedef enum _HT_CAP_AMPDU_FACTOR { + MAX_AMPDU_FACTOR_8K = 0, + MAX_AMPDU_FACTOR_16K = 1, + MAX_AMPDU_FACTOR_32K = 2, + MAX_AMPDU_FACTOR_64K = 3, +} HT_CAP_AMPDU_FACTOR; + +typedef enum _VHT_CAP_AMPDU_FACTOR { + MAX_AMPDU_FACTOR_128K = 4, + MAX_AMPDU_FACTOR_256K = 5, + MAX_AMPDU_FACTOR_512K = 6, + MAX_AMPDU_FACTOR_1M = 7, +} VHT_CAP_AMPDU_FACTOR; + +typedef enum _HT_CAP_AMPDU_DENSITY { + AMPDU_DENSITY_VALUE_0 = 0 , /* For no restriction */ + AMPDU_DENSITY_VALUE_1 = 1 , /* For 1/4 us */ + AMPDU_DENSITY_VALUE_2 = 2 , /* For 1/2 us */ + AMPDU_DENSITY_VALUE_3 = 3 , /* For 1 us */ + AMPDU_DENSITY_VALUE_4 = 4 , /* For 2 us */ + AMPDU_DENSITY_VALUE_5 = 5 , /* For 4 us */ + AMPDU_DENSITY_VALUE_6 = 6 , /* For 8 us */ + AMPDU_DENSITY_VALUE_7 = 7 , /* For 16 us */ +} HT_CAP_AMPDU_DENSITY; + +/* 802.11n HT capabilities masks */ +#define IEEE80211_HT_CAP_LDPC_CODING 0x0001 +#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002 +#define IEEE80211_HT_CAP_SM_PS 0x000C +#define IEEE80211_HT_CAP_GRN_FLD 0x0010 +#define IEEE80211_HT_CAP_SGI_20 0x0020 +#define IEEE80211_HT_CAP_SGI_40 0x0040 +#define IEEE80211_HT_CAP_TX_STBC 0x0080 +#define IEEE80211_HT_CAP_RX_STBC_1R 0x0100 +#define IEEE80211_HT_CAP_RX_STBC_2R 0x0200 +#define IEEE80211_HT_CAP_RX_STBC_3R 0x0300 +#define IEEE80211_HT_CAP_DELAY_BA 0x0400 +#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 +#define IEEE80211_HT_CAP_DSSSCCK40 0x1000 +#define RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT ((u16) BIT(14)) +/* 802.11n HT capability AMPDU settings */ +#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 +#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C +/* 802.11n HT capability MSC set */ +#define IEEE80211_SUPP_MCS_SET_UEQM 4 +#define IEEE80211_HT_CAP_MAX_STREAMS 4 +#define IEEE80211_SUPP_MCS_SET_LEN 10 +/* maximum streams the spec allows */ +#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 +#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 +#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C +#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 +/* 802.11n HT capability TXBF capability */ +#define IEEE80211_HT_CAP_TXBF_RX_NDP 0x00000008 +#define IEEE80211_HT_CAP_TXBF_TX_NDP 0x00000010 +#define IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP 0x00000400 + +/* 802.11n HT IE masks */ +#define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03 +#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00 +#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01 +#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03 +#define IEEE80211_HT_IE_CHA_WIDTH 0x04 +#define IEEE80211_HT_IE_HT_PROTECTION 0x0003 +#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 +#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 + +/* block-ack parameters */ +#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 +#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C +#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0 +#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 +#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 + +/* Spatial Multiplexing Power Save Modes */ +#define WLAN_HT_CAP_SM_PS_STATIC 0 +#define WLAN_HT_CAP_SM_PS_DYNAMIC 1 +#define WLAN_HT_CAP_SM_PS_INVALID 2 +#define WLAN_HT_CAP_SM_PS_DISABLED 3 + +#define OP_MODE_PURE 0 +#define OP_MODE_MAY_BE_LEGACY_STAS 1 +#define OP_MODE_20MHZ_HT_STA_ASSOCED 2 +#define OP_MODE_MIXED 3 + +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2)) +#define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3)) +#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4)) +#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5)) + +#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \ + ((u16) (0x0001 | 0x0002)) +#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0 +#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2)) +#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) +#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) + +#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) +#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) +#define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8)) +#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) +#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) +#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) + +/* #endif */ + +/* ===============WPS Section=============== */ +/* For WPSv1.0 */ +#define WPSOUI 0x0050f204 +/* WPS attribute ID */ +#define WPS_ATTR_VER1 0x104A +#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 +#define WPS_ATTR_RESP_TYPE 0x103B +#define WPS_ATTR_UUID_E 0x1047 +#define WPS_ATTR_MANUFACTURER 0x1021 +#define WPS_ATTR_MODEL_NAME 0x1023 +#define WPS_ATTR_MODEL_NUMBER 0x1024 +#define WPS_ATTR_SERIAL_NUMBER 0x1042 +#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 +#define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055 +#define WPS_ATTR_DEVICE_NAME 0x1011 +#define WPS_ATTR_CONF_METHOD 0x1008 +#define WPS_ATTR_RF_BANDS 0x103C +#define WPS_ATTR_DEVICE_PWID 0x1012 +#define WPS_ATTR_REQUEST_TYPE 0x103A +#define WPS_ATTR_ASSOCIATION_STATE 0x1002 +#define WPS_ATTR_CONFIG_ERROR 0x1009 +#define WPS_ATTR_VENDOR_EXT 0x1049 +#define WPS_ATTR_SELECTED_REGISTRAR 0x1041 + +/* Value of WPS attribute "WPS_ATTR_DEVICE_NAME */ +#define WPS_MAX_DEVICE_NAME_LEN 32 + +/* Value of WPS Request Type Attribute */ +#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 +#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 +#define WPS_REQ_TYPE_REGISTRAR 0x02 +#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 + +/* Value of WPS Response Type Attribute */ +#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 +#define WPS_RESPONSE_TYPE_8021X 0x01 +#define WPS_RESPONSE_TYPE_REGISTRAR 0x02 +#define WPS_RESPONSE_TYPE_AP 0x03 + +/* Value of WPS WiFi Simple Configuration State Attribute */ +#define WPS_WSC_STATE_NOT_CONFIG 0x01 +#define WPS_WSC_STATE_CONFIG 0x02 + +/* Value of WPS Version Attribute */ +#define WPS_VERSION_1 0x10 + +/* Value of WPS Configuration Method Attribute */ +#define WPS_CONFIG_METHOD_FLASH 0x0001 +#define WPS_CONFIG_METHOD_ETHERNET 0x0002 +#define WPS_CONFIG_METHOD_LABEL 0x0004 +#define WPS_CONFIG_METHOD_DISPLAY 0x0008 +#define WPS_CONFIG_METHOD_E_NFC 0x0010 +#define WPS_CONFIG_METHOD_I_NFC 0x0020 +#define WPS_CONFIG_METHOD_NFC 0x0040 +#define WPS_CONFIG_METHOD_PBC 0x0080 +#define WPS_CONFIG_METHOD_KEYPAD 0x0100 +#define WPS_CONFIG_METHOD_VPBC 0x0280 +#define WPS_CONFIG_METHOD_PPBC 0x0480 +#define WPS_CONFIG_METHOD_VDISPLAY 0x2008 +#define WPS_CONFIG_METHOD_PDISPLAY 0x4008 + +/* Value of Category ID of WPS Primary Device Type Attribute */ +#define WPS_PDT_CID_DISPLAYS 0x0007 +#define WPS_PDT_CID_MULIT_MEDIA 0x0008 +#define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA + +/* Value of Sub Category ID of WPS Primary Device Type Attribute */ +#define WPS_PDT_SCID_MEDIA_SERVER 0x0005 +#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER + +/* Value of Device Password ID */ +#define WPS_DPID_PIN 0x0000 +#define WPS_DPID_USER_SPEC 0x0001 +#define WPS_DPID_MACHINE_SPEC 0x0002 +#define WPS_DPID_REKEY 0x0003 +#define WPS_DPID_PBC 0x0004 +#define WPS_DPID_REGISTRAR_SPEC 0x0005 + +/* Value of WPS RF Bands Attribute */ +#define WPS_RF_BANDS_2_4_GHZ 0x01 +#define WPS_RF_BANDS_5_GHZ 0x02 + +/* Value of WPS Association State Attribute */ +#define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00 +#define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01 +#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02 +#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 +#define WPS_ASSOC_STATE_IP_FAILURE 0x04 + +/* =====================P2P Section===================== */ +/* For P2P */ +#define P2POUI 0x506F9A09 + +/* P2P Attribute ID */ +#define P2P_ATTR_STATUS 0x00 +#define P2P_ATTR_MINOR_REASON_CODE 0x01 +#define P2P_ATTR_CAPABILITY 0x02 +#define P2P_ATTR_DEVICE_ID 0x03 +#define P2P_ATTR_GO_INTENT 0x04 +#define P2P_ATTR_CONF_TIMEOUT 0x05 +#define P2P_ATTR_LISTEN_CH 0x06 +#define P2P_ATTR_GROUP_BSSID 0x07 +#define P2P_ATTR_EX_LISTEN_TIMING 0x08 +#define P2P_ATTR_INTENDED_IF_ADDR 0x09 +#define P2P_ATTR_MANAGEABILITY 0x0A +#define P2P_ATTR_CH_LIST 0x0B +#define P2P_ATTR_NOA 0x0C +#define P2P_ATTR_DEVICE_INFO 0x0D +#define P2P_ATTR_GROUP_INFO 0x0E +#define P2P_ATTR_GROUP_ID 0x0F +#define P2P_ATTR_INTERFACE 0x10 +#define P2P_ATTR_OPERATING_CH 0x11 +#define P2P_ATTR_INVITATION_FLAGS 0x12 + +/* Value of Status Attribute */ +#define P2P_STATUS_SUCCESS 0x00 +#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 +#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 +#define P2P_STATUS_FAIL_INVALID_PARAM 0x04 +#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 +#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 +#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 +#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 +#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A +#define P2P_STATUS_FAIL_USER_REJECT 0x0B + +/* Value of Inviation Flags Attribute */ +#define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) + +#define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \ + P2P_DEVCAP_CLIENT_DISCOVERABILITY | \ + P2P_DEVCAP_CONCURRENT_OPERATION | \ + P2P_DEVCAP_INVITATION_PROC) + +#define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS) + +/* Value of Device Capability Bitmap */ +#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) +#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) +#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) +#define P2P_DEVCAP_INFRA_MANAGED BIT(3) +#define P2P_DEVCAP_DEVICE_LIMIT BIT(4) +#define P2P_DEVCAP_INVITATION_PROC BIT(5) + +/* Value of Group Capability Bitmap */ +#define P2P_GRPCAP_GO BIT(0) +#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) +#define P2P_GRPCAP_GROUP_LIMIT BIT(2) +#define P2P_GRPCAP_INTRABSS BIT(3) +#define P2P_GRPCAP_CROSS_CONN BIT(4) +#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) +#define P2P_GRPCAP_GROUP_FORMATION BIT(6) + +/* P2P Public Action Frame ( Management Frame ) */ +#define P2P_PUB_ACTION_ACTION 0x09 + +/* P2P Public Action Frame Type */ +#define P2P_GO_NEGO_REQ 0 +#define P2P_GO_NEGO_RESP 1 +#define P2P_GO_NEGO_CONF 2 +#define P2P_INVIT_REQ 3 +#define P2P_INVIT_RESP 4 +#define P2P_DEVDISC_REQ 5 +#define P2P_DEVDISC_RESP 6 +#define P2P_PROVISION_DISC_REQ 7 +#define P2P_PROVISION_DISC_RESP 8 + +/* P2P Action Frame Type */ +#define P2P_NOTICE_OF_ABSENCE 0 +#define P2P_PRESENCE_REQUEST 1 +#define P2P_PRESENCE_RESPONSE 2 +#define P2P_GO_DISC_REQUEST 3 + +#define P2P_MAX_PERSISTENT_GROUP_NUM 10 + +#define P2P_PROVISIONING_SCAN_CNT 3 + +#define P2P_WILDCARD_SSID_LEN 7 + +#define P2P_FINDPHASE_EX_NONE 0 /* default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase */ +#define P2P_FINDPHASE_EX_FULL 1 /* used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase */ +#define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1) +#define P2P_FINDPHASE_EX_MAX 4 +#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX + +#define P2P_PROVISION_TIMEOUT 5000 /* 5 seconds timeout for sending the provision discovery request */ +#define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 /* 3 seconds timeout for sending the provision discovery request under concurrent mode */ +#define P2P_GO_NEGO_TIMEOUT 5000 /* 5 seconds timeout for receiving the group negotation response */ +#define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 /* 3 seconds timeout for sending the negotiation request under concurrent mode */ +#define P2P_TX_PRESCAN_TIMEOUT 100 /* 100ms */ +#define P2P_INVITE_TIMEOUT 5000 /* 5 seconds timeout for sending the invitation request */ +#define P2P_CONCURRENT_INVITE_TIMEOUT 3000 /* 3 seconds timeout for sending the invitation request under concurrent mode */ +#define P2P_RESET_SCAN_CH 25000 /* 25 seconds timeout to reset the scan channel (based on channel plan) */ +#define P2P_MAX_INTENT 15 + +#define P2P_MAX_NOA_NUM 2 + +/* WPS Configuration Method */ +#define WPS_CM_NONE 0x0000 +#define WPS_CM_LABEL 0x0004 +#define WPS_CM_DISPLYA 0x0008 +#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 +#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 +#define WPS_CM_NFC_INTERFACE 0x0040 +#define WPS_CM_PUSH_BUTTON 0x0080 +#define WPS_CM_KEYPAD 0x0100 +#define WPS_CM_SW_PUHS_BUTTON 0x0280 +#define WPS_CM_HW_PUHS_BUTTON 0x0480 +#define WPS_CM_SW_DISPLAY_PIN 0x2008 +#define WPS_CM_LCD_DISPLAY_PIN 0x4008 + +enum P2P_ROLE { + P2P_ROLE_DISABLE = 0, + P2P_ROLE_DEVICE = 1, + P2P_ROLE_CLIENT = 2, + P2P_ROLE_GO = 3 +}; + +enum P2P_STATE { + P2P_STATE_NONE = 0, /* P2P disable */ + P2P_STATE_IDLE = 1, /* P2P had enabled and do nothing , buddy adapters is linked */ + P2P_STATE_LISTEN = 2, /* In pure listen state */ + P2P_STATE_SCAN = 3, /* In scan phase */ + P2P_STATE_FIND_PHASE_LISTEN = 4, /* In the listen state of find phase */ + P2P_STATE_FIND_PHASE_SEARCH = 5, /* In the search state of find phase */ + P2P_STATE_TX_PROVISION_DIS_REQ = 6, /* In P2P provisioning discovery */ + P2P_STATE_RX_PROVISION_DIS_RSP = 7, + P2P_STATE_RX_PROVISION_DIS_REQ = 8, + P2P_STATE_GONEGO_ING = 9, /* Doing the group owner negoitation handshake */ + P2P_STATE_GONEGO_OK = 10, /* finish the group negoitation handshake with success */ + P2P_STATE_GONEGO_FAIL = 11, /* finish the group negoitation handshake with failure */ + P2P_STATE_RECV_INVITE_REQ_MATCH = 12, /* receiving the P2P Inviation request and match with the profile. */ + P2P_STATE_PROVISIONING_ING = 13, /* Doing the P2P WPS */ + P2P_STATE_PROVISIONING_DONE = 14, /* Finish the P2P WPS */ + P2P_STATE_TX_INVITE_REQ = 15, /* Transmit the P2P Invitation request */ + P2P_STATE_RX_INVITE_RESP_OK = 16, /* Receiving the P2P Invitation response */ + P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17, /* receiving the P2P Inviation request and dismatch with the profile. */ + P2P_STATE_RECV_INVITE_REQ_GO = 18, /* receiving the P2P Inviation request and this wifi is GO. */ + P2P_STATE_RECV_INVITE_REQ_JOIN = 19, /* receiving the P2P Inviation request to join an existing P2P Group. */ + P2P_STATE_RX_INVITE_RESP_FAIL = 20, /* recveing the P2P Inviation response with failure */ + P2P_STATE_RX_INFOR_NOREADY = 21, /* receiving p2p negoitation response with information is not available */ + P2P_STATE_TX_INFOR_NOREADY = 22, /* sending p2p negoitation response with information is not available */ +}; + +enum P2P_WPSINFO { + P2P_NO_WPSINFO = 0, + P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1, + P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2, + P2P_GOT_WPSINFO_PBC = 3, +}; + +#define P2P_PRIVATE_IOCTL_SET_LEN 64 + +enum P2P_PROTO_WK_ID { + P2P_FIND_PHASE_WK = 0, + P2P_RESTORE_STATE_WK = 1, + P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, + P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, + P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, + P2P_AP_P2P_CH_SWITCH_PROCESS_WK = 5, + P2P_RO_CH_WK = 6, + P2P_CANCEL_RO_CH_WK = 7, +}; + +enum P2P_PS_STATE { + P2P_PS_DISABLE = 0, + P2P_PS_ENABLE = 1, + P2P_PS_SCAN = 2, + P2P_PS_SCAN_DONE = 3, + P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */ +}; + +enum P2P_PS_MODE { + P2P_PS_NONE = 0, + P2P_PS_CTWINDOW = 1, + P2P_PS_NOA = 2, + P2P_PS_MIX = 3, /* CTWindow and NoA */ +}; + +/* =====================WFD Section===================== + * For Wi-Fi Display */ +#define WFD_ATTR_DEVICE_INFO 0x00 +#define WFD_ATTR_ASSOC_BSSID 0x01 +#define WFD_ATTR_COUPLED_SINK_INFO 0x06 +#define WFD_ATTR_LOCAL_IP_ADDR 0x08 +#define WFD_ATTR_SESSION_INFO 0x09 +#define WFD_ATTR_ALTER_MAC 0x0a + +/* For WFD Device Information Attribute */ +#define WFD_DEVINFO_SOURCE 0x0000 +#define WFD_DEVINFO_PSINK 0x0001 +#define WFD_DEVINFO_SSINK 0x0002 +#define WFD_DEVINFO_DUAL 0x0003 + +#define WFD_DEVINFO_SESSION_AVAIL 0x0010 +#define WFD_DEVINFO_WSD 0x0040 +#define WFD_DEVINFO_PC_TDLS 0x0080 +#define WFD_DEVINFO_HDCP_SUPPORT 0x0100 + +#define IP_MCAST_MAC(mac) ((mac[0] == 0x01) && (mac[1] == 0x00) && (mac[2] == 0x5e)) +#define ICMPV6_MCAST_MAC(mac) ((mac[0] == 0x33) && (mac[1] == 0x33) && (mac[2] != 0xff)) + + +#endif /* _WIFI_H_ */ diff --git a/drivers/staging/rtl8821ce/include/wlan_bssdef.h b/drivers/staging/rtl8821ce/include/wlan_bssdef.h new file mode 100644 index 000000000000..8436c4e314d4 --- /dev/null +++ b/drivers/staging/rtl8821ce/include/wlan_bssdef.h @@ -0,0 +1,360 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __WLAN_BSSDEF_H__ +#define __WLAN_BSSDEF_H__ + +#define MAX_IE_SZ 768 + + +#define NDIS_802_11_LENGTH_SSID 32 +#define NDIS_802_11_LENGTH_RATES 8 +#define NDIS_802_11_LENGTH_RATES_EX 16 + +typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; +typedef long NDIS_802_11_RSSI; /* in dBm */ +typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; /* Set of 8 data rates */ +typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; /* Set of 16 data rates */ + +typedef ULONG NDIS_802_11_KEY_INDEX; +typedef unsigned long long NDIS_802_11_KEY_RSC; + +typedef struct _NDIS_802_11_SSID { + ULONG SsidLength; + UCHAR Ssid[32]; +} NDIS_802_11_SSID, *PNDIS_802_11_SSID; + +typedef enum _NDIS_802_11_NETWORK_TYPE { + Ndis802_11FH, + Ndis802_11DS, + Ndis802_11OFDM5, + Ndis802_11OFDM24, + Ndis802_11NetworkTypeMax /* not a real type, defined as an upper bound */ +} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; + +typedef struct _NDIS_802_11_CONFIGURATION_FH { + ULONG Length; /* Length of structure */ + ULONG HopPattern; /* As defined by 802.11, MSB set */ + ULONG HopSet; /* to one if non-802.11 */ + ULONG DwellTime; /* units are Kusec */ +} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; + +/* + FW will only save the channel number in DSConfig. + ODI Handler will convert the channel number to freq. number. +*/ +typedef struct _NDIS_802_11_CONFIGURATION { + ULONG Length; /* Length of structure */ + ULONG BeaconPeriod; /* units are Kusec */ + ULONG ATIMWindow; /* units are Kusec */ + ULONG DSConfig; /* channel number */ + NDIS_802_11_CONFIGURATION_FH FHConfig; +} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; + +typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE { + Ndis802_11IBSS, + Ndis802_11Infrastructure, + Ndis802_11AutoUnknown, + Ndis802_11InfrastructureMax, /* Not a real value, defined as upper bound */ + Ndis802_11APMode, + Ndis802_11Monitor, +} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; + +typedef struct _NDIS_802_11_FIXED_IEs { + UCHAR Timestamp[8]; + USHORT BeaconInterval; + USHORT Capabilities; +} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; + +typedef struct _NDIS_802_11_VARIABLE_IEs { + UCHAR ElementID; + UCHAR Length; + UCHAR data[1]; +} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; + +/* + +Length is the 4 bytes multiples of the sume of + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG) ++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) ++ sizeof (NDIS_802_11_RATES_EX) + IELength + +Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the +partial sum. + +*/ + +typedef enum _NDIS_802_11_AUTHENTICATION_MODE { + Ndis802_11AuthModeOpen, + Ndis802_11AuthModeShared, + Ndis802_11AuthModeAutoSwitch, + Ndis802_11AuthModeWPA, + Ndis802_11AuthModeWPAPSK, + Ndis802_11AuthModeWPANone, + Ndis802_11AuthModeWAPI, + Ndis802_11AuthModeMax /* Not a real mode, defined as upper bound */ +} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; + +typedef enum _NDIS_802_11_WEP_STATUS { + Ndis802_11WEPEnabled, + Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, + Ndis802_11WEPDisabled, + Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, + Ndis802_11WEPKeyAbsent, + Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, + Ndis802_11WEPNotSupported, + Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, + Ndis802_11Encryption2Enabled, + Ndis802_11Encryption2KeyAbsent, + Ndis802_11Encryption3Enabled, + Ndis802_11Encryption3KeyAbsent, + Ndis802_11_EncrypteionWAPI +} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, +NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; + +#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 +#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 +#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 + +#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 +#define NDIS_802_11_AI_RESFI_STATUSCODE 2 +#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 + +typedef struct _NDIS_802_11_AI_REQFI { + USHORT Capabilities; + USHORT ListenInterval; + NDIS_802_11_MAC_ADDRESS CurrentAPAddress; +} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; + +typedef struct _NDIS_802_11_AI_RESFI { + USHORT Capabilities; + USHORT StatusCode; + USHORT AssociationId; +} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; + +typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION { + ULONG Length; + USHORT AvailableRequestFixedIEs; + NDIS_802_11_AI_REQFI RequestFixedIEs; + ULONG RequestIELength; + ULONG OffsetRequestIEs; + USHORT AvailableResponseFixedIEs; + NDIS_802_11_AI_RESFI ResponseFixedIEs; + ULONG ResponseIELength; + ULONG OffsetResponseIEs; +} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; + +typedef enum _NDIS_802_11_RELOAD_DEFAULTS { + Ndis802_11ReloadWEPKeys +} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; + +/* Key mapping keys require a BSSID */ +typedef struct _NDIS_802_11_KEY { + ULONG Length; /* Length of this structure */ + ULONG KeyIndex; + ULONG KeyLength; /* length of key in bytes */ + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_KEY_RSC KeyRSC; + UCHAR KeyMaterial[32]; /* variable length depending on above field */ +} NDIS_802_11_KEY, *PNDIS_802_11_KEY; + +typedef struct _NDIS_802_11_REMOVE_KEY { + ULONG Length; /* Length of this structure */ + ULONG KeyIndex; + NDIS_802_11_MAC_ADDRESS BSSID; +} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; + +typedef struct _NDIS_802_11_WEP { + ULONG Length; /* Length of this structure */ + ULONG KeyIndex; /* 0 is the per-client key, 1-N are the global keys */ + ULONG KeyLength; /* length of key in bytes */ + UCHAR KeyMaterial[16];/* variable length depending on above field */ +} NDIS_802_11_WEP, *PNDIS_802_11_WEP; + +typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST { + ULONG Length; /* Length of structure */ + NDIS_802_11_MAC_ADDRESS Bssid; + ULONG Flags; +} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; + +typedef enum _NDIS_802_11_STATUS_TYPE { + Ndis802_11StatusType_Authentication, + Ndis802_11StatusType_MediaStreamMode, + Ndis802_11StatusType_PMKID_CandidateList, + Ndis802_11StatusTypeMax /* not a real type, defined as an upper bound */ +} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; + +typedef struct _NDIS_802_11_STATUS_INDICATION { + NDIS_802_11_STATUS_TYPE StatusType; +} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; + +/* mask for authentication/integrity fields */ +#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f +#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 +#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 +#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 +#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E + +/* MIC check time, 60 seconds. */ +#define MIC_CHECK_TIME 60000000 + +typedef struct _NDIS_802_11_AUTHENTICATION_EVENT { + NDIS_802_11_STATUS_INDICATION Status; + NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; +} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; + +typedef struct _NDIS_802_11_TEST { + ULONG Length; + ULONG Type; + union { + NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; + NDIS_802_11_RSSI RssiTrigger; + } tt; +} NDIS_802_11_TEST, *PNDIS_802_11_TEST; + + +#ifndef Ndis802_11APMode +#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) +#endif + +typedef struct _WLAN_PHY_INFO { + u8 SignalStrength;/* (in percentage) */ + u8 SignalQuality;/* (in percentage) */ + u8 Optimum_antenna; /* for Antenna diversity */ + u8 Reserved_0; +} WLAN_PHY_INFO, *PWLAN_PHY_INFO; + +typedef struct _WLAN_BCN_INFO { + /* these infor get from rtw_get_encrypt_info when + * * translate scan to UI */ + u8 encryp_protocol;/* ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI */ + int group_cipher; /* WPA/WPA2 group cipher */ + int pairwise_cipher;/* //WPA/WPA2/WEP pairwise cipher */ + int is_8021x; + + /* bwmode 20/40 and ch_offset UP/LOW */ + unsigned short ht_cap_info; + unsigned char ht_info_infos_0; +} WLAN_BCN_INFO, *PWLAN_BCN_INFO; + +/* temporally add #pragma pack for structure alignment issue of +* WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() +*/ +typedef struct _WLAN_BSSID_EX { + ULONG Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + UCHAR Reserved[2];/* [0]: IS beacon frame */ + NDIS_802_11_SSID Ssid; + ULONG Privacy; + NDIS_802_11_RSSI Rssi;/* (in dBM,raw data ,get from PHY) */ + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + WLAN_PHY_INFO PhyInfo; + ULONG IELength; + UCHAR IEs[MAX_IE_SZ]; /* (timestamp, beacon interval, and capability information) */ +} +__attribute__((packed)) +WLAN_BSSID_EX, *PWLAN_BSSID_EX; + +#define BSS_EX_IES(bss_ex) ((bss_ex)->IEs) +#define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength) +#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == 2 ? 0 : 12) +#define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex))) +#define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex))) + +__inline static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss) +{ + return sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + bss->IELength; +} + +struct wlan_network { + _list list; + int network_type; /* refer to ieee80211.h for WIRELESS_11A/B/G */ + int fixed; /* set to fixed when not to be removed as site-surveying */ + unsigned long last_scanned; /* timestamp for the network */ + int aid; /* will only be valid when a BSS is joinned. */ + int join_res; + WLAN_BSSID_EX network; /* must be the last item */ + WLAN_BCN_INFO BcnInfo; + +}; + +enum VRTL_CARRIER_SENSE { + DISABLE_VCS, + ENABLE_VCS, + AUTO_VCS +}; + +enum VCS_TYPE { + NONE_VCS, + RTS_CTS, + CTS_TO_SELF +}; + +#define PWR_CAM 0 +#define PWR_MINPS 1 +#define PWR_MAXPS 2 +#define PWR_UAPSD 3 +#define PWR_VOIP 4 + +enum UAPSD_MAX_SP { + NO_LIMIT, + TWO_MSDU, + FOUR_MSDU, + SIX_MSDU +}; + +/* john */ +#define NUM_PRE_AUTH_KEY 16 +#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY + +/* +* WPA2 +*/ + +typedef struct _PMKID_CANDIDATE { + NDIS_802_11_MAC_ADDRESS BSSID; + ULONG Flags; +} PMKID_CANDIDATE, *PPMKID_CANDIDATE; + +typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST { + ULONG Version; /* Version of the structure */ + ULONG NumCandidates; /* No. of pmkid candidates */ + PMKID_CANDIDATE CandidateList[1]; +} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST; + +typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION { + NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported; + NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported; + +} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION; + +typedef struct _NDIS_802_11_CAPABILITY { + ULONG Length; + ULONG Version; + ULONG NoOfPMKIDs; + ULONG NoOfAuthEncryptPairsSupported; + NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1]; + +} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY; + +#endif /* #ifndef WLAN_BSSDEF_H_ */ diff --git a/drivers/staging/rtl8821ce/include/xmit_osdep.h b/drivers/staging/rtl8821ce/include/xmit_osdep.h new file mode 100644 index 000000000000..cb80fa7cc9ac --- /dev/null +++ b/drivers/staging/rtl8821ce/include/xmit_osdep.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __XMIT_OSDEP_H_ +#define __XMIT_OSDEP_H_ + +struct pkt_file { + _pkt *pkt; + SIZE_T pkt_len; /* the remainder length of the open_file */ + _buffer *cur_buffer; + u8 *buf_start; + u8 *cur_addr; + SIZE_T buf_len; +}; + +#define NR_XMITFRAME 256 + +struct xmit_priv; +struct pkt_attrib; +struct sta_xmit_priv; +struct xmit_frame; +struct xmit_buf; + +extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); + +void rtw_os_xmit_schedule(_adapter *padapter); + +int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag); +void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag); + +extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib); + +extern uint rtw_remainder_len(struct pkt_file *pfile); +extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile); +extern uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen); +extern sint rtw_endofpktfile(struct pkt_file *pfile); + +extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt); +extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe); + +void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed); + +void dump_os_queue(void *sel, _adapter *padapter); + +#endif /* __XMIT_OSDEP_H_ */ diff --git a/drivers/staging/rtl8821ce/os_dep/linux/ioctl_linux.c b/drivers/staging/rtl8821ce/os_dep/linux/ioctl_linux.c new file mode 100644 index 000000000000..25bcb6a5897f --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/ioctl_linux.c @@ -0,0 +1,8796 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _IOCTL_LINUX_C_ + +#include <drv_types.h> +#include <rtw_mp.h> +#include <rtw_mp_ioctl.h> +#include "../../hal/phydm/phydm_precomp.h" +#include "../../hal/hal_halmac.h" + +extern int rtw_ht_enable; + +#define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV+30) + +#define SCAN_ITEM_SIZE 768 +#define MAX_CUSTOM_LEN 64 +#define RATE_COUNT 4 + +extern int ui_pid[3]; + +/* combo scan */ +#define WEXT_CSCAN_AMOUNT 9 +#define WEXT_CSCAN_BUF_LEN 360 +#define WEXT_CSCAN_HEADER "CSCAN S\x01\x00\x00S\x00" +#define WEXT_CSCAN_HEADER_SIZE 12 +#define WEXT_CSCAN_SSID_SECTION 'S' +#define WEXT_CSCAN_CHANNEL_SECTION 'C' +#define WEXT_CSCAN_NPROBE_SECTION 'N' +#define WEXT_CSCAN_ACTV_DWELL_SECTION 'A' +#define WEXT_CSCAN_PASV_DWELL_SECTION 'P' +#define WEXT_CSCAN_HOME_DWELL_SECTION 'H' +#define WEXT_CSCAN_TYPE_SECTION 'T' + +extern u8 key_2char2num(u8 hch, u8 lch); +extern u8 str_2char2num(u8 hch, u8 lch); +extern void macstr2num(u8 *dst, u8 *src); +extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); + +u32 rtw_rates[] = {1000000, 2000000, 5500000, 11000000, + 6000000, 9000000, 12000000, 18000000, 24000000, 36000000, 48000000, 54000000}; + +static const char *const iw_operation_mode[] = { + "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor" +}; + +static int hex2num_i(char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + return -1; +} + +static int hex2byte_i(const char *hex) +{ + int a, b; + a = hex2num_i(*hex++); + if (a < 0) + return -1; + b = hex2num_i(*hex++); + if (b < 0) + return -1; + return (a << 4) | b; +} + +/** + * hwaddr_aton - Convert ASCII string to MAC address + * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") + * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes) + * Returns: 0 on success, -1 on failure (e.g., string not a MAC address) + */ +static int hwaddr_aton_i(const char *txt, u8 *addr) +{ + int i; + + for (i = 0; i < 6; i++) { + int a, b; + + a = hex2num_i(*txt++); + if (a < 0) + return -1; + b = hex2num_i(*txt++); + if (b < 0) + return -1; + *addr++ = (a << 4) | b; + if (i < 5 && *txt++ != ':') + return -1; + } + + return 0; +} + + +void indicate_wx_scan_complete_event(_adapter *padapter) +{ + union iwreq_data wrqu; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); + + /* RTW_INFO("+rtw_indicate_wx_scan_complete_event\n"); */ + wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL); +} + +void rtw_indicate_wx_assoc_event(_adapter *padapter) +{ + union iwreq_data wrqu; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); + + _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); + + wrqu.ap_addr.sa_family = ARPHRD_ETHER; + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) + _rtw_memcpy(wrqu.ap_addr.sa_data, pnetwork->MacAddress, ETH_ALEN); + else + _rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN); + + RTW_PRINT("assoc success\n"); + wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); +} + +void rtw_indicate_wx_disassoc_event(_adapter *padapter) +{ + union iwreq_data wrqu; + + _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); + + wrqu.ap_addr.sa_family = ARPHRD_ETHER; + _rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN); + + RTW_PRINT("indicate disassoc\n"); + wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); +} + +/* +uint rtw_is_cckrates_included(u8 *rate) +{ + u32 i = 0; + + while(rate[i]!=0) + { + if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || + (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) + return _TRUE; + i++; + } + + return _FALSE; +} + +uint rtw_is_cckratesonly_included(u8 *rate) +{ + u32 i = 0; + + while(rate[i]!=0) + { + if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && + (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) + return _FALSE; + i++; + } + + return _TRUE; +} +*/ + +static int search_p2p_wfd_ie(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + if (SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type) { + + } else if ((SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type) || + (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type)) + { + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + u32 blnGotP2PIE = _FALSE; + + /* User is doing the P2P device discovery */ + /* The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. */ + /* If not, the driver should ignore this AP and go to the next AP. */ + + /* Verifying the SSID */ + if (_rtw_memcmp(pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN)) { + u32 p2pielen = 0; + + /* Verifying the P2P IE */ + if (rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen)) + blnGotP2PIE = _TRUE; + } + + if (blnGotP2PIE == _FALSE) + return _FALSE; + + } + } + + if (SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type) { + u32 blnGotWFD = _FALSE; + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK) { + /* the first two bits will indicate the WFD device type */ + if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_SOURCE) { + /* If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. */ + blnGotWFD = _TRUE; + } + } else if (pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE) { + /* the first two bits will indicate the WFD device type */ + if ((wfd_devinfo[1] & 0x03) == WFD_DEVINFO_PSINK) { + /* If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. */ + /* Todo: How about the SSink?! */ + blnGotWFD = _TRUE; + } + } + } + } + + if (blnGotWFD == _FALSE) + return _FALSE; + } + + return _TRUE; +} +static inline char *iwe_stream_mac_addr_proess(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + /* AP MAC address */ + iwe->cmd = SIOCGIWAP; + iwe->u.ap_addr.sa_family = ARPHRD_ETHER; + + _rtw_memcpy(iwe->u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN); + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_ADDR_LEN); + return start; +} +static inline char *iwe_stream_essid_proess(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + + /* Add the ESSID */ + iwe->cmd = SIOCGIWESSID; + iwe->u.data.flags = 1; + iwe->u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32); + start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid); + return start; +} + +static inline char *iwe_stream_chan_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + if (pnetwork->network.Configuration.DSConfig < 1 /*|| pnetwork->network.Configuration.DSConfig>14*/) + pnetwork->network.Configuration.DSConfig = 1; + + /* Add frequency/channel */ + iwe->cmd = SIOCGIWFREQ; + iwe->u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000; + iwe->u.freq.e = 1; + iwe->u.freq.i = pnetwork->network.Configuration.DSConfig; + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_FREQ_LEN); + return start; +} +static inline char *iwe_stream_mode_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe, u16 cap) +{ + /* Add mode */ + if (cap & (WLAN_CAPABILITY_IBSS | WLAN_CAPABILITY_BSS)) { + iwe->cmd = SIOCGIWMODE; + if (cap & WLAN_CAPABILITY_BSS) + iwe->u.mode = IW_MODE_MASTER; + else + iwe->u.mode = IW_MODE_ADHOC; + + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_UINT_LEN); + } + return start; +} +static inline char *iwe_stream_encryption_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe, u16 cap) +{ + + /* Add encryption capability */ + iwe->cmd = SIOCGIWENCODE; + if (cap & WLAN_CAPABILITY_PRIVACY) + iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + else + iwe->u.data.flags = IW_ENCODE_DISABLED; + iwe->u.data.length = 0; + start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid); + return start; + +} + +static inline char *iwe_stream_protocol_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + u16 ht_cap = _FALSE, vht_cap = _FALSE; + u32 ht_ielen = 0, vht_ielen = 0; + char *p; + u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); /* Probe Request */ + + /* parsing HT_CAP_IE */ + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); + if (p && ht_ielen > 0) + ht_cap = _TRUE; + + /* parsing VHT_CAP_IE */ + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); + if (p && vht_ielen > 0) + vht_cap = _TRUE; + /* Add the protocol name */ + iwe->cmd = SIOCGIWNAME; + if ((rtw_is_cckratesonly_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) { + if (ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bn"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11b"); + } else if ((rtw_is_cckrates_included((u8 *)&pnetwork->network.SupportedRates)) == _TRUE) { + if (ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bgn"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bg"); + } else { + if (pnetwork->network.Configuration.DSConfig > 14) { + if (vht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11AC"); + else + { + if (ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11an"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11a"); + } + } else { + if (ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11gn"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11g"); + } + } + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_CHAR_LEN); + return start; +} + +static inline char *iwe_stream_rate_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + u32 ht_ielen = 0, vht_ielen = 0; + char *p; + u16 max_rate = 0, rate, ht_cap = _FALSE, vht_cap = _FALSE; + u32 i = 0; + u8 bw_40MHz = 0, short_GI = 0, bw_160MHz = 0, vht_highest_rate = 0; + u16 mcs_rate = 0, vht_data_rate = 0; + char custom[MAX_CUSTOM_LEN] = {0}; + u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); /* Probe Request */ + + /* parsing HT_CAP_IE */ + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength - ie_offset); + if (p && ht_ielen > 0) { + struct rtw_ieee80211_ht_cap *pht_capie; + ht_cap = _TRUE; + pht_capie = (struct rtw_ieee80211_ht_cap *)(p + 2); + _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); + bw_40MHz = (pht_capie->cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ? 1 : 0; + short_GI = (pht_capie->cap_info & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) ? 1 : 0; + } + + /* parsing VHT_CAP_IE */ + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength - ie_offset); + if (p && vht_ielen > 0) { + u8 mcs_map[2]; + + vht_cap = _TRUE; + bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p + 2); + if (bw_160MHz) + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p + 2); + else + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p + 2); + + _rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p + 2), 2); + + vht_highest_rate = rtw_get_vht_highest_rate(mcs_map); + vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate); + } + + /*Add basic and extended rates */ + p = custom; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); + while (pnetwork->network.SupportedRates[i] != 0) { + rate = pnetwork->network.SupportedRates[i] & 0x7F; + if (rate > max_rate) + max_rate = rate; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), + "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); + i++; + } + if (vht_cap == _TRUE) + max_rate = vht_data_rate; + else + if (ht_cap == _TRUE) { + if (mcs_rate & 0x8000) /* MCS15 */ + max_rate = (bw_40MHz) ? ((short_GI) ? 300 : 270) : ((short_GI) ? 144 : 130); + + else if (mcs_rate & 0x0080) /* MCS7 */ + max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65); + else { /* default MCS7 */ + /* RTW_INFO("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); */ + max_rate = (bw_40MHz) ? ((short_GI) ? 150 : 135) : ((short_GI) ? 72 : 65); + } + + max_rate = max_rate * 2; /* Mbps/2; */ + } + + iwe->cmd = SIOCGIWRATE; + iwe->u.bitrate.fixed = iwe->u.bitrate.disabled = 0; + iwe->u.bitrate.value = max_rate * 500000; + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_PARAM_LEN); + return start ; +} + +static inline char *iwe_stream_wpa_wpa2_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + int buf_size = MAX_WPA_IE_LEN * 2; + /* u8 pbuf[buf_size]={0}; */ + u8 *pbuf = rtw_zmalloc(buf_size); + + u8 wpa_ie[255] = {0}, rsn_ie[255] = {0}; + u16 i, wpa_len = 0, rsn_len = 0; + u8 *p; + sint out_len = 0; + + if (pbuf) { + p = pbuf; + + /* parsing WPA/WPA2 IE */ + if (pnetwork->network.Reserved[0] != 2) { /* Probe Request */ + out_len = rtw_get_sec_ie(pnetwork->network.IEs , pnetwork->network.IELength, rsn_ie, &rsn_len, wpa_ie, &wpa_len); + + if (wpa_len > 0) { + + _rtw_memset(pbuf, 0, buf_size); + p += sprintf(p, "wpa_ie="); + for (i = 0; i < wpa_len; i++) + p += sprintf(p, "%02x", wpa_ie[i]); + + if (wpa_len > 100) { + printk("-----------------Len %d----------------\n", wpa_len); + for (i = 0; i < wpa_len; i++) + printk("%02x ", wpa_ie[i]); + printk("\n"); + printk("-----------------Len %d----------------\n", wpa_len); + } + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVCUSTOM; + iwe->u.data.length = strlen(pbuf); + start = iwe_stream_add_point(info, start, stop, iwe, pbuf); + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVGENIE; + iwe->u.data.length = wpa_len; + start = iwe_stream_add_point(info, start, stop, iwe, wpa_ie); + } + if (rsn_len > 0) { + + _rtw_memset(pbuf, 0, buf_size); + p += sprintf(p, "rsn_ie="); + for (i = 0; i < rsn_len; i++) + p += sprintf(p, "%02x", rsn_ie[i]); + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVCUSTOM; + iwe->u.data.length = strlen(pbuf); + start = iwe_stream_add_point(info, start, stop, iwe, pbuf); + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVGENIE; + iwe->u.data.length = rsn_len; + start = iwe_stream_add_point(info, start, stop, iwe, rsn_ie); + } + } + + rtw_mfree(pbuf, buf_size); + } + return start; +} + +static inline char *iwe_stream_wps_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + /* parsing WPS IE */ + uint cnt = 0, total_ielen; + u8 *wpsie_ptr = NULL; + uint wps_ielen = 0; + u8 ie_offset = (pnetwork->network.Reserved[0] == 2 ? 0 : 12); + + u8 *ie_ptr = pnetwork->network.IEs + ie_offset; + total_ielen = pnetwork->network.IELength - ie_offset; + + if (pnetwork->network.Reserved[0] == 2) { /* Probe Request */ + ie_ptr = pnetwork->network.IEs; + total_ielen = pnetwork->network.IELength; + } else { /* Beacon or Probe Respones */ + ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_; + total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_; + } + while (cnt < total_ielen) { + if (rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen > 2)) { + wpsie_ptr = &ie_ptr[cnt]; + iwe->cmd = IWEVGENIE; + iwe->u.data.length = (u16)wps_ielen; + start = iwe_stream_add_point(info, start, stop, iwe, wpsie_ptr); + } + cnt += ie_ptr[cnt + 1] + 2; /* goto next */ + } + return start; +} + +static inline char *iwe_stream_wapi_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + return start; +} + +static inline char *iwe_stream_rssi_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + u8 ss, sq; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + /* Add quality statistics */ + iwe->cmd = IWEVQUAL; + iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED + | IW_QUAL_NOISE_INVALID + ; + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { + ss = padapter->recvpriv.signal_strength; + sq = padapter->recvpriv.signal_qual; + } else { + ss = pnetwork->network.PhyInfo.SignalStrength; + sq = pnetwork->network.PhyInfo.SignalQuality; + } + + { + /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ + + HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); + + iwe->u.qual.level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, ss); + } + + iwe->u.qual.qual = (u8)sq; /* signal quality */ + + iwe->u.qual.noise = 0; /* noise level */ + + /* RTW_INFO("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); */ + + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_QUAL_LEN); + return start; +} + +static inline char *iwe_stream_net_rsv_process(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop, struct iw_event *iwe) +{ + u8 buf[32] = {0}; + u8 *p, *pos; + int len; + p = buf; + pos = pnetwork->network.Reserved; + + p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]); + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVCUSTOM; + iwe->u.data.length = strlen(buf); + start = iwe_stream_add_point(info, start, stop, iwe, buf); + return start; +} + +static char *translate_scan(_adapter *padapter, + struct iw_request_info *info, struct wlan_network *pnetwork, + char *start, char *stop) +{ + struct iw_event iwe; + u16 cap = 0; + _rtw_memset(&iwe, 0, sizeof(iwe)); + + if (_FALSE == search_p2p_wfd_ie(padapter, info, pnetwork, start, stop)) + return start; + + start = iwe_stream_mac_addr_proess(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_essid_proess(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_protocol_process(padapter, info, pnetwork, start, stop, &iwe); + if (pnetwork->network.Reserved[0] == 2) /* Probe Request */ + cap = 0; + else { + _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); + cap = le16_to_cpu(cap); + } + + start = iwe_stream_mode_process(padapter, info, pnetwork, start, stop, &iwe, cap); + start = iwe_stream_chan_process(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_encryption_process(padapter, info, pnetwork, start, stop, &iwe, cap); + start = iwe_stream_rate_process(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_wpa_wpa2_process(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_wps_process(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_wapi_process(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_rssi_process(padapter, info, pnetwork, start, stop, &iwe); + start = iwe_stream_net_rsv_process(padapter, info, pnetwork, start, stop, &iwe); + + return start; +} + +static int wpa_set_auth_algs(struct net_device *dev, u32 value) +{ + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + int ret = 0; + + if ((value & AUTH_ALG_SHARED_KEY) && (value & AUTH_ALG_OPEN_SYSTEM)) { + RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n", value); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; + } else if (value & AUTH_ALG_SHARED_KEY) { + RTW_INFO("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY [value:0x%x]\n", value); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; + } else if (value & AUTH_ALG_OPEN_SYSTEM) { + RTW_INFO("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n"); + /* padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; */ + if (padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) { + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; + } + + } else if (value & AUTH_ALG_LEAP) + RTW_INFO("wpa_set_auth_algs, AUTH_ALG_LEAP\n"); + else { + RTW_INFO("wpa_set_auth_algs, error!\n"); + ret = -EINVAL; + } + + return ret; + +} + +static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ + int ret = 0; + u32 wep_key_idx, wep_key_len, wep_total_len; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + + if (param_len < (u32)((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) { + ret = -EINVAL; + goto exit; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + + if (param->u.crypt.idx >= WEP_KEYS + ) { + ret = -EINVAL; + goto exit; + } + } else { + { + ret = -EINVAL; + goto exit; + } + } + + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + RTW_INFO("wpa_set_encryption, crypt.alg = WEP\n"); + + wep_key_idx = param->u.crypt.idx; + wep_key_len = param->u.crypt.key_len; + + if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) { + ret = -EINVAL; + goto exit; + } + + if (psecuritypriv->bWepDefaultKeyIdxSet == 0) { + /* wep default key has not been set, so use this key index as default key.*/ + + wep_key_len = wep_key_len <= 5 ? 5 : 13; + + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + + if (wep_key_len == 13) { + psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + + psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + } + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len); + + psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len; + + psecuritypriv->key_mask |= BIT(wep_key_idx); + + goto exit; + } + + if (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802_1x */ + struct sta_info *psta, *pbcmc_sta; + struct sta_priv *pstapriv = &padapter->stapriv; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) { /* sta mode */ + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) { + /* DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail\n")); */ + } else { + /* Jeff: don't disable ieee8021x_blocked while clearing key */ + if (strcmp(param->u.crypt.alg, "none") != 0) + psta->ieee8021x_blocked = _FALSE; + + if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + + if (param->u.crypt.set_tx == 1) { /* pairwise key */ + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + + if (strcmp(param->u.crypt.alg, "TKIP") == 0) { /* set mic key */ + /* DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + + padapter->securitypriv.busetkipkey = _FALSE; + } + + /* DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); */ + RTW_INFO(" ~~~~set sta key:unicastkey\n"); + + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); + + psta->bpairwise_key_installed = _TRUE; + + } else { /* group key */ + if (strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) { + _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, + (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + /* only TKIP group key need to install this */ + if (param->u.crypt.key_len > 16) { + _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + } + padapter->securitypriv.binstallGrpkey = _TRUE; + /* DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */ + if (param->u.crypt.idx < 4) { + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + _rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], + param->u.crypt.seq, 8); + } + + RTW_INFO(" ~~~~set sta key:groupkey\n"); + + padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; + + rtw_set_key(padapter, &padapter->securitypriv, param->u.crypt.idx, 1, _TRUE); + } + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) + rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); + + } + } + + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + if (pbcmc_sta == NULL) { + /* DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null\n")); */ + } else { + /* Jeff: don't disable ieee8021x_blocked while clearing key */ + if (strcmp(param->u.crypt.alg, "none") != 0) + pbcmc_sta->ieee8021x_blocked = _FALSE; + + if ((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled) || + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + } + } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { /* adhoc mode */ + } + } + +exit: + + return ret; +} + +static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) +{ + u8 *buf = NULL, *pos = NULL; + u32 left; + int group_cipher = 0, pairwise_cipher = 0; + int ret = 0; + u8 null_addr[] = {0, 0, 0, 0, 0, 0}; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + if ((ielen > MAX_WPA_IE_LEN) || (pie == NULL)) { + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); + if (pie == NULL) + return ret; + else + return -EINVAL; + } + + if (ielen) { + buf = rtw_zmalloc(ielen); + if (buf == NULL) { + ret = -ENOMEM; + goto exit; + } + + _rtw_memcpy(buf, pie , ielen); + + /* dump */ + { + int i; + RTW_INFO("\n wpa_ie(length:%d):\n", ielen); + for (i = 0; i < ielen; i = i + 8) + RTW_INFO("0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x\n", buf[i], buf[i + 1], buf[i + 2], buf[i + 3], buf[i + 4], buf[i + 5], buf[i + 6], buf[i + 7]); + } + + pos = buf; + if (ielen < RSN_HEADER_LEN) { + ret = -1; + goto exit; + } + + if (rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; + _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); + } + + if (rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) { + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; + _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); + } + + if (group_cipher == 0) + group_cipher = WPA_CIPHER_NONE; + if (pairwise_cipher == 0) + pairwise_cipher = WPA_CIPHER_NONE; + + switch (group_cipher) { + case WPA_CIPHER_NONE: + padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; + break; + case WPA_CIPHER_WEP40: + padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WPA_CIPHER_TKIP: + padapter->securitypriv.dot118021XGrpPrivacy = _TKIP_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case WPA_CIPHER_CCMP: + padapter->securitypriv.dot118021XGrpPrivacy = _AES_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + case WPA_CIPHER_WEP104: + padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + } + + switch (pairwise_cipher) { + case WPA_CIPHER_NONE: + padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; + break; + case WPA_CIPHER_WEP40: + padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WPA_CIPHER_TKIP: + padapter->securitypriv.dot11PrivacyAlgrthm = _TKIP_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case WPA_CIPHER_CCMP: + padapter->securitypriv.dot11PrivacyAlgrthm = _AES_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + case WPA_CIPHER_WEP104: + padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + } + + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); + {/* set wps_ie */ + u16 cnt = 0; + u8 eid, wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; + + while (cnt < ielen) { + eid = buf[cnt]; + + if ((eid == _VENDOR_SPECIFIC_IE_) && (_rtw_memcmp(&buf[cnt + 2], wps_oui, 4) == _TRUE)) { + RTW_INFO("SET WPS_IE\n"); + + padapter->securitypriv.wps_ie_len = ((buf[cnt + 1] + 2) < MAX_WPS_IE_LEN) ? (buf[cnt + 1] + 2) : MAX_WPS_IE_LEN; + + _rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len); + + set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) + rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING); + cnt += buf[cnt + 1] + 2; + + break; + } else { + cnt += buf[cnt + 1] + 2; /* goto next */ + } + } + } + } + + /* TKIP and AES disallow multicast packets until installing group key */ + if (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) + /* WPS open need to enable multicast + * || check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) */ + rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); + +exit: + + if (buf) + rtw_mfree(buf, ielen); + + return ret; +} + +static int rtw_wx_get_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u16 cap; + u32 ht_ielen = 0; + char *p; + u8 ht_cap = _FALSE, vht_cap = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + NDIS_802_11_RATES_EX *prates = NULL; + + if (check_fwstate(pmlmepriv, _FW_LINKED | WIFI_ADHOC_MASTER_STATE) == _TRUE) { + /* parsing HT_CAP_IE */ + p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength - 12); + if (p && ht_ielen > 0) + ht_cap = _TRUE; + + if (pmlmepriv->vhtpriv.vht_option == _TRUE) + vht_cap = _TRUE; + + prates = &pcur_bss->SupportedRates; + + if (rtw_is_cckratesonly_included((u8 *)prates) == _TRUE) { + if (ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b"); + } else if ((rtw_is_cckrates_included((u8 *)prates)) == _TRUE) { + if (ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg"); + } else { + if (pcur_bss->Configuration.DSConfig > 14) { + if (vht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11AC"); + else + { + if (ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a"); + } + } else { + if (ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); + } + } + } else { + /* prates = &padapter->registrypriv.dev_network.SupportedRates; */ + /* snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); */ + snprintf(wrqu->name, IFNAMSIZ, "unassociated"); + } + + return 0; +} + +static int rtw_wx_set_freq(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + int exp = 1, freq = 0, div = 0; + + if (wrqu->freq.m <= 1000) { + if (wrqu->freq.flags == IW_FREQ_AUTO) { + if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, wrqu->freq.m) > 0) { + padapter->mlmeextpriv.cur_channel = wrqu->freq.m; + RTW_INFO("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m); + } else { + padapter->mlmeextpriv.cur_channel = 1; + RTW_INFO("%s: channel is auto, Channel Plan don't match just set to channel 1\n", __func__); + } + } else { + padapter->mlmeextpriv.cur_channel = wrqu->freq.m; + RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); + } + } else { + while (wrqu->freq.e) { + exp *= 10; + wrqu->freq.e--; + } + + freq = wrqu->freq.m; + + while (!(freq % 10)) { + freq /= 10; + exp *= 10; + } + + /* freq unit is MHz here */ + div = 1000000 / exp; + + if (div) + freq /= div; + else { + div = exp / 1000000; + freq *= div; + } + + /* If freq is invalid, rtw_freq2ch() will return channel 1 */ + padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq); + RTW_INFO("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); + } + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ + set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + + return 0; +} + +static int rtw_wx_get_freq(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) { + + wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000; + wrqu->freq.e = 1; + wrqu->freq.i = pcur_bss->Configuration.DSConfig; + + } else { + wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000; + wrqu->freq.e = 1; + wrqu->freq.i = padapter->mlmeextpriv.cur_channel; + } + + return 0; +} + +static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ; + int ret = 0; + + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = -EPERM; + goto exit; + } + + if (!rtw_is_hw_init_completed(padapter)) { + ret = -EPERM; + goto exit; + } + + /* initial default type */ + dev->type = ARPHRD_ETHER; + + if (wrqu->mode == IW_MODE_MONITOR) { + rtw_ps_deny(padapter, PS_DENY_MONITOR_MODE); + LeaveAllPowerSaveMode(padapter); + } else { + rtw_ps_deny_cancel(padapter, PS_DENY_MONITOR_MODE); + } + + switch (wrqu->mode) { + case IW_MODE_MONITOR: + networkType = Ndis802_11Monitor; + dev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */ + RTW_INFO("set_mode = IW_MODE_MONITOR\n"); + break; + + case IW_MODE_AUTO: + networkType = Ndis802_11AutoUnknown; + RTW_INFO("set_mode = IW_MODE_AUTO\n"); + break; + case IW_MODE_ADHOC: + networkType = Ndis802_11IBSS; + RTW_INFO("set_mode = IW_MODE_ADHOC\n"); + break; + case IW_MODE_MASTER: + networkType = Ndis802_11APMode; + RTW_INFO("set_mode = IW_MODE_MASTER\n"); + /* rtw_setopmode_cmd(padapter, networkType,_TRUE); */ + break; + case IW_MODE_INFRA: + networkType = Ndis802_11Infrastructure; + RTW_INFO("set_mode = IW_MODE_INFRA\n"); + break; + + default: + ret = -EINVAL;; + goto exit; + } + + /* + if(Ndis802_11APMode == networkType) + { + rtw_setopmode_cmd(padapter, networkType,_TRUE); + } + else + { + rtw_setopmode_cmd(padapter, Ndis802_11AutoUnknown,_TRUE); + } + */ + + if (rtw_set_802_11_infrastructure_mode(padapter, networkType) == _FALSE) { + + ret = -EPERM; + goto exit; + + } + + rtw_setopmode_cmd(padapter, networkType, _TRUE); + + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) + rtw_indicate_connect(padapter); + +exit: + + return ret; + +} + +static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + wrqu->mode = IW_MODE_INFRA; + else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + + wrqu->mode = IW_MODE_ADHOC; + else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + wrqu->mode = IW_MODE_MASTER; + else if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) + wrqu->mode = IW_MODE_MONITOR; + else + wrqu->mode = IW_MODE_AUTO; + + return 0; + +} + +static int rtw_wx_set_pmkid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 j, blInserted = _FALSE; + int intReturn = _FALSE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct iw_pmksa *pPMK = (struct iw_pmksa *) extra; + u8 strZeroMacAddress[ETH_ALEN] = { 0x00 }; + u8 strIssueBssid[ETH_ALEN] = { 0x00 }; + + _rtw_memcpy(strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN); + if (pPMK->cmd == IW_PMKSA_ADD) { + RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n"); + if (_rtw_memcmp(strIssueBssid, strZeroMacAddress, ETH_ALEN) == _TRUE) + return intReturn ; + else + intReturn = _TRUE; + blInserted = _FALSE; + + /* overwrite PMKID */ + for (j = 0 ; j < NUM_PMKID_CACHE; j++) { + if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) { + /* BSSID is matched, the same AP => rewrite with new PMKID. */ + + RTW_INFO("[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n"); + + _rtw_memcpy(psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN); + psecuritypriv->PMKIDList[j].bUsed = _TRUE; + psecuritypriv->PMKIDIndex = j + 1; + blInserted = _TRUE; + break; + } + } + + if (!blInserted) { + /* Find a new entry */ + RTW_INFO("[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n", + psecuritypriv->PMKIDIndex); + + _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN); + _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN); + + psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE; + psecuritypriv->PMKIDIndex++ ; + if (psecuritypriv->PMKIDIndex == 16) + psecuritypriv->PMKIDIndex = 0; + } + } else if (pPMK->cmd == IW_PMKSA_REMOVE) { + RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n"); + intReturn = _TRUE; + for (j = 0 ; j < NUM_PMKID_CACHE; j++) { + if (_rtw_memcmp(psecuritypriv->PMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) == _TRUE) { + /* BSSID is matched, the same AP => Remove this PMKID information and reset it. */ + _rtw_memset(psecuritypriv->PMKIDList[j].Bssid, 0x00, ETH_ALEN); + psecuritypriv->PMKIDList[j].bUsed = _FALSE; + break; + } + } + } else if (pPMK->cmd == IW_PMKSA_FLUSH) { + RTW_INFO("[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n"); + _rtw_memset(&psecuritypriv->PMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE); + psecuritypriv->PMKIDIndex = 0; + intReturn = _TRUE; + } + return intReturn ; +} + +static int rtw_wx_get_sens(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + { + wrqu->sens.value = 0; + wrqu->sens.fixed = 0; /* no auto select */ + wrqu->sens.disabled = 1; + } + return 0; +} + +static int rtw_wx_get_range(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct iw_range *range = (struct iw_range *)extra; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + u16 val; + int i; + + wrqu->data.length = sizeof(*range); + _rtw_memset(range, 0, sizeof(*range)); + + /* Let's try to keep this struct in the same order as in + * linux/include/wireless.h + */ + + /* TODO: See what values we can set, and remove the ones we can't + * set, or fill them with some default data. + */ + + /* ~5 Mb/s real (802.11b) */ + range->throughput = 5 * 1000 * 1000; + + /* TODO: Not used in 802.11b? + * range->min_nwid; Minimal NWID we are able to set */ + /* TODO: Not used in 802.11b? + * range->max_nwid; Maximal NWID we are able to set */ + + /* Old Frequency (backward compat - moved lower ) */ + /* range->old_num_channels; + * range->old_num_frequency; + * range->old_freq[6]; Filler to keep "version" at the same offset */ + + /* signal level threshold range */ + + /* Quality of link & SNR stuff */ + /* Quality range (link, level, noise) + * If the quality is absolute, it will be in the range [0 ; max_qual], + * if the quality is dBm, it will be in the range [max_qual ; 0]. + * Don't forget that we use 8 bit arithmetics... + * + * If percentage range is 0~100 + * Signal strength dbm range logical is -100 ~ 0 + * but usually value is -90 ~ -20 + * When CONFIG_SIGNAL_SCALE_MAPPING is defined, dbm range is -95 ~ -45 + */ + range->max_qual.qual = 100; + /* percent values between 0 and 100. */ + range->max_qual.level = 100; + range->max_qual.noise = 100; + range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ + + /* This should contain the average/typical values of the quality + * indicator. This should be the threshold between a "good" and + * a "bad" link (example : monitor going from green to orange). + * Currently, user space apps like quality monitors don't have any + * way to calibrate the measurement. With this, they can split + * the range between 0 and max_qual in different quality level + * (using a geometric subdivision centered on the average). + * I expect that people doing the user space apps will feedback + * us on which value we need to put in each driver... */ + range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */ + /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ + range->avg_qual.level = 30; + range->avg_qual.noise = 100; + range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ + + range->num_bitrates = RATE_COUNT; + + for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) + range->bitrate[i] = rtw_rates[i]; + + range->min_frag = MIN_FRAG_THRESHOLD; + range->max_frag = MAX_FRAG_THRESHOLD; + + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 16; + + /* range->retry_capa; What retry options are supported + * range->retry_flags; How to decode max/min retry limit + * range->r_time_flags; How to decode max/min retry life + * range->min_retry; Minimal number of retries + * range->max_retry; Maximal number of retries + * range->min_r_time; Minimal retry lifetime + * range->max_r_time; Maximal retry lifetime */ + + for (i = 0, val = 0; i < pmlmeext->max_chan_nums; i++) { + + /* Include only legal frequencies for some countries */ + if (pmlmeext->channel_set[i].ChannelNum != 0) { + range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; + range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; + range->freq[val].e = 1; + val++; + } + + if (val == IW_MAX_FREQUENCIES) + break; + } + + range->num_channels = val; + range->num_frequency = val; + + /* Commented by Albert 2009/10/13 + * The following code will proivde the security capability to network manager. + * If the driver doesn't provide this capability to network manager, + * the WPA/WPA2 routers can't be choosen in the network manager. */ + + /* + #define IW_SCAN_CAPA_NONE 0x00 + #define IW_SCAN_CAPA_ESSID 0x01 + #define IW_SCAN_CAPA_BSSID 0x02 + #define IW_SCAN_CAPA_CHANNEL 0x04 + #define IW_SCAN_CAPA_MODE 0x08 + #define IW_SCAN_CAPA_RATE 0x10 + #define IW_SCAN_CAPA_TYPE 0x20 + #define IW_SCAN_CAPA_TIME 0x40 + */ + + range->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 | + IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP; + +#ifdef IW_SCAN_CAPA_ESSID /* WIRELESS_EXT > 21 */ + range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE | IW_SCAN_CAPA_BSSID | + IW_SCAN_CAPA_CHANNEL | IW_SCAN_CAPA_MODE | IW_SCAN_CAPA_RATE; +#endif + + return 0; + +} + +/* set bssid flow + * s1. rtw_set_802_11_infrastructure_mode() + * s2. rtw_set_802_11_authentication_mode() + * s3. set_802_11_encryption_mode() + * s4. rtw_set_802_11_bssid() */ +static int rtw_wx_set_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ + _irqL irqL; + uint ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct sockaddr *temp = (struct sockaddr *)awrq; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _list *phead; + u8 *dst_bssid, *src_bssid; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + NDIS_802_11_AUTHENTICATION_MODE authmode; + + rtw_ps_deny(padapter, PS_DENY_JOIN); + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = -1; + goto cancel_ps_deny; + } + + if (!padapter->bup) { + ret = -1; + goto cancel_ps_deny; + } + + if (temp->sa_family != ARPHRD_ETHER) { + ret = -EINVAL; + goto cancel_ps_deny; + } + + authmode = padapter->securitypriv.ndisauthtype; + _enter_critical_bh(&queue->lock, &irqL); + phead = get_list_head(queue); + pmlmepriv->pscanned = get_next(phead); + + while (1) { + if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); + + pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); + + dst_bssid = pnetwork->network.MacAddress; + + src_bssid = temp->sa_data; + + if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) { + if (!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode)) { + ret = -1; + _exit_critical_bh(&queue->lock, &irqL); + goto cancel_ps_deny; + } + + break; + } + + } + _exit_critical_bh(&queue->lock, &irqL); + + rtw_set_802_11_authentication_mode(padapter, authmode); + /* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */ + if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) { + ret = -1; + goto cancel_ps_deny; + } + +cancel_ps_deny: + rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); + + return ret; +} + +static int rtw_wx_get_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + + wrqu->ap_addr.sa_family = ARPHRD_ETHER; + + _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); + + if (((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) || + ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) || + ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE)) + + _rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN); + else + _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); + + return 0; + +} + +static int rtw_wx_set_mlme(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + u16 reason; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_mlme *mlme = (struct iw_mlme *) extra; + + if (mlme == NULL) + return -1; + + RTW_INFO("%s\n", __FUNCTION__); + + reason = cpu_to_le16(mlme->reason_code); + + RTW_INFO("%s, cmd=%d, reason=%d\n", __FUNCTION__, mlme->cmd, reason); + + switch (mlme->cmd) { + case IW_MLME_DEAUTH: + if (!rtw_set_802_11_disassociate(padapter)) + ret = -1; + break; + + case IW_MLME_DISASSOC: + if (!rtw_set_802_11_disassociate(padapter)) + ret = -1; + + break; + + default: + return -EOPNOTSUPP; + } + + return ret; +} + +static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + u8 _status = _FALSE; + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + + if (rtw_mi_mp_mode_check(padapter)) { + RTW_INFO("MP mode block Scan request\n"); + ret = -EPERM; + goto exit; + } + if (rtw_is_scan_deny(padapter)) { + indicate_wx_scan_complete_event(padapter); + goto exit; + } + + rtw_ps_deny(padapter, PS_DENY_SCAN); + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = -1; + goto cancel_ps_deny; + } + + if (!rtw_is_adapter_up(padapter)) { + ret = -1; + goto cancel_ps_deny; + } + +#ifndef CONFIG_DOSCAN_IN_BUSYTRAFFIC + /* When Busy Traffic, driver do not site survey. So driver return success. */ + /* wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. */ + /* modify by thomas 2011-02-22. */ + if (rtw_mi_busy_traffic_check(padapter, _FALSE)) { + indicate_wx_scan_complete_event(padapter); + goto cancel_ps_deny; + } +#endif + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) && check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) { + RTW_INFO("AP mode process WPS\n"); + indicate_wx_scan_complete_event(padapter); + goto cancel_ps_deny; + } + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) == _TRUE) { + indicate_wx_scan_complete_event(padapter); + goto cancel_ps_deny; + } + + + if (pwdinfo->p2p_state != P2P_STATE_NONE) { + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL); + rtw_free_network_queue(padapter, _TRUE); + } + + _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID) * RTW_SSID_SCAN_AMOUNT); + + if (wrqu->data.length == sizeof(struct iw_scan_req)) { + struct iw_scan_req *req = (struct iw_scan_req *)extra; + + if (wrqu->data.flags & IW_SCAN_THIS_ESSID) { + int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE); + + _rtw_memcpy(ssid[0].Ssid, req->essid, len); + ssid[0].SsidLength = len; + + RTW_INFO("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len); + + _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, 1, NULL, 0); + + } else if (req->scan_type == IW_SCAN_TYPE_PASSIVE) + RTW_INFO("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n"); + + } else + + if (wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE + && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE + ) { + int len = wrqu->data.length - WEXT_CSCAN_HEADER_SIZE; + char *pos = extra + WEXT_CSCAN_HEADER_SIZE; + char section; + char sec_len; + int ssid_index = 0; + + /* RTW_INFO("%s COMBO_SCAN header is recognized\n", __FUNCTION__); */ + + while (len >= 1) { + section = *(pos++); + len -= 1; + + switch (section) { + case WEXT_CSCAN_SSID_SECTION: + /* RTW_INFO("WEXT_CSCAN_SSID_SECTION\n"); */ + if (len < 1) { + len = 0; + break; + } + + sec_len = *(pos++); + len -= 1; + + if (sec_len > 0 && sec_len <= len) { + ssid[ssid_index].SsidLength = sec_len; + _rtw_memcpy(ssid[ssid_index].Ssid, pos, ssid[ssid_index].SsidLength); + /* RTW_INFO("%s COMBO_SCAN with specific ssid:%s, %d\n", __FUNCTION__ */ + /* , ssid[ssid_index].Ssid, ssid[ssid_index].SsidLength); */ + ssid_index++; + } + + pos += sec_len; + len -= sec_len; + break; + + case WEXT_CSCAN_CHANNEL_SECTION: + /* RTW_INFO("WEXT_CSCAN_CHANNEL_SECTION\n"); */ + pos += 1; + len -= 1; + break; + case WEXT_CSCAN_ACTV_DWELL_SECTION: + /* RTW_INFO("WEXT_CSCAN_ACTV_DWELL_SECTION\n"); */ + pos += 2; + len -= 2; + break; + case WEXT_CSCAN_PASV_DWELL_SECTION: + /* RTW_INFO("WEXT_CSCAN_PASV_DWELL_SECTION\n"); */ + pos += 2; + len -= 2; + break; + case WEXT_CSCAN_HOME_DWELL_SECTION: + /* RTW_INFO("WEXT_CSCAN_HOME_DWELL_SECTION\n"); */ + pos += 2; + len -= 2; + break; + case WEXT_CSCAN_TYPE_SECTION: + /* RTW_INFO("WEXT_CSCAN_TYPE_SECTION\n"); */ + pos += 1; + len -= 1; + break; + + default: + /* RTW_INFO("Unknown CSCAN section %c\n", section); */ + len = 0; /* stop parsing */ + } + /* RTW_INFO("len:%d\n", len); */ + + } + + /* jeff: it has still some scan paramater to parse, we only do this now... */ + _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, RTW_SSID_SCAN_AMOUNT, NULL, 0); + + } else + + _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0, NULL, 0); + + if (_status == _FALSE) + ret = -1; + +cancel_ps_deny: + rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); + +exit: + + return ret; +} + +static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + _irqL irqL; + _list *plist, *phead; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + char *ev = extra; + char *stop = ev + wrqu->data.length; + u32 ret = 0; + u32 cnt = 0; + u32 wait_for_surveydone; + sint wait_status; + + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + + if (adapter_to_pwrctl(padapter)->brfoffbyhw && rtw_is_drv_stopped(padapter)) { + ret = -EINVAL; + goto exit; + } + + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + wait_for_surveydone = 200; + else { + /* P2P is disabled */ + wait_for_surveydone = 100; + } + + wait_status = _FW_UNDER_SURVEY + | _FW_UNDER_LINKING + ; + + while (check_fwstate(pmlmepriv, wait_status) == _TRUE) + return -EAGAIN; + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + if ((stop - ev) < SCAN_ITEM_SIZE) { + ret = -E2BIG; + break; + } + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + /* report network only if the current channel set contains the channel to which this network belongs */ + if (rtw_chset_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) + ) + ev = translate_scan(padapter, a, pnetwork, ev, stop); + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + wrqu->data.length = ev - extra; + wrqu->data.flags = 0; + +exit: + + + return ret ; + +} + +/* set ssid flow + * s1. rtw_set_802_11_infrastructure_mode() + * s2. set_802_11_authenticaion_mode() + * s3. set_802_11_encryption_mode() + * s4. rtw_set_802_11_ssid() */ +static int rtw_wx_set_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + _irqL irqL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _queue *queue = &pmlmepriv->scanned_queue; + _list *phead; + s8 status = _TRUE; + struct wlan_network *pnetwork = NULL; + NDIS_802_11_AUTHENTICATION_MODE authmode; + NDIS_802_11_SSID ndis_ssid; + u8 *dst_ssid, *src_ssid; + + uint ret = 0, len; + +#ifdef CONFIG_WEXT_DONT_JOIN_BYSSID + RTW_INFO("%s: CONFIG_WEXT_DONT_JOIN_BYSSID be defined!! only allow bssid joining\n", __func__); + return -EPERM; +#endif + + if (wrqu->essid.length > IW_ESSID_MAX_SIZE) { + ret = -E2BIG; + goto exit; + } + + rtw_ps_deny(padapter, PS_DENY_JOIN); + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = -1; + goto cancel_ps_deny; + } + + if (!padapter->bup) { + ret = -1; + goto cancel_ps_deny; + } + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + ret = -1; + goto cancel_ps_deny; + } + + authmode = padapter->securitypriv.ndisauthtype; + RTW_INFO("=>%s\n", __FUNCTION__); + if (wrqu->essid.flags && wrqu->essid.length) { + /* Commented by Albert 20100519 */ + /* We got the codes in "set_info" function of iwconfig source code. */ + /* ========================================= */ + /* wrq.u.essid.length = strlen(essid) + 1; */ + /* if(we_kernel_version > 20) */ + /* wrq.u.essid.length--; */ + /* ========================================= */ + /* That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. */ + len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE; + + if (wrqu->essid.length != 33) + RTW_INFO("ssid=%s, len=%d\n", extra, wrqu->essid.length); + + _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); + ndis_ssid.SsidLength = len; + _rtw_memcpy(ndis_ssid.Ssid, extra, len); + src_ssid = ndis_ssid.Ssid; + + _enter_critical_bh(&queue->lock, &irqL); + phead = get_list_head(queue); + pmlmepriv->pscanned = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); + + pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); + + dst_ssid = pnetwork->network.Ssid.Ssid; + + if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) && + (pnetwork->network.Ssid.SsidLength == ndis_ssid.SsidLength)) { + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) { + if (pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) + continue; + } + + if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) { + ret = -1; + _exit_critical_bh(&queue->lock, &irqL); + goto cancel_ps_deny; + } + + break; + } + } + _exit_critical_bh(&queue->lock, &irqL); + rtw_set_802_11_authentication_mode(padapter, authmode); + /* set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */ + if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { + ret = -1; + goto cancel_ps_deny; + } + } + +cancel_ps_deny: + rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); + +exit: + RTW_INFO("<=%s, ret %d\n", __FUNCTION__, ret); + + + return ret; +} + +static int rtw_wx_get_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + u32 len, ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + len = pcur_bss->Ssid.SsidLength; + + wrqu->essid.length = len; + + _rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len); + + wrqu->essid.flags = 1; + } else { + ret = -1; + goto exit; + } + +exit: + + return ret; + +} + +static int rtw_wx_set_rate(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + int i, ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 datarates[NumRates]; + u32 target_rate = wrqu->bitrate.value; + u32 fixed = wrqu->bitrate.fixed; + u32 ratevalue = 0; + u8 mpdatarate[NumRates] = {11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff}; + + if (target_rate == -1) { + ratevalue = 11; + goto set_rate; + } + target_rate = target_rate / 100000; + + switch (target_rate) { + case 10: + ratevalue = 0; + break; + case 20: + ratevalue = 1; + break; + case 55: + ratevalue = 2; + break; + case 60: + ratevalue = 3; + break; + case 90: + ratevalue = 4; + break; + case 110: + ratevalue = 5; + break; + case 120: + ratevalue = 6; + break; + case 180: + ratevalue = 7; + break; + case 240: + ratevalue = 8; + break; + case 360: + ratevalue = 9; + break; + case 480: + ratevalue = 10; + break; + case 540: + ratevalue = 11; + break; + default: + ratevalue = 11; + break; + } + +set_rate: + + for (i = 0; i < NumRates; i++) { + if (ratevalue == mpdatarate[i]) { + datarates[i] = mpdatarate[i]; + if (fixed == 0) + break; + } else + datarates[i] = 0xff; + + } + + if (rtw_setdatarate_cmd(padapter, datarates) != _SUCCESS) { + ret = -1; + } + + return ret; +} + +static int rtw_wx_get_rate(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + u16 max_rate = 0; + + max_rate = rtw_get_cur_max_rate((_adapter *)rtw_netdev_priv(dev)); + + if (max_rate == 0) + return -EPERM; + + wrqu->bitrate.fixed = 0; /* no auto select */ + wrqu->bitrate.value = max_rate * 100000; + + return 0; +} + +static int rtw_wx_set_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if (wrqu->rts.disabled) + padapter->registrypriv.rts_thresh = 2347; + else { + if (wrqu->rts.value < 0 || + wrqu->rts.value > 2347) + return -EINVAL; + + padapter->registrypriv.rts_thresh = wrqu->rts.value; + } + + RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); + + return 0; + +} + +static int rtw_wx_get_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_INFO("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); + + wrqu->rts.value = padapter->registrypriv.rts_thresh; + wrqu->rts.fixed = 0; /* no auto select */ + /* wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); */ + + return 0; +} + +static int rtw_wx_set_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if (wrqu->frag.disabled) + padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD; + else { + if (wrqu->frag.value < MIN_FRAG_THRESHOLD || + wrqu->frag.value > MAX_FRAG_THRESHOLD) + return -EINVAL; + + padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1; + } + + RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); + + return 0; + +} + +static int rtw_wx_get_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_INFO("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); + + wrqu->frag.value = padapter->xmitpriv.frag_len; + wrqu->frag.fixed = 0; /* no auto select */ + /* wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); */ + + return 0; +} + +static int rtw_wx_get_retry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + /* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */ + + wrqu->retry.value = 7; + wrqu->retry.fixed = 0; /* no auto select */ + wrqu->retry.disabled = 1; + + return 0; + +} + +static int rtw_wx_set_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ + u32 key, ret = 0; + u32 keyindex_provided; + NDIS_802_11_WEP wep; + NDIS_802_11_AUTHENTICATION_MODE authmode; + + struct iw_point *erq = &(wrqu->encoding); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + RTW_INFO("+rtw_wx_set_enc, flags=0x%x\n", erq->flags); + + _rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP)); + + key = erq->flags & IW_ENCODE_INDEX; + + if (erq->flags & IW_ENCODE_DISABLED) { + RTW_INFO("EncryptionDisabled\n"); + padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; + padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */ + authmode = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisauthtype = authmode; + + goto exit; + } + + if (key) { + if (key > WEP_KEYS) + return -EINVAL; + key--; + keyindex_provided = 1; + } else { + keyindex_provided = 0; + key = padapter->securitypriv.dot11PrivacyKeyIndex; + RTW_INFO("rtw_wx_set_enc, key=%d\n", key); + } + + /* set authentication mode */ + if (erq->flags & IW_ENCODE_OPEN) { + RTW_INFO("rtw_wx_set_enc():IW_ENCODE_OPEN\n"); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */ + + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; + + padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_; + authmode = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisauthtype = authmode; + } else if (erq->flags & IW_ENCODE_RESTRICTED) { + RTW_INFO("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n"); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; + + padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_; + padapter->securitypriv.dot118021XGrpPrivacy = _WEP40_; + authmode = Ndis802_11AuthModeShared; + padapter->securitypriv.ndisauthtype = authmode; + } else { + RTW_INFO("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags); + + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;/* Ndis802_11EncryptionDisabled; */ + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */ + padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_; + authmode = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisauthtype = authmode; + } + + wep.KeyIndex = key; + if (erq->length > 0) { + wep.KeyLength = erq->length <= 5 ? 5 : 13; + + wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); + } else { + wep.KeyLength = 0 ; + + if (keyindex_provided == 1) { /* set key_id only, no given KeyMaterial(erq->length==0). */ + padapter->securitypriv.dot11PrivacyKeyIndex = key; + + RTW_INFO("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]); + + switch (padapter->securitypriv.dot11DefKeylen[key]) { + case 5: + padapter->securitypriv.dot11PrivacyAlgrthm = _WEP40_; + break; + case 13: + padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_; + break; + default: + padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; + break; + } + + goto exit; + + } + + } + + wep.KeyIndex |= 0x80000000; + + _rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength); + + if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) { + if (rf_on == pwrpriv->rf_pwrstate) + ret = -EOPNOTSUPP; + goto exit; + } + +exit: + + return ret; + +} + +static int rtw_wx_get_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ + uint key, ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *erq = &(wrqu->encoding); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) { + if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) { + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + return 0; + } + } + + key = erq->flags & IW_ENCODE_INDEX; + + if (key) { + if (key > WEP_KEYS) + return -EINVAL; + key--; + } else + key = padapter->securitypriv.dot11PrivacyKeyIndex; + + erq->flags = key + 1; + + /* if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) */ + /* { */ + /* erq->flags |= IW_ENCODE_OPEN; */ + /* } */ + + switch (padapter->securitypriv.ndisencryptstatus) { + case Ndis802_11EncryptionNotSupported: + case Ndis802_11EncryptionDisabled: + + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + + break; + + case Ndis802_11Encryption1Enabled: + + erq->length = padapter->securitypriv.dot11DefKeylen[key]; + + if (erq->length) { + _rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]); + + erq->flags |= IW_ENCODE_ENABLED; + + if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) + erq->flags |= IW_ENCODE_OPEN; + else if (padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared) + erq->flags |= IW_ENCODE_RESTRICTED; + } else { + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + } + + break; + + case Ndis802_11Encryption2Enabled: + case Ndis802_11Encryption3Enabled: + + erq->length = 16; + erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY); + + break; + + default: + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + + break; + + } + + return ret; + +} + +static int rtw_wx_get_power(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + /* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */ + + wrqu->power.value = 0; + wrqu->power.fixed = 0; /* no auto select */ + wrqu->power.disabled = 1; + + return 0; + +} + +static int rtw_wx_set_gen_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length); + + return ret; +} + +static int rtw_wx_set_auth(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_param *param = (struct iw_param *)&(wrqu->param); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u32 value = param->value; + int ret = 0; + + switch (param->flags & IW_AUTH_INDEX) { + + case IW_AUTH_WPA_VERSION: + break; + case IW_AUTH_CIPHER_PAIRWISE: + + break; + case IW_AUTH_CIPHER_GROUP: + + break; + case IW_AUTH_KEY_MGMT: + /* + * ??? does not use these parameters + */ + break; + + case IW_AUTH_TKIP_COUNTERMEASURES: { + if (param->value) { + /* wpa_supplicant is enabling the tkip countermeasure. */ + padapter->securitypriv.btkip_countermeasure = _TRUE; + } else { + /* wpa_supplicant is disabling the tkip countermeasure. */ + padapter->securitypriv.btkip_countermeasure = _FALSE; + } + break; + } + case IW_AUTH_DROP_UNENCRYPTED: { + /* HACK: + * + * wpa_supplicant calls set_wpa_enabled when the driver + * is loaded and unloaded, regardless of if WPA is being + * used. No other calls are made which can be used to + * determine if encryption will be used or not prior to + * association being expected. If encryption is not being + * used, drop_unencrypted is set to false, else true -- we + * can use this to determine if the CAP_PRIVACY_ON bit should + * be set. + */ + + if (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) { + break;/* it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, */ + /* then it needn't reset it; */ + } + + if (param->value) { + padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; + padapter->securitypriv.dot11PrivacyAlgrthm = _NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy = _NO_PRIVACY_; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */ + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; + } + + break; + } + + case IW_AUTH_80211_AUTH_ALG: + + /* + * It's the starting point of a link layer connection using wpa_supplicant + */ + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { + LeaveAllPowerSaveMode(padapter); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); + RTW_INFO("%s...call rtw_indicate_disconnect\n ", __FUNCTION__); + rtw_indicate_disconnect(padapter, 0, _FALSE); + rtw_free_assoc_resources(padapter, 1); + } + + ret = wpa_set_auth_algs(dev, (u32)param->value); + + break; + + case IW_AUTH_WPA_ENABLED: + + /* if(param->value) */ + /* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; */ /* 802.1x */ + /* else */ + /* padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; */ /* open system */ + + /* _disassociate(priv); */ + + break; + + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + /* ieee->ieee802_1x = param->value; */ + break; + + case IW_AUTH_PRIVACY_INVOKED: + /* ieee->privacy_invoked = param->value; */ + break; + + default: + return -EOPNOTSUPP; + + } + + return ret; + +} + +static int rtw_wx_set_enc_ext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *alg_name; + u32 param_len; + struct ieee_param *param = NULL; + struct iw_point *pencoding = &wrqu->encoding; + struct iw_encode_ext *pext = (struct iw_encode_ext *)extra; + int ret = 0; + + param_len = sizeof(struct ieee_param) + pext->key_len; + param = (struct ieee_param *)rtw_malloc(param_len); + if (param == NULL) + return -1; + + _rtw_memset(param, 0, param_len); + + param->cmd = IEEE_CMD_SET_ENCRYPTION; + _rtw_memset(param->sta_addr, 0xff, ETH_ALEN); + + switch (pext->alg) { + case IW_ENCODE_ALG_NONE: + /* todo: remove key */ + /* remove = 1; */ + alg_name = "none"; + break; + case IW_ENCODE_ALG_WEP: + alg_name = "WEP"; + break; + case IW_ENCODE_ALG_TKIP: + alg_name = "TKIP"; + break; + case IW_ENCODE_ALG_CCMP: + alg_name = "CCMP"; + break; + default: + ret = -1; + goto exit; + } + + strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); + + if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) + param->u.crypt.set_tx = 1; + + /* cliW: WEP does not have group key + * just not checking GROUP key setting + */ + if ((pext->alg != IW_ENCODE_ALG_WEP) && + ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) + )) + param->u.crypt.set_tx = 0; + + param->u.crypt.idx = (pencoding->flags & 0x00FF) - 1 ; + + if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) { + _rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8); + } + + if (pext->key_len) { + param->u.crypt.key_len = pext->key_len; + /* _rtw_memcpy(param + 1, pext + 1, pext->key_len); */ + _rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len); + } + + if (pencoding->flags & IW_ENCODE_DISABLED) { + /* todo: remove key */ + /* remove = 1; */ + } + + ret = wpa_set_encryption(dev, param, param_len); + +exit: + if (param) + rtw_mfree((u8 *)param, param_len); + + return ret; +} + +static int rtw_wx_get_nick(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + if (extra) { + wrqu->data.length = 14; + wrqu->data.flags = 1; + _rtw_memcpy(extra, "<WIFI@REALTEK>", 14); + } + + return 0; + +} + +static int rtw_wx_read32(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter; + struct iw_point *p; + u16 len; + u32 addr; + u32 data32; + u32 bytes; + u8 *ptmp; + int ret; + + ret = 0; + padapter = (PADAPTER)rtw_netdev_priv(dev); + p = &wrqu->data; + len = p->length; + if (0 == len) + return -EINVAL; + + ptmp = (u8 *)rtw_malloc(len); + if (NULL == ptmp) + return -ENOMEM; + + if (copy_from_user(ptmp, p->pointer, len)) { + ret = -EFAULT; + goto exit; + } + + bytes = 0; + addr = 0; + sscanf(ptmp, "%d,%x", &bytes, &addr); + + switch (bytes) { + case 1: + data32 = rtw_read8(padapter, addr); + sprintf(extra, "0x%02X", data32); + break; + case 2: + data32 = rtw_read16(padapter, addr); + sprintf(extra, "0x%04X", data32); + break; + case 4: + data32 = rtw_read32(padapter, addr); + sprintf(extra, "0x%08X", data32); + break; + + default: + RTW_INFO("%s: usage> read [bytes],[address(hex)]\n", __func__); + ret = -EINVAL; + goto exit; + } + RTW_INFO("%s: addr=0x%08X data=%s\n", __func__, addr, extra); + +exit: + rtw_mfree(ptmp, len); + + return 0; +} + +static int rtw_wx_write32(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); + + u32 addr; + u32 data32; + u32 bytes; + + bytes = 0; + addr = 0; + data32 = 0; + sscanf(extra, "%d,%x,%x", &bytes, &addr, &data32); + + switch (bytes) { + case 1: + rtw_write8(padapter, addr, (u8)data32); + RTW_INFO("%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32); + break; + case 2: + rtw_write16(padapter, addr, (u16)data32); + RTW_INFO("%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32); + break; + case 4: + rtw_write32(padapter, addr, data32); + RTW_INFO("%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32); + break; + default: + RTW_INFO("%s: usage> write [bytes],[address(hex)],[data(hex)]\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int rtw_wx_read_rf(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u32 path, addr, data32; + + path = *(u32 *)extra; + addr = *((u32 *)extra + 1); + data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF); + /* RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */ + /* + * IMPORTANT!! + * Only when wireless private ioctl is at odd order, + * "extra" would be copied to user space. + */ + sprintf(extra, "0x%05x", data32); + + return 0; +} + +static int rtw_wx_write_rf(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u32 path, addr, data32; + + path = *(u32 *)extra; + addr = *((u32 *)extra + 1); + data32 = *((u32 *)extra + 2); + /* RTW_INFO("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); */ + rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32); + + return 0; +} + +static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + return -1; +} + +static int dummy(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + /* _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); */ + /* struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); */ + + /* RTW_INFO("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv)); */ + + return -1; + +} + +static int rtw_wx_set_channel_plan(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 channel_plan_req = (u8)(*((int *)wrqu)); + + if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req)) + return -EPERM; + + return 0; +} + +static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + return 0; +} + +static int rtw_wx_get_sensitivity(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *buf) +{ + return 0; +} + +static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + return 0; +} + +/* +typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +*/ +/* + * For all data larger than 16 octets, we need to use a + * pointer to memory allocated in user space. + */ +static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + return 0; +} + +static int rtw_get_ap_info(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int bssid_match, ret = 0; + u32 cnt = 0, wpa_ielen; + _irqL irqL; + _list *plist, *phead; + unsigned char *pbuf; + u8 bssid[ETH_ALEN]; + char data[32]; + struct wlan_network *pnetwork = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct iw_point *pdata = &wrqu->data; + + RTW_INFO("+rtw_get_aplist_info\n"); + + if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) { + ret = -EINVAL; + goto exit; + } + + while ((check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING))) == _TRUE) { + rtw_msleep_os(30); + cnt++; + if (cnt > 100) + break; + } + + /* pdata->length = 0; */ /* ? */ + pdata->flags = 0; + if (pdata->length >= 32) { + if (copy_from_user(data, pdata->pointer, 32)) { + ret = -EINVAL; + goto exit; + } + } else { + ret = -EINVAL; + goto exit; + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + /* if(hwaddr_aton_i(pdata->pointer, bssid)) */ + if (hwaddr_aton_i(data, bssid)) { + RTW_INFO("Invalid BSSID '%s'.\n", (u8 *)data); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + return -EINVAL; + } + + if (_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) { /* BSSID match, then check if supporting wpa/wpa2 */ + RTW_INFO("BSSID:" MAC_FMT "\n", MAC_ARG(bssid)); + + pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); + if (pbuf && (wpa_ielen > 0)) { + pdata->flags = 1; + break; + } + + pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength - 12); + if (pbuf && (wpa_ielen > 0)) { + pdata->flags = 2; + break; + } + + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (pdata->length >= 34) { + if (copy_to_user((u8 *)pdata->pointer + 32, (u8 *)&pdata->flags, 1)) { + ret = -EINVAL; + goto exit; + } + } + +exit: + + return ret; + +} + +static int rtw_set_pid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = rtw_netdev_priv(dev); + int *pdata = (int *)wrqu; + int selector; + + if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) { + ret = -EINVAL; + goto exit; + } + + selector = *pdata; + if (selector < 3 && selector >= 0) { + padapter->pid[selector] = *(pdata + 1); + ui_pid[selector] = *(pdata + 1); + RTW_INFO("%s set pid[%d]=%d\n", __FUNCTION__, selector , padapter->pid[selector]); + } else + RTW_INFO("%s selector %d error\n", __FUNCTION__, selector); + +exit: + + return ret; + +} + +static int rtw_wps_start(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + u32 u32wps_start = 0; + unsigned int uintRet = 0; + + if (RTW_CANNOT_RUN(padapter) || (NULL == pdata)) { + ret = -EINVAL; + goto exit; + } + + uintRet = copy_from_user((void *) &u32wps_start, pdata->pointer, 4); + if (u32wps_start == 0) + u32wps_start = *extra; + + RTW_INFO("[%s] wps_start = %d\n", __FUNCTION__, u32wps_start); + + if (u32wps_start == 1) /* WPS Start */ + rtw_led_control(padapter, LED_CTL_START_WPS); + else if (u32wps_start == 2) /* WPS Stop because of wps success */ + rtw_led_control(padapter, LED_CTL_STOP_WPS); + else if (u32wps_start == 3) /* WPS Stop because of wps fail */ + rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL); + +exit: + + return ret; + +} + +static int rtw_wext_p2p_enable(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + enum P2P_ROLE init_role = P2P_ROLE_DISABLE; + + if (*extra == '0') + init_role = P2P_ROLE_DISABLE; + else if (*extra == '1') + init_role = P2P_ROLE_DEVICE; + else if (*extra == '2') + init_role = P2P_ROLE_CLIENT; + else if (*extra == '3') + init_role = P2P_ROLE_GO; + + if (_FAIL == rtw_p2p_enable(padapter, init_role)) { + ret = -EFAULT; + goto exit; + } + + /* set channel/bandwidth */ + if (init_role != P2P_ROLE_DISABLE) { + u8 channel, ch_offset; + u16 bwmode; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) { + /* Stay at the listen state and wait for discovery. */ + channel = pwdinfo->listen_channel; + pwdinfo->operating_channel = pwdinfo->listen_channel; + ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + bwmode = CHANNEL_WIDTH_20; + } + else { + pwdinfo->operating_channel = pmlmeext->cur_channel; + + channel = pwdinfo->operating_channel; + ch_offset = pmlmeext->cur_ch_offset; + bwmode = pmlmeext->cur_bwmode; + } + + set_channel_bwmode(padapter, channel, ch_offset, bwmode); + } + +exit: + return ret; + +} + +static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen(extra)); + _rtw_memcpy(pwdinfo->nego_ssid, extra, strlen(extra)); + pwdinfo->nego_ssidlen = strlen(extra); + + return ret; + +} + +static int rtw_p2p_set_intent(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 intent = pwdinfo->intent; + + extra[wrqu->data.length] = 0x00; + + intent = rtw_atoi(extra); + + if (intent <= 15) + pwdinfo->intent = intent; + else + ret = -1; + + RTW_INFO("[%s] intent = %d\n", __FUNCTION__, intent); + + return ret; + +} + +static int rtw_p2p_set_listen_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 listen_ch = pwdinfo->listen_channel; /* Listen channel number */ + + extra[wrqu->data.length] = 0x00; + listen_ch = rtw_atoi(extra); + + if ((listen_ch == 1) || (listen_ch == 6) || (listen_ch == 11)) { + pwdinfo->listen_channel = listen_ch; + set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } else + ret = -1; + + RTW_INFO("[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel); + + return ret; + +} + +static int rtw_p2p_set_op_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + /* Commented by Albert 20110524 + * This function is used to set the operating channel if the driver will become the group owner */ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 op_ch = pwdinfo->operating_channel; /* Operating channel number */ + + extra[wrqu->data.length] = 0x00; + + op_ch = (u8) rtw_atoi(extra); + if (op_ch > 0) + pwdinfo->operating_channel = op_ch; + else + ret = -1; + + RTW_INFO("[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel); + + return ret; + +} + +static int rtw_p2p_profilefound(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + /* Comment by Albert 2010/10/13 */ + /* Input data format: */ + /* Ex: 0 */ + /* Ex: 1XX:XX:XX:XX:XX:XXYYSSID */ + /* 0 => Reflush the profile record list. */ + /* 1 => Add the profile list */ + /* XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) */ + /* YY => SSID Length */ + /* SSID => SSID for persistence group */ + + RTW_INFO("[%s] In value = %s, len = %d\n", __FUNCTION__, extra, wrqu->data.length - 1); + + /* The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + if (extra[0] == '0') { + /* Remove all the profile information of wifidirect_info structure. */ + _rtw_memset(&pwdinfo->profileinfo[0], 0x00, sizeof(struct profile_info) * P2P_MAX_PERSISTENT_GROUP_NUM); + pwdinfo->profileindex = 0; + } else { + if (pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM) + ret = -1; + else { + int jj, kk; + + /* Add this profile information into pwdinfo->profileinfo */ + /* Ex: 1XX:XX:XX:XX:XX:XXYYSSID */ + for (jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3) + pwdinfo->profileinfo[pwdinfo->profileindex].peermac[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + /* pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[19] - '0' ); */ + /* _rtw_memcpy( pwdinfo->profileinfo[pwdinfo->profileindex].ssid, &extra[20], pwdinfo->profileinfo[pwdinfo->profileindex].ssidlen ); */ + pwdinfo->profileindex++; + } + } + } + + return ret; + +} + +static int rtw_p2p_setDN(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1); + _rtw_memset(pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN); + _rtw_memcpy(pwdinfo->device_name, extra, wrqu->data.length - 1); + pwdinfo->device_name_len = wrqu->data.length - 1; + + return ret; + +} + +static int rtw_p2p_get_status(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (padapter->bShowGetP2PState) { + RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + } + + /* Commented by Albert 2010/10/12 */ + /* Because of the output size limitation, I had removed the "Role" information. */ + /* About the "Role" information, we will use the new private IOCTL to get the "Role" information. */ + sprintf(extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo)); + wrqu->data.length = strlen(extra); + + return ret; + +} + +/* Commented by Albert 20110520 + * This function will return the config method description + * This config method description will show us which config method the remote P2P device is intented to use + * by sending the provisioning discovery request frame. */ + +static int rtw_p2p_get_req_cm(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + sprintf(extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req); + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_role(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + + sprintf(extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo)); + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + + sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], pwdinfo->p2p_peer_interface_addr[2], + pwdinfo->p2p_peer_interface_addr[3], pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5]); + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_peer_devaddr(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], + pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], + pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); + sprintf(extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X", + pwdinfo->rx_prov_disc_info.peerDevAddr[0], pwdinfo->rx_prov_disc_info.peerDevAddr[1], + pwdinfo->rx_prov_disc_info.peerDevAddr[2], pwdinfo->rx_prov_disc_info.peerDevAddr[3], + pwdinfo->rx_prov_disc_info.peerDevAddr[4], pwdinfo->rx_prov_disc_info.peerDevAddr[5]); + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], + pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], + pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); + sprintf(extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", + pwdinfo->p2p_peer_device_addr[0], pwdinfo->p2p_peer_device_addr[1], + pwdinfo->p2p_peer_device_addr[2], pwdinfo->p2p_peer_device_addr[3], + pwdinfo->p2p_peer_device_addr[4], pwdinfo->p2p_peer_device_addr[5]); + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_groupid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + sprintf(extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s", + pwdinfo->groupid_info.go_device_addr[0], pwdinfo->groupid_info.go_device_addr[1], + pwdinfo->groupid_info.go_device_addr[2], pwdinfo->groupid_info.go_device_addr[3], + pwdinfo->groupid_info.go_device_addr[4], pwdinfo->groupid_info.go_device_addr[5], + pwdinfo->groupid_info.ssid); + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_op_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel); + + sprintf(extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel); + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_wps_configmethod(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u16 attr_content = 0; + uint attr_contentlen = 0; + u8 attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + /* Commented by Albert 20110727 */ + /* The input data is the MAC address which the application wants to know its WPS config method. */ + /* After knowing its WPS config method, the application can decide the config method for provisioning discovery. */ + /* Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { + u8 *wpsie; + uint wpsie_len = 0; + + /* The mac address is matched. */ + + wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]); + if (wpsie) { + rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen); + if (attr_contentlen) { + attr_content = be16_to_cpu(attr_content); + sprintf(attr_content_str, "\n\nM=%.4d", attr_content); + blnMatch = 1; + } + } + + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + sprintf(attr_content_str, "\n\nM=0000"); + + wrqu->data.length = strlen(attr_content_str); + _rtw_memcpy(extra, attr_content_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_get_peer_wfd_port(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo)); + + sprintf(extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport); + RTW_INFO("[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport); + + wrqu->data.length = strlen(extra); + return ret; + +} + +static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + sprintf(extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc); + RTW_INFO("[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc); + + wrqu->data.length = strlen(extra); + pwdinfo->wfd_info->wfd_pc = _FALSE; /* Reset the WFD preferred connection to P2P */ + return ret; + +} + +static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + sprintf(extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail); + RTW_INFO("[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail); + + wrqu->data.length = strlen(extra); + pwdinfo->wfd_info->peer_session_avail = _TRUE; /* Reset the WFD session available */ + return ret; + +} + +static int rtw_p2p_get_go_device_address(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + u8 attr_content[100] = { 0x00 }; + u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + /* Commented by Albert 20121209 */ + /* The input data is the GO's interface address which the application wants to know its device address. */ + /* Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { + /* Commented by Albert 2011/05/18 */ + /* Match the device address located in the P2P IE */ + /* This is for the case that the P2P device address is not the same as the P2P interface address. */ + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + while (p2pie) { + /* The P2P Device ID attribute is included in the Beacon frame. */ + /* The P2P Device Info attribute is included in the probe response frame. */ + + _rtw_memset(attr_content, 0x00, 100); + if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { + /* Handle the P2P Device ID attribute of Beacon first */ + blnMatch = 1; + break; + + } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { + /* Handle the P2P Device Info attribute of probe response */ + blnMatch = 1; + break; + } + + /* Get the next P2P IE */ + p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); + } + } + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + sprintf(go_devadd_str, "\n\ndev_add=NULL"); + else { + sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X", + attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]); + } + + wrqu->data.length = strlen(go_devadd_str); + _rtw_memcpy(extra, go_devadd_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_get_device_type(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 dev_type[8] = { 0x00 }; + uint dev_type_len = 0; + u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; /* +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer */ + + /* Commented by Albert 20121209 */ + /* The input data is the MAC address which the application wants to know its device type. */ + /* Such user interface could know the device type. */ + /* Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { + u8 *wpsie; + uint wpsie_len = 0; + + /* The mac address is matched. */ + + wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]); + if (wpsie) { + rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len); + if (dev_type_len) { + u16 type = 0; + + _rtw_memcpy(&type, dev_type, 2); + type = be16_to_cpu(type); + sprintf(dev_type_str, "\n\nN=%.2d", type); + blnMatch = 1; + } + } + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + sprintf(dev_type_str, "\n\nN=00"); + + wrqu->data.length = strlen(dev_type_str); + _rtw_memcpy(extra, dev_type_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_get_device_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 }; + uint dev_len = 0; + u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + /* Commented by Albert 20121225 */ + /* The input data is the MAC address which the application wants to know its device name. */ + /* Such user interface could show peer device's device name instead of ssid. */ + /* Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { + u8 *wpsie; + uint wpsie_len = 0; + + /* The mac address is matched. */ + + wpsie = rtw_get_wps_ie_from_scan_queue(&pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0]); + if (wpsie) { + rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len); + if (dev_len) { + sprintf(dev_name_str, "\n\nN=%s", dev_name); + blnMatch = 1; + } + } + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + sprintf(dev_name_str, "\n\nN=0000"); + + wrqu->data.length = strlen(dev_name_str); + _rtw_memcpy(extra, dev_name_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_get_invitation_procedure(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + u8 attr_content[2] = { 0x00 }; + u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + /* Commented by Ouden 20121226 */ + /* The application wants to know P2P initation procedure is support or not. */ + /* Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { + /* Commented by Albert 20121226 */ + /* Match the device address located in the P2P IE */ + /* This is for the case that the P2P device address is not the same as the P2P interface address. */ + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + while (p2pie) { + /* _rtw_memset( attr_content, 0x00, 2); */ + if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) { + /* Handle the P2P capability attribute */ + blnMatch = 1; + break; + + } + + /* Get the next P2P IE */ + p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); + } + } + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + sprintf(inv_proc_str, "\nIP=-1"); + else { + if ((attr_content[0] & 0x20) == 0x20) + sprintf(inv_proc_str, "\nIP=1"); + else + sprintf(inv_proc_str, "\nIP=0"); + } + + wrqu->data.length = strlen(inv_proc_str); + _rtw_memcpy(extra, inv_proc_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_connect(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + int jj, kk; + u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; + + /* Commented by Albert 20110304 */ + /* The input data contains two informations. */ + /* 1. First information is the MAC address which wants to formate with */ + /* 2. Second information is the WPS PINCode or "pbc" string for push button method */ + /* Format: 00:E0:4C:00:00:05 */ + /* Format: 00:E0:4C:00:00:05 */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if (pwdinfo->p2p_state == P2P_STATE_NONE) { + RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); + return ret; + } + + if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) + return -1; + + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) { + if (pnetwork->network.Configuration.DSConfig != 0) + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + else if (pwdinfo->nego_req_info.peer_ch != 0) + uintPeerChannel = pnetwork->network.Configuration.DSConfig = pwdinfo->nego_req_info.peer_ch; + else { + /* Unexpected case */ + uintPeerChannel = 0; + RTW_INFO("%s uintPeerChannel = 0\n", __func__); + } + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (uintPeerChannel) { + + _rtw_memset(&pwdinfo->nego_req_info, 0x00, sizeof(struct tx_nego_req_info)); + _rtw_memset(&pwdinfo->groupid_info, 0x00, sizeof(struct group_id_info)); + + pwdinfo->nego_req_info.peer_channel_num[0] = uintPeerChannel; + _rtw_memcpy(pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN); + pwdinfo->nego_req_info.benable = _TRUE; + + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + if (rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK) { + /* Restore to the listen state if the current p2p state is not nego OK */ + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); + } + + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); + + + RTW_INFO("[%s] Start PreTx Procedure!\n", __FUNCTION__); + _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT); + + } else { + RTW_INFO("[%s] Not Found in Scanning Queue~\n", __FUNCTION__); + ret = -1; + } + + return ret; +} + +static int rtw_p2p_invite_req(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + int jj, kk; + u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; + u8 attr_content[50] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; + struct tx_invite_req_info *pinvite_req_info = &pwdinfo->invitereq_info; + + /* Commented by Albert 20120321 */ + /* The input data contains two informations. */ + /* 1. First information is the P2P device address which you want to send to. */ + /* 2. Second information is the group id which combines with GO's mac address, space and GO's ssid. */ + /* Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy" */ + /* Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if (wrqu->data.length <= 37) { + RTW_INFO("[%s] Wrong format!\n", __FUNCTION__); + return ret; + } + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); + return ret; + } else { + /* Reset the content of struct tx_invite_req_info */ + pinvite_req_info->benable = _FALSE; + _rtw_memset(pinvite_req_info->go_bssid, 0x00, ETH_ALEN); + _rtw_memset(pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN); + pinvite_req_info->ssidlen = 0x00; + pinvite_req_info->operating_ch = pwdinfo->operating_channel; + _rtw_memset(pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN); + pinvite_req_info->token = 3; + } + + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + pinvite_req_info->peer_macaddr[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + /* Commented by Albert 2011/05/18 */ + /* Match the device address located in the P2P IE */ + /* This is for the case that the P2P device address is not the same as the P2P interface address. */ + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + /* The P2P Device ID attribute is included in the Beacon frame. */ + /* The P2P Device Info attribute is included in the probe response frame. */ + + if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { + /* Handle the P2P Device ID attribute of Beacon first */ + if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { + /* Handle the P2P Device Info attribute of probe response */ + if (_rtw_memcmp(attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN)) { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST) && uintPeerChannel) { + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__); + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + u16 wfd_devinfo_field = 0; + + /* Commented by Albert 20120319 */ + /* The first two bytes are the WFD device information field of WFD device information subelement. */ + /* In big endian format. */ + wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); + if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL) + pwfd_info->peer_session_avail = _TRUE; + else + pwfd_info->peer_session_avail = _FALSE; + } + } + + if (_FALSE == pwfd_info->peer_session_avail) { + RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__); + goto exit; + } + } + + if (uintPeerChannel) { + + /* Store the GO's bssid */ + for (jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3) + pinvite_req_info->go_bssid[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + /* Store the GO's ssid */ + pinvite_req_info->ssidlen = wrqu->data.length - 36; + _rtw_memcpy(pinvite_req_info->go_ssid, &extra[36], (u32) pinvite_req_info->ssidlen); + pinvite_req_info->benable = _TRUE; + pinvite_req_info->peer_ch = uintPeerChannel; + + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ); + + set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + + _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + + _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT); + + } else + RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__); +exit: + + return ret; + +} + +static int rtw_p2p_set_persistent(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + int jj, kk; + u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; + u8 attr_content[50] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; + struct tx_invite_req_info *pinvite_req_info = &pwdinfo->invitereq_info; + + /* Commented by Albert 20120328 */ + /* The input data is 0 or 1 */ + /* 0: disable persistent group functionality */ + /* 1: enable persistent group founctionality */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); + return ret; + } else { + if (extra[0] == '0') /* Disable the persistent group function. */ + pwdinfo->persistent_supported = _FALSE; + else if (extra[0] == '1') /* Enable the persistent group function. */ + pwdinfo->persistent_supported = _TRUE; + else + pwdinfo->persistent_supported = _FALSE; + } + printk("[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported); + + return ret; + +} + +static int hexstr2bin(const char *hex, u8 *buf, size_t len) +{ + size_t i; + int a; + const char *ipos = hex; + u8 *opos = buf; + + for (i = 0; i < len; i++) { + a = hex2byte_i(ipos); + if (a < 0) + return -1; + *opos++ = a; + ipos += 2; + } + return 0; +} + +static int uuid_str2bin(const char *str, u8 *bin) +{ + const char *pos; + u8 *opos; + + pos = str; + opos = bin; + + if (hexstr2bin(pos, opos, 4)) + return -1; + pos += 8; + opos += 4; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) + return -1; + pos += 4; + opos += 2; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) + return -1; + pos += 4; + opos += 2; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) + return -1; + pos += 4; + opos += 2; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 6)) + return -1; + + return 0; +} + +static int rtw_p2p_set_wps_uuid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0)) + pwdinfo->external_uuid = 1; + else { + pwdinfo->external_uuid = 0; + ret = -EINVAL; + } + + return ret; + +} +static int rtw_p2p_set_pc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + int jj, kk; + u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 attr_content[50] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; + uint uintPeerChannel = 0; + + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + + /* Commented by Albert 20120512 */ + /* 1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) */ + /* Format: 00:E0:4C:00:00:05 */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); + return ret; + } + + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + /* Commented by Albert 2011/05/18 */ + /* Match the device address located in the P2P IE */ + /* This is for the case that the P2P device address is not the same as the P2P interface address. */ + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + /* The P2P Device ID attribute is included in the Beacon frame. */ + /* The P2P Device Info attribute is included in the probe response frame. */ + printk("[%s] Got P2P IE\n", __FUNCTION__); + if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { + /* Handle the P2P Device ID attribute of Beacon first */ + printk("[%s] P2P_ATTR_DEVICE_ID\n", __FUNCTION__); + if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { + /* Handle the P2P Device Info attribute of probe response */ + printk("[%s] P2P_ATTR_DEVICE_INFO\n", __FUNCTION__); + if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + printk("[%s] channel = %d\n", __FUNCTION__, uintPeerChannel); + + if (uintPeerChannel) { + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__); + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + u16 wfd_devinfo_field = 0; + + /* Commented by Albert 20120319 */ + /* The first two bytes are the WFD device information field of WFD device information subelement. */ + /* In big endian format. */ + wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); + if (wfd_devinfo_field & WFD_DEVINFO_PC_TDLS) + pwfd_info->wfd_pc = _TRUE; + else + pwfd_info->wfd_pc = _FALSE; + } + } + } else + RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__); + + return ret; + +} + +static int rtw_p2p_set_wfd_device_type(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + + /* Commented by Albert 20120328 */ + /* The input data is 0 or 1 */ + /* 0: specify to Miracast source device */ + /* 1 or others: specify to Miracast sink device (display device) */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if (extra[0] == '0') /* Set to Miracast source device. */ + pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE; + else /* Set to Miracast sink device. */ + pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK; + + return ret; + +} + +static int rtw_p2p_set_wfd_enable(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + /* Commented by Kurt 20121206 + * This function is used to set wfd enabled */ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (*extra == '0') + rtw_wfd_enable(padapter, 0); + else if (*extra == '1') + rtw_wfd_enable(padapter, 1); + + RTW_INFO("[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable); + + return ret; + +} + +static int rtw_p2p_set_driver_iface(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + /* Commented by Kurt 20121206 + * This function is used to set driver iface is WEXT or CFG80211 */ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + if (*extra == '1') { + pwdinfo->driver_interface = DRIVER_WEXT; + RTW_INFO("[%s] driver_interface = WEXT\n", __FUNCTION__); + } else if (*extra == '2') { + pwdinfo->driver_interface = DRIVER_CFG80211; + RTW_INFO("[%s] driver_interface = CFG80211\n", __FUNCTION__); + } + + return ret; + +} + +/* To set the WFD session available to enable or disable */ +static int rtw_p2p_set_sa(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if (0) { + RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); + return ret; + } else { + if (extra[0] == '0') /* Disable the session available. */ + pwdinfo->session_available = _FALSE; + else if (extra[0] == '1') /* Enable the session available. */ + pwdinfo->session_available = _TRUE; + else + pwdinfo->session_available = _FALSE; + } + printk("[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available); + + return ret; + +} + +static int rtw_p2p_prov_disc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + int jj, kk; + u8 peerMACStr[ETH_ALEN * 2] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; + u8 attr_content[100] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; + + /* Commented by Albert 20110301 */ + /* The input data contains two informations. */ + /* 1. First information is the MAC address which wants to issue the provisioning discovery request frame. */ + /* 2. Second information is the WPS configuration method which wants to discovery */ + /* Format: 00:E0:4C:00:00:05_display */ + /* Format: 00:E0:4C:00:00:05_keypad */ + /* Format: 00:E0:4C:00:00:05_pbc */ + /* Format: 00:E0:4C:00:00:05_label */ + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + + if (pwdinfo->p2p_state == P2P_STATE_NONE) { + RTW_INFO("[%s] WiFi Direct is disable!\n", __FUNCTION__); + return ret; + } else { + + /* Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. */ + _rtw_memset(pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN); + _rtw_memset(pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN); + _rtw_memset(&pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof(NDIS_802_11_SSID)); + pwdinfo->tx_prov_disc_info.peer_channel_num[0] = 0; + pwdinfo->tx_prov_disc_info.peer_channel_num[1] = 0; + pwdinfo->tx_prov_disc_info.benable = _FALSE; + } + + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + peerMAC[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + if (_rtw_memcmp(&extra[18], "display", 7)) + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; + else if (_rtw_memcmp(&extra[18], "keypad", 7)) + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; + else if (_rtw_memcmp(&extra[18], "pbc", 3)) + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; + else if (_rtw_memcmp(&extra[18], "label", 5)) + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; + else { + RTW_INFO("[%s] Unknown WPS config methodn", __FUNCTION__); + return ret ; + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + if (uintPeerChannel != 0) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + /* Commented by Albert 2011/05/18 */ + /* Match the device address located in the P2P IE */ + /* This is for the case that the P2P device address is not the same as the P2P interface address. */ + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + while (p2pie) { + /* The P2P Device ID attribute is included in the Beacon frame. */ + /* The P2P Device Info attribute is included in the probe response frame. */ + + if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) { + /* Handle the P2P Device ID attribute of Beacon first */ + if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) { + /* Handle the P2P Device Info attribute of probe response */ + if (_rtw_memcmp(attr_content, peerMAC, ETH_ALEN)) { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + + /* Get the next P2P IE */ + p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); + } + + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (uintPeerChannel) { + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + RTW_INFO("[%s] Found WFD IE!\n", __FUNCTION__); + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + u16 wfd_devinfo_field = 0; + + /* Commented by Albert 20120319 */ + /* The first two bytes are the WFD device information field of WFD device information subelement. */ + /* In big endian format. */ + wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); + if (wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL) + pwfd_info->peer_session_avail = _TRUE; + else + pwfd_info->peer_session_avail = _FALSE; + } + } + + if (_FALSE == pwfd_info->peer_session_avail) { + RTW_INFO("[%s] WFD Session not avaiable!\n", __FUNCTION__); + goto exit; + } + } + + RTW_INFO("[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel); + _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN); + _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN); + pwdinfo->tx_prov_disc_info.peer_channel_num[0] = (u16) uintPeerChannel; + pwdinfo->tx_prov_disc_info.benable = _TRUE; + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ); + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) + _rtw_memcpy(&pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID)); + else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + _rtw_memcpy(pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN); + pwdinfo->tx_prov_disc_info.ssid.SsidLength = P2P_WILDCARD_SSID_LEN; + } + + set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + + _set_timer(&pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT); + + _set_timer(&pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT); + + } else { + RTW_INFO("[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__); + } +exit: + + return ret; + +} + +/* Added by Albert 20110328 + * This function is used to inform the driver the user had specified the pin code value or pbc + * to application. */ + +static int rtw_p2p_got_wpsinfo(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + RTW_INFO("[%s] data = %s\n", __FUNCTION__, extra); + /* Added by Albert 20110328 */ + /* if the input data is P2P_NO_WPSINFO -> reset the wpsinfo */ + /* if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. */ + /* if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. */ + /* if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC */ + + if (*extra == '0') + pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; + else if (*extra == '1') + pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN; + else if (*extra == '2') + pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN; + else if (*extra == '3') + pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC; + else + pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; + + return ret; + +} + + +static int rtw_p2p_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra); + + if (_rtw_memcmp(extra, "enable=", 7)) + rtw_wext_p2p_enable(dev, info, wrqu, &extra[7]); + else if (_rtw_memcmp(extra, "setDN=", 6)) { + wrqu->data.length -= 6; + rtw_p2p_setDN(dev, info, wrqu, &extra[6]); + } else if (_rtw_memcmp(extra, "profilefound=", 13)) { + wrqu->data.length -= 13; + rtw_p2p_profilefound(dev, info, wrqu, &extra[13]); + } else if (_rtw_memcmp(extra, "prov_disc=", 10)) { + wrqu->data.length -= 10; + rtw_p2p_prov_disc(dev, info, wrqu, &extra[10]); + } else if (_rtw_memcmp(extra, "nego=", 5)) { + wrqu->data.length -= 5; + rtw_p2p_connect(dev, info, wrqu, &extra[5]); + } else if (_rtw_memcmp(extra, "intent=", 7)) { + /* Commented by Albert 2011/03/23 */ + /* The wrqu->data.length will include the null character */ + /* So, we will decrease 7 + 1 */ + wrqu->data.length -= 8; + rtw_p2p_set_intent(dev, info, wrqu, &extra[7]); + } else if (_rtw_memcmp(extra, "ssid=", 5)) { + wrqu->data.length -= 5; + rtw_p2p_set_go_nego_ssid(dev, info, wrqu, &extra[5]); + } else if (_rtw_memcmp(extra, "got_wpsinfo=", 12)) { + wrqu->data.length -= 12; + rtw_p2p_got_wpsinfo(dev, info, wrqu, &extra[12]); + } else if (_rtw_memcmp(extra, "listen_ch=", 10)) { + /* Commented by Albert 2011/05/24 */ + /* The wrqu->data.length will include the null character */ + /* So, we will decrease (10 + 1) */ + wrqu->data.length -= 11; + rtw_p2p_set_listen_ch(dev, info, wrqu, &extra[10]); + } else if (_rtw_memcmp(extra, "op_ch=", 6)) { + /* Commented by Albert 2011/05/24 */ + /* The wrqu->data.length will include the null character */ + /* So, we will decrease (6 + 1) */ + wrqu->data.length -= 7; + rtw_p2p_set_op_ch(dev, info, wrqu, &extra[6]); + } else if (_rtw_memcmp(extra, "invite=", 7)) { + wrqu->data.length -= 8; + rtw_p2p_invite_req(dev, info, wrqu, &extra[7]); + } else if (_rtw_memcmp(extra, "persistent=", 11)) { + wrqu->data.length -= 11; + rtw_p2p_set_persistent(dev, info, wrqu, &extra[11]); + } else if (_rtw_memcmp(extra, "uuid=", 5)) { + wrqu->data.length -= 5; + ret = rtw_p2p_set_wps_uuid(dev, info, wrqu, &extra[5]); + } + + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (_rtw_memcmp(extra, "sa=", 3)) { + /* sa: WFD Session Available information */ + wrqu->data.length -= 3; + rtw_p2p_set_sa(dev, info, wrqu, &extra[3]); + } else if (_rtw_memcmp(extra, "pc=", 3)) { + /* pc: WFD Preferred Connection */ + wrqu->data.length -= 3; + rtw_p2p_set_pc(dev, info, wrqu, &extra[3]); + } else if (_rtw_memcmp(extra, "wfd_type=", 9)) { + wrqu->data.length -= 9; + rtw_p2p_set_wfd_device_type(dev, info, wrqu, &extra[9]); + } else if (_rtw_memcmp(extra, "wfd_enable=", 11)) { + wrqu->data.length -= 11; + rtw_p2p_set_wfd_enable(dev, info, wrqu, &extra[11]); + } else if (_rtw_memcmp(extra, "driver_iface=", 13)) { + wrqu->data.length -= 13; + rtw_p2p_set_driver_iface(dev, info, wrqu, &extra[13]); + } + } + + + return ret; + +} + +static int rtw_p2p_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (padapter->bShowGetP2PState) + RTW_INFO("[%s] extra = %s\n", __FUNCTION__, (char *) wrqu->data.pointer); + + if (_rtw_memcmp(wrqu->data.pointer, "status", 6)) + rtw_p2p_get_status(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "role", 4)) + rtw_p2p_get_role(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "peer_ifa", 8)) + rtw_p2p_get_peer_ifaddr(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "req_cm", 6)) + rtw_p2p_get_req_cm(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "peer_deva", 9)) { + /* Get the P2P device address when receiving the provision discovery request frame. */ + rtw_p2p_get_peer_devaddr(dev, info, wrqu, extra); + } else if (_rtw_memcmp(wrqu->data.pointer, "group_id", 8)) + rtw_p2p_get_groupid(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "inv_peer_deva", 13)) { + /* Get the P2P device address when receiving the P2P Invitation request frame. */ + rtw_p2p_get_peer_devaddr_by_invitation(dev, info, wrqu, extra); + } else if (_rtw_memcmp(wrqu->data.pointer, "op_ch", 5)) + rtw_p2p_get_op_ch(dev, info, wrqu, extra); + + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (_rtw_memcmp(wrqu->data.pointer, "peer_port", 9)) + rtw_p2p_get_peer_wfd_port(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "wfd_sa", 6)) + rtw_p2p_get_peer_wfd_session_available(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "wfd_pc", 6)) + rtw_p2p_get_peer_wfd_preferred_connection(dev, info, wrqu, extra); + } + + + return ret; + +} + +static int rtw_p2p_get2(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + + + int length = wrqu->data.length; + char *buffer = (u8 *)rtw_malloc(length); + + if (buffer == NULL) { + ret = -ENOMEM; + goto bad; + } + + if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) { + ret = -EFAULT; + goto bad; + } + + RTW_INFO("[%s] buffer = %s\n", __FUNCTION__, buffer); + + if (_rtw_memcmp(buffer, "wpsCM=", 6)) + ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]); + else if (_rtw_memcmp(buffer, "devN=", 5)) + ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]); + else if (_rtw_memcmp(buffer, "dev_type=", 9)) + ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]); + else if (_rtw_memcmp(buffer, "go_devadd=", 10)) + ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]); + else if (_rtw_memcmp(buffer, "InvProc=", 8)) + ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]); + else { + snprintf(extra, sizeof("Command not found."), "Command not found."); + wrqu->data.length = strlen(extra); + } + +bad: + if (buffer) + rtw_mfree(buffer, length); + + + return ret; + +} + +static int rtw_cta_test_start(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + RTW_INFO("%s %s\n", __func__, extra); + if (!strcmp(extra, "1")) + padapter->in_cta_test = 1; + else + padapter->in_cta_test = 0; + + if (padapter->in_cta_test) { + u32 v = rtw_read32(padapter, REG_RCR); + v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); /* | RCR_ADF */ + rtw_write32(padapter, REG_RCR, v); + RTW_INFO("enable RCR_ADF\n"); + } else { + u32 v = rtw_read32(padapter, REG_RCR); + v |= RCR_CBSSID_DATA | RCR_CBSSID_BCN ;/* | RCR_ADF */ + rtw_write32(padapter, REG_RCR, v); + RTW_INFO("disable RCR_ADF\n"); + } + return ret; +} + +extern int rtw_change_ifname(_adapter *padapter, const char *ifname); +static int rtw_rereg_nd_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv; + char new_ifname[IFNAMSIZ]; + + if (rereg_priv->old_ifname[0] == 0) { + char *reg_ifname; + reg_ifname = padapter->registrypriv.if2name; + + strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ); + rereg_priv->old_ifname[IFNAMSIZ - 1] = 0; + } + + /* RTW_INFO("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length); */ + if (wrqu->data.length > IFNAMSIZ) + return -EFAULT; + + if (copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ)) + return -EFAULT; + + if (0 == strcmp(rereg_priv->old_ifname, new_ifname)) + return ret; + + RTW_INFO("%s new_ifname:%s\n", __FUNCTION__, new_ifname); + rtw_set_rtnl_lock_holder(dvobj, current); + ret = rtw_change_ifname(padapter, new_ifname); + rtw_set_rtnl_lock_holder(dvobj, NULL); + if (0 != ret) + goto exit; + + if (_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) { + padapter->ledpriv.bRegUseLed = rereg_priv->old_bRegUseLed; + rtw_hal_sw_led_init(padapter); + /* rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); */ + } + + strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ); + rereg_priv->old_ifname[IFNAMSIZ - 1] = 0; + + if (_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) { + + RTW_INFO("%s disable\n", __FUNCTION__); + /* free network queue for Android's timming issue */ + rtw_free_network_queue(padapter, _TRUE); + + /* close led */ + rtw_led_control(padapter, LED_CTL_POWER_OFF); + rereg_priv->old_bRegUseLed = padapter->ledpriv.bRegUseLed; + padapter->ledpriv.bRegUseLed = _FALSE; + rtw_hal_sw_led_deinit(padapter); + + /* the interface is being "disabled", we can do deeper IPS */ + /* rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); */ + /* rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); */ + } +exit: + return ret; + +} + + +/* +#ifdef DBG_DUMP_TSF_BY_PORT +extern void get_tsf_by_port(_adapter *adapter, u8 *tsftr, u8 hw_port); +#endif +*/ +static int rtw_dbg_port(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _irqL irqL; + int ret = 0; + u8 major_cmd, minor_cmd; + u16 arg; + u32 extra_arg, *pdata, val32; + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + + pdata = (u32 *)&wrqu->data; + + val32 = *pdata; + arg = (u16)(val32 & 0x0000ffff); + major_cmd = (u8)(val32 >> 24); + minor_cmd = (u8)((val32 >> 16) & 0x00ff); + + extra_arg = *(pdata + 1); + + switch (major_cmd) { + case 0x70: /* read_reg */ + switch (minor_cmd) { + case 1: + RTW_INFO("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); + break; + case 2: + RTW_INFO("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); + break; + case 4: + RTW_INFO("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); + break; + } + break; + case 0x71: /* write_reg */ + switch (minor_cmd) { + case 1: + rtw_write8(padapter, arg, extra_arg); + RTW_INFO("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); + break; + case 2: + rtw_write16(padapter, arg, extra_arg); + RTW_INFO("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); + break; + case 4: + rtw_write32(padapter, arg, extra_arg); + RTW_INFO("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); + break; + } + break; + case 0x72: /* read_bb */ + RTW_INFO("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); + break; + case 0x73: /* write_bb */ + rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg); + RTW_INFO("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); + break; + case 0x74: /* read_rf */ + RTW_INFO("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); + break; + case 0x75: /* write_rf */ + rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg); + RTW_INFO("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n", minor_cmd, arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); + break; + + case 0x76: + switch (minor_cmd) { + case 0x00: /* normal mode, */ + padapter->recvpriv.is_signal_dbg = 0; + break; + case 0x01: /* dbg mode */ + padapter->recvpriv.is_signal_dbg = 1; + extra_arg = extra_arg > 100 ? 100 : extra_arg; + padapter->recvpriv.signal_strength_dbg = extra_arg; + break; + } + break; + case 0x78: /* IOL test */ + switch (minor_cmd) { + } + break; + case 0x79: { + /* + * dbg 0x79000000 [value], set RESP_TXAGC to + value, value:0~15 + * dbg 0x79010000 [value], set RESP_TXAGC to - value, value:0~15 + */ + u8 value = extra_arg & 0x0f; + u8 sign = minor_cmd; + u16 write_value = 0; + + RTW_INFO("%s set RESP_TXAGC to %s %u\n", __func__, sign ? "minus" : "plus", value); + + if (sign) + value = value | 0x10; + + write_value = value | (value << 5); + rtw_write16(padapter, 0x6d9, write_value); + } + break; + case 0x7a: + receive_disconnect(padapter, pmlmeinfo->network.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); + break; + case 0x7F: + switch (minor_cmd) { + case 0x0: + RTW_INFO("fwstate=0x%x\n", get_fwstate(pmlmepriv)); + break; + case 0x01: + RTW_INFO("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", + psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, + psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); + break; + case 0x02: + RTW_INFO("pmlmeinfo->state=0x%x\n", pmlmeinfo->state); + RTW_INFO("DrvBcnEarly=%d\n", pmlmeext->DrvBcnEarly); + RTW_INFO("DrvBcnTimeOut=%d\n", pmlmeext->DrvBcnTimeOut); + break; + case 0x03: + RTW_INFO("qos_option=%d\n", pmlmepriv->qospriv.qos_option); + RTW_INFO("ht_option=%d\n", pmlmepriv->htpriv.ht_option); + break; + case 0x04: + RTW_INFO("cur_ch=%d\n", pmlmeext->cur_channel); + RTW_INFO("cur_bw=%d\n", pmlmeext->cur_bwmode); + RTW_INFO("cur_ch_off=%d\n", pmlmeext->cur_ch_offset); + + RTW_INFO("oper_ch=%d\n", rtw_get_oper_ch(padapter)); + RTW_INFO("oper_bw=%d\n", rtw_get_oper_bw(padapter)); + RTW_INFO("oper_ch_offet=%d\n", rtw_get_oper_choffset(padapter)); + + break; + case 0x05: + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if (psta) { + RTW_INFO("SSID=%s\n", cur_network->network.Ssid.Ssid); + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_INFO("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); + + sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); + } else + RTW_INFO("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); + break; + case 0x06: { + #ifdef DBG_DUMP_TSF_BY_PORT + u64 tsf = 0; + + get_tsf_by_port(padapter, (u8 *)&tsf, extra_arg); + RTW_INFO(" PORT-%d TSF :%lld\n", extra_arg, tsf); + #endif + } + break; + case 0x07: + RTW_INFO("bSurpriseRemoved=%s, bDriverStopped=%s\n" + , rtw_is_surprise_removed(padapter) ? "True" : "False" + , rtw_is_drv_stopped(padapter) ? "True" : "False"); + break; + case 0x08: { + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct recv_priv *precvpriv = &padapter->recvpriv; + + RTW_INFO("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d" + ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d" + ", free_recvframe_cnt=%d\n", + pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, + pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, + precvpriv->free_recvframe_cnt); + } + break; + case 0x09: { + int i; + _list *plist, *phead; + + RTW_INFO("sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + plist = get_next(plist); + + if (extra_arg == psta->aid) { + RTW_INFO("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + RTW_INFO("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); + RTW_INFO("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); + RTW_INFO("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + RTW_INFO("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, + psta->htpriv.sgi_40m); + RTW_INFO("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + RTW_INFO("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); + + RTW_INFO("capability=0x%x\n", psta->capability); + RTW_INFO("flags=0x%x\n", psta->flags); + RTW_INFO("wpa_psk=0x%x\n", psta->wpa_psk); + RTW_INFO("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); + RTW_INFO("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); + RTW_INFO("qos_info=0x%x\n", psta->qos_info); + RTW_INFO("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); + + sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); + } + + } + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + } + break; + + case 0x0b: { /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ + /* u8 driver_vcs_en; */ /* Enable=1, Disable=0 driver control vrtl_carrier_sense. */ + /* u8 driver_vcs_type; */ /* force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. */ + + if (arg == 0) { + RTW_INFO("disable driver ctrl vcs\n"); + padapter->driver_vcs_en = 0; + } else if (arg == 1) { + RTW_INFO("enable driver ctrl vcs = %d\n", extra_arg); + padapter->driver_vcs_en = 1; + + if (extra_arg > 2) + padapter->driver_vcs_type = 1; + else + padapter->driver_vcs_type = extra_arg; + } + } + break; + case 0x0c: { /* dump rx/tx packet */ + if (arg == 0) { + RTW_INFO("dump rx packet (%d)\n", extra_arg); + /* pHalData->bDumpRxPkt =extra_arg; */ + rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg)); + } else if (arg == 1) { + RTW_INFO("dump tx packet (%d)\n", extra_arg); + rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg)); + } + } + break; + case 0x0e: { + if (arg == 0) { + RTW_INFO("disable driver ctrl rx_ampdu_factor\n"); + padapter->driver_rx_ampdu_factor = 0xFF; + } else if (arg == 1) { + + RTW_INFO("enable driver ctrl rx_ampdu_factor = %d\n", extra_arg); + + if (extra_arg > 0x03) + padapter->driver_rx_ampdu_factor = 0xFF; + else + padapter->driver_rx_ampdu_factor = extra_arg; + } + } + break; + case 0x0f: { + if (extra_arg == 0) { + RTW_INFO("###### silent reset test.......#####\n"); + rtw_hal_sreset_reset(padapter); + } else { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + psrtpriv->dbg_trigger_point = extra_arg; + } + + } + break; + case 0x15: { + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + RTW_INFO("==>silent resete cnts:%d\n", pwrpriv->ips_enter_cnts); + } + break; + + + case 0x10: /* driver version display */ + dump_drv_version(RTW_DBGDUMP); + break; + case 0x11: { /* dump linked status */ + int pre_mode; + pre_mode = padapter->bLinkInfoDump; + /* linked_info_dump(padapter,extra_arg); */ + if (extra_arg == 1 || (extra_arg == 0 && pre_mode == 1)) /* not consider pwr_saving 0: */ + padapter->bLinkInfoDump = extra_arg; + + else if ((extra_arg == 2) || (extra_arg == 0 && pre_mode == 2)) { /* consider power_saving */ + /* RTW_INFO("linked_info_dump =%s\n", (padapter->bLinkInfoDump)?"enable":"disable") */ + linked_info_dump(padapter, extra_arg); + } + + } + break; + case 0x12: { /* set rx_stbc */ + struct registry_priv *pregpriv = &padapter->registrypriv; + /* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g */ + /* default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ + if (pregpriv && (extra_arg == 0 || extra_arg == 1 || extra_arg == 2 || extra_arg == 3)) { + pregpriv->rx_stbc = extra_arg; + RTW_INFO("set rx_stbc=%d\n", pregpriv->rx_stbc); + } else + RTW_INFO("get rx_stbc=%d\n", pregpriv->rx_stbc); + + } + break; + case 0x13: { /* set ampdu_enable */ + struct registry_priv *pregpriv = &padapter->registrypriv; + /* 0: disable, 0x1:enable */ + if (pregpriv && extra_arg < 2) { + pregpriv->ampdu_enable = extra_arg; + RTW_INFO("set ampdu_enable=%d\n", pregpriv->ampdu_enable); + } else + RTW_INFO("get ampdu_enable=%d\n", pregpriv->ampdu_enable); + + } + break; + case 0x14: { /* get wifi_spec */ + struct registry_priv *pregpriv = &padapter->registrypriv; + RTW_INFO("get wifi_spec=%d\n", pregpriv->wifi_spec); + + } + break; + + case 0x19: { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + /* extra_arg : */ + /* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, */ + /* BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ + if (arg == 0) { + RTW_INFO("driver disable LDPC\n"); + pregistrypriv->ldpc_cap = 0x00; + } else if (arg == 1) { + RTW_INFO("driver set LDPC cap = 0x%x\n", extra_arg); + pregistrypriv->ldpc_cap = (u8)(extra_arg & 0x33); + } + } + break; + case 0x1a: { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + /* extra_arg : */ + /* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, */ + /* BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ + if (arg == 0) { + RTW_INFO("driver disable STBC\n"); + pregistrypriv->stbc_cap = 0x00; + } else if (arg == 1) { + RTW_INFO("driver set STBC cap = 0x%x\n", extra_arg); + pregistrypriv->stbc_cap = (u8)(extra_arg & 0x33); + } + } + break; + case 0x1b: { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + if (arg == 0) { + RTW_INFO("disable driver ctrl max_rx_rate, reset to default_rate_set\n"); + init_mlme_default_rate_set(padapter); + pregistrypriv->ht_enable = (u8)rtw_ht_enable; + } else if (arg == 1) { + + int i; + u8 max_rx_rate; + + RTW_INFO("enable driver ctrl max_rx_rate = 0x%x\n", extra_arg); + + max_rx_rate = (u8)extra_arg; + + if (max_rx_rate < 0xc) { /* max_rx_rate < MSC0->B or G -> disable HT */ + pregistrypriv->ht_enable = 0; + for (i = 0; i < NumRates; i++) { + if (pmlmeext->datarate[i] > max_rx_rate) + pmlmeext->datarate[i] = 0xff; + } + + } + else if (max_rx_rate < 0x1c) { /* mcs0~mcs15 */ + u32 mcs_bitmap = 0x0; + + for (i = 0; i < ((max_rx_rate + 1) - 0xc); i++) + mcs_bitmap |= BIT(i); + + set_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap); + } + } + } + break; + case 0x1c: { /* enable/disable driver control AMPDU Density for peer sta's rx */ + if (arg == 0) { + RTW_INFO("disable driver ctrl ampdu density\n"); + padapter->driver_ampdu_spacing = 0xFF; + } else if (arg == 1) { + + RTW_INFO("enable driver ctrl ampdu density = %d\n", extra_arg); + + if (extra_arg > 0x07) + padapter->driver_ampdu_spacing = 0xFF; + else + padapter->driver_ampdu_spacing = extra_arg; + } + } + break; + + case 0x20: + { + if (arg == 0xAA) { + u8 page_offset, page_num; + u32 page_size = 0; + u8 *buffer = NULL; + u32 buf_size = 0; + + page_offset = (u8)(extra_arg >> 16); + page_num = (u8)(extra_arg & 0xFF); + rtw_dump_rsvd_page(RTW_DBGDUMP, padapter, page_offset, page_num); + } +#ifdef CONFIG_SUPPORT_FIFO_DUMP + else { + u8 fifo_sel; + u32 addr, size; + u8 *buffer = NULL; + + fifo_sel = (u8)(arg & 0x0F); + addr = (extra_arg >> 16) & 0xFFFF; + size = extra_arg & 0xFFFF; + + RTW_INFO("fifo_sel:%d, start_addr:0x%04x, size:%d\n", fifo_sel, addr, size); + if (size) { + size = RND4(size); + buffer = rtw_zvmalloc(size); + if (NULL == buffer) + size = 0; + } + rtw_halmac_dump_fifo(adapter_to_dvobj(padapter), fifo_sel, addr, size, buffer); + if (buffer) + rtw_vmfree(buffer, size); + } +#endif + } + break; + + case 0x23: { + RTW_INFO("turn %s the bNotifyChannelChange Variable\n", (extra_arg == 1) ? "on" : "off"); + padapter->bNotifyChannelChange = extra_arg; + break; + } + case 0x24: { + RTW_INFO("turn %s the bShowGetP2PState Variable\n", (extra_arg == 1) ? "on" : "off"); + padapter->bShowGetP2PState = extra_arg; + break; + } + case 0xaa: { + if ((extra_arg & 0x7F) > 0x3F) + extra_arg = 0xFF; + RTW_INFO("chang data rate to :0x%02x\n", extra_arg); + padapter->fix_rate = extra_arg; + } + break; + case 0xdd: { /* registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg */ + if (extra_arg == 0) + mac_reg_dump(RTW_DBGDUMP, padapter); + else if (extra_arg == 1) + bb_reg_dump(RTW_DBGDUMP, padapter); + else if (extra_arg == 2) + rf_reg_dump(RTW_DBGDUMP, padapter); + else if (extra_arg == 11) + bb_reg_dump_ex(RTW_DBGDUMP, padapter); + } + break; + + case 0xee: { + RTW_INFO(" === please control /proc to trun on/off PHYDM func ===\n"); + } + break; + + case 0xfd: + rtw_write8(padapter, 0xc50, arg); + RTW_INFO("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); + rtw_write8(padapter, 0xc58, arg); + RTW_INFO("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); + break; + case 0xfe: + RTW_INFO("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); + RTW_INFO("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); + break; + case 0xff: { + RTW_INFO("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); + RTW_INFO("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); + RTW_INFO("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); + RTW_INFO("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); + RTW_INFO("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); + + RTW_INFO("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); + + RTW_INFO("\n"); + + RTW_INFO("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); + RTW_INFO("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); + + RTW_INFO("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); + + RTW_INFO("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); + + RTW_INFO("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); + RTW_INFO("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); + + RTW_INFO("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); + RTW_INFO("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); + RTW_INFO("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); + RTW_INFO("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); + } + break; + } + break; + default: + RTW_INFO("error dbg cmd!\n"); + break; + } + + return ret; + +} + +static int wpa_set_param(struct net_device *dev, u8 name, u32 value) +{ + uint ret = 0; + u32 flags; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + switch (name) { + case IEEE_PARAM_WPA_ENABLED: + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; /* 802.1x */ + + switch ((value) & 0xff) { + case 1: /* WPA */ + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; /* WPA_PSK */ + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case 2: /* WPA2 */ + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; /* WPA2_PSK */ + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + } + + break; + + case IEEE_PARAM_AUTH_ALGS: + ret = wpa_set_auth_algs(dev, value); + break; + + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + switch (command) { + case IEEE_MLME_STA_DEAUTH: + + if (!rtw_set_802_11_disassociate(padapter)) + ret = -1; + + break; + + case IEEE_MLME_STA_DISASSOC: + + if (!rtw_set_802_11_disassociate(padapter)) + ret = -1; + + break; + + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; + +} + +static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) +{ + struct ieee_param *param; + uint ret = 0; + + /* down(&ieee->wx_sem); */ + + if (p->length < sizeof(struct ieee_param) || !p->pointer) { + ret = -EINVAL; + goto out; + } + + param = (struct ieee_param *)rtw_malloc(p->length); + if (param == NULL) { + ret = -ENOMEM; + goto out; + } + + if (copy_from_user(param, p->pointer, p->length)) { + rtw_mfree((u8 *)param, p->length); + ret = -EFAULT; + goto out; + } + + switch (param->cmd) { + + case IEEE_CMD_SET_WPA_PARAM: + ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value); + break; + + case IEEE_CMD_SET_WPA_IE: + /* ret = wpa_set_wpa_ie(dev, param, p->length); */ + ret = rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char *)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len); + break; + + case IEEE_CMD_SET_ENCRYPTION: + ret = wpa_set_encryption(dev, param, p->length); + break; + + case IEEE_CMD_MLME: + ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code); + break; + + default: + RTW_INFO("Unknown WPA supplicant request: %d\n", param->cmd); + ret = -EOPNOTSUPP; + break; + + } + + if (ret == 0 && copy_to_user(p->pointer, param, p->length)) + ret = -EFAULT; + + rtw_mfree((u8 *)param, p->length); + +out: + + /* up(&ieee->wx_sem); */ + + return ret; + +} + +static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ + int ret = 0; + u32 wep_key_idx, wep_key_len, wep_total_len; + NDIS_802_11_WEP *pwep = NULL; + struct sta_info *psta = NULL, *pbcmc_sta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &(padapter->securitypriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + RTW_INFO("%s\n", __FUNCTION__); + + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + + /* sizeof(struct ieee_param) = 64 bytes; */ + /* if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) */ + if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) { + ret = -EINVAL; + goto exit; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) { + if (param->u.crypt.idx >= WEP_KEYS + ) { + ret = -EINVAL; + goto exit; + } + } else { + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (!psta) { + /* ret = -EINVAL; */ + RTW_INFO("rtw_set_encryption(), sta has already been removed or never been added\n"); + goto exit; + } + } + + if (strcmp(param->u.crypt.alg, "none") == 0 && (psta == NULL)) { + /* todo:clear default encryption keys */ + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; + psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + + RTW_INFO("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); + + goto exit; + } + + if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta == NULL)) { + RTW_INFO("r871x_set_encryption, crypt.alg = WEP\n"); + + wep_key_idx = param->u.crypt.idx; + wep_key_len = param->u.crypt.key_len; + + RTW_INFO("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); + + if ((wep_key_idx >= WEP_KEYS) || (wep_key_len <= 0)) { + ret = -EINVAL; + goto exit; + } + + if (wep_key_len > 0) { + wep_key_len = wep_key_len <= 5 ? 5 : 13; + wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); + pwep = (NDIS_802_11_WEP *)rtw_malloc(wep_total_len); + if (pwep == NULL) { + RTW_INFO(" r871x_set_encryption: pwep allocate fail !!!\n"); + goto exit; + } + + _rtw_memset(pwep, 0, wep_total_len); + + pwep->KeyLength = wep_key_len; + pwep->Length = wep_total_len; + + } + + pwep->KeyIndex = wep_key_idx; + + _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); + + if (param->u.crypt.set_tx) { + RTW_INFO("wep, set_tx=1\n"); + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + + if (pwep->KeyLength == 13) { + psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + + psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + + psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; + + rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1); + } else { + RTW_INFO("wep, set_tx=0\n"); + + /* don't update "psecuritypriv->dot11PrivacyAlgrthm" and */ + /* "psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam */ + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + + psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; + + rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0); + } + + goto exit; + + } + + if (!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) /* */ { /* group key */ + if (param->u.crypt.set_tx == 1) { + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + RTW_INFO("%s, set group_key, WEP\n", __FUNCTION__); + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if (param->u.crypt.key_len == 13) + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO("%s, set group_key, TKIP\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _TKIP_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + + /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ + /* set mic key */ + _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + RTW_INFO("%s, set group_key, CCMP\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _AES_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + } + else { + RTW_INFO("%s, set group_key, none\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } + + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + + psecuritypriv->binstallGrpkey = _TRUE; + + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ + + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + if (pbcmc_sta) { + pbcmc_sta->ieee8021x_blocked = _FALSE; + pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ + } + + } + + goto exit; + + } + + if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) { /* psk/802_1x */ + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + if (param->u.crypt.set_tx == 1) { + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + RTW_INFO("%s, set pairwise key, WEP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _WEP40_; + if (param->u.crypt.key_len == 13) + psta->dot118021XPrivacy = _WEP104_; + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + RTW_INFO("%s, set pairwise key, TKIP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _TKIP_; + + /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ + /* set mic key */ + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + + RTW_INFO("%s, set pairwise key, CCMP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _AES_; + } else { + RTW_INFO("%s, set pairwise key, none\n", __FUNCTION__); + + psta->dot118021XPrivacy = _NO_PRIVACY_; + } + + rtw_ap_set_pairwise_key(padapter, psta); + + psta->ieee8021x_blocked = _FALSE; + + psta->bpairwise_key_installed = _TRUE; + + } else { /* group key??? */ + if (strcmp(param->u.crypt.alg, "WEP") == 0) { + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if (param->u.crypt.key_len == 13) + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } else if (strcmp(param->u.crypt.alg, "TKIP") == 0) { + psecuritypriv->dot118021XGrpPrivacy = _TKIP_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + + /* DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); */ + /* set mic key */ + _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } else if (strcmp(param->u.crypt.alg, "CCMP") == 0) { + psecuritypriv->dot118021XGrpPrivacy = _AES_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16 : param->u.crypt.key_len)); + } else + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + + psecuritypriv->binstallGrpkey = _TRUE; + + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;/* !!! */ + + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + if (pbcmc_sta) { + pbcmc_sta->ieee8021x_blocked = _FALSE; + pbcmc_sta->dot118021XPrivacy = psecuritypriv->dot118021XGrpPrivacy; /* rx will use bmc_sta's dot118021XPrivacy */ + } + + } + + } + + } + +exit: + + if (pwep) + rtw_mfree((u8 *)pwep, wep_total_len); + + return ret; + +} + +static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + unsigned char *pbuf = param->u.bcn_ie.buf; + + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); + + if ((pstapriv->max_num_sta > NUM_STA) || (pstapriv->max_num_sta <= 0)) + pstapriv->max_num_sta = NUM_STA; + + if (rtw_check_beacon_data(padapter, pbuf, (len - 12 - 2)) == _SUCCESS) /* 12 = param header, 2:no packed */ + ret = 0; + else + ret = -EINVAL; + + return ret; + +} + +static int rtw_hostapd_sta_flush(struct net_device *dev) +{ + /* _irqL irqL; */ + /* _list *phead, *plist; */ + int ret = 0; + /* struct sta_info *psta = NULL; */ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + /* struct sta_priv *pstapriv = &padapter->stapriv; */ + + RTW_INFO("%s\n", __FUNCTION__); + + flush_all_cam_entry(padapter); /* clear CAM */ + + ret = rtw_sta_flush(padapter, _TRUE); + + return ret; + +} + +static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) +{ + _irqL irqL; + int ret = 0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + RTW_INFO("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr)); + + if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; + + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (psta) { + int flags = param->u.add_sta.flags; + + /* RTW_INFO("rtw_add_sta(), init sta's variables, psta=%p\n", psta); */ + + psta->aid = param->u.add_sta.aid;/* aid=1~2007 */ + + _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); + + /* check wmm cap. */ + if (WLAN_STA_WME & flags) + psta->qos_option = 1; + else + psta->qos_option = 0; + + if (pmlmepriv->qospriv.qos_option == 0) + psta->qos_option = 0; + + /* chec 802.11n ht cap. */ + if (WLAN_STA_HT & flags) { + psta->htpriv.ht_option = _TRUE; + psta->qos_option = 1; + _rtw_memcpy((void *)&psta->htpriv.ht_cap, (void *)¶m->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); + } else + psta->htpriv.ht_option = _FALSE; + + if (pmlmepriv->htpriv.ht_option == _FALSE) + psta->htpriv.ht_option = _FALSE; + + update_sta_info_apmode(padapter, psta); + + } else + ret = -ENOMEM; + + return ret; + +} + +static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) +{ + _irqL irqL; + int ret = 0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + RTW_INFO("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr)); + + if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; + + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (psta) { + u8 updated = _FALSE; + + /* RTW_INFO("free psta=%p, aid=%d\n", psta, psta->aid); */ + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + + psta = NULL; + + } else { + RTW_INFO("rtw_del_sta(), sta has already been removed or never been added\n"); + + /* ret = -1; */ + } + + return ret; + +} + +static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param; + struct sta_data *psta_data = (struct sta_data *)param_ex->data; + + RTW_INFO("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr)); + + if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; + + if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff && + param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff && + param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff) + return -EINVAL; + + psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr); + if (psta) { + psta_data->aid = (u16)psta->aid; + psta_data->capability = psta->capability; + psta_data->flags = psta->flags; + + psta_data->sta_set = ((psta->nonerp_set) | + (psta->no_short_slot_time_set << 1) | + (psta->no_short_preamble_set << 2) | + (psta->no_ht_gf_set << 3) | + (psta->no_ht_set << 4) | + (psta->ht_20mhz_set << 5)); + + psta_data->tx_supp_rates_len = psta->bssratelen; + _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen); + _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); + psta_data->rx_pkts = psta->sta_stats.rx_data_pkts; + psta_data->rx_bytes = psta->sta_stats.rx_bytes; + psta_data->rx_drops = psta->sta_stats.rx_drops; + + psta_data->tx_pkts = psta->sta_stats.tx_pkts; + psta_data->tx_bytes = psta->sta_stats.tx_bytes; + psta_data->tx_drops = psta->sta_stats.tx_drops; + + } else + ret = -1; + + return ret; + +} + +static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) +{ + int ret = 0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + RTW_INFO("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr)); + + if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) != _TRUE) + return -EINVAL; + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; + + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if (psta) { + if ((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) { + int wpa_ie_len; + int copy_len; + + wpa_ie_len = psta->wpa_ie[1]; + + copy_len = ((wpa_ie_len + 2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)) : (wpa_ie_len + 2); + + param->u.wpa_ie.len = copy_len; + + _rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len); + } else { + /* ret = -1; */ + RTW_INFO("sta's wpa_ie is NONE\n"); + } + } else + ret = -1; + + return ret; + +} + +static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + unsigned char wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int ie_len; + + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ + + if (pmlmepriv->wps_beacon_ie) { + rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); + pmlmepriv->wps_beacon_ie = NULL; + } + + if (ie_len > 0) { + pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len); + pmlmepriv->wps_beacon_ie_len = ie_len; + if (pmlmepriv->wps_beacon_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + _rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len); + + update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE); + + pmlmeext->bstart_bss = _TRUE; + + } + + return ret; + +} + +static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int ie_len; + + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ + + if (pmlmepriv->wps_probe_resp_ie) { + rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); + pmlmepriv->wps_probe_resp_ie = NULL; + } + + if (ie_len > 0) { + pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len); + pmlmepriv->wps_probe_resp_ie_len = ie_len; + if (pmlmepriv->wps_probe_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len); + } + + return ret; + +} + +static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int ie_len; + + RTW_INFO("%s, len=%d\n", __FUNCTION__, len); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ + + if (pmlmepriv->wps_assoc_resp_ie) { + rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); + pmlmepriv->wps_assoc_resp_ie = NULL; + } + + if (ie_len > 0) { + pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); + pmlmepriv->wps_assoc_resp_ie_len = ie_len; + if (pmlmepriv->wps_assoc_resp_ie == NULL) { + RTW_INFO("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len); + } + + return ret; + +} + +static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + int ie_len; + u8 *ssid_ie; + char ssid[NDIS_802_11_LENGTH_SSID + 1]; + sint ssid_len = 0; + u8 ignore_broadcast_ssid; + + if (check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE) + return -EPERM; + + if (param->u.bcn_ie.reserved[0] != 0xea) + return -EINVAL; + + mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1]; + + ie_len = len - 12 - 2; /* 12 = param header, 2:no packed */ + ssid_ie = rtw_get_ie(param->u.bcn_ie.buf, WLAN_EID_SSID, &ssid_len, ie_len); + + if (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) { + WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network; + WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network; + + _rtw_memcpy(ssid, ssid_ie + 2, ssid_len); + ssid[ssid_len] = 0x0; + + if (0) + RTW_INFO(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), + ssid, ssid_len, + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + + _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len); + pbss_network->Ssid.SsidLength = ssid_len; + _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len); + pbss_network_ext->Ssid.SsidLength = ssid_len; + + if (0) + RTW_INFO(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + } + + RTW_INFO(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter), + ignore_broadcast_ssid, ssid, ssid_len); + + return ret; +} + +static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; + + ret = rtw_acl_remove_sta(padapter, param->sta_addr); + + return ret; + +} + +static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + return -EINVAL; + + ret = rtw_acl_add_sta(padapter, param->sta_addr); + + return ret; + +} + +static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + rtw_set_macaddr_acl(padapter, param->u.mlme.command); + + return ret; +} + +static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) +{ + struct ieee_param *param; + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + /* RTW_INFO("%s\n", __FUNCTION__); */ + + /* + * this function is expect to call in master mode, which allows no power saving + * so, we just check hw_init_completed + */ + + if (!rtw_is_hw_init_completed(padapter)) { + ret = -EPERM; + goto out; + } + + /* if (p->length < sizeof(struct ieee_param) || !p->pointer){ */ + if (!p->pointer) { + ret = -EINVAL; + goto out; + } + + param = (struct ieee_param *)rtw_malloc(p->length); + if (param == NULL) { + ret = -ENOMEM; + goto out; + } + + if (copy_from_user(param, p->pointer, p->length)) { + rtw_mfree((u8 *)param, p->length); + ret = -EFAULT; + goto out; + } + + /* RTW_INFO("%s, cmd=%d\n", __FUNCTION__, param->cmd); */ + + switch (param->cmd) { + case RTL871X_HOSTAPD_FLUSH: + + ret = rtw_hostapd_sta_flush(dev); + + break; + + case RTL871X_HOSTAPD_ADD_STA: + + ret = rtw_add_sta(dev, param); + + break; + + case RTL871X_HOSTAPD_REMOVE_STA: + + ret = rtw_del_sta(dev, param); + + break; + + case RTL871X_HOSTAPD_SET_BEACON: + + ret = rtw_set_beacon(dev, param, p->length); + + break; + + case RTL871X_SET_ENCRYPTION: + + ret = rtw_set_encryption(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_GET_WPAIE_STA: + + ret = rtw_get_sta_wpaie(dev, param); + + break; + + case RTL871X_HOSTAPD_SET_WPS_BEACON: + + ret = rtw_set_wps_beacon(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP: + + ret = rtw_set_wps_probe_resp(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP: + + ret = rtw_set_wps_assoc_resp(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_HIDDEN_SSID: + + ret = rtw_set_hidden_ssid(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_GET_INFO_STA: + + ret = rtw_ioctl_get_sta_data(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_MACADDR_ACL: + ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length); + break; + case RTL871X_HOSTAPD_ACL_ADD_STA: + ret = rtw_ioctl_acl_add_sta(dev, param, p->length); + break; + case RTL871X_HOSTAPD_ACL_REMOVE_STA: + ret = rtw_ioctl_acl_remove_sta(dev, param, p->length); + break; + + default: + RTW_INFO("Unknown hostapd request: %d\n", param->cmd); + ret = -EOPNOTSUPP; + break; + + } + + if (ret == 0 && copy_to_user(p->pointer, param, p->length)) + ret = -EFAULT; + + rtw_mfree((u8 *)param, p->length); + +out: + + return ret; + +} + +static int rtw_wx_set_priv(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ + +#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + char *ext_dbg; +#endif + + int ret = 0; + int len = 0; + char *ext; + int i; + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *dwrq = (struct iw_point *)awrq; + + if (dwrq->length == 0) + return -EFAULT; + + len = dwrq->length; + ext = rtw_vmalloc(len); + if (!ext) + return -ENOMEM; + + if (copy_from_user(ext, dwrq->pointer, len)) { + rtw_vmfree(ext, len); + return -EFAULT; + } + +#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + ext_dbg = rtw_vmalloc(len); + if (!ext_dbg) { + rtw_vmfree(ext, len); + return -ENOMEM; + } + + _rtw_memcpy(ext_dbg, ext, len); +#endif + + /* added for wps2.0 @20110524 */ + if (dwrq->flags == 0x8766 && len > 8) { + u32 cp_sz; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 *probereq_wpsie = ext; + int probereq_wpsie_len = len; + u8 wps_oui[4] = {0x0, 0x50, 0xf2, 0x04}; + + if ((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) && + (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) == _TRUE)) { + cp_sz = probereq_wpsie_len > MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN : probereq_wpsie_len; + + if (pmlmepriv->wps_probe_req_ie) { + u32 free_len = pmlmepriv->wps_probe_req_ie_len; + pmlmepriv->wps_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); + pmlmepriv->wps_probe_req_ie = NULL; + } + + pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz); + if (pmlmepriv->wps_probe_req_ie == NULL) { + printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + ret = -EINVAL; + goto FREE_EXT; + + } + + _rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz); + pmlmepriv->wps_probe_req_ie_len = cp_sz; + + } + + goto FREE_EXT; + + } + + if (len >= WEXT_CSCAN_HEADER_SIZE + && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE + ) { + ret = rtw_wx_set_scan(dev, info, awrq, ext); + goto FREE_EXT; + } + + +FREE_EXT: + + rtw_vmfree(ext, len); + #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + rtw_vmfree(ext_dbg, len); + #endif + + /* RTW_INFO("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n", */ + /* dev->name, ret); */ + + return ret; + +} + + +static int rtw_pm_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + unsigned mode = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + RTW_INFO("[%s] extra = %s\n", __FUNCTION__, extra); + + if (_rtw_memcmp(extra, "lps=", 4)) { + sscanf(extra + 4, "%u", &mode); + ret = rtw_pm_set_lps(padapter, mode); + } else if (_rtw_memcmp(extra, "ips=", 4)) { + sscanf(extra + 4, "%u", &mode); + ret = rtw_pm_set_ips(padapter, mode); + } else if (_rtw_memcmp(extra, "lps_level=", 10)) { + if (sscanf(extra + 10, "%u", &mode) > 0) + ret = rtw_pm_set_lps_level(padapter, mode); + } else + ret = -EINVAL; + + return ret; +} + +static int rtw_mp_efuse_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + PEFUSE_HAL pEfuseHal; + struct iw_point *wrqu; + + u8 *PROMContent = pHalData->efuse_eeprom_data; + u8 ips_mode = IPS_NUM; /* init invalid value */ + u8 lps_mode = PS_MODE_NUM; /* init invalid value */ + struct pwrctrl_priv *pwrctrlpriv ; + u8 *data = NULL; + u8 *rawdata = NULL; + char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00}; + u16 i = 0, j = 0, mapLen = 0, addr = 0, cnts = 0; + u16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0; + u16 mask_len; + u8 mask_buf[64] = ""; + int err; + + wrqu = (struct iw_point *)wdata; + pwrctrlpriv = adapter_to_pwrctl(padapter); + pEfuseHal = &pHalData->EfuseHal; + + err = 0; + data = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); + if (data == NULL) { + err = -ENOMEM; + goto exit; + } + rawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); + if (rawdata == NULL) { + err = -ENOMEM; + goto exit; + } + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) { + err = -EFAULT; + goto exit; + } + lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ + rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + + ips_mode = pwrctrlpriv->ips_mode;/* keep org value */ + rtw_pm_set_ips(padapter, IPS_NONE); + + pch = extra; + RTW_INFO("%s: in=%s\n", __FUNCTION__, extra); + + i = 0; + /* mac 16 "00e04c871200" rmap,00,2 */ + while ((token = strsep(&pch, ",")) != NULL) { + if (i > 2) + break; + tmp[i] = token; + i++; + } + + if (strcmp(tmp[0], "status") == 0) { + sprintf(extra, "Load File efuse=%s,Load File MAC=%s" + , pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK" + , pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK" + ); + goto exit; + } else if (strcmp(tmp[0], "drvmap") == 0) { + static u8 drvmaporder = 0; + u8 *efuse; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (void *)&mapLen, _FALSE); + + efuse = pHalData->efuse_eeprom_data; + + shift = blksz * drvmaporder; + efuse += shift; + cnt = mapLen - shift; + + if (cnt > blksz) { + cnt = blksz; + drvmaporder++; + } else + drvmaporder = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + sprintf(extra, "%s0x%02x\t", extra, shift + i); + for (j = 0; j < 8; j++) + sprintf(extra, "%s%02X ", extra, efuse[i + j]); + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) + sprintf(extra, "%s%02X ", extra, efuse[i + j]); + sprintf(extra, "%s\n", extra); + } + if ((shift + cnt) < mapLen) + sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + + } else if (strcmp(tmp[0], "realmap") == 0) { + static u8 order = 0; + u8 *efuse; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE); + efuse = pEfuseHal->fakeEfuseInitMap; + if (rtw_efuse_mask_map_read(padapter, 0, mapLen, efuse) == _FAIL) { + RTW_INFO("%s: read realmap Fail!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + shift = blksz * order; + efuse += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + order++; + } else + order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + sprintf(extra, "%s0x%02x\t", extra, shift + i); + for (j = 0; j < 8; j++) + sprintf(extra, "%s%02X ", extra, efuse[i + j]); + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) + sprintf(extra, "%s%02X ", extra, efuse[i + j]); + sprintf(extra, "%s\n", extra); + } + if ((shift + cnt) < mapLen) + sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + } else if (strcmp(tmp[0], "rmap") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + + /* rmap addr cnts */ + addr = simple_strtoul(tmp[1], &ptmp, 16); + RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) { + RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (PVOID)&max_available_len, _FALSE); + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EINVAL; + goto exit; + } + + if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) { + RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__); + err = -EFAULT; + goto exit; + } + + /* RTW_INFO("%s: data={", __FUNCTION__); */ + *extra = 0; + for (i = 0; i < cnts; i++) { + /* RTW_INFO("0x%02x ", data[i]); */ + sprintf(extra, "%s0x%02X ", extra, data[i]); + } + /* RTW_INFO("}\n"); */ + } else if (strcmp(tmp[0], "realraw") == 0) { + static u8 raw_order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + + addr = 0; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN , (PVOID)&mapLen, _FALSE); + RTW_INFO("Real content len = %d\n",mapLen ); + + if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); + err = -EFAULT; + goto exit; + } + + _rtw_memset(extra, '\0', strlen(extra)); + + shift = blksz * raw_order; + rawdata += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + raw_order++; + } else + raw_order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + sprintf(extra, "%s0x%02x\t", extra, shift + i); + for (j = 0; j < 8; j++) + sprintf(extra, "%s%02X ", extra, rawdata[i + j]); + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) + sprintf(extra, "%s%02X ", extra, rawdata[i + j]); + sprintf(extra, "%s\n", extra); + } + if ((shift + cnt) < mapLen) + sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + + } else if (strcmp(tmp[0], "btrealraw") == 0) { + static u8 bt_raw_order = 0; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + + addr = 0; + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&mapLen, _FALSE); + RTW_INFO("Real content len = %d\n", mapLen); + if (rtw_efuse_bt_access(padapter, _FALSE, 0, mapLen, rawdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_access Fail!!\n", __func__); + err = -EFAULT; + goto exit; + } + _rtw_memset(extra, '\0', strlen(extra)); + + shift = blksz * bt_raw_order; + rawdata += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + bt_raw_order++; + } else + bt_raw_order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + sprintf(extra, "%s0x%02x\t", extra, shift + i); + for (j = 0; j < 8; j++) + sprintf(extra, "%s%02X ", extra, rawdata[i + j]); + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) + sprintf(extra, "%s%02X ", extra, rawdata[i + j]); + sprintf(extra, "%s\n", extra); + } + if ((shift + cnt) < mapLen) + sprintf(extra, "%s\t...more (left:%d/%d)\n", extra, mapLen-(shift + cnt), mapLen); + + } else if (strcmp(tmp[0], "mac") == 0) { + if (hal_efuse_macaddr_offset(padapter) == -1) { + err = -EFAULT; + goto exit; + } + + addr = hal_efuse_macaddr_offset(padapter); + cnts = 6; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) { + RTW_INFO("%s: rtw_efuse_mask_map_read error!\n", __func__); + err = -EFAULT; + goto exit; + } + + /* RTW_INFO("%s: MAC address={", __FUNCTION__); */ + *extra = 0; + for (i = 0; i < cnts; i++) { + /* RTW_INFO("%02X", data[i]); */ + sprintf(extra, "%s%02X", extra, data[i]); + if (i != (cnts - 1)) { + /* RTW_INFO(":"); */ + sprintf(extra, "%s:", extra); + } + } + /* RTW_INFO("}\n"); */ + } else if (strcmp(tmp[0], "vidpid") == 0) { + cnts = 4; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) { + RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + /* RTW_INFO("%s: {VID,PID}={", __FUNCTION__); */ + *extra = 0; + for (i = 0; i < cnts; i++) { + /* RTW_INFO("0x%02x", data[i]); */ + sprintf(extra, "%s0x%02X", extra, data[i]); + if (i != (cnts - 1)) { + /* RTW_INFO(","); */ + sprintf(extra, "%s,", extra); + } + } + /* RTW_INFO("}\n"); */ + } else if (strcmp(tmp[0], "ableraw") == 0) { + raw_maxsize = efuse_GetavailableSize(padapter); + sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize); + } else if (strcmp(tmp[0], "btableraw") == 0) { + efuse_bt_GetCurrentSize(padapter, &raw_cursize); + raw_maxsize = efuse_bt_GetMaxSize(padapter); + sprintf(extra, "[available raw size]= %d bytes\n", raw_maxsize - raw_cursize); + } else if (strcmp(tmp[0], "btfmap") == 0) { + + BTEfuse_PowerSwitch(padapter, 1, _TRUE); + + mapLen = EFUSE_BT_MAX_MAP_LEN; + if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) { + RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ + sprintf(extra, "\n"); + for (i = 0; i < 512; i += 16) { /* set 512 because the iwpriv's extra size have limit 0x7FF */ + /* RTW_INFO("0x%03x\t", i); */ + sprintf(extra, "%s0x%03x\t", extra, i); + for (j = 0; j < 8; j++) { + /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + } + /* RTW_INFO("\t"); */ + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) { + /* RTW_INFO("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + } + /* RTW_INFO("\n"); */ + sprintf(extra, "%s\n", extra); + } + /* RTW_INFO("\n"); */ + } else if (strcmp(tmp[0], "btbmap") == 0) { + BTEfuse_PowerSwitch(padapter, 1, _TRUE); + + mapLen = EFUSE_BT_MAX_MAP_LEN; + if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) { + RTW_INFO("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ + sprintf(extra, "\n"); + for (i = 512; i < 1024 ; i += 16) { + /* RTW_INFO("0x%03x\t", i); */ + sprintf(extra, "%s0x%03x\t", extra, i); + for (j = 0; j < 8; j++) { + /* RTW_INFO("%02X ", data[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + } + /* RTW_INFO("\t"); */ + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) { + /* RTW_INFO("%02X ", data[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i + j]); + } + /* RTW_INFO("\n"); */ + sprintf(extra, "%s\n", extra); + } + /* RTW_INFO("\n"); */ + } else if (strcmp(tmp[0], "btrmap") == 0) { + u8 BTStatus; + + rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */ + BTStatus = rtw_read8(padapter, 0xa0); + + RTW_INFO("%s: Check 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus); + if (BTStatus != 0x04) { + sprintf(extra, "BT Status not Active ,can't to read BT eFuse\n"); + goto exit; + } + + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + BTEfuse_PowerSwitch(padapter, 1, _TRUE); + + /* rmap addr cnts */ + addr = simple_strtoul(tmp[1], &ptmp, 16); + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) { + RTW_INFO("%s: btrmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) { + RTW_INFO("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + *extra = 0; + /* RTW_INFO("%s: bt efuse data={", __FUNCTION__); */ + for (i = 0; i < cnts; i++) { + /* RTW_INFO("0x%02x ", data[i]); */ + sprintf(extra, "%s 0x%02X ", extra, data[i]); + } + /* RTW_INFO("}\n"); */ + RTW_INFO(FUNC_ADPT_FMT ": BT MAC=[%s]\n", FUNC_ADPT_ARG(padapter), extra); + } else if (strcmp(tmp[0], "btffake") == 0) { + /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ + sprintf(extra, "\n"); + for (i = 0; i < 512; i += 16) { + /* RTW_INFO("0x%03x\t", i); */ + sprintf(extra, "%s0x%03x\t", extra, i); + for (j = 0; j < 8; j++) { + /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + } + /* RTW_INFO("\t"); */ + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) { + /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + } + /* RTW_INFO("\n"); */ + sprintf(extra, "%s\n", extra); + } + /* RTW_INFO("\n"); */ + } else if (strcmp(tmp[0], "btbfake") == 0) { + /* RTW_INFO("OFFSET\tVALUE(hex)\n"); */ + sprintf(extra, "\n"); + for (i = 512; i < 1024; i += 16) { + /* RTW_INFO("0x%03x\t", i); */ + sprintf(extra, "%s0x%03x\t", extra, i); + for (j = 0; j < 8; j++) { + /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + } + /* RTW_INFO("\t"); */ + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) { + /* RTW_INFO("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); */ + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + } + /* RTW_INFO("\n"); */ + sprintf(extra, "%s\n", extra); + } + /* RTW_INFO("\n"); */ + } else if (strcmp(tmp[0], "wlrfkmap") == 0) { + static u8 fk_order = 0; + u8 *efuse; + u32 shift, cnt; + u32 blksz = 0x200; /* The size of one time show, default 512 */ + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&mapLen, _FALSE); + efuse = pEfuseHal->fakeEfuseModifiedMap; + + shift = blksz * fk_order; + efuse += shift; + cnt = mapLen - shift; + if (cnt > blksz) { + cnt = blksz; + fk_order++; + } else + fk_order = 0; + + sprintf(extra, "\n"); + for (i = 0; i < cnt; i += 16) { + sprintf(extra, "%s0x%02x\t", extra, shift + i); + for (j = 0; j < 8; j++) + sprintf(extra, "%s%02X ", extra, efuse[i + j]); + sprintf(extra, "%s\t", extra); + for (; j < 16; j++) + sprintf(extra, "%s%02X ", extra, efuse[i + j]); + sprintf(extra, "%s\n", extra); + } + if ((shift + cnt) < mapLen) + sprintf(extra, "%s\t...more\n", extra); + + } else if (strcmp(tmp[0], "wlrfkrmap") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + /* rmap addr cnts */ + addr = simple_strtoul(tmp[1], &ptmp, 16); + RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) { + RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + + /* RTW_INFO("%s: data={", __FUNCTION__); */ + *extra = 0; + for (i = 0; i < cnts; i++) { + RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeEfuseModifiedMap[addr + i]); + sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeEfuseModifiedMap[addr + i]); + } + } else if (strcmp(tmp[0], "btrfkrmap") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + RTW_INFO("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + /* rmap addr cnts */ + addr = simple_strtoul(tmp[1], &ptmp, 16); + RTW_INFO("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) { + RTW_INFO("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + + /* RTW_INFO("%s: data={", __FUNCTION__); */ + *extra = 0; + for (i = 0; i < cnts; i++) { + RTW_INFO("wlrfkrmap = 0x%02x\n", pEfuseHal->fakeBTEfuseModifiedMap[addr + i]); + sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[addr + i]); + } + } else if (strcmp(tmp[0], "mask") == 0) { + *extra = 0; + mask_len = sizeof(u8) * rtw_get_efuse_mask_arraylen(padapter); + rtw_efuse_mask_array(padapter, mask_buf); + + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) + _rtw_memcpy(mask_buf, maskfileBuffer, mask_len); + + sprintf(extra, "\n"); + for (i = 0; i < mask_len; i++) + sprintf(extra, "%s0x%02X\n", extra, mask_buf[i]); + + } else + sprintf(extra, "Command not found!"); + +exit: + if (data) + rtw_mfree(data, EFUSE_BT_MAX_MAP_LEN); + if (rawdata) + rtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN); + if (!err) + wrqu->length = strlen(extra); + + if (padapter->registrypriv.mp_mode == 0) { + rtw_pm_set_ips(padapter, ips_mode); + + rtw_pm_set_lps(padapter, lps_mode); + } + + return err; +} + +static int rtw_mp_efuse_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + struct iw_point *wrqu; + PADAPTER padapter; + struct pwrctrl_priv *pwrctrlpriv ; + PHAL_DATA_TYPE pHalData; + PEFUSE_HAL pEfuseHal; + struct hal_ops *pHalFunc; + struct mp_priv *pmp_priv; + + u8 ips_mode = IPS_NUM; /* init invalid value */ + u8 lps_mode = PS_MODE_NUM; /* init invalid value */ + u32 i = 0, j = 0, jj, kk; + u8 *setdata = NULL; + u8 *ShadowMapBT = NULL; + u8 *ShadowMapWiFi = NULL; + u8 *setrawdata = NULL; + char *pch, *ptmp, *token, *tmp[3] = {0x00, 0x00, 0x00}; + u16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0; + u16 wifimaplen; + int err; + + wrqu = (struct iw_point *)wdata; + padapter = rtw_netdev_priv(dev); + pwrctrlpriv = adapter_to_pwrctl(padapter); + pHalData = GET_HAL_DATA(padapter); + pEfuseHal = &pHalData->EfuseHal; + pHalFunc = &padapter->hal_func; + pmp_priv = &padapter->mppriv; + + err = 0; + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (void *)&wifimaplen, _FALSE); + + setdata = rtw_zmalloc(1024); + if (setdata == NULL) { + err = -ENOMEM; + goto exit; + } + ShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN); + if (ShadowMapBT == NULL) { + err = -ENOMEM; + goto exit; + } + ShadowMapWiFi = rtw_malloc(wifimaplen); + if (ShadowMapWiFi == NULL) { + err = -ENOMEM; + goto exit; + } + setrawdata = rtw_malloc(EFUSE_MAX_SIZE); + if (setrawdata == NULL) { + err = -ENOMEM; + goto exit; + } + + lps_mode = pwrctrlpriv->power_mgnt;/* keep org value */ + rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + + ips_mode = pwrctrlpriv->ips_mode;/* keep org value */ + rtw_pm_set_ips(padapter, IPS_NONE); + + pch = extra; + RTW_INFO("%s: in=%s\n", __FUNCTION__, extra); + + i = 0; + while ((token = strsep(&pch, ",")) != NULL) { + if (i > 2) + break; + tmp[i] = token; + i++; + } + + /* tmp[0],[1],[2] */ + /* wmap,addr,00e04c871200 */ + if (strcmp(tmp[0], "wmap") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: map data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); + + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + *extra = 0; + RTW_INFO("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__); + if (rtw_efuse_mask_map_read(padapter, addr, cnts, ShadowMapWiFi) == _SUCCESS) { + if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)setdata, cnts)) { + RTW_INFO("%s: WiFi write map afterf compare success\n", __FUNCTION__); + sprintf(extra, "WiFi write map compare OK\n"); + err = 0; + goto exit; + } else { + sprintf(extra, "WiFi write map compare FAIL\n"); + RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__); + err = 0; + goto exit; + } + } + } else if (strcmp(tmp[0], "wraw") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + + if (rtw_efuse_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + } else if (strcmp(tmp[0], "btwraw") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: raw data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setrawdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + if (rtw_efuse_bt_access(padapter, _TRUE, addr, cnts, setrawdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_access error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + } else if (strcmp(tmp[0], "mac") == 0) { + if (tmp[1] == NULL) { + err = -EINVAL; + goto exit; + } + + /* mac,00e04c871200 */ + + if (hal_efuse_macaddr_offset(padapter) == -1) { + err = -EFAULT; + goto exit; + } + + addr = hal_efuse_macaddr_offset(padapter); + cnts = strlen(tmp[1]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + if (cnts > 6) { + RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]); + err = -EFAULT; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); + + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + } else if (strcmp(tmp[0], "vidpid") == 0) { + if (tmp[1] == NULL) { + err = -EINVAL; + goto exit; + } + + cnts = strlen(tmp[1]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: VID/PID=%s\n", __FUNCTION__, tmp[1]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); + if ((addr + cnts) > max_available_len) { + RTW_INFO("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + } else if (strcmp(tmp[0], "wldumpfake") == 0) { + if (wifimaplen > EFUSE_MAX_MAP_LEN) + cnts = EFUSE_MAX_MAP_LEN; + else + cnts = wifimaplen; + if (rtw_efuse_mask_map_read(padapter, 0, cnts, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS) + RTW_INFO("%s: WiFi hw efuse dump to Fake map success\n", __func__); + else { + RTW_INFO("%s: WiFi hw efuse dump to Fake map Fail\n", __func__); + err = -EFAULT; + } + } else if (strcmp(tmp[0], "btwmap") == 0) { + rtw_write8(padapter, 0xa3, 0x05); /* For 8723AB ,8821S ? */ + BTStatus = rtw_read8(padapter, 0xa0); + RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus); + if (BTStatus != 0x04) { + sprintf(extra, "BT Status not Active ,can't do Write\n"); + goto exit; + } + + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: BT data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + setdata[jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + if (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { + RTW_INFO("%s: rtw_BT_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + *extra = 0; + RTW_INFO("%s: after rtw_BT_efuse_map_write to _rtw_memcmp\n", __FUNCTION__); + if ((rtw_BT_efuse_map_read(padapter, addr, cnts, ShadowMapBT) == _SUCCESS)) { + if (_rtw_memcmp((void *)ShadowMapBT , (void *)setdata, cnts)) { + RTW_INFO("%s: BT write map compare OK BTStatus=0x%x\n", __FUNCTION__, BTStatus); + sprintf(extra, "BT write map compare OK"); + err = 0; + goto exit; + } else { + sprintf(extra, "BT write map compare FAIL"); + RTW_INFO("%s: BT write map compare FAIL BTStatus=0x%x\n", __FUNCTION__, BTStatus); + err = 0; + goto exit; + } + } + } else if (strcmp(tmp[0], "btwfake") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: BT tmp data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + pEfuseHal->fakeBTEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + } else if (strcmp(tmp[0], "btdumpfake") == 0) { + if (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS) + RTW_INFO("%s: BT read all map success\n", __FUNCTION__); + else { + RTW_INFO("%s: BT read all map Fail!\n", __FUNCTION__); + err = -EFAULT; + } + } else if (strcmp(tmp[0], "btfk2map") == 0) { + rtw_write8(padapter, 0xa3, 0x05); + BTStatus = rtw_read8(padapter, 0xa0); + RTW_INFO("%s: btwmap before read 0xa0 BT Status =0x%x\n", __FUNCTION__, BTStatus); + if (BTStatus != 0x04) { + sprintf(extra, "BT Status not Active Write FAIL\n"); + goto exit; + } + _rtw_memcpy(pEfuseHal->BTEfuseModifiedMap, pEfuseHal->fakeBTEfuseModifiedMap, EFUSE_BT_MAX_MAP_LEN); + + if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) { + RTW_INFO("%s: rtw_BT_efuse_map_write error!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + RTW_INFO("pEfuseHal->fakeBTEfuseModifiedMap OFFSET\tVALUE(hex)\n"); + for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) { + printk("0x%02x\t", i); + for (j = 0; j < 8; j++) + printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + printk("\t"); + + for (; j < 16; j++) + printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i + j]); + printk("\n"); + } + printk("\n"); + err = -EFAULT; + RTW_INFO("%s: rtw_BT_efuse_map_read _rtw_memcmp\n", __FUNCTION__); + if ((rtw_BT_efuse_map_read(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS)) { + if (_rtw_memcmp((void *)pEfuseHal->fakeBTEfuseModifiedMap, (void *)pEfuseHal->fakeBTEfuseInitMap, EFUSE_BT_MAX_MAP_LEN)) { + sprintf(extra, "BT write map compare OK"); + RTW_INFO("%s: BT write map afterf compare success BTStatus=0x%x\n", __FUNCTION__, BTStatus); + err = 0; + goto exit; + } else { + sprintf(extra, "BT write map compare FAIL"); + if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) + RTW_INFO("%s: rtw_BT_efuse_map_write compare error,retry = %d!\n", __FUNCTION__, i); + + if (rtw_BT_efuse_map_read(padapter, EFUSE_BT, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS) { + RTW_INFO("pEfuseHal->fakeBTEfuseInitMap OFFSET\tVALUE(hex)\n"); + + for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) { + printk("0x%02x\t", i); + for (j = 0; j < 8; j++) + printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]); + printk("\t"); + for (; j < 16; j++) + printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i + j]); + printk("\n"); + } + printk("\n"); + } + RTW_INFO("%s: BT write map afterf compare not match to write efuse try write Map again , BTStatus=0x%x\n", __FUNCTION__, BTStatus); + goto exit; + } + } + + } else if (strcmp(tmp[0], "wlfk2map") == 0) { + *extra = 0; + + if (padapter->registrypriv.bFileMaskEfuse != _TRUE && pmp_priv->bloadefusemap == _TRUE) { + RTW_INFO("%s: File eFuse mask file not to be loaded\n", __FUNCTION__); + sprintf(extra, "Not load eFuse mask file yet, Please use the efuse_mask CMD.\n"); + err = 0; + goto exit; + } + + if (wifimaplen > EFUSE_MAX_MAP_LEN) + cnts = EFUSE_MAX_MAP_LEN; + else + cnts = wifimaplen; + if (rtw_efuse_map_write(padapter, 0x00, cnts, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) { + RTW_INFO("%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_mask_map_read(padapter, 0x00, wifimaplen, ShadowMapWiFi) == _SUCCESS) { + if (_rtw_memcmp((void *)ShadowMapWiFi , (void *)pEfuseHal->fakeEfuseModifiedMap, cnts)) { + RTW_INFO("%s: WiFi write map afterf compare OK\n", __FUNCTION__); + sprintf(extra, "WiFi write map compare OK\n"); + err = 0; + goto exit; + } else { + sprintf(extra, "WiFi write map compare FAIL\n"); + RTW_INFO("%s: WiFi write map compare Fail\n", __FUNCTION__); + err = 0; + goto exit; + } + } + } else if (strcmp(tmp[0], "wlwfake") == 0) { + if ((tmp[1] == NULL) || (tmp[2] == NULL)) { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: map tmp data=%s\n", __FUNCTION__, tmp[2]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[2][kk], tmp[2][kk + 1]); + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "wlwfake OK\n"); + + } + else if (strcmp(tmp[0], "wfakemac") == 0) { + if (tmp[1] == NULL) { + err = -EINVAL; + goto exit; + } + /* wfakemac,00e04c871200 */ + if (hal_efuse_macaddr_offset(padapter) == -1) { + err = -EFAULT; + goto exit; + } + + addr = hal_efuse_macaddr_offset(padapter); + cnts = strlen(tmp[1]); + if (cnts % 2) { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) { + err = -EINVAL; + goto exit; + } + if (cnts > 6) { + RTW_INFO("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]); + err = -EFAULT; + goto exit; + } + + RTW_INFO("%s: addr=0x%X\n", __FUNCTION__, addr); + RTW_INFO("%s: cnts=%d\n", __FUNCTION__, cnts); + RTW_INFO("%s: MAC address=%s\n", __FUNCTION__, tmp[1]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) + pEfuseHal->fakeEfuseModifiedMap[addr + jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "write mac addr to fake map OK\n"); + } else if(strcmp(tmp[0], "update") == 0) { + RTW_INFO("To Use new eFuse map\n"); + /*step read efuse/eeprom data and get mac_addr*/ + rtw_hal_read_chip_info(padapter); + /* set mac addr*/ + rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); + _rtw_memcpy(padapter->pnetdev->dev_addr, get_hal_mac_addr(padapter), ETH_ALEN); /* set mac addr to net_device */ + + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); + rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */ + /*pHalFunc->hal_deinit(padapter);*/ + if (pHalFunc->hal_init(padapter) == _FAIL) { + err = -EINVAL; + goto exit; + } + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "eFuse Update OK\n"); + } + +exit: + if (setdata) + rtw_mfree(setdata, 1024); + if (ShadowMapBT) + rtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN); + if (ShadowMapWiFi) + rtw_mfree(ShadowMapWiFi, wifimaplen); + if (setrawdata) + rtw_mfree(setrawdata, EFUSE_MAX_SIZE); + + wrqu->length = strlen(extra); + + if (padapter->registrypriv.mp_mode == 0) { + rtw_pm_set_ips(padapter, ips_mode); + + rtw_pm_set_lps(padapter, lps_mode); + } + + return err; +} + + +static int rtw_priv_mp_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + + switch (subcmd) { + case CTA_TEST: + RTW_INFO("set CTA_TEST\n"); + rtw_cta_test_start(dev, info, wdata, extra); + break; + case MP_DISABLE_BT_COEXIST: + RTW_INFO("set case MP_DISABLE_BT_COEXIST\n"); + rtw_mp_disable_bt_coexist(dev, info, wdata, extra); + break; + case MP_IQK: + RTW_INFO("set MP_IQK\n"); + rtw_mp_iqk(dev, info, wrqu, extra); + break; + case MP_LCK: + RTW_INFO("set MP_LCK\n"); + rtw_mp_lck(dev, info, wrqu, extra); + break; + + default: + return -EIO; + } + + return 0; +} + +static int rtw_priv_mp_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + + switch (subcmd) { + case MP_START: + RTW_INFO("set case mp_start\n"); + rtw_mp_start(dev, info, wrqu, extra); + break; + case MP_STOP: + RTW_INFO("set case mp_stop\n"); + rtw_mp_stop(dev, info, wrqu, extra); + break; + case MP_BANDWIDTH: + RTW_INFO("set case mp_bandwidth\n"); + rtw_mp_bandwidth(dev, info, wrqu, extra); + break; + case MP_RESET_STATS: + RTW_INFO("set case MP_RESET_STATS\n"); + rtw_mp_reset_stats(dev, info, wrqu, extra); + break; + case MP_SetRFPathSwh: + RTW_INFO("set MP_SetRFPathSwitch\n"); + rtw_mp_SetRFPath(dev, info, wrqu, extra); + break; + case WRITE_REG: + rtw_mp_write_reg(dev, info, wrqu, extra); + break; + case WRITE_RF: + rtw_mp_write_rf(dev, info, wrqu, extra); + break; + case MP_PHYPARA: + RTW_INFO("mp_get MP_PHYPARA\n"); + rtw_mp_phypara(dev, info, wrqu, extra); + break; + case MP_CHANNEL: + RTW_INFO("set case mp_channel\n"); + rtw_mp_channel(dev , info, wrqu, extra); + break; + case READ_REG: + RTW_INFO("mp_get READ_REG\n"); + rtw_mp_read_reg(dev, info, wrqu, extra); + break; + case READ_RF: + RTW_INFO("mp_get READ_RF\n"); + rtw_mp_read_rf(dev, info, wrqu, extra); + break; + case MP_RATE: + RTW_INFO("set case mp_rate\n"); + rtw_mp_rate(dev, info, wrqu, extra); + break; + case MP_TXPOWER: + RTW_INFO("set case MP_TXPOWER\n"); + rtw_mp_txpower(dev, info, wrqu, extra); + break; + case MP_ANT_TX: + RTW_INFO("set case MP_ANT_TX\n"); + rtw_mp_ant_tx(dev, info, wrqu, extra); + break; + case MP_ANT_RX: + RTW_INFO("set case MP_ANT_RX\n"); + rtw_mp_ant_rx(dev, info, wrqu, extra); + break; + case MP_QUERY: + rtw_mp_trx_query(dev, info, wrqu, extra); + break; + case MP_CTX: + RTW_INFO("set case MP_CTX\n"); + rtw_mp_ctx(dev, info, wrqu, extra); + break; + case MP_ARX: + RTW_INFO("set case MP_ARX\n"); + rtw_mp_arx(dev, info, wrqu, extra); + break; + case MP_DUMP: + RTW_INFO("set case MP_DUMP\n"); + rtw_mp_dump(dev, info, wrqu, extra); + break; + case MP_PSD: + RTW_INFO("set case MP_PSD\n"); + rtw_mp_psd(dev, info, wrqu, extra); + break; + case MP_THER: + RTW_INFO("set case MP_THER\n"); + rtw_mp_thermal(dev, info, wrqu, extra); + break; + case MP_PwrCtlDM: + RTW_INFO("set MP_PwrCtlDM\n"); + rtw_mp_PwrCtlDM(dev, info, wrqu, extra); + break; + case MP_QueryDrvStats: + RTW_INFO("mp_get MP_QueryDrvStats\n"); + rtw_mp_QueryDrv(dev, info, wdata, extra); + break; + case MP_PWRTRK: + RTW_INFO("set case MP_PWRTRK\n"); + rtw_mp_pwrtrk(dev, info, wrqu, extra); + break; + case EFUSE_SET: + RTW_INFO("set case efuse set\n"); + rtw_mp_efuse_set(dev, info, wdata, extra); + break; + case EFUSE_GET: + RTW_INFO("efuse get EFUSE_GET\n"); + rtw_mp_efuse_get(dev, info, wdata, extra); + break; + case MP_GET_TXPOWER_INX: + RTW_INFO("mp_get MP_GET_TXPOWER_INX\n"); + rtw_mp_txpower_index(dev, info, wrqu, extra); + break; + case MP_GETVER: + RTW_INFO("mp_get MP_GETVER\n"); + rtw_mp_getver(dev, info, wdata, extra); + break; + case MP_MON: + RTW_INFO("mp_get MP_MON\n"); + rtw_mp_mon(dev, info, wdata, extra); + break; + case EFUSE_MASK: + RTW_INFO("mp_get EFUSE_MASK\n"); + rtw_efuse_mask_file(dev, info, wdata, extra); + break; + case EFUSE_FILE: + RTW_INFO("mp_get EFUSE_FILE\n"); + rtw_efuse_file_map(dev, info, wdata, extra); + break; + case MP_TX: + RTW_INFO("mp_get MP_TX\n"); + rtw_mp_tx(dev, info, wdata, extra); + break; + case MP_RX: + RTW_INFO("mp_get MP_RX\n"); + rtw_mp_rx(dev, info, wdata, extra); + break; + case MP_HW_TX_MODE: + RTW_INFO("mp_get MP_HW_TX_MODE\n"); + rtw_mp_hwtx(dev, info, wdata, extra); + break; + default: + return -EIO; + } + + return 0; +} + + +static int rtw_priv_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (padapter == NULL) + return -ENETDOWN; + + if (padapter->bup == _FALSE) { + RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__); + return -ENETDOWN; + } + + if (RTW_CANNOT_RUN(padapter)) { + RTW_INFO("%s fail =>(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", __func__); + return -ENETDOWN; + } + + if (extra == NULL) { + wrqu->length = 0; + return -EIO; + } + + if (subcmd < MP_NULL) { + rtw_priv_mp_set(dev, info, wdata, extra); + return 0; + } + + switch (subcmd) { + default: + return -EIO; + } + + return 0; +} + +static int rtw_priv_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (padapter == NULL) + return -ENETDOWN; + + if (padapter->bup == _FALSE) { + RTW_INFO(" %s fail =>(padapter->bup == _FALSE )\n", __FUNCTION__); + return -ENETDOWN; + } + + if (RTW_CANNOT_RUN(padapter)) { + RTW_INFO("%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)\n", __func__); + return -ENETDOWN; + } + + if (extra == NULL) { + wrqu->length = 0; + return -EIO; + } + + if (subcmd < MP_NULL) { + rtw_priv_mp_get(dev, info, wdata, extra); + return 0; + } + + switch (subcmd) { + default: + return -EIO; + } + + rtw_msleep_os(10); /* delay 5ms for sending pkt before exit adb shell operation */ + return 0; +} + +static int rtw_tdls(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + + return ret; +} + +static int rtw_tdls_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + + return ret; +} + + +static int rtw_test( + struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + u32 len; + u8 *pbuf, *pch; + char *ptmp; + u8 *delim = ","; + PADAPTER padapter = rtw_netdev_priv(dev); + + RTW_INFO("+%s\n", __func__); + len = wrqu->data.length; + + pbuf = (u8 *)rtw_zmalloc(len); + if (pbuf == NULL) { + RTW_INFO("%s: no memory!\n", __func__); + return -ENOMEM; + } + + if (copy_from_user(pbuf, wrqu->data.pointer, len)) { + rtw_mfree(pbuf, len); + RTW_INFO("%s: copy from user fail!\n", __func__); + return -EFAULT; + } + RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf); + + ptmp = (char *)pbuf; + pch = strsep(&ptmp, delim); + if ((pch == NULL) || (strlen(pch) == 0)) { + rtw_mfree(pbuf, len); + RTW_INFO("%s: parameter error(level 1)!\n", __func__); + return -EFAULT; + } + + + if (strcmp(pch, "bton") == 0) { + rtw_btcoex_SetManualControl(padapter, _FALSE); + goto free_buf; + } else if (strcmp(pch, "btoff") == 0) { + rtw_btcoex_SetManualControl(padapter, _TRUE); + goto free_buf; + } + + if (strcmp(pch, "h2c") == 0) { + u8 param[8]; + u8 count = 0; + u32 tmp; + u8 i; + u32 pos; + u8 ret; + + do { + pch = strsep(&ptmp, delim); + if ((pch == NULL) || (strlen(pch) == 0)) + break; + + sscanf(pch, "%x", &tmp); + param[count++] = (u8)tmp; + } while (count < 8); + + if (count == 0) { + rtw_mfree(pbuf, len); + RTW_INFO("%s: parameter error(level 2)!\n", __func__); + return -EFAULT; + } + + ret = rtw_test_h2c_cmd(padapter, param, count); + + pos = sprintf(extra, "H2C ID=0x%02x content=", param[0]); + for (i = 1; i < count; i++) + pos += sprintf(extra + pos, "%02x,", param[i]); + extra[pos] = 0; + pos--; + pos += sprintf(extra + pos, " %s", ret == _FAIL ? "FAIL" : "OK"); + + wrqu->data.length = strlen(extra) + 1; + + goto free_buf; + } + +free_buf: + rtw_mfree(pbuf, len); + return 0; +} + +static iw_handler rtw_handlers[] = { + NULL, /* SIOCSIWCOMMIT */ + rtw_wx_get_name, /* SIOCGIWNAME */ + dummy, /* SIOCSIWNWID */ + dummy, /* SIOCGIWNWID */ + rtw_wx_set_freq, /* SIOCSIWFREQ */ + rtw_wx_get_freq, /* SIOCGIWFREQ */ + rtw_wx_set_mode, /* SIOCSIWMODE */ + rtw_wx_get_mode, /* SIOCGIWMODE */ + dummy, /* SIOCSIWSENS */ + rtw_wx_get_sens, /* SIOCGIWSENS */ + NULL, /* SIOCSIWRANGE */ + rtw_wx_get_range, /* SIOCGIWRANGE */ + rtw_wx_set_priv, /* SIOCSIWPRIV */ + NULL, /* SIOCGIWPRIV */ + NULL, /* SIOCSIWSTATS */ + NULL, /* SIOCGIWSTATS */ + dummy, /* SIOCSIWSPY */ + dummy, /* SIOCGIWSPY */ + NULL, /* SIOCGIWTHRSPY */ + NULL, /* SIOCWIWTHRSPY */ + rtw_wx_set_wap, /* SIOCSIWAP */ + rtw_wx_get_wap, /* SIOCGIWAP */ + rtw_wx_set_mlme, /* request MLME operation; uses struct iw_mlme */ + dummy, /* SIOCGIWAPLIST -- depricated */ + rtw_wx_set_scan, /* SIOCSIWSCAN */ + rtw_wx_get_scan, /* SIOCGIWSCAN */ + rtw_wx_set_essid, /* SIOCSIWESSID */ + rtw_wx_get_essid, /* SIOCGIWESSID */ + dummy, /* SIOCSIWNICKN */ + rtw_wx_get_nick, /* SIOCGIWNICKN */ + NULL, /* -- hole -- */ + NULL, /* -- hole -- */ + rtw_wx_set_rate, /* SIOCSIWRATE */ + rtw_wx_get_rate, /* SIOCGIWRATE */ + rtw_wx_set_rts, /* SIOCSIWRTS */ + rtw_wx_get_rts, /* SIOCGIWRTS */ + rtw_wx_set_frag, /* SIOCSIWFRAG */ + rtw_wx_get_frag, /* SIOCGIWFRAG */ + dummy, /* SIOCSIWTXPOW */ + dummy, /* SIOCGIWTXPOW */ + dummy, /* SIOCSIWRETRY */ + rtw_wx_get_retry, /* SIOCGIWRETRY */ + rtw_wx_set_enc, /* SIOCSIWENCODE */ + rtw_wx_get_enc, /* SIOCGIWENCODE */ + dummy, /* SIOCSIWPOWER */ + rtw_wx_get_power, /* SIOCGIWPOWER */ + NULL, /*---hole---*/ + NULL, /*---hole---*/ + rtw_wx_set_gen_ie, /* SIOCSIWGENIE */ + NULL, /* SIOCGWGENIE */ + rtw_wx_set_auth, /* SIOCSIWAUTH */ + NULL, /* SIOCGIWAUTH */ + rtw_wx_set_enc_ext, /* SIOCSIWENCODEEXT */ + NULL, /* SIOCGIWENCODEEXT */ + rtw_wx_set_pmkid, /* SIOCSIWPMKSA */ + NULL, /*---hole---*/ +}; + +static const struct iw_priv_args rtw_private_args[] = { + { + SIOCIWFIRSTPRIV + 0x0, + IW_PRIV_TYPE_CHAR | 0x7FF, 0, "write" + }, + { + SIOCIWFIRSTPRIV + 0x1, + IW_PRIV_TYPE_CHAR | 0x7FF, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "read" + }, + { + SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext" + }, + { + SIOCIWFIRSTPRIV + 0x3, 0, 0, "mp_ioctl" + }, + { + SIOCIWFIRSTPRIV + 0x4, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo" + }, + { + SIOCIWFIRSTPRIV + 0x5, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid" + }, + { + SIOCIWFIRSTPRIV + 0x6, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start" + }, + /* for PLATFORM_MT53XX */ + { + SIOCIWFIRSTPRIV + 0x7, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity" + }, + { + SIOCIWFIRSTPRIV + 0x8, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie" + }, + { + SIOCIWFIRSTPRIV + 0x9, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie" + }, + + /* for RTK_DMP_PLATFORM */ + { + SIOCIWFIRSTPRIV + 0xA, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan" + }, + + { + SIOCIWFIRSTPRIV + 0xB, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg" + }, + { + SIOCIWFIRSTPRIV + 0xC, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw" + }, + { + SIOCIWFIRSTPRIV + 0xD, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr" + }, + { + SIOCIWFIRSTPRIV + 0x10, + IW_PRIV_TYPE_CHAR | 1024, 0, "p2p_set" + }, + { + SIOCIWFIRSTPRIV + 0x11, + IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "p2p_get" + }, + { + SIOCIWFIRSTPRIV + 0x12, 0, 0, "NULL" + }, + { + SIOCIWFIRSTPRIV + 0x13, + IW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , "p2p_get2" + }, + { + SIOCIWFIRSTPRIV + 0x14, + IW_PRIV_TYPE_CHAR | 64, 0, "tdls" + }, + { + SIOCIWFIRSTPRIV + 0x15, + IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "tdls_get" + }, + { + SIOCIWFIRSTPRIV + 0x16, + IW_PRIV_TYPE_CHAR | 64, 0, "pm_set" + }, + + {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"}, + {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"}, + {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"}, + { + SIOCIWFIRSTPRIV + 0x1D, + IW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, "test" + }, + + { SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, /* set */ + { SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},/* get + * --- sub-ioctls definitions --- */ + +}; + +static const struct iw_priv_args rtw_mp_private_args[] = { + /* --- sub-ioctls definitions --- */ + { MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" }, + { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" }, + { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" }, + { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" }, + { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"}, + { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, + { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"}, + { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, + { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, + { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, + { READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" }, + { MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"}, + { MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" }, + { MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"}, + { MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"}, + { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"}, + { WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" }, + { WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" }, + { MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"}, + { MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"}, + { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, + { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" }, + { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, + { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"}, + { MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" }, + { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, + { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" }, + { MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" }, + { MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" }, + { MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" }, + { MP_MON, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_mon" }, + { EFUSE_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_mask" }, + { EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_file" }, + { MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" }, + { MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" }, + { MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" }, + { CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"}, + { MP_IQK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_iqk"}, + { MP_LCK, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_lck"}, + +}; + +static iw_handler rtw_private_handler[] = { + rtw_wx_write32, /* 0x00 */ + rtw_wx_read32, /* 0x01 */ + rtw_drvext_hdl, /* 0x02 */ + rtw_wx_priv_null, + /* for MM DTV platform */ + rtw_get_ap_info, /* 0x04 */ + + rtw_set_pid, /* 0x05 */ + rtw_wps_start, /* 0x06 */ + + /* for PLATFORM_MT53XX */ + rtw_wx_get_sensitivity, /* 0x07 */ + rtw_wx_set_mtk_wps_probe_ie, /* 0x08 */ + rtw_wx_set_mtk_wps_ie, /* 0x09 */ + + /* for RTK_DMP_PLATFORM + * Set Channel depend on the country code */ + rtw_wx_set_channel_plan, /* 0x0A */ + + rtw_dbg_port, /* 0x0B */ + rtw_wx_write_rf, /* 0x0C */ + rtw_wx_read_rf, /* 0x0D */ + + rtw_priv_set, /*0x0E*/ + rtw_priv_get, /*0x0F*/ + + rtw_p2p_set, /* 0x10 */ + rtw_p2p_get, /* 0x11 */ + NULL, /* 0x12 */ + rtw_p2p_get2, /* 0x13 */ + + rtw_tdls, /* 0x14 */ + rtw_tdls_get, /* 0x15 */ + + rtw_pm_set, /* 0x16 */ + rtw_wx_priv_null, /* 0x17 */ + rtw_rereg_nd_name, /* 0x18 */ + rtw_wx_priv_null, /* 0x19 */ + rtw_wx_priv_null, /* 0x1A */ + rtw_wx_priv_null, /* 0x1B */ + NULL, /* 0x1C is reserved for hostapd */ + rtw_test, /* 0x1D */ +}; + +static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_statistics *piwstats = &padapter->iwstats; + int tmp_level = 0; + int tmp_qual = 0; + int tmp_noise = 0; + + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) != _TRUE) { + piwstats->qual.qual = 0; + piwstats->qual.level = 0; + piwstats->qual.noise = 0; + /* RTW_INFO("No link level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); */ + } else { + { + /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ + + HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); + + tmp_level = (u8)odm_signal_scale_mapping(&pHal->odmpriv, padapter->recvpriv.signal_strength); + } + + tmp_qual = padapter->recvpriv.signal_qual; + rtw_get_noise(padapter); + tmp_noise = padapter->recvpriv.noise; + /* RTW_INFO("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); */ + + piwstats->qual.level = tmp_level; + piwstats->qual.qual = tmp_qual; + piwstats->qual.noise = tmp_noise; + } + piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;/* |IW_QUAL_DBM; */ + + return &padapter->iwstats; +} + +struct iw_handler_def rtw_handlers_def = { + .standard = rtw_handlers, + .num_standard = sizeof(rtw_handlers) / sizeof(iw_handler), + .get_wireless_stats = rtw_get_wireless_stats, +}; + +/* copy from net/wireless/wext.c start + * ---------------------------------------------------------------- + * + * Calculate size of private arguments + */ +static const char iw_priv_type_size[] = { + 0, /* IW_PRIV_TYPE_NONE */ + 1, /* IW_PRIV_TYPE_BYTE */ + 1, /* IW_PRIV_TYPE_CHAR */ + 0, /* Not defined */ + sizeof(__u32), /* IW_PRIV_TYPE_INT */ + sizeof(struct iw_freq), /* IW_PRIV_TYPE_FLOAT */ + sizeof(struct sockaddr), /* IW_PRIV_TYPE_ADDR */ + 0, /* Not defined */ +}; + +static int get_priv_size(__u16 args) +{ + int num = args & IW_PRIV_SIZE_MASK; + int type = (args & IW_PRIV_TYPE_MASK) >> 12; + + return num * iw_priv_type_size[type]; +} +/* copy from net/wireless/wext.c end */ + +static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data) +{ + int err = 0; + u8 *input = NULL; + u32 input_len = 0; + const char delim[] = " "; + u8 *output = NULL; + u32 output_len = 0; + u32 count = 0; + u8 *buffer = NULL; + u32 buffer_len = 0; + char *ptr = NULL; + u8 cmdname[17] = {0}; /* IFNAMSIZ+1 */ + u32 cmdlen; + s32 len; + u8 *extra = NULL; + u32 extra_size = 0; + + s32 k; + const iw_handler *priv; /* Private ioctl */ + const struct iw_priv_args *priv_args; /* Private ioctl description */ + const struct iw_priv_args *mp_priv_args; /*MP Private ioctl description */ + const struct iw_priv_args *sel_priv_args; /*Selected Private ioctl description */ + u32 num_priv; /* Number of ioctl */ + u32 num_priv_args; /* Number of descriptions */ + u32 num_mp_priv_args; /*Number of MP descriptions */ + u32 num_sel_priv_args; /*Number of Selected descriptions */ + iw_handler handler; + int temp; + int subcmd = 0; /* sub-ioctl index */ + int offset = 0; /* Space for sub-ioctl index */ + + union iwreq_data wdata; + + _rtw_memcpy(&wdata, wrq_data, sizeof(wdata)); + + input_len = wdata.data.length; + if (!input_len) + return -EINVAL; + input = rtw_zmalloc(input_len); + if (NULL == input) + return -ENOMEM; + if (copy_from_user(input, wdata.data.pointer, input_len)) { + err = -EFAULT; + goto exit; + } + input[input_len - 1] = '\0'; + ptr = input; + len = input_len; + + if (ptr == NULL) { + err = -EOPNOTSUPP; + goto exit; + } + + sscanf(ptr, "%16s", cmdname); + cmdlen = strlen(cmdname); + RTW_INFO("%s: cmd=%s\n", __func__, cmdname); + + /* skip command string */ + if (cmdlen > 0) + cmdlen += 1; /* skip one space */ + ptr += cmdlen; + len -= cmdlen; + RTW_INFO("%s: parameters=%s\n", __func__, ptr); + + priv = rtw_private_handler; + priv_args = rtw_private_args; + mp_priv_args = rtw_mp_private_args; + num_priv = sizeof(rtw_private_handler) / sizeof(iw_handler); + num_priv_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args); + num_mp_priv_args = sizeof(rtw_mp_private_args) / sizeof(struct iw_priv_args); + + if (num_priv_args == 0) { + err = -EOPNOTSUPP; + goto exit; + } + + /* Search the correct ioctl */ + k = -1; + sel_priv_args = priv_args; + num_sel_priv_args = num_priv_args; + while + ((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname)) + ; + + /* If not found... */ + if (k == num_sel_priv_args) { + k = -1; + sel_priv_args = mp_priv_args; + num_sel_priv_args = num_mp_priv_args; + while + ((++k < num_sel_priv_args) && strcmp(sel_priv_args[k].name, cmdname)) + ; + + if (k == num_sel_priv_args) { + err = -EOPNOTSUPP; + goto exit; + } + } + + /* Watch out for sub-ioctls ! */ + if (sel_priv_args[k].cmd < SIOCDEVPRIVATE) { + int j = -1; + + /* Find the matching *real* ioctl */ + while ((++j < num_priv_args) && ((priv_args[j].name[0] != '\0') || + (priv_args[j].set_args != sel_priv_args[k].set_args) || + (priv_args[j].get_args != sel_priv_args[k].get_args))) + ; + + /* If not found... */ + if (j == num_priv_args) { + err = -EINVAL; + goto exit; + } + + /* Save sub-ioctl number */ + subcmd = sel_priv_args[k].cmd; + /* Reserve one int (simplify alignment issues) */ + offset = sizeof(__u32); + /* Use real ioctl definition from now on */ + k = j; + } + + buffer = rtw_zmalloc(4096); + if (NULL == buffer) { + err = -ENOMEM; + goto exit; + } + + /* If we have to set some data */ + if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) && + (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) { + u8 *str; + + switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) { + case IW_PRIV_TYPE_BYTE: + /* Fetch args */ + count = 0; + do { + str = strsep(&ptr, delim); + if (NULL == str) + break; + sscanf(str, "%i", &temp); + buffer[count++] = (u8)temp; + } while (1); + buffer_len = count; + + /* Number of args to fetch */ + wdata.data.length = count; + if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) + wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; + + break; + + case IW_PRIV_TYPE_INT: + /* Fetch args */ + count = 0; + do { + str = strsep(&ptr, delim); + if (NULL == str) + break; + sscanf(str, "%i", &temp); + ((s32 *)buffer)[count++] = (s32)temp; + } while (1); + buffer_len = count * sizeof(s32); + + /* Number of args to fetch */ + wdata.data.length = count; + if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) + wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; + + break; + + case IW_PRIV_TYPE_CHAR: + if (len > 0) { + /* Size of the string to fetch */ + wdata.data.length = len; + if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) + wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; + + /* Fetch string */ + _rtw_memcpy(buffer, ptr, wdata.data.length); + } else { + wdata.data.length = 1; + buffer[0] = '\0'; + } + buffer_len = wdata.data.length; + break; + + default: + RTW_INFO("%s: Not yet implemented...\n", __func__); + err = -1; + goto exit; + } + + if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && + (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) { + RTW_INFO("%s: The command %s needs exactly %d argument(s)...\n", + __func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK); + err = -EINVAL; + goto exit; + } + } /* if args to set */ + else + wdata.data.length = 0L; + + /* Those two tests are important. They define how the driver + * will have to handle the data */ + if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && + ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) { + /* First case : all SET args fit within wrq */ + if (offset) + wdata.mode = subcmd; + _rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset); + } else { + if ((priv_args[k].set_args == 0) && + (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && + (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) { + /* Second case : no SET args, GET args fit within wrq */ + if (offset) + wdata.mode = subcmd; + } else { + /* Third case : args won't fit in wrq, or variable number of args */ + if (copy_to_user(wdata.data.pointer, buffer, buffer_len)) { + err = -EFAULT; + goto exit; + } + wdata.data.flags = subcmd; + } + } + + rtw_mfree(input, input_len); + input = NULL; + + extra_size = 0; + if (IW_IS_SET(priv_args[k].cmd)) { + /* Size of set arguments */ + extra_size = get_priv_size(priv_args[k].set_args); + + /* Does it fits in iwr ? */ + if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && + ((extra_size + offset) <= IFNAMSIZ)) + extra_size = 0; + } else { + /* Size of get arguments */ + extra_size = get_priv_size(priv_args[k].get_args); + + /* Does it fits in iwr ? */ + if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && + (extra_size <= IFNAMSIZ)) + extra_size = 0; + } + + if (extra_size == 0) { + extra = (u8 *)&wdata; + rtw_mfree(buffer, 4096); + buffer = NULL; + } else + extra = buffer; + + handler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV]; + err = handler(dev, NULL, &wdata, extra); + + /* If we have to get some data */ + if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) && + (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) { + int j; + int n = 0; /* number of args */ + u8 str[20] = {0}; + + /* Check where is the returned data */ + if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && + (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) + n = priv_args[k].get_args & IW_PRIV_SIZE_MASK; + else + n = wdata.data.length; + + output = rtw_zmalloc(4096); + if (NULL == output) { + err = -ENOMEM; + goto exit; + } + + switch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) { + case IW_PRIV_TYPE_BYTE: + /* Display args */ + for (j = 0; j < n; j++) { + sprintf(str, "%d ", extra[j]); + len = strlen(str); + output_len = strlen(output); + if ((output_len + len + 1) > 4096) { + err = -E2BIG; + goto exit; + } + _rtw_memcpy(output + output_len, str, len); + } + break; + + case IW_PRIV_TYPE_INT: + /* Display args */ + for (j = 0; j < n; j++) { + sprintf(str, "%d ", ((__s32 *)extra)[j]); + len = strlen(str); + output_len = strlen(output); + if ((output_len + len + 1) > 4096) { + err = -E2BIG; + goto exit; + } + _rtw_memcpy(output + output_len, str, len); + } + break; + + case IW_PRIV_TYPE_CHAR: + /* Display args */ + _rtw_memcpy(output, extra, n); + break; + + default: + RTW_INFO("%s: Not yet implemented...\n", __func__); + err = -1; + goto exit; + } + + output_len = strlen(output) + 1; + wrq_data->data.length = output_len; + if (copy_to_user(wrq_data->data.pointer, output, output_len)) { + err = -EFAULT; + goto exit; + } + } /* if args to set */ + else + wrq_data->data.length = 0; + +exit: + if (input) + rtw_mfree(input, input_len); + if (buffer) + rtw_mfree(buffer, 4096); + if (output) + rtw_mfree(output, 4096); + + return err; +} + +static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq) +{ + struct iw_point *iwp; + struct ifreq ifrq; + union iwreq_data wrq_data; + int err = 0; + iwp = &wrq_data.data; + RTW_INFO("%s:...\n", __func__); + if (copy_from_user(iwp, rq->ifr_ifru.ifru_data, sizeof(struct iw_point))) + return -EFAULT; + + err = _rtw_ioctl_wext_private(dev, &wrq_data); + + if (copy_to_user(rq->ifr_ifru.ifru_data, iwp, sizeof(struct iw_point))) + return -EFAULT; + + return err; +} + +static int rtw_ioctl_wext_private(struct net_device *dev, struct ifreq *rq) +{ + return rtw_ioctl_standard_wext_private(dev, rq); +} + +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct iwreq *wrq = (struct iwreq *)rq; + int ret = 0; + + switch (cmd) { + case RTL_IOCTL_WPA_SUPPLICANT: + ret = wpa_supplicant_ioctl(dev, &wrq->u.data); + break; + case RTL_IOCTL_HOSTAPD: + ret = rtw_hostapd_ioctl(dev, &wrq->u.data); + break; + case SIOCSIWMODE: + ret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL); + break; + case SIOCDEVPRIVATE: + ret = rtw_ioctl_wext_private(dev, rq); + break; + case (SIOCDEVPRIVATE+1): + ret = rtw_android_priv_cmd(dev, rq, cmd); + break; + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} diff --git a/drivers/staging/rtl8821ce/os_dep/linux/ioctl_mp.c b/drivers/staging/rtl8821ce/os_dep/linux/ioctl_mp.c new file mode 100644 index 000000000000..4cb366f6ffce --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/ioctl_mp.c @@ -0,0 +1,2071 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> +#include <rtw_mp.h> +#include <rtw_mp_ioctl.h> +#include "../../hal/phydm/phydm_precomp.h" + +/* + * Input Format: %s,%d,%d + * %s is width, could be + * "b" for 1 byte + * "w" for WORD (2 bytes) + * "dw" for DWORD (4 bytes) + * 1st %d is address(offset) + * 2st %d is data to write + */ +int rtw_mp_write_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + char *pch, *pnext, *ptmp; + char *width_str; + char width, buf[5]; + u32 addr, data; + int ret; + PADAPTER padapter = rtw_netdev_priv(dev); + char *input; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + _rtw_memset(extra, 0, wrqu->length); + + pch = input; + + pnext = strpbrk(pch, " ,.-"); + if (pnext == NULL) { + rc = -EINVAL; + goto out; + } + *pnext = 0; + width_str = pch; + + pch = pnext + 1; + pnext = strpbrk(pch, " ,.-"); + if (pnext == NULL) { + rc = -EINVAL; + goto out; + } + *pnext = 0; + /*addr = simple_strtoul(pch, &ptmp, 16); + _rtw_memset(buf, '\0', sizeof(buf)); + _rtw_memcpy(buf, pch, pnext-pch); + ret = kstrtoul(buf, 16, &addr);*/ + ret = sscanf(pch, "%x", &addr); + if (addr > 0x3FFF) { + rc = -EINVAL; + goto out; + } + + pch = pnext + 1; + pnext = strpbrk(pch, " ,.-"); + if ((pch - input) >= wrqu->length) { + rc = -EINVAL; + goto out; + } + /*data = simple_strtoul(pch, &ptmp, 16);*/ + ret = sscanf(pch, "%x", &data); + RTW_INFO("data=%x,addr=%x\n", (u32)data, (u32)addr); + ret = 0; + width = width_str[0]; + switch (width) { + case 'b': + /* 1 byte*/ + if (data > 0xFF) { + rc = -EINVAL; + break; + } + rtw_write8(padapter, addr, data); + break; + case 'w': + /* 2 bytes*/ + if (data > 0xFFFF) { + rc = -EINVAL; + break; + } + rtw_write16(padapter, addr, data); + break; + case 'd': + /* 4 bytes*/ + rtw_write32(padapter, addr, data); + break; + default: + rc = -EINVAL; + break; + } + +out: + kfree(input); + + return rc; +} + +/* + * Input Format: %s,%d + * %s is width, could be + * "b" for 1 byte + * "w" for WORD (2 bytes) + * "dw" for DWORD (4 bytes) + * %d is address(offset) + * + * Return: + * %d for data readed + */ +int rtw_mp_read_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + char *input; + char *pch, *pnext, *ptmp; + char *width_str; + char width; + char data[20], tmp[20], buf[3]; + u32 addr = 0, strtout = 0; + u32 i = 0, j = 0, ret = 0, data32 = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + int rc = 0; + + if (wrqu->length > 128) + return -EFAULT; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + _rtw_memset(extra, 0, wrqu->length); + _rtw_memset(data, '\0', sizeof(data)); + _rtw_memset(tmp, '\0', sizeof(tmp)); + pch = input; + pnext = strpbrk(pch, " ,.-"); + if (pnext == NULL) { + rc = -EINVAL; + goto out; + } + *pnext = 0; + width_str = pch; + + pch = pnext + 1; + + ret = sscanf(pch, "%x", &addr); + if (addr > 0x3FFF) { + rc = -EINVAL; + goto out; + } + + ret = 0; + width = width_str[0]; + + switch (width) { + case 'b': + data32 = rtw_read8(padapter, addr); + RTW_INFO("%x\n", data32); + sprintf(extra, "%d", data32); + wrqu->length = strlen(extra); + break; + case 'w': + /* 2 bytes*/ + sprintf(data, "%04x\n", rtw_read16(padapter, addr)); + + for (i = 0 ; i <= strlen(data) ; i++) { + if (i % 2 == 0) { + tmp[j] = ' '; + j++; + } + if (data[i] != '\0') + tmp[j] = data[i]; + + j++; + } + pch = tmp; + RTW_INFO("pch=%s", pch); + + while (*pch != '\0') { + pnext = strpbrk(pch, " "); + if (!pnext || ((pnext - tmp) > 4)) + break; + + pnext++; + if (*pnext != '\0') { + /*strtout = simple_strtoul(pnext , &ptmp, 16);*/ + ret = sscanf(pnext, "%x", &strtout); + sprintf(extra, "%s %d" , extra , strtout); + } else + break; + pch = pnext; + } + wrqu->length = strlen(extra); + break; + case 'd': + /* 4 bytes */ + sprintf(data, "%08x", rtw_read32(padapter, addr)); + /*add read data format blank*/ + for (i = 0 ; i <= strlen(data) ; i++) { + if (i % 2 == 0) { + tmp[j] = ' '; + j++; + } + if (data[i] != '\0') + tmp[j] = data[i]; + + j++; + } + pch = tmp; + RTW_INFO("pch=%s", pch); + + while (*pch != '\0') { + pnext = strpbrk(pch, " "); + if (!pnext) + break; + + pnext++; + if (*pnext != '\0') { + ret = sscanf(pnext, "%x", &strtout); + sprintf(extra, "%s %d" , extra , strtout); + } else + break; + pch = pnext; + } + wrqu->length = strlen(extra); + break; + + default: + wrqu->length = 0; + rc = -EINVAL; + break; + } + +out: + kfree(input); + + return ret; +} + +/* + * Input Format: %d,%x,%x + * %d is RF path, should be smaller than MAX_RF_PATH_NUMS + * 1st %x is address(offset) + * 2st %x is data to write + */ +int rtw_mp_write_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + u32 path, addr, data; + int ret = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + char *input; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + _rtw_memset(input, 0, wrqu->length); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + ret = sscanf(input, "%d,%x,%x", &path, &addr, &data); + if (ret < 3) { + rc = -EINVAL; + goto out; + } + + if (path >= GET_HAL_RFPATH_NUM(padapter)) { + rc = -EINVAL; + goto out; + } + if (addr > 0xFF) { + rc = -EINVAL; + goto out; + } + if (data > 0xFFFFF) { + rc = -EINVAL; + goto out; + } + + _rtw_memset(extra, 0, wrqu->length); + + write_rfreg(padapter, path, addr, data); + + sprintf(extra, "write_rf completed\n"); + wrqu->length = strlen(extra); + +out: + kfree(input); + + return rc; +} + +/* + * Input Format: %d,%x + * %d is RF path, should be smaller than MAX_RF_PATH_NUMS + * %x is address(offset) + * + * Return: + * %d for data readed + */ +int rtw_mp_read_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + char *input; + char *pch, *pnext, *ptmp; + char data[20], tmp[20], buf[3]; + u32 path, addr, strtou; + u32 ret = 0, i = 0 , j = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + int rc = 0; + + if (wrqu->length > 128) + return -EFAULT; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + _rtw_memset(input, 0, wrqu->length); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + ret = sscanf(input, "%d,%x", &path, &addr); + if (ret < 2) { + rc = -EINVAL; + goto out; + } + + if (path >= GET_HAL_RFPATH_NUM(padapter)) { + rc = -EINVAL; + goto out; + } + if (addr > 0xFF) { + rc = -EINVAL; + goto out; + } + + _rtw_memset(extra, 0, wrqu->length); + + sprintf(data, "%08x", read_rfreg(padapter, path, addr)); + /*add read data format blank*/ + for (i = 0 ; i <= strlen(data) ; i++) { + if (i % 2 == 0) { + tmp[j] = ' '; + j++; + } + tmp[j] = data[i]; + j++; + } + pch = tmp; + RTW_INFO("pch=%s", pch); + + while (*pch != '\0') { + pnext = strpbrk(pch, " "); + if (!pnext) + break; + pnext++; + if (*pnext != '\0') { + /*strtou =simple_strtoul(pnext , &ptmp, 16);*/ + ret = sscanf(pnext, "%x", &strtou); + sprintf(extra, "%s %d" , extra , strtou); + } else + break; + pch = pnext; + } + wrqu->length = strlen(extra); + +out: + kfree(input); + + return rc; +} + +int rtw_mp_start(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int ret = 0; + u8 val8; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct hal_ops *pHalFunc = &padapter->hal_func; + + rtw_pm_set_ips(padapter, IPS_NONE); + LeaveAllPowerSaveMode(padapter); + + if (rtw_mi_check_fwstate(padapter, _FW_UNDER_SURVEY)) + rtw_mi_scan_abort(padapter, _FALSE); + + if (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS) + ret = -EPERM; + + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail"); + wrqu->length = strlen(extra); + + return ret; +} + +int rtw_mp_stop(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int ret = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + struct hal_ops *pHalFunc = &padapter->hal_func; + + if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS) + ret = -EPERM; + + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_stop %s\n", ret == 0 ? "ok" : "fail"); + wrqu->length = strlen(extra); + + return ret; +} + +int rtw_mp_rate(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 rate = MPT_RATE_1M; + char *input; + PADAPTER padapter = rtw_netdev_priv(dev); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + rate = rtw_mpRateParseFunc(padapter, input); + padapter->mppriv.rateidx = rate; + + if (rate == 0 && strcmp(input, "1M") != 0) { + rate = rtw_atoi(input); + padapter->mppriv.rateidx = MRateToHwRate(rate); + /*if (rate <= 0x7f) + rate = wifirate2_ratetbl_inx((u8)rate); + else if (rate < 0xC8) + rate = (rate - 0x79 + MPT_RATE_MCS0); + HT rate 0x80(MCS0) ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159 + VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179 + VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199 + else + VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153 + rate =(rate - MPT_RATE_VHT1SS_MCS0); + */ + } + _rtw_memset(extra, 0, wrqu->length); + + sprintf(extra, "Set data rate to %s index %d" , input, padapter->mppriv.rateidx); + RTW_INFO("%s: %s rate index=%d\n", __func__, input, padapter->mppriv.rateidx); + + if (padapter->mppriv.rateidx >= DESC_RATEVHTSS4MCS9) { + rc = -EINVAL; + goto out; + } + + pMptCtx->mpt_rate_index = HwRateToMPTRate(padapter->mppriv.rateidx); + SetDataRate(padapter); + + wrqu->length = strlen(extra); +out: + kfree(input); + + return rc; +} + +int rtw_mp_channel(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + char *input; + u32 channel = 1; + int cur_ch_offset; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + channel = rtw_atoi(input); + /*RTW_INFO("%s: channel=%d\n", __func__, channel);*/ + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel); + padapter->mppriv.channel = channel; + SetChannel(padapter); + pHalData->current_channel = channel; + + wrqu->length = strlen(extra); + +out: + kfree(input); + return rc; +} + +int rtw_mp_bandwidth(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 bandwidth = 0, sg = 0; + int cur_ch_offset; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + char *input; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + if (sscanf(input, "40M=%d,shortGI=%d", &bandwidth, &sg) > 0) + RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth , sg); + + if (bandwidth == 1) + bandwidth = CHANNEL_WIDTH_40; + else if (bandwidth == 2) + bandwidth = CHANNEL_WIDTH_80; + + padapter->mppriv.bandwidth = (u8)bandwidth; + padapter->mppriv.preamble = sg; + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "Change BW %d to BW %d\n", pHalData->current_channel_bw , bandwidth); + + SetBandwidth(padapter); + pHalData->current_channel_bw = bandwidth; + /*cur_ch_offset = rtw_get_offset_by_ch(padapter->mppriv.channel);*/ + /*set_channel_bwmode(padapter, padapter->mppriv.channel, cur_ch_offset, bandwidth);*/ + wrqu->length = strlen(extra); + +out: + kfree(input); + + return rc; +} + +int rtw_mp_txpower_index(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char *input; + u32 rfpath; + u32 txpower_inx; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (wrqu->length > 128) { + rc = -EFAULT; + goto out; + } + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + rfpath = rtw_atoi(input); + txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath); + sprintf(extra, " %d", txpower_inx); + wrqu->length = strlen(extra); + +out: + kfree(input); + + return rc; +} + +int rtw_mp_txpower(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0, status = 0; + int MsetPower = 1; + char *input; + PADAPTER padapter = rtw_netdev_priv(dev); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + MsetPower = strncmp(input, "off", 3); + if (MsetPower == 0) { + padapter->mppriv.bSetTxPower = 0; + sprintf(extra, "MP Set power off"); + } else { + if (sscanf(input, "patha=%d,pathb=%d,pathc=%d,pathd=%d", &idx_a, &idx_b, &idx_c, &idx_d) < 3) + RTW_INFO("Invalid format on line %s ,patha=%d,pathb=%d,pathc=%d,pathd=%d\n", input , idx_a , idx_b , idx_c , idx_d); + + sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d); + padapter->mppriv.txpoweridx = (u8)idx_a; + + pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)idx_a; + pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)idx_b; + pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)idx_c; + pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)idx_d; + padapter->mppriv.bSetTxPower = 1; + + SetTxPower(padapter); + } + + wrqu->length = strlen(extra); + +out: + kfree(input); + return rc; +} + +int rtw_mp_ant_tx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 i; + char *input; + u16 antenna = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + sprintf(extra, "switch Tx antenna to %s", input); + + for (i = 0; i < strlen(input); i++) { + switch (input[i]) { + case 'a': + antenna |= ANTENNA_A; + break; + case 'b': + antenna |= ANTENNA_B; + break; + case 'c': + antenna |= ANTENNA_C; + break; + case 'd': + antenna |= ANTENNA_D; + break; + } + } + /*antenna |= BIT(extra[i]-'a');*/ + RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + /*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);*/ + pHalData->antenna_tx_path = antenna; + + SetAntenna(padapter); + + wrqu->length = strlen(extra); +out: + kfree(input); + + return rc; +} + +int rtw_mp_ant_rx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 i; + u16 antenna = 0; + char *input; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + /*RTW_INFO("%s: input=%s\n", __func__, input);*/ + _rtw_memset(extra, 0, wrqu->length); + + sprintf(extra, "switch Rx antenna to %s", input); + + for (i = 0; i < strlen(input); i++) { + switch (input[i]) { + case 'a': + antenna |= ANTENNA_A; + break; + case 'b': + antenna |= ANTENNA_B; + break; + case 'c': + antenna |= ANTENNA_C; + break; + case 'd': + antenna |= ANTENNA_D; + break; + } + } + + RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + pHalData->AntennaRxPath = antenna; + /*RTW_INFO("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx);*/ + SetAntenna(padapter); + wrqu->length = strlen(extra); + +out: + kfree(input); + + return rc; +} + +int rtw_set_ctx_destAddr(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int jj, kk = 0; + + struct pkt_attrib *pattrib; + struct mp_priv *pmp_priv; + PADAPTER padapter = rtw_netdev_priv(dev); + + pmp_priv = &padapter->mppriv; + pattrib = &pmp_priv->tx.attrib; + + if (strlen(extra) < 5) + return _FAIL; + + RTW_INFO("%s: in=%s\n", __func__, extra); + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + pattrib->dst[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + RTW_INFO("pattrib->dst:%x %x %x %x %x %x\n", pattrib->dst[0], pattrib->dst[1], pattrib->dst[2], pattrib->dst[3], pattrib->dst[4], pattrib->dst[5]); + return 0; +} + +int rtw_mp_ctx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 pkTx = 1; + int countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1; + u32 bStartTest = 1; + u32 count = 0, pktinterval = 0, pktlen = 0; + u8 status; + struct mp_priv *pmp_priv; + struct pkt_attrib *pattrib; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + pmp_priv = &padapter->mppriv; + pattrib = &pmp_priv->tx.attrib; + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + RTW_INFO("%s: in=%s\n", __func__, extra); + countPkTx = strncmp(extra, "count=", 5); /* strncmp TRUE is 0*/ + cotuTx = strncmp(extra, "background", 20); + CarrSprTx = strncmp(extra, "background,cs", 20); + scTx = strncmp(extra, "background,sc", 20); + sgleTx = strncmp(extra, "background,stone", 20); + pkTx = strncmp(extra, "background,pkt", 20); + stop = strncmp(extra, "stop", 4); + if (sscanf(extra, "count=%d,pkt", &count) > 0) + RTW_INFO("count= %d\n", count); + if (sscanf(extra, "pktinterval=%d", &pktinterval) > 0) + RTW_INFO("pktinterval= %d\n", pktinterval); + + if (sscanf(extra, "pktlen=%d", &pktlen) > 0) + RTW_INFO("pktlen= %d\n", pktlen); + + if (_rtw_memcmp(extra, "destmac=", 8)) { + wrqu->length -= 8; + rtw_set_ctx_destAddr(dev, info, wrqu, &extra[8]); + sprintf(extra, "Set dest mac OK !\n"); + return 0; + } + + /*RTW_INFO("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop);*/ + _rtw_memset(extra, '\0', strlen(extra)); + + if (pktinterval != 0) { + sprintf(extra, "Pkt Interval = %d", pktinterval); + padapter->mppriv.pktInterval = pktinterval; + wrqu->length = strlen(extra); + return 0; + } + if (pktlen != 0) { + sprintf(extra, "Pkt len = %d", pktlen); + pattrib->pktlen = pktlen; + wrqu->length = strlen(extra); + return 0; + } + if (stop == 0) { + bStartTest = 0; /* To set Stop*/ + pmp_priv->tx.stop = 1; + sprintf(extra, "Stop continuous Tx"); + odm_write_dig(&pHalData->odmpriv, 0x20); + } else { + bStartTest = 1; + odm_write_dig(&pHalData->odmpriv, 0x7f); + if (pmp_priv->mode != MP_ON) { + if (pmp_priv->tx.stop != 1) { + RTW_INFO("%s: MP_MODE != ON %d\n", __func__, pmp_priv->mode); + return -EFAULT; + } + } + } + + pmp_priv->tx.count = count; + + if (pkTx == 0 || countPkTx == 0) + pmp_priv->mode = MP_PACKET_TX; + if (sgleTx == 0) + pmp_priv->mode = MP_SINGLE_TONE_TX; + if (cotuTx == 0) + pmp_priv->mode = MP_CONTINUOUS_TX; + if (CarrSprTx == 0) + pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX; + if (scTx == 0) + pmp_priv->mode = MP_SINGLE_CARRIER_TX; + + status = rtw_mp_pretx_proc(padapter, bStartTest, extra); + + wrqu->length = strlen(extra); + return status; +} + +int rtw_mp_disable_bt_coexist(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct hal_ops *pHalFunc = &padapter->hal_func; + char *input; + u32 bt_coexist; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->data.length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) { + rc = -EFAULT; + goto out; + } + + bt_coexist = rtw_atoi(input); + + if (bt_coexist == 0) { + RTW_INFO("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n"); + rtw_btcoex_HaltNotify(padapter); + rtw_btcoex_SetManualControl(padapter, _TRUE); + /* Force to switch Antenna to WiFi*/ + rtw_write16(padapter, 0x870, 0x300); + rtw_write16(padapter, 0x860, 0x110); + /* CONFIG_BT_COEXIST */ + } else { + rtw_btcoex_SetManualControl(padapter, _FALSE); + } + +out: + kfree(input); + + return rc; +} + +int rtw_mp_arx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0; + int bmac_filter = 0, bfilter_init = 0, bmon = 0, bSmpCfg = 0, bloopbk = 0; + char *input; + char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00}; + u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, ret = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmppriv = &padapter->mppriv; + struct dbg_rx_counter rx_counter; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + RTW_INFO("%s: %s\n", __func__, input); + bStartRx = (strncmp(input, "start", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bStopRx = (strncmp(input, "stop", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bQueryPhy = (strncmp(input, "phy", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bQueryMac = (strncmp(input, "mac", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bSetBssid = (strncmp(input, "setbssid=", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + /*bfilter_init = (strncmp(input, "filter_init",11)==0)?1:0;*/ + bmac_filter = (strncmp(input, "accept_mac", 10) == 0) ? 1 : 0; + bmon = (strncmp(input, "mon=", 4) == 0) ? 1 : 0; + bSmpCfg = (strncmp(input , "smpcfg=" , 7) == 0) ? 1 : 0; + pmppriv->bloopback = (strncmp(input, "loopbk", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + + if (bSetBssid == 1) { + pch = input; + while ((token = strsep(&pch, "=")) != NULL) { + if (i > 1) + break; + tmp[i] = token; + i++; + } + if ((tmp[0] != NULL) && (tmp[1] != NULL)) { + cnts = strlen(tmp[1]) / 2; + if (cnts < 1) { + rc = -EFAULT; + goto out; + } + RTW_INFO("%s: cnts=%d\n", __func__, cnts); + RTW_INFO("%s: data=%s\n", __func__, tmp[1]); + for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) { + pmppriv->network_macaddr[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + RTW_INFO("network_macaddr[%d]=%x\n", jj, pmppriv->network_macaddr[jj]); + } + } else { + rc = -EFAULT; + goto out; + } + + pmppriv->bSetRxBssid = _TRUE; + } + + if (bmac_filter) { + pmppriv->bmac_filter = bmac_filter; + pch = input; + while ((token = strsep(&pch, "=")) != NULL) { + if (i > 1) + break; + tmp[i] = token; + i++; + } + if ((tmp[0] != NULL) && (tmp[1] != NULL)) { + cnts = strlen(tmp[1]) / 2; + if (cnts < 1) { + rc = -EFAULT; + goto out; + } + RTW_INFO("%s: cnts=%d\n", __func__, cnts); + RTW_INFO("%s: data=%s\n", __func__, tmp[1]); + for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) { + pmppriv->mac_filter[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + RTW_INFO("%s mac_filter[%d]=%x\n", __func__, jj, pmppriv->mac_filter[jj]); + } + } else { + rc = -EFAULT; + goto out; + } + + } + + if (bStartRx) { + sprintf(extra, "start"); + SetPacketRx(padapter, bStartRx, _FALSE); + } else if (bStopRx) { + SetPacketRx(padapter, bStartRx, _FALSE); + pmppriv->bmac_filter = _FALSE; + pmppriv->bSetRxBssid = _FALSE; + sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out); + } else if (bQueryPhy) { + _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter)); + rtw_dump_phy_rx_counters(padapter, &rx_counter); + + RTW_INFO("%s: OFDM_FA =%d\n", __func__, rx_counter.rx_ofdm_fa); + RTW_INFO("%s: CCK_FA =%d\n", __func__, rx_counter.rx_cck_fa); + sprintf(extra, "Phy Received packet OK:%d CRC error:%d FA Counter: %d", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa); + + } else if (bQueryMac) { + _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter)); + rtw_dump_mac_rx_counters(padapter, &rx_counter); + sprintf(extra, "Mac Received packet OK: %d , CRC error: %d , Drop Packets: %d\n", + rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop); + + } + + if (bmon == 1) { + ret = sscanf(input, "mon=%d", &bmon); + + if (bmon == 1) { + pmppriv->rx_bindicatePkt = _TRUE; + sprintf(extra, "Indicating Receive Packet to network start\n"); + } else { + pmppriv->rx_bindicatePkt = _FALSE; + sprintf(extra, "Indicating Receive Packet to network Stop\n"); + } + } + if (bSmpCfg == 1) { + ret = sscanf(input, "smpcfg=%d", &bSmpCfg); + + if (bSmpCfg == 1) { + pmppriv->bRTWSmbCfg = _TRUE; + sprintf(extra , "Indicate By Simple Config Format\n"); + SetPacketRx(padapter, _TRUE, _TRUE); + } else { + pmppriv->bRTWSmbCfg = _FALSE; + sprintf(extra , "Indicate By Normal Format\n"); + SetPacketRx(padapter, _TRUE, _FALSE); + } + } + + if (pmppriv->bloopback == _TRUE) { + sprintf(extra , "Enter MAC LoopBack mode\n"); + _rtw_write32(padapter, 0x100, 0xB0106FF); + RTW_INFO("0x100 :0x%x" , _rtw_read32(padapter, 0x100)); + _rtw_write16(padapter, 0x608, 0x30c); + RTW_INFO("0x100 :0x%x" , _rtw_read32(padapter, 0x608)); + } + + wrqu->length = strlen(extra) + 1; + +out: + kfree(input); + + return rc; +} + +int rtw_mp_trx_query(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 txok, txfail, rxok, rxfail, rxfilterout; + PADAPTER padapter = rtw_netdev_priv(dev); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; + + if (PMacTxInfo.bEnPMacTx == TRUE) + txok = hal_mpt_query_phytxok(padapter); + else + txok = padapter->mppriv.tx.sended; + + txfail = 0; + rxok = padapter->mppriv.rx_pktcount; + rxfail = padapter->mppriv.rx_crcerrpktcount; + rxfilterout = padapter->mppriv.rx_pktcount_filter_out; + + _rtw_memset(extra, '\0', 128); + + sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ,Rx Filter out:%d\n", txok, txfail, rxok, rxfail, rxfilterout); + + wrqu->length = strlen(extra) + 1; + + return 0; +} + +int rtw_mp_pwrtrk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 enable; + u32 thermal; + int ret = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + char *input; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + _rtw_memset(extra, 0, wrqu->length); + + enable = 1; + if (wrqu->length > 1) { + /* not empty string*/ + if (strncmp(input, "stop", 4) == 0) { + enable = 0; + sprintf(extra, "mp tx power tracking stop"); + } else if (sscanf(input, "ther=%d", &thermal) == 1) { + ret = SetThermalMeter(padapter, (u8)thermal); + if (ret == _FAIL) { + rc = -EPERM; + goto out; + } + sprintf(extra, "mp tx power tracking start,target value=%d ok", thermal); + } else { + rc = -EINVAL; + goto out; + } + } + + ret = SetPowerTracking(padapter, enable); + if (ret == _FAIL) { + rc = -EPERM; + goto out; + } + + wrqu->length = strlen(extra); + +out: + kfree(input); + + return rc; +} + +int rtw_mp_psd(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char *input; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + strcpy(extra, input); + + wrqu->length = mp_query_psd(padapter, extra); + +out: + kfree(input); + + return rc; +} + +int rtw_mp_thermal(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 val; + int bwrite = 1; + + u16 addr = EEPROM_THERMAL_METER_8821C; + u16 cnt = 1; + u16 max_available_size = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + bwrite = strncmp(extra, "write", 6);/* strncmp TRUE is 0*/ + + GetThermalMeter(padapter, &val); + + if (bwrite == 0) { + /*RTW_INFO("to write val:%d",val);*/ + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); + if (2 > max_available_size) { + RTW_INFO("no available efuse!\n"); + return -EFAULT; + } + if (rtw_efuse_map_write(padapter, addr, cnt, &val) == _FAIL) { + RTW_INFO("rtw_efuse_map_write error\n"); + return -EFAULT; + } + sprintf(extra, " efuse write ok :%d", val); + } else + sprintf(extra, "%d", val); + wrqu->length = strlen(extra); + + return 0; +} + +int rtw_mp_reset_stats(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + struct mp_priv *pmp_priv; + struct pkt_attrib *pattrib; + PADAPTER padapter = rtw_netdev_priv(dev); + + pmp_priv = &padapter->mppriv; + + pmp_priv->tx.sended = 0; + pmp_priv->tx_pktcount = 0; + pmp_priv->rx_pktcount = 0; + pmp_priv->rx_pktcount_filter_out = 0; + pmp_priv->rx_crcerrpktcount = 0; + + rtw_reset_phy_rx_counters(padapter); + rtw_reset_mac_rx_counters(padapter); + + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_reset_stats ok\n"); + wrqu->length = strlen(extra); + + return 0; +} + +int rtw_mp_dump(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + struct mp_priv *pmp_priv; + struct pkt_attrib *pattrib; + u32 value; + char *input; + u8 rf_type, path_nums = 0; + u32 i, j = 1, path; + PADAPTER padapter = rtw_netdev_priv(dev); + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + pmp_priv = &padapter->mppriv; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + if (strncmp(input, "all", 4) == 0) { + mac_reg_dump(RTW_DBGDUMP, padapter); + bb_reg_dump(RTW_DBGDUMP, padapter); + rf_reg_dump(RTW_DBGDUMP, padapter); + } + +out: + kfree(input); + return rc; +} + +int rtw_mp_phypara(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + char *input; + u32 valxcap, ret; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + RTW_INFO("%s:iwpriv in=%s\n", __func__, input); + + ret = sscanf(input, "xcap=%d", &valxcap); + + pHalData->crystal_cap = (u8)valxcap; + hal_set_crystal_cap(padapter , valxcap); + + sprintf(extra, "Set xcap=%d", valxcap); + wrqu->length = strlen(extra) + 1; + +out: + kfree(input); + + return rc; +} + +int rtw_mp_SetRFPath(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char *input; + int bMain = 1, bTurnoff = 1; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + RTW_INFO("%s:iwpriv in=%s\n", __func__, input); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + bMain = strncmp(input, "1", 2); /* strncmp TRUE is 0*/ + bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/ + + _rtw_memset(extra, 0, wrqu->length); + + if (bMain == 0) { + MP_PHY_SetRFPathSwitch(padapter, _TRUE); + RTW_INFO("%s:PHY_SetRFPathSwitch=TRUE\n", __func__); + sprintf(extra, "mp_setrfpath Main\n"); + + } else if (bTurnoff == 0) { + MP_PHY_SetRFPathSwitch(padapter, _FALSE); + RTW_INFO("%s:PHY_SetRFPathSwitch=FALSE\n", __func__); + sprintf(extra, "mp_setrfpath Aux\n"); + } else { + bMain = MP_PHY_QueryRFPathSwitch(padapter); + RTW_INFO("%s:PHY_SetRFPathSwitch = %s\n", __func__, (bMain ? "Main":"Aux")); + sprintf(extra, "mp_setrfpath %s\n" , (bMain ? "Main":"Aux")); + } + + wrqu->length = strlen(extra); + +out: + kfree(input); + + return rc; +} + +int rtw_mp_QueryDrv(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char *input; + int qAutoLoad = 1; + int rc = 0; + + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + input = kmalloc(sizeof(char) * wrqu->data.length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) { + rc = -EFAULT; + goto out; + } + RTW_INFO("%s:iwpriv in=%s\n", __func__, input); + + qAutoLoad = strncmp(input, "autoload", 8); /* strncmp TRUE is 0*/ + + if (qAutoLoad == 0) { + RTW_INFO("%s:qAutoLoad\n", __func__); + + if (pHalData->bautoload_fail_flag) + sprintf(extra, "fail"); + else + sprintf(extra, "ok"); + } + wrqu->data.length = strlen(extra) + 1; + +out: + kfree(input); + return rc; +} + +int rtw_mp_PwrCtlDM(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char *input; + int bstart = 1; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + rc = -EFAULT; + goto out; + } + + bstart = strncmp(input, "start", 5); /* strncmp TRUE is 0*/ + if (bstart == 0) { + sprintf(extra, "PwrCtlDM start\n"); + MPT_PwrCtlDM(padapter, 1); + } else { + sprintf(extra, "PwrCtlDM stop\n"); + MPT_PwrCtlDM(padapter, 0); + } + wrqu->length = strlen(extra); + +out: + kfree(input); + return rc; +} + +int rtw_mp_iqk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + + rtw_mp_trigger_iqk(padapter); + + return 0; +} + +int rtw_mp_lck(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + + rtw_mp_trigger_lck(padapter); + + return 0; +} + +int rtw_mp_getver(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv; + + pmp_priv = &padapter->mppriv; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + sprintf(extra, "rtwpriv=%d\n", RTWPRIV_VER_INFO); + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_mon(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = &padapter->mppriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct hal_ops *pHalFunc = &padapter->hal_func; + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; + int bstart = 1, bstop = 1; + + networkType = Ndis802_11Infrastructure; + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_pm_set_ips(padapter, IPS_NONE); + LeaveAllPowerSaveMode(padapter); + + if (init_mp_priv(padapter) == _FAIL) + RTW_INFO("%s: initialize MP private data Fail!\n", __func__); + padapter->mppriv.channel = 6; + + bstart = strncmp(extra, "start", 5); /* strncmp TRUE is 0*/ + bstop = strncmp(extra, "stop", 4); /* strncmp TRUE is 0*/ + if (bstart == 0) { + mp_join(padapter, WIFI_FW_ADHOC_STATE); + SetPacketRx(padapter, _TRUE, _FALSE); + SetChannel(padapter); + pmp_priv->rx_bindicatePkt = _TRUE; + pmp_priv->bRTWSmbCfg = _TRUE; + sprintf(extra, "monitor mode start\n"); + } else if (bstop == 0) { + SetPacketRx(padapter, _FALSE, _FALSE); + pmp_priv->rx_bindicatePkt = _FALSE; + pmp_priv->bRTWSmbCfg = _FALSE; + padapter->registrypriv.mp_mode = 1; + pHalFunc->hal_deinit(padapter); + padapter->registrypriv.mp_mode = 0; + pHalFunc->hal_init(padapter); + /*rtw_disassoc_cmd(padapter, 0, 0);*/ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + rtw_disassoc_cmd(padapter, 500, 0); + rtw_indicate_disconnect(padapter, 0, _FALSE); + /*rtw_free_assoc_resources(padapter, 1);*/ + } + rtw_pm_set_ips(padapter, IPS_NORMAL); + sprintf(extra, "monitor mode Stop\n"); + } + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + + switch (pmp_priv->mode) { + + case MP_PACKET_TX: + if (bStartTest == 0) { + pmp_priv->tx.stop = 1; + pmp_priv->mode = MP_ON; + sprintf(extra, "Stop continuous Tx"); + } else if (pmp_priv->tx.stop == 1) { + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500 count=%u\n", extra, pmp_priv->tx.count); + pmp_priv->tx.stop = 0; + SetPacketTx(padapter); + } else + return -EFAULT; + return 0; + case MP_SINGLE_TONE_TX: + if (bStartTest != 0) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + SetSingleToneTx(padapter, (u8)bStartTest); + break; + case MP_CONTINUOUS_TX: + if (bStartTest != 0) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + SetContinuousTx(padapter, (u8)bStartTest); + break; + case MP_CARRIER_SUPPRISSION_TX: + if (bStartTest != 0) { + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + else + sprintf(extra, "%s\nSpecify carrier suppression but not CCK rate", extra); + } + SetCarrierSuppressionTx(padapter, (u8)bStartTest); + break; + case MP_SINGLE_CARRIER_TX: + if (bStartTest != 0) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + SetSingleCarrierTx(padapter, (u8)bStartTest); + break; + + default: + sprintf(extra, "Error! Continuous-Tx is not on-going."); + return -EFAULT; + } + + if (bStartTest == 1 && pmp_priv->mode != MP_ON) { + struct mp_priv *pmp_priv = &padapter->mppriv; + + if (pmp_priv->tx.stop == 0) { + pmp_priv->tx.stop = 1; + rtw_msleep_os(5); + } + pmp_priv->tx.attrib.ht_en = 1; + pmp_priv->tx.stop = 0; + pmp_priv->tx.count = 1; + SetPacketTx(padapter); + } else + pmp_priv->mode = MP_ON; + + return 0; +} + +int rtw_mp_tx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + u32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0; + u8 i = 0, j = 0, bStartTest = 1, status = 0, Idx = 0, tmpU1B = 0; + u16 antenna = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + RTW_INFO("extra = %s\n", extra); + + if (strncmp(extra, "stop", 3) == 0) { + bStartTest = 0; /* To set Stop*/ + pmp_priv->tx.stop = 1; + sprintf(extra, "Stop continuous Tx"); + status = rtw_mp_pretx_proc(padapter, bStartTest, extra); + wrqu->data.length = strlen(extra); + return status; + } else if (strncmp(extra, "count", 5) == 0) { + if (sscanf(extra, "count=%d", &count) < 1) + RTW_INFO("Got Count=%d]\n", count); + pmp_priv->tx.count = count; + return 0; + } else if (strncmp(extra, "setting", 7) == 0) { + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Current Setting :\n Channel:%d", pmp_priv->channel); + sprintf(extra, "%s\n Bandwidth:%d", extra, pmp_priv->bandwidth); + sprintf(extra, "%s\n Rate index:%d", extra, pmp_priv->rateidx); + sprintf(extra, "%s\n TxPower index:%d", extra, pmp_priv->txpoweridx); + sprintf(extra, "%s\n Antenna TxPath:%d", extra, pmp_priv->antenna_tx); + sprintf(extra, "%s\n Antenna RxPath:%d", extra, pmp_priv->antenna_rx); + sprintf(extra, "%s\n MP Mode:%d", extra, pmp_priv->mode); + wrqu->data.length = strlen(extra); + return 0; + } else { + + if (sscanf(extra, "ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) { + RTW_INFO("Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "\n Please input correct format as bleow:\n"); + sprintf(extra, "%s\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", extra, channel, bandwidth, rate, txpower, ant, txmode); + sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); + sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); + sprintf(extra, "%s\n [ rate : CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]", extra); + sprintf(extra, "%s\n [ OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>", extra); + sprintf(extra, "%s\n [ HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >", extra); + sprintf(extra, "%s\n [ HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >", extra); + sprintf(extra, "%s\n [ VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >", extra); + sprintf(extra, "%s\n [ txpower : 1~63 power index", extra); + sprintf(extra, "%s\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12", extra); + sprintf(extra, "%s\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n", extra); + wrqu->data.length = strlen(extra); + return status; + + } else { + RTW_INFO("Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel); + padapter->mppriv.channel = channel; + SetChannel(padapter); + pHalData->current_channel = channel; + + if (bandwidth == 1) + bandwidth = CHANNEL_WIDTH_40; + else if (bandwidth == 2) + bandwidth = CHANNEL_WIDTH_80; + sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + padapter->mppriv.bandwidth = (u8)bandwidth; + padapter->mppriv.preamble = sg; + SetBandwidth(padapter); + pHalData->current_channel_bw = bandwidth; + + sprintf(extra, "%s\nSet power level :%d", extra, txpower); + padapter->mppriv.txpoweridx = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)txpower; + + RTW_INFO("%s: bw=%d sg=%d\n", __func__, bandwidth, sg); + + if (rate <= 0x7f) + rate = wifirate2_ratetbl_inx((u8)rate); + else if (rate < 0xC8) + rate = (rate - 0x80 + MPT_RATE_MCS0); + /*HT rate 0x80(MCS0) ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159 + VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179 + VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199 + else + VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153 + rate =(rate - MPT_RATE_VHT1SS_MCS0); + */ + RTW_INFO("%s: rate index=%d\n", __func__, rate); + if (rate >= MPT_RATE_LAST) + return -EINVAL; + sprintf(extra, "%s\nSet data rate to %d index %d", extra, padapter->mppriv.rateidx, rate); + + padapter->mppriv.rateidx = rate; + pMptCtx->mpt_rate_index = rate; + SetDataRate(padapter); + + sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + switch (ant) { + case 1: + antenna = ANTENNA_A; + break; + case 2: + antenna = ANTENNA_B; + break; + case 4: + antenna = ANTENNA_C; + break; + case 8: + antenna = ANTENNA_D; + break; + case 3: + antenna = ANTENNA_AB; + break; + case 5: + antenna = ANTENNA_AC; + break; + case 9: + antenna = ANTENNA_AD; + break; + case 6: + antenna = ANTENNA_BC; + break; + case 10: + antenna = ANTENNA_BD; + break; + case 12: + antenna = ANTENNA_CD; + break; + case 7: + antenna = ANTENNA_ABC; + break; + case 14: + antenna = ANTENNA_BCD; + break; + case 11: + antenna = ANTENNA_ABD; + break; + case 15: + antenna = ANTENNA_ABCD; + break; + } + RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + pHalData->antenna_tx_path = antenna; + SetAntenna(padapter); + + if (txmode == 0) + pmp_priv->mode = MP_CONTINUOUS_TX; + else if (txmode == 1) { + pmp_priv->mode = MP_PACKET_TX; + pmp_priv->tx.count = count; + } else if (txmode == 2) + pmp_priv->mode = MP_SINGLE_TONE_TX; + else if (txmode == 3) + pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX; + else if (txmode == 4) + pmp_priv->mode = MP_SINGLE_CARRIER_TX; + + status = rtw_mp_pretx_proc(padapter, bStartTest, extra); + } + + } + + wrqu->data.length = strlen(extra); + return status; +} + +int rtw_mp_rx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + + u32 bandwidth = 0, sg = 0, channel = 6, ant = 0; + u16 antenna = 0; + u8 bStartRx = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + + if (strncmp(extra, "stop", 4) == 0) { + _rtw_memset(extra, 0, wrqu->data.length); + SetPacketRx(padapter, bStartRx, _FALSE); + pmp_priv->bmac_filter = _FALSE; + sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out); + wrqu->data.length = strlen(extra); + return 0; + + } else if (sscanf(extra, "ch=%d,bw=%d,ant=%d", &channel, &bandwidth, &ant) < 3) { + RTW_INFO("Invalid format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "\n Please input correct format as bleow:\n"); + sprintf(extra, "%s\t ch=%d,bw=%d,ant=%d\n", extra, channel, bandwidth, ant); + sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); + sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); + sprintf(extra, "%s\n [ ant : <A = 1, B = 2, C = 4, D = 8> ,2T ex: AB=3 BC=6 CD=12", extra); + wrqu->data.length = strlen(extra); + return 0; + + } else { + bStartRx = 1; + RTW_INFO("Got format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel); + padapter->mppriv.channel = channel; + SetChannel(padapter); + pHalData->current_channel = channel; + + if (bandwidth == 1) + bandwidth = CHANNEL_WIDTH_40; + else if (bandwidth == 2) + bandwidth = CHANNEL_WIDTH_80; + sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + padapter->mppriv.bandwidth = (u8)bandwidth; + padapter->mppriv.preamble = sg; + SetBandwidth(padapter); + pHalData->current_channel_bw = bandwidth; + + sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + switch (ant) { + case 1: + antenna = ANTENNA_A; + break; + case 2: + antenna = ANTENNA_B; + break; + case 4: + antenna = ANTENNA_C; + break; + case 8: + antenna = ANTENNA_D; + break; + case 3: + antenna = ANTENNA_AB; + break; + case 5: + antenna = ANTENNA_AC; + break; + case 9: + antenna = ANTENNA_AD; + break; + case 6: + antenna = ANTENNA_BC; + break; + case 10: + antenna = ANTENNA_BD; + break; + case 12: + antenna = ANTENNA_CD; + break; + case 7: + antenna = ANTENNA_ABC; + break; + case 14: + antenna = ANTENNA_BCD; + break; + case 11: + antenna = ANTENNA_ABD; + break; + case 15: + antenna = ANTENNA_ABCD; + break; + } + RTW_INFO("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + pHalData->antenna_tx_path = antenna; + SetAntenna(padapter); + + sprintf(extra, "%s\nstart Rx", extra); + SetPacketRx(padapter, bStartRx, _FALSE); + } + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_hwtx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx); + char *input; + int rc = 0; + + input = kmalloc(sizeof(char) * wrqu->data.length, GFP_KERNEL); + if (!input) + return -ENOMEM; + + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) { + rc = -EFAULT; + goto out; + } + + _rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO)); + _rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)input, sizeof(RT_PMAC_TX_INFO)); + + mpt_ProSetPMacTx(padapter); + sprintf(extra, "Set PMac Tx Mode start\n"); + + wrqu->data.length = strlen(extra); +out: + kfree(input); + + return 0; +} + +int rtw_efuse_mask_file(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_mask_file_path; + u8 Status; + PADAPTER padapter = rtw_netdev_priv(dev); + + _rtw_memset(maskfileBuffer, 0x00, sizeof(maskfileBuffer)); + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { + padapter->registrypriv.boffefusemask = 1; + sprintf(extra, "Turn off Efuse Mask\n"); + wrqu->data.length = strlen(extra); + return 0; + } + if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { + padapter->registrypriv.boffefusemask = 0; + sprintf(extra, "Turn on Efuse Mask\n"); + wrqu->data.length = strlen(extra); + return 0; + } + if (strncmp(extra, "data,", 5) == 0) { + u8 *pch, *pdata; + char *ptmp, tmp; + u8 count = 0; + u8 i = 0; + u32 datalen = 0; + + ptmp = extra; + pch = strsep(&ptmp, ","); + + if ((pch == NULL) || (strlen(pch) == 0)) { + RTW_INFO("%s: parameter error(no cmd)!\n", __func__); + return -EFAULT; + } + + do { + pch = strsep(&ptmp, ":"); + if ((pch == NULL) || (strlen(pch) == 0)) + break; + if (strlen(pch) != 2 + || IsHexDigit(*pch) == _FALSE + || IsHexDigit(*(pch + 1)) == _FALSE + || sscanf(pch, "%hhx", &tmp) != 1 + ) { + RTW_INFO("%s: invalid 8-bit hex! input format: data,01:23:45:67:89:ab:cd:ef...\n", __func__); + return -EFAULT; + } + maskfileBuffer[count++] = tmp; + + } while (count < 64); + + for (i = 0; i < count; i++) + sprintf(extra, "%s:%02x", extra, maskfileBuffer[i]); + + padapter->registrypriv.bFileMaskEfuse = _TRUE; + + sprintf(extra, "%s\nLoad Efuse Mask data %d hex ok\n", extra, count); + wrqu->data.length = strlen(extra); + return 0; + } + rtw_efuse_mask_file_path = extra; + + if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) { + RTW_INFO("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer)); + Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer)); + if (Status == _TRUE) + padapter->registrypriv.bFileMaskEfuse = _TRUE; + sprintf(extra, "efuse mask file read OK\n"); + } else { + padapter->registrypriv.bFileMaskEfuse = _FALSE; + sprintf(extra, "efuse mask file readable FAIL\n"); + RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + } + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status; + PEFUSE_HAL pEfuseHal; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + + pEfuseHal = &pHalData->EfuseHal; + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + + _rtw_memset(pEfuseHal->fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN); + + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + RTW_INFO("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap)); + if (Status == _TRUE) { + pmp_priv->bloadefusemap = _TRUE; + sprintf(extra, "efuse file file_read OK\n"); + } else { + pmp_priv->bloadefusemap = _FALSE; + sprintf(extra, "efuse file file_read FAIL\n"); + } + } else { + sprintf(extra, "efuse file readable FAIL\n"); + RTW_INFO("%s rtw_is_file_readable fail!\n", __func__); + } + wrqu->data.length = strlen(extra); + return 0; +} + diff --git a/drivers/staging/rtl8821ce/os_dep/linux/mlme_linux.c b/drivers/staging/rtl8821ce/os_dep/linux/mlme_linux.c new file mode 100644 index 000000000000..fdf2444090de --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/mlme_linux.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _MLME_OSDEP_C_ + +#include <drv_types.h> + + +extern void rtw_indicate_wx_assoc_event(_adapter *padapter); +extern void rtw_indicate_wx_disassoc_event(_adapter *padapter); + +void rtw_os_indicate_connect(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + + + rtw_indicate_wx_assoc_event(adapter); + netif_carrier_on(adapter->pnetdev); + + if (adapter->pid[2] != 0) + rtw_signal_process(adapter->pid[2], SIGALRM); + + +} + +extern void indicate_wx_scan_complete_event(_adapter *padapter); +void rtw_os_indicate_scan_done(_adapter *padapter, bool aborted) +{ + indicate_wx_scan_complete_event(padapter); +} + +static RT_PMKID_LIST backupPMKIDList[NUM_PMKID_CACHE]; +void rtw_reset_securitypriv(_adapter *adapter) +{ + u8 backupPMKIDIndex = 0; + u8 backupTKIPCountermeasure = 0x00; + u32 backupTKIPcountermeasure_time = 0; + /* add for CONFIG_IEEE80211W, none 11w also can use */ + _irqL irqL; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + _enter_critical_bh(&adapter->security_key_mutex, &irqL); + + if (adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) { /* 802.1x */ + /* Added by Albert 2009/02/18 */ + /* We have to backup the PMK information for WiFi PMK Caching test item. */ + /* */ + /* Backup the btkip_countermeasure information. */ + /* When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. */ + + _rtw_memset(&backupPMKIDList[0], 0x00, sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE); + + _rtw_memcpy(&backupPMKIDList[0], &adapter->securitypriv.PMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE); + backupPMKIDIndex = adapter->securitypriv.PMKIDIndex; + backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure; + backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time; + _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof(struct security_priv)); + + /* Added by Albert 2009/02/18 */ + /* Restore the PMK information to securitypriv structure for the following connection. */ + _rtw_memcpy(&adapter->securitypriv.PMKIDList[0], &backupPMKIDList[0], sizeof(RT_PMKID_LIST) * NUM_PMKID_CACHE); + adapter->securitypriv.PMKIDIndex = backupPMKIDIndex; + adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure; + adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time; + + adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; + adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; + + } else { /* reset values in securitypriv */ + /* if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) */ + /* { */ + struct security_priv *psec_priv = &adapter->securitypriv; + + psec_priv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */ + psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + psec_priv->dot11PrivacyKeyIndex = 0; + + psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_; + psec_priv->dot118021XGrpKeyid = 1; + + psec_priv->ndisauthtype = Ndis802_11AuthModeOpen; + psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled; + /* } */ + } + /* add for CONFIG_IEEE80211W, none 11w also can use */ + _exit_critical_bh(&adapter->security_key_mutex, &irqL); + + RTW_INFO(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(adapter)); +} + +void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated) +{ + /* RT_PMKID_LIST backupPMKIDList[NUM_PMKID_CACHE]; */ + + netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */ + + + rtw_indicate_wx_disassoc_event(adapter); + + /* modify for CONFIG_IEEE80211W, none 11w also can use the same command */ + rtw_reset_securitypriv_cmd(adapter); + +} + +void rtw_report_sec_ie(_adapter *adapter, u8 authmode, u8 *sec_ie) +{ + uint len; + u8 *buff, *p, i; + union iwreq_data wrqu; + + buff = NULL; + if (authmode == _WPA_IE_ID_) { + + buff = rtw_zmalloc(IW_CUSTOM_MAX); + if (NULL == buff) { + RTW_INFO(FUNC_ADPT_FMT ": alloc memory FAIL!!\n", + FUNC_ADPT_ARG(adapter)); + return; + } + p = buff; + + p += sprintf(p, "ASSOCINFO(ReqIEs="); + + len = sec_ie[1] + 2; + len = (len < IW_CUSTOM_MAX) ? len : IW_CUSTOM_MAX; + + for (i = 0; i < len; i++) + p += sprintf(p, "%02x", sec_ie[i]); + + p += sprintf(p, ")"); + + _rtw_memset(&wrqu, 0, sizeof(wrqu)); + + wrqu.data.length = p - buff; + + wrqu.data.length = (wrqu.data.length < IW_CUSTOM_MAX) ? wrqu.data.length : IW_CUSTOM_MAX; + + wireless_send_event(adapter->pnetdev, IWEVCUSTOM, &wrqu, buff); + + rtw_mfree(buff, IW_CUSTOM_MAX); + } + +} + + +void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta) +{ + union iwreq_data wrqu; + struct sta_priv *pstapriv = &padapter->stapriv; + + if (psta == NULL) + return; + + if (psta->aid > NUM_STA) + return; + + if (pstapriv->sta_aid[psta->aid - 1] != psta) + return; + + wrqu.addr.sa_family = ARPHRD_ETHER; + + _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + + RTW_INFO("+rtw_indicate_sta_assoc_event\n"); + + wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL); + +} + +void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta) +{ + union iwreq_data wrqu; + struct sta_priv *pstapriv = &padapter->stapriv; + + if (psta == NULL) + return; + + if (psta->aid > NUM_STA) + return; + + if (pstapriv->sta_aid[psta->aid - 1] != psta) + return; + + wrqu.addr.sa_family = ARPHRD_ETHER; + + _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + + RTW_INFO("+rtw_indicate_sta_disassoc_event\n"); + + wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL); + +} + diff --git a/drivers/staging/rtl8821ce/os_dep/linux/os_intfs.c b/drivers/staging/rtl8821ce/os_dep/linux/os_intfs.c new file mode 100644 index 000000000000..db2d8b3711f8 --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/os_intfs.c @@ -0,0 +1,2389 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _OS_INTFS_C_ + +#include <drv_types.h> +#include <hal_data.h> + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); +MODULE_AUTHOR("Realtek Semiconductor Corp."); +MODULE_VERSION(DRIVERVERSION); + +/* module param defaults */ +int rtw_chip_version = 0x00; +int rtw_rfintfs = HWPI; +int rtw_lbkmode = 0;/* RTL8712_AIR_TRX; */ + +int rtw_network_mode = Ndis802_11IBSS;/* Ndis802_11Infrastructure; */ /* infra, ad-hoc, auto */ +/* NDIS_802_11_SSID ssid; */ +int rtw_channel = 1;/* ad-hoc support requirement */ +int rtw_wireless_mode = WIRELESS_MODE_MAX; +int rtw_vrtl_carrier_sense = AUTO_VCS; +int rtw_vcs_type = RTS_CTS; +int rtw_rts_thresh = 2347; +int rtw_frag_thresh = 2346; +int rtw_preamble = PREAMBLE_LONG;/* long, short, auto */ +int rtw_scan_mode = 1;/* active, passive */ +int rtw_adhoc_tx_pwr = 1; +int rtw_soft_ap = 0; +/* int smart_ps = 1; */ + int rtw_power_mgnt = PS_MODE_MAX; + int rtw_ips_mode = IPS_NORMAL; + +int rtw_lps_level = LPS_NORMAL; +module_param(rtw_ips_mode, int, 0644); +MODULE_PARM_DESC(rtw_ips_mode, "The default IPS mode"); + +module_param(rtw_lps_level, int, 0644); +MODULE_PARM_DESC(rtw_lps_level, "The default LPS level"); + +int rtw_smart_ps = 2; + +int rtw_check_fw_ps = 1; + + +int rtw_usb_rxagg_mode = 2;/* RX_AGG_DMA=1, RX_AGG_USB=2 */ +module_param(rtw_usb_rxagg_mode, int, 0644); + +int rtw_dynamic_agg_enable = 1; +module_param(rtw_dynamic_agg_enable, int, 0644); + +uint rtw_drv_log_level = 3; +module_param(rtw_drv_log_level, uint, 0644); +MODULE_PARM_DESC(rtw_drv_log_level, "set log level when insert driver module, default log level is 3"); + +int rtw_radio_enable = 1; +int rtw_long_retry_lmt = 7; +int rtw_short_retry_lmt = 7; +int rtw_busy_thresh = 40; +/* int qos_enable = 0; */ /* * */ +int rtw_ack_policy = NORMAL_ACK; + +int rtw_mp_mode = 0; + + +int rtw_software_encrypt = 0; +int rtw_software_decrypt = 0; + +int rtw_acm_method = 0;/* 0:By SW 1:By HW. */ + +int rtw_wmm_enable = 1;/* default is set to enable the wmm. */ +int rtw_uapsd_enable = 0; +int rtw_uapsd_max_sp = NO_LIMIT; +int rtw_uapsd_acbk_en = 0; +int rtw_uapsd_acbe_en = 0; +int rtw_uapsd_acvi_en = 0; +int rtw_uapsd_acvo_en = 0; + /*PHYDM API, must enable by default*/ + int rtw_pwrtrim_enable = 1; + +uint rtw_tx_bw_mode = 0x21; +module_param(rtw_tx_bw_mode, uint, 0644); +MODULE_PARM_DESC(rtw_tx_bw_mode, "The max tx bw for 2.4G and 5G. format is the same as rtw_bw_mode"); + +int rtw_ht_enable = 1; +/* 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz +* 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 +* 0x21 means enable 2.4G 40MHz & 5G 80MHz */ +int rtw_bw_mode = 0x21; +int rtw_ampdu_enable = 1;/* for enable tx_ampdu , */ /* 0: disable, 0x1:enable */ +int rtw_rx_stbc = 1;/* 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ */ +int rtw_rx_ampdu_amsdu;/* 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on */ +/* +* 2: Follow the AMSDU filed in ADDBA Resp. (Deault) +* 0: Force the AMSDU filed in ADDBA Resp. to be disabled. +* 1: Force the AMSDU filed in ADDBA Resp. to be enabled. +*/ +int rtw_tx_ampdu_amsdu = 2; + +static uint rtw_rx_ampdu_sz_limit_1ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_1SS; +static uint rtw_rx_ampdu_sz_limit_1ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_1ss, uint, &rtw_rx_ampdu_sz_limit_1ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_1ss, "RX AMPDU size limit for 1SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_2ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_2SS; +static uint rtw_rx_ampdu_sz_limit_2ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_2ss, uint, &rtw_rx_ampdu_sz_limit_2ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_2ss, "RX AMPDU size limit for 2SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_3ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_3SS; +static uint rtw_rx_ampdu_sz_limit_3ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_3ss, uint, &rtw_rx_ampdu_sz_limit_3ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_3ss, "RX AMPDU size limit for 3SS link of each BW, 0xFF: no limitation"); + +static uint rtw_rx_ampdu_sz_limit_4ss[4] = CONFIG_RTW_RX_AMPDU_SZ_LIMIT_4SS; +static uint rtw_rx_ampdu_sz_limit_4ss_num = 0; +module_param_array(rtw_rx_ampdu_sz_limit_4ss, uint, &rtw_rx_ampdu_sz_limit_4ss_num, 0644); +MODULE_PARM_DESC(rtw_rx_ampdu_sz_limit_4ss, "RX AMPDU size limit for 4SS link of each BW, 0xFF: no limitation"); + +/* Short GI support Bit Map +* BIT0 - 20MHz, 0: non-support, 1: support +* BIT1 - 40MHz, 0: non-support, 1: support +* BIT2 - 80MHz, 0: non-support, 1: support +* BIT3 - 160MHz, 0: non-support, 1: support */ +int rtw_short_gi = 0xf; +/* BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx */ +int rtw_ldpc_cap = 0x33; +/* BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx */ +int rtw_stbc_cap = 0x13; +/* +* BIT0: Enable VHT SU Beamformer +* BIT1: Enable VHT SU Beamformee +* BIT2: Enable VHT MU Beamformer, depend on VHT SU Beamformer +* BIT3: Enable VHT MU Beamformee, depend on VHT SU Beamformee +* BIT4: Enable HT Beamformer +* BIT5: Enable HT Beamformee +*/ +int rtw_beamform_cap = BIT(1) | BIT(3); +int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/ +int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum Rf path number, 0 for auto, others for manual*/ + + +int rtw_vht_enable = 1; /* 0:disable, 1:enable, 2:force auto enable */ +module_param(rtw_vht_enable, int, 0644); + +int rtw_ampdu_factor = 7; + +uint rtw_vht_rx_mcs_map = 0xaaaa; +module_param(rtw_vht_rx_mcs_map, uint, 0644); +MODULE_PARM_DESC(rtw_vht_rx_mcs_map, "VHT RX MCS map"); + +int rtw_lowrate_two_xmit = 1;/* Use 2 path Tx to transmit MCS0~7 and legacy mode */ + +int rtw_rf_config = RF_TYPE_AUTO; +module_param(rtw_rf_config, int, 0644); + +/* 0: not check in watch dog, 1: check in watch dog */ +int rtw_check_hw_status = 0; + +int rtw_low_power = 0; + int rtw_wifi_spec = 0; + + bool rtw_support_default_patterns = _FALSE; + +int rtw_special_rf_path = 0; /* 0: 2T2R ,1: only turn on path A 1T1R */ + +char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00}; +char *rtw_country_code = rtw_country_unspecified; +module_param(rtw_country_code, charp, 0644); +MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)"); + +int rtw_channel_plan = RTW_CHPLAN_MAX; +module_param(rtw_channel_plan, int, 0644); +MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid"); + +static uint rtw_excl_chs[MAX_CHANNEL_NUM] = CONFIG_RTW_EXCL_CHS; +static int rtw_excl_chs_num = 0; +module_param_array(rtw_excl_chs, uint, &rtw_excl_chs_num, 0644); +MODULE_PARM_DESC(rtw_excl_chs, "exclusive channel array"); + +/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list. +But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/ +#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE + int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/ +#else + int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/ +#endif + +int rtw_btcoex_enable = 2; +module_param(rtw_btcoex_enable, int, 0644); +MODULE_PARM_DESC(rtw_btcoex_enable, "BT co-existence on/off, 0:off, 1:on, 2:by efuse"); + +int rtw_ant_num = 0; +module_param(rtw_ant_num, int, 0644); +MODULE_PARM_DESC(rtw_ant_num, "Antenna number setting, 0:by efuse"); + +int rtw_bt_iso = 2;/* 0:Low, 1:High, 2:From Efuse */ +int rtw_bt_sco = 3;/* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy */ +int rtw_bt_ampdu = 1 ; /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */ + +int rtw_AcceptAddbaReq = _TRUE;/* 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. */ + +int rtw_antdiv_cfg = 2; /* 0:OFF , 1:ON, 2:decide by Efuse config */ +int rtw_antdiv_type = 0 + ; /* 0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) */ + +int rtw_drv_ant_band_switch = 1; /* 0:OFF , 1:ON, Driver control antenna band switch*/ + +int rtw_single_ant_path; /*0:main ant , 1:aux ant , Fixed single antenna path, default main ant*/ + +/* 0: doesn't switch, 1: switch from usb2.0 to usb 3.0 2: switch from usb3.0 to usb 2.0 */ +int rtw_switch_usb_mode = 0; + +int rtw_enusbss = 0;/* 0:disable,1:enable */ + +int rtw_hwpdn_mode = 2; /* 0:disable,1:enable,2: by EFUSE config */ + +int rtw_hwpwrp_detect = 0; /* HW power ping detect 0:disable , 1:enable */ + +int rtw_hw_wps_pbc = 0; + +int rtw_mc2u_disable = 0; + +int rtw_80211d = 0; + +#ifdef CONFIG_PCI_ASPM +/* CLK_REQ:BIT0 L0s:BIT1 ASPM_L1:BIT2 L1Off:BIT3*/ +int rtw_pci_aspm_enable = 0xF; +#else +int rtw_pci_aspm_enable; +#endif + + +int rtw_force_igi_lb = CONFIG_RTW_FORCE_IGI_LB; +module_param(rtw_force_igi_lb, int, 0644); +MODULE_PARM_DESC(rtw_force_igi_lb, "force IGI low-bound, 0:no specified"); + +#ifdef CONFIG_QOS_OPTIMIZATION +int rtw_qos_opt_enable = 1; /* 0: disable,1:enable */ +#else +int rtw_qos_opt_enable = 0; /* 0: disable,1:enable */ +#endif +module_param(rtw_qos_opt_enable, int, 0644); + + +char *ifname = "wlan%d"; +module_param(ifname, charp, 0644); +MODULE_PARM_DESC(ifname, "The default name to allocate for first interface"); + + char *if2name = "wlan%d"; +module_param(if2name, charp, 0644); +MODULE_PARM_DESC(if2name, "The default name to allocate for second interface"); + +char *rtw_initmac = 0; /* temp mac address if users want to use instead of the mac address in Efuse */ + + +module_param(rtw_pwrtrim_enable, int, 0644); +module_param(rtw_initmac, charp, 0644); +module_param(rtw_special_rf_path, int, 0644); +module_param(rtw_chip_version, int, 0644); +module_param(rtw_rfintfs, int, 0644); +module_param(rtw_lbkmode, int, 0644); +module_param(rtw_network_mode, int, 0644); +module_param(rtw_channel, int, 0644); +module_param(rtw_mp_mode, int, 0644); +module_param(rtw_wmm_enable, int, 0644); +module_param(rtw_vrtl_carrier_sense, int, 0644); +module_param(rtw_vcs_type, int, 0644); +module_param(rtw_busy_thresh, int, 0644); + +module_param(rtw_ht_enable, int, 0644); +module_param(rtw_bw_mode, int, 0644); +module_param(rtw_ampdu_enable, int, 0644); +module_param(rtw_rx_stbc, int, 0644); +module_param(rtw_rx_ampdu_amsdu, int, 0644); +module_param(rtw_tx_ampdu_amsdu, int, 0644); + +module_param(rtw_lowrate_two_xmit, int, 0644); + +module_param(rtw_power_mgnt, int, 0644); +module_param(rtw_smart_ps, int, 0644); +module_param(rtw_low_power, int, 0644); +module_param(rtw_wifi_spec, int, 0644); + +module_param(rtw_full_ch_in_p2p_handshake, int, 0644); +module_param(rtw_antdiv_cfg, int, 0644); +module_param(rtw_antdiv_type, int, 0644); + +module_param(rtw_drv_ant_band_switch, int, 0644); +module_param(rtw_single_ant_path, int, 0644); + +module_param(rtw_switch_usb_mode, int, 0644); + +module_param(rtw_enusbss, int, 0644); +module_param(rtw_hwpdn_mode, int, 0644); +module_param(rtw_hwpwrp_detect, int, 0644); + +module_param(rtw_hw_wps_pbc, int, 0644); +module_param(rtw_check_hw_status, int, 0644); + +module_param(rtw_pci_aspm_enable, int, 0644); + + +uint rtw_max_roaming_times = 2; +module_param(rtw_max_roaming_times, uint, 0644); +MODULE_PARM_DESC(rtw_max_roaming_times, "The max roaming times to try"); + + + +module_param(rtw_mc2u_disable, int, 0644); + +module_param(rtw_80211d, int, 0644); +MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism"); + +uint rtw_notch_filter = 0; +module_param(rtw_notch_filter, uint, 0644); +MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P"); + +uint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER; +module_param(rtw_hiq_filter, uint, 0644); +MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all"); + +uint rtw_adaptivity_en = 0; +module_param(rtw_adaptivity_en, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable"); + +uint rtw_adaptivity_mode = 0; +module_param(rtw_adaptivity_mode, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense"); + +uint rtw_adaptivity_dml = CONFIG_RTW_ADAPTIVITY_DML; +module_param(rtw_adaptivity_dml, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_dml, "0:disable, 1:enable"); + +uint rtw_adaptivity_dc_backoff = CONFIG_RTW_ADAPTIVITY_DC_BACKOFF; +module_param(rtw_adaptivity_dc_backoff, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_dc_backoff, "DC backoff for Adaptivity"); + +int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI; +module_param(rtw_adaptivity_th_l2h_ini, int, 0644); +MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "th_l2h_ini for Adaptivity"); + +int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF; +module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644); +MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "th_edcca_hl_diff for Adaptivity"); + + +uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G; +module_param(rtw_amplifier_type_2g, uint, 0644); +MODULE_PARM_DESC(rtw_amplifier_type_2g, "BIT3:2G ext-PA, BIT4:2G ext-LNA"); + +uint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G; +module_param(rtw_amplifier_type_5g, uint, 0644); +MODULE_PARM_DESC(rtw_amplifier_type_5g, "BIT6:5G ext-PA, BIT7:5G ext-LNA"); + +uint rtw_RFE_type = CONFIG_RTW_RFE_TYPE; +module_param(rtw_RFE_type, uint, 0644); +MODULE_PARM_DESC(rtw_RFE_type, "default init value:64"); + +uint rtw_powertracking_type = 64; +module_param(rtw_powertracking_type, uint, 0644); +MODULE_PARM_DESC(rtw_powertracking_type, "default init value:64"); + +uint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE; +module_param(rtw_GLNA_type, uint, 0644); +MODULE_PARM_DESC(rtw_GLNA_type, "default init value:0"); + +uint rtw_TxBBSwing_2G = 0xFF; +module_param(rtw_TxBBSwing_2G, uint, 0644); +MODULE_PARM_DESC(rtw_TxBBSwing_2G, "default init value:0xFF"); + +uint rtw_TxBBSwing_5G = 0xFF; +module_param(rtw_TxBBSwing_5G, uint, 0644); +MODULE_PARM_DESC(rtw_TxBBSwing_5G, "default init value:0xFF"); + +uint rtw_OffEfuseMask = 0; +module_param(rtw_OffEfuseMask, uint, 0644); +MODULE_PARM_DESC(rtw_OffEfuseMask, "default open Efuse Mask value:0"); + +uint rtw_FileMaskEfuse = 0; +module_param(rtw_FileMaskEfuse, uint, 0644); +MODULE_PARM_DESC(rtw_FileMaskEfuse, "default drv Mask Efuse value:0"); + +uint rtw_rxgain_offset_2g = 0; +module_param(rtw_rxgain_offset_2g, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_2g, "default RF Gain 2G Offset value:0"); + +uint rtw_rxgain_offset_5gl = 0; +module_param(rtw_rxgain_offset_5gl, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_5gl, "default RF Gain 5GL Offset value:0"); + +uint rtw_rxgain_offset_5gm = 0; +module_param(rtw_rxgain_offset_5gm, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GM Offset value:0"); + +uint rtw_rxgain_offset_5gh = 0; +module_param(rtw_rxgain_offset_5gh, uint, 0644); +MODULE_PARM_DESC(rtw_rxgain_offset_5gm, "default RF Gain 5GL Offset value:0"); + +uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL; +module_param(rtw_pll_ref_clk_sel, uint, 0644); +MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value"); + +int rtw_tx_pwr_by_rate = 2; +module_param(rtw_tx_pwr_by_rate, int, 0644); +MODULE_PARM_DESC(rtw_tx_pwr_by_rate, "0:Disable, 1:Enable, 2: Depend on efuse"); + +int rtw_tx_pwr_lmt_enable = 2; +module_param(rtw_tx_pwr_lmt_enable, int, 0644); +MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable, "0:Disable, 1:Enable, 2: Depend on efuse"); + +static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A; +static int rtw_target_tx_pwr_2g_a_num = 0; +module_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, "2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B; +static int rtw_target_tx_pwr_2g_b_num = 0; +module_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, "2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C; +static int rtw_target_tx_pwr_2g_c_num = 0; +module_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, "2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D; +static int rtw_target_tx_pwr_2g_d_num = 0; +module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A; +static int rtw_target_tx_pwr_5g_a_num = 0; +module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, "5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B; +static int rtw_target_tx_pwr_5g_b_num = 0; +module_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, "5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C; +static int rtw_target_tx_pwr_5g_c_num = 0; +module_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, "5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D; +static int rtw_target_tx_pwr_5g_d_num = 0; +module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); + +char *rtw_phy_file_path; +module_param(rtw_phy_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_phy_file_path, "The path of phy parameter"); +/* PHY FILE Bit Map +* BIT0 - MAC, 0: non-support, 1: support +* BIT1 - BB, 0: non-support, 1: support +* BIT2 - BB_PG, 0: non-support, 1: support +* BIT3 - BB_MP, 0: non-support, 1: support +* BIT4 - RF, 0: non-support, 1: support +* BIT5 - RF_TXPWR_TRACK, 0: non-support, 1: support +* BIT6 - RF_TXPWR_LMT, 0: non-support, 1: support */ +int rtw_load_phy_file = (BIT2 | BIT6); +module_param(rtw_load_phy_file, int, 0644); +MODULE_PARM_DESC(rtw_load_phy_file, "PHY File Bit Map"); +int rtw_decrypt_phy_file = 0; +module_param(rtw_decrypt_phy_file, int, 0644); +MODULE_PARM_DESC(rtw_decrypt_phy_file, "Enable Decrypt PHY File"); + + +int _netdev_open(struct net_device *pnetdev); +int netdev_open(struct net_device *pnetdev); +static int netdev_close(struct net_device *pnetdev); + +/*following setting should define NAPI in Makefile +enable napi only = 1, disable napi = 0*/ +int rtw_en_napi = 1; +module_param(rtw_en_napi, int, 0644); +/*following setting should define GRO in Makefile +enable gro = 1, disable gro = 0*/ +int rtw_en_gro = 1; +module_param(rtw_en_gro, int, 0644); + +void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) +{ + int path, rs; + int *target_tx_pwr; + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path == RF_PATH_A) + target_tx_pwr = rtw_target_tx_pwr_2g_a; + else if (path == RF_PATH_B) + target_tx_pwr = rtw_target_tx_pwr_2g_b; + else if (path == RF_PATH_C) + target_tx_pwr = rtw_target_tx_pwr_2g_c; + else if (path == RF_PATH_D) + target_tx_pwr = rtw_target_tx_pwr_2g_d; + + for (rs = CCK; rs < RATE_SECTION_NUM; rs++) + regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs]; + } + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path == RF_PATH_A) + target_tx_pwr = rtw_target_tx_pwr_5g_a; + else if (path == RF_PATH_B) + target_tx_pwr = rtw_target_tx_pwr_5g_b; + else if (path == RF_PATH_C) + target_tx_pwr = rtw_target_tx_pwr_5g_c; + else if (path == RF_PATH_D) + target_tx_pwr = rtw_target_tx_pwr_5g_d; + + for (rs = OFDM; rs < RATE_SECTION_NUM; rs++) + regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1]; + } +} + +inline void rtw_regsty_load_excl_chs(struct registry_priv *regsty) +{ + int i; + int ch_num = 0; + + for (i = 0; i < MAX_CHANNEL_NUM; i++) + if (((u8)rtw_excl_chs[i]) != 0) + regsty->excl_chs[ch_num++] = (u8)rtw_excl_chs[i]; + + if (ch_num < MAX_CHANNEL_NUM) + regsty->excl_chs[ch_num] = 0; +} + +inline void rtw_regsty_init_rx_ampdu_sz_limit(struct registry_priv *regsty) +{ + int i, j; + uint *sz_limit; + + for (i = 0; i < 4; i++) { + if (i == 0) + sz_limit = rtw_rx_ampdu_sz_limit_1ss; + else if (i == 1) + sz_limit = rtw_rx_ampdu_sz_limit_2ss; + else if (i == 2) + sz_limit = rtw_rx_ampdu_sz_limit_3ss; + else if (i == 3) + sz_limit = rtw_rx_ampdu_sz_limit_4ss; + + for (j = 0; j < 4; j++) + regsty->rx_ampdu_sz_limit_by_nss_bw[i][j] = sz_limit[j]; + } +} + +uint loadparam(_adapter *padapter) +{ + uint status = _SUCCESS; + struct registry_priv *registry_par = &padapter->registrypriv; + + if (rtw_drv_log_level >= _DRV_MAX_) + rtw_drv_log_level = _DRV_DEBUG_; + + registry_par->chip_version = (u8)rtw_chip_version; + registry_par->rfintfs = (u8)rtw_rfintfs; + registry_par->lbkmode = (u8)rtw_lbkmode; + /* registry_par->hci = (u8)hci; */ + registry_par->network_mode = (u8)rtw_network_mode; + + _rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3); + registry_par->ssid.SsidLength = 3; + + registry_par->channel = (u8)rtw_channel; + registry_par->wireless_mode = (u8)rtw_wireless_mode; + + if (IsSupported24G(registry_par->wireless_mode) && (!is_supported_5g(registry_par->wireless_mode)) + && (registry_par->channel > 14)) + registry_par->channel = 1; + else if (is_supported_5g(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode)) + && (registry_par->channel <= 14)) + registry_par->channel = 36; + + registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ; + registry_par->vcs_type = (u8)rtw_vcs_type; + registry_par->rts_thresh = (u16)rtw_rts_thresh; + registry_par->frag_thresh = (u16)rtw_frag_thresh; + registry_par->preamble = (u8)rtw_preamble; + registry_par->scan_mode = (u8)rtw_scan_mode; + registry_par->adhoc_tx_pwr = (u8)rtw_adhoc_tx_pwr; + registry_par->soft_ap = (u8)rtw_soft_ap; + registry_par->smart_ps = (u8)rtw_smart_ps; + registry_par->check_fw_ps = (u8)rtw_check_fw_ps; + registry_par->power_mgnt = (u8)rtw_power_mgnt; + registry_par->ips_mode = (u8)rtw_ips_mode; + registry_par->lps_level = (u8)rtw_lps_level; + registry_par->radio_enable = (u8)rtw_radio_enable; + registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; + registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; + registry_par->busy_thresh = (u16)rtw_busy_thresh; + /* registry_par->qos_enable = (u8)rtw_qos_enable; */ + registry_par->ack_policy = (u8)rtw_ack_policy; + registry_par->mp_mode = (u8)rtw_mp_mode; + registry_par->software_encrypt = (u8)rtw_software_encrypt; + registry_par->software_decrypt = (u8)rtw_software_decrypt; + + registry_par->acm_method = (u8)rtw_acm_method; + registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode; + registry_par->dynamic_agg_enable = (u8)rtw_dynamic_agg_enable; + + /* UAPSD */ + registry_par->wmm_enable = (u8)rtw_wmm_enable; + registry_par->uapsd_enable = (u8)rtw_uapsd_enable; + registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp; + registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en; + registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en; + registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en; + registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en; + + registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable; + + registry_par->tx_bw_mode = (u8)rtw_tx_bw_mode; + + registry_par->ht_enable = (u8)rtw_ht_enable; + registry_par->bw_mode = (u8)rtw_bw_mode; + registry_par->ampdu_enable = (u8)rtw_ampdu_enable; + registry_par->rx_stbc = (u8)rtw_rx_stbc; + registry_par->rx_ampdu_amsdu = (u8)rtw_rx_ampdu_amsdu; + registry_par->tx_ampdu_amsdu = (u8)rtw_tx_ampdu_amsdu; + registry_par->short_gi = (u8)rtw_short_gi; + registry_par->ldpc_cap = (u8)rtw_ldpc_cap; + registry_par->stbc_cap = (u8)rtw_stbc_cap; + registry_par->beamform_cap = (u8)rtw_beamform_cap; + registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number; + registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number; + rtw_regsty_init_rx_ampdu_sz_limit(registry_par); + + registry_par->vht_enable = (u8)rtw_vht_enable; + registry_par->ampdu_factor = (u8)rtw_ampdu_factor; + registry_par->vht_rx_mcs_map[0] = (u8)(rtw_vht_rx_mcs_map & 0xFF); + registry_par->vht_rx_mcs_map[1] = (u8)((rtw_vht_rx_mcs_map & 0xFF00) >> 8); + + registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit; + registry_par->rf_config = (u8)rtw_rf_config; + registry_par->low_power = (u8)rtw_low_power; + + registry_par->check_hw_status = (u8)rtw_check_hw_status; + + registry_par->wifi_spec = (u8)rtw_wifi_spec; + + if (strlen(rtw_country_code) != 2 + || is_alpha(rtw_country_code[0]) == _FALSE + || is_alpha(rtw_country_code[1]) == _FALSE + ) { + if (rtw_country_code != rtw_country_unspecified) + RTW_ERR("%s discard rtw_country_code not in alpha2\n", __func__); + _rtw_memset(registry_par->alpha2, 0xFF, 2); + } else + _rtw_memcpy(registry_par->alpha2, rtw_country_code, 2); + + registry_par->channel_plan = (u8)rtw_channel_plan; + rtw_regsty_load_excl_chs(registry_par); + + registry_par->special_rf_path = (u8)rtw_special_rf_path; + + registry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake; + registry_par->btcoex = (u8)rtw_btcoex_enable; + registry_par->bt_iso = (u8)rtw_bt_iso; + registry_par->bt_sco = (u8)rtw_bt_sco; + registry_par->bt_ampdu = (u8)rtw_bt_ampdu; + registry_par->ant_num = (u8)rtw_ant_num; + registry_par->single_ant_path = (u8) rtw_single_ant_path; + + registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq; + + registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg; + registry_par->antdiv_type = (u8)rtw_antdiv_type; + + registry_par->drv_ant_band_switch = (u8) rtw_drv_ant_band_switch; + + registry_par->switch_usb_mode = (u8)rtw_switch_usb_mode; + + + registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc; + + + registry_par->max_roaming_times = (u8)rtw_max_roaming_times; + + + registry_par->enable80211d = (u8)rtw_80211d; + + snprintf(registry_par->ifname, 16, "%s", ifname); + snprintf(registry_par->if2name, 16, "%s", if2name); + + registry_par->notch_filter = (u8)rtw_notch_filter; + + + + registry_par->force_igi_lb = (u8)rtw_force_igi_lb; + + registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel; + + registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable; + registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate; + + rtw_regsty_load_target_tx_power(registry_par); + + registry_par->RegPowerBase = 14; + registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G; + registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G; + registry_par->bEn_RFE = 1; + registry_par->RFE_Type = (u8)rtw_RFE_type; + registry_par->PowerTracking_Type = (u8)rtw_powertracking_type; + registry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g; + registry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g; + registry_par->GLNA_Type = (u8)rtw_GLNA_type; + registry_par->load_phy_file = (u8)rtw_load_phy_file; + registry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file; + registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable; + + registry_par->hiq_filter = (u8)rtw_hiq_filter; + + registry_par->adaptivity_en = (u8)rtw_adaptivity_en; + registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode; + registry_par->adaptivity_dml = (u8)rtw_adaptivity_dml; + registry_par->adaptivity_dc_backoff = (u8)rtw_adaptivity_dc_backoff; + registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini; + registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff; + + registry_par->boffefusemask = (u8)rtw_OffEfuseMask; + registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse; + registry_par->reg_rxgain_offset_2g = (u32) rtw_rxgain_offset_2g; + registry_par->reg_rxgain_offset_5gl = (u32) rtw_rxgain_offset_5gl; + registry_par->reg_rxgain_offset_5gm = (u32) rtw_rxgain_offset_5gm; + registry_par->reg_rxgain_offset_5gh = (u32) rtw_rxgain_offset_5gh; + + + + + registry_par->pci_aspm_config = rtw_pci_aspm_enable; + + registry_par->en_napi = (u8)rtw_en_napi; + registry_par->en_gro = (u8)rtw_en_gro; + if (!registry_par->en_napi && registry_par->en_gro) { + registry_par->en_gro = 0; + RTW_WARN("Disable GRO because NAPI is not enabled\n"); + } + + return status; +} + +/** + * rtw_net_set_mac_address + * This callback function is used for the Media Access Control address + * of each net_device needs to be changed. + * + * Arguments: + * @pnetdev: net_device pointer. + * @addr: new MAC address. + * + * Return: + * ret = 0: Permit to change net_device's MAC address. + * ret = -1 (Default): Operation not permitted. + * + * Auther: Arvin Liu + * Date: 2015/05/29 + */ +static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sockaddr *sa = (struct sockaddr *)addr; + int ret = -1; + + /* only the net_device is in down state to permit modifying mac addr */ + if ((pnetdev->flags & IFF_UP) == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT": The net_device's is not in down state\n" + , FUNC_ADPT_ARG(padapter)); + + return ret; + } + + /* if the net_device is linked, it's not permit to modify mac addr */ + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) || + check_fwstate(pmlmepriv, _FW_LINKED) || + check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + RTW_INFO(FUNC_ADPT_FMT": The net_device's is not idle currently\n" + , FUNC_ADPT_ARG(padapter)); + + return ret; + } + + /* check whether the input mac address is valid to permit modifying mac addr */ + if (rtw_check_invalid_mac_address(sa->sa_data, _FALSE) == _TRUE) { + RTW_INFO(FUNC_ADPT_FMT": Invalid Mac Addr for "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); + + return ret; + } + + _rtw_memcpy(adapter_mac_addr(padapter), sa->sa_data, ETH_ALEN); /* set mac addr to adapter */ + _rtw_memcpy(pnetdev->dev_addr, sa->sa_data, ETH_ALEN); /* set mac addr to net_device */ + + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ + rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */ + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + + RTW_INFO(FUNC_ADPT_FMT": Set Mac Addr to "MAC_FMT" Successfully\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); + + ret = 0; + + return ret; +} + +static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct recv_priv *precvpriv = &(padapter->recvpriv); + + padapter->stats.tx_packets = pxmitpriv->tx_pkts;/* pxmitpriv->tx_pkts++; */ + padapter->stats.rx_packets = precvpriv->rx_pkts;/* precvpriv->rx_pkts++; */ + padapter->stats.tx_dropped = pxmitpriv->tx_drop; + padapter->stats.rx_dropped = precvpriv->rx_drop; + padapter->stats.tx_bytes = pxmitpriv->tx_bytes; + padapter->stats.rx_bytes = precvpriv->rx_bytes; + + return &padapter->stats; +} + +/* + * AC to queue mapping + * + * AC_VO -> queue 0 + * AC_VI -> queue 1 + * AC_BE -> queue 2 + * AC_BK -> queue 3 + */ +static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 }; + +/* Given a data frame determine the 802.1p/1d tag to use. */ +unsigned int rtw_classify8021d(struct sk_buff *skb) +{ + unsigned int dscp; + + /* skb->priority values from 256->263 are magic values to + * directly indicate a specific 802.1d priority. This is used + * to allow 802.1d priority to be passed directly in from VLAN + * tags, etc. + */ + if (skb->priority >= 256 && skb->priority <= 263) + return skb->priority - 256; + + switch (skb->protocol) { + case htons(ETH_P_IP): + dscp = ip_hdr(skb)->tos & 0xfc; + break; + default: + return 0; + } + + return dscp >> 5; +} + +static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb, + struct net_device *sb_dev) +{ + _adapter *padapter = rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + skb->priority = rtw_classify8021d(skb); + + if (pmlmepriv->acm_mask != 0) + skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority); + + return rtw_1d_to_queue[skb->priority]; +} + +u16 rtw_recv_select_queue(struct sk_buff *skb) +{ + struct iphdr *piphdr; + unsigned int dscp; + u16 eth_type; + u32 priority; + u8 *pdata = skb->data; + + _rtw_memcpy(ð_type, pdata + (ETH_ALEN << 1), 2); + + switch (eth_type) { + case htons(ETH_P_IP): + + piphdr = (struct iphdr *)(pdata + ETH_HLEN); + + dscp = piphdr->tos & 0xfc; + + priority = dscp >> 5; + + break; + default: + priority = 0; + } + + return rtw_1d_to_queue[priority]; + +} + +static int rtw_ndev_notifier_call(struct notifier_block *nb, unsigned long state, void *ptr) +{ + struct net_device *dev = netdev_notifier_info_to_dev(ptr); + + if (dev == NULL) + return NOTIFY_DONE; + + if (dev->netdev_ops == NULL) + return NOTIFY_DONE; + + if (dev->netdev_ops->ndo_do_ioctl == NULL) + return NOTIFY_DONE; + + if (dev->netdev_ops->ndo_do_ioctl != rtw_ioctl) + return NOTIFY_DONE; + + RTW_INFO(FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(dev), state); + + return NOTIFY_DONE; +} + +static struct notifier_block rtw_ndev_notifier = { + .notifier_call = rtw_ndev_notifier_call, +}; + +int rtw_ndev_notifier_register(void) +{ + return register_netdevice_notifier(&rtw_ndev_notifier); +} + +void rtw_ndev_notifier_unregister(void) +{ + unregister_netdevice_notifier(&rtw_ndev_notifier); +} + +int rtw_ndev_init(struct net_device *dev) +{ + _adapter *adapter = rtw_netdev_priv(dev); + + RTW_PRINT(FUNC_ADPT_FMT" if%d mac_addr="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1), MAC_ARG(dev->dev_addr)); + strncpy(adapter->old_ifname, dev->name, IFNAMSIZ); + adapter->old_ifname[IFNAMSIZ - 1] = '\0'; + + return 0; +} + +void rtw_ndev_uninit(struct net_device *dev) +{ + _adapter *adapter = rtw_netdev_priv(dev); + + RTW_PRINT(FUNC_ADPT_FMT" if%d\n" + , FUNC_ADPT_ARG(adapter), (adapter->iface_id + 1)); +} + +static const struct net_device_ops rtw_netdev_ops = { + .ndo_init = rtw_ndev_init, + .ndo_uninit = rtw_ndev_uninit, + .ndo_open = netdev_open, + .ndo_stop = netdev_close, + .ndo_start_xmit = rtw_xmit_entry, + .ndo_select_queue = rtw_select_queue, + .ndo_set_mac_address = rtw_net_set_mac_address, + .ndo_get_stats = rtw_net_get_stats, + .ndo_do_ioctl = rtw_ioctl, +}; + +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) +{ + _adapter *padapter = rtw_netdev_priv(pnetdev); + + if (dev_alloc_name(pnetdev, ifname) < 0) + RTW_ERR("dev_alloc_name, fail!\n"); + + netif_carrier_off(pnetdev); + /* rtw_netif_stop_queue(pnetdev); */ + + return 0; +} + +void rtw_hook_if_ops(struct net_device *ndev) +{ + ndev->netdev_ops = &rtw_netdev_ops; +} + +struct net_device *rtw_init_netdev(_adapter *old_padapter) +{ + _adapter *padapter; + struct net_device *pnetdev; + + if (old_padapter != NULL) { + rtw_os_ndev_free(old_padapter); + pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter); + } else + pnetdev = rtw_alloc_etherdev(sizeof(_adapter)); + + if (!pnetdev) + return NULL; + + padapter = rtw_netdev_priv(pnetdev); + padapter->pnetdev = pnetdev; + + rtw_hook_if_ops(pnetdev); + + pnetdev->watchdog_timeo = HZ * 3; /* 3 second timeout */ + + pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def; + + return pnetdev; +} + +int rtw_os_ndev_alloc(_adapter *adapter) +{ + int ret = _FAIL; + struct net_device *ndev = NULL; + + ndev = rtw_init_netdev(adapter); + if (ndev == NULL) { + rtw_warn_on(1); + goto exit; + } + SET_NETDEV_DEV(ndev, dvobj_to_dev(adapter_to_dvobj(adapter))); + + if (adapter_to_dvobj(adapter)->bdma64) + ndev->features |= NETIF_F_HIGHDMA; + ndev->irq = adapter_to_dvobj(adapter)->irq; + + + ret = _SUCCESS; + + if (ret != _SUCCESS && ndev) + rtw_free_netdev(ndev); +exit: + return ret; +} + +void rtw_os_ndev_free(_adapter *adapter) +{ + + if (adapter->pnetdev) { + rtw_free_netdev(adapter->pnetdev); + adapter->pnetdev = NULL; + } +} + +int rtw_os_ndev_register(_adapter *adapter, const char *name) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int ret = _SUCCESS; + struct net_device *ndev = adapter->pnetdev; + u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + + netif_napi_add(ndev, &adapter->napi, rtw_recv_napi_poll, RTL_NAPI_WEIGHT); + + + /* alloc netdev name */ + rtw_init_netdev_name(ndev, name); + + _rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN); + + /* Tell the network stack we exist */ + + if (rtnl_lock_needed) + ret = (register_netdev(ndev) == 0) ? _SUCCESS : _FAIL; + else + ret = (register_netdevice(ndev) == 0) ? _SUCCESS : _FAIL; + + if (ret == _SUCCESS) + adapter->registered = 1; + else + RTW_INFO(FUNC_NDEV_FMT" if%d Failed!\n", FUNC_NDEV_ARG(ndev), (adapter->iface_id + 1)); + + if (ret != _SUCCESS) + netif_napi_del(&adapter->napi); + + return ret; +} + +void rtw_os_ndev_unregister(_adapter *adapter) +{ + struct net_device *netdev = NULL; + + if (adapter == NULL || adapter->registered == 0) + return; + + adapter->ndev_unregistering = 1; + + netdev = adapter->pnetdev; + + + if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) { + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + u8 rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + + if (rtnl_lock_needed) + unregister_netdev(netdev); + else + unregister_netdevice(netdev); + } + + + if (adapter->napi_state == NAPI_ENABLE) { + napi_disable(&adapter->napi); + adapter->napi_state = NAPI_DISABLE; + } + netif_napi_del(&adapter->napi); + + adapter->registered = 0; + adapter->ndev_unregistering = 0; +} + +/** + * rtw_os_ndev_init - Allocate and register OS layer net device and relating structures for @adapter + * @adapter: the adapter on which this function applies + * @name: the requesting net device name + * + * Returns: + * _SUCCESS or _FAIL + */ +int rtw_os_ndev_init(_adapter *adapter, const char *name) +{ + int ret = _FAIL; + + if (rtw_os_ndev_alloc(adapter) != _SUCCESS) + goto exit; + + if (rtw_os_ndev_register(adapter, name) != _SUCCESS) + goto os_ndev_free; + + ret = _SUCCESS; + +os_ndev_free: + if (ret != _SUCCESS) + rtw_os_ndev_free(adapter); +exit: + return ret; +} + +/** + * rtw_os_ndev_deinit - Unregister and free OS layer net device and relating structures for @adapter + * @adapter: the adapter on which this function applies + */ +void rtw_os_ndev_deinit(_adapter *adapter) +{ + rtw_os_ndev_unregister(adapter); + rtw_os_ndev_free(adapter); +} + +int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj) +{ + int i, status = _SUCCESS; + _adapter *adapter; + + + for (i = 0; i < dvobj->iface_nums; i++) { + + if (i >= CONFIG_IFACE_NUMBER) { + RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER); + rtw_warn_on(1); + continue; + } + + adapter = dvobj->padapters[i]; + if (adapter && !adapter->pnetdev) { + + #ifdef CONFIG_RTW_DYNAMIC_NDEV + if (!is_primary_adapter(adapter)) + continue; + #endif + + status = rtw_os_ndev_alloc(adapter); + if (status != _SUCCESS) { + rtw_warn_on(1); + break; + } + } + } + + if (status != _SUCCESS) { + for (; i >= 0; i--) { + adapter = dvobj->padapters[i]; + if (adapter && adapter->pnetdev) + rtw_os_ndev_free(adapter); + } + } + + return status; +} + +void rtw_os_ndevs_free(struct dvobj_priv *dvobj) +{ + int i; + _adapter *adapter = NULL; + + for (i = 0; i < dvobj->iface_nums; i++) { + + if (i >= CONFIG_IFACE_NUMBER) { + RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER); + rtw_warn_on(1); + continue; + } + + adapter = dvobj->padapters[i]; + + if (adapter == NULL) + continue; + + rtw_os_ndev_free(adapter); + } + +} + +u32 rtw_start_drv_threads(_adapter *padapter) +{ + u32 _status = _SUCCESS; + + + + if (is_primary_adapter(padapter)) { + padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); + if (IS_ERR(padapter->cmdThread)) + _status = _FAIL; + else + _rtw_down_sema(&padapter->cmdpriv.start_cmdthread_sema); /* wait for cmd_thread to run */ + } + + + rtw_hal_start_thread(padapter); + return _status; + +} + +void rtw_stop_drv_threads(_adapter *padapter) +{ + + if (is_primary_adapter(padapter)) + rtw_stop_cmd_thread(padapter); + + + + + rtw_hal_stop_thread(padapter); +} + +u8 rtw_init_default_value(_adapter *padapter); +u8 rtw_init_default_value(_adapter *padapter) +{ + u8 ret = _SUCCESS; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + + /* xmit_priv */ + pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; + pxmitpriv->vcs = pregistrypriv->vcs_type; + pxmitpriv->vcs_type = pregistrypriv->vcs_type; + /* pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; */ + pxmitpriv->frag_len = pregistrypriv->frag_thresh; + + /* security_priv */ + /* rtw_get_encrypt_decrypt_from_registrypriv(padapter); */ + psecuritypriv->binstallGrpkey = _FAIL; + psecuritypriv->sw_encrypt = pregistrypriv->software_encrypt; + psecuritypriv->sw_decrypt = pregistrypriv->software_decrypt; + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */ + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + + psecuritypriv->dot11PrivacyKeyIndex = 0; + + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + psecuritypriv->dot118021XGrpKeyid = 1; + + psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; + psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled; + + /* pwrctrl_priv */ + + /* registry_priv */ + rtw_init_registrypriv_dev_network(padapter); + rtw_update_registrypriv_dev_network(padapter); + + /* hal_priv */ + rtw_hal_def_value_init(padapter); + + /* misc. */ + RTW_ENABLE_FUNC(padapter, DF_RX_BIT); + RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + padapter->bLinkInfoDump = 0; + padapter->bNotifyChannelChange = _FALSE; + padapter->bShowGetP2PState = 1; + + /* for debug purpose */ + padapter->fix_rate = 0xFF; + padapter->data_fb = 0; + padapter->fix_bw = 0xFF; + padapter->power_offset = 0; + padapter->rsvd_page_offset = 0; + padapter->rsvd_page_num = 0; + + padapter->driver_tx_bw_mode = pregistrypriv->tx_bw_mode; + + padapter->driver_ampdu_spacing = 0xFF; + padapter->driver_rx_ampdu_factor = 0xFF; + padapter->driver_rx_ampdu_spacing = 0xFF; + padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; + padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID; + padapter->driver_tx_max_agg_num = 0xFF; + padapter->napi_state = NAPI_DISABLE; + padapter->tsf.sync_port = MAX_HW_PORT; + padapter->tsf.offset = 0; + + return ret; +} + +struct dvobj_priv *devobj_init(void) +{ + struct dvobj_priv *pdvobj = NULL; + + pdvobj = (struct dvobj_priv *)rtw_zmalloc(sizeof(*pdvobj)); + if (pdvobj == NULL) + return NULL; + + _rtw_mutex_init(&pdvobj->hw_init_mutex); + _rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex); + _rtw_mutex_init(&pdvobj->setch_mutex); + _rtw_mutex_init(&pdvobj->setbw_mutex); + _rtw_mutex_init(&pdvobj->rf_read_reg_mutex); + + + pdvobj->processing_dev_remove = _FALSE; + + ATOMIC_SET(&pdvobj->disable_func, 0); + + rtw_macid_ctl_init(&pdvobj->macid_ctl); + _rtw_spinlock_init(&pdvobj->cam_ctl.lock); + _rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex); + + pdvobj->nr_ap_if = 0; + pdvobj->inter_bcn_space = DEFAULT_BCN_INTERVAL; /* default value is equal to the default beacon_interval (100ms) */ + _rtw_init_queue(&pdvobj->ap_if_q); + + rtw_init_timer(&(pdvobj->dynamic_chk_timer), NULL, rtw_dynamic_check_timer_handlder, pdvobj); + + return pdvobj; + +} + +void devobj_deinit(struct dvobj_priv *pdvobj) +{ + if (!pdvobj) + return; + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ + + _rtw_mutex_free(&pdvobj->hw_init_mutex); + _rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex); + + + _rtw_mutex_free(&pdvobj->setch_mutex); + _rtw_mutex_free(&pdvobj->setbw_mutex); + _rtw_mutex_free(&pdvobj->rf_read_reg_mutex); + + rtw_macid_ctl_deinit(&pdvobj->macid_ctl); + _rtw_spinlock_free(&pdvobj->cam_ctl.lock); + _rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex); + + + _rtw_spinlock_free(&(pdvobj->ap_if_q.lock)); + + rtw_mfree((u8 *)pdvobj, sizeof(*pdvobj)); +} + +inline u8 rtw_rtnl_lock_needed(struct dvobj_priv *dvobj) +{ + if (dvobj->rtnl_lock_holder && dvobj->rtnl_lock_holder == current) + return 0; + return 1; +} + +inline void rtw_set_rtnl_lock_holder(struct dvobj_priv *dvobj, _thread_hdl_ thd_hdl) +{ + rtw_warn_on(!rtnl_is_locked()); + + if (!thd_hdl || rtnl_is_locked()) + dvobj->rtnl_lock_holder = thd_hdl; + + if (dvobj->rtnl_lock_holder && 0) + RTW_INFO("rtnl_lock_holder: %s:%d\n", current->comm, current->pid); +} + +u8 rtw_reset_drv_sw(_adapter *padapter) +{ + u8 ret8 = _SUCCESS; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + /* hal_priv */ + if (is_primary_adapter(padapter)) + rtw_hal_def_value_init(padapter); + + RTW_ENABLE_FUNC(padapter, DF_RX_BIT); + RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + + padapter->tsf.sync_port = MAX_HW_PORT; + padapter->tsf.offset = 0; + + padapter->bLinkInfoDump = 0; + + padapter->xmitpriv.tx_pkts = 0; + padapter->recvpriv.rx_pkts = 0; + + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + + /* pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; */ + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING); + + + if (is_primary_adapter(padapter)) + rtw_hal_sreset_reset_value(padapter); + pwrctrlpriv->pwr_state_check_cnts = 0; + + /* mlmeextpriv */ + mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE); + + rtw_set_signal_stat_timer(&padapter->recvpriv); + + return ret8; +} + +u8 rtw_init_drv_sw(_adapter *padapter) +{ + + u8 ret8 = _SUCCESS; + + _rtw_init_listhead(&padapter->list); + + ret8 = rtw_init_default_value(padapter); + + if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) { + ret8 = _FAIL; + goto exit; + } + + padapter->cmdpriv.padapter = padapter; + + if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) { + ret8 = _FAIL; + goto exit; + } + + rtw_rfctl_init(padapter); + + if (rtw_init_mlme_priv(padapter) == _FAIL) { + ret8 = _FAIL; + goto exit; + } + + rtw_init_wifidirect_timers(padapter); + init_wifidirect_info(padapter, P2P_ROLE_DISABLE); + reset_global_wifidirect_info(padapter); + if (rtw_init_wifi_display_info(padapter) == _FAIL) + RTW_ERR("Can't init init_wifi_display_info\n"); + + if (init_mlme_ext_priv(padapter) == _FAIL) { + ret8 = _FAIL; + goto exit; + } + + if (_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) { + RTW_INFO("Can't _rtw_init_xmit_priv\n"); + ret8 = _FAIL; + goto exit; + } + + if (_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) { + RTW_INFO("Can't _rtw_init_recv_priv\n"); + ret8 = _FAIL; + goto exit; + } + /* add for CONFIG_IEEE80211W, none 11w also can use */ + _rtw_spinlock_init(&padapter->security_key_mutex); + + /* We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). */ + /* _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); */ + + if (_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) { + RTW_INFO("Can't _rtw_init_sta_priv\n"); + ret8 = _FAIL; + goto exit; + } + + padapter->stapriv.padapter = padapter; + padapter->setband = WIFI_FREQUENCY_BAND_AUTO; + padapter->fix_rate = 0xFF; + padapter->power_offset = 0; + padapter->rsvd_page_offset = 0; + padapter->rsvd_page_num = 0; + + padapter->data_fb = 0; + padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; + padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID; + rtw_init_bcmc_stainfo(padapter); + + rtw_init_pwrctrl_priv(padapter); + + /* _rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv)); */ /* move to mlme_priv */ + + if (init_mp_priv(padapter) == _FAIL) + RTW_INFO("%s: initialize MP private data Fail!\n", __func__); + + rtw_hal_dm_init(padapter); + rtw_hal_sreset_init(padapter); + + _rtw_spinlock_init(&padapter->br_ext_lock); + + +exit: + + return ret8; + +} + + +void rtw_cancel_all_timer(_adapter *padapter) +{ + + _cancel_timer_ex(&padapter->mlmepriv.assoc_timer); + + _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer); + + + _cancel_timer_ex(&adapter_to_dvobj(padapter)->dynamic_chk_timer); + + /* cancel sw led timer */ + rtw_hal_sw_led_deinit(padapter); + + _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer)); + + + + + _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer); + + + /* cancel dm timer */ + rtw_hal_dm_deinit(padapter); + +#ifdef CONFIG_PLATFORM_FS_MX61 + msleep(50); +#endif +} + +u8 rtw_free_drv_sw(_adapter *padapter) +{ + + /* we can call rtw_p2p_enable here, but: */ + /* 1. rtw_p2p_enable may have IO operation */ + /* 2. rtw_p2p_enable is bundled with wext interface */ + { + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + _cancel_timer_ex(&pwdinfo->find_phase_timer); + _cancel_timer_ex(&pwdinfo->restore_p2p_state_timer); + _cancel_timer_ex(&pwdinfo->pre_tx_scan_timer); + rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); + } + } + /* add for CONFIG_IEEE80211W, none 11w also can use */ + _rtw_spinlock_free(&padapter->security_key_mutex); + + _rtw_spinlock_free(&padapter->br_ext_lock); + + free_mlme_ext_priv(&padapter->mlmeextpriv); + + rtw_free_cmd_priv(&padapter->cmdpriv); + + rtw_free_evt_priv(&padapter->evtpriv); + + rtw_free_mlme_priv(&padapter->mlmepriv); + + /* free_io_queue(padapter); */ + + _rtw_free_xmit_priv(&padapter->xmitpriv); + + _rtw_free_sta_priv(&padapter->stapriv); /* will free bcmc_stainfo here */ + + _rtw_free_recv_priv(&padapter->recvpriv); + + rtw_free_pwrctrl_priv(padapter); + + /* rtw_mfree((void *)padapter, sizeof (padapter)); */ + + + rtw_hal_free_data(padapter); + + /* free the old_pnetdev */ + if (padapter->rereg_nd_name_priv.old_pnetdev) { + free_netdev(padapter->rereg_nd_name_priv.old_pnetdev); + padapter->rereg_nd_name_priv.old_pnetdev = NULL; + } + + return _SUCCESS; + +} +void rtw_intf_start(_adapter *adapter) +{ + if (adapter->intf_start) + adapter->intf_start(adapter); +} +void rtw_intf_stop(_adapter *adapter) +{ + if (adapter->intf_stop) + adapter->intf_stop(adapter); +} + + +int rtw_os_ndevs_register(struct dvobj_priv *dvobj) +{ + int i, status = _SUCCESS; + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + _adapter *adapter; + + + for (i = 0; i < dvobj->iface_nums; i++) { + + if (i >= CONFIG_IFACE_NUMBER) { + RTW_ERR("%s %d >= CONFIG_IFACE_NUMBER(%d)\n", __func__, i, CONFIG_IFACE_NUMBER); + rtw_warn_on(1); + continue; + } + + adapter = dvobj->padapters[i]; + if (adapter) { + char *name; + + #ifdef CONFIG_RTW_DYNAMIC_NDEV + if (!is_primary_adapter(adapter)) + continue; + #endif + + if (adapter->iface_id == IFACE_ID0) + name = regsty->ifname; + else if (adapter->iface_id == IFACE_ID1) + name = regsty->if2name; + else + name = "wlan%d"; + + status = rtw_os_ndev_register(adapter, name); + + if (status != _SUCCESS) { + rtw_warn_on(1); + break; + } + } + } + + if (status != _SUCCESS) { + for (; i >= 0; i--) { + adapter = dvobj->padapters[i]; + if (adapter) + rtw_os_ndev_unregister(adapter); + } + } + + return status; +} + +void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj) +{ + int i; + _adapter *adapter = NULL; + + for (i = 0; i < dvobj->iface_nums; i++) { + adapter = dvobj->padapters[i]; + + if (adapter == NULL) + continue; + + rtw_os_ndev_unregister(adapter); + } + +} + +/** + * rtw_os_ndevs_init - Allocate and register OS layer net devices and relating structures for @dvobj + * @dvobj: the dvobj on which this function applies + * + * Returns: + * _SUCCESS or _FAIL + */ +int rtw_os_ndevs_init(struct dvobj_priv *dvobj) +{ + int ret = _FAIL; + + if (rtw_os_ndevs_alloc(dvobj) != _SUCCESS) + goto exit; + + if (rtw_os_ndevs_register(dvobj) != _SUCCESS) + goto os_ndevs_free; + + ret = _SUCCESS; + +os_ndevs_free: + if (ret != _SUCCESS) + rtw_os_ndevs_free(dvobj); +exit: + return ret; +} + +/** + * rtw_os_ndevs_deinit - Unregister and free OS layer net devices and relating structures for @dvobj + * @dvobj: the dvobj on which this function applies + */ +void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj) +{ + rtw_os_ndevs_unregister(dvobj); + rtw_os_ndevs_free(dvobj); +} + +void netdev_br_init(struct net_device *netdev) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + + rcu_read_lock(); + + /* if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) */ + { + /* struct net_bridge *br = netdev->br_port->br; */ /* ->dev->dev_addr; */ + if (rcu_dereference(adapter->pnetdev->rx_handler_data)) + { + struct net_device *br_netdev; + struct net *devnet = NULL; + + devnet = dev_net(netdev); + br_netdev = dev_get_by_name(devnet, "br0"); + + if (br_netdev) { + memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN); + dev_put(br_netdev); + } else + printk("%s()-%d: dev_get_by_name() failed!", __FUNCTION__, __LINE__); + } + + adapter->ethBrExtInfo.addPPPoETag = 1; + } + + rcu_read_unlock(); +} + +int _netdev_open(struct net_device *pnetdev) +{ + uint status; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + + padapter->netif_up = _TRUE; + + + if (pwrctrlpriv->ps_flag == _TRUE) { + padapter->net_closed = _FALSE; + goto netdev_open_normal_process; + } + + if (padapter->bup == _FALSE) { + + rtw_clr_surprise_removed(padapter); + rtw_clr_drv_stopped(padapter); + + status = rtw_hal_init(padapter); + if (status == _FAIL) { + goto netdev_open_error; + } + + RTW_INFO("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); + + status = rtw_start_drv_threads(padapter); + if (status == _FAIL) { + RTW_INFO("Initialize driver software resource Failed!\n"); + goto netdev_open_error; + } + + if(padapter->napi_state == NAPI_DISABLE) { + napi_enable(&padapter->napi); + padapter->napi_state = NAPI_ENABLE; + } + + rtw_intf_start(padapter); + + + rtw_led_control(padapter, LED_CTL_NO_LINK); + + padapter->bup = _TRUE; + pwrctrlpriv->bips_processing = _FALSE; + + } + padapter->net_closed = _FALSE; + + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); + +#ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(pwrctrlpriv); +#endif + + /* netif_carrier_on(pnetdev); */ /* call this func when rtw_joinbss_event_callback return success */ + rtw_netif_wake_queue(pnetdev); + + netdev_br_init(pnetdev); + +netdev_open_normal_process: + + + RTW_INFO("-871x_drv - drv_open, bup=%d\n", padapter->bup); + + return 0; + +netdev_open_error: + + padapter->bup = _FALSE; + + if(padapter->napi_state == NAPI_ENABLE) { + napi_disable(&padapter->napi); + padapter->napi_state = NAPI_DISABLE; + } + + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + + RTW_INFO("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); + + return -1; + +} + +int netdev_open(struct net_device *pnetdev) +{ + int ret = _FALSE; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (pwrctrlpriv->bInSuspend == _TRUE) { + RTW_INFO(" [WARN] "ADPT_FMT" %s failed, bInSuspend=%d\n", ADPT_ARG(padapter), __func__, pwrctrlpriv->bInSuspend); + return 0; + } + + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + if (is_primary_adapter(padapter)) + ret = _netdev_open(pnetdev); + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + + + return ret; +} + +int ips_netdrv_open(_adapter *padapter) +{ + int status = _SUCCESS; + /* struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); */ + + padapter->net_closed = _FALSE; + + RTW_INFO("===> %s.........\n", __FUNCTION__); + + rtw_clr_drv_stopped(padapter); + /* padapter->bup = _TRUE; */ + + status = rtw_hal_init(padapter); + if (status == _FAIL) { + goto netdev_open_error; + } + rtw_intf_start(padapter); + +#ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter)); +#endif + _set_timer(&adapter_to_dvobj(padapter)->dynamic_chk_timer, 2000); + + return _SUCCESS; + +netdev_open_error: + /* padapter->bup = _FALSE; */ + RTW_INFO("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup); + + return _FAIL; +} + +int rtw_ips_pwr_up(_adapter *padapter) +{ + int result; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + u32 start_time = rtw_get_current_time(); + RTW_INFO("===> rtw_ips_pwr_up..............\n"); + +#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) + if (psrtpriv->silent_reset_inprogress == _TRUE) +#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */ + rtw_reset_drv_sw(padapter); + + result = ips_netdrv_open(padapter); + + rtw_led_control(padapter, LED_CTL_NO_LINK); + + RTW_INFO("<=== rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time)); + return result; + +} + +void rtw_ips_pwr_down(_adapter *padapter) +{ + u32 start_time = rtw_get_current_time(); + RTW_INFO("===> rtw_ips_pwr_down...................\n"); + + padapter->net_closed = _TRUE; + + rtw_ips_dev_unload(padapter); + RTW_INFO("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time)); +} +void rtw_ips_dev_unload(_adapter *padapter) +{ + struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + RTW_INFO("====> %s...\n", __FUNCTION__); + +#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) + if (psrtpriv->silent_reset_inprogress == _TRUE) +#endif /* defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) */ + { + rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0); + rtw_intf_stop(padapter); + } + + if (!rtw_is_surprise_removed(padapter)) + rtw_hal_deinit(padapter); + +} + +int pm_netdev_open(struct net_device *pnetdev, u8 bnormal) +{ + int status = 0; + + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + + if (_TRUE == bnormal) { + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + status = _netdev_open(pnetdev); + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + } + else + status = (_SUCCESS == ips_netdrv_open(padapter)) ? (0) : (-1); + + return status; +} + +static int netdev_close(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + RTW_INFO(FUNC_NDEV_FMT" , bup=%d\n", FUNC_NDEV_ARG(pnetdev), padapter->bup); + if (pwrctl->bInternalAutoSuspend == _TRUE) { + /* rtw_pwr_wakeup(padapter); */ + if (pwrctl->rf_pwrstate == rf_off) + pwrctl->ps_flag = _TRUE; + } + padapter->net_closed = _TRUE; + padapter->netif_up = _FALSE; + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + + /* if (!rtw_is_hw_init_completed(padapter)) { + RTW_INFO("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE"); + + rtw_set_drv_stopped(padapter); + + rtw_dev_unload(padapter); + } + else*/ + if (pwrctl->rf_pwrstate == rf_on) { + RTW_INFO("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE"); + + /* s1. */ + if (pnetdev) + rtw_netif_stop_queue(pnetdev); + + /* s2. */ + LeaveAllPowerSaveMode(padapter); + rtw_disassoc_cmd(padapter, 500, RTW_CMDF_DIRECTLY); + /* s2-2. indicate disconnect to os */ + rtw_indicate_disconnect(padapter, 0, _FALSE); + /* s2-3. */ + rtw_free_assoc_resources(padapter, 1); + /* s2-4. */ + rtw_free_network_queue(padapter, _TRUE); + /* Close LED */ + rtw_led_control(padapter, LED_CTL_POWER_OFF); + } + + /* if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) */ + { + /* void nat25_db_cleanup(_adapter *priv); */ + nat25_db_cleanup(padapter); + } + + if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE)) + rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); + + + + RTW_INFO("-871x_drv - drv_close, bup=%d\n", padapter->bup); + + return 0; + +} + +int pm_netdev_close(struct net_device *pnetdev, u8 bnormal) +{ + int status = 0; + + status = netdev_close(pnetdev); + + return status; +} + +void rtw_ndev_destructor(struct net_device *ndev) +{ + RTW_INFO(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + free_netdev(ndev); +} + + +void rtw_dev_unload(PADAPTER padapter) +{ + struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct dvobj_priv *pobjpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &pobjpriv->drv_dbg; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 cnt = 0; + + if (padapter->bup == _TRUE) { + RTW_INFO("==> "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + rtw_set_drv_stopped(padapter); + if (padapter->xmitpriv.ack_tx) + rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); + + rtw_intf_stop(padapter); + + if (!pwrctl->bInternalAutoSuspend) + rtw_stop_drv_threads(padapter); + + while (ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE) { + if (cnt > 5) { + RTW_INFO("stop cmdthd timeout\n"); + break; + } else { + cnt++; + RTW_INFO("cmdthd is running(%d)\n", cnt); + rtw_msleep_os(10); + } + } + + /* check the status of IPS */ + if (rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { /* check HW status and SW state */ + RTW_PRINT("%s: driver in IPS-FWLPS\n", __func__); + pdbgpriv->dbg_dev_unload_inIPS_cnt++; + } else + RTW_PRINT("%s: driver not in IPS\n", __func__); + + if (!rtw_is_surprise_removed(padapter)) { + rtw_btcoex_IpsNotify(padapter, pwrctl->ips_mode_req); + { + /* amy modify 20120221 for power seq is different between driver open and ips */ + rtw_hal_deinit(padapter); + } + rtw_set_surprise_removed(padapter); + } + + padapter->bup = _FALSE; + + RTW_INFO("<== "FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + } else { + RTW_INFO("%s: bup==_FALSE\n", __FUNCTION__); + } + rtw_cancel_all_timer(padapter); +} + +int rtw_suspend_free_assoc_resource(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct net_device *pnetdev = padapter->pnetdev; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) + && check_fwstate(pmlmepriv, _FW_LINKED) + && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + ) { + RTW_INFO("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n", __FUNCTION__, + pmlmepriv->cur_network.network.Ssid.Ssid, + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.SsidLength, + pmlmepriv->assoc_ssid.SsidLength); + rtw_set_to_roam(padapter, 1); + } + } + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) { + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); + /* s2-2. indicate disconnect to os */ + rtw_indicate_disconnect(padapter, 0, _FALSE); + } + else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) + rtw_sta_flush(padapter, _TRUE); + + /* s2-3. */ + rtw_free_assoc_resources(padapter, 1); + + /* s2-4. */ + rtw_free_network_queue(padapter, _TRUE); + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + RTW_PRINT("%s: fw_under_survey\n", __func__); + rtw_indicate_scan_done(padapter, 1); + clr_fwstate(pmlmepriv, _FW_UNDER_SURVEY); + } + + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + RTW_PRINT("%s: fw_under_linking\n", __FUNCTION__); + rtw_indicate_disconnect(padapter, 0, _FALSE); + } + + RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); + return _SUCCESS; +} + + + +int rtw_suspend_normal(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + int ret = _SUCCESS; + + RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_SUSPEND); + + rtw_mi_netif_stop_queue(padapter, _TRUE); + + rtw_mi_suspend_free_assoc_resource(padapter); + + rtw_led_control(padapter, LED_CTL_POWER_OFF); + + if ((rtw_hal_check_ips_status(padapter) == _TRUE) + || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) + RTW_PRINT("%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__); + + rtw_dev_unload(padapter); + + /* sdio_deinit(adapter_to_dvobj(padapter)); */ + if (padapter->intf_deinit) + padapter->intf_deinit(adapter_to_dvobj(padapter)); + +#if !(CONFIG_RTW_SDIO_KEEP_IRQ) + if(padapter->intf_free_irq) + padapter->intf_free_irq(adapter_to_dvobj(padapter)); +#endif + + RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); + return ret; +} + +int rtw_suspend_common(_adapter *padapter) +{ + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + int ret = 0; + u32 start_time = rtw_get_current_time(); + + RTW_PRINT(" suspend start\n"); + RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid); + + pdbgpriv->dbg_suspend_cnt++; + + pwrpriv->bInSuspend = _TRUE; + + while (pwrpriv->bips_processing == _TRUE) + rtw_msleep_os(1); + +#ifdef CONFIG_IOL_READ_EFUSE_MAP + if (!padapter->bup) { + u8 bMacPwrCtrlOn = _FALSE; + rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if (bMacPwrCtrlOn) + rtw_hal_power_off(padapter); + } +#endif + + if ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) { + RTW_INFO("%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n", __func__ + , padapter->bup + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False"); + pdbgpriv->dbg_suspend_error_cnt++; + goto exit; + } + rtw_ps_deny(padapter, PS_DENY_SUSPEND); + + rtw_mi_cancel_all_timer(padapter); + LeaveAllPowerSaveModeDirect(padapter); + rtw_stop_cmd_thread(padapter); + + rtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND); + + if (rtw_mi_check_status(padapter, MI_AP_MODE) == _FALSE) { + rtw_suspend_normal(padapter); + } else if (rtw_mi_check_status(padapter, MI_AP_MODE)) { + rtw_suspend_normal(padapter); + } + + RTW_PRINT("rtw suspend success in %d ms\n", + rtw_get_passing_time_ms(start_time)); + +exit: + RTW_INFO("<=== %s return %d.............. in %dms\n", __FUNCTION__ + , ret, rtw_get_passing_time_ms(start_time)); + + return ret; +} + + + +void rtw_mi_resume_process_normal(_adapter *padapter) +{ + int i; + _adapter *iface; + struct mlme_priv *pmlmepriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + pmlmepriv = &iface->mlmepriv; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) + rtw_roaming(padapter, NULL); + + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + rtw_ap_restore_network(padapter); + } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + else + RTW_INFO(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + } + } +} + +int rtw_resume_process_normal(_adapter *padapter) +{ + struct net_device *pnetdev; + struct pwrctrl_priv *pwrpriv; + struct dvobj_priv *psdpriv; + struct debug_priv *pdbgpriv; + + int ret = _SUCCESS; + + if (!padapter) { + ret = -1; + goto exit; + } + + pnetdev = padapter->pnetdev; + pwrpriv = adapter_to_pwrctl(padapter); + psdpriv = padapter->dvobj; + pdbgpriv = &psdpriv->drv_dbg; + + RTW_INFO("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + /* interface init */ + /* if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) */ + if ((padapter->intf_init) && (padapter->intf_init(adapter_to_dvobj(padapter)) != _SUCCESS)) { + ret = -1; + goto exit; + } + rtw_clr_surprise_removed(padapter); + rtw_hal_disable_interrupt(padapter); +#if !(CONFIG_RTW_SDIO_KEEP_IRQ) + /* if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) */ + if ((padapter->intf_alloc_irq) && (padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) { + ret = -1; + goto exit; + } +#endif + + rtw_mi_reset_drv_sw(padapter); + + pwrpriv->bkeepfwalive = _FALSE; + + RTW_INFO("bkeepfwalive(%x)\n", pwrpriv->bkeepfwalive); + if (pm_netdev_open(pnetdev, _TRUE) != 0) { + ret = -1; + pdbgpriv->dbg_resume_error_cnt++; + goto exit; + } + + rtw_mi_netif_carrier_on(padapter); + + if (padapter->pid[1] != 0) { + RTW_INFO("pid[1]:%d\n", padapter->pid[1]); + rtw_signal_process(padapter->pid[1], SIGUSR2); + } + + rtw_btcoex_SuspendNotify(padapter, BTCOEX_SUSPEND_STATE_RESUME); + + rtw_mi_resume_process_normal(padapter); + + RTW_INFO("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); + +exit: + return ret; +} + +int rtw_resume_common(_adapter *padapter) +{ + int ret = 0; + u32 start_time = rtw_get_current_time(); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (pwrpriv->bInSuspend == _FALSE) + return 0; + + RTW_PRINT("resume start\n"); + RTW_INFO("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid); + + if (rtw_mi_check_status(padapter, WIFI_AP_STATE) == _FALSE) { + rtw_resume_process_normal(padapter); + + } else if (rtw_mi_check_status(padapter, WIFI_AP_STATE)) { + rtw_resume_process_normal(padapter); + } + + if (pwrpriv) { + pwrpriv->bInSuspend = _FALSE; + } + RTW_PRINT("%s:%d in %d ms\n", __FUNCTION__ , ret, + rtw_get_passing_time_ms(start_time)); + + return ret; +} diff --git a/drivers/staging/rtl8821ce/os_dep/linux/pci_intf.c b/drivers/staging/rtl8821ce/os_dep/linux/pci_intf.c new file mode 100644 index 000000000000..7b7aaa12eafa --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/pci_intf.c @@ -0,0 +1,1574 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HCI_INTF_C_ + +#include <drv_types.h> +#include <hal_data.h> + +#include <linux/pci_regs.h> + + extern int rtw_ht_enable; + extern int rtw_bw_mode; + extern int rtw_ampdu_enable;/* for enable tx_ampdu */ + +int ui_pid[3] = {0, 0, 0}; + +extern int pm_netdev_open(struct net_device *pnetdev, u8 bnormal); +int rtw_resume_process(_adapter *padapter); + +#ifdef CONFIG_PM_SLEEP +static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state); +static int rtw_pci_resume(struct pci_dev *pdev); +#endif + +static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid); +static void rtw_dev_remove(struct pci_dev *pdev); + +static struct specific_device_id specific_device_id_tbl[] = { + {.idVendor = 0x0b05, .idProduct = 0x1791, .flags = SPEC_DEV_ID_DISABLE_HT}, + {.idVendor = 0x13D3, .idProduct = 0x3311, .flags = SPEC_DEV_ID_DISABLE_HT}, + {} +}; + +struct pci_device_id rtw_pci_id_tbl[] = { + {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC821), .driver_data = RTL8821C}, + {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC82A), .driver_data = RTL8821C}, + {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0xC82B), .driver_data = RTL8821C}, + + {}, +}; + +struct pci_drv_priv { + struct pci_driver rtw_pci_drv; + int drv_registered; +}; + +static struct pci_drv_priv pci_drvpriv = { + .rtw_pci_drv.name = (char *)DRV_NAME, + .rtw_pci_drv.probe = rtw_drv_init, + .rtw_pci_drv.remove = rtw_dev_remove, + .rtw_pci_drv.shutdown = rtw_dev_remove, + .rtw_pci_drv.id_table = rtw_pci_id_tbl, +#ifdef CONFIG_PM_SLEEP + .rtw_pci_drv.suspend = rtw_pci_suspend, + .rtw_pci_drv.resume = rtw_pci_resume, +#endif +}; + +MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl); + +static u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { + INTEL_VENDOR_ID, + ATI_VENDOR_ID, + AMD_VENDOR_ID, + SIS_VENDOR_ID +}; + +#define PCI_PM_CAP_ID 0x01 /* The Capability ID for PME function */ +void PlatformClearPciPMEStatus(PADAPTER Adapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + BOOLEAN PCIClkReq = _FALSE; + u8 CapId = 0xff; + u8 CapPointer = 0; + /* u16 CapHdr; */ + RT_PCI_CAPABILITIES_HEADER CapHdr; + u8 PMCSReg; + int result; + + /* Get the Capability pointer first, */ + /* the Capability Pointer is located at offset 0x34 from the Function Header */ + + result = pci_read_config_byte(pdev, 0x34, &CapPointer); + if (result != 0) + RTW_INFO("%s() pci_read_config_byte 0x34 Failed!\n", __func__); + else { + RTW_INFO("PlatformClearPciPMEStatus(): PCI configration 0x34 = 0x%2x\n", CapPointer); + do { + /* end of pci capability */ + if (CapPointer == 0x00) { + CapId = 0xff; + break; + } + + /* result = pci_read_config_word(pdev, CapPointer, &CapHdr); */ + result = pci_read_config_byte(pdev, CapPointer, &CapHdr.CapabilityID); + if (result != 0) { + RTW_INFO("%s() pci_read_config_byte %x Failed!\n", __func__, CapPointer); + CapId = 0xff; + break; + } + + result = pci_read_config_byte(pdev, CapPointer + 1, &CapHdr.Next); + if (result != 0) { + RTW_INFO("%s() pci_read_config_byte %x Failed!\n", __func__, CapPointer); + CapId = 0xff; + break; + } + + /* CapId = CapHdr & 0xFF; */ + CapId = CapHdr.CapabilityID; + + RTW_INFO("PlatformClearPciPMEStatus(): in pci configration1, CapPointer%x = %x\n", CapPointer, CapId); + + if (CapId == PCI_PM_CAP_ID) + break; + else { + /* point to next Capability */ + /* CapPointer = (CapHdr >> 8) & 0xFF; */ + CapPointer = CapHdr.Next; + } + } while (_TRUE); + + if (CapId == PCI_PM_CAP_ID) { + /* Get the PM CSR (Control/Status Register), */ + /* The PME_Status is located at PM Capatibility offset 5, bit 7 */ + result = pci_read_config_byte(pdev, CapPointer + 5, &PMCSReg); + if (PMCSReg & BIT7) { + /* PME event occured, clear the PM_Status by write 1 */ + PMCSReg = PMCSReg | BIT7; + + pci_write_config_byte(pdev, CapPointer + 5, PMCSReg); + PCIClkReq = _TRUE; + /* Read it back to check */ + pci_read_config_byte(pdev, CapPointer + 5, &PMCSReg); + RTW_INFO("PlatformClearPciPMEStatus(): Clear PME status 0x%2x to 0x%2x\n", CapPointer + 5, PMCSReg); + } else + RTW_INFO("PlatformClearPciPMEStatus(): PME status(0x%2x) = 0x%2x\n", CapPointer + 5, PMCSReg); + } else + RTW_INFO("PlatformClearPciPMEStatus(): Cannot find PME Capability\n"); + } + + RTW_INFO("PME, value_offset = %x, PME EN = %x\n", CapPointer + 5, PCIClkReq); +} + +void rtw_pci_aspm_config_clkreql0sl1(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 tmp8 = 0; + u16 tmp16 = 0; + + /* 0x70f Bit7 for L0s */ + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); + + if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L0s) + tmp8 |= BIT7; + else + tmp8 &= (~BIT7); + + rtw_hal_pci_dbi_write(padapter, 0x70f, tmp8); + + /* 0x719 Bit 3 for L1 , Bit4 for clock req */ + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + + if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1) + tmp8 |= BIT3; + else + tmp8 &= (~BIT3); + + if (pHalData->pci_backdoor_ctrl & PCI_BC_CLK_REQ) + tmp8 |= BIT4; + else + tmp8 &= (~BIT4); + + rtw_hal_pci_dbi_write(padapter, 0x719, tmp8); + + if (pHalData->pci_backdoor_ctrl & PCI_BC_CLK_REQ) { + tmp16 = rtw_hal_pci_mdio_read(padapter, 0x10); + rtw_hal_pci_mdio_write(padapter, 0x10, (tmp16 | BIT2)); + } +} + +void rtw_pci_aspm_config_l1off(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + u8 enable_l1off = _FALSE; + + if (pHalData->pci_backdoor_ctrl & PCI_BC_ASPM_L1Off) + enable_l1off = rtw_hal_pci_l1off_nic_support(padapter); + + padapter->hal_func.hal_set_l1ssbackdoor_handler(padapter, enable_l1off); + +} + +void rtw_pci_aspm_config_l1off_general(_adapter *padapter, u8 enablel1off) +{ + + u8 tmp8; + u16 tmp16; + + if (enablel1off) { + /* 0x718 Bit5 for L1SS */ + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); + rtw_hal_pci_dbi_write(padapter, 0x718, (tmp8 | BIT5)); + + tmp16 = rtw_hal_pci_mdio_read(padapter, 0x1b); + rtw_hal_pci_mdio_write(padapter, 0x1b, (tmp16 | BIT4)); + } else { + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); + rtw_hal_pci_dbi_write(padapter, 0x718, (tmp8 & (~BIT5))); + } + +} + +void rtw_pci_dump_aspm_info(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + u8 tmp8 = 0; + u16 tmp16 = 0; + u32 tmp32 = 0; + + RTW_INFO("***** ASPM Capability *****\n"); + + pci_read_config_dword(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCAP, &tmp32); + + RTW_INFO("CLK REQ: %s\n", (tmp32&PCI_EXP_LNKCAP_CLKPM) ? "Enable" : "Disable"); + + RTW_INFO("ASPM L0s: %s\n", (tmp32&BIT10) ? "Enable" : "Disable"); + RTW_INFO("ASPM L1: %s\n", (tmp32&BIT11) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_l1off_capability(padapter); + RTW_INFO("ASPM L1OFF:%s\n", tmp8 ? "Enable" : "Disable"); + + RTW_INFO("***** ASPM CTRL Reg *****\n"); + + pci_read_config_word(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + PCI_EXP_LNKCTL, &tmp16); + + RTW_INFO("CLK REQ: %s\n", (tmp16&PCI_EXP_LNKCTL_CLKREQ_EN) ? "Enable" : "Disable"); + RTW_INFO("ASPM L0s: %s\n", (tmp16&BIT0) ? "Enable" : "Disable"); + RTW_INFO("ASPM L1: %s\n", (tmp16&BIT1) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_l1off_nic_support(padapter); + RTW_INFO("ASPM L1OFF:%s\n", tmp8 ? "Enable" : "Disable"); + + RTW_INFO("***** ASPM Backdoor *****\n"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_INFO("CLK REQ: %s\n", (tmp8 & BIT4) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x70f); + RTW_INFO("ASPM L0s: %s\n", (tmp8&BIT7) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x719); + RTW_INFO("ASPM L1: %s\n", (tmp8 & BIT3) ? "Enable" : "Disable"); + + tmp8 = rtw_hal_pci_dbi_read(padapter, 0x718); + RTW_INFO("ASPM L1OFF:%s\n", (tmp8 & BIT5) ? "Enable" : "Disable"); + RTW_INFO("*************************\n"); +} + +void rtw_pci_aspm_config(_adapter *padapter) +{ + rtw_pci_aspm_config_clkreql0sl1(padapter); + rtw_pci_aspm_config_l1off(padapter); + rtw_pci_dump_aspm_info(padapter); +} + +static u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + BOOLEAN bResult = _FALSE; + int Result = 0; + int error; + + Result = pci_write_config_byte(pdvobjpriv->ppcidev, pcipriv->pciehdr_offset + 0x10, value); /* enable I/O space */ + RTW_INFO("PlatformSwitchDevicePciASPM(0x%x) = 0x%x\n", pcipriv->pciehdr_offset + 0x10, value); + if (Result != 0) { + RTW_INFO("PlatformSwitchDevicePciASPM() Failed!\n"); + bResult = _FALSE; + } else + bResult = _TRUE; + + return bResult; +} + +/* + * When we set 0x01 to enable clk request. Set 0x0 to disable clk req. + */ +static u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + u8 buffer, bResult = _FALSE; + int error; + + buffer = value; + + if (!rtw_is_hw_init_completed(padapter)) + return bResult; + + /* the clock request is located at offset 0x81, suppose the PCIE Capability register is located at offset 0x70 */ + /* the correct code should be: search the PCIE capability register first and then the clock request is located offset 0x11 */ + error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, buffer); + if (error != 0) + RTW_INFO("rtw_pci_switch_clk_req error (%d)\n", error); + else + bResult = _TRUE; + + return bResult; +} + +/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ +void rtw_pci_disable_aspm(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + u8 linkctrl_reg; + u8 pcibridge_linkctrlreg, aspmlevel = 0; + + /* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */ + if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM))) + return; + + if (!rtw_is_hw_init_completed(padapter)) + return; + + if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) + return; + + linkctrl_reg = pcipriv->linkctrl_reg; + pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg; + + /* Set corresponding value. */ + aspmlevel |= BIT(0) | BIT(1); + linkctrl_reg &= ~aspmlevel; + pcibridge_linkctrlreg &= ~aspmlevel; + + /* */ + /* 09/08/21 MH From Sd1 suggestion. we need to adjust ASPM enable sequence */ + /* CLK_REQ ==> delay 50us ==> Device ==> Host ==> delay 50us */ + /* */ + + if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { + RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); + rtw_pci_switch_clk_req(padapter, 0x0); + } + + { + /*for promising device will in L0 state after an I/O.*/ + u8 tmp_u1b; + + pci_read_config_byte(pdev, (pcipriv->pciehdr_offset + 0x10), &tmp_u1b); + } + + rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg); + + rtw_udelay_os(50); + + /* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */ + /* we do not execute any action and return. Added by tynli. */ + if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) || + (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) { + /* Do Nothing!! */ + } else { + /* 4 */ /* Disable Pci Bridge ASPM */ + pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg); + RTW_INFO("PlatformDisableASPM():PciBridge Write reg[%x] = %x\n", + (pcipriv->pcibridge_pciehdr_offset + 0x10), pcibridge_linkctrlreg); + rtw_udelay_os(50); + } + +} + +/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for + * power saving We should follow the sequence to enable + * RTL8192SE first then enable Pci Bridge ASPM + * or the system will show bluescreen. +*/ +void rtw_pci_enable_aspm(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); + struct pci_dev *pdev = pdvobjpriv->ppcidev; + struct pci_dev *bridge_pdev = pdev->bus->self; + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + u16 aspmlevel = 0; + u8 u_pcibridge_aspmsetting = 0; + u8 u_device_aspmsetting = 0; + u32 u_device_aspmsupportsetting = 0; + + /* We shall check RF Off Level for ASPM function instead of registry settings, revised by Roger, 2013.03.29. */ + if (!(pwrpriv->reg_rfps_level & (RT_RF_LPS_LEVEL_ASPM | RT_RF_PS_LEVEL_ALWAYS_ASPM))) + return; + + /* When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, */ + /* we do not execute any action and return. Added by tynli. */ + if ((pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) || + (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff)) { + RTW_INFO("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n"); + return; + } + + /* Get Bridge ASPM Support + * not to enable bridge aspm if bridge does not support + * Added by sherry 20100803 + */ + { + /* Get the Link Capability, it ls located at offset 0x0c from the PCIE Capability */ + pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x0C), &u_device_aspmsupportsetting); + + RTW_INFO("rtw_pci_enable_aspm(): Bridge ASPM support %x\n", u_device_aspmsupportsetting); + if (((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) { + if (pdvobjpriv->const_devicepci_aspm_setting == 3) { + RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n"); + return; + } else if (pdvobjpriv->const_devicepci_aspm_setting == 2) { + if ((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) { + RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L1\n"); + return; + } + } else if (pdvobjpriv->const_devicepci_aspm_setting == 1) { + if ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) { + RTW_INFO("rtw_pci_enable_aspm(): Bridge not support L0s\n"); + return; + } + + } + } else + RTW_INFO("rtw_pci_enable_aspm(): Bridge support L0s and L1\n"); + } + + /* + * Skip following settings if ASPM has already enabled, added by Roger, 2013.03.15. + */ + if ((pcipriv->pcibridge_linkctrlreg & (BIT0 | BIT1)) && + (pcipriv->linkctrl_reg & (BIT0 | BIT1))) { + /* BIT0: L0S, BIT1:L1 */ + + RTW_INFO("PlatformEnableASPM(): ASPM is already enabled, skip incoming settings!!\n"); + return; + } + + /* 4 Enable Pci Bridge ASPM */ + /* Write PCI bridge PCIE-capability Link Control Register */ + /* Justin: Can we change the ASPM Control register ? */ + /* The system BIOS should set this register with a correct value */ + /* If we change the force enable the ASPM L1/L0s, this may cause the system hang */ + u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg; + u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting; + + if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL || + pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS) + u_pcibridge_aspmsetting &= ~BIT(0); /* for intel host 42 device 43 */ + + pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset + 0x10), u_pcibridge_aspmsetting); + RTW_INFO("PlatformEnableASPM():PciBridge Write reg[%x] = %x\n", + (pcipriv->pcibridge_pciehdr_offset + 0x10), + u_pcibridge_aspmsetting); + + rtw_udelay_os(50); + + /*Get ASPM level (with/without Clock Req)*/ + aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting; + u_device_aspmsetting = pcipriv->linkctrl_reg; + u_device_aspmsetting |= aspmlevel; /* device 43 */ + + rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting); + + if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { + rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); + RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); + } + + rtw_udelay_os(50); +} + +static u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *pdvobjpriv, struct pci_dev *pdev) +{ + u8 status = _FALSE; + u8 offset_e0; + u32 offset_e4; + + pci_write_config_byte(pdev, 0xE0, 0xA0); + pci_read_config_byte(pdev, 0xE0, &offset_e0); + + if (offset_e0 == 0xA0) { + pci_read_config_dword(pdev, 0xE4, &offset_e4); + if (offset_e4 & BIT(23)) + status = _TRUE; + } + + return status; +} + +static s32 rtw_pci_get_linkcontrol_reg(struct pci_dev *pdev, u8 *LinkCtrlReg, u8 *HdrOffset) +{ + u8 CapabilityPointer; + RT_PCI_CAPABILITIES_HEADER CapabilityHdr; + s32 status = _FAIL; + + /* get CapabilityOffset */ + pci_read_config_byte(pdev, 0x34, &CapabilityPointer); /* the capability pointer is located offset 0x34 */ + + /* Loop through the capabilities in search of the power management capability. */ + /* The list is NULL-terminated, so the last offset will always be zero. */ + + while (CapabilityPointer != 0) { + /* Read the header of the capability at this offset. If the retrieved capability is not */ + /* the power management capability that we are looking for, follow the link to the */ + /* next capability and continue looping. */ + + /* 4 get CapabilityHdr */ + /* pci_read_config_word(pdev, CapabilityPointer, (u16 *)&CapabilityHdr); */ + pci_read_config_byte(pdev, CapabilityPointer, (u8 *)&CapabilityHdr.CapabilityID); + pci_read_config_byte(pdev, CapabilityPointer + 1, (u8 *)&CapabilityHdr.Next); + + /* Found the PCI express capability */ + if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) + break; + else { + /* This is some other capability. Keep looking for the PCI express capability. */ + CapabilityPointer = CapabilityHdr.Next; + } + } + + /* Get the Link Control Register, it located at offset 0x10 from the Capability Header */ + if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) { + *HdrOffset = CapabilityPointer; + pci_read_config_byte(pdev, CapabilityPointer + 0x10, LinkCtrlReg); + + status = _SUCCESS; + } else { + /* We didn't find a PCIe capability. */ + RTW_INFO("GetPciLinkCtrlReg(): Cannot Find PCIe Capability\n"); + } + + return status; +} + +static s32 rtw_set_pci_cache_line_size(struct pci_dev *pdev, u8 CacheLineSizeToSet) +{ + u8 ucPciCacheLineSize; + s32 Result; + + /* ucPciCacheLineSize = pPciConfig->CacheLineSize; */ + pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize); + + if (ucPciCacheLineSize < 8 || ucPciCacheLineSize > 16) { + RTW_INFO("Driver Sets default Cache Line Size...\n"); + + ucPciCacheLineSize = CacheLineSizeToSet; + + Result = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, ucPciCacheLineSize); + + if (Result != 0) { + RTW_INFO("pci_write_config_byte (CacheLineSize) Result=%d\n", Result); + goto _SET_CACHELINE_SIZE_FAIL; + } + + Result = pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &ucPciCacheLineSize); + if (Result != 0) { + RTW_INFO("pci_read_config_byte (PciCacheLineSize) Result=%d\n", Result); + goto _SET_CACHELINE_SIZE_FAIL; + } + + if (ucPciCacheLineSize != CacheLineSizeToSet) { + RTW_INFO("Failed to set Cache Line Size to 0x%x! ucPciCacheLineSize=%x\n", CacheLineSizeToSet, ucPciCacheLineSize); + goto _SET_CACHELINE_SIZE_FAIL; + } + } + + return _SUCCESS; + +_SET_CACHELINE_SIZE_FAIL: + + return _FAIL; +} + +#define PCI_CMD_ENABLE_BUS_MASTER BIT(2) +#define PCI_CMD_DISABLE_INTERRUPT BIT(10) +#define CMD_BUS_MASTER BIT(2) + +static s32 rtw_pci_parse_configuration(struct pci_dev *pdev, struct dvobj_priv *pdvobjpriv) +{ + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + /* PPCI_COMMON_CONFIG pPciConfig = (PPCI_COMMON_CONFIG) pucBuffer; */ + /* u16 usPciCommand = pPciConfig->Command; */ + u16 usPciCommand = 0; + int Result, ret; + u8 CapabilityOffset; + RT_PCI_CAPABILITIES_HEADER CapabilityHdr; + u8 PCIeCap; + u8 LinkCtrlReg; + u8 ClkReqReg; + + /* RTW_INFO("%s==>\n", __func__); */ + + pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand); + + do { + /* 3 Enable bus matering if it isn't enabled by the BIOS */ + if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) { + RTW_INFO("Bus master is not enabled by BIOS! usPciCommand=%x\n", usPciCommand); + + usPciCommand |= CMD_BUS_MASTER; + + Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand); + if (Result != 0) { + RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result); + ret = _FAIL; + break; + } + + Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand); + if (Result != 0) { + RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result); + ret = _FAIL; + break; + } + + if (!(usPciCommand & PCI_CMD_ENABLE_BUS_MASTER)) { + RTW_INFO("Failed to enable bus master! usPciCommand=%x\n", usPciCommand); + ret = _FAIL; + break; + } + } + RTW_INFO("Bus master is enabled. usPciCommand=%x\n", usPciCommand); + + /* 3 Enable interrupt */ + if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) { + RTW_INFO("INTDIS==1 usPciCommand=%x\n", usPciCommand); + + usPciCommand &= (~PCI_CMD_DISABLE_INTERRUPT); + + Result = pci_write_config_word(pdev, PCI_COMMAND, usPciCommand); + if (Result != 0) { + RTW_INFO("pci_write_config_word (Command) Result=%d\n", Result); + ret = _FAIL; + break; + } + + Result = pci_read_config_word(pdev, PCI_COMMAND, &usPciCommand); + if (Result != 0) { + RTW_INFO("pci_read_config_word (Command) Result=%d\n", Result); + ret = _FAIL; + break; + } + + if ((usPciCommand & PCI_CMD_DISABLE_INTERRUPT)) { + RTW_INFO("Failed to set INTDIS to 0! usPciCommand=%x\n", usPciCommand); + ret = _FAIL; + break; + } + } + + /* */ + /* Description: Find PCI express capability offset. Porting from 818xB by tynli 2008.12.19 */ + /* */ + /* ------------------------------------------------------------- */ + + /* 3 PCIeCap */ + /* The device supports capability lists. Find the capabilities. */ + + /* CapabilityOffset = pPciConfig->u.type0.CapabilitiesPtr; */ + pci_read_config_byte(pdev, PCI_CAPABILITY_LIST, &CapabilityOffset); + + /* Loop through the capabilities in search of the power management capability. */ + /* The list is NULL-terminated, so the last offset will always be zero. */ + + while (CapabilityOffset != 0) { + /* Read the header of the capability at this offset. If the retrieved capability is not */ + /* the power management capability that we are looking for, follow the link to the */ + /* next capability and continue looping. */ + + /* Result = pci_read_config_word(pdev, CapabilityOffset, (u16 *)&CapabilityHdr); */ + Result = pci_read_config_byte(pdev, CapabilityOffset, (u8 *)&CapabilityHdr.CapabilityID); + if (Result != 0) + break; + + Result = pci_read_config_byte(pdev, CapabilityOffset + 1, (u8 *)&CapabilityHdr.Next); + if (Result != 0) + break; + + /* Found the PCI express capability */ + if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) + break; + else { + /* This is some other capability. Keep looking for the PCI express capability. */ + CapabilityOffset = CapabilityHdr.Next; + } + } + + if (Result != 0) { + RTW_INFO("pci_read_config_word (RT_PCI_CAPABILITIES_HEADER) Result=%d\n", Result); + break; + } + + if (CapabilityHdr.CapabilityID == PCI_CAPABILITY_ID_PCI_EXPRESS) { + pcipriv->pciehdr_offset = CapabilityOffset; + RTW_INFO("PCIe Header Offset =%x\n", CapabilityOffset); + + /* Skip past the capabilities header and read the PCI express capability */ + /* Justin: The PCI-e capability size should be 2 bytes, why we just get 1 byte */ + /* Beside, this PCIeCap seems no one reference it in the driver code */ + Result = pci_read_config_byte(pdev, CapabilityOffset + 2, &PCIeCap); + + if (Result != 0) { + RTW_INFO("pci_read_config_byte (PCIE Capability) Result=%d\n", Result); + break; + } + + pcipriv->pcie_cap = PCIeCap; + RTW_INFO("PCIe Capability =%x\n", PCIeCap); + + /* 3 Link Control Register */ + /* Read "Link Control Register" Field (80h ~81h) */ + Result = pci_read_config_byte(pdev, CapabilityOffset + 0x10, &LinkCtrlReg); + if (Result != 0) { + RTW_INFO("pci_read_config_byte (Link Control Register) Result=%d\n", Result); + break; + } + + pcipriv->linkctrl_reg = LinkCtrlReg; + RTW_INFO("Link Control Register =%x\n", LinkCtrlReg); + + /* 3 Get Capability of PCI Clock Request */ + /* The clock request setting is located at 0x81[0] */ + Result = pci_read_config_byte(pdev, CapabilityOffset + 0x11, &ClkReqReg); + if (Result != 0) { + pcipriv->pci_clk_req = _FALSE; + RTW_INFO("pci_read_config_byte (Clock Request Register) Result=%d\n", Result); + break; + } + if (ClkReqReg & BIT(0)) + pcipriv->pci_clk_req = _TRUE; + else + pcipriv->pci_clk_req = _FALSE; + RTW_INFO("Clock Request =%x\n", pcipriv->pci_clk_req); + } else { + /* We didn't find a PCIe capability. */ + RTW_INFO("Didn't Find PCIe Capability\n"); + break; + } + + /* 3 Fill Cacheline */ + ret = rtw_set_pci_cache_line_size(pdev, 8); + if (ret != _SUCCESS) { + RTW_INFO("rtw_set_pci_cache_line_size fail\n"); + break; + } + + /* Include 92C suggested by SD1. Added by tynli. 2009.11.25. + * Enable the Backdoor + */ + { + u8 tmp; + + Result = pci_read_config_byte(pdev, 0x98, &tmp); + + tmp |= BIT4; + + Result = pci_write_config_byte(pdev, 0x98, tmp); + + } + ret = _SUCCESS; + } while (_FALSE); + + return ret; +} + +/* + * Update PCI dependent default settings. + * + */ +static void rtw_pci_update_default_setting(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(pdvobjpriv); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + /* reset pPSC->reg_rfps_level & priv->b_support_aspm */ + pwrpriv->reg_rfps_level = 0; + + /* Update PCI ASPM setting */ + /* pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; */ + switch (pdvobjpriv->const_pci_aspm) { + case 0: /* No ASPM */ + break; + + case 1: /* ASPM dynamically enabled/disable. */ + pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; + break; + + case 2: /* ASPM with Clock Req dynamically enabled/disable. */ + pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ); + break; + + case 3: /* Always enable ASPM and Clock Req from initialization to halt. */ + pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); + pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ); + break; + + case 4: /* Always enable ASPM without Clock Req from initialization to halt. */ + pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ); + pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; + break; + + case 5: /* Linux do not support ASPM OSC, added by Roger, 2013.03.27. */ + break; + } + + pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; + + /* Update Radio OFF setting */ + switch (pdvobjpriv->const_hwsw_rfoff_d3) { + case 1: + if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) + pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; + break; + + case 2: + if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) + pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; + pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; + break; + + case 3: + pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; + break; + } + + /* Update Rx 2R setting */ + /* pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); */ + + /* */ + /* Set HW definition to determine if it supports ASPM. */ + /* */ + switch (pdvobjpriv->const_support_pciaspm) { + case 1: { /* Support ASPM. */ + u8 b_support_backdoor = _TRUE; + u8 b_support_l1_on_amd = _FALSE; + + rtw_hal_get_def_var(padapter, HAL_DEF_PCI_AMD_L1_SUPPORT, &b_support_l1_on_amd); + + if (pHalData->CustomerID == RT_CID_TOSHIBA && + pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD && + !pcipriv->amd_l1_patch && !b_support_l1_on_amd) { + RTW_INFO("%s(): Disable L1 Backdoor!!\n", __func__); + b_support_backdoor = _FALSE; + } + rtw_hal_set_def_var(padapter, HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, &b_support_backdoor); + } + break; + + default: + /* Do nothing. Set when finding the chipset. */ + break; + } +} + +static void rtw_pci_initialize_adapter_common(_adapter *padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + rtw_pci_update_default_setting(padapter); + + if (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { + /* Always enable ASPM & Clock Req. */ + rtw_pci_enable_aspm(padapter); + RT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM); + } + +} + +/* + * 2009/10/28 MH Enable rtl8192ce DMA64 function. We need to enable 0x719 BIT5 + * */ + +#define rtw_pci_interrupt(x, y, z) rtw_pci_interrupt(x, y) + +static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs) +{ + struct dvobj_priv *dvobj = (struct dvobj_priv *)priv; + _adapter *adapter = dvobj_get_primary_adapter(dvobj); + + if (dvobj->irq_enabled == 0) + return IRQ_HANDLED; + + if (rtw_hal_interrupt_handler(adapter) == _FAIL) + return IRQ_HANDLED; + /* return IRQ_NONE; */ + + return IRQ_HANDLED; +} + + +int pci_alloc_irq(struct dvobj_priv *dvobj) +{ + int err; + struct pci_dev *pdev = dvobj->ppcidev; + int ret; + + ret = pci_enable_msi(pdev); + + RTW_INFO("pci_enable_msi ret=%d\n", ret); + +#if defined(IRQF_SHARED) + err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj); +#else + err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj); +#endif + if (err) + RTW_INFO("Error allocating IRQ %d", pdev->irq); + else { + dvobj->irq_alloc = 1; + dvobj->irq = pdev->irq; + RTW_INFO("Request_irq OK, IRQ %d\n", pdev->irq); + } + + return err ? _FAIL : _SUCCESS; +} + +static void rtw_decide_chip_type_by_pci_driver_data(struct dvobj_priv *pdvobj, const struct pci_device_id *pdid) +{ + pdvobj->chip_type = pdid->driver_data; + + if (pdvobj->chip_type == RTL8821C) { + pdvobj->HardwareType = HARDWARE_TYPE_RTL8821CE; + RTW_INFO("CHIP TYPE: RTL8821CE\n"); + } + +} + +static struct dvobj_priv *pci_dvobj_init(struct pci_dev *pdev, const struct pci_device_id *pdid) +{ + int err; + u32 status = _FAIL; + struct dvobj_priv *dvobj = NULL; + struct pci_priv *pcipriv = NULL; + struct pci_dev *bridge_pdev = pdev->bus->self; + /* u32 pci_cfg_space[16]; */ + unsigned long pmem_start, pmem_len, pmem_flags; + u8 tmp; + u8 PciBgVIdIdx; + int i; + + dvobj = devobj_init(); + if (dvobj == NULL) + goto exit; + + dvobj->ppcidev = pdev; + pcipriv = &(dvobj->pcipriv); + pci_set_drvdata(pdev, dvobj); + + err = pci_enable_device(pdev); + if (err != 0) { + RTW_ERR("%s : Cannot enable new PCI device\n", pci_name(pdev)); + goto free_dvobj; + } + + { + if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err != 0) { + RTW_ERR("Unable to obtain 32bit DMA for consistent allocations\n"); + goto disable_picdev; + } + } + } + + pci_set_master(pdev); + + err = pci_request_regions(pdev, DRV_NAME); + if (err != 0) { + RTW_ERR("Can't obtain PCI resources\n"); + goto disable_picdev; + } + + /* Search for memory map resource (index 0~5) */ + for (i = 0 ; i < 6 ; i++) { + pmem_start = pci_resource_start(pdev, i); + pmem_len = pci_resource_len(pdev, i); + pmem_flags = pci_resource_flags(pdev, i); + + if (pmem_flags & IORESOURCE_MEM) + break; + } + + if (i == 6) { + RTW_ERR("%s: No MMIO resource found, abort!\n", __func__); + goto release_regions; + } + + /* shared mem start */ + dvobj->pci_mem_start = (unsigned long)pci_iomap(pdev, i, pmem_len); + if (dvobj->pci_mem_start == 0) { + RTW_ERR("Can't map PCI mem\n"); + goto release_regions; + } + + RTW_INFO("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", + pmem_start, pmem_len, pmem_flags, dvobj->pci_mem_start); + + /*find bus info*/ + pcipriv->busnumber = pdev->bus->number; + pcipriv->devnumber = PCI_SLOT(pdev->devfn); + pcipriv->funcnumber = PCI_FUNC(pdev->devfn); + + /*find bridge info*/ + if (bridge_pdev) { + pcipriv->pcibridge_busnum = bridge_pdev->bus->number; + pcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn); + pcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn); + pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; + pcipriv->pcibridge_vendorid = bridge_pdev->vendor; + pcipriv->pcibridge_deviceid = bridge_pdev->device; + } + + /*step 1-1., decide the chip_type via device info*/ + dvobj->interface_type = RTW_PCIE; + rtw_decide_chip_type_by_pci_driver_data(dvobj, pdid); + + /* rtw_pci_parse_configuration(pdev, dvobj, (u8 *)&pci_cfg_space); */ + rtw_pci_parse_configuration(pdev, dvobj); + + for (PciBgVIdIdx = 0; PciBgVIdIdx < PCI_BRIDGE_VENDOR_MAX; PciBgVIdIdx++) { + if (pcipriv->pcibridge_vendorid == pcibridge_vendors[PciBgVIdIdx]) { + pcipriv->pcibridge_vendor = PciBgVIdIdx; + RTW_INFO("Pci Bridge Vendor is found: VID=0x%x, VendorIdx=%d\n", pcipriv->pcibridge_vendorid, PciBgVIdIdx); + break; + } + } + + if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) { + rtw_pci_get_linkcontrol_reg(bridge_pdev, &pcipriv->pcibridge_linkctrlreg, &pcipriv->pcibridge_pciehdr_offset); + + if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) + pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj, bridge_pdev); + } + + status = _SUCCESS; + + if (status != _SUCCESS && dvobj->pci_mem_start != 0) { + pci_iounmap(pdev, (void *)dvobj->pci_mem_start); + dvobj->pci_mem_start = 0; + } + +release_regions: + if (status != _SUCCESS) + pci_release_regions(pdev); +disable_picdev: + if (status != _SUCCESS) + pci_disable_device(pdev); +free_dvobj: + if (status != _SUCCESS && dvobj) { + pci_set_drvdata(pdev, NULL); + devobj_deinit(dvobj); + dvobj = NULL; + } +exit: + return dvobj; +} + +static void pci_dvobj_deinit(struct pci_dev *pdev) +{ + struct dvobj_priv *dvobj = pci_get_drvdata(pdev); + + pci_set_drvdata(pdev, NULL); + if (dvobj) { + if (dvobj->irq_alloc) { + free_irq(pdev->irq, dvobj); + pci_disable_msi(pdev); + dvobj->irq_alloc = 0; + } + + if (dvobj->pci_mem_start != 0) { + pci_iounmap(pdev, (void *)dvobj->pci_mem_start); + dvobj->pci_mem_start = 0; + } + + devobj_deinit(dvobj); + } + + pci_release_regions(pdev); + pci_disable_device(pdev); + +} + +u8 rtw_set_hal_ops(_adapter *padapter) +{ + /* alloc memory for HAL DATA */ + if (rtw_hal_data_init(padapter) == _FAIL) + return _FAIL; + + if (rtw_get_chip_type(padapter) == RTL8821C) + rtl8821ce_set_hal_ops(padapter); + + if (rtw_hal_ops_check(padapter) == _FAIL) + return _FAIL; + + if (hal_spec_init(padapter) == _FAIL) + return _FAIL; + + return _SUCCESS; +} + +void pci_set_intf_ops(_adapter *padapter, struct _io_ops *pops) +{ + + if (rtw_get_chip_type(padapter) == RTL8821C) + rtl8821ce_set_intf_ops(pops); + +} + +static void pci_intf_start(_adapter *padapter) +{ + + RTW_INFO("+pci_intf_start\n"); + + /* Enable hw interrupt */ + rtw_hal_enable_interrupt(padapter); + + RTW_INFO("-pci_intf_start\n"); +} +static void rtw_mi_pci_tasklets_kill(_adapter *padapter) +{ + int i; + _adapter *iface; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if ((iface) && rtw_is_adapter_up(iface)) { + tasklet_kill(&(padapter->recvpriv.recv_tasklet)); + tasklet_kill(&(padapter->recvpriv.irq_prepare_beacon_tasklet)); + tasklet_kill(&(padapter->xmitpriv.xmit_tasklet)); + } + } +} + +static void pci_intf_stop(_adapter *padapter) +{ + + /* Disable hw interrupt */ + if (!rtw_is_surprise_removed(padapter)) { + /* device still exists, so driver can do i/o operation */ + rtw_hal_disable_interrupt(padapter); + rtw_mi_pci_tasklets_kill(padapter); + + rtw_hal_set_hwreg(padapter, HW_VAR_PCIE_STOP_TX_DMA, 0); + + rtw_hal_irp_reset(padapter); + + } else { + /* Clear irq_enabled to prevent handle interrupt function. */ + adapter_to_dvobj(padapter)->irq_enabled = 0; + } + +} + +static void disable_ht_for_spec_devid(const struct pci_device_id *pdid) +{ + u16 vid, pid; + u32 flags; + int i; + int num = sizeof(specific_device_id_tbl) / sizeof(struct specific_device_id); + + for (i = 0; i < num; i++) { + vid = specific_device_id_tbl[i].idVendor; + pid = specific_device_id_tbl[i].idProduct; + flags = specific_device_id_tbl[i].flags; + + if ((pdid->vendor == vid) && (pdid->device == pid) && (flags & SPEC_DEV_ID_DISABLE_HT)) { + rtw_ht_enable = 0; + rtw_bw_mode = 0; + rtw_ampdu_enable = 0; + } + + } +} + +#ifdef CONFIG_PM_SLEEP +static int rtw_pci_suspend(struct pci_dev *pdev, pm_message_t state) +{ + int ret = 0; + struct dvobj_priv *dvobj = pci_get_drvdata(pdev); + _adapter *padapter = dvobj_get_primary_adapter(dvobj); + + ret = rtw_suspend_common(padapter); + ret = pci_save_state(pdev); + if (ret != 0) { + RTW_INFO("%s Failed on pci_save_state (%d)\n", __func__, ret); + goto exit; + } + + pci_disable_device(pdev); + + ret = pci_set_power_state(pdev, pci_choose_state(pdev, state)); + if (ret != 0) + RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __func__, ret); + +exit: + return ret; + +} + +int rtw_resume_process(_adapter *padapter) +{ + return rtw_resume_common(padapter); +} + +static int rtw_pci_resume(struct pci_dev *pdev) +{ + struct dvobj_priv *dvobj = pci_get_drvdata(pdev); + _adapter *padapter = dvobj_get_primary_adapter(dvobj); + struct net_device *pnetdev = padapter->pnetdev; + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + int err = 0; + + err = pci_set_power_state(pdev, PCI_D0); + if (err != 0) { + RTW_INFO("%s Failed on pci_set_power_state (%d)\n", __func__, err); + goto exit; + } + + err = pci_enable_device(pdev); + if (err != 0) { + RTW_INFO("%s Failed on pci_enable_device (%d)\n", __func__, err); + goto exit; + } + + pci_restore_state(pdev); + + if (pwrpriv->bInternalAutoSuspend) + err = rtw_resume_process(padapter); + else { + if (pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) { + rtw_resume_lock_suspend(); + err = rtw_resume_process(padapter); + rtw_resume_unlock_suspend(); + } else { + if (rtw_is_earlysuspend_registered(pwrpriv)) { + /* jeff: bypass resume here, do in late_resume */ + rtw_set_do_late_resume(pwrpriv, _TRUE); + } else { + rtw_resume_lock_suspend(); + err = rtw_resume_process(padapter); + rtw_resume_unlock_suspend(); + } + } + } + +exit: + + return err; +} +#endif /* CONFIG_PM_SLEEP */ + +_adapter *rtw_pci_primary_adapter_init(struct dvobj_priv *dvobj, struct pci_dev *pdev) +{ + _adapter *padapter = NULL; + int status = _FAIL; + + padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter)); + if (padapter == NULL) + goto exit; + + if (loadparam(padapter) != _SUCCESS) + goto free_adapter; + + padapter->dvobj = dvobj; + + rtw_set_drv_stopped(padapter);/*init*/ + + dvobj->padapters[dvobj->iface_nums++] = padapter; + padapter->iface_id = IFACE_ID0; + + /* set adapter_type/iface type for primary padapter */ + padapter->isprimary = _TRUE; + padapter->adapter_type = PRIMARY_ADAPTER; + padapter->hw_port = HW_PORT0; + + if (rtw_init_io_priv(padapter, pci_set_intf_ops) == _FAIL) + goto free_adapter; + + /* step 2. hook HalFunc, allocate HalData */ + /* hal_set_hal_ops(padapter); */ + if (rtw_set_hal_ops(padapter) == _FAIL) + goto free_hal_data; + + /* step 3. */ + padapter->intf_start = &pci_intf_start; + padapter->intf_stop = &pci_intf_stop; + + /* .3 */ + rtw_hal_read_chip_version(padapter); + + /* .4 */ + rtw_hal_chip_configure(padapter); + + /* step 4. read efuse/eeprom data and get mac_addr */ + if (rtw_hal_read_chip_info(padapter) == _FAIL) + goto free_hal_data; + + /* step 5. */ + if (rtw_init_drv_sw(padapter) == _FAIL) + goto free_hal_data; + + if (GET_HAL_DATA(padapter)->EEPROMBluetoothCoexist) + rtw_btcoex_Initialize(padapter); + else + rtw_btcoex_wifionly_initialize(padapter); + + if (rtw_hal_inirp_init(padapter) == _FAIL) + goto free_hal_data; + + rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); + + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); + + rtw_hal_disable_interrupt(padapter); + + /* step 6. Init pci related configuration */ + rtw_pci_initialize_adapter_common(padapter); + + RTW_INFO("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%s\n" + , rtw_is_drv_stopped(padapter) ? "True" : "False" + , rtw_is_surprise_removed(padapter) ? "True" : "False" + , padapter->bup + , rtw_is_hw_init_completed(padapter) ? "True" : "False" + ); + + status = _SUCCESS; + +free_hal_data: + if (status != _SUCCESS && padapter->HalData) + rtw_hal_free_data(padapter); + +free_adapter: + if (status != _SUCCESS && padapter) { + rtw_vmfree((u8 *)padapter, sizeof(*padapter)); + padapter = NULL; + } +exit: + return padapter; +} + +static void rtw_pci_primary_adapter_deinit(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + /* padapter->intf_stop(padapter); */ + + if (check_fwstate(pmlmepriv, _FW_LINKED)) + rtw_disassoc_cmd(padapter, 0, RTW_CMDF_DIRECTLY); + + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + free_mlme_ap_info(padapter); + } + + /*rtw_cancel_all_timer(padapte);*/ + rtw_dev_unload(padapter); + + RTW_INFO("%s, hw_init_completed=%s\n", __func__, rtw_is_hw_init_completed(padapter) ? "_TRUE" : "_FALSE"); + + rtw_hal_inirp_deinit(padapter); + rtw_free_drv_sw(padapter); + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ + rtw_os_ndev_free(padapter); + + rtw_halmac_deinit_adapter(adapter_to_dvobj(padapter)); + + rtw_vmfree((u8 *)padapter, sizeof(_adapter)); + +#ifdef CONFIG_PLATFORM_RTD2880B + RTW_INFO("wlan link down\n"); + rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); +#endif +} + +/* + * drv_init() - a device potentially for us + * + * notes: drv_init() is called when the bus driver has located a card for us to support. + * We accept the new device by returning 0. +*/ +static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid) +{ + int i, err = -ENODEV; + + int status = _FAIL; + _adapter *padapter = NULL; + struct dvobj_priv *dvobj; + struct net_device *pnetdev; + + /* RTW_INFO("+rtw_drv_init\n"); */ + + /* step 0. */ + disable_ht_for_spec_devid(pdid); + + /* Initialize dvobj_priv */ + dvobj = pci_dvobj_init(pdev, pdid); + if (dvobj == NULL) + goto exit; + + /* Initialize primary adapter */ + padapter = rtw_pci_primary_adapter_init(dvobj, pdev); + if (padapter == NULL) { + RTW_INFO("rtw_pci_primary_adapter_init Failed!\n"); + goto free_dvobj; + } + + /* Initialize virtual interface */ + + if (ui_pid[1] != 0) { + RTW_INFO("ui_pid[1]:%d\n", ui_pid[1]); + rtw_signal_process(ui_pid[1], SIGUSR2); + } + + /* dev_alloc_name && register_netdev */ + if (rtw_os_ndevs_init(dvobj) != _SUCCESS) + goto free_if_vir; + + +#ifdef CONFIG_PLATFORM_RTD2880B + RTW_INFO("wlan link up\n"); + rtd2885_wlan_netlink_sendMsg("linkup", "8712"); +#endif + + /* alloc irq */ + if (pci_alloc_irq(dvobj) != _SUCCESS) + goto os_ndevs_deinit; + + /* RTW_INFO("-871x_drv - drv_init, success!\n"); */ + + status = _SUCCESS; + +os_ndevs_deinit: + if (status != _SUCCESS) + rtw_os_ndevs_deinit(dvobj); +free_if_vir: + if (status != _SUCCESS) { + } + + if (status != _SUCCESS && padapter) + rtw_pci_primary_adapter_deinit(padapter); + +free_dvobj: + if (status != _SUCCESS) + pci_dvobj_deinit(pdev); +exit: + return status == _SUCCESS ? 0 : -ENODEV; +} + +/* + * dev_remove() - our device is being removed +*/ +/* rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both */ +static void rtw_dev_remove(struct pci_dev *pdev) +{ + struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev); + _adapter *padapter = dvobj_get_primary_adapter(pdvobjpriv); + struct net_device *pnetdev = padapter->pnetdev; + + if (pdvobjpriv->processing_dev_remove == _TRUE) { + RTW_WARN("%s-line%d: Warning! device has been removed!\n", __func__, __LINE__); + return; + } + + RTW_INFO("+rtw_dev_remove\n"); + + pdvobjpriv->processing_dev_remove = _TRUE; + + if (unlikely(!padapter)) + return; + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ + rtw_os_ndevs_unregister(pdvobjpriv); + + + if (padapter->bFWReady == _TRUE) { + rtw_pm_set_ips(padapter, IPS_NONE); + rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + + LeaveAllPowerSaveMode(padapter); + } + + rtw_set_drv_stopped(padapter); /*for stop thread*/ + rtw_stop_cmd_thread(padapter); + + rtw_btcoex_HaltNotify(padapter); + + rtw_pci_primary_adapter_deinit(padapter); + + + pci_dvobj_deinit(pdev); + + RTW_INFO("-r871xu_dev_remove, done\n"); + + return; +} + +static int __init rtw_drv_entry(void) +{ + int ret = 0; + + RTW_PRINT("module init start\n"); + dump_drv_version(RTW_DBGDUMP); +#ifdef BTCOEXVERSION + RTW_PRINT(DRV_NAME" BT-Coex version = %s\n", BTCOEXVERSION); +#endif /* BTCOEXVERSION */ + + pci_drvpriv.drv_registered = _TRUE; + rtw_suspend_lock_init(); + rtw_ndev_notifier_register(); + + ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv); + + if (ret != 0) { + pci_drvpriv.drv_registered = _FALSE; + rtw_suspend_lock_uninit(); + rtw_ndev_notifier_unregister(); + goto exit; + } + +exit: + RTW_PRINT("module init ret=%d\n", ret); + return ret; +} + +static void __exit rtw_drv_halt(void) +{ + RTW_PRINT("module exit start\n"); + + pci_drvpriv.drv_registered = _FALSE; + + pci_unregister_driver(&pci_drvpriv.rtw_pci_drv); + + rtw_suspend_lock_uninit(); + rtw_ndev_notifier_unregister(); + + RTW_PRINT("module exit success\n"); + + rtw_mstat_dump(RTW_DBGDUMP); +} + +module_init(rtw_drv_entry); +module_exit(rtw_drv_halt); diff --git a/drivers/staging/rtl8821ce/os_dep/linux/recv_linux.c b/drivers/staging/rtl8821ce/os_dep/linux/recv_linux.c new file mode 100644 index 000000000000..5b1541d3f8e5 --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/recv_linux.c @@ -0,0 +1,577 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RECV_OSDEP_C_ + +#include <drv_types.h> + +int rtw_os_recvframe_duplicate_skb(_adapter *padapter, union recv_frame *pcloneframe, _pkt *pskb) +{ + int res = _SUCCESS; + _pkt *pkt_copy = NULL; + struct rx_pkt_attrib *pattrib = &pcloneframe->u.hdr.attrib; + + if (pskb == NULL) { + RTW_INFO("%s [WARN] skb == NULL, drop frag frame\n", __func__); + return _FAIL; + } + pkt_copy = rtw_skb_copy(pskb); + + if (pkt_copy == NULL) { + RTW_INFO("%s [WARN] rtw_skb_copy fail , drop frag frame\n", __func__); + return _FAIL; + } + pkt_copy->dev = padapter->pnetdev; + + pcloneframe->u.hdr.pkt = pkt_copy; + pcloneframe->u.hdr.rx_head = pkt_copy->head; + pcloneframe->u.hdr.rx_data = pkt_copy->data; + pcloneframe->u.hdr.rx_end = skb_end_pointer(pkt_copy); + pcloneframe->u.hdr.rx_tail = skb_tail_pointer(pkt_copy); + pcloneframe->u.hdr.len = pkt_copy->len; + + return res; +} + +int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb) +{ + int res = _SUCCESS; + u8 shift_sz = 0; + u32 skb_len, alloc_sz; + _pkt *pkt_copy = NULL; + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + + if (pdata == NULL) { + precvframe->u.hdr.pkt = NULL; + res = _FAIL; + return res; + } + + /* Modified by Albert 20101213 */ + /* For 8 bytes IP header alignment. */ + shift_sz = pattrib->qos ? 6 : 0; /* Qos data, wireless lan header length is 26 */ + + skb_len = pattrib->pkt_len; + + /* for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. */ + /* modify alloc_sz for recvive crc error packet by thomas 2011-06-02 */ + if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) { + /* alloc_sz = 1664; */ /* 1664 is 128 alignment. */ + alloc_sz = (skb_len <= 1650) ? 1664 : (skb_len + 14); + } else { + alloc_sz = skb_len; + /* 6 is for IP header 8 bytes alignment in QoS packet case. */ + /* 8 is for skb->data 4 bytes alignment. */ + alloc_sz += 14; + } + + pkt_copy = rtw_skb_alloc(alloc_sz); + + if (pkt_copy) { + pkt_copy->dev = padapter->pnetdev; + pkt_copy->len = skb_len; + precvframe->u.hdr.pkt = pkt_copy; + precvframe->u.hdr.rx_head = pkt_copy->head; + precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; + skb_reserve(pkt_copy, 8 - ((SIZE_PTR)(pkt_copy->data) & 7)); /* force pkt_copy->data at 8-byte alignment address */ + skb_reserve(pkt_copy, shift_sz);/* force ip_hdr at 8-byte alignment address according to shift_sz. */ + _rtw_memcpy(pkt_copy->data, pdata, skb_len); + precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; + } else { + + if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) { + RTW_INFO("%s: alloc_skb fail , drop frag frame\n", __FUNCTION__); + /* rtw_free_recvframe(precvframe, pfree_recv_queue); */ + res = _FAIL; + goto exit_rtw_os_recv_resource_alloc; + } + + if (pskb == NULL) { + res = _FAIL; + goto exit_rtw_os_recv_resource_alloc; + } + + precvframe->u.hdr.pkt = rtw_skb_clone(pskb); + if (precvframe->u.hdr.pkt) { + precvframe->u.hdr.pkt->dev = padapter->pnetdev; + precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pdata; + precvframe->u.hdr.rx_end = pdata + alloc_sz; + } else { + RTW_INFO("%s: rtw_skb_clone fail\n", __FUNCTION__); + /* rtw_free_recvframe(precvframe, pfree_recv_queue); */ + /*exit_rtw_os_recv_resource_alloc;*/ + res = _FAIL; + } + } + +exit_rtw_os_recv_resource_alloc: + + return res; + +} + +void rtw_os_free_recvframe(union recv_frame *precvframe) +{ + if (precvframe->u.hdr.pkt) { + rtw_skb_free(precvframe->u.hdr.pkt);/* free skb by driver */ + + precvframe->u.hdr.pkt = NULL; + } +} + +/* init os related resource in struct recv_priv */ +int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter) +{ + int res = _SUCCESS; + + skb_queue_head_init(&precvpriv->rx_napi_skb_queue); + + return res; +} + +/* alloc os related resource in union recv_frame */ +int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe) +{ + int res = _SUCCESS; + + precvframe->u.hdr.pkt_newalloc = precvframe->u.hdr.pkt = NULL; + + return res; +} + +/* free os related resource in union recv_frame */ +void rtw_os_recv_resource_free(struct recv_priv *precvpriv) +{ + sint i; + union recv_frame *precvframe; + precvframe = (union recv_frame *) precvpriv->precv_frame_buf; + + if (skb_queue_len(&precvpriv->rx_napi_skb_queue)) + RTW_WARN("rx_napi_skb_queue not empty\n"); + rtw_skb_queue_purge(&precvpriv->rx_napi_skb_queue); + + for (i = 0; i < NR_RECVFRAME; i++) { + if (precvframe->u.hdr.pkt) { + rtw_skb_free(precvframe->u.hdr.pkt);/* free skb by driver */ + precvframe->u.hdr.pkt = NULL; + } + precvframe++; + } +} + +/* alloc os related resource in struct recv_buf */ +int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf) +{ + int res = _SUCCESS; + + return res; +} + +/* free os related resource in struct recv_buf */ +int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) +{ + int ret = _SUCCESS; + + if (precvbuf->pskb) { + rtw_skb_free(precvbuf->pskb); + } + return ret; + +} + +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata) +{ + u16 eth_type; + u8 *data_ptr; + _pkt *sub_skb; + struct rx_pkt_attrib *pattrib; + + pattrib = &prframe->u.hdr.attrib; + + sub_skb = rtw_skb_alloc(nSubframe_Length + 12); + if (sub_skb) { + skb_reserve(sub_skb, 12); + data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); + _rtw_memcpy(data_ptr, (pdata + ETH_HLEN), nSubframe_Length); + } else + { + sub_skb = rtw_skb_clone(prframe->u.hdr.pkt); + if (sub_skb) { + sub_skb->data = pdata + ETH_HLEN; + sub_skb->len = nSubframe_Length; + skb_set_tail_pointer(sub_skb, nSubframe_Length); + } else { + RTW_INFO("%s(): rtw_skb_clone() Fail!!!\n", __FUNCTION__); + return NULL; + } + } + + eth_type = RTW_GET_BE16(&sub_skb->data[6]); + + if (sub_skb->len >= 8 && + ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) && + eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || + _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE))) { + /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ + skb_pull(sub_skb, SNAP_SIZE); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + } else { + u16 len; + /* Leave Ethernet header part of hdr and full payload */ + len = htons(sub_skb->len); + _rtw_memcpy(skb_push(sub_skb, 2), &len, 2); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + } + + return sub_skb; +} + +static int napi_recv(_adapter *padapter, int budget) +{ + _pkt *pskb; + struct recv_priv *precvpriv = &padapter->recvpriv; + int work_done = 0; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + u8 rx_ok; + + while ((work_done < budget) && + (!skb_queue_empty(&precvpriv->rx_napi_skb_queue))) { + pskb = skb_dequeue(&precvpriv->rx_napi_skb_queue); + if (!pskb) + break; + + rx_ok = _FALSE; + + if (pregistrypriv->en_gro) { + if (rtw_napi_gro_receive(&padapter->napi, pskb) != GRO_DROP) + rx_ok = _TRUE; + goto next; + } + + if (rtw_netif_receive_skb(padapter->pnetdev, pskb) == NET_RX_SUCCESS) + rx_ok = _TRUE; + +next: + if (rx_ok == _TRUE) { + work_done++; + DBG_COUNTER(padapter->rx_logs.os_netif_ok); + } else { + DBG_COUNTER(padapter->rx_logs.os_netif_err); + } + } + + return work_done; +} + +int rtw_recv_napi_poll(struct napi_struct *napi, int budget) +{ + _adapter *padapter = container_of(napi, _adapter, napi); + int work_done = 0; + struct recv_priv *precvpriv = &padapter->recvpriv; + + work_done = napi_recv(padapter, budget); + if (work_done < budget) { + napi_complete(napi); + if (!skb_queue_empty(&precvpriv->rx_napi_skb_queue)) + napi_schedule(napi); + } + + return work_done; +} + + +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct recv_priv *precvpriv = &(padapter->recvpriv); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + void *br_port = NULL; + int ret; + + /* Indicat the packets to upper layer */ + if (pkt) { + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + _pkt *pskb2 = NULL; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + int bmcast = IS_MCAST(pattrib->dst); + + /* RTW_INFO("bmcast=%d\n", bmcast); */ + + if (_rtw_memcmp(pattrib->dst, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) { + /* RTW_INFO("not ap psta=%p, addr=%pM\n", psta, pattrib->dst); */ + + if (bmcast) { + psta = rtw_get_bcmc_stainfo(padapter); + pskb2 = rtw_skb_clone(pkt); + } else + psta = rtw_get_stainfo(pstapriv, pattrib->dst); + + if (psta) { + struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; + + /* RTW_INFO("directly forwarding to the rtw_xmit_entry\n"); */ + + /* skb->ip_summed = CHECKSUM_NONE; */ + pkt->dev = pnetdev; + skb_set_queue_mapping(pkt, rtw_recv_select_queue(pkt)); + + _rtw_xmit_entry(pkt, pnetdev); + + if (bmcast && (pskb2 != NULL)) { + pkt = pskb2; + DBG_COUNTER(padapter->rx_logs.os_indicate_ap_mcast); + } else { + DBG_COUNTER(padapter->rx_logs.os_indicate_ap_forward); + return; + } + } + } else { /* to APself */ + /* RTW_INFO("to APSelf\n"); */ + DBG_COUNTER(padapter->rx_logs.os_indicate_ap_self); + } + } + + /* Insert NAT2.5 RX here! */ + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); + + if (br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE) == _TRUE)) { + int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); + if (nat25_handle_frame(padapter, pkt) == -1) { + } + } + if (precvpriv->sink_udpport > 0) + rtw_sink_rtp_seq_dbg(padapter, pkt); + /* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */ + pkt->protocol = eth_type_trans(pkt, padapter->pnetdev); + pkt->dev = padapter->pnetdev; + + pkt->ip_summed = CHECKSUM_NONE; + + if (pregistrypriv->en_napi) { + skb_queue_tail(&precvpriv->rx_napi_skb_queue, pkt); + napi_schedule(&padapter->napi); + return; + } + + ret = rtw_netif_rx(padapter->pnetdev, pkt); + if (ret == NET_RX_SUCCESS) + DBG_COUNTER(padapter->rx_logs.os_netif_ok); + else + DBG_COUNTER(padapter->rx_logs.os_netif_err); + } +} + +void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup) +{ + union iwreq_data wrqu; + struct iw_michaelmicfailure ev; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + u32 cur_time = 0; + + if (psecuritypriv->last_mic_err_time == 0) + psecuritypriv->last_mic_err_time = rtw_get_current_time(); + else { + cur_time = rtw_get_current_time(); + + if (cur_time - psecuritypriv->last_mic_err_time < 60 * HZ) { + psecuritypriv->btkip_countermeasure = _TRUE; + psecuritypriv->last_mic_err_time = 0; + psecuritypriv->btkip_countermeasure_time = cur_time; + } else + psecuritypriv->last_mic_err_time = rtw_get_current_time(); + } + + + _rtw_memset(&ev, 0x00, sizeof(ev)); + if (bgroup) + ev.flags |= IW_MICFAILURE_GROUP; + else + ev.flags |= IW_MICFAILURE_PAIRWISE; + + ev.src_addr.sa_family = ARPHRD_ETHER; + _rtw_memcpy(ev.src_addr.sa_data, sta->hwaddr, ETH_ALEN); + + _rtw_memset(&wrqu, 0x00, sizeof(wrqu)); + wrqu.data.length = sizeof(ev); + + wireless_send_event(padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char *) &ev); +} + +void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) +{ +} + + +int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) +{ + int ret = _FAIL; + struct recv_priv *precvpriv; + _queue *pfree_recv_queue; + _pkt *skb; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct rx_pkt_attrib *pattrib; + + if (NULL == precv_frame) + goto _recv_drop; + + pattrib = &precv_frame->u.hdr.attrib; + precvpriv = &(padapter->recvpriv); + pfree_recv_queue = &(precvpriv->free_recv_queue); + + skb = precv_frame->u.hdr.pkt; + if (skb == NULL) { + RTW_INFO("%s :skb==NULL something wrong!!!!\n", __func__); + goto _recv_drop; + } + + skb->data = precv_frame->u.hdr.rx_data; + skb_set_tail_pointer(skb, precv_frame->u.hdr.len); + skb->len = precv_frame->u.hdr.len; + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = htons(0x0019); /* ETH_P_80211_RAW */ + + rtw_netif_rx(padapter->pnetdev, skb); + + /* pointers to NULL before rtw_free_recvframe() */ + precv_frame->u.hdr.pkt = NULL; + + ret = _SUCCESS; + +_recv_drop: + + /* enqueue back to free_recv_queue */ + if (precv_frame) + rtw_free_recvframe(precv_frame, pfree_recv_queue); + + return ret; + +} + +int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) +{ + struct recv_priv *precvpriv; + _queue *pfree_recv_queue; + _pkt *skb; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct rx_pkt_attrib *pattrib; + + if (NULL == precv_frame) + goto _recv_indicatepkt_drop; + + DBG_COUNTER(padapter->rx_logs.os_indicate); + pattrib = &precv_frame->u.hdr.attrib; + precvpriv = &(padapter->recvpriv); + pfree_recv_queue = &(precvpriv->free_recv_queue); + + + skb = precv_frame->u.hdr.pkt; + if (skb == NULL) { + goto _recv_indicatepkt_drop; + } + + skb->data = precv_frame->u.hdr.rx_data; + + skb_set_tail_pointer(skb, precv_frame->u.hdr.len); + + skb->len = precv_frame->u.hdr.len; + + if (pattrib->eth_type == 0x888e) + RTW_PRINT("recv eapol packet\n"); + + + /* TODO: move to core */ + { + _pkt *pkt = skb; + struct ethhdr *etherhdr = (struct ethhdr *)pkt->data; + struct sta_info *sta = precv_frame->u.hdr.psta; + + if (!sta) + goto bypass_session_tracker; + + if (ntohs(etherhdr->h_proto) == ETH_P_IP) { + u8 *ip = pkt->data + 14; + + if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ + && rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE + ) { + u8 *tcp = ip + GET_IPV4_IHL(ip) * 4; + + if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, padapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) { + if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { + session_tracker_add_cmd(padapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + if (GET_TCP_FIN(tcp)) { + session_tracker_del_cmd(padapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + RTW_INFO(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + } + + } + } +bypass_session_tracker: + ; + } + + rtw_os_recv_indicate_pkt(padapter, skb, pattrib); + + precv_frame->u.hdr.pkt = NULL; /* pointers to NULL before rtw_free_recvframe() */ + + rtw_free_recvframe(precv_frame, pfree_recv_queue); + + return _SUCCESS; + +_recv_indicatepkt_drop: + + /* enqueue back to free_recv_queue */ + if (precv_frame) + rtw_free_recvframe(precv_frame, pfree_recv_queue); + + DBG_COUNTER(padapter->rx_logs.os_indicate_err); + + return _FAIL; + +} + +void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + +} + diff --git a/drivers/staging/rtl8821ce/os_dep/linux/rtw_android.c b/drivers/staging/rtl8821ce/os_dep/linux/rtw_android.c new file mode 100644 index 000000000000..099e2e483478 --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/rtw_android.c @@ -0,0 +1,549 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include <drv_types.h> + +#define strnicmp strncasecmp + +#include "rtw_version.h" + +extern void macstr2num(u8 *dst, u8 *src); + +const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = { + "START", + "STOP", + "SCAN-ACTIVE", + "SCAN-PASSIVE", + "RSSI", + "LINKSPEED", + "RXFILTER-START", + "RXFILTER-STOP", + "RXFILTER-ADD", + "RXFILTER-REMOVE", + "BTCOEXSCAN-START", + "BTCOEXSCAN-STOP", + "BTCOEXMODE", + "SETSUSPENDOPT", + "P2P_DEV_ADDR", + "SETFWPATH", + "SETBAND", + "GETBAND", + "COUNTRY", + "P2P_SET_NOA", + "P2P_GET_NOA", + "P2P_SET_PS", + "SET_AP_WPS_P2P_IE", + + "MIRACAST", + + + "MACADDR", + + "BLOCK_SCAN", + "BLOCK", + "WFD-ENABLE", + "WFD-DISABLE", + "WFD-SET-TCPPORT", + "WFD-SET-MAXTPUT", + "WFD-SET-DEVTYPE", + "SET_DTIM", + "HOSTAPD_SET_MACADDR_ACL", + "HOSTAPD_ACL_ADD_STA", + "HOSTAPD_ACL_REMOVE_STA", +/* Private command for P2P disable*/ + "P2P_DISABLE", + "DRIVER_VERSION" +}; + + +typedef struct android_wifi_priv_cmd { + char *buf; + int used_len; + int total_len; +} android_wifi_priv_cmd; + +/** + * Local (static) functions and variables + */ + +/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first + * time (only) in dhd_open, subsequential wifi on will be handled by + * wl_android_wifi_on + */ +static int g_wifi_on = _TRUE; + +unsigned int oob_irq = 0; +unsigned int oob_gpio = 0; + + +int rtw_android_cmdstr_to_num(char *cmdstr) +{ + int cmd_num; + for (cmd_num = 0 ; cmd_num < ANDROID_WIFI_CMD_MAX; cmd_num++) + if (0 == strnicmp(cmdstr , android_wifi_cmd_str[cmd_num], strlen(android_wifi_cmd_str[cmd_num]))) + break; + + return cmd_num; +} + +int rtw_android_get_rssi(struct net_device *net, char *command, int total_len) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *pcur_network = &pmlmepriv->cur_network; + int bytes_written = 0; + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d", + pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); + } + + return bytes_written; +} + +int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *pcur_network = &pmlmepriv->cur_network; + int bytes_written = 0; + u16 link_speed = 0; + + link_speed = rtw_get_cur_max_rate(padapter) / 10; + bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed); + + return bytes_written; +} + +int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(net); + int bytes_written = 0; + + bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr)); + return bytes_written; +} + +int rtw_android_set_country(struct net_device *net, char *command, int total_len) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(net); + char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1; + int ret = _FAIL; + + ret = rtw_set_country(adapter, country_code); + + return (ret == _SUCCESS) ? 0 : -1; +} + +int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len) +{ + int bytes_written = 0; + + /* We use the same address as our HW MAC address */ + _rtw_memcpy(command, net->dev_addr, ETH_ALEN); + + bytes_written = ETH_ALEN; + return bytes_written; +} + +int rtw_android_set_block_scan(struct net_device *net, char *command, int total_len) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(net); + char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK_SCAN]) + 1; + + + return 0; +} + +int rtw_android_set_block(struct net_device *net, char *command, int total_len) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(net); + char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1; + + + return 0; +} + +int rtw_android_setband(struct net_device *net, char *command, int total_len) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(net); + char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SETBAND]) + 1; + u32 band = WIFI_FREQUENCY_BAND_AUTO; + int ret = _FAIL; + + if (sscanf(arg, "%u", &band) >= 1) + ret = rtw_set_band(adapter, band); + + return (ret == _SUCCESS) ? 0 : -1; +} + +int rtw_android_getband(struct net_device *net, char *command, int total_len) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(net); + int bytes_written = 0; + + bytes_written = snprintf(command, total_len, "%u", adapter->setband); + + return bytes_written; +} + +int rtw_android_set_miracast_mode(struct net_device *net, char *command, int total_len) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(net); + struct wifi_display_info *wfd_info = &adapter->wfd_info; + char *arg = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_MIRACAST]) + 1; + u8 mode; + int num; + int ret = _FAIL; + + num = sscanf(arg, "%hhu", &mode); + + if (num < 1) + goto exit; + + switch (mode) { + case 1: /* soruce */ + mode = MIRACAST_SOURCE; + break; + case 2: /* sink */ + mode = MIRACAST_SINK; + break; + case 0: /* disabled */ + default: + mode = MIRACAST_DISABLED; + break; + } + wfd_info->stack_wfd_mode = mode; + RTW_INFO("stack miracast mode: %s\n", get_miracast_mode_str(wfd_info->stack_wfd_mode)); + + ret = _SUCCESS; + +exit: + return (ret == _SUCCESS) ? 0 : -1; +} + +int get_int_from_command(char *pcmd) +{ + int i = 0; + + for (i = 0; i < strlen(pcmd); i++) { + if (pcmd[i] == '=') { + /* Skip the '=' and space characters. */ + i += 2; + break; + } + } + return rtw_atoi(pcmd + i) ; +} + + +int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) +{ + int ret = 0; + char *command = NULL; + int cmd_num; + int bytes_written = 0; + android_wifi_priv_cmd priv_cmd; + _adapter *padapter = (_adapter *) rtw_netdev_priv(net); + struct wifi_display_info *pwfd_info; + + rtw_lock_suspend(); + + if (!ifr->ifr_data) { + ret = -EINVAL; + goto exit; + } + if (padapter->registrypriv.mp_mode == 1) { + ret = -EINVAL; + goto exit; + } + if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) { + ret = -EFAULT; + goto exit; + } + if (padapter->registrypriv.mp_mode == 1) { + ret = -EFAULT; + goto exit; + } + /*RTW_INFO("%s priv_cmd.buf=%p priv_cmd.total_len=%d priv_cmd.used_len=%d\n",__func__,priv_cmd.buf,priv_cmd.total_len,priv_cmd.used_len);*/ + command = rtw_zmalloc(priv_cmd.total_len); + if (!command) { + RTW_INFO("%s: failed to allocate memory\n", __FUNCTION__); + ret = -ENOMEM; + goto exit; + } + + if (!access_ok(priv_cmd.buf, priv_cmd.total_len)) { + RTW_INFO("%s: failed to access memory\n", __FUNCTION__); + ret = -EFAULT; + goto exit; + } + if (copy_from_user(command, (void *)priv_cmd.buf, priv_cmd.total_len)) { + ret = -EFAULT; + goto exit; + } + + RTW_INFO("%s: Android private cmd \"%s\" on %s\n" + , __FUNCTION__, command, ifr->ifr_name); + + cmd_num = rtw_android_cmdstr_to_num(command); + + switch (cmd_num) { + case ANDROID_WIFI_CMD_START: + /* bytes_written = wl_android_wifi_on(net); */ + goto response; + case ANDROID_WIFI_CMD_SETFWPATH: + goto response; + } + + if (!g_wifi_on) { + RTW_INFO("%s: Ignore private cmd \"%s\" - iface %s is down\n" + , __FUNCTION__, command, ifr->ifr_name); + ret = 0; + goto exit; + } + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + switch (cmd_num) { + case ANDROID_WIFI_CMD_WFD_ENABLE: + case ANDROID_WIFI_CMD_WFD_DISABLE: + case ANDROID_WIFI_CMD_WFD_SET_TCPPORT: + case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: + case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE: + goto response; + } + } + + switch (cmd_num) { + + case ANDROID_WIFI_CMD_STOP: + /* bytes_written = wl_android_wifi_off(net); */ + break; + + case ANDROID_WIFI_CMD_SCAN_ACTIVE: + /* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); */ +#ifdef CONFIG_PLATFORM_MSTAR +#endif /* CONFIG_PLATFORM_MSTAR */ + break; + case ANDROID_WIFI_CMD_SCAN_PASSIVE: + /* rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); */ + break; + + case ANDROID_WIFI_CMD_RSSI: + bytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len); + break; + case ANDROID_WIFI_CMD_LINKSPEED: + bytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len); + break; + + case ANDROID_WIFI_CMD_MACADDR: + bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len); + break; + + case ANDROID_WIFI_CMD_BLOCK_SCAN: + bytes_written = rtw_android_set_block_scan(net, command, priv_cmd.total_len); + break; + + case ANDROID_WIFI_CMD_BLOCK: + bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len); + break; + + case ANDROID_WIFI_CMD_RXFILTER_START: + /* bytes_written = net_os_set_packet_filter(net, 1); */ + break; + case ANDROID_WIFI_CMD_RXFILTER_STOP: + /* bytes_written = net_os_set_packet_filter(net, 0); */ + break; + case ANDROID_WIFI_CMD_RXFILTER_ADD: + /* int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0'; */ + /* bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num); */ + break; + case ANDROID_WIFI_CMD_RXFILTER_REMOVE: + /* int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0'; */ + /* bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num); */ + break; + + case ANDROID_WIFI_CMD_BTCOEXSCAN_START: + /* TBD: BTCOEXSCAN-START */ + break; + case ANDROID_WIFI_CMD_BTCOEXSCAN_STOP: + /* TBD: BTCOEXSCAN-STOP */ + break; + case ANDROID_WIFI_CMD_BTCOEXMODE: + break; + + case ANDROID_WIFI_CMD_SETSUSPENDOPT: + /* bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len); */ + break; + + case ANDROID_WIFI_CMD_SETBAND: + bytes_written = rtw_android_setband(net, command, priv_cmd.total_len); + break; + + case ANDROID_WIFI_CMD_GETBAND: + bytes_written = rtw_android_getband(net, command, priv_cmd.total_len); + break; + + case ANDROID_WIFI_CMD_COUNTRY: + bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len); + break; + + + case ANDROID_WIFI_CMD_P2P_DEV_ADDR: + bytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len); + break; + case ANDROID_WIFI_CMD_P2P_SET_NOA: + /* int skip = strlen(CMD_P2P_SET_NOA) + 1; */ + /* bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip); */ + break; + case ANDROID_WIFI_CMD_P2P_GET_NOA: + /* bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len); */ + break; + case ANDROID_WIFI_CMD_P2P_SET_PS: + /* int skip = strlen(CMD_P2P_SET_PS) + 1; */ + /* bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip); */ + break; + + + + case ANDROID_WIFI_CMD_MIRACAST: + bytes_written = rtw_android_set_miracast_mode(net, command, priv_cmd.total_len); + break; + + case ANDROID_WIFI_CMD_WFD_ENABLE: { + /* Commented by Albert 2012/07/24 */ + /* We can enable the WFD function by using the following command: */ + /* wpa_cli driver wfd-enable */ + + if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) + rtw_wfd_enable(padapter, 1); + break; + } + + case ANDROID_WIFI_CMD_WFD_DISABLE: { + /* Commented by Albert 2012/07/24 */ + /* We can disable the WFD function by using the following command: */ + /* wpa_cli driver wfd-disable */ + + if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) + rtw_wfd_enable(padapter, 0); + break; + } + case ANDROID_WIFI_CMD_WFD_SET_TCPPORT: { + /* Commented by Albert 2012/07/24 */ + /* We can set the tcp port number by using the following command: */ + /* wpa_cli driver wfd-set-tcpport = 554 */ + + if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) + rtw_wfd_set_ctrl_port(padapter, (u16)get_int_from_command(priv_cmd.buf)); + break; + } + case ANDROID_WIFI_CMD_WFD_SET_MAX_TPUT: { + break; + } + case ANDROID_WIFI_CMD_WFD_SET_DEVTYPE: { + /* Commented by Albert 2012/08/28 */ + /* Specify the WFD device type ( WFD source/primary sink ) */ + + pwfd_info = &padapter->wfd_info; + if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { + pwfd_info->wfd_device_type = (u8) get_int_from_command(priv_cmd.buf); + pwfd_info->wfd_device_type &= WFD_DEVINFO_DUAL; + } + break; + } + case ANDROID_WIFI_CMD_CHANGE_DTIM: { + u8 dtim; + u8 *ptr = (u8 *) &priv_cmd.buf; + + ptr += 9;/* string command length of "SET_DTIM"; */ + + dtim = rtw_atoi(ptr); + + RTW_INFO("DTIM=%d\n", dtim); + + rtw_lps_change_dtim_cmd(padapter, dtim); + } + break; + + case ANDROID_WIFI_CMD_HOSTAPD_SET_MACADDR_ACL: { + rtw_set_macaddr_acl(padapter, get_int_from_command(command)); + break; + } + case ANDROID_WIFI_CMD_HOSTAPD_ACL_ADD_STA: { + u8 addr[ETH_ALEN] = {0x00}; + macstr2num(addr, command + strlen("HOSTAPD_ACL_ADD_STA") + 3); /* 3 is space bar + "=" + space bar these 3 chars */ + rtw_acl_add_sta(padapter, addr); + break; + } + case ANDROID_WIFI_CMD_HOSTAPD_ACL_REMOVE_STA: { + u8 addr[ETH_ALEN] = {0x00}; + macstr2num(addr, command + strlen("HOSTAPD_ACL_REMOVE_STA") + 3); /* 3 is space bar + "=" + space bar these 3 chars */ + rtw_acl_remove_sta(padapter, addr); + break; + } + case ANDROID_WIFI_CMD_P2P_DISABLE: { + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 channel, ch_offset; + u16 bwmode; + + rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); + break; + } + case ANDROID_WIFI_CMD_DRIVERVERSION: { + bytes_written = strlen(DRIVERVERSION); + snprintf(command, bytes_written + 1, DRIVERVERSION); + break; + } + default: + RTW_INFO("Unknown PRIVATE command %s - ignored\n", command); + snprintf(command, 3, "OK"); + bytes_written = strlen("OK"); + } + +response: + if (bytes_written >= 0) { + if ((bytes_written == 0) && (priv_cmd.total_len > 0)) + command[0] = '\0'; + if (bytes_written >= priv_cmd.total_len) { + RTW_INFO("%s: bytes_written = %d\n", __FUNCTION__, bytes_written); + bytes_written = priv_cmd.total_len; + } else + bytes_written++; + priv_cmd.used_len = bytes_written; + if (copy_to_user((void *)priv_cmd.buf, command, bytes_written)) { + RTW_INFO("%s: failed to copy data to user buffer\n", __FUNCTION__); + ret = -EFAULT; + } + } else + ret = bytes_written; + +exit: + rtw_unlock_suspend(); + if (command) + rtw_mfree(command, priv_cmd.total_len); + + return ret; +} + +/** + * Functions for Android WiFi card detection + */ diff --git a/drivers/staging/rtl8821ce/os_dep/linux/xmit_linux.c b/drivers/staging/rtl8821ce/os_dep/linux/xmit_linux.c new file mode 100644 index 000000000000..fab51f9b1cfe --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/linux/xmit_linux.c @@ -0,0 +1,353 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _XMIT_OSDEP_C_ + +#include <drv_types.h> + +#define DBG_DUMP_OS_QUEUE_CTL 0 + +uint rtw_remainder_len(struct pkt_file *pfile) +{ + return pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start)); +} + +void _rtw_open_pktfile(_pkt *pktptr, struct pkt_file *pfile) +{ + + pfile->pkt = pktptr; + pfile->cur_addr = pfile->buf_start = pktptr->data; + pfile->pkt_len = pfile->buf_len = pktptr->len; + + pfile->cur_buffer = pfile->buf_start ; + +} + +uint _rtw_pktfile_read(struct pkt_file *pfile, u8 *rmem, uint rlen) +{ + uint len = 0; + + len = rtw_remainder_len(pfile); + len = (rlen > len) ? len : rlen; + + if (rmem) + skb_copy_bits(pfile->pkt, pfile->buf_len - pfile->pkt_len, rmem, len); + + pfile->cur_addr += len; + pfile->pkt_len -= len; + + return len; +} + +sint rtw_endofpktfile(struct pkt_file *pfile) +{ + + if (pfile->pkt_len == 0) { + return _TRUE; + } + + return _FALSE; +} + +void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib) +{ + + +} + +int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag) +{ + if (alloc_sz > 0) { + pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz); + if (pxmitbuf->pallocated_buf == NULL) + return _FAIL; + + pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); + } + + return _SUCCESS; +} + +void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag) +{ + if (free_sz > 0) { + if (pxmitbuf->pallocated_buf) + rtw_mfree(pxmitbuf->pallocated_buf, free_sz); + } +} + +#define WMM_XMIT_THRESHOLD (NR_XMITFRAME*2/5) + +static inline bool rtw_os_need_wake_queue(_adapter *padapter, u16 qidx) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (padapter->registrypriv.wifi_spec) { + if (pxmitpriv->hwxmits[qidx].accnt < WMM_XMIT_THRESHOLD) + return _TRUE; + } else { + return _TRUE; + } + return _FALSE; +} + +static inline bool rtw_os_need_stop_queue(_adapter *padapter, u16 qidx) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + if (padapter->registrypriv.wifi_spec) { + /* No free space for Tx, tx_worker is too slow */ + if (pxmitpriv->hwxmits[qidx].accnt > WMM_XMIT_THRESHOLD) + return _TRUE; + } else { + if (pxmitpriv->free_xmitframe_cnt <= 4) + return _TRUE; + } + return _FALSE; +} + +void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt) +{ + u16 qidx; + + qidx = skb_get_queue_mapping(pkt); + if (rtw_os_need_wake_queue(padapter, qidx)) { + if (DBG_DUMP_OS_QUEUE_CTL) + RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), qidx); + netif_wake_subqueue(padapter->pnetdev, qidx); + } + + rtw_skb_free(pkt); +} + +void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe) +{ + if (pxframe->pkt) + rtw_os_pkt_complete(padapter, pxframe->pkt); + + pxframe->pkt = NULL; +} + +void rtw_os_xmit_schedule(_adapter *padapter) +{ + _irqL irqL; + struct xmit_priv *pxmitpriv; + + if (!padapter) + return; + + pxmitpriv = &padapter->xmitpriv; + + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + if (rtw_txframes_pending(padapter)) + tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + + +} + +static bool rtw_check_xmit_resource(_adapter *padapter, _pkt *pkt) +{ + bool busy = _FALSE; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + u16 qidx; + + qidx = skb_get_queue_mapping(pkt); + if (rtw_os_need_stop_queue(padapter, qidx)) { + if (DBG_DUMP_OS_QUEUE_CTL) + RTW_INFO(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), qidx); + netif_stop_subqueue(padapter->pnetdev, qidx); + busy = _TRUE; + } + return busy; +} + +void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed) +{ + int i; + + for (i = 0; i < 4; i++) { + if (qcnt_freed[i] == 0) + continue; + + if (rtw_os_need_wake_queue(padapter, i)) { + if (DBG_DUMP_OS_QUEUE_CTL) + RTW_INFO(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), i); + netif_wake_subqueue(padapter->pnetdev, i); + } + } +} + +int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _irqL irqL; + _list *phead, *plist; + struct sk_buff *newskb; + struct sta_info *psta = NULL; + u8 chk_alive_num = 0; + char chk_alive_list[NUM_STA]; + u8 bc_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[6] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + int i; + s32 res; + + DBG_COUNTER(padapter->tx_logs.os_tx_m2u); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + /* free sta asoc_queue */ + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) + chk_alive_list[chk_alive_num++] = stainfo_offset; + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + for (i = 0; i < chk_alive_num; i++) { + psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); + if (!(psta->state & _FW_LINKED)) { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_fw_linked); + continue; + } + + /* avoid come from STA1 and send back STA1 */ + if (_rtw_memcmp(psta->hwaddr, &skb->data[6], 6) == _TRUE + || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE + || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE + ) { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_self); + continue; + } + + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry); + + newskb = rtw_skb_copy(skb); + + if (newskb) { + _rtw_memcpy(newskb->data, psta->hwaddr, 6); + res = rtw_xmit(padapter, &newskb); + if (res < 0) { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_xmit); + RTW_INFO("%s()-%d: rtw_xmit() return error! res=%d\n", __FUNCTION__, __LINE__, res); + pxmitpriv->tx_drop++; + rtw_skb_free(newskb); + } + } else { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_skb); + RTW_INFO("%s-%d: rtw_skb_copy() failed!\n", __FUNCTION__, __LINE__); + pxmitpriv->tx_drop++; + /* rtw_skb_free(skb); */ + return _FALSE; /* Caller shall tx this multicast frame via normal way. */ + } + } + + rtw_skb_free(skb); + return _TRUE; +} + +int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + extern int rtw_mc2u_disable; + s32 res = 0; + u16 queue; + + if (padapter->registrypriv.mp_mode) { + RTW_INFO("MP_TX_DROP_OS_FRAME\n"); + goto drop_packet; + } + DBG_COUNTER(padapter->tx_logs.os_tx); + + if (rtw_if_up(padapter) == _FALSE) { + DBG_COUNTER(padapter->tx_logs.os_tx_err_up); + goto drop_packet; + } + + rtw_check_xmit_resource(padapter, pkt); + + if (!rtw_mc2u_disable + && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE + && (IP_MCAST_MAC(pkt->data) + || ICMPV6_MCAST_MAC(pkt->data) + #ifdef CONFIG_TX_BCAST2UNI + || is_broadcast_mac_addr(pkt->data) + #endif + ) + && (padapter->registrypriv.wifi_spec == 0) + ) { + if (pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME / 4)) { + res = rtw_mlcst2unicst(padapter, pkt); + if (res == _TRUE) + goto exit; + } else { + /* RTW_INFO("Stop M2U(%d, %d)! ", pxmitpriv->free_xmitframe_cnt, pxmitpriv->free_xmitbuf_cnt); */ + /* RTW_INFO("!m2u ); */ + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_stop); + } + } + + res = rtw_xmit(padapter, &pkt); + if (res < 0) { + goto drop_packet; + } + + goto exit; + +drop_packet: + pxmitpriv->tx_drop++; + rtw_os_pkt_complete(padapter, pkt); + +exit: + + return 0; +} + +int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int ret = 0; + + if (pkt) { + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) { + rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev); + } + else { + rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize); + ret = _rtw_xmit_entry(pkt, pnetdev); + } + + } + + return ret; +} diff --git a/drivers/staging/rtl8821ce/os_dep/osdep_service.c b/drivers/staging/rtl8821ce/os_dep/osdep_service.c new file mode 100644 index 000000000000..0a99432107e3 --- /dev/null +++ b/drivers/staging/rtl8821ce/os_dep/osdep_service.c @@ -0,0 +1,1325 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _OSDEP_SERVICE_C_ + +#include <drv_types.h> + +#define RT_TAG '1178' + + +/* +* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE +* @return: one of RTW_STATUS_CODE +*/ +inline int RTW_STATUS_CODE(int error_code) +{ + if (error_code >= 0) + return _SUCCESS; + + switch (error_code) { + /* case -ETIMEDOUT: */ + /* return RTW_STATUS_TIMEDOUT; */ + default: + return _FAIL; + } +} + +u32 rtw_atoi(u8 *s) +{ + + int num = 0, flag = 0; + int i; + for (i = 0; i <= strlen(s); i++) { + if (s[i] >= '0' && s[i] <= '9') + num = num * 10 + s[i] - '0'; + else if (s[0] == '-' && i == 0) + flag = 1; + else + break; + } + + if (flag == 1) + num = num * -1; + + return num; + +} + +inline u8 *_rtw_vmalloc(u32 sz) +{ + u8 *pbuf; + pbuf = vmalloc(sz); + + + return pbuf; +} + +inline u8 *_rtw_zvmalloc(u32 sz) +{ + u8 *pbuf; + pbuf = _rtw_vmalloc(sz); + if (pbuf != NULL) + memset(pbuf, 0, sz); + + return pbuf; +} + +inline void _rtw_vmfree(u8 *pbuf, u32 sz) +{ + vfree(pbuf); + +} + +u8 *_rtw_malloc(u32 sz) +{ + + u8 *pbuf = NULL; + + pbuf = kmalloc(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + + + + return pbuf; + +} + +u8 *_rtw_zmalloc(u32 sz) +{ + u8 *pbuf = _rtw_malloc(sz); + + if (pbuf != NULL) { + + memset(pbuf, 0, sz); + + } + + return pbuf; +} + +void _rtw_mfree(u8 *pbuf, u32 sz) +{ + + kfree(pbuf); + + + +} + + +inline struct sk_buff *_rtw_skb_alloc(u32 sz) +{ + return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + +} + +inline void _rtw_skb_free(struct sk_buff *skb) +{ + dev_kfree_skb_any(skb); +} + +inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb) +{ + return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + +} + +inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb) +{ + return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + +} +inline struct sk_buff *_rtw_pskb_copy(struct sk_buff *skb) +{ + return pskb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); +} + +inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) +{ + skb->dev = ndev; + return netif_rx(skb); +} + +inline int _rtw_netif_receive_skb(_nic_hdl ndev, struct sk_buff *skb) +{ + skb->dev = ndev; + return netif_receive_skb(skb); +} + +inline gro_result_t _rtw_napi_gro_receive(struct napi_struct *napi, struct sk_buff *skb) +{ + return napi_gro_receive(napi, skb); +} + +void _rtw_skb_queue_purge(struct sk_buff_head *list) +{ + struct sk_buff *skb; + + while ((skb = skb_dequeue(list)) != NULL) + _rtw_skb_free(skb); +} + + +void *rtw_malloc2d(int h, int w, size_t size) +{ + int j; + + void **a = (void **) rtw_zmalloc(h * sizeof(void *) + h * w * size); + if (a == NULL) { + RTW_INFO("%s: alloc memory fail!\n", __FUNCTION__); + return NULL; + } + + for (j = 0; j < h; j++) + a[j] = ((char *)(a + h)) + j * w * size; + + return a; +} + +void rtw_mfree2d(void *pbuf, int h, int w, int size) +{ + rtw_mfree((u8 *)pbuf, h * sizeof(void *) + w * h * size); +} + +void _rtw_memcpy(void *dst, const void *src, u32 sz) +{ + + + memcpy(dst, src, sz); + + +} + +inline void _rtw_memmove(void *dst, const void *src, u32 sz) +{ + memmove(dst, src, sz); +} + +int _rtw_memcmp(const void *dst, const void *src, u32 sz) +{ + + /* under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 */ + + if (!(memcmp(dst, src, sz))) + return _TRUE; + else + return _FALSE; + +} + +void _rtw_memset(void *pbuf, int c, u32 sz) +{ + + + memset(pbuf, c, sz); + + +} + + +void _rtw_init_listhead(_list *list) +{ + + + INIT_LIST_HEAD(list); + + + +} + +/* +For the following list_xxx operations, +caller must guarantee the atomic context. +Otherwise, there will be racing condition. +*/ +u32 rtw_is_list_empty(_list *phead) +{ + + + if (list_empty(phead)) + return _TRUE; + else + return _FALSE; + + +} + +void rtw_list_insert_head(_list *plist, _list *phead) +{ + + list_add(plist, phead); + + +} + +void rtw_list_insert_tail(_list *plist, _list *phead) +{ + + + list_add_tail(plist, phead); + + +} + +void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc, void *ctx) +{ + _adapter *adapter = (_adapter *)padapter; + + _init_timer(ptimer, adapter->pnetdev, pfunc, ctx); +} + +/* + +Caller must check if the list is empty before calling rtw_list_delete + +*/ + +void _rtw_init_sema(_sema *sema, int init_val) +{ + + + sema_init(sema, init_val); + + + +} + +void _rtw_free_sema(_sema *sema) +{ + +} + +void _rtw_up_sema(_sema *sema) +{ + + + up(sema); + + +} + +u32 _rtw_down_sema(_sema *sema) +{ + + + if (down_interruptible(sema)) + return _FAIL; + else + return _SUCCESS; + + +} + +inline void thread_exit(_completion *comp) +{ + complete_and_exit(comp, 0); + + + +} + +inline void _rtw_init_completion(_completion *comp) +{ + init_completion(comp); +} +inline void _rtw_wait_for_comp_timeout(_completion *comp) +{ + wait_for_completion_timeout(comp, msecs_to_jiffies(3000)); +} +inline void _rtw_wait_for_comp(_completion *comp) +{ + wait_for_completion(comp); +} + +inline bool rtw_thread_stop(_thread_hdl_ th) +{ + return kthread_stop(th); +} + +inline bool rtw_thread_should_stop(void) +{ + return kthread_should_stop(); +} + +void _rtw_mutex_init(_mutex *pmutex) +{ + mutex_init(pmutex); +} + +void _rtw_mutex_free(_mutex *pmutex) +{ + mutex_destroy(pmutex); +} + +void _rtw_spinlock_init(_lock *plock) +{ + + + spin_lock_init(plock); + + +} + +void _rtw_spinlock_free(_lock *plock) +{ + +} + +void _rtw_spinlock(_lock *plock) +{ + + + spin_lock(plock); + + +} + +void _rtw_spinunlock(_lock *plock) +{ + + + spin_unlock(plock); + +} + +void _rtw_spinlock_ex(_lock *plock) +{ + + + spin_lock(plock); + + +} + +void _rtw_spinunlock_ex(_lock *plock) +{ + + + spin_unlock(plock); + +} + +void _rtw_init_queue(_queue *pqueue) +{ + _rtw_init_listhead(&(pqueue->queue)); + _rtw_spinlock_init(&(pqueue->lock)); +} + +void _rtw_deinit_queue(_queue *pqueue) +{ + _rtw_spinlock_free(&(pqueue->lock)); +} + +u32 _rtw_queue_empty(_queue *pqueue) +{ + return rtw_is_list_empty(&(pqueue->queue)); +} + +u32 rtw_end_of_queue_search(_list *head, _list *plist) +{ + if (head == plist) + return _TRUE; + else + return _FALSE; +} + +u32 rtw_get_current_time(void) +{ + + return jiffies; +} + +inline u32 rtw_systime_to_ms(u32 systime) +{ + return systime * 1000 / HZ; +} + +inline u32 rtw_ms_to_systime(u32 ms) +{ + return ms * HZ / 1000; +} + +/* the input parameter start use the same unit as returned by rtw_get_current_time */ +inline s32 rtw_get_passing_time_ms(u32 start) +{ + return rtw_systime_to_ms(jiffies - start); +} + +inline s32 rtw_get_time_interval_ms(u32 start, u32 end) +{ + return rtw_systime_to_ms(end - start); +} + +void rtw_sleep_schedulable(int ms) +{ + + + u32 delta; + + delta = (ms * HZ) / 1000; /* (ms) */ + if (delta == 0) { + delta = 1;/* 1 ms */ + } + set_current_state(TASK_INTERRUPTIBLE); + if (schedule_timeout(delta) != 0) + return ; + return; + + +} + +void rtw_msleep_os(int ms) +{ + + if (ms < 20) { + unsigned long us = ms * 1000UL; + usleep_range(us, us + 1000UL); + } else + msleep((unsigned int)ms); +} +void rtw_usleep_os(int us) +{ + usleep_range(us, us + 1); +} + +void rtw_mdelay_os(int ms) +{ + + + mdelay((unsigned long)ms); + + +} +void rtw_udelay_os(int us) +{ + + + udelay((unsigned long)us); + + +} + +void rtw_yield_os(void) +{ + yield(); +} + +#define RTW_SUSPEND_LOCK_NAME "rtw_wifi" +#define RTW_SUSPEND_EXT_LOCK_NAME "rtw_wifi_ext" +#define RTW_SUSPEND_RX_LOCK_NAME "rtw_wifi_rx" +#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic" +#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume" +#define RTW_RESUME_SCAN_LOCK_NAME "rtw_wifi_scan" + +inline void rtw_suspend_lock_init(void) +{ +} + +inline void rtw_suspend_lock_uninit(void) +{ +} + +inline void rtw_lock_suspend(void) +{ + +} + +inline void rtw_unlock_suspend(void) +{ + +} + +inline void rtw_resume_lock_suspend(void) +{ + +} + +inline void rtw_resume_unlock_suspend(void) +{ + +} + +inline void rtw_lock_suspend_timeout(u32 timeout_ms) +{ +} + +inline void rtw_lock_ext_suspend_timeout(u32 timeout_ms) +{ + /* RTW_INFO("EXT lock timeout:%d\n", timeout_ms); */ +} + +inline void rtw_lock_rx_suspend_timeout(u32 timeout_ms) +{ + /* RTW_INFO("RX lock timeout:%d\n", timeout_ms); */ +} + +inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) +{ + /* RTW_INFO("traffic lock timeout:%d\n", timeout_ms); */ +} + +inline void rtw_lock_resume_scan_timeout(u32 timeout_ms) +{ + /* RTW_INFO("resume scan lock:%d\n", timeout_ms); */ +} + +inline void ATOMIC_SET(ATOMIC_T *v, int i) +{ + atomic_set(v, i); +} + +inline int ATOMIC_READ(ATOMIC_T *v) +{ + return atomic_read(v); +} + +inline void ATOMIC_ADD(ATOMIC_T *v, int i) +{ + atomic_add(i, v); +} +inline void ATOMIC_SUB(ATOMIC_T *v, int i) +{ + atomic_sub(i, v); +} + +inline void ATOMIC_INC(ATOMIC_T *v) +{ + atomic_inc(v); +} + +inline void ATOMIC_DEC(ATOMIC_T *v) +{ + atomic_dec(v); +} + +inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) +{ + return atomic_add_return(i, v); +} + +inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) +{ + return atomic_sub_return(i, v); +} + +inline int ATOMIC_INC_RETURN(ATOMIC_T *v) +{ + return atomic_inc_return(v); +} + +inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) +{ + return atomic_dec_return(v); +} + +/* +* Open a file with the specific @param path, @param flag, @param mode +* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success +* @param path the path of the file to open +* @param flag file operation flags, please refer to linux document +* @param mode please refer to linux document +* @return Linux specific error code +*/ +static int openFile(struct file **fpp, const char *path, int flag, int mode) +{ + struct file *fp; + + fp = filp_open(path, flag, mode); + if (IS_ERR(fp)) { + *fpp = NULL; + return PTR_ERR(fp); + } else { + *fpp = fp; + return 0; + } +} + +/* +* Close the file with the specific @param fp +* @param fp the pointer of struct file to close +* @return always 0 +*/ +static int closeFile(struct file *fp) +{ + filp_close(fp, NULL); + return 0; +} + +static int readFile(struct file *fp, char *buf, int len) +{ + int rlen = 0, sum = 0; + + if (!(fp->f_mode & FMODE_CAN_READ)) + return -EPERM; + + while (sum < len) { + rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos); + if (rlen > 0) + sum += rlen; + else if (0 != rlen) + return rlen; + else + break; + } + + return sum; + +} + +static int writeFile(struct file *fp, char *buf, int len) +{ + int wlen = 0, sum = 0; + + if (!fp->f_op || !fp->f_op->write) + return -EPERM; + + while (sum < len) { + wlen = fp->f_op->write(fp, buf + sum, len - sum, &fp->f_pos); + if (wlen > 0) + sum += wlen; + else if (0 != wlen) + return wlen; + else + break; + } + + return sum; + +} + +/* +* Test if the specifi @param path is a file and readable +* If readable, @param sz is got +* @param path the path of the file to test +* @return Linux specific error code +*/ +static int isFileReadable(const char *path, u32 *sz) +{ + struct file *fp; + int ret = 0; + mm_segment_t oldfs; + char buf; + + fp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(fp)) + ret = PTR_ERR(fp); + else { + oldfs = get_fs(); + set_fs(KERNEL_DS); + + if (1 != readFile(fp, &buf, 1)) + ret = PTR_ERR(fp); + + if (ret == 0 && sz) { + *sz = i_size_read(fp->f_path.dentry->d_inode); + } + + set_fs(oldfs); + filp_close(fp, NULL); + } + return ret; +} + +/* +* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most +* @param path the path of the file to open and read +* @param buf the starting address of the buffer to store file content +* @param sz how many bytes to read at most +* @return the byte we've read, or Linux specific error code +*/ +static int retriveFromFile(const char *path, u8 *buf, u32 sz) +{ + int ret = -1; + mm_segment_t oldfs; + struct file *fp; + + if (path && buf) { + ret = openFile(&fp, path, O_RDONLY, 0); + if (0 == ret) { + RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); + + oldfs = get_fs(); + set_fs(KERNEL_DS); + ret = readFile(fp, buf, sz); + set_fs(oldfs); + closeFile(fp); + + RTW_INFO("%s readFile, ret:%d\n", __FUNCTION__, ret); + + } else + RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret); + } else { + RTW_INFO("%s NULL pointer\n", __FUNCTION__); + ret = -EINVAL; + } + return ret; +} + +/* +* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file +* @param path the path of the file to open and write +* @param buf the starting address of the data to write into file +* @param sz how many bytes to write at most +* @return the byte we've written, or Linux specific error code +*/ +static int storeToFile(const char *path, u8 *buf, u32 sz) +{ + int ret = 0; + mm_segment_t oldfs; + struct file *fp; + + if (path && buf) { + ret = openFile(&fp, path, O_CREAT | O_WRONLY, 0666); + if (0 == ret) { + RTW_INFO("%s openFile path:%s fp=%p\n", __FUNCTION__, path , fp); + + oldfs = get_fs(); + set_fs(KERNEL_DS); + ret = writeFile(fp, buf, sz); + set_fs(oldfs); + closeFile(fp); + + RTW_INFO("%s writeFile, ret:%d\n", __FUNCTION__, ret); + + } else + RTW_INFO("%s openFile path:%s Fail, ret:%d\n", __FUNCTION__, path, ret); + } else { + RTW_INFO("%s NULL pointer\n", __FUNCTION__); + ret = -EINVAL; + } + return ret; +} + +/* +* Test if the specifi @param path is a file and readable +* @param path the path of the file to test +* @return _TRUE or _FALSE +*/ +int rtw_is_file_readable(const char *path) +{ + if (isFileReadable(path, NULL) == 0) + return _TRUE; + else + return _FALSE; +} + +/* +* Test if the specifi @param path is a file and readable. +* If readable, @param sz is got +* @param path the path of the file to test +* @return _TRUE or _FALSE +*/ +int rtw_is_file_readable_with_size(const char *path, u32 *sz) +{ + if (isFileReadable(path, sz) == 0) + return _TRUE; + else + return _FALSE; +} + +/* +* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most +* @param path the path of the file to open and read +* @param buf the starting address of the buffer to store file content +* @param sz how many bytes to read at most +* @return the byte we've read +*/ +int rtw_retrieve_from_file(const char *path, u8 *buf, u32 sz) +{ + int ret = retriveFromFile(path, buf, sz); + return ret >= 0 ? ret : 0; +} + +/* +* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file +* @param path the path of the file to open and write +* @param buf the starting address of the data to write into file +* @param sz how many bytes to write at most +* @return the byte we've written +*/ +int rtw_store_to_file(const char *path, u8 *buf, u32 sz) +{ + int ret = storeToFile(path, buf, sz); + return ret >= 0 ? ret : 0; +} + +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv) +{ + struct net_device *pnetdev; + struct rtw_netdev_priv_indicator *pnpi; + + pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); + if (!pnetdev) + goto RETURN; + + pnpi = netdev_priv(pnetdev); + pnpi->priv = old_priv; + pnpi->sizeof_priv = sizeof_priv; + +RETURN: + return pnetdev; +} + +struct net_device *rtw_alloc_etherdev(int sizeof_priv) +{ + struct net_device *pnetdev; + struct rtw_netdev_priv_indicator *pnpi; + + pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); + if (!pnetdev) + goto RETURN; + + pnpi = netdev_priv(pnetdev); + + pnpi->priv = rtw_zvmalloc(sizeof_priv); + if (!pnpi->priv) { + free_netdev(pnetdev); + pnetdev = NULL; + goto RETURN; + } + + pnpi->sizeof_priv = sizeof_priv; +RETURN: + return pnetdev; +} + +void rtw_free_netdev(struct net_device *netdev) +{ + struct rtw_netdev_priv_indicator *pnpi; + + if (!netdev) + goto RETURN; + + pnpi = netdev_priv(netdev); + + if (!pnpi->priv) + goto RETURN; + + free_netdev(netdev); + +RETURN: + return; +} + +int rtw_change_ifname(_adapter *padapter, const char *ifname) +{ + struct dvobj_priv *dvobj; + struct net_device *pnetdev; + struct net_device *cur_pnetdev; + struct rereg_nd_name_data *rereg_priv; + int ret; + u8 rtnl_lock_needed; + + if (!padapter) + goto error; + + dvobj = adapter_to_dvobj(padapter); + cur_pnetdev = padapter->pnetdev; + rereg_priv = &padapter->rereg_nd_name_priv; + + /* free the old_pnetdev */ + if (rereg_priv->old_pnetdev) { + free_netdev(rereg_priv->old_pnetdev); + rereg_priv->old_pnetdev = NULL; + } + + rtnl_lock_needed = rtw_rtnl_lock_needed(dvobj); + + if (rtnl_lock_needed) + unregister_netdev(cur_pnetdev); + else + unregister_netdevice(cur_pnetdev); + + rereg_priv->old_pnetdev = cur_pnetdev; + + pnetdev = rtw_init_netdev(padapter); + if (!pnetdev) { + ret = -1; + goto error; + } + + SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter))); + + rtw_init_netdev_name(pnetdev, ifname); + + _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); + + if (rtnl_lock_needed) + ret = register_netdev(pnetdev); + else + ret = register_netdevice(pnetdev); + + if (ret != 0) { + goto error; + } + + return 0; + +error: + + return -1; + +} + + +#ifdef CONFIG_PLATFORM_SPRD + #ifdef do_div + #undef do_div + #endif + #include <asm-generic/div64.h> +#endif + +u64 rtw_modular64(u64 x, u64 y) +{ + return do_div(x, y); +} + +u64 rtw_division64(u64 x, u64 y) +{ + do_div(x, y); + return x; +} + +inline u32 rtw_random32(void) +{ + return prandom_u32(); +} + +void rtw_buf_free(u8 **buf, u32 *buf_len) +{ + u32 ori_len; + + if (!buf || !buf_len) + return; + + ori_len = *buf_len; + + if (*buf) { + u32 tmp_buf_len = *buf_len; + *buf_len = 0; + rtw_mfree(*buf, tmp_buf_len); + *buf = NULL; + } +} + +void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len) +{ + u32 ori_len = 0, dup_len = 0; + u8 *ori = NULL; + u8 *dup = NULL; + + if (!buf || !buf_len) + return; + + if (!src || !src_len) + goto keep_ori; + + /* duplicate src */ + dup = rtw_malloc(src_len); + if (dup) { + dup_len = src_len; + _rtw_memcpy(dup, src, dup_len); + } + +keep_ori: + ori = *buf; + ori_len = *buf_len; + + /* replace buf with dup */ + *buf_len = 0; + *buf = dup; + *buf_len = dup_len; + + /* free ori */ + if (ori && ori_len > 0) + rtw_mfree(ori, ori_len); +} + +/** + * rtw_cbuf_full - test if cbuf is full + * @cbuf: pointer of struct rtw_cbuf + * + * Returns: _TRUE if cbuf is full + */ +inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf) +{ + return (cbuf->write == cbuf->read - 1) ? _TRUE : _FALSE; +} + +/** + * rtw_cbuf_empty - test if cbuf is empty + * @cbuf: pointer of struct rtw_cbuf + * + * Returns: _TRUE if cbuf is empty + */ +inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf) +{ + return (cbuf->write == cbuf->read) ? _TRUE : _FALSE; +} + +/** + * rtw_cbuf_push - push a pointer into cbuf + * @cbuf: pointer of struct rtw_cbuf + * @buf: pointer to push in + * + * Lock free operation, be careful of the use scheme + * Returns: _TRUE push success + */ +bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf) +{ + if (rtw_cbuf_full(cbuf)) + return _FAIL; + + if (0) + RTW_INFO("%s on %u\n", __func__, cbuf->write); + cbuf->bufs[cbuf->write] = buf; + cbuf->write = (cbuf->write + 1) % cbuf->size; + + return _SUCCESS; +} + +/** + * rtw_cbuf_pop - pop a pointer from cbuf + * @cbuf: pointer of struct rtw_cbuf + * + * Lock free operation, be careful of the use scheme + * Returns: pointer popped out + */ +void *rtw_cbuf_pop(struct rtw_cbuf *cbuf) +{ + void *buf; + if (rtw_cbuf_empty(cbuf)) + return NULL; + + if (0) + RTW_INFO("%s on %u\n", __func__, cbuf->read); + buf = cbuf->bufs[cbuf->read]; + cbuf->read = (cbuf->read + 1) % cbuf->size; + + return buf; +} + +/** + * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization + * @size: size of pointer + * + * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure + */ +struct rtw_cbuf *rtw_cbuf_alloc(u32 size) +{ + struct rtw_cbuf *cbuf; + + cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void *) * size); + + if (cbuf) { + cbuf->write = cbuf->read = 0; + cbuf->size = size; + } + + return cbuf; +} + +/** + * rtw_cbuf_free - free the given rtw_cbuf + * @cbuf: pointer of struct rtw_cbuf to free + */ +void rtw_cbuf_free(struct rtw_cbuf *cbuf) +{ + rtw_mfree((u8 *)cbuf, sizeof(*cbuf) + sizeof(void *) * cbuf->size); +} + +/** + * map_readN - read a range of map data + * @map: map to read + * @offset: start address to read + * @len: length to read + * @buf: pointer of buffer to store data read + * + * Returns: _SUCCESS or _FAIL + */ +int map_readN(const struct map_t *map, u16 offset, u16 len, u8 *buf) +{ + const struct map_seg_t *seg; + int ret = _FAIL; + int i; + + if (len == 0) { + rtw_warn_on(1); + goto exit; + } + + if (offset + len > map->len) { + rtw_warn_on(1); + goto exit; + } + + _rtw_memset(buf, map->init_value, len); + + for (i = 0; i < map->seg_num; i++) { + u8 *c_dst, *c_src; + u16 c_len; + + seg = map->segs + i; + if (seg->sa + seg->len <= offset || seg->sa >= offset + len) + continue; + + if (seg->sa >= offset) { + c_dst = buf + (seg->sa - offset); + c_src = seg->c; + if (seg->sa + seg->len <= offset + len) + c_len = seg->len; + else + c_len = offset + len - seg->sa; + } else { + c_dst = buf; + c_src = seg->c + (offset - seg->sa); + if (seg->sa + seg->len >= offset + len) + c_len = len; + else + c_len = seg->sa + seg->len - offset; + } + + _rtw_memcpy(c_dst, c_src, c_len); + } + +exit: + return ret; +} + +/** + * map_read8 - read 1 byte of map data + * @map: map to read + * @offset: address to read + * + * Returns: value of data of specified offset. map.init_value if offset is out of range + */ +u8 map_read8(const struct map_t *map, u16 offset) +{ + const struct map_seg_t *seg; + u8 val = map->init_value; + int i; + + if (offset + 1 > map->len) { + rtw_warn_on(1); + goto exit; + } + + for (i = 0; i < map->seg_num; i++) { + seg = map->segs + i; + if (seg->sa + seg->len <= offset || seg->sa >= offset + 1) + continue; + + val = *(seg->c + offset - seg->sa); + break; + } + +exit: + return val; +} + +/** +* is_null - +* +* Return TRUE if c is null character +* FALSE otherwise. +*/ +inline BOOLEAN is_null(char c) +{ + if (c == '\0') + return _TRUE; + else + return _FALSE; +} + +inline BOOLEAN is_all_null(char *c, int len) +{ + for (; len > 0; len--) + if (c[len - 1] != '\0') + return _FALSE; + + return _TRUE; +} + +/** +* is_eol - +* +* Return TRUE if c is represent for EOL (end of line) +* FALSE otherwise. +*/ +inline BOOLEAN is_eol(char c) +{ + if (c == '\r' || c == '\n') + return _TRUE; + else + return _FALSE; +} + +/** +* is_space - +* +* Return TRUE if c is represent for space +* FALSE otherwise. +*/ +inline BOOLEAN is_space(char c) +{ + if (c == ' ' || c == '\t') + return _TRUE; + else + return _FALSE; +} + +/** +* IsHexDigit - +* +* Return TRUE if chTmp is represent for hex digit +* FALSE otherwise. +*/ +inline BOOLEAN IsHexDigit(char chTmp) +{ + if ((chTmp >= '0' && chTmp <= '9') || + (chTmp >= 'a' && chTmp <= 'f') || + (chTmp >= 'A' && chTmp <= 'F')) + return _TRUE; + else + return _FALSE; +} + +/** +* is_alpha - +* +* Return TRUE if chTmp is represent for alphabet +* FALSE otherwise. +*/ +inline BOOLEAN is_alpha(char chTmp) +{ + if ((chTmp >= 'a' && chTmp <= 'z') || + (chTmp >= 'A' && chTmp <= 'Z')) + return _TRUE; + else + return _FALSE; +} + +inline char alpha_to_upper(char c) +{ + if ((c >= 'a' && c <= 'z')) + c = 'A' + (c - 'a'); + return c; +} -- 2.17.1
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