To avoid people reading this code being very confused, add a comment clarifying the need for invert resets on some chip revisions. Suggested-by: Dan Carpenter <dan.carpenter@xxxxxxxxxx> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx> --- drivers/staging/mt7621-pci/pci-mt7621.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index c5e33fbdf225..31310b6fb7db 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -589,6 +589,10 @@ static int mt7621_pcie_init_port(struct mt7621_pcie_port *port) u32 slot = port->slot; u32 val = 0; + /* + * Any MT7621 Ralink pcie controller that doesn't have 0x0101 at + * the end of the chip_id has inverted PCI resets. + */ mt7621_reset_port(port); val = read_config(pcie, slot, PCIE_FTS_NUM); -- 2.19.1 _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
