On Mon, Aug 13, 2018 at 06:09:46PM +0300, Dmitry Osipenko wrote: > On Monday, 13 August 2018 17:50:14 MSK Thierry Reding wrote: > > From: Thierry Reding <treding@xxxxxxxxxx> > > > > The BSEV clock has a separate gate bit and can not be assumed to be > > always enabled. Add explicit handling for the BSEV clock and reset. > > > > This fixes an issue on Tegra124 where the BSEV clock is not enabled > > by default and therefore accessing the BSEV registers will hang the > > CPU if the BSEV clock is not enabled and the reset not deasserted. > > > > Signed-off-by: Thierry Reding <treding@xxxxxxxxxx> > > --- > > Are you sure that BSEV clock is really needed for T20/30? I've tried already > to disable the clock explicitly and everything kept working, though I'll try > again. I think you're right that these aren't strictly required for VDE to work on Tegra20 and Tegra30. However, the BSEV clock and reset do exist on those platforms, so I didn't see a reason why they shouldn't be handled uniformly across all generations. > The device-tree changes should be reflected in the binding documentation. Indeed, I forgot to update that. Thierry
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