On Sun, Jul 22, 2018 at 09:27:37PM -0400, Jacob Feder wrote: > This IP core has read and write AXI-Stream FIFOs, the contents of which can > be accessed from the AXI4 memory-mapped interface. This is useful for > transferring data from a processor into the FPGA fabric. The driver creates > a character device that can be read/written to with standard > open/read/write/close. > > See Xilinx PG080 document for IP details. > > https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf > > The driver currently supports only store-forward mode with a 32-bit > AXI4 Lite interface. DOES NOT support: > - cut-through mode > - AXI4 (non-lite) > > Signed-off-by: Jacob Feder <jacobsfeder@xxxxxxxxx> > --- Looks good, now applied to my tree, let's see what happens! :) greg k-h _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
