On Wed, 18 Jul 2018 22:46:34 -0400
Jacob Feder <jacobsfeder@xxxxxxxxx> wrote:
> +MODULE_DESCRIPTION("Xilinx AXI-Stream FIFO v4.1 IP core driver\n\n"
> +"This IP core has read and write AXI-Stream FIFOs, the contents of which can\n"
> +"be accessed from the AXI4 memory-mapped interface. This is useful for\n"
> +"transferring data from a processor into the FPGA fabric. The driver creates\n"
> +"a character device that can be read/written to with standard\n"
> +"open/read/write/close.\n\n"
> +"See Xilinx PG080 document for IP details.\n"
> +"https://www.xilinx.com/support/documentation/ip_documentation/axi_fifo_mm_s/v4_1/pg080-axi-fifo-mm-s.pdf\n\n";
> +"The driver currently supports only store-forward mode with a 32-bit\n"
> +"AXI4 Lite interface. DOES NOT support:\n"
> +" - cut-through mode\n"
> +" - AXI4 (non-lite)");
One line for MODULE_DESCRIPTION it is for the modinfo tool, not marketing or documentation.
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