On Mon, May 07, 2018 at 11:20:26AM +1000, James Kelly wrote: > This series of patches attempts to implement many of the outstanding TODOs > for the Xilinx Clocking Wizard IP driver that has been languishing in the > staging tree for some time. I had a need for this driver so I thought it > appropriate to give it some love. Hopefully others will find these patches > useful. > > Highlights include: > - Support for fractional ratios when available in hardware. > - Support for clk_round_rate and clk_set_rate kernel APIs. > - Automatic set rate of internal clocks when rate of output clock is set. > - Automatic set rate of input clock and internal clocks when rate of > output clock is set. > > A CCF clock provider has been implemented within the driver to support > the new functionality as it was not possible to do this with the existing > clock providers. There is also code to handle a limitation of Clocking > Wizard IP which prevents changes to the clock ratios if the PLL is not > locked. Great care has to be taken to ensure the PLL will always lock as > there is no way for the driver to recover if the PLL fails to lock under > transient conditions that may drive the PLL VCO frequency out of range. > > The patches were built on the current staging-next branch. > > The patches also work with the xlnx_rebase_v4.14 branch of the Xilinx > linux tree at https://github.com/Xilinx/linux-xlnx.git - this branch is > used by the current release (2018.1) of the Xilinx development tools. > Patches corresponding to the following staging tree commits are required as > prerequisites before applying this patch series to xlnx_rebase_v4.14: > > 667063acb81931e2f8fd0cb91df9fcccad131d9a > regmap: add iopoll-like polling macro for regmap_field > 1dbb3344d9e9cd6e72da23f4058f3e6e926614b6 > staging: clocking-wizard: add SPDX identifier > 09956d59bad5f5bb238efb805f0767060e624378 > staging: clocking-wizard: remove redundant license text > a08f06bb7a0743a7fc8d571899c93d882468096e > seq_file: Introduce DEFINE_SHOW_ATTRIBUTE() helper macro > > Testing has been done on a Digilent Zybo-Z7 development board. This uses a > 32-bit ARM architecture Zynq-7020 SoC. Testing used the 2018.1 release of > the Xilinx development tools which has v6.0 of the Clocking Wizard IP. > > The patches are also applicable to, but are currently untested on: > - 64-bit ARM architecture (Zynq Ultrascale+ MPSoC etc.) > - Microblaze architecture (7-Series, Ultrascale, Ultrascale+ FPGAs) > Others with access to suitable hardware will need to test these platforms. > > Potential users of this driver may use the Xilinx device tree generator > from https://github.com/Xilinx/device-tree-xlnx.git either directly or via > the development tools provided by Xilinx. There are two issues with the > DTG that any potential testers of these patches should be aware of: > - The DTG generates a negative value for the device-tree speed-grade > property. The 7th patch has a hack to handle this quirk until Xilinx > fix their DTG. > - The 2018.1 DTG changed the device-tree clock-output-names property so > it no longer provides any information about how the Clocking Wizard IP > is actually configured. These patches will still work with the new > 2018.1 DTG behaviour but the names of the output clocks will no longer > match those used in the Clocking Wizard IP customization, and the > maximum number of clocks will always be created even if not used or > FPGA. A warning will also be issued stating that there are too many > clock output names. Further details can be found in the Xilinx Community > forums at https://bit.ly/2jmFIRf. > > The original driver author appears to have left Xilinx so I have not > included them as an addressee for these patches and instead directed > them to another Xilinx Linux maintainer. Can you please fix up the issues reported in this series, rebase on my latest tree, and resend so that I can apply them? thanks, greg k-h _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
