On 7.5.2018 03:20, James Kelly wrote: > Provide initial support for CCF clk_set_rate API on all clock components. > > Clock consumers that want to set the first divider or PLL clock will need > to use clk_get_parent on one of the output clocks as there is no support > for CLK_SET_RATE_PARENT yet. > > Care must be taken when setting the first divider clock to ensure that > the PLL clock rate will remain within a valid range for the VCO, as it > is impossible to subsequently update any clock if the PLL does not lock. > A subsequent patch will address this issue. > > Signed-off-by: James Kelly <jamespeterkelly@xxxxxxxxx> > --- > drivers/staging/clocking-wizard/TODO | 4 +- > .../clocking-wizard/clk-xlnx-clock-wizard.c | 115 +++++++++++++++++++++ > 2 files changed, 117 insertions(+), 2 deletions(-) > > diff --git a/drivers/staging/clocking-wizard/TODO b/drivers/staging/clocking-wizard/TODO > index 53c9941fcc35..50193bdd61e1 100644 > --- a/drivers/staging/clocking-wizard/TODO > +++ b/drivers/staging/clocking-wizard/TODO > @@ -1,8 +1,8 @@ > TODO: > - - support for set_rate() operations (may benefit from Stephen Boyd's > - refactoring of the clk primitives: https://lkml.org/lkml/2014/9/5/766) > - review arithmetic > - overflow after multiplication? > + - implement CLK_SET_RATE_PARENT to set internal clocks > + - implement CLK_SET_RATE_PARENT to set input clock > - test on 64-bit ARM and Microblaze architectures. > - support clk_set_phase > > diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c > index 8828dac6faaf..455ee9887c77 100644 > --- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c > +++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c > @@ -76,6 +76,7 @@ > #define KHz 1000UL > #define MHz 1000000UL > #define WZRD_ACLK_MAX_FREQ (250 * MHz) > +#define WZRD_PLL_LOCK_TIMEOUT 1000 // usec > #define WZRD_FRAC_BITS 3 > #define WZRD_FRAC_MASK (BIT(WZRD_FRAC_BITS) - 1) > #define WZRD_FRAC_SCALE (1000 >> WZRD_FRAC_BITS) > @@ -85,6 +86,8 @@ > #define WZRD_FLAG_FRAC BIT(1) > #define WZRD_FLAG_ADJUST_MIN BIT(2) > > +struct clk_wzrd; > + > /* > * Clock rate constraints extracted from Xilinx data sheets listed below. > * The minimum rates depend on family and clock type and the maximum rates > @@ -310,6 +313,7 @@ static const struct reg_field clk_wzrd_reconfig = REG_FIELD(0x25C, 0, 1); > * > * @hw: handle between common and hardware-specific interfaces > * @flags: hardware specific flags > + * @cw; pointer to platform device data s/;/:/ M _______________________________________________ devel mailing list devel@xxxxxxxxxxxxxxxxxxxxxx http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel
