Introduction
============
On some Intel processors [1] a microcode update will always abort
Transactional Synchronization Extensions (TSX) transactions by default. These
CPUs were previously affected by the TSX memory ordering issue [2]. A
workaround was earlier added to perf related to memory ordering which is no
longer required(because TSX is defeatured on these systems). This series adds
support for new bits added to TSX_FORCE_ABORT MSR and CPUID to enumerate new
abort behavior and to bypass the workaround.
Roadmap to this series
======================
0001: Define new CPUID and MSR bits that are added by the microcode update.
(The new CPUID.RTM_ALWAYS_ABORT is not shown in /proc/cpuinfo)
0002: When new microcode is enumerated bypass perf counter workaround for [1].
Perf workaround is no longer required after the microcode update.
0003: Clear CPUID.RTM and CPUID.HLE when TSX is defeatured, so that software
does not enumerate and try to use TSX.
0004: Add tsx=fake cmdline option to not hide CPUID.RTM and CPUID.HLE. This
may be desirable when resuming saved guest image that require RTM and HLE
feature bits to be present.
Thanks,
Pawan
[1] Intel® TSX Memory and Performance Monitoring Update for Intel® Processors
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html
[2] Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory
http://cdrdv2.intel.com/v1/dl/getContent/604224
Pawan Gupta (4):
x86/msr: Define new bits in TSX_FORCE_ABORT MSR
perf/x86/intel: Do not deploy workaround when TSX is deprecated
x86/tsx: Clear CPUID bits when TSX always force aborts
x86/tsx: Add cmdline tsx=fake to not clear CPUID bits RTM and HLE
Documentation/admin-guide/kernel-parameters.txt | 3 +-
arch/x86/events/intel/core.c | 22 +++++++--
arch/x86/include/asm/cpufeatures.h | 1 +-
arch/x86/include/asm/msr-index.h | 4 ++-
arch/x86/kernel/cpu/bugs.c | 5 +-
arch/x86/kernel/cpu/cpu.h | 3 +-
arch/x86/kernel/cpu/intel.c | 4 +-
arch/x86/kernel/cpu/tsx.c | 44 ++++++++++++++++--
8 files changed, 75 insertions(+), 11 deletions(-)
base-commit: 614124bea77e452aa6df7a8714e8bc820b489922
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git-series 0.9.1
