On Sun, Mar 28, 2021 at 10:37 PM Max Filippov <jcmvbkbc@xxxxxxxxx> wrote: > > On Sun, Mar 28, 2021 at 10:18 PM Bhaskar Chowdhury > <unixbhaskar@xxxxxxxxx> wrote: > > > > s/controlers/controllers/ > > > > Signed-off-by: Bhaskar Chowdhury <unixbhaskar@xxxxxxxxx> > > --- > > Documentation/xtensa/atomctl.rst | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/Documentation/xtensa/atomctl.rst b/Documentation/xtensa/atomctl.rst > > index 1ecbd0ba9a2e..a0efab2abe8f 100644 > > --- a/Documentation/xtensa/atomctl.rst > > +++ b/Documentation/xtensa/atomctl.rst > > @@ -23,7 +23,7 @@ doing a Cached (WB) transaction and use the Memory RCW for un-cached > > operations. > > > > For systems without an coherent cache controller, non-MX, we always > > -use the memory controllers RCW, thought non-MX controlers likely > > +use the memory controllers RCW, thought non-MX controllers likely > > In this line you could also do s/thought/though/. ...and s/memory controllers/memory controller's/ -- Thanks. -- Max
