On Thu, Dec 31, 2020 at 03:29:38PM +0100, Paul Kocialkowski wrote: > Bits related to the interface data width are only applicable to the > parallel interface and are irrelevant when the CSI controller is taking > input from the MIPI CSI-2 controller. > > In prevision of adding support for this case, set these bits > conditionally so there is no ambiguity. The conditional block is > moved around before the interlaced conditional block for nicer code > symmetry (conditional blocks first) while at it. > > Co-developed-by: Kévin L'hôpital <kevin.lhopital@xxxxxxxxxxx> > Signed-off-by: Kévin L'hôpital <kevin.lhopital@xxxxxxxxxxx> > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@xxxxxxxxxxx> Acked-by: Maxime Ripard <mripard@xxxxxxxxxx> Thanks! Maxime
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