Hi Doug, On Tue, Aug 4, 2020 at 7:07 PM Doug Smythies <dsmythies@xxxxxxxxx> wrote: > > Hi Rafael, > > I was just writing you about V5 when this V6 came. > > On 2020.08.04 08:11 Rafael J. Wysocki wrote: > ... > > This is on top of the material already in the mainline. > > Oh, should have read that part better, > but did get there in the end. > ... > > v5 -> v6: > > * Fix the problem with the EPP setting via sysfs not working with the > > performance and powersave governors by stopping and restarting the > > governor around the sysfs-based EPP updates in the passive mode. > > * Because of that, use the epp_cached field just for avoiding the above > > if the new EPP value for the given CPU is the same as the old one. > > * Export cpufreq_start/stop_governor() from the core (for the above). > > EPP is still not right. > I am not messing with it at all, just observing via my msr-decoder. If you are not touching it, then it should not change in the passive mode. > I booted without any intel_pstate related directives for the > kernel command line. The below is as expected (performance gov.): Note that the active mode performance scaling algorithm (which is not the same as the performance cpufreq governor) sets the EPP to 0 for all of the CPUs that it is used with and the driver sets the EPP to 255 in ->stop_cpu. That last bit is questionable, but that's the active mode behavior which is not changed by the $subject patch. It would be more reasonable to restore the previous EPP when stopping CPUs. Let me cut a v7 with that changed. > # /home/doug/c/msr-decoder > How many CPUs?: 6 > 8.) 0x198: IA32_PERF_STATUS : CPU 0-5 : 46 : 46 : 46 : 46 : 46 : 46 : > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable > 1.) 0x19C: IA32_THERM_STATUS: 88450000 > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination enabled OOB Bit 8 reset OOB Bit 18 reset > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 88430000 > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0 > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO disable > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 109252E : high 46 : guaranteed 37 : efficient 9 : lowest 1 > 6.) 0x774: IA32_HWP_REQUEST: CPU 0-5 : > raw: 00002E2E : 00002E2E : 00002E2E : 00002E2E : 00002E2E : 00002E2E : > min: 46 : 46 : 46 : 46 : 46 : 46 : > max: 46 : 46 : 46 : 46 : 46 : 46 : > des: 0 : 0 : 0 : 0 : 0 : 0 : > epp: 0 : 0 : 0 : 0 : 0 : 0 : > act: 0 : 0 : 0 : 0 : 0 : 0 : > 7.) 0x777: IA32_HWP_STATUS: 4 : high 4 : guaranteed 0 : efficient 0 : lowest 0 > > and then switched to passive mode later. EPP is not as expected. Expect 0 > (performance mode): > > # /home/doug/c/msr-decoder > How many CPUs?: 6 > 8.) 0x198: IA32_PERF_STATUS : CPU 0-5 : 46 : 46 : 46 : 46 : 46 : 46 : > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable > 1.) 0x19C: IA32_THERM_STATUS: 88440000 > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination enabled OOB Bit 8 reset OOB Bit 18 reset > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 88420000 > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0 > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO disable > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 108252E : high 46 : guaranteed 37 : efficient 8 : lowest 1 > 6.) 0x774: IA32_HWP_REQUEST: CPU 0-5 : > raw: FF002E2E : FF002E2E : FF002E2E : FF002E2E : FF002E2E : FF002E2E : > min: 46 : 46 : 46 : 46 : 46 : 46 : > max: 46 : 46 : 46 : 46 : 46 : 46 : > des: 0 : 0 : 0 : 0 : 0 : 0 : > epp: 255 : 255 : 255 : 255 : 255 : 255 : > act: 0 : 0 : 0 : 0 : 0 : 0 : > 7.) 0x777: IA32_HWP_STATUS: 4 : high 4 : guaranteed 0 : efficient 0 : lowest 0 The 0xFF EPP value is what the active mode left behind and the passive mode doesn't touch the EPP at all. > Then switched to ondemand governor, and put 100% load on 2 CPUs. > EPP is not as expected, which I don't actually know what to expect, > but assume 128: > > # /home/doug/c/msr-decoder > How many CPUs?: 6 > 8.) 0x198: IA32_PERF_STATUS : CPU 0-5 : 46 : 46 : 46 : 46 : 46 : 46 : > B.) 0x770: IA32_PM_ENABLE: 1 : HWP enable > 1.) 0x19C: IA32_THERM_STATUS: 883B0000 > 2.) 0x1AA: MSR_MISC_PWR_MGMT: 401CC0 EIST enabled Coordination enabled OOB Bit 8 reset OOB Bit 18 reset > 3.) 0x1B1: IA32_PACKAGE_THERM_STATUS: 882B0000 > 4.) 0x64F: MSR_CORE_PERF_LIMIT_REASONS: 0 > A.) 0x1FC: MSR_POWER_CTL: 3C005D : C1E disable : EEO disable : RHO disable > 5.) 0x771: IA32_HWP_CAPABILITIES (performance): 10B252E : high 46 : guaranteed 37 : efficient 11 : lowest 1 > 6.) 0x774: IA32_HWP_REQUEST: CPU 0-5 : > raw: FF002E09 : FF002E0C : FF002E2E : FF002E08 : FF002E2E : FF002E18 : > min: 9 : 12 : 46 : 8 : 46 : 24 : > max: 46 : 46 : 46 : 46 : 46 : 46 : > des: 0 : 0 : 0 : 0 : 0 : 0 : > epp: 255 : 255 : 255 : 255 : 255 : 255 : > act: 0 : 0 : 0 : 0 : 0 : 0 : > 7.) 0x777: IA32_HWP_STATUS: 4 : high 4 : guaranteed 0 : efficient 0 : lowest 0 It is still 0xFF as previously (because the passive mode doesn't change the EPP). > For what it's worth, Kernel: > > 78b39581ed85 (HEAD -> dtemp) cpufreq: intel_pstate: Implement passive mode with HWP enabled > c0842fbc1b18 (origin/master, origin/HEAD, master) random32: move the pseudo-random 32-bit definitions to prandom.h > 2baa85d6927d Merge tag 'acpi-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm > 04084978003c Merge tag 'pm-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Thanks!
