> -----Original Message----- > From: Andrew Lunn <andrew@xxxxxxx> > Sent: Friday, January 3, 2020 6:48 PM > To: Madalin Bucur (OSS) <madalin.bucur@xxxxxxxxxxx> > Cc: Russell King - ARM Linux admin <linux@xxxxxxxxxxxxxxx>; Florian > Fainelli <f.fainelli@xxxxxxxxx>; Heiner Kallweit <hkallweit1@xxxxxxxxx>; > David S. Miller <davem@xxxxxxxxxxxxx>; Jonathan Corbet <corbet@xxxxxxx>; > Kishon Vijay Abraham I <kishon@xxxxxx>; linux-doc@xxxxxxxxxxxxxxx; > netdev@xxxxxxxxxxxxxxx > Subject: Re: [PATCH net-next 0/2] Fix 10G PHY interface types > > > And here is a LS1046A SoC document that describes XFI and 10GBASE_KR: > > > > https://www.mouser.com/pdfdocs/LS1046A.pdf You need to register, unfortunately, but the information is in the reference manual (18.3 MB of download): https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1046a-and-1026a-multicore-communications-processors:LS1046A?tab=Documentation_Tab You can find there also an application note on the backplane ethernet support on this device, with a description of the current solution, describing the SoC internal PCS (manageable through an MDIO bus) as a PHY to be able to use the PHYlib infrastructure to control it. The code is still under refinement, not upstream yet, but it's available and in use by customers. > I don't see any register descriptions here. So you failed to answer my > question. What do you actually need to configure? What needs to go > into DT? > > You keep avoiding the questions Russell and I pose, which is not > helping your argument. We need details, not hand waiving. > > Andrew Answers are there, spreading the conversation on multiple threads and removing history is not helping. Madalin
