From: Kedareswara rao Appana <appana.durga.rao@xxxxxxxxxx> This patch adds the documentaion for the sysfs entries in the driver. Signed-off-by: Kedareswara rao Appana <appana.durga.rao@xxxxxxxxxx> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xxxxxxxxxx> --- Documentation/misc-devices/xilinx_trafgen.txt | 97 +++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/misc-devices/xilinx_trafgen.txt diff --git a/Documentation/misc-devices/xilinx_trafgen.txt b/Documentation/misc-devices/xilinx_trafgen.txt new file mode 100644 index 0000000..dadcdad --- /dev/null +++ b/Documentation/misc-devices/xilinx_trafgen.txt @@ -0,0 +1,97 @@ +Kernel driver xilinx_trafgen +============================ + +Supported chips: +Zynq SOC, Xilinx 7 series fpga's (Virtex,Kintex,Artix) + +Data Sheet: + http://www.xilinx.com/support/documentation/ip_documentation/axi_traffic_gen/v2_0/pg125-axi-traffic-gen.pdf + +Author: + Kedareswara Rao Appana <appanad@xxxxxxxxxx> + +Description +----------- + +AXI Traffic Generator IP is a core that stresses the AXI4 interconnect and other +AXI4 peripherals in the system. It generates a wide variety of AXI4 transactions +based on the core programming. + +Features: +---> Configurable option to generate and accept data according to different +traffic profiles. +---> Supports dependent/independent transaction between read/write master port +with configurable delays. +---> Programmable repeat count for each transaction with +constant/increment/random address. +---> External start/stop to generate traffic without processor intervention. +---> Generates IP-specific traffic on AXI interface for pre-defined protocols. + +SYSFS: + +id + RO - shows the trafgen id. + +resource + RO - shows the baseaddress for the trafgen. + +master_start_stop + RW - monitors the master start logic. + +config_slave_status + RW - configure and monitors the slave status. + +err_sts + RW - get the error statistics/clear the errors. + +err_en + WO - enable the errors. + +intr_en + WO - enable the interrupts. + +last_valid_index + RW - gets the last valid index value. + +config_sts_show + RO - show the config status value. + +mram_clear + WO - clears the master ram. + +cram_clear + WO - clears the command ram. + +pram_clear + WO - clears the parameter ram. + +static_enable + RO - enables the static mode. + +static_burst_len + RW - gets/sets the static burst length. + +static_transferdone + RW - monitors the static transfer done status. + +reset_static_transferdone + RO - resets the static transferdone bit. + +stream_cfg + RW - sets the stream configuration parameters like delay. + +stream_tktsn + RW - TSTRB/TKEEP value for the last beat of the +transfer set n. N can be 1 to 4. + +stream_enable + RO - enables the streaming mode. + +stream_transferlen + RW - get/set the streaming mode transfer length. + +stream_transfercnt + RW - get/set the streaming mode transfer count. + +loop_enable + RW - get/set loop enable value. -- 2.1.1
