On Mon, 07 May 2018, Andrea Parri <andrea.parri@xxxxxxxxxxxxxxxxxxxx> wrote:
> On Mon, May 07, 2018 at 06:35:41AM -0300, Mauro Carvalho Chehab wrote:
>> The cachetlb.txt is already in ReST format. So, move it to the
>> core-api guide, where it belongs.
>>
>> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@xxxxxxxxxx>
>> ---
>> Documentation/00-INDEX | 2 --
>> Documentation/{cachetlb.txt => core-api/cachetlb.rst} | 0
>> Documentation/core-api/index.rst | 1 +
>> Documentation/memory-barriers.txt | 2 +-
>> Documentation/translations/ko_KR/memory-barriers.txt | 2 +-
>> 5 files changed, 3 insertions(+), 4 deletions(-)
>> rename Documentation/{cachetlb.txt => core-api/cachetlb.rst} (100%)
>
> I see a few "inline" references to the .txt file in -rc4 (see below):
> I am not sure if you managed to update them too.
Side note, there's scripts/documentation-file-ref-check to grep the
kernel tree for things that look like file references to Documentation/*
and complain if they don't exist.
I get about 350+ hits with that, patches welcome! ;)
BR,
Jani.
>
> ./arch/microblaze/include/asm/cacheflush.h:/* Look at Documentation/cachetlb.txt */
> ./arch/unicore32/include/asm/cacheflush.h: * See Documentation/cachetlb.txt for more information.
> ./arch/arm64/include/asm/cacheflush.h: * See Documentation/cachetlb.txt for more information. Please note that
> ./arch/arm/include/asm/cacheflush.h: * See Documentation/cachetlb.txt for more information.
> ./arch/xtensa/include/asm/cacheflush.h: * (see also Documentation/cachetlb.txt)
> ./arch/xtensa/include/asm/cacheflush.h:/* This is not required, see Documentation/cachetlb.txt */
>
> Andrea
>
>
>>
>> diff --git a/Documentation/00-INDEX b/Documentation/00-INDEX
>> index 53699c79ee54..04074059bcdc 100644
>> --- a/Documentation/00-INDEX
>> +++ b/Documentation/00-INDEX
>> @@ -76,8 +76,6 @@ bus-devices/
>> - directory with info on TI GPMC (General Purpose Memory Controller)
>> bus-virt-phys-mapping.txt
>> - how to access I/O mapped memory from within device drivers.
>> -cachetlb.txt
>> - - describes the cache/TLB flushing interfaces Linux uses.
>> cdrom/
>> - directory with information on the CD-ROM drivers that Linux has.
>> cgroup-v1/
>> diff --git a/Documentation/cachetlb.txt b/Documentation/core-api/cachetlb.rst
>> similarity index 100%
>> rename from Documentation/cachetlb.txt
>> rename to Documentation/core-api/cachetlb.rst
>> diff --git a/Documentation/core-api/index.rst b/Documentation/core-api/index.rst
>> index c670a8031786..d4d71ee564ae 100644
>> --- a/Documentation/core-api/index.rst
>> +++ b/Documentation/core-api/index.rst
>> @@ -14,6 +14,7 @@ Core utilities
>> kernel-api
>> assoc_array
>> atomic_ops
>> + cachetlb
>> refcount-vs-atomic
>> cpu_hotplug
>> idr
>> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
>> index 6dafc8085acc..983249906fc6 100644
>> --- a/Documentation/memory-barriers.txt
>> +++ b/Documentation/memory-barriers.txt
>> @@ -2903,7 +2903,7 @@ is discarded from the CPU's cache and reloaded. To deal with this, the
>> appropriate part of the kernel must invalidate the overlapping bits of the
>> cache on each CPU.
>>
>> -See Documentation/cachetlb.txt for more information on cache management.
>> +See Documentation/core-api/cachetlb.rst for more information on cache management.
>>
>>
>> CACHE COHERENCY VS MMIO
>> diff --git a/Documentation/translations/ko_KR/memory-barriers.txt b/Documentation/translations/ko_KR/memory-barriers.txt
>> index 0a0930ab4156..081937577c1a 100644
>> --- a/Documentation/translations/ko_KR/memory-barriers.txt
>> +++ b/Documentation/translations/ko_KR/memory-barriers.txt
>> @@ -2846,7 +2846,7 @@ CPU 의 캐시에서 RAM 으로 쓰여지는 더티 캐시 라인에 의해 덮
>> 문제를 해결하기 위해선, 커널의 적절한 부분에서 각 CPU 의 캐시 안의 문제가 되는
>> 비트들을 무효화 시켜야 합니다.
>>
>> -캐시 관리에 대한 더 많은 정보를 위해선 Documentation/cachetlb.txt 를
>> +캐시 관리에 대한 더 많은 정보를 위해선 Documentation/core-api/cachetlb.rst 를
>> 참고하세요.
>>
>>
>> --
>> 2.17.0
>>
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--
Jani Nikula, Intel Open Source Technology Center
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