Hi Andy,
On 28.05.2017 01:28, Andy Shevchenko wrote:
> On Tue, May 9, 2017 at 11:19 AM, Claudiu Beznea
> <claudiu.beznea@xxxxxxxxxxxxx> wrote:
>> Extends PWM framework to support PWM dead-times.
>> The notions introduced are rising edge dead-time
>> and falling edge dead-time. These are useful for
>> PWM controllers with channels that have more than
>> one outputs.
>> The implementation add sysfs interface for
>> configuration. It extends the pwm_state structure
>> with two new members which keeps the values for
>> dead-times.
>> There were no additions in device tree for PWM channels
>> initialized by device tree.
>
> AFAIU it's effectively called phase of the signal.
It is actually a delay introduce by the PWM controller
between it's outputs. As I said in cover letter, for
PWM controllers with 2 output signals per channel
(these signals are on different physical pins), this
dead-time is the delay introduced b/w these two outputs.
The term is a PWM literature specific.
These delays are useful when PWM drives a half bridge
converter where you need delays b/w positive edges of
the signals which drivers the transistors to avoid
shoot through scenarios.
> It looks to me much simpler if you allow to have linked / virtual
> channels instead of creating a lot of (duplicated) properties.My linked channels (the 2 outputs per PWM channel) are PWM controller
specifics. The standard output of these linked channels is as
follows:
__ __ __ __
channel Xa __| |__| |__| |__| |__
__ __ __ __ __
channel Xb |__| |__| |__| |__|
<--T-->
This is the default output. To be able to use the controller
in applications which needs delays b/w the fronts of this outputs
I introduced the dead-time configuration. This allow the user
to set it's PWM output as he needs in his setup (these dead-times,
delays, if PWM is used e.g. in half bridge converters, depends
on the transistors used).
Thank you,
Claudiu Beznea
>
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