On Wed, Apr 27, 2016 at 8:05 AM, Tom Lendacky <thomas.lendacky@xxxxxxx> wrote: > On 04/27/2016 09:47 AM, Andy Lutomirski wrote: >> On Wed, Apr 27, 2016 at 7:44 AM, Tom Lendacky <thomas.lendacky@xxxxxxx> wrote: >>> On 04/27/2016 09:33 AM, Andy Lutomirski wrote: >>>> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky <thomas.lendacky@xxxxxxx> wrote: >>>>> For AMD processors that support PAT, set the write-protect cache mode >>>>> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). >>>> >>>> What's the purpose of using the WP memory type? >>> >>> The WP memory type is used for encrypting or decrypting data "in place". >>> The use of the WP on the source data will prevent any of the source >>> data from being cached. Refer to section 7.10.8 "Encrypt-in-Place" in >>> the AMD64 APM link provided in the cover letter. >>> >>> This memory type will be used in subsequent patches for this purpose. >> >> OK. >> >> Why AMD-only? I thought Intel supported WP, too. > > Just me being conservative. If there aren't any objections from the > Intel folks about it we can remove the vendor check and just set it. I think there are some errata that will cause high PAT references to incorrectly reference the low parts of the table, but I don't recall any that go the other way around. So merely setting WP in a high entry should be harmless unless something tries to use it. > > Thanks, > Tom > >> >> --Andy >> -- Andy Lutomirski AMA Capital Management, LLC -- To unsubscribe from this list: send the line "unsubscribe linux-doc" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
