> Hi Hidehiro, > > [auto build test results on v4.3-rc2 -- if it's inappropriate base, please ignore] > > config: ia64-allyesconfig (attached as .config) > reproduce: > wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > git checkout 0077681103150af584e5e592c0238fd010654c26 > # save the attached .config to linux build tree > make.cross ARCH=ia64 [snip] > arch/ia64/include/uapi/asm/cmpxchg.h:56:2: warning: value computed is not used [-Wunused-value] > ((__typeof__(*(ptr))) __xchg((unsigned long) (x), (ptr), sizeof(*(ptr)))) > ^ > arch/ia64/include/asm/atomic.h:135:30: note: in expansion of macro 'xchg' > #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) > ^ > >> kernel/kexec_core.c:899:3: note: in expansion of macro 'atomic_xchg' > atomic_xchg(&panic_cpu, -1); > ^ I changed to use atomic_xchg() instead of atomic_set() in V3 because atomic_set() doesn't mean memory barrier. However, I thought again and there is no need of barrier; there is no problem if a competitor sees old value of panic_cpu or new one. So, atomic_set() is sufficient and using it will remove this warning. I will resend the fixed version later. > vim +/atomic_xchg +899 kernel/kexec_core.c > > 883 > 884 /* > 885 * Only one CPU is allowed to execute the crash_kexec() code as with > 886 * panic(). Otherwise parallel calls of panic() and crash_kexec() > 887 * may stop each other. To exclude them, we use panic_cpu here too. > 888 */ > 889 this_cpu = raw_smp_processor_id(); > 890 old_cpu = atomic_cmpxchg(&panic_cpu, -1, this_cpu); > 891 if (old_cpu == -1) { > 892 /* This is the 1st CPU which comes here, so go ahead. */ > 893 __crash_kexec(regs); > 894 > 895 /* > 896 * Reset panic_cpu to allow another panic()/crash_kexec() > 897 * call. > 898 */ > > 899 atomic_xchg(&panic_cpu, -1); > 900 } > 901 } > 902 > 903 size_t crash_get_memory_size(void) > 904 { > 905 size_t size = 0; > 906 > 907 mutex_lock(&kexec_mutex); > > --- > 0-DAY kernel test infrastructure Open Source Technology Center > https://lists.01.org/pipermail/kbuild-all Intel Corporation Hidehiro Kawai Hitachi, Ltd. Research & Development Group ��.n��������+%������w��{.n�����{����* jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
