On Thu, Jun 04, 2015 at 09:28:44AM -0500, tthayer@xxxxxxxxxxxxxxxxxxxxx wrote:
> From: Thor Thayer <tthayer@xxxxxxxxxxxxxxxxxxxxx>
>
> This series of patches adds support for the Arria10 EDAC. The
> SDRAM controller and ECC registers are significantly different
> from the CycloneV/ArriaV but common areas could be abstracted.
>
> Thor Thayer (4):
> edac, altera: Generalize driver to use DT Memory size
> edac, altera: Refactor EDAC for Altera CycloneV SoC.
> edac, altera: Addition of Arria10 EDAC
> arm: socfpga: dts: Arria10 SDRAM EDAC DTS additions.
>
> .../bindings/arm/altera/socfpga-sdram-edac.txt | 2 +-
> arch/arm/boot/dts/socfpga_arria10.dtsi | 11 +
> drivers/edac/altera_edac.c | 364 ++++++++++++--------
> drivers/edac/altera_edac.h | 201 +++++++++++
> 4 files changed, 437 insertions(+), 141 deletions(-)
> create mode 100644 drivers/edac/altera_edac.h
Ok, all applied, no need to redo them.
altera_edac still builds ok with the cross compiler here but you should
doublecheck my final result just in case:
git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git#for-next
Thanks.
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.
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