On Tue, Apr 28, 2015 at 9:08 PM, Ben Shelton <ben.shelton@xxxxxx> wrote:
> Hi Punnaiah,
>
> On 04/13, Punnaiah Choudary Kalluri wrote:
>> Add driver for arm pl353 static memory controller nand interface with
>> HW ECC support. This controller is used in xilinx zynq soc for interfacing
>> the nand flash memory.
>>
>> Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xxxxxxxxxx>
>
> [...]
>
>> +
>> +static int pl353_nand_init_timing(struct device *dev, int mode)
>> +{
>> + const struct nand_sdr_timings *time;
>> + u32 t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr;
>> + ulong clkrate;
>> +
>> + time = onfi_async_timing_mode_to_sdr_timings(mode);
>> + if (IS_ERR(time))
>> + return PTR_ERR(time);
>> +
>> + clkrate = pl353_smc_get_clkrate(dev);
>> + t_rc = get_cyc_from_ns(clkrate, time->tRC_min / 1000);
>> + t_wc = get_cyc_from_ns(clkrate, time->tWC_min / 1000);
>> + t_rea = get_cyc_from_ns(clkrate, time->tREA_max / 1000);
>> + t_wp = get_cyc_from_ns(clkrate, time->tWP_min / 1000);
>> + t_clr = get_cyc_from_ns(clkrate, time->tCLR_min / 1000);
>> + t_ar = get_cyc_from_ns(clkrate, time->tAR_min / 1000);
>> + t_rr = get_cyc_from_ns(clkrate, time->tRR_min / 1000);
>
> I tested this patch set in conjunction with your PL353 SMC patch set.
>
> Our first stage bootloader sets the SMC memclk rate to 166.6 MHz, which leads
> this code to calculate a t_rc and t_wc of 17 cycles for ONFI mode 0. As I
> mentioned in my response to your SMC patch, this overflows the 4-bit-wide
> register fields in the SMC that hold these values.
The better way is fixing the frequency to correct value to avoid the
overflow conditions.
Even as per ONFI spec, the maximum cycle time for SDR mode is 20 ns and DDR mode
is 10 ns. As you pointed i will update the smc driver with required
boundary checks for the lower
and upper limits.
>
> Could we somehow set it up so the NAND and SMC drivers work together to adjust
> the memclk rate, if necessary, to achieve the desired timings? Or is there a
> better way to handle this?
Let me check on this. I didn't see the option to control the clock
rate at module level, otherwise
probably we can have DT entry and configure the required frequency
during the probe time.
Regards,
Punnaiah
>
>> +
>> + pl353_smc_set_cycles(dev, t_rc, t_wc, t_rea, t_wp, t_clr, t_ar, t_rr);
>> +
>> + return 0;
>> +}
>
> Thanks,
> Ben
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