On Thu, 17 Jul 2014, Ley Foon Tan wrote:
> On Tue, Jul 15, 2014 at 5:51 PM, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
> > On Tue, 15 Jul 2014, Ley Foon Tan wrote:
> >> +#ifndef _ASM_NIOS2_IRQ_H
> >> +#define _ASM_NIOS2_IRQ_H
> >> +
> >> +#define NIOS2_CPU_NR_IRQS 32
> >> +/* Reserve 32 additional interrupts for GPIO IRQs */
> >> +#define NR_IRQS (NIOS2_CPU_NR_IRQS + 32)
> >
> > Please use sparse irqs. Hardcoded limits tend to work out really bad.
> Yes, will change this.
> >
> >> +#include <linux/init.h>
> >> +#include <linux/interrupt.h>
> >> +#include <linux/of.h>
> >> +
>
> >> +static void chip_unmask(struct irq_data *d)
> >> +{
> >> + u32 ien;
> >> + ien = RDCTL(CTL_IENABLE);
> >> + ien |= (1 << d->hwirq);
> >> + WRCTL(CTL_IENABLE, ien);
> >
> > So this is UP only, right?
> Yes, this is to enable one interrupt.
The question was, whether this is always a UniProcessor machine.
> > Also why don't you cache the register content so spare the extra read
> > from the hardware?
> Need to make sure nobody modify the register if we cache the register content.
> Will keep as it is.
Sigh.
If this is a uniprocessor only design, then nothing can modify the
cached values as all these functions are always called with interrupts
disabled.
If this should be SMP safe, then you'd need serialization of the
register access as well becasue the read/modify/write sequence is not
atomic.
Thanks,
tglx
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