On Thu, Apr 10, 2014 at 03:39:51PM +0800, Xiubo Li-B47053 wrote:
> > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
> > index db9f75e..7cd4af9 100644
> > --- a/sound/soc/fsl/fsl_sai.c
> > +++ b/sound/soc/fsl/fsl_sai.c
> > @@ -401,7 +401,23 @@ static int fsl_sai_startup(struct snd_pcm_substream
> > *substream,
> > struct snd_soc_dai *cpu_dai)
> > {
> > struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
> > - u32 reg;
> > + struct device *dev = &sai->pdev->dev;
> > + u32 reg, i;
> > + int ret;
> > +
> > + ret = clk_prepare_enable(sai->bus_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to enable bus clock\n");
> > + return ret;
> > + }
> > +
> > + for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
> > + ret = clk_prepare_enable(sai->mclk_clk[i]);
> > + if (ret) {
> > + dev_err(dev, "failed to enable mclk%d clock\n", i + 1);
> > + goto err;
> > + }
> > + }
> >
>
> Why prepare and enable all the mclks here ?
> And at last only one of 'bus', 'mclk1', 'mclk2' and 'mclk3' will be selected
> To generate the bit clock. How about just prepare and enable the selected
> one ?
That's a fair suggestion. I'll do the revise.
But in this way. We can provisionally drop the clock enabling part and add
them later after my clock dividing patch is ready.
Thank you,
Nicolin
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