Hello Jingoo Han,
On Wed, Mar 12, 2014 at 1:31 AM, Jingoo Han <jg1.han@xxxxxxxxxxx> wrote:
> On Thursday, March 06, 2014 3:06 PM, Tanmay Inamdar wrote:
>>
>> This patch adds the device tree nodes for APM X-Gene PCIe controller and
>> PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts
>> nodes are added.
>>
>> Signed-off-by: Tanmay Inamdar <tinamdar@xxxxxxx>
>> ---
>> arch/arm64/boot/dts/apm-mustang.dts | 8 ++
>> arch/arm64/boot/dts/apm-storm.dtsi | 155 +++++++++++++++++++++++++++++++++++
>> 2 files changed, 163 insertions(+)
>
> [.....]
>
>> --- a/arch/arm64/boot/dts/apm-storm.dtsi
>> +++ b/arch/arm64/boot/dts/apm-storm.dtsi
>
> [.....]
>
>> +
>> + pcie0: pcie@1f2b0000 {
>> + status = "disabled";
>> + device_type = "pci";
>> + compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
>> + #interrupt-cells = <1>;
>> + #size-cells = <2>;
>> + #address-cells = <3>;
>> + reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
>> + 0xe0 0xd0000000 0x0 0x00200000>; /* PCI config space */
>> + reg-names = "csr", "cfg";
>> + ranges = <0x01000000 0x00 0x00000000 0xe0 0x00000000 0x00 0x00010000 /* io */
>> + 0x02000000 0x00 0x10000000 0xe0 0x10000000 0x00 0x80000000>; /* mem */
> ^^^
>
> I have a question about the fourth number '0xe0' of 'ranges' property.
> Would you let me know what the '0xe0' means?
>
In X-Gene address map, the physical address range starting from
0xe0_00000000 is reserved for PCIe Port 0 outbound memory mappings.
> Best regards,
> Jingoo Han
>
>> + dma-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000>;
>> + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
>> + interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
>> + 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
>> + 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
>> + 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
>> + clocks = <&pcie0clk 0>;
>> + };
>
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