Add device tree binding for ImgTec Consumer Infrared block, specifically
major revision 1 of the hardware.
Signed-off-by: James Hogan <james.hogan@xxxxxxxxxx>
Cc: Mauro Carvalho Chehab <m.chehab@xxxxxxxxxxx>
Cc: linux-media@xxxxxxxxxxxxxxx
Cc: Rob Herring <robh+dt@xxxxxxxxxx>
Cc: Pawel Moll <pawel.moll@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Cc: Ian Campbell <ijc+devicetree@xxxxxxxxxxxxxx>
Cc: Kumar Gala <galak@xxxxxxxxxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Rob Landley <rob@xxxxxxxxxxx>
Cc: linux-doc@xxxxxxxxxxxxxxx
Cc: Tomasz Figa <tomasz.figa@xxxxxxxxx>
---
v2:
- Future proof compatible string from "img,ir" to "img,ir1", where the 1
corresponds to the major revision number of the hardware (Tomasz
Figa).
- Added clock-names property and three specific clock names described in
the manual, only one of which is used by the current driver (Tomasz
Figa).
---
.../devicetree/bindings/media/img-ir1.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/img-ir1.txt
diff --git a/Documentation/devicetree/bindings/media/img-ir1.txt b/Documentation/devicetree/bindings/media/img-ir1.txt
new file mode 100644
index 0000000..ace5fd9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/img-ir1.txt
@@ -0,0 +1,30 @@
+* ImgTec Infrared (IR) decoder version 1
+
+This binding is for Imagination Technologies' Infrared decoder block,
+specifically major revision 1.
+
+Required properties:
+- compatible: Should be "img,ir1"
+- reg: Physical base address of the controller and length of
+ memory mapped region.
+- interrupts: The interrupt specifier to the cpu.
+
+Optional properties:
+- clocks: List of clock specifiers as described in standard
+ clock bindings.
+- clock-names: List of clock names corresponding to the clocks
+ specified in the clocks property.
+ Accepted clock names are:
+ "core": Core clock (defaults to 32.768KHz if omitted).
+ "sys": System side (fast) clock.
+ "mod": Power modulation clock.
+
+Example:
+
+ ir@02006200 {
+ compatible = "img,ir1";
+ reg = <0x02006200 0x100>;
+ interrupts = <29 4>;
+ clocks = <&clk_32khz>;
+ clock-names = "core";
+ };
--
1.8.3.2
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