Hi Inochi, On 11/03/2025 13:34, Inochi Amaoto wrote:
On Thu, Feb 13, 2025 at 08:38:44AM +0800, Inochi Amaoto wrote:Add description for the BFloat16 precision Floating-Point ISA extension, (Zfbfmin, Zvfbfmin, Zvfbfwma). which was ratified in commit 4dc23d62 ("Added Chapter title to BF16") of the riscv-isa-manual. Changed from v3: 1. rebase for v6.14-rc1 2. patch2: add validate for zfbfmin, zvfbfmin, zvfbfwma 3. patch2: apply Clément's tag Changed from v2: 1. rebase for v6.13-rc1 Changed from v1: 1. patch3: add missing code in sys_hwprobe.c Inochi Amaoto (3): dt-bindings: riscv: add bfloat16 ISA extension description riscv: add ISA extension parsing for bfloat16 ISA extension riscv: hwprobe: export bfloat16 ISA extension Documentation/arch/riscv/hwprobe.rst | 12 +++++ .../devicetree/bindings/riscv/extensions.yaml | 45 +++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 3 ++ arch/riscv/include/uapi/asm/hwprobe.h | 3 ++ arch/riscv/kernel/cpufeature.c | 35 +++++++++++++++ arch/riscv/kernel/sys_hwprobe.c | 3 ++ 6 files changed, 101 insertions(+) -- 2.48.1I wonder whether this patch could get merged? So I can submit the SG2044 board dts without this as dependency.
It is on my list for for-next so it *should* be merged in 6.15. Thanks, Alex
Regards, Inochi _______________________________________________ linux-riscv mailing list linux-riscv@xxxxxxxxxxxxxxxxxxx http://lists.infradead.org/mailman/listinfo/linux-riscv
