Hi, Tianyang, On Mon, Mar 3, 2025 at 6:15 PM Tianyang Zhang <zhangtianyang@xxxxxxxxxxx> wrote: > > Introduce the Redirect interrupt controllers.When the redirected interrupt > controller is enabled, the routing target of MSI interrupts is no longer a > specific CPU and vector number, but a specific redirected entry. The actual > CPU and vector number used are described by the redirected entry. You call it "redirect interrupt controller", then don't call "redirected interrupt controller" in other place. > > Signed-off-by: Tianyang Zhang <zhangtianyang@xxxxxxxxxxx> > --- > .../arch/loongarch/irq-chip-model.rst | 38 +++++++++++++++++++ > .../zh_CN/arch/loongarch/irq-chip-model.rst | 37 ++++++++++++++++++ > 2 files changed, 75 insertions(+) > > diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst > index a7ecce11e445..45cba22ff181 100644 > --- a/Documentation/arch/loongarch/irq-chip-model.rst > +++ b/Documentation/arch/loongarch/irq-chip-model.rst > @@ -181,6 +181,44 @@ go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:: > | Devices | > +---------+ > > +Advanced Extended-Redirect IRQ model Call it as "Advanced Extended IRQ model (with redirection)" and "高级扩展IRQ模型 (带重定向)" Huacai > +=============== > + > +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go > +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go > +to REDIRECT for remapping it to AVEC, and then go to CPUINTC directly, while all > +other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then > +go to CPUINTC directly:: > + > + +-----+ +-----------------------+ +-------+ > + | IPI | --> | CPUINTC | <-- | Timer | > + +-----+ +-----------------------+ +-------+ > + ^ ^ ^ > + | | | > + +---------+ +----------+ +---------+ +-------+ > + | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | > + +---------+ +----------+ +---------+ +-------+ > + ^ ^ > + | | > + | +----------+ > + | | REDIRECT | > + | +----------+ > + | ^ > + | | > + +---------+ +---------+ > + | PCH-PIC | | PCH-MSI | > + +---------+ +---------+ > + ^ ^ ^ > + | | | > + +---------+ +---------+ +---------+ > + | Devices | | PCH-LPC | | Devices | > + +---------+ +---------+ +---------+ > + ^ > + | > + +---------+ > + | Devices | > + +---------+ > + > ACPI-related definitions > ======================== > > diff --git a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst > index d4ff80de47b6..d935da47ce3b 100644 > --- a/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst > +++ b/Documentation/translations/zh_CN/arch/loongarch/irq-chip-model.rst > @@ -174,6 +174,43 @@ CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断发送到AVECINTC， > | Devices | > +---------+ > > +高级扩展-重定向IRQ模型 > +=============== > + > +在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC， > +CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断首先发送到REDIRECT模块,完成重定向后发 > +送到AVECINTC，而后通过AVECINTC直接送达CPUINTC，而其他所有设备的中断则分别发送到所连 > +接的PCH-PIC/PCH-LPC，然后由EIOINTC统一收集，再直接到达CPUINTC:: > + > + +-----+ +-----------------------+ +-------+ > + | IPI | --> | CPUINTC | <-- | Timer | > + +-----+ +-----------------------+ +-------+ > + ^ ^ ^ > + | | | > + +---------+ +----------+ +---------+ +-------+ > + | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | > + +---------+ +----------+ +---------+ +-------+ > + ^ ^ > + | | > + | +----------+ > + | | REDIRECT | > + | +----------+ > + | ^ > + | | > + +---------+ +---------+ > + | PCH-PIC | | PCH-MSI | > + +---------+ +---------+ > + ^ ^ ^ > + | | | > + +---------+ +---------+ +---------+ > + | Devices | | PCH-LPC | | Devices | > + +---------+ +---------+ +---------+ > + ^ > + | > + +---------+ > + | Devices | > + +---------+ > + > ACPI相关的定义 > ============== > > -- > 2.43.0 > >
