On Mon, Jan 13, 2025 at 07:29:39PM +0800, yunhui cui wrote:
> Hi drew,
>
> On Mon, Jan 13, 2025 at 5:07 PM Andrew Jones <ajones@xxxxxxxxxxxxxxxx> wrote:
> >
> > On Mon, Jan 13, 2025 at 04:36:34PM +0800, Yunhui Cui wrote:
> > > Expose Zicbom through hwprobe and also provide a key to extract its
> > > respective block size.
> > >
> > > Signed-off-by: Yunhui Cui <cuiyunhui@xxxxxxxxxxxxx>
> > > ---
> > > Documentation/arch/riscv/hwprobe.rst | 6 ++++++
> > > arch/riscv/include/asm/hwprobe.h | 2 +-
> > > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> > > arch/riscv/kernel/sys_hwprobe.c | 6 ++++++
> > > 4 files changed, 15 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> > > index 955fbcd19ce9..7a47cbdbcf8e 100644
> > > --- a/Documentation/arch/riscv/hwprobe.rst
> > > +++ b/Documentation/arch/riscv/hwprobe.rst
> > > @@ -94,6 +94,9 @@ The following keys are defined:
> > > * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
> > > ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
> > >
> > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
> > > + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
> > > +
> >
> > This should come after RISCV_HWPROBE_EXT_SUPM since this document has the
> > defines sorted in the order in which they are introduced (although I
> > personally wouldn't mind if we ordered them alphabetically instead)
> OK
>
> >
> > > * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
> > > in version 1.0 of the Bit-Manipulation ISA extensions.
> > >
> > > @@ -273,6 +276,9 @@ The following keys are defined:
> > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
> > > represents the size of the Zicboz block in bytes.
> > >
> > > +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
> > > + represents the size of the Zicbom block in bytes.
> > > +
> >
> > Should be moved below RISCV_HWPROBE_KEY_TIME_CSR_FREQ
>
> Why should it be moved below RISCV_HWPROBE_KEY_TIME_CSR_FREQ?
Oh, right. It should be below RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF for
the same reason as above (order of introduction).
Thanks,
drew
