[RFCv2 endianess 0/4] Add Freescale FTM PWM driver.

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I'm sending the RFCv2 patch series about the FTM IP block registers
read and write endian issue, and there is no buffers or descriptors
involved.

For the FTM IP block, in Vybird VF610 Tower the LE mode is in use,
in LS-1 the BE mode is in use. And the CPU always operates in LE mode.

So now I must take care of all these two cases. In this patch series I
have implemented two functions fsl_pwm_readl() and fsl_pwm_writel() to
replace readl() and writel(). At the same time there should add one
"big-endian" property for dt node.

And this patch is based the V6 series.


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