Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@xxxxxxxxxxxx>:
On Tue, 20 Aug 2024 11:24:18 -0400 you wrote:
> Adds support for detecting and reporting the speed of unaligned vector
> accesses on RISC-V CPUs. Adds vec_misaligned_speed key to the hwprobe
> adds Zicclsm to cpufeature and fixes the check for scalar unaligned
> emulated all CPUs. The vec_misaligned_speed key keeps the same format
> as the scalar unaligned access speed key.
>
> This set does not emulate unaligned vector accesses on CPUs that do not
> support them. Only reports if userspace can run them and speed of
> unaligned vector accesses if supported.
>
> [...]
Here is the summary with links:
- [v9,1/6] RISC-V: Check scalar unaligned access on all CPUs
https://git.kernel.org/riscv/c/8d20a739f17a
- [v9,2/6] RISC-V: Scalar unaligned access emulated on hotplug CPUs
https://git.kernel.org/riscv/c/9c528b5f7927
- [v9,3/6] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
https://git.kernel.org/riscv/c/c05a62c92516
- [v9,4/6] RISC-V: Detect unaligned vector accesses supported
(no matching commit)
- [v9,5/6] RISC-V: Report vector unaligned access speed hwprobe
https://git.kernel.org/riscv/c/e7c9d66e313b
- [v9,6/6] RISC-V: hwprobe: Document unaligned vector perf key
https://git.kernel.org/riscv/c/40e09ebd791f
You are awesome, thank you!
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