Hi Babu, On 10/9/24 10:39 AM, Babu Moger wrote: > Add the functionality to enable/disable AMD ABMC feature. > > AMD ABMC feature is enabled by setting enabled bit(0) in MSR > L3_QOS_EXT_CFG. When the state of ABMC is changed, the MSR needs > to be updated on all the logical processors in the QOS Domain. > > Hardware counters will reset when ABMC state is changed. > > The ABMC feature details are documented in APM listed below [1]. > [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming > Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth > Monitoring (ABMC). > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Signed-off-by: Babu Moger <babu.moger@xxxxxxx> > --- With the MSRs ordered numerically per Tony's suggestion: |Reviewed-by: Reinette Chatre <reinette.chatre@xxxxxxxxx> Reinette
