Add missing bitfields to CONTEXT_SWITCH_CNTL in a6xx.xml. Tested-by: Rob Clark <robdclark@xxxxxxxxx> Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8650-QRD Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8550-QRD Tested-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> # on SM8450-HDK Signed-off-by: Antonino Maniscalco <antomani103@xxxxxxxxx> --- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 2dfe6913ab4f52449b76c2f75b2d101c08115d16..fd31d1d7a11eef7f38dcc2975dc1034f6b7a2e41 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1337,7 +1337,12 @@ to upconvert to 32b float internally? <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> </array> - <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/> + <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"> + <bitfield name="STOP" pos="0" type="boolean"/> + <bitfield name="LEVEL" low="6" high="7"/> + <bitfield name="USES_GMEM" pos="8" type="boolean"/> + <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> + </reg32> <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> -- 2.46.1
