Charlie Jenkins <charlie@xxxxxxxxxxxx> 於 2024年9月12日 週四 下午1:57寫道： > > Add a property analogous to the vlenb CSR so that software can detect > the vector length of each CPU prior to it being brought online. > Currently software has to assume that the vector length read from the > boot CPU applies to all possible CPUs. On T-Head CPUs implementing > pre-ratification vector, reading the th.vlenb CSR may produce an illegal > instruction trap, so this property is required on such systems. > > Signed-off-by: Charlie Jenkins <charlie@xxxxxxxxxxxx> > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Reviewed-by: Andy Chiu <andybnac@xxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 8edc8261241a..c0cf6cf56749 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -26,6 +26,18 @@ description: | > allOf: > - $ref: /schemas/cpu.yaml# > - $ref: extensions.yaml > + - if: > + not: > + properties: > + compatible: > + contains: > + enum: > + - thead,c906 > + - thead,c910 > + - thead,c920 > + then: > + properties: > + thead,vlenb: false > > properties: > compatible: > @@ -95,6 +107,13 @@ properties: > description: > The blocksize in bytes for the Zicboz cache operations. > > + thead,vlenb: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + VLEN/8, the vector register length in bytes. This property is required on > + thead systems where the vector register length is not identical on all harts, or > + the vlenb CSR is not available. > + > # RISC-V has multiple properties for cache op block sizes as the sizes > # differ between individual CBO extensions > cache-op-block-size: false > > -- > 2.45.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@xxxxxxxxxxxxxxxxxxx > http://lists.infradead.org/mailman/listinfo/linux-riscv
