Hi Babu, On 9/4/24 3:21 PM, Babu Moger wrote: > Add the functionality to enable/disable AMD ABMC feature. > > AMD ABMC feature is enabled by setting enabled bit(0) in MSR > L3_QOS_EXT_CFG. When the state of ABMC is changed, the MSR needs > to be updated on all the logical processors in the QOS Domain. > > Hardware counters will reset when ABMC state is changed. Reset the > architectural state maintained by resctrl so that reading of a hardware > counter is not considered as an overflow in next update. Above mentions that architectural state is also reset, but that does not seem to form part of this patch? > > The ABMC feature details are documented in APM listed below [1]. > [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming > Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth > Monitoring (ABMC). > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > Signed-off-by: Babu Moger <babu.moger@xxxxxxx> > --- ... > static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) > diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c > index 7e76f8d839fc..0178555bf3f6 100644 > --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c > +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c > @@ -2402,6 +2402,41 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable) > return 0; > } > > +/* > + * Update L3_QOS_EXT_CFG MSR on all the CPUs associated with the resource. This comment is not accurate since the function below only sets MSR on current CPU. > + */ > +static void resctrl_abmc_set_one_amd(void *arg) Reinette
