On Wed, Sep 04, 2024 at 02:59:46PM +0200, Joerg Roedel wrote: > From: Joerg Roedel <jroedel@xxxxxxx> > > Add the 'pgsize_4k' as a valid value to the amd_iommu= command line > parameter to limit the page-sizes used for V1 page-tables for 4 KiB. > This is needed to make some devices working when attached to an AMD > SEV-SNP virtual machine. Details? > Signed-off-by: Joerg Roedel <jroedel@xxxxxxx> > --- > Documentation/admin-guide/kernel-parameters.txt | 2 ++ > drivers/iommu/amd/amd_iommu.h | 1 + > drivers/iommu/amd/amd_iommu_types.h | 4 ++++ > drivers/iommu/amd/init.c | 5 +++++ > drivers/iommu/amd/io_pgtable.c | 2 +- > 5 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 09126bb8cc9f..3187976ae052 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -339,6 +339,8 @@ > pgtbl_v1 - Use v1 page table for DMA-API (Default). > pgtbl_v2 - Use v2 page table for DMA-API. > irtcachedis - Disable Interrupt Remapping Table (IRT) caching. > + pgsize_4k - Limit the available page-sizes for v1 page-tables > + to 4 KiB. Why is this a kernel command line? Surely it should be negotiated automaticaly with capability registers or ACPI like everone else does if there is something functionally wrong with the vIOMMU?? If we are doing this we also have a problem on mlx5 devices where there are too many page sizes in the v1 table and it blows up the ATS caching. It would be nice to widen this option to limit the page sizes to other combinations (4k/2M/1G or something). Jason
