Re: [PATCH v11 20/39] arm64/gcs: Context switch GCS state for EL0

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Thu, Aug 22, 2024 at 02:15:23AM +0100, Mark Brown wrote:
> There are two registers controlling the GCS state of EL0, GCSPR_EL0 which
> is the current GCS pointer and GCSCRE0_EL1 which has enable bits for the
> specific GCS functionality enabled for EL0. Manage these on context switch
> and process lifetime events, GCS is reset on exec().  Also ensure that
> any changes to the GCS memory are visible to other PEs and that changes
> from other PEs are visible on this one by issuing a GCSB DSYNC when
> moving to or from a thread with GCS.
> 
> Since the current GCS configuration of a thread will be visible to
> userspace we store the configuration in the format used with userspace
> and provide a helper which configures the system register as needed.
> 
> On systems that support GCS we always allow access to GCSPR_EL0, this
> facilitates reporting of GCS faults if userspace implements disabling of
> GCS on error - the GCS can still be discovered and examined even if GCS
> has been disabled.
> 
> Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>

We could do with a bit more code comments around GCSB DSYNC but
otherwise it looks fine now.

Reviewed-by: Catalin Marinas <catalin.marinas@xxxxxxx>




[Index of Archives]     [Kernel Newbies]     [Security]     [Netfilter]     [Bugtraq]     [Linux FS]     [Yosemite Forum]     [MIPS Linux]     [ARM Linux]     [Linux Security]     [Linux RAID]     [Samba]     [Video 4 Linux]     [Device Mapper]     [Linux Resources]

  Powered by Linux