Hi Babu,
On 8/19/24 11:07 AM, Moger, Babu wrote:
Hi Reinette,
On 8/16/24 16:31, Reinette Chatre wrote:
Hi Babu,
On 8/6/24 3:00 PM, Babu Moger wrote:
Add the functionality to enable/disable AMD ABMC feature.
AMD ABMC feature is enabled by setting enabled bit(0) in MSR
L3_QOS_EXT_CFG. When the state of ABMC is changed, the MSR needs
to be updated on all the logical processors in the QOS Domain.
Hardware counters will reset when ABMC state is changed. Reset the
Could you please clarify how this works when ABMC state is changed on
one CPU in a domain vs all (as done in this patch) CPUs of a domain? In this
patch it is clear that all hardware counters are reset and consequently
the architectural state maintained by resctrl is reset also. Later, when
the code is added to handle CPU online I see that ABMC state is changed
on a new online CPU but I do not see matching reset of architectural state.
(more in that patch later)
Yes. I missed testing this scenario.
When new cpu comes online, it should inherit the abmc state which is set
already. it should not force it either way. In that case, it is not
required to reset the architectural state.
I need to make few changes to make it work properly.
We need to set abmc state to "enabled" during the init when abmc is
detected. resctrl_late_init -> .. -> rdt_get_mon_l3_config
This only happens once during the init.
Then during the hotplug, just update the abmc state which is already set
duing the init. This should work fine.
The discussion about this flow is now split between this thread and the
discussion of patch #20. I tried to merge the discussions in my response [1]
to patch #20.
Reinette
[1] https://lore.kernel.org/lkml/6b1ad4b2-d99f-44fb-afcc-b9f48e51df6e@xxxxxxxxx/
