This series of patches introduces support for advanced extended
interrupt controllers (AVECINTC), and this hardware feature will
be supported on 3C6000 for the first time
Changes log:
V0->V1:
1.Modified some formats and declarations
2.Removed kmalloc/kfree when adding affinity related data to pending_list,
and used moving tag to replace the original behavior
3.Adjusted the process that enables AVEC interrupts, now it is at the end of all processes
4.Removed CPUHP related callbacks, now irq_matrix_online/irq_matrix_offline is completed in start_secondary/loongson_cpu_disable
5.Adjusted compatibility issues for CONFIG_ACPI
6.About question:
> irr = csr_read64(LOONGARCH_CSR_IRR0 + vector / 64);
> should be good enough, no?
csr_read64 was built-in as __csrrd_d, it doesn't seem to support variables as parameters
>>>>
drivers/irqchip/irq-loongarch-avec.c: In function ‘complete_irq_moving’:
./arch/loongarch/include/asm/loongarch.h:164:25: error: invalid argument to built-in function
164 | #define csr_read64(reg) __csrrd_d(reg)
| ^~~~~~~~~
drivers/irqchip/irq-loongarch-avec.c:170:23: note: in expansion of macro ‘csr_read64’
170 | irr = csr_read64(LOONGARCH_CSR_IRR_BASE + vector / VECTORS_PER_REG);
| ^~~~~~~~~~
>>>>
So we have temporarily retained the previous implementation.
V1->V2:
Fixed up coding style. Made on/offline functions void
Added compatibility when CONFIG_SMP is turned off
V2->V3:
Squash two patches into one
V3->V4:
Update NR_IRQS
Update Register's name
Fixed up coding style
V4->V5:
Retain feature CPUCFG1_MSGINT
Fixed up coding style
Delete the test code introduced by V4, and now msi msg address still uses the 32-bit address
V5->V6:
Fix definition of NR_IRQS
Define arch_probe_nr_irqs()
Handle all avecintc interrupts in one dispatch
Use cpuhotplug callbacks instead of direct call to avec_online_cpu()/avec_offline_cpu()
Rename {SMP,ACTION}_CLEAR_VECT to {SMP,ACTION}_CLEAR_VECTOR
Use avecintc_ prefix instead of loongarch_avec_ to keep consistancy
V6->V7:
Fixed compatibility issue with cpuhp_setup_state_nocalls when CONFIG_SMP is turned off
Rename avecintc_online/offline_cpu as avecintc_cpu_online/offline
Use pch_msi_handle[0] as default value of get_pch_msi_handle
Rework commit-message
V7->V8:
Fixed up coding style
Support per-device-MSI domain
Replaced spin_lock ops with guard/scope_guard
Always execute irq_metrix_offline while the CPU is offline
V8->V9:
Fixed up coding style and potential bugs
V9->V10:
Add a cover of series patch
Huacai Chen (1):
irqchip/loongson-pch-msi: Switch to MSI parent domains
Tianyang Zhang (1):
irqchip/loongarch-avec: Add AVEC irqchip support
.../arch/loongarch/irq-chip-model.rst | 32 ++
.../zh_CN/arch/loongarch/irq-chip-model.rst | 32 ++
arch/loongarch/Kconfig | 1 +
arch/loongarch/include/asm/cpu-features.h | 1 +
arch/loongarch/include/asm/cpu.h | 2 +
arch/loongarch/include/asm/hardirq.h | 3 +-
arch/loongarch/include/asm/hw_irq.h | 2 +
arch/loongarch/include/asm/irq.h | 25 +-
arch/loongarch/include/asm/loongarch.h | 18 +-
arch/loongarch/include/asm/smp.h | 2 +
arch/loongarch/kernel/cpu-probe.c | 3 +-
arch/loongarch/kernel/irq.c | 15 +-
arch/loongarch/kernel/paravirt.c | 5 +
arch/loongarch/kernel/smp.c | 6 +
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/Makefile | 2 +-
drivers/irqchip/irq-loongarch-avec.c | 426 ++++++++++++++++++
drivers/irqchip/irq-loongarch-cpu.c | 5 +-
drivers/irqchip/irq-loongson-eiointc.c | 7 +-
drivers/irqchip/irq-loongson-pch-msi.c | 82 ++--
include/linux/cpuhotplug.h | 3 +-
21 files changed, 615 insertions(+), 58 deletions(-)
create mode 100644 drivers/irqchip/irq-loongarch-avec.c
--
2.20.1
