Re: [PATCH v6 5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED

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To: Jesse Taube <jesse@xxxxxxxxxxxx>
Subject: Re: [PATCH v6 5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
From: Evan Green <evan@xxxxxxxxxxxx>
Date: Thu, 25 Jul 2024 11:59:44 -0700
Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx, Jonathan Corbet <corbet@xxxxxxx>, Paul Walmsley <paul.walmsley@xxxxxxxxxx>, Palmer Dabbelt <palmer@xxxxxxxxxxx>, Albert Ou <aou@xxxxxxxxxxxxxxxxx>, Conor Dooley <conor@xxxxxxxxxx>, Rob Herring <robh@xxxxxxxxxx>, Krzysztof Kozlowski <krzk+dt@xxxxxxxxxx>, Clément Léger <cleger@xxxxxxxxxxxx>, Andrew Jones <ajones@xxxxxxxxxxxxxxxx>, Charlie Jenkins <charlie@xxxxxxxxxxxx>, Xiao Wang <xiao.w.wang@xxxxxxxxx>, Andy Chiu <andy.chiu@xxxxxxxxxx>, Eric Biggers <ebiggers@xxxxxxxxxx>, Greentime Hu <greentime.hu@xxxxxxxxxx>, Björn Töpel <bjorn@xxxxxxxxxxxx>, Heiko Stuebner <heiko@xxxxxxxxx>, Costa Shulyupin <costa.shul@xxxxxxxxxx>, Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>, Baoquan He <bhe@xxxxxxxxxx>, Anup Patel <apatel@xxxxxxxxxxxxxxxx>, Zong Li <zong.li@xxxxxxxxxx>, Sami Tolvanen <samitolvanen@xxxxxxxxxx>, Ben Dooks <ben.dooks@xxxxxxxxxxxxxxx>, Alexandre Ghiti <alexghiti@xxxxxxxxxxxx>, "Gustavo A. R. Silva" <gustavoars@xxxxxxxxxx>, Erick Archer <erick.archer@xxxxxxx>, Joel Granados <j.granados@xxxxxxxxxxx>, linux-doc@xxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, devicetree@xxxxxxxxxxxxxxx, Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
In-reply-to: <20240724183605.4038597-6-jesse@rivosinc.com>
References: <20240724183605.4038597-1-jesse@rivosinc.com> <20240724183605.4038597-6-jesse@rivosinc.com>

On Wed, Jul 24, 2024 at 11:36 AM Jesse Taube <jesse@xxxxxxxxxxxx> wrote:
>
> Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED to allow
> for the addition of RISCV_VECTOR_MISALIGNED in a later patch.
>
> Signed-off-by: Jesse Taube <jesse@xxxxxxxxxxxx>
> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
> Reviewed-by: Charlie Jenkins <charlie@xxxxxxxxxxxx>

Reviewed-by: Evan Green <evan@xxxxxxxxxxxx>

References:
- [PATCH v6 0/8] RISC-V: Detect and report speed of unaligned vector accesses
  - From: Jesse Taube
- [PATCH v6 5/8] RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
  - From: Jesse Taube

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