This implements [cmp]xchgXX() macros using Zacas and Zabha extensions and finally uses those newly introduced macros to add support for qspinlocks: note that this implementation of qspinlocks satisfies the forward progress guarantee. It also uses Ziccrse to provide the qspinlock implementation. Thanks to Guo and Leonardo for their work! v2: https://lore.kernel.org/linux-riscv/20240626130347.520750-1-alexghiti@xxxxxxxxxxxx/ v1: https://lore.kernel.org/linux-riscv/20240528151052.313031-1-alexghiti@xxxxxxxxxxxx/ Changes in v3: - Fix patch 4 to restrict the optimization to fully ordered AMO (Andrea) - Move RISCV_ISA_EXT_ZABHA definition to patch 4 (Andrea) - !Zacas at build time => no CAS from Zabha too (Andrea) - drop patch 7 "riscv: Improve amoswap.X use in xchg()" (Andrea) - Switch lr/sc and cas order (Guo) - Combo spinlocks do not depend on Zabha - Add a Kconfig for ticket/queued/combo (Guo) - Use Ziccrse (Guo) Changes in v2: - Add patch for Zabha dtbinding (Conor) - Fix cmpxchg128() build warnings missed in v1 - Make arch_cmpxchg128() fully ordered - Improve Kconfig help texts for both extensions (Conor) - Fix Makefile dependencies by requiring TOOLCHAIN_HAS_XXX (Nathan) - Fix compilation errors when the toolchain does not support the extensions (Nathan) - Fix C23 warnings about label at the end of coumpound statements (Nathan) - Fix Zabha and !Zacas configurations (Andrea) - Add COMBO spinlocks (Guo) - Improve amocas fully ordered operations by using .aqrl semantics and removing the fence rw, rw (Andrea) - Rebase on top "riscv: Fix fully ordered LR/SC xchg[8|16]() implementations" - Add ARCH_WEAK_RELEASE_ACQUIRE (Andrea) - Remove the extension version in march for LLVM since it is only required for experimental extensions (Nathan) - Fix cmpxchg128() implementation by adding both registers of a pair in the list of input/output operands Alexandre Ghiti (9): riscv: Implement cmpxchg32/64() using Zacas dt-bindings: riscv: Add Zabha ISA extension description riscv: Implement cmpxchg8/16() using Zabha riscv: Improve zacas fully-ordered cmpxchg() riscv: Implement arch_cmpxchg128() using Zacas riscv: Implement xchg8/16() using Zabha riscv: Add ISA extension parsing for Ziccrse dt-bindings: riscv: Add Ziccrse ISA extension description riscv: Add qspinlock support Guo Ren (2): asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock asm-generic: ticket-lock: Add separate ticket-lock.h .../devicetree/bindings/riscv/extensions.yaml | 12 ++ .../locking/queued-spinlocks/arch-support.txt | 2 +- arch/riscv/Kconfig | 64 +++++++ arch/riscv/Makefile | 6 + arch/riscv/include/asm/Kbuild | 4 +- arch/riscv/include/asm/cmpxchg.h | 173 +++++++++++++++--- arch/riscv/include/asm/hwcap.h | 2 + arch/riscv/include/asm/spinlock.h | 39 ++++ arch/riscv/kernel/cpufeature.c | 2 + arch/riscv/kernel/setup.c | 33 ++++ include/asm-generic/qspinlock.h | 2 + include/asm-generic/spinlock.h | 87 +-------- include/asm-generic/spinlock_types.h | 12 +- include/asm-generic/ticket_spinlock.h | 105 +++++++++++ 14 files changed, 424 insertions(+), 119 deletions(-) create mode 100644 arch/riscv/include/asm/spinlock.h create mode 100644 include/asm-generic/ticket_spinlock.h -- 2.39.2
